1 Allwinner A10 Display Pipeline
2 ==============================
4 The Allwinner A10 Display pipeline is composed of several components
5 that are going to be documented below:
7 For the input port of all components up to the TCON in the display
8 pipeline, if there are multiple components, the local endpoint IDs
9 must correspond to the index of the upstream block. For example, if
10 the remote endpoint is Frontend 1, then the local endpoint ID must
13 Conversely, for the output ports of the same group, the remote endpoint
14 ID must be the index of the local hardware block. If the local backend
15 is backend 1, then the remote endpoint ID must be 1.
20 The HDMI Encoder supports the HDMI video and audio outputs, and does
21 CEC. It is one end of the pipeline.
24 - compatible: value must be one of:
25 * allwinner,sun5i-a10s-hdmi
26 - reg: base address and size of memory-mapped region
27 - interrupts: interrupt associated to this IP
28 - clocks: phandles to the clocks feeding the HDMI encoder
29 * ahb: the HDMI interface clock
30 * mod: the HDMI module clock
31 * pll-0: the first video PLL
32 * pll-1: the second video PLL
33 - clock-names: the clock names mentioned above
34 - dmas: phandles to the DMA channels used by the HDMI encoder
35 * ddc-tx: The channel for DDC transmission
36 * ddc-rx: The channel for DDC reception
37 * audio-tx: The channel used for audio transmission
38 - dma-names: the channel names mentioned above
40 - ports: A ports node with endpoint definitions as defined in
41 Documentation/devicetree/bindings/media/video-interfaces.txt. The
42 first port should be the input endpoint. The second should be the
43 output, usually to an HDMI connector.
48 The TV Encoder supports the composite and VGA output. It is one end of
52 - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
53 - reg: base address and size of memory-mapped region
54 - clocks: the clocks driving the TV encoder
55 - resets: phandle to the reset controller driving the encoder
57 - ports: A ports node with endpoint definitions as defined in
58 Documentation/devicetree/bindings/media/video-interfaces.txt. The
59 first port should be the input endpoint.
64 The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
67 - compatible: value must be either:
68 * allwinner,sun5i-a13-tcon
69 * allwinner,sun6i-a31-tcon
70 * allwinner,sun6i-a31s-tcon
71 * allwinner,sun8i-a33-tcon
72 * allwinner,sun8i-v3s-tcon
73 - reg: base address and size of memory-mapped region
74 - interrupts: interrupt associated to this IP
75 - clocks: phandles to the clocks feeding the TCON. Three are needed:
76 - 'ahb': the interface clocks
77 - 'tcon-ch0': The clock driving the TCON channel 0
78 - resets: phandles to the reset controllers driving the encoder
79 - "lcd": the reset line for the TCON channel 0
81 - clock-names: the clock names mentioned above
82 - reset-names: the reset names mentioned above
83 - clock-output-names: Name of the pixel clock created
85 - ports: A ports node with endpoint definitions as defined in
86 Documentation/devicetree/bindings/media/video-interfaces.txt. The
87 first port should be the input endpoint, the second one the output
89 The output may have multiple endpoints. The TCON has two channels,
90 usually with the first channel being used for the panels interfaces
91 (RGB, LVDS, etc.), and the second being used for the outputs that
92 require another controller (TV Encoder, HDMI, etc.). The endpoints
93 will take an extra property, allwinner,tcon-channel, to specify the
94 channel the endpoint is associated to. If that property is not
95 present, the endpoint number will be used as the channel number.
97 On SoCs other than the A33 and V3s, there is one more clock required:
98 - 'tcon-ch1': The clock driving the TCON channel 1
103 The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
104 (A31, A23, A33), allows to dynamically adjust pixel
105 brightness/contrast based on histogram measurements for LCD content
106 adaptive backlight control.
110 - compatible: value must be one of:
111 * allwinner,sun6i-a31-drc
112 * allwinner,sun6i-a31s-drc
113 * allwinner,sun8i-a33-drc
114 - reg: base address and size of the memory-mapped region.
115 - interrupts: interrupt associated to this IP
116 - clocks: phandles to the clocks feeding the DRC
117 * ahb: the DRC interface clock
118 * mod: the DRC module clock
119 * ram: the DRC DRAM clock
120 - clock-names: the clock names mentioned above
121 - resets: phandles to the reset line driving the DRC
123 - ports: A ports node with endpoint definitions as defined in
124 Documentation/devicetree/bindings/media/video-interfaces.txt. The
125 first port should be the input endpoints, the second one the outputs
127 Display Engine Backend
128 ----------------------
130 The display engine backend exposes layers and sprites to the
134 - compatible: value must be one of:
135 * allwinner,sun5i-a13-display-backend
136 * allwinner,sun6i-a31-display-backend
137 * allwinner,sun8i-a33-display-backend
138 - reg: base address and size of the memory-mapped region.
139 - interrupts: interrupt associated to this IP
140 - clocks: phandles to the clocks feeding the frontend and backend
141 * ahb: the backend interface clock
142 * mod: the backend module clock
143 * ram: the backend DRAM clock
144 - clock-names: the clock names mentioned above
145 - resets: phandles to the reset controllers driving the backend
147 - ports: A ports node with endpoint definitions as defined in
148 Documentation/devicetree/bindings/media/video-interfaces.txt. The
149 first port should be the input endpoints, the second one the output
151 On the A33, some additional properties are required:
152 - reg needs to have an additional region corresponding to the SAT
153 - reg-names need to be set, with "be" and "sat"
154 - clocks and clock-names need to have a phandle to the SAT bus
155 clocks, whose name will be "sat"
156 - resets and reset-names need to have a phandle to the SAT bus
157 resets, whose name will be "sat"
159 Display Engine Frontend
160 -----------------------
162 The display engine frontend does formats conversion, scaling,
163 deinterlacing and color space conversion.
166 - compatible: value must be one of:
167 * allwinner,sun5i-a13-display-frontend
168 * allwinner,sun6i-a31-display-frontend
169 * allwinner,sun8i-a33-display-frontend
170 - reg: base address and size of the memory-mapped region.
171 - interrupts: interrupt associated to this IP
172 - clocks: phandles to the clocks feeding the frontend and backend
173 * ahb: the backend interface clock
174 * mod: the backend module clock
175 * ram: the backend DRAM clock
176 - clock-names: the clock names mentioned above
177 - resets: phandles to the reset controllers driving the backend
179 - ports: A ports node with endpoint definitions as defined in
180 Documentation/devicetree/bindings/media/video-interfaces.txt. The
181 first port should be the input endpoints, the second one the outputs
183 Display Engine 2.0 Mixer
184 ------------------------
186 The DE2 mixer have many functionalities, currently only layer blending is
190 - compatible: value must be one of:
191 * allwinner,sun8i-v3s-de2-mixer
192 - reg: base address and size of the memory-mapped region.
193 - clocks: phandles to the clocks feeding the mixer
194 * bus: the mixer interface clock
195 * mod: the mixer module clock
196 - clock-names: the clock names mentioned above
197 - resets: phandles to the reset controllers driving the mixer
199 - ports: A ports node with endpoint definitions as defined in
200 Documentation/devicetree/bindings/media/video-interfaces.txt. The
201 first port should be the input endpoints, the second one the output
204 Display Engine Pipeline
205 -----------------------
207 The display engine pipeline (and its entry point, since it can be
208 either directly the backend or the frontend) is represented as an
212 - compatible: value must be one of:
213 * allwinner,sun5i-a10s-display-engine
214 * allwinner,sun5i-a13-display-engine
215 * allwinner,sun6i-a31-display-engine
216 * allwinner,sun6i-a31s-display-engine
217 * allwinner,sun8i-a33-display-engine
218 * allwinner,sun8i-v3s-display-engine
220 - allwinner,pipelines: list of phandle to the display engine
221 frontends (DE 1.0) or mixers (DE 2.0) available.
226 compatible = "olimex,lcd-olinuxino-43-ts";
227 #address-cells = <1>;
231 #address-cells = <1>;
234 panel_input: endpoint {
235 remote-endpoint = <&tcon0_out_panel>;
241 compatible = "hdmi-connector";
245 hdmi_con_in: endpoint {
246 remote-endpoint = <&hdmi_out_con>;
251 hdmi: hdmi@01c16000 {
252 compatible = "allwinner,sun5i-a10s-hdmi";
253 reg = <0x01c16000 0x1000>;
255 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
256 <&ccu CLK_PLL_VIDEO0_2X>,
257 <&ccu CLK_PLL_VIDEO1_2X>;
258 clock-names = "ahb", "mod", "pll-0", "pll-1";
259 dmas = <&dma SUN4I_DMA_NORMAL 16>,
260 <&dma SUN4I_DMA_NORMAL 16>,
261 <&dma SUN4I_DMA_DEDICATED 24>;
262 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
266 #address-cells = <1>;
270 #address-cells = <1>;
274 hdmi_in_tcon0: endpoint {
275 remote-endpoint = <&tcon0_out_hdmi>;
280 #address-cells = <1>;
284 hdmi_out_con: endpoint {
285 remote-endpoint = <&hdmi_con_in>;
291 tve0: tv-encoder@01c0a000 {
292 compatible = "allwinner,sun4i-a10-tv-encoder";
293 reg = <0x01c0a000 0x1000>;
294 clocks = <&ahb_gates 34>;
295 resets = <&tcon_ch0_clk 0>;
298 #address-cells = <1>;
301 tve0_in_tcon0: endpoint@0 {
303 remote-endpoint = <&tcon0_out_tve0>;
308 tcon0: lcd-controller@1c0c000 {
309 compatible = "allwinner,sun5i-a13-tcon";
310 reg = <0x01c0c000 0x1000>;
312 resets = <&tcon_ch0_clk 1>;
314 clocks = <&ahb_gates 36>,
320 clock-output-names = "tcon-pixel-clock";
323 #address-cells = <1>;
327 #address-cells = <1>;
331 tcon0_in_be0: endpoint@0 {
333 remote-endpoint = <&be0_out_tcon0>;
338 #address-cells = <1>;
342 tcon0_out_panel: endpoint@0 {
344 remote-endpoint = <&panel_input>;
347 tcon0_out_tve0: endpoint@1 {
349 remote-endpoint = <&tve0_in_tcon0>;
355 fe0: display-frontend@1e00000 {
356 compatible = "allwinner,sun5i-a13-display-frontend";
357 reg = <0x01e00000 0x20000>;
359 clocks = <&ahb_gates 46>, <&de_fe_clk>,
361 clock-names = "ahb", "mod",
363 resets = <&de_fe_clk>;
366 #address-cells = <1>;
370 #address-cells = <1>;
374 fe0_out_be0: endpoint {
375 remote-endpoint = <&be0_in_fe0>;
381 be0: display-backend@1e60000 {
382 compatible = "allwinner,sun5i-a13-display-backend";
383 reg = <0x01e60000 0x10000>;
385 clocks = <&ahb_gates 44>, <&de_be_clk>,
387 clock-names = "ahb", "mod",
389 resets = <&de_be_clk>;
392 #address-cells = <1>;
396 #address-cells = <1>;
400 be0_in_fe0: endpoint@0 {
402 remote-endpoint = <&fe0_out_be0>;
407 #address-cells = <1>;
411 be0_out_tcon0: endpoint@0 {
413 remote-endpoint = <&tcon0_in_be0>;
420 compatible = "allwinner,sun5i-a13-display-engine";
421 allwinner,pipelines = <&fe0>;