Bindings/memory-controllers/nvidia,tegra30-emc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: NVIDIA Tegra30 SoC External Memory Controller
   8
   9 maintainers:
  10   - Dmitry Osipenko <digetx@gmail.com>
  11   - Jon Hunter <jonathanh@nvidia.com>
  12   - Thierry Reding <thierry.reding@gmail.com>
  13
  14 description: |
  15   The EMC interfaces with the off-chip SDRAM to service the request stream
  16   sent from Memory Controller. The EMC also has various performance-affecting
  17   settings beyond the obvious SDRAM configuration parameters and initialization
  18   settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
  19   LPDDR3, and DDR3.
  20
  21 properties:
  22   compatible:
  23     const: nvidia,tegra30-emc
  24
  25   reg:
  26     maxItems: 1
  27
  28   clocks:
  29     maxItems: 1
  30
  31   interrupts:
  32     maxItems: 1
  33
  34   nvidia,memory-controller:
  35     $ref: /schemas/types.yaml#/definitions/phandle
  36     description:
  37       Phandle of the Memory Controller node.
  38
  39 patternProperties:
  40   "^emc-timings-[0-9]+$":
  41     type: object
  42     properties:
  43       nvidia,ram-code:
  44         $ref: /schemas/types.yaml#/definitions/uint32
  45         description:
  46           Value of RAM_CODE this timing set is used for.
  47
  48     patternProperties:
  49       "^timing-[0-9]+$":
  50         type: object
  51         properties:
  52           clock-frequency:
  53             description:
  54               Memory clock rate in Hz.
  55             minimum: 1000000
  56             maximum: 900000000
  57
  58           nvidia,emc-auto-cal-interval:
  59             allOf:
  60               - $ref: /schemas/types.yaml#/definitions/uint32
  61             description:
  62               Pad calibration interval in microseconds.
  63             minimum: 0
  64             maximum: 2097151
  65
  66           nvidia,emc-mode-1:
  67             $ref: /schemas/types.yaml#/definitions/uint32
  68             description:
  69               Mode Register 1.
  70
  71           nvidia,emc-mode-2:
  72             $ref: /schemas/types.yaml#/definitions/uint32
  73             description:
  74               Mode Register 2.
  75
  76           nvidia,emc-mode-reset:
  77             $ref: /schemas/types.yaml#/definitions/uint32
  78             description:
  79               Mode Register 0.
  80
  81           nvidia,emc-zcal-cnt-long:
  82             allOf:
  83               - $ref: /schemas/types.yaml#/definitions/uint32
  84             description:
  85               Number of EMC clocks to wait before issuing any commands after
  86               sending ZCAL_MRW_CMD.
  87             minimum: 0
  88             maximum: 1023
  89
  90           nvidia,emc-cfg-dyn-self-ref:
  91             type: boolean
  92             description:
  93               Dynamic self-refresh enabled.
  94
  95           nvidia,emc-cfg-periodic-qrst:
  96             type: boolean
  97             description:
  98               FBIO "read" FIFO periodic resetting enabled.
  99
 100           nvidia,emc-configuration:
 101             allOf:
 102               - $ref: /schemas/types.yaml#/definitions/uint32-array
 103             description:
 104               EMC timing characterization data. These are the registers
 105               (see section "18.13.2 EMC Registers" in the TRM) whose values
 106               need to be specified, according to the board documentation.
 107             items:
 108               - description: EMC_RC
 109               - description: EMC_RFC
 110               - description: EMC_RAS
 111               - description: EMC_RP
 112               - description: EMC_R2W
 113               - description: EMC_W2R
 114               - description: EMC_R2P
 115               - description: EMC_W2P
 116               - description: EMC_RD_RCD
 117               - description: EMC_WR_RCD
 118               - description: EMC_RRD
 119               - description: EMC_REXT
 120               - description: EMC_WEXT
 121               - description: EMC_WDV
 122               - description: EMC_QUSE
 123               - description: EMC_QRST
 124               - description: EMC_QSAFE
 125               - description: EMC_RDV
 126               - description: EMC_REFRESH
 127               - description: EMC_BURST_REFRESH_NUM
 128               - description: EMC_PRE_REFRESH_REQ_CNT
 129               - description: EMC_PDEX2WR
 130               - description: EMC_PDEX2RD
 131               - description: EMC_PCHG2PDEN
 132               - description: EMC_ACT2PDEN
 133               - description: EMC_AR2PDEN
 134               - description: EMC_RW2PDEN
 135               - description: EMC_TXSR
 136               - description: EMC_TXSRDLL
 137               - description: EMC_TCKE
 138               - description: EMC_TFAW
 139               - description: EMC_TRPAB
 140               - description: EMC_TCLKSTABLE
 141               - description: EMC_TCLKSTOP
 142               - description: EMC_TREFBW
 143               - description: EMC_QUSE_EXTRA
 144               - description: EMC_FBIO_CFG6
 145               - description: EMC_ODT_WRITE
 146               - description: EMC_ODT_READ
 147               - description: EMC_FBIO_CFG5
 148               - description: EMC_CFG_DIG_DLL
 149               - description: EMC_CFG_DIG_DLL_PERIOD
 150               - description: EMC_DLL_XFORM_DQS0
 151               - description: EMC_DLL_XFORM_DQS1
 152               - description: EMC_DLL_XFORM_DQS2
 153               - description: EMC_DLL_XFORM_DQS3
 154               - description: EMC_DLL_XFORM_DQS4
 155               - description: EMC_DLL_XFORM_DQS5
 156               - description: EMC_DLL_XFORM_DQS6
 157               - description: EMC_DLL_XFORM_DQS7
 158               - description: EMC_DLL_XFORM_QUSE0
 159               - description: EMC_DLL_XFORM_QUSE1
 160               - description: EMC_DLL_XFORM_QUSE2
 161               - description: EMC_DLL_XFORM_QUSE3
 162               - description: EMC_DLL_XFORM_QUSE4
 163               - description: EMC_DLL_XFORM_QUSE5
 164               - description: EMC_DLL_XFORM_QUSE6
 165               - description: EMC_DLL_XFORM_QUSE7
 166               - description: EMC_DLI_TRIM_TXDQS0
 167               - description: EMC_DLI_TRIM_TXDQS1
 168               - description: EMC_DLI_TRIM_TXDQS2
 169               - description: EMC_DLI_TRIM_TXDQS3
 170               - description: EMC_DLI_TRIM_TXDQS4
 171               - description: EMC_DLI_TRIM_TXDQS5
 172               - description: EMC_DLI_TRIM_TXDQS6
 173               - description: EMC_DLI_TRIM_TXDQS7
 174               - description: EMC_DLL_XFORM_DQ0
 175               - description: EMC_DLL_XFORM_DQ1
 176               - description: EMC_DLL_XFORM_DQ2
 177               - description: EMC_DLL_XFORM_DQ3
 178               - description: EMC_XM2CMDPADCTRL
 179               - description: EMC_XM2DQSPADCTRL2
 180               - description: EMC_XM2DQPADCTRL2
 181               - description: EMC_XM2CLKPADCTRL
 182               - description: EMC_XM2COMPPADCTRL
 183               - description: EMC_XM2VTTGENPADCTRL
 184               - description: EMC_XM2VTTGENPADCTRL2
 185               - description: EMC_XM2QUSEPADCTRL
 186               - description: EMC_XM2DQSPADCTRL3
 187               - description: EMC_CTT_TERM_CTRL
 188               - description: EMC_ZCAL_INTERVAL
 189               - description: EMC_ZCAL_WAIT_CNT
 190               - description: EMC_MRS_WAIT_CNT
 191               - description: EMC_AUTO_CAL_CONFIG
 192               - description: EMC_CTT
 193               - description: EMC_CTT_DURATION
 194               - description: EMC_DYN_SELF_REF_CONTROL
 195               - description: EMC_FBIO_SPARE
 196               - description: EMC_CFG_RSV
 197
 198         required:
 199           - clock-frequency
 200           - nvidia,emc-auto-cal-interval
 201           - nvidia,emc-mode-1
 202           - nvidia,emc-mode-2
 203           - nvidia,emc-mode-reset
 204           - nvidia,emc-zcal-cnt-long
 205           - nvidia,emc-configuration
 206
 207         additionalProperties: false
 208
 209     required:
 210       - nvidia,ram-code
 211
 212     additionalProperties: false
 213
 214 required:
 215   - compatible
 216   - reg
 217   - interrupts
 218   - clocks
 219   - nvidia,memory-controller
 220
 221 additionalProperties: false
 222
 223 examples:
 224   - |
 225     external-memory-controller@7000f400 {
 226         compatible = "nvidia,tegra30-emc";
 227         reg = <0x7000f400 0x400>;
 228         interrupts = <0 78 4>;
 229         clocks = <&tegra_car 57>;
 230
 231         nvidia,memory-controller = <&mc>;
 232
 233         emc-timings-1 {
 234             nvidia,ram-code = <1>;
 235
 236             timing-667000000 {
 237                 clock-frequency = <667000000>;
 238
 239                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 240                 nvidia,emc-mode-1 = <0x80100002>;
 241                 nvidia,emc-mode-2 = <0x80200018>;
 242                 nvidia,emc-mode-reset = <0x80000b71>;
 243                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 244                 nvidia,emc-cfg-periodic-qrst;
 245
 246                 nvidia,emc-configuration = <
 247                     0x00000020 /* EMC_RC */
 248                     0x0000006a /* EMC_RFC */
 249                     0x00000017 /* EMC_RAS */
 250                     0x00000007 /* EMC_RP */
 251                     0x00000005 /* EMC_R2W */
 252                     0x0000000c /* EMC_W2R */
 253                     0x00000003 /* EMC_R2P */
 254                     0x00000011 /* EMC_W2P */
 255                     0x00000007 /* EMC_RD_RCD */
 256                     0x00000007 /* EMC_WR_RCD */
 257                     0x00000002 /* EMC_RRD */
 258                     0x00000001 /* EMC_REXT */
 259                     0x00000000 /* EMC_WEXT */
 260                     0x00000007 /* EMC_WDV */
 261                     0x0000000a /* EMC_QUSE */
 262                     0x00000009 /* EMC_QRST */
 263                     0x0000000b /* EMC_QSAFE */
 264                     0x00000011 /* EMC_RDV */
 265                     0x00001412 /* EMC_REFRESH */
 266                     0x00000000 /* EMC_BURST_REFRESH_NUM */
 267                     0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
 268                     0x00000002 /* EMC_PDEX2WR */
 269                     0x0000000e /* EMC_PDEX2RD */
 270                     0x00000001 /* EMC_PCHG2PDEN */
 271                     0x00000000 /* EMC_ACT2PDEN */
 272                     0x0000000c /* EMC_AR2PDEN */
 273                     0x00000016 /* EMC_RW2PDEN */
 274                     0x00000072 /* EMC_TXSR */
 275                     0x00000200 /* EMC_TXSRDLL */
 276                     0x00000005 /* EMC_TCKE */
 277                     0x00000015 /* EMC_TFAW */
 278                     0x00000000 /* EMC_TRPAB */
 279                     0x00000006 /* EMC_TCLKSTABLE */
 280                     0x00000007 /* EMC_TCLKSTOP */
 281                     0x00001453 /* EMC_TREFBW */
 282                     0x0000000b /* EMC_QUSE_EXTRA */
 283                     0x00000006 /* EMC_FBIO_CFG6 */
 284                     0x00000000 /* EMC_ODT_WRITE */
 285                     0x00000000 /* EMC_ODT_READ */
 286                     0x00005088 /* EMC_FBIO_CFG5 */
 287                     0xf00b0191 /* EMC_CFG_DIG_DLL */
 288                     0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 289                     0x00000008 /* EMC_DLL_XFORM_DQS0 */
 290                     0x00000008 /* EMC_DLL_XFORM_DQS1 */
 291                     0x00000008 /* EMC_DLL_XFORM_DQS2 */
 292                     0x00000008 /* EMC_DLL_XFORM_DQS3 */
 293                     0x0000000a /* EMC_DLL_XFORM_DQS4 */
 294                     0x0000000a /* EMC_DLL_XFORM_DQS5 */
 295                     0x0000000a /* EMC_DLL_XFORM_DQS6 */
 296                     0x0000000a /* EMC_DLL_XFORM_DQS7 */
 297                     0x00018000 /* EMC_DLL_XFORM_QUSE0 */
 298                     0x00018000 /* EMC_DLL_XFORM_QUSE1 */
 299                     0x00018000 /* EMC_DLL_XFORM_QUSE2 */
 300                     0x00018000 /* EMC_DLL_XFORM_QUSE3 */
 301                     0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 302                     0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 303                     0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 304                     0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 305                     0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 306                     0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 307                     0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 308                     0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 309                     0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 310                     0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 311                     0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 312                     0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 313                     0x0000000a /* EMC_DLL_XFORM_DQ0 */
 314                     0x0000000a /* EMC_DLL_XFORM_DQ1 */
 315                     0x0000000a /* EMC_DLL_XFORM_DQ2 */
 316                     0x0000000a /* EMC_DLL_XFORM_DQ3 */
 317                     0x000002a0 /* EMC_XM2CMDPADCTRL */
 318                     0x0800013d /* EMC_XM2DQSPADCTRL2 */
 319                     0x22220000 /* EMC_XM2DQPADCTRL2 */
 320                     0x77fff884 /* EMC_XM2CLKPADCTRL */
 321                     0x01f1f501 /* EMC_XM2COMPPADCTRL */
 322                     0x07077404 /* EMC_XM2VTTGENPADCTRL */
 323                     0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
 324                     0x080001e8 /* EMC_XM2QUSEPADCTRL */
 325                     0x0c000021 /* EMC_XM2DQSPADCTRL3 */
 326                     0x00000802 /* EMC_CTT_TERM_CTRL */
 327                     0x00020000 /* EMC_ZCAL_INTERVAL */
 328                     0x00000100 /* EMC_ZCAL_WAIT_CNT */
 329                     0x0155000c /* EMC_MRS_WAIT_CNT */
 330                     0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 331                     0x00000000 /* EMC_CTT */
 332                     0x00000000 /* EMC_CTT_DURATION */
 333                     0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
 334                     0xe8000000 /* EMC_FBIO_SPARE */
 335                     0xff00ff49 /* EMC_CFG_RSV */
 336                 >;
 337             };
 338         };
 339     };