1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
10 - Brian Norris <briannorris@chromium.org>
18 $ref: /schemas/types.yaml#/definitions/phandle
20 Node to get DDR loading. Refer to
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
30 operating-points-v2: true
37 $ref: /schemas/types.yaml#/definitions/phandle
39 Phandle to the syscon managing the "PMU general register files".
44 The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
45 finishes, a DCF interrupt is triggered.
47 rockchip,ddr3_speed_bin:
49 $ref: /schemas/types.yaml#/definitions/uint32
51 For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
52 DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
53 datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
58 $ref: /schemas/types.yaml#/definitions/uint32
60 Configure the PD_IDLE value. Defines the power-down idle period in which
61 memories are placed into power-down mode if bus is idle for PD_IDLE DFI
63 See also rockchip,pd-idle-ns.
67 $ref: /schemas/types.yaml#/definitions/uint32
69 Configure the SR_IDLE value. Defines the self-refresh idle period in
70 which memories are placed into self-refresh mode if bus is idle for
71 SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
72 See also rockchip,sr-idle-ns.
75 rockchip,sr_mc_gate_idle:
77 $ref: /schemas/types.yaml#/definitions/uint32
79 Defines the memory self-refresh and controller clock gating idle period.
80 Memories are placed into self-refresh mode and memory controller clock
81 arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
83 See also rockchip,sr-mc-gate-idle-ns.
85 rockchip,srpd_lite_idle:
87 $ref: /schemas/types.yaml#/definitions/uint32
89 Defines the self-refresh power down idle period in which memories are
90 placed into self-refresh power down mode if bus is idle for
91 srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
93 See also rockchip,srpd-lite-idle-ns.
95 rockchip,standby_idle:
97 $ref: /schemas/types.yaml#/definitions/uint32
99 Defines the standby idle period in which memories are placed into
100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
101 if bus is idle for standby_idle * DFI clock cycles.
102 See also rockchip,standby-idle-ns.
104 rockchip,dram_dll_dis_freq:
106 $ref: /schemas/types.yaml#/definitions/uint32
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
110 Note: if DLL was bypassed, the odt will also stop working.
112 rockchip,phy_dll_dis_freq:
114 $ref: /schemas/types.yaml#/definitions/uint32
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
117 is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
118 Note: PHY DLL and PHY ODT are independent.
120 rockchip,auto_pd_dis_freq:
122 $ref: /schemas/types.yaml#/definitions/uint32
124 Defines the auto PD disable frequency in MHz.
126 rockchip,ddr3_odt_dis_freq:
127 $ref: /schemas/types.yaml#/definitions/uint32
128 minimum: 1000000 # In case anyone thought this was MHz.
130 When the DRAM type is DDR3, this parameter defines the ODT disable
131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
132 the ODT on the DRAM side and controller side are both disabled.
136 $ref: /schemas/types.yaml#/definitions/uint32
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
144 $ref: /schemas/types.yaml#/definitions/uint32
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
150 rockchip,phy_ddr3_ca_drv:
152 $ref: /schemas/types.yaml#/definitions/uint32
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
155 (incluing command line, address line and clock line) drive strength.
158 rockchip,phy_ddr3_dq_drv:
160 $ref: /schemas/types.yaml#/definitions/uint32
162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
163 (including DQS/DQ/DM line) drive strength.
166 rockchip,phy_ddr3_odt:
168 $ref: /schemas/types.yaml#/definitions/uint32
170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
174 rockchip,lpddr3_odt_dis_freq:
175 $ref: /schemas/types.yaml#/definitions/uint32
176 minimum: 1000000 # In case anyone thought this was MHz.
178 When the DRAM type is LPDDR3, this parameter defines then ODT disable
179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
180 ODT on the DRAM side and controller side are both disabled.
184 $ref: /schemas/types.yaml#/definitions/uint32
186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
192 $ref: /schemas/types.yaml#/definitions/uint32
194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
198 rockchip,phy_lpddr3_ca_drv:
200 $ref: /schemas/types.yaml#/definitions/uint32
202 When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
203 (including command line, address line and clock line) drive strength.
206 rockchip,phy_lpddr3_dq_drv:
208 $ref: /schemas/types.yaml#/definitions/uint32
210 When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
211 (including DQS/DQ/DM line) drive strength.
214 rockchip,phy_lpddr3_odt:
216 $ref: /schemas/types.yaml#/definitions/uint32
218 When dram type is LPDDR3, this parameter define the phy side odt
219 strength, default value is 240.
221 rockchip,lpddr4_odt_dis_freq:
222 $ref: /schemas/types.yaml#/definitions/uint32
223 minimum: 1000000 # In case anyone thought this was MHz.
225 When the DRAM type is LPDDR4, this parameter defines the ODT disable
226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
227 the ODT on the DRAM side and controller side are both disabled.
231 $ref: /schemas/types.yaml#/definitions/uint32
233 When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
237 rockchip,lpddr4_dq_odt:
239 $ref: /schemas/types.yaml#/definitions/uint32
241 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
242 DQS/DQ line strength in ohms.
245 rockchip,lpddr4_ca_odt:
247 $ref: /schemas/types.yaml#/definitions/uint32
249 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
250 CA line strength in ohms.
253 rockchip,phy_lpddr4_ca_drv:
255 $ref: /schemas/types.yaml#/definitions/uint32
257 When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
258 (including command address line) drive strength.
261 rockchip,phy_lpddr4_ck_cs_drv:
263 $ref: /schemas/types.yaml#/definitions/uint32
265 When the DRAM type is LPDDR4, this parameter defines the PHY side clock
266 line and CS line drive strength.
269 rockchip,phy_lpddr4_dq_drv:
271 $ref: /schemas/types.yaml#/definitions/uint32
273 When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
274 (including DQS/DQ/DM line) drive strength.
277 rockchip,phy_lpddr4_odt:
279 $ref: /schemas/types.yaml#/definitions/uint32
281 When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
287 Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
288 period in which memories are placed into power-down mode if bus is idle
289 for PD_IDLE nanoseconds.
293 Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
294 period in which memories are placed into self-refresh mode if bus is idle
295 for SR_IDLE nanoseconds.
298 rockchip,sr-mc-gate-idle-ns:
300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
301 Memories are placed into self-refresh mode and memory controller clock
302 arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
304 rockchip,srpd-lite-idle-ns:
306 Defines the self-refresh power down idle period in which memories are
307 placed into self-refresh power down mode if bus is idle for
308 srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.
310 rockchip,standby-idle-ns:
312 Defines the standby idle period in which memories are placed into
313 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
314 if bus is idle for standby_idle nanoseconds.
316 rockchip,pd-idle-dis-freq-hz:
318 Defines the power-down idle disable frequency in Hz. When the DDR
319 frequency is greater than pd-idle-dis-freq, power-down idle is disabled.
320 See also rockchip,pd-idle-ns.
322 rockchip,sr-idle-dis-freq-hz:
324 Defines the self-refresh idle disable frequency in Hz. When the DDR
325 frequency is greater than sr-idle-dis-freq, self-refresh idle is
326 disabled. See also rockchip,sr-idle-ns.
328 rockchip,sr-mc-gate-idle-dis-freq-hz:
330 Defines the self-refresh and memory-controller clock gating disable
331 frequency in Hz. When the DDR frequency is greater than
332 sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
333 rockchip,sr-mc-gate-idle-ns.
335 rockchip,srpd-lite-idle-dis-freq-hz:
337 Defines the self-refresh power down idle disable frequency in Hz. When
338 the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will
339 not be placed into self-refresh power down mode when idle. See also
340 rockchip,srpd-lite-idle-ns.
342 rockchip,standby-idle-dis-freq-hz:
344 Defines the standby idle disable frequency in Hz. When the DDR frequency
345 is greater than standby-idle-dis-freq, standby idle is disabled. See also
346 rockchip,standby-idle-ns.
353 - operating-points-v2
356 additionalProperties: false
360 #include <dt-bindings/clock/rk3399-cru.h>
361 #include <dt-bindings/interrupt-controller/arm-gic.h>
363 compatible = "rockchip,rk3399-dmc";
364 devfreq-events = <&dfi>;
365 rockchip,pmu = <&pmu>;
366 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&cru SCLK_DDRC>;
368 clock-names = "dmc_clk";
369 operating-points-v2 = <&dmc_opp_table>;
370 center-supply = <&ppvar_centerlogic>;
371 rockchip,pd-idle-ns = <160>;
372 rockchip,sr-idle-ns = <10240>;
373 rockchip,sr-mc-gate-idle-ns = <40960>;
374 rockchip,srpd-lite-idle-ns = <61440>;
375 rockchip,standby-idle-ns = <81920>;
376 rockchip,ddr3_odt_dis_freq = <333000000>;
377 rockchip,lpddr3_odt_dis_freq = <333000000>;
378 rockchip,lpddr4_odt_dis_freq = <333000000>;
379 rockchip,pd-idle-dis-freq-hz = <1000000000>;
380 rockchip,sr-idle-dis-freq-hz = <1000000000>;
381 rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
382 rockchip,srpd-lite-idle-dis-freq-hz = <0>;
383 rockchip,standby-idle-dis-freq-hz = <928000000>;