Bindings/mmc/arasan,sdhci.txt

   1 Device Tree Bindings for the Arasan SDHCI Controller
   2
   3   The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
   4   Only deviations are documented here.
   5
   6   [1] Documentation/devicetree/bindings/mmc/mmc.txt
   7   [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
   8   [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
   9   [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
  10
  11 Required Properties:
  12   - compatible: Compatibility string.  One of:
  13     - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
  14     - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
  15     - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
  16     - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
  17       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  18     - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
  19       For this device it is strongly suggested to include clock-output-names and
  20       #clock-cells.
  21     - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
  22         Note: This binding has been deprecated and moved to [5].
  23     - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
  24       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  25     - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
  26       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  27
  28   [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
  29
  30   - reg: From mmc bindings: Register location and length.
  31   - clocks: From clock bindings: Handles to clock inputs.
  32   - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
  33   - interrupts: Interrupt specifier
  34
  35 Required Properties for "arasan,sdhci-5.1":
  36   - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
  37   - phy-names:  MUST be "phy_arasan".
  38
  39 Optional Properties:
  40   - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
  41     used to access core corecfg registers.  Offsets of registers in this
  42     syscon are determined based on the main compatible string for the device.
  43   - clock-output-names: If specified, this will be the name of the card clock
  44     which will be exposed by this device.  Required if #clock-cells is
  45     specified.
  46   - #clock-cells: If specified this should be the value <0> or <1>. With this
  47     property in place we will export one or two clocks representing the Card
  48     Clock. These clocks are expected to be consumed by our PHY.
  49   - xlnx,fails-without-test-cd: when present, the controller doesn't work when
  50     the CD line is not connected properly, and the line is not connected
  51     properly. Test mode can be used to force the controller to function.
  52   - xlnx,int-clock-stable-broken: when present, the controller always reports
  53     that the internal clock is stable even when it is not.
  54
  55   - xlnx,mio-bank: When specified, this will indicate the MIO bank number in
  56     which the command and data lines are configured. If not specified, driver
  57     will assume this as 0.
  58
  59 Example:
  60         sdhci@e0100000 {
  61                 compatible = "arasan,sdhci-8.9a";
  62                 reg = <0xe0100000 0x1000>;
  63                 clock-names = "clk_xin", "clk_ahb";
  64                 clocks = <&clkc 21>, <&clkc 32>;
  65                 interrupt-parent = <&gic>;
  66                 interrupts = <0 24 4>;
  67         } ;
  68
  69         sdhci@e2800000 {
  70                 compatible = "arasan,sdhci-5.1";
  71                 reg = <0xe2800000 0x1000>;
  72                 clock-names = "clk_xin", "clk_ahb";
  73                 clocks = <&cru 8>, <&cru 18>;
  74                 interrupt-parent = <&gic>;
  75                 interrupts = <0 24 4>;
  76                 phys = <&emmc_phy>;
  77                 phy-names = "phy_arasan";
  78         } ;
  79
  80         sdhci: sdhci@fe330000 {
  81                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
  82                 reg = <0x0 0xfe330000 0x0 0x10000>;
  83                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  84                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
  85                 clock-names = "clk_xin", "clk_ahb";
  86                 arasan,soc-ctl-syscon = <&grf>;
  87                 assigned-clocks = <&cru SCLK_EMMC>;
  88                 assigned-clock-rates = <200000000>;
  89                 clock-output-names = "emmc_cardclock";
  90                 phys = <&emmc_phy>;
  91                 phy-names = "phy_arasan";
  92                 #clock-cells = <0>;
  93         };
  94
  95         sdhci: mmc@ff160000 {
  96                 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
  97                 interrupt-parent = <&gic>;
  98                 interrupts = <0 48 4>;
  99                 reg = <0x0 0xff160000 0x0 0x1000>;
 100                 clocks = <&clk200>, <&clk200>;
 101                 clock-names = "clk_xin", "clk_ahb";
 102                 clock-output-names = "clk_out_sd0", "clk_in_sd0";
 103                 #clock-cells = <1>;
 104                 clk-phase-sd-hs = <63>, <72>;
 105         };
 106
 107         emmc: sdhci@ec700000 {
 108                 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
 109                 reg = <0xec700000 0x300>;
 110                 interrupt-parent = <&ioapic1>;
 111                 interrupts = <44 1>;
 112                 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
 113                          <&cgu0 LGM_GCLK_EMMC>;
 114                 clock-names = "clk_xin", "clk_ahb", "gate";
 115                 clock-output-names = "emmc_cardclock";
 116                 #clock-cells = <0>;
 117                 phys = <&emmc_phy>;
 118                 phy-names = "phy_arasan";
 119                 arasan,soc-ctl-syscon = <&sysconf>;
 120         };
 121
 122         sdxc: sdhci@ec600000 {
 123                 compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
 124                 reg = <0xec600000 0x300>;
 125                 interrupt-parent = <&ioapic1>;
 126                 interrupts = <43 1>;
 127                 clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
 128                          <&cgu0 LGM_GCLK_SDXC>;
 129                 clock-names = "clk_xin", "clk_ahb", "gate";
 130                 clock-output-names = "sdxc_cardclock";
 131                 #clock-cells = <0>;
 132                 phys = <&sdxc_phy>;
 133                 phy-names = "phy_arasan";
 134                 arasan,soc-ctl-syscon = <&sysconf>;
 135         };