Bindings/net/can/xilinx,can.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title:
   8   Xilinx Axi CAN/Zynq CANPS controller
   9
  10 maintainers:
  11   - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - xlnx,zynq-can-1.0
  17       - xlnx,axi-can-1.00.a
  18       - xlnx,canfd-1.0
  19       - xlnx,canfd-2.0
  20
  21   reg:
  22     maxItems: 1
  23
  24   interrupts:
  25     maxItems: 1
  26
  27   clocks:
  28     minItems: 1
  29     maxItems: 2
  30
  31   clock-names:
  32     maxItems: 2
  33
  34   power-domains:
  35     maxItems: 1
  36
  37   tx-fifo-depth:
  38     $ref: /schemas/types.yaml#/definitions/uint32
  39     description: CAN Tx fifo depth (Zynq, Axi CAN).
  40
  41   rx-fifo-depth:
  42     $ref: /schemas/types.yaml#/definitions/uint32
  43     description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
  44
  45   tx-mailbox-count:
  46     $ref: /schemas/types.yaml#/definitions/uint32
  47     description: CAN Tx mailbox buffer count (CAN FD)
  48
  49 required:
  50   - compatible
  51   - reg
  52   - interrupts
  53   - clocks
  54   - clock-names
  55
  56 unevaluatedProperties: false
  57
  58 allOf:
  59   - $ref: can-controller.yaml#
  60   - if:
  61       properties:
  62         compatible:
  63           contains:
  64             enum:
  65               - xlnx,zynq-can-1.0
  66
  67     then:
  68       properties:
  69         clock-names:
  70           items:
  71             - const: can_clk
  72             - const: pclk
  73       required:
  74         - tx-fifo-depth
  75         - rx-fifo-depth
  76
  77   - if:
  78       properties:
  79         compatible:
  80           contains:
  81             enum:
  82               - xlnx,axi-can-1.00.a
  83
  84     then:
  85       properties:
  86         clock-names:
  87           items:
  88             - const: can_clk
  89             - const: s_axi_aclk
  90       required:
  91         - tx-fifo-depth
  92         - rx-fifo-depth
  93
  94   - if:
  95       properties:
  96         compatible:
  97           contains:
  98             enum:
  99               - xlnx,canfd-1.0
 100               - xlnx,canfd-2.0
 101
 102     then:
 103       properties:
 104         clock-names:
 105           items:
 106             - const: can_clk
 107             - const: s_axi_aclk
 108       required:
 109         - tx-mailbox-count
 110         - rx-fifo-depth
 111
 112 examples:
 113   - |
 114     #include <dt-bindings/interrupt-controller/arm-gic.h>
 115
 116     can@e0008000 {
 117         compatible = "xlnx,zynq-can-1.0";
 118         reg = <0xe0008000 0x1000>;
 119         clocks = <&clkc 19>, <&clkc 36>;
 120         clock-names = "can_clk", "pclk";
 121         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 122         interrupt-parent = <&intc>;
 123         tx-fifo-depth = <0x40>;
 124         rx-fifo-depth = <0x40>;
 125     };
 126
 127   - |
 128     can@40000000 {
 129         compatible = "xlnx,axi-can-1.00.a";
 130         reg = <0x40000000 0x10000>;
 131         clocks = <&clkc 0>, <&clkc 1>;
 132         clock-names = "can_clk", "s_axi_aclk";
 133         interrupt-parent = <&intc>;
 134         interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
 135         tx-fifo-depth = <0x40>;
 136         rx-fifo-depth = <0x40>;
 137     };
 138
 139   - |
 140     can@40000000 {
 141         compatible = "xlnx,canfd-1.0";
 142         reg = <0x40000000 0x2000>;
 143         clocks = <&clkc 0>, <&clkc 1>;
 144         clock-names = "can_clk", "s_axi_aclk";
 145         interrupt-parent = <&intc>;
 146         interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
 147         tx-mailbox-count = <0x20>;
 148         rx-fifo-depth = <0x20>;
 149     };
 150
 151   - |
 152     can@ff060000 {
 153         compatible = "xlnx,canfd-2.0";
 154         reg = <0xff060000 0x6000>;
 155         clocks = <&clkc 0>, <&clkc 1>;
 156         clock-names = "can_clk", "s_axi_aclk";
 157         interrupt-parent = <&intc>;
 158         interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
 159         tx-mailbox-count = <0x20>;
 160         rx-fifo-depth = <0x40>;
 161     };