Bindings/net/dsa/renesas,rzn1-a5psw.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas RZ/N1 Advanced 5 ports ethernet switch
   8
   9 maintainers:
  10   - Clément Léger <clement.leger@bootlin.com>
  11
  12 description: |
  13   The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and
  14   handles 4 ports + 1 CPU management port.
  15
  16 allOf:
  17   - $ref: dsa.yaml#
  18
  19 properties:
  20   compatible:
  21     items:
  22       - enum:
  23           - renesas,r9a06g032-a5psw
  24       - const: renesas,rzn1-a5psw
  25
  26   reg:
  27     maxItems: 1
  28
  29   interrupts:
  30     items:
  31       - description: Device Level Ring (DLR) interrupt
  32       - description: Switch interrupt
  33       - description: Parallel Redundancy Protocol (PRP) interrupt
  34       - description: Integrated HUB module interrupt
  35       - description: Receive Pattern Match interrupt
  36
  37   interrupt-names:
  38     items:
  39       - const: dlr
  40       - const: switch
  41       - const: prp
  42       - const: hub
  43       - const: ptrn
  44
  45   power-domains:
  46     maxItems: 1
  47
  48   mdio:
  49     $ref: /schemas/net/mdio.yaml#
  50     unevaluatedProperties: false
  51
  52   clocks:
  53     items:
  54       - description: AHB clock used for the switch register interface
  55       - description: Switch system clock
  56
  57   clock-names:
  58     items:
  59       - const: hclk
  60       - const: clk
  61
  62   ethernet-ports:
  63     type: object
  64     properties:
  65       '#address-cells':
  66         const: 1
  67       '#size-cells':
  68         const: 0
  69
  70     patternProperties:
  71       "^(ethernet-)?port@[0-4]$":
  72         type: object
  73         description: Ethernet switch ports
  74
  75         properties:
  76           pcs-handle:
  77             maxItems: 1
  78             description:
  79               phandle pointing to a PCS sub-node compatible with
  80               renesas,rzn1-miic.yaml#
  81
  82 unevaluatedProperties: false
  83
  84 required:
  85   - compatible
  86   - reg
  87   - clocks
  88   - clock-names
  89   - power-domains
  90
  91 examples:
  92   - |
  93     #include <dt-bindings/gpio/gpio.h>
  94     #include <dt-bindings/clock/r9a06g032-sysctrl.h>
  95     #include <dt-bindings/interrupt-controller/arm-gic.h>
  96
  97     switch@44050000 {
  98         compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
  99         reg = <0x44050000 0x10000>;
 100         clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>;
 101         clock-names = "hclk", "clk";
 102         power-domains = <&sysctrl>;
 103         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 104                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 105                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 106                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 107                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 108         interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";
 109
 110         dsa,member = <0 0>;
 111
 112         ethernet-ports {
 113             #address-cells = <1>;
 114             #size-cells = <0>;
 115
 116             port@0 {
 117                 reg = <0>;
 118                 label = "lan0";
 119                 phy-handle = <&switch0phy3>;
 120                 pcs-handle = <&mii_conv4>;
 121             };
 122
 123             port@1 {
 124                 reg = <1>;
 125                 label = "lan1";
 126                 phy-handle = <&switch0phy1>;
 127                 pcs-handle = <&mii_conv3>;
 128             };
 129
 130             port@4 {
 131                 reg = <4>;
 132                 ethernet = <&gmac2>;
 133                 phy-mode = "internal";
 134
 135                 fixed-link {
 136                   speed = <1000>;
 137                   full-duplex;
 138                 };
 139             };
 140         };
 141
 142         mdio {
 143             #address-cells = <1>;
 144             #size-cells = <0>;
 145
 146             reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>;
 147             reset-delay-us = <15>;
 148             clock-frequency = <2500000>;
 149
 150             switch0phy1: ethernet-phy@1{
 151                 reg = <1>;
 152             };
 153
 154             switch0phy3: ethernet-phy@3{
 155                 reg = <3>;
 156             };
 157         };
 158     };