1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MAC
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
14 # Select every compatible, including the deprecated ones. This way, we
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
17 # as a valid value in the compatible property description
44 # We need to include all the compatibles from schemas that will
45 # include that schemas, otherwise compatible won't validate for
50 - allwinner,sun7i-a20-gmac
51 - allwinner,sun8i-a83t-emac
52 - allwinner,sun8i-h3-emac
53 - allwinner,sun8i-r40-gmac
54 - allwinner,sun8i-v3s-emac
55 - allwinner,sun50i-a64-emac
56 - amlogic,meson6-dwmac
57 - amlogic,meson8b-dwmac
58 - amlogic,meson8m2-dwmac
59 - amlogic,meson-gxbb-dwmac
60 - amlogic,meson-axg-dwmac
68 - renesas,r9a06g032-gmac
71 - rockchip,rk3128-gmac
72 - rockchip,rk3228-gmac
73 - rockchip,rk3288-gmac
74 - rockchip,rk3328-gmac
75 - rockchip,rk3366-gmac
76 - rockchip,rk3368-gmac
77 - rockchip,rk3588-gmac
78 - rockchip,rk3399-gmac
79 - rockchip,rv1108-gmac
100 - description: Combined signal for various interrupt events
101 - description: The interrupt to manage the remote wake-up packet detection
102 - description: The interrupt that occurs when Rx exits the LPI state
108 - const: eth_wake_irq
114 additionalItems: true
116 - description: GMAC main clock
117 - description: Peripheral registers interface clock
119 PTP reference clock. This clock is used for programming the
120 Timestamp Addend Register. If not passed then the system
121 clock will be used and this is fine on some platforms.
126 additionalItems: true
145 $ref: ethernet-controller.yaml#/properties/phy-connection-type
147 The property is identical to 'phy-mode', and assumes that there is mode
148 converter in-between the MAC & PHY (e.g. GMII-to-RGMII). This converter
149 can be passive (no SW requirement), and requires that the MAC operate
150 in a different mode than the PHY in order to function.
153 $ref: /schemas/types.yaml#/definitions/phandle
155 AXI BUS Mode parameters. Phandle to a node that can contain the
157 * snps,lpi_en, enable Low Power Interface
158 * snps,xit_frm, unlock on WoL
159 * snps,wr_osr_lmt, max write outstanding req. limit
160 * snps,rd_osr_lmt, max read outstanding req. limit
161 * snps,kbbe, do not cross 1KiB boundary.
162 * snps,blen, this is a vector of supported burst length.
163 * snps,fb, fixed-burst
164 * snps,mb, mixed-burst
165 * snps,rb, rebuild INCRx Burst
168 $ref: /schemas/types.yaml#/definitions/phandle
170 Multiple RX Queues parameters. Phandle to a node that
171 implements the 'rx-queues-config' object described in
177 snps,rx-queues-to-use:
178 $ref: /schemas/types.yaml#/definitions/uint32
179 description: number of RX queues to be used in the driver
182 description: Strict priority
185 description: Weighted Strict priority
192 snps,rx-sched-wsp: false
198 snps,rx-sched-sp: false
201 description: Each subnode represents a queue.
206 description: Queue to be enabled as DCB
209 description: Queue to be enabled as AVB
210 snps,map-to-dma-channel:
211 $ref: /schemas/types.yaml#/definitions/uint32
212 description: DMA channel id to map
215 description: AV Untagged Control packets
218 description: PTP Packets
221 description: DCB Control Packets
224 description: Untagged Packets
225 snps,route-multi-broad:
227 description: Multicast & Broadcast Packets
229 $ref: /schemas/types.yaml#/definitions/uint32
230 description: Bitmask of the tagged frames priorities assigned to the queue
237 snps,avb-algorithm: false
243 snps,dcb-algorithm: false
249 snps,route-ptp: false
250 snps,route-dcbcp: false
252 snps,route-multi-broad: false
258 snps,route-avcp: false
259 snps,route-dcbcp: false
261 snps,route-multi-broad: false
267 snps,route-avcp: false
268 snps,route-ptp: false
270 snps,route-multi-broad: false
276 snps,route-avcp: false
277 snps,route-ptp: false
278 snps,route-dcbcp: false
279 snps,route-multi-broad: false
282 - snps,route-multi-broad
285 snps,route-avcp: false
286 snps,route-ptp: false
287 snps,route-dcbcp: false
289 additionalProperties: false
290 additionalProperties: false
293 $ref: /schemas/types.yaml#/definitions/phandle
295 Multiple TX Queues parameters. Phandle to a node that
296 implements the 'tx-queues-config' object described in
302 snps,tx-queues-to-use:
303 $ref: /schemas/types.yaml#/definitions/uint32
304 description: number of TX queues to be used in the driver
307 description: Weighted Round Robin
310 description: Weighted Fair Queuing
313 description: Deficit Weighted Round Robin
316 description: Strict priority
323 snps,tx-sched-wfq: false
324 snps,tx-sched-dwrr: false
325 snps,tx-sched-sp: false
331 snps,tx-sched-wrr: false
332 snps,tx-sched-dwrr: false
333 snps,tx-sched-sp: false
339 snps,tx-sched-wrr: false
340 snps,tx-sched-wfq: false
341 snps,tx-sched-sp: false
347 snps,tx-sched-wrr: false
348 snps,tx-sched-wfq: false
349 snps,tx-sched-dwrr: false
352 description: Each subnode represents a queue.
356 $ref: /schemas/types.yaml#/definitions/uint32
357 description: TX queue weight (if using a DCB weight algorithm)
360 description: TX queue will be working in DCB
364 TX queue will be working in AVB.
365 Queue 0 is reserved for legacy traffic and so no AVB is
366 available in this queue.
368 $ref: /schemas/types.yaml#/definitions/uint32
369 description: enable Low Power Interface
371 $ref: /schemas/types.yaml#/definitions/uint32
372 description: unlock on WoL
374 $ref: /schemas/types.yaml#/definitions/uint32
375 description: max write outstanding req. limit
377 $ref: /schemas/types.yaml#/definitions/uint32
378 description: max read outstanding req. limit
380 $ref: /schemas/types.yaml#/definitions/uint32
382 Bitmask of the tagged frames priorities assigned to the queue.
383 When a PFC frame is received with priorities matching the bitmask,
384 the queue is blocked from transmitting for the pause time specified
392 snps,avb-algorithm: false
398 snps,dcb-algorithm: false
400 additionalProperties: false
401 additionalProperties: false
409 snps,reset-active-low:
411 $ref: /schemas/types.yaml#/definitions/flag
413 Indicates that the PHY Reset is active low
415 snps,reset-delays-us:
418 Triplet of delays. The 1st cell is reset pre-delay in micro
419 seconds. The 2nd cell is reset pulse in micro seconds. The 3rd
420 cell is reset post-delay in micro seconds.
425 $ref: /schemas/types.yaml#/definitions/flag
427 Use Address-Aligned Beats
430 $ref: /schemas/types.yaml#/definitions/flag
432 Program the DMA to use the fixed burst mode
435 $ref: /schemas/types.yaml#/definitions/flag
437 Program the DMA to use the mixed burst mode
439 snps,force_thresh_dma_mode:
440 $ref: /schemas/types.yaml#/definitions/flag
442 Force DMA to use the threshold mode for both tx and rx
444 snps,force_sf_dma_mode:
445 $ref: /schemas/types.yaml#/definitions/flag
447 Force DMA to use the Store and Forward mode for both tx and
448 rx. This flag is ignored if force_thresh_dma_mode is set.
450 snps,en-tx-lpi-clockgating:
451 $ref: /schemas/types.yaml#/definitions/flag
453 Enable gating of the MAC TX clock during TX low-power mode
455 snps,multicast-filter-bins:
456 $ref: /schemas/types.yaml#/definitions/uint32
458 Number of multicast filter hash bins supported by this device
461 snps,perfect-filter-entries:
462 $ref: /schemas/types.yaml#/definitions/uint32
464 Number of perfect filter entries supported by this device
468 $ref: /schemas/types.yaml#/definitions/uint32
470 Port selection speed that can be passed to the core when PCS
471 is supported. For example, this is used in case of SGMII and
475 $ref: /schemas/types.yaml#/definitions/uint32
477 Frequency division factor for MDC clock.
481 unevaluatedProperties: false
483 Creates and registers an MDIO bus.
487 const: snps,dwmac-mdio
494 unevaluatedProperties: false
496 AXI BUS Mode parameters.
500 $ref: /schemas/types.yaml#/definitions/flag
502 enable Low Power Interface
505 $ref: /schemas/types.yaml#/definitions/flag
510 $ref: /schemas/types.yaml#/definitions/uint32
512 max write outstanding req. limit
515 $ref: /schemas/types.yaml#/definitions/uint32
517 max read outstanding req. limit
520 $ref: /schemas/types.yaml#/definitions/uint32
522 do not cross 1KiB boundary.
525 $ref: /schemas/types.yaml#/definitions/uint32-array
527 this is a vector of supported burst length.
532 $ref: /schemas/types.yaml#/definitions/flag
537 $ref: /schemas/types.yaml#/definitions/flag
542 $ref: /schemas/types.yaml#/definitions/flag
554 snps,reset-active-low: ["snps,reset-gpio"]
555 snps,reset-delay-us: ["snps,reset-gpio"]
558 - $ref: "ethernet-controller.yaml#"
564 - allwinner,sun7i-a20-gmac
565 - allwinner,sun8i-a83t-emac
566 - allwinner,sun8i-h3-emac
567 - allwinner,sun8i-r40-gmac
568 - allwinner,sun8i-v3s-emac
569 - allwinner,sun50i-a64-emac
586 Programmable Burst Length (tx and rx)
587 $ref: /schemas/types.yaml#/definitions/uint32
588 enum: [1, 2, 4, 8, 16, 32]
592 Tx Programmable Burst Length. If set, DMA tx will use this
593 value rather than snps,pbl.
594 $ref: /schemas/types.yaml#/definitions/uint32
595 enum: [1, 2, 4, 8, 16, 32]
599 Rx Programmable Burst Length. If set, DMA rx will use this
600 value rather than snps,pbl.
601 $ref: /schemas/types.yaml#/definitions/uint32
602 enum: [1, 2, 4, 8, 16, 32]
605 $ref: /schemas/types.yaml#/definitions/flag
607 Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
608 rev < 3.50, don\'t multiply the values by 4.
615 - allwinner,sun7i-a20-gmac
616 - allwinner,sun8i-a83t-emac
617 - allwinner,sun8i-h3-emac
618 - allwinner,sun8i-r40-gmac
619 - allwinner,sun8i-v3s-emac
620 - allwinner,sun50i-a64-emac
621 - loongson,ls2k-dwmac
622 - loongson,ls7a-dwmac
639 $ref: /schemas/types.yaml#/definitions/flag
641 Enables the TSO feature otherwise it will be managed by
642 MAC HW capability register.
644 additionalProperties: true
648 gmac0: ethernet@e0800000 {
649 compatible = "snps,dwxgmac-2.10", "snps,dwxgmac";
650 reg = <0xe0800000 0x8000>;
651 interrupt-parent = <&vic1>;
652 interrupts = <24 23 22>;
653 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
654 mac-address = [000000000000]; /* Filled in by U-Boot */
655 max-frame-size = <3800>;
657 snps,multicast-filter-bins = <256>;
658 snps,perfect-filter-entries = <128>;
659 rx-fifo-depth = <16384>;
660 tx-fifo-depth = <16384>;
662 clock-names = "stmmaceth";
663 snps,axi-config = <&stmmac_axi_setup>;
664 snps,mtl-rx-config = <&mtl_rx_setup>;
665 snps,mtl-tx-config = <&mtl_tx_setup>;
667 stmmac_axi_setup: stmmac-axi-config {
668 snps,wr_osr_lmt = <0xf>;
669 snps,rd_osr_lmt = <0xf>;
670 snps,blen = <256 128 64 32 0 0 0>;
673 mtl_rx_setup: rx-queues-config {
674 snps,rx-queues-to-use = <1>;
678 snps,map-to-dma-channel = <0x0>;
679 snps,priority = <0x0>;
683 mtl_tx_setup: tx-queues-config {
684 snps,tx-queues-to-use = <2>;
687 snps,weight = <0x10>;
689 snps,priority = <0x0>;
694 snps,send_slope = <0x1000>;
695 snps,idle_slope = <0x1000>;
696 snps,high_credit = <0x3E800>;
697 snps,low_credit = <0xFFC18000>;
698 snps,priority = <0x1>;
703 #address-cells = <1>;
705 compatible = "snps,dwmac-mdio";
706 phy1: ethernet-phy@0 {
712 # FIXME: We should set it, but it would report all the generic
713 # properties as additional properties.
714 # additionalProperties: false