1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PCIe Endpoint Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
20 - description: Qualcomm-specific PARF configuration registers
21 - description: DesignWare PCIe registers
22 - description: External local bus interface registers
23 - description: Address Translation Unit (ATU) registers
24 - description: Memory region used to map remote RC address space
25 - description: BAR memory region
45 description: Reference to a syscon representing TCSR followed by the two
46 offsets within syscon for Perst enable and Perst separation
48 $ref: /schemas/types.yaml#/definitions/phandle-array
51 - description: Syscon to TCSR system registers
52 - description: Perst enable offset
53 - description: Perst separation enable offset
57 - description: PCIe Global interrupt
58 - description: PCIe Doorbell interrupt
66 description: GPIO used as PERST# input signal
70 description: GPIO used as WAKE# output signal
116 - description: PCIe Auxiliary clock
117 - description: PCIe CFG AHB clock
118 - description: PCIe Master AXI clock
119 - description: PCIe Slave AXI clock
120 - description: PCIe Slave Q2A AXI clock
121 - description: PCIe Sleep clock
122 - description: PCIe Reference clock
138 - qcom,sm8450-pcie-ep
143 - description: PCIe Auxiliary clock
144 - description: PCIe CFG AHB clock
145 - description: PCIe Master AXI clock
146 - description: PCIe Slave AXI clock
147 - description: PCIe Slave Q2A AXI clock
148 - description: PCIe Reference clock
149 - description: PCIe DDRSS SF TBU clock
150 - description: PCIe AGGRE NOC AXI clock
159 - const: ddrss_sf_tbu
160 - const: aggre_noc_axi
162 unevaluatedProperties: false
166 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
167 #include <dt-bindings/gpio/gpio.h>
168 #include <dt-bindings/interrupt-controller/arm-gic.h>
169 pcie_ep: pcie-ep@1c00000 {
170 compatible = "qcom,sdx55-pcie-ep";
171 reg = <0x01c00000 0x3000>,
177 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
180 clocks = <&gcc GCC_PCIE_AUX_CLK>,
181 <&gcc GCC_PCIE_CFG_AHB_CLK>,
182 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
183 <&gcc GCC_PCIE_SLV_AXI_CLK>,
184 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
185 <&gcc GCC_PCIE_SLEEP_CLK>,
186 <&gcc GCC_PCIE_0_CLKREF_CLK>;
187 clock-names = "aux", "cfg", "bus_master", "bus_slave",
188 "slave_q2a", "sleep", "ref";
190 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
192 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
194 interrupt-names = "global", "doorbell";
195 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
196 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
197 resets = <&gcc GCC_PCIE_BCR>;
198 reset-names = "core";
199 power-domains = <&gcc PCIE_GDSC>;
200 phys = <&pcie0_lane>;
201 phy-names = "pciephy";
202 max-link-speed = <3>;