1 * Qualcomm PCI express root complex
5 Value type: <stringlist>
6 Definition: Value should contain
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-apq8064" for apq8064
9 - "qcom,pcie-apq8084" for apq8084
10 - "qcom,pcie-msm8996" for msm8996 or apq8096
11 - "qcom,pcie-ipq4019" for ipq4019
15 Value type: <prop-encoded-array>
16 Definition: Register ranges as listed in the reg-names property
20 Value type: <stringlist>
21 Definition: Must include the following entries
22 - "parf" Qualcomm specific registers
23 - "dbi" Designware PCIe registers
24 - "elbi" External local bus interface registers
25 - "config" PCIe configuration space
30 Definition: Should be "pci". As specified in designware-pcie.txt
35 Definition: Should be 3. As specified in designware-pcie.txt
40 Definition: Should be 2. As specified in designware-pcie.txt
44 Value type: <prop-encoded-array>
45 Definition: As specified in designware-pcie.txt
49 Value type: <prop-encoded-array>
50 Definition: MSI interrupt
54 Value type: <stringlist>
55 Definition: Should contain "msi"
60 Definition: Should be 1. As specified in designware-pcie.txt
64 Value type: <prop-encoded-array>
65 Definition: As specified in designware-pcie.txt
69 Value type: <prop-encoded-array>
70 Definition: As specified in designware-pcie.txt
74 Value type: <prop-encoded-array>
75 Definition: List of phandle and clock specifier pairs as listed
76 in clock-names property
80 Value type: <stringlist>
81 Definition: Should contain the following entries
82 - "iface" Configuration AHB clock
85 Usage: required for ipq/apq8064
86 Value type: <stringlist>
87 Definition: Should contain the following entries
88 - "core" Clocks the pcie hw block
89 - "phy" Clocks the pcie PHY block
91 Usage: required for apq8084/ipq4019
92 Value type: <stringlist>
93 Definition: Should contain the following entries
94 - "aux" Auxiliary (AUX) clock
95 - "bus_master" Master AXI clock
96 - "bus_slave" Slave AXI clock
99 Usage: required for msm8996/apq8096
100 Value type: <stringlist>
101 Definition: Should contain the following entries
102 - "pipe" Pipe Clock driving internal logic
103 - "aux" Auxiliary (AUX) clock
104 - "cfg" Configuration clock
105 - "bus_master" Master AXI clock
106 - "bus_slave" Slave AXI clock
110 Value type: <prop-encoded-array>
111 Definition: List of phandle and reset specifier pairs as listed
112 in reset-names property
115 Usage: required for ipq/apq8064
116 Value type: <stringlist>
117 Definition: Should contain the following entries
125 Usage: required for apq8084
126 Value type: <stringlist>
127 Definition: Should contain the following entries
131 Usage: required for ipq/apq8064
132 Value type: <stringlist>
133 Definition: Should contain the following entries
134 - "axi_m" AXI master reset
135 - "axi_s" AXI slave reset
137 - "axi_m_vmid" VMID reset
138 - "axi_s_xpu" XPU reset
141 - "axi_m_sticky" AXI sticky reset
142 - "pipe_sticky" PIPE sticky reset
145 - "phy_ahb" PHY AHB reset
148 Usage: required for apq8084 and msm8996/apq8096
149 Value type: <prop-encoded-array>
150 Definition: A phandle and power domain specifier pair to the
151 power domain which is responsible for collapsing
152 and restoring power to the peripheral
156 Value type: <phandle>
157 Definition: A phandle to the core analog power supply
160 Usage: required for ipq/apq8064
161 Value type: <phandle>
162 Definition: A phandle to the analog power supply for PHY
164 - vdda_refclk-supply:
165 Usage: required for ipq/apq8064
166 Value type: <phandle>
167 Definition: A phandle to the analog power supply for IC which generates
171 Usage: required for apq8084
172 Value type: <phandle>
173 Definition: List of phandle(s) as listed in phy-names property
176 Usage: required for apq8084
177 Value type: <stringlist>
178 Definition: Should contain "pciephy"
182 Value type: <prop-encoded-array>
183 Definition: List of phandle and gpio specifier pairs. Should contain
184 - "perst-gpios" PCIe endpoint reset signal line
185 - "wake-gpios" PCIe endpoint wake signal line
187 * Example for ipq/apq8064
189 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
190 reg = <0x1b500000 0x1000
193 0x0ff00000 0x100000>;
194 reg-names = "dbi", "elbi", "parf", "config";
196 linux,pci-domain = <0>;
197 bus-range = <0x00 0xff>;
199 #address-cells = <3>;
201 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
202 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
203 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
204 interrupt-names = "msi";
205 #interrupt-cells = <1>;
206 interrupt-map-mask = <0 0 0 0x7>;
207 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
208 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
209 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
210 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
211 clocks = <&gcc PCIE_A_CLK>,
214 clock-names = "core", "iface", "phy";
215 resets = <&gcc PCIE_ACLK_RESET>,
216 <&gcc PCIE_HCLK_RESET>,
217 <&gcc PCIE_POR_RESET>,
218 <&gcc PCIE_PCI_RESET>,
219 <&gcc PCIE_PHY_RESET>;
220 reset-names = "axi", "ahb", "por", "pci", "phy";
221 pinctrl-0 = <&pcie_pins_default>;
222 pinctrl-names = "default";
225 * Example for apq8084
227 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
228 reg = <0xfc520000 0x2000>,
232 reg-names = "parf", "dbi", "elbi", "config";
234 linux,pci-domain = <0>;
235 bus-range = <0x00 0xff>;
237 #address-cells = <3>;
239 ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
240 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
241 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
242 interrupt-names = "msi";
243 #interrupt-cells = <1>;
244 interrupt-map-mask = <0 0 0 0x7>;
245 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
246 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
247 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
248 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
249 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
250 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
251 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
252 <&gcc GCC_PCIE_0_AUX_CLK>;
253 clock-names = "iface", "master_bus", "slave_bus", "aux";
254 resets = <&gcc GCC_PCIE_0_BCR>;
255 reset-names = "core";
256 power-domains = <&gcc PCIE0_GDSC>;
257 vdda-supply = <&pma8084_l3>;
259 phy-names = "pciephy";
260 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
261 pinctrl-0 = <&pcie0_pins_default>;
262 pinctrl-names = "default";