1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Torrent SD0801 PHY
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
12 PHY also supports multilink multiprotocol combinations including protocols
13 such as PCIe, USB, SGMII, QSGMII etc.
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
38 PHY reference clock for 1 item. Must contain an entry in clock-names.
39 Optional Parent to enable output reference clock.
45 - const: phy_en_refclk
50 - description: Offset of the Torrent PHY configuration registers.
51 - description: Offset of the DPTX PHY configuration registers.
62 - description: Torrent PHY reset.
63 - description: Torrent APB reset. This is optional.
68 - const: torrent_reset
75 Each group of PHY lanes with a single master lane should be represented as a sub-node.
79 The master lane number. This is the lowest numbered lane in the lane group.
87 Contains list of resets, one per lane, to get all the link lanes out of reset.
94 Specifies the type of PHY for which the group of PHY lanes is used.
95 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
96 $ref: /schemas/types.yaml#/definitions/uint32
103 $ref: /schemas/types.yaml#/definitions/uint32
109 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
110 EXTERNAL_SSC or INTERNAL_SSC.
111 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
112 $ref: /schemas/types.yaml#/definitions/uint32
118 Maximum DisplayPort link bit rate to use, in Mbps
119 $ref: /schemas/types.yaml#/definitions/uint32
120 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
130 additionalProperties: false
143 additionalProperties: false
147 #include <dt-bindings/phy/phy.h>
150 #address-cells = <2>;
153 torrent-phy@f0fb500000 {
154 compatible = "cdns,torrent-phy";
155 reg = <0xf0 0xfb500000 0x0 0x00100000>,
156 <0xf0 0xfb030a00 0x0 0x00000040>;
157 reg-names = "torrent_phy", "dptx_phy";
158 resets = <&phyrst 0>;
159 reset-names = "torrent_reset";
161 clock-names = "refclk";
162 #address-cells = <1>;
166 resets = <&phyrst 1>, <&phyrst 2>,
167 <&phyrst 3>, <&phyrst 4>;
169 cdns,phy-type = <PHY_TYPE_DP>;
170 cdns,num-lanes = <4>;
171 cdns,max-bit-rate = <8100>;
176 #include <dt-bindings/phy/phy.h>
177 #include <dt-bindings/phy/phy-cadence.h>
180 #address-cells = <2>;
183 torrent-phy@f0fb500000 {
184 compatible = "cdns,torrent-phy";
185 reg = <0xf0 0xfb500000 0x0 0x00100000>;
186 reg-names = "torrent_phy";
187 resets = <&phyrst 0>, <&phyrst 1>;
188 reset-names = "torrent_reset", "torrent_apb";
190 clock-names = "refclk";
191 #address-cells = <1>;
195 resets = <&phyrst 2>, <&phyrst 3>;
197 cdns,phy-type = <PHY_TYPE_PCIE>;
198 cdns,num-lanes = <2>;
199 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
204 resets = <&phyrst 4>;
206 cdns,phy-type = <PHY_TYPE_SGMII>;
207 cdns,num-lanes = <1>;
208 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;