Bindings/phy/qcom,qmp-usb3-dp-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Qualcomm QMP USB3 DP PHY controller
   9
  10 maintainers:
  11   - Manu Gautam <mgautam@codeaurora.org>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - qcom,sc7180-qmp-usb3-phy
  17       - qcom,sdm845-qmp-usb3-phy
  18   reg:
  19     items:
  20       - description: Address and length of PHY's common serdes block.
  21       - description: Address and length of the DP_COM control block.
  22
  23   reg-names:
  24     items:
  25       - const: reg-base
  26       - const: dp_com
  27
  28   "#clock-cells":
  29      enum: [ 1, 2 ]
  30
  31   "#address-cells":
  32     enum: [ 1, 2 ]
  33
  34   "#size-cells":
  35     enum: [ 1, 2 ]
  36
  37   ranges: true
  38
  39   clocks:
  40     items:
  41       - description: Phy aux clock.
  42       - description: Phy config clock.
  43       - description: 19.2 MHz ref clk.
  44       - description: Phy common block aux clock.
  45
  46   clock-names:
  47     items:
  48       - const: aux
  49       - const: cfg_ahb
  50       - const: ref
  51       - const: com_aux
  52
  53   resets:
  54     items:
  55       - description: reset of phy block.
  56       - description: phy common block reset.
  57
  58   reset-names:
  59     items:
  60       - const: phy
  61       - const: common
  62
  63   vdda-phy-supply:
  64     description:
  65         Phandle to a regulator supply to PHY core block.
  66
  67   vdda-pll-supply:
  68     description:
  69         Phandle to 1.8V regulator supply to PHY refclk pll block.
  70
  71   vddp-ref-clk-supply:
  72     description:
  73         Phandle to a regulator supply to any specific refclk
  74         pll block.
  75
  76 #Required nodes:
  77 patternProperties:
  78   "^phy@[0-9a-f]+$":
  79     type: object
  80     description:
  81       Each device node of QMP phy is required to have as many child nodes as
  82       the number of lanes the PHY has.
  83
  84 required:
  85   - compatible
  86   - reg
  87   - reg-names
  88   - "#clock-cells"
  89   - "#address-cells"
  90   - "#size-cells"
  91   - ranges
  92   - clocks
  93   - clock-names
  94   - resets
  95   - reset-names
  96   - vdda-phy-supply
  97   - vdda-pll-supply
  98
  99 additionalProperties: false
 100
 101 examples:
 102   - |
 103     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 104     usb_1_qmpphy: phy-wrapper@88e9000 {
 105         compatible = "qcom,sdm845-qmp-usb3-phy";
 106         reg = <0x088e9000 0x18c>,
 107               <0x088e8000 0x10>;
 108         reg-names = "reg-base", "dp_com";
 109         #clock-cells = <1>;
 110         #address-cells = <1>;
 111         #size-cells = <1>;
 112         ranges = <0x0 0x088e9000 0x1000>;
 113
 114         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
 115                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 116                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 117                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
 118         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
 119
 120         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
 121                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
 122         reset-names = "phy", "common";
 123
 124         vdda-phy-supply = <&vdda_usb2_ss_1p2>;
 125         vdda-pll-supply = <&vdda_usb2_ss_core>;
 126
 127         phy@200 {
 128             reg = <0x200 0x128>,
 129                   <0x400 0x200>,
 130                   <0xc00 0x218>,
 131                   <0x600 0x128>,
 132                   <0x800 0x200>,
 133                   <0xa00 0x100>;
 134             #clock-cells = <0>;
 135             #phy-cells = <0>;
 136             clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 137             clock-names = "pipe0";
 138             clock-output-names = "usb3_phy_pipe_clk_src";
 139         };
 140     };