1 Qualcomm QUSB2 phy controller
2 =============================
4 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
7 - compatible: compatible list, contains
8 "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
9 "qcom,qusb2-v2-phy" for QUSB2 V2 PHY.
11 - reg: offset and length of the PHY register set.
12 - #phy-cells: must be 0.
14 - clocks: a list of phandles and clock-specifier pairs,
15 one for each entry in clock-names.
16 - clock-names: must be "cfg_ahb" for phy config clock,
17 "ref" for 19.2 MHz ref clk,
18 "iface" for phy interface clock (Optional).
20 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
21 - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
23 - resets: Phandle to reset to phy block.
26 - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
27 tuning parameter value for qusb2 phy.
29 - qcom,tcsr-syscon: Phandle to TCSR syscon register region.
32 hsusb_phy: phy@7411000 {
33 compatible = "qcom,msm8996-qusb2-phy";
34 reg = <0x7411000 0x180>;
37 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
38 <&gcc GCC_RX1_USB2_CLKREF_CLK>,
39 clock-names = "cfg_ahb", "ref";
41 vdda-pll-supply = <&pm8994_l12>;
42 vdda-phy-dpdm-supply = <&pm8994_l24>;
44 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
45 nvmem-cells = <&qusb2p_hstx_trim>;