Bindings/phy/ti,phy-gmii-sel.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
   9
  10 maintainers:
  11   - Kishon Vijay Abraham I <kishon@ti.com>
  12
  13 description: |
  14   TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
  15   two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
  16   The interface mode is selected by configuring the MII mode selection register(s)
  17   (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
  18   bit fields placement in SCM are different between SoCs while fields meaning
  19   is the same.
  20                                                +--------------+
  21         +-------------------------------+      |SCM           |
  22         |                     CPSW      |      |  +---------+ |
  23         |        +--------------------------------+gmii_sel | |
  24         |        |                      |      |  +---------+ |
  25         |   +----v---+     +--------+   |      +--------------+
  26         |   |Port 1..<--+-->GMII/MII<------->
  27         |   |        |  |  |        |   |
  28         |   +--------+  |  +--------+   |
  29         |               |               |
  30         |               |  +--------+   |
  31         |               |  | RMII   <------->
  32         |               +-->        |   |
  33         |               |  +--------+   |
  34         |               |               |
  35         |               |  +--------+   |
  36         |               |  | RGMII  <------->
  37         |               +-->        |   |
  38         |                  +--------+   |
  39         +-------------------------------+
  40
  41   CPSW Port's Interface Mode Selection PHY describes MII interface mode between
  42   CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
  43   |
  44   CPSW Port's Interface Mode Selection PHY device should defined as child device
  45   of SCM node (scm_conf) and can be attached to each CPSW port node using standard
  46   PHY bindings.
  47
  48 properties:
  49   compatible:
  50     enum:
  51       - ti,am3352-phy-gmii-sel
  52       - ti,dra7xx-phy-gmii-sel
  53       - ti,am43xx-phy-gmii-sel
  54       - ti,dm814-phy-gmii-sel
  55       - ti,am654-phy-gmii-sel
  56       - ti,j7200-cpsw5g-phy-gmii-sel
  57
  58   reg:
  59     maxItems: 1
  60
  61   '#phy-cells': true
  62
  63   ti,qsgmii-main-ports:
  64     $ref: /schemas/types.yaml#/definitions/uint32-array
  65     description: |
  66       Required only for QSGMII mode. Array to select the port for
  67       QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
  68       ports automatically. Any one of the 4 CPSW5G ports can act as the
  69       main port with the rest of them being the QSGMII_SUB ports.
  70     maxItems: 1
  71     items:
  72       minimum: 1
  73       maximum: 4
  74
  75 allOf:
  76   - if:
  77       properties:
  78         compatible:
  79           contains:
  80             enum:
  81               - ti,dra7xx-phy-gmii-sel
  82               - ti,dm814-phy-gmii-sel
  83               - ti,am654-phy-gmii-sel
  84     then:
  85       properties:
  86         '#phy-cells':
  87           const: 1
  88           description: CPSW port number (starting from 1)
  89
  90   - if:
  91       not:
  92         properties:
  93           compatible:
  94             contains:
  95               enum:
  96                 - ti,j7200-cpsw5g-phy-gmii-sel
  97     then:
  98       properties:
  99         ti,qsgmii-main-ports: false
 100
 101   - if:
 102       properties:
 103         compatible:
 104           contains:
 105             enum:
 106               - ti,am3352-phy-gmii-sel
 107               - ti,am43xx-phy-gmii-sel
 108     then:
 109       properties:
 110         '#phy-cells':
 111           const: 2
 112           description: |
 113             - CPSW port number (starting from 1)
 114             - RMII refclk mode
 115
 116 required:
 117   - compatible
 118   - reg
 119   - '#phy-cells'
 120
 121 additionalProperties: false
 122
 123 examples:
 124   - |
 125     phy_gmii_sel: phy@650 {
 126         compatible = "ti,am3352-phy-gmii-sel";
 127         reg = <0x650 0x4>;
 128         #phy-cells = <2>;
 129     };