1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8m-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale IMX8M IOMUX Controller
10 - Peng Fan <peng.fan@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14 for common binding part and usage.
27 # Client device subnode's properties
32 Pinctrl node's client devices use subnodes for desired pin configuration.
33 Client device subnodes use below standard properties.
38 each entry consists of 6 integers and represents the mux and config
39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
40 mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
41 be found in <arch/arm64/boot/dts/freescale/imx8m[m,n,p,q]-pinfunc.h>.
42 The last integer CONFIG is the pad setting value like pull-up on this
43 pin. Please refer to i.MX8M Mini/Nano/Plus/Quad Reference Manual for
44 detailed CONFIG settings.
45 $ref: /schemas/types.yaml#/definitions/uint32-matrix
49 "mux_reg" indicates the offset of mux register.
51 "conf_reg" indicates the offset of pad configuration register.
53 "input_reg" indicates the offset of select input register.
55 "mux_val" indicates the mux value to be applied.
57 "input_val" indicates the select input value to be applied.
59 "pad_setting" indicates the pad configuration value to be
65 additionalProperties: false
74 additionalProperties: false
77 # Pinmux controller node
79 iomuxc: pinctrl@30330000 {
80 compatible = "fsl,imx8mm-iomuxc";
81 reg = <0x30330000 0x10000>;
83 pinctrl_uart2: uart2grp {
85 <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
86 <0x240 0x4A8 0x000 0x0 0x0 0x140>;