Bindings/pinctrl/qcom,ipq9574-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12
  13 description:
  14   Top Level Mode Multiplexer pin controller in Qualcomm IPQ9574 SoC.
  15
  16 properties:
  17   compatible:
  18     const: qcom,ipq9574-tlmm
  19
  20   reg:
  21     maxItems: 1
  22
  23   interrupts:
  24     maxItems: 1
  25
  26   interrupt-controller: true
  27   "#interrupt-cells": true
  28   gpio-controller: true
  29   "#gpio-cells": true
  30   gpio-ranges: true
  31   wakeup-parent: true
  32
  33   gpio-reserved-ranges:
  34     minItems: 1
  35     maxItems: 33
  36
  37   gpio-line-names:
  38     maxItems: 65
  39
  40 patternProperties:
  41   "-state$":
  42     oneOf:
  43       - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
  44       - patternProperties:
  45           "-pins$":
  46             $ref: "#/$defs/qcom-ipq9574-tlmm-state"
  47         additionalProperties: false
  48
  49 $defs:
  50   qcom-ipq9574-tlmm-state:
  51     type: object
  52     description:
  53       Pinctrl node's client devices use subnodes for desired pin configuration.
  54       Client device subnodes use below standard properties.
  55     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  56
  57     properties:
  58       pins:
  59         description:
  60           List of gpio pins affected by the properties specified in this
  61           subnode.
  62         items:
  63           pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
  64         minItems: 1
  65         maxItems: 8
  66
  67       function:
  68         description:
  69           Specify the alternative function to be configured for the specified
  70           pins.
  71
  72         enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
  73                 audio_pdm0, audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
  74                 blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
  75                 blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
  76                 blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
  77                 cri_trng1, cri_trng2, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
  78                 gcc_plltest, gcc_tlmm, gpio, mac, mdc, mdio, pcie0_clk, pcie0_wake,
  79                 pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, pcie3_clk, pcie3_wake,
  80                 prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, pta, pwm,
  81                 qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
  82                 qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
  83                 qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
  84                 qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
  85                 qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
  86                 rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
  87                 wci20, wci21, wsa_swrm ]
  88
  89       bias-pull-down: true
  90       bias-pull-up: true
  91       bias-disable: true
  92       drive-strength: true
  93       input-enable: true
  94       output-high: true
  95       output-low: true
  96
  97     required:
  98       - pins
  99
 100     additionalProperties: false
 101
 102 allOf:
 103   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
 104
 105 required:
 106   - compatible
 107   - reg
 108
 109 additionalProperties: false
 110
 111 examples:
 112   - |
 113     #include <dt-bindings/interrupt-controller/arm-gic.h>
 114     tlmm: pinctrl@1000000 {
 115         compatible = "qcom,ipq9574-tlmm";
 116         reg = <0x01000000 0x300000>;
 117         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 118         gpio-controller;
 119         #gpio-cells = <2>;
 120         interrupt-controller;
 121         #interrupt-cells = <2>;
 122         gpio-ranges = <&tlmm 0 0 65>;
 123
 124         uart2-state {
 125             pins = "gpio34", "gpio35";
 126             function = "blsp2_uart";
 127             drive-strength = <8>;
 128             bias-pull-down;
 129         };
 130     };