Bindings/pinctrl/qcom,mdm9615-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. MDM9615 TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11
  12 description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.
  13
  14 $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  15
  16 properties:
  17   compatible:
  18     const: qcom,mdm9615-pinctrl
  19
  20   reg:
  21     maxItems: 1
  22
  23   interrupts:
  24     maxItems: 1
  25
  26   interrupt-controller: true
  27   '#interrupt-cells': true
  28   gpio-controller: true
  29   '#gpio-cells': true
  30   gpio-ranges: true
  31
  32 required:
  33   - compatible
  34   - reg
  35
  36 additionalProperties: false
  37
  38 patternProperties:
  39   "-state$":
  40     oneOf:
  41       - $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
  42       - patternProperties:
  43           "-pins$":
  44             $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
  45         additionalProperties: false
  46
  47 $defs:
  48   qcom-mdm9615-pinctrl-state:
  49     type: object
  50     description:
  51       Pinctrl node's client devices use subnodes for desired pin configuration.
  52       Client device subnodes use below standard properties.
  53     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  54     unevaluatedProperties: false
  55
  56     properties:
  57       pins:
  58         description:
  59           List of gpio pins affected by the properties specified in this
  60           subnode.
  61         items:
  62           pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$"
  63         minItems: 1
  64         maxItems: 16
  65
  66       function:
  67         description:
  68           Specify the alternative function to be configured for the specified
  69           pins.
  70
  71         enum: [ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
  72                 sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, cdc_mclk, ]
  73
  74     required:
  75       - pins
  76
  77 examples:
  78   - |
  79     #include <dt-bindings/interrupt-controller/arm-gic.h>
  80     tlmm: pinctrl@1000000 {
  81       compatible = "qcom,mdm9615-pinctrl";
  82       reg = <0x01000000 0x300000>;
  83       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  84       gpio-controller;
  85       gpio-ranges = <&msmgpio 0 0 88>;
  86       #gpio-cells = <2>;
  87       interrupt-controller;
  88       #interrupt-cells = <2>;
  89
  90       gsbi3-state {
  91         pins = "gpio8", "gpio9", "gpio10", "gpio11";
  92         function = "gsbi3";
  93         drive-strength = <8>;
  94         bias-disable;
  95       };
  96
  97       gsbi5-i2c-state {
  98         sda-pins {
  99           pins = "gpio16";
 100           function = "gsbi5_i2c";
 101           drive-strength = <8>;
 102           bias-disable;
 103         };
 104
 105         scl-pins {
 106           pins = "gpio17";
 107           function = "gsbi5_i2c";
 108           drive-strength = <2>;
 109           bias-disable;
 110         };
 111       };
 112     };