Bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SC7280 SoC LPASS LPI TLMM
   8
   9 maintainers:
  10   - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
  14   (LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC.
  15
  16 properties:
  17   compatible:
  18     const: qcom,sc7280-lpass-lpi-pinctrl
  19
  20   qcom,adsp-bypass-mode:
  21     description:
  22       Tells ADSP is in bypass mode.
  23     type: boolean
  24
  25   reg:
  26     maxItems: 2
  27
  28   gpio-controller: true
  29
  30   "#gpio-cells":
  31     description: Specifying the pin number and flags, as defined in
  32       include/dt-bindings/gpio/gpio.h
  33     const: 2
  34
  35   gpio-ranges:
  36     maxItems: 1
  37
  38 patternProperties:
  39   "-state$":
  40     oneOf:
  41       - $ref: "#/$defs/qcom-sc7280-lpass-state"
  42       - patternProperties:
  43           "-pins$":
  44             $ref: "#/$defs/qcom-sc7280-lpass-state"
  45         additionalProperties: false
  46
  47 $defs:
  48   qcom-sc7280-lpass-state:
  49     type: object
  50     description:
  51       Pinctrl node's client devices use subnodes for desired pin configuration.
  52       Client device subnodes use below standard properties.
  53     $ref: "/schemas/pinctrl/pincfg-node.yaml"
  54
  55     properties:
  56       pins:
  57         description:
  58           List of gpio pins affected by the properties specified in this
  59           subnode.
  60         items:
  61           oneOf:
  62             - pattern: "^gpio([0-9]|[1-9][0-9])$"
  63         minItems: 1
  64         maxItems: 15
  65
  66       function:
  67         enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
  68                 qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
  69                 dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
  70                 i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
  71                 dmic3_data, i2s2_data ]
  72         description:
  73           Specify the alternative function to be configured for the specified
  74           pins.
  75
  76       drive-strength:
  77         enum: [2, 4, 6, 8, 10, 12, 14, 16]
  78         default: 2
  79         description:
  80           Selects the drive strength for the specified pins, in mA.
  81
  82       slew-rate:
  83         enum: [0, 1, 2, 3]
  84         default: 0
  85         description: |
  86             0: No adjustments
  87             1: Higher Slew rate (faster edges)
  88             2: Lower Slew rate (slower edges)
  89             3: Reserved (No adjustments)
  90
  91       bias-pull-down: true
  92       bias-pull-up: true
  93       bias-bus-hold: true
  94       bias-disable: true
  95       output-high: true
  96       output-low: true
  97
  98     required:
  99       - pins
 100       - function
 101
 102     additionalProperties: false
 103
 104 required:
 105   - compatible
 106   - reg
 107   - gpio-controller
 108   - "#gpio-cells"
 109   - gpio-ranges
 110
 111 additionalProperties: false
 112
 113 examples:
 114   - |
 115     lpass_tlmm: pinctrl@33c0000 {
 116         compatible = "qcom,sc7280-lpass-lpi-pinctrl";
 117         reg = <0x33c0000 0x20000>,
 118               <0x3550000 0x10000>;
 119         gpio-controller;
 120         #gpio-cells = <2>;
 121         gpio-ranges = <&lpass_tlmm 0 0 15>;
 122
 123         dmic01-state {
 124             dmic01-clk-pins {
 125                 pins = "gpio6";
 126                 function = "dmic1_clk";
 127             };
 128
 129             dmic01-clk-sleep-pins {
 130                 pins = "gpio6";
 131                 function = "dmic1_clk";
 132             };
 133         };
 134
 135         tx-swr-data-sleep-state {
 136             pins = "gpio1", "gpio2", "gpio14";
 137             function = "swr_tx_data";
 138         };
 139     };