Bindings/pinctrl/qcom,sdm845-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SDM845 TLMM pin controller
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12
  13 description:
  14   Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC.
  15
  16 allOf:
  17   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sdm845-pinctrl
  22
  23   reg:
  24     maxItems: 1
  25
  26   interrupts:
  27     maxItems: 1
  28
  29   interrupt-controller: true
  30   "#interrupt-cells": true
  31   gpio-controller: true
  32
  33   gpio-reserved-ranges:
  34     minItems: 1
  35     maxItems: 75
  36
  37   gpio-line-names:
  38     maxItems: 150
  39
  40   "#gpio-cells": true
  41   gpio-ranges: true
  42   wakeup-parent: true
  43
  44 patternProperties:
  45   "-state$":
  46     oneOf:
  47       - $ref: "#/$defs/qcom-sdm845-tlmm-state"
  48       - patternProperties:
  49           "-pins$":
  50             $ref: "#/$defs/qcom-sdm845-tlmm-state"
  51         additionalProperties: false
  52
  53   "-hog(-[0-9]+)?$":
  54     required:
  55       - gpio-hog
  56
  57 $defs:
  58   qcom-sdm845-tlmm-state:
  59     type: object
  60     description:
  61       Pinctrl node's client devices use subnodes for desired pin configuration.
  62       Client device subnodes use below standard properties.
  63     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  64     unevaluatedProperties: false
  65
  66     properties:
  67       pins:
  68         description:
  69           List of gpio pins affected by the properties specified in this
  70           subnode.
  71         items:
  72           oneOf:
  73             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
  74             - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
  75         minItems: 1
  76         maxItems: 36
  77
  78       function:
  79         description:
  80           Specify the alternative function to be configured for the specified
  81           pins.
  82         enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2,
  83                 atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13,
  84                 atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23,
  85                 audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
  86                 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
  87                 cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
  88                 ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
  89                 gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update,
  90                 lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
  91                 mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0,
  92                 pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
  93                 pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
  94                 qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0,
  95                 qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3,
  96                 qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
  97                 sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu,
  98                 spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
  99                 tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
 100                 tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
 101                 tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
 102                 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
 103                 uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
 104                 wlan1_adc1, wlan2_adc0, wlan2_adc1]
 105
 106     required:
 107       - pins
 108
 109 required:
 110   - compatible
 111   - reg
 112
 113 additionalProperties: false
 114
 115 examples:
 116   - |
 117     #include <dt-bindings/gpio/gpio.h>
 118     #include <dt-bindings/interrupt-controller/arm-gic.h>
 119
 120     pinctrl@3400000 {
 121         compatible = "qcom,sdm845-pinctrl";
 122         reg = <0x03400000 0xc00000>;
 123         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 124         gpio-controller;
 125         #gpio-cells = <2>;
 126         interrupt-controller;
 127         #interrupt-cells = <2>;
 128         gpio-ranges = <&tlmm 0 0 151>;
 129         wakeup-parent = <&pdc_intc>;
 130
 131         ap-suspend-l-hog {
 132             gpio-hog;
 133             gpios = <126 GPIO_ACTIVE_LOW>;
 134             output-low;
 135         };
 136
 137         cci0-default-state {
 138             pins = "gpio17", "gpio18";
 139             function = "cci_i2c";
 140
 141             bias-pull-up;
 142             drive-strength = <2>;
 143         };
 144
 145         cam0-default-state {
 146             rst-pins {
 147                 pins = "gpio9";
 148                 function = "gpio";
 149
 150                 drive-strength = <16>;
 151                 bias-disable;
 152             };
 153
 154             mclk0-pins {
 155                 pins = "gpio13";
 156                 function = "cam_mclk";
 157
 158                 drive-strength = <16>;
 159                 bias-disable;
 160             };
 161         };
 162     };