1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SM8250 TLMM block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Top Level Mode Multiplexer pin controller in the Qualcomm SM8250 SoC.
17 const: qcom,sm8250-pinctrl
29 interrupt-controller: true
30 "#interrupt-cells": true
46 - $ref: "#/$defs/qcom-sm8250-tlmm-state"
49 $ref: "#/$defs/qcom-sm8250-tlmm-state"
50 additionalProperties: false
53 qcom-sm8250-tlmm-state:
56 Pinctrl node's client devices use subnodes for desired pin configuration.
57 Client device subnodes use below standard properties.
58 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
63 List of gpio pins affected by the properties specified in this
67 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
68 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
74 Specify the alternative function to be configured for the specified
77 enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
78 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
79 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
80 ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
81 ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
82 mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
83 mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
84 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
85 pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
86 pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
87 qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
88 qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
89 qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
90 sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
91 tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
92 tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
93 tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
106 additionalProperties: false
109 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
116 additionalProperties: false
120 #include <dt-bindings/interrupt-controller/arm-gic.h>
122 compatible = "qcom,sm8250-pinctrl";
123 reg = <0x0f100000 0x300000>,
124 <0x0f500000 0x300000>,
125 <0x0f900000 0x300000>;
126 reg-names = "west", "south", "north";
127 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 gpio-ranges = <&tlmm 0 0 180>;
133 wakeup-parent = <&pdc>;