Bindings/spi/spi-sifive.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: SiFive SPI controller
   8
   9 maintainers:
  10   - Pragnesh Patel <pragnesh.patel@sifive.com>
  11   - Paul Walmsley  <paul.walmsley@sifive.com>
  12   - Palmer Dabbelt <palmer@sifive.com>
  13
  14 allOf:
  15   - $ref: "spi-controller.yaml#"
  16
  17 properties:
  18   compatible:
  19     items:
  20       - const: sifive,fu540-c000-spi
  21       - const: sifive,spi0
  22
  23     description:
  24       Should be "sifive,<chip>-spi" and "sifive,spi<version>".
  25       Supported compatible strings are -
  26       "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
  27       onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
  28       SPI v0 IP block with no chip integration tweaks.
  29       Please refer to sifive-blocks-ip-versioning.txt for details
  30
  31       SPI RTL that corresponds to the IP block version numbers can be found here -
  32       https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
  33
  34   reg:
  35     maxItems: 1
  36
  37     description:
  38       Physical base address and size of SPI registers map
  39       A second (optional) range can indicate memory mapped flash
  40
  41   interrupts:
  42     maxItems: 1
  43
  44   clocks:
  45     maxItems: 1
  46
  47     description:
  48       Must reference the frequency given to the controller
  49
  50   sifive,fifo-depth:
  51     description:
  52       Depth of hardware queues; defaults to 8
  53     allOf:
  54       - $ref: "/schemas/types.yaml#/definitions/uint32"
  55       - enum: [ 8 ]
  56       - default: 8
  57
  58   sifive,max-bits-per-word:
  59     description:
  60       Maximum bits per word; defaults to 8
  61     allOf:
  62       - $ref: "/schemas/types.yaml#/definitions/uint32"
  63       - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8 ]
  64       - default: 8
  65
  66 required:
  67   - compatible
  68   - reg
  69   - interrupts
  70   - clocks
  71
  72 examples:
  73   - |
  74     spi: spi@10040000 {
  75       compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  76       reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
  77       interrupt-parent = <&plic>;
  78       interrupts = <51>;
  79       clocks = <&tlclk>;
  80       #address-cells = <1>;
  81       #size-cells = <0>;
  82       sifive,fifo-depth = <8>;
  83       sifive,max-bits-per-word = <8>;
  84     };
  85
  86 ...