1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 # Copyright 2019 Linaro Ltd.
5 $id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: QCOM SoC Temperature Sensor (TSENS)
11 - Amit Kucheria <amitk@kernel.org>
14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15 three distinct major versions of the IP that is supported by a single driver.
16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17 everything before v1 when there was no versioning information.
22 - description: msm8960 TSENS based
28 - description: v0.1 of TSENS
35 - const: qcom,tsens-v0_1
37 - description: v1 of TSENS
43 - const: qcom,tsens-v1
45 - description: v2 of TSENS
64 - const: qcom,tsens-v2
66 - description: v2 of TSENS with combined interrupt
72 - description: TM registers
73 - description: SROT registers
88 Reference to an nvmem node for the calibration data
92 Reference to nvmem cells for the calibration mode, two calibration
93 bases and two cells per each sensor
94 # special case for msm8974 / apq8084
97 Reference to nvmem cells for the calibration mode, two calibration
98 bases and two cells per each sensor, main and backup copies, plus use_backup cell
113 - pattern: '^s[0-9]+_p1$'
114 - pattern: '^s[0-9]+_p2$'
115 - pattern: '^s[0-9]+_p1$'
116 - pattern: '^s[0-9]+_p2$'
117 - pattern: '^s[0-9]+_p1$'
118 - pattern: '^s[0-9]+_p2$'
119 - pattern: '^s[0-9]+_p1$'
120 - pattern: '^s[0-9]+_p2$'
121 - pattern: '^s[0-9]+_p1$'
122 - pattern: '^s[0-9]+_p2$'
123 - pattern: '^s[0-9]+_p1$'
124 - pattern: '^s[0-9]+_p2$'
125 - pattern: '^s[0-9]+_p1$'
126 - pattern: '^s[0-9]+_p2$'
127 - pattern: '^s[0-9]+_p1$'
128 - pattern: '^s[0-9]+_p2$'
129 - pattern: '^s[0-9]+_p1$'
130 - pattern: '^s[0-9]+_p2$'
131 - pattern: '^s[0-9]+_p1$'
132 - pattern: '^s[0-9]+_p2$'
133 - pattern: '^s[0-9]+_p1$'
134 - pattern: '^s[0-9]+_p2$'
135 - pattern: '^s[0-9]+_p1$'
136 - pattern: '^s[0-9]+_p2$'
137 - pattern: '^s[0-9]+_p1$'
138 - pattern: '^s[0-9]+_p2$'
139 - pattern: '^s[0-9]+_p1$'
140 - pattern: '^s[0-9]+_p2$'
141 - pattern: '^s[0-9]+_p1$'
142 - pattern: '^s[0-9]+_p2$'
143 - pattern: '^s[0-9]+_p1$'
144 - pattern: '^s[0-9]+_p2$'
145 # special case for msm8974 / apq8084
152 - const: base1_backup
153 - const: base2_backup
176 - const: s0_p1_backup
177 - const: s0_p2_backup
178 - const: s1_p1_backup
179 - const: s1_p2_backup
180 - const: s2_p1_backup
181 - const: s2_p2_backup
182 - const: s3_p1_backup
183 - const: s3_p2_backup
184 - const: s4_p1_backup
185 - const: s4_p2_backup
186 - const: s5_p1_backup
187 - const: s5_p2_backup
188 - const: s6_p1_backup
189 - const: s6_p2_backup
190 - const: s7_p1_backup
191 - const: s7_p2_backup
192 - const: s8_p1_backup
193 - const: s8_p2_backup
194 - const: s9_p1_backup
195 - const: s9_p2_backup
196 - const: s10_p1_backup
197 - const: s10_p2_backup
201 Number of sensors enabled on this platform
202 $ref: /schemas/types.yaml#/definitions/uint32
206 "#thermal-sensor-cells":
209 Number of cells required to uniquely identify the thermal sensors. Since
210 we have multiple sensors this is set to 1
216 - "#thermal-sensor-cells"
238 - description: Combined interrupt if upper or lower threshold crossed
254 - qcom,sc8280xp-tsens
267 - description: Combined interrupt if upper or lower threshold crossed
268 - description: Interrupt if critical threshold crossed
284 - description: Combined interrupt if upper, lower or critical thresholds crossed
303 additionalProperties: false
307 #include <dt-bindings/interrupt-controller/arm-gic.h>
308 // Example msm9860 based SoC (ipq8064):
309 gcc: clock-controller {
313 tsens: thermal-sensor {
314 compatible = "qcom,ipq8064-tsens";
316 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
317 nvmem-cell-names = "calib", "calib_backup";
318 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
319 interrupt-names = "uplow";
321 #qcom,sensors = <11>;
322 #thermal-sensor-cells = <1>;
327 #include <dt-bindings/interrupt-controller/arm-gic.h>
328 // Example 1 (new calbiration data: for pre v1 IP):
329 thermal-sensor@4a9000 {
330 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
331 reg = <0x4a9000 0x1000>, /* TM */
332 <0x4a8000 0x1000>; /* SROT */
334 nvmem-cells = <&tsens_mode>,
335 <&tsens_base1>, <&tsens_base2>,
336 <&tsens_s0_p1>, <&tsens_s0_p2>,
337 <&tsens_s1_p1>, <&tsens_s1_p2>,
338 <&tsens_s2_p1>, <&tsens_s2_p2>,
339 <&tsens_s4_p1>, <&tsens_s4_p2>,
340 <&tsens_s5_p1>, <&tsens_s5_p2>;
341 nvmem-cell-names = "mode",
349 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "uplow";
353 #thermal-sensor-cells = <1>;
357 #include <dt-bindings/interrupt-controller/arm-gic.h>
358 // Example 1 (legacy: for pre v1 IP):
359 tsens1: thermal-sensor@4a9000 {
360 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
361 reg = <0x4a9000 0x1000>, /* TM */
362 <0x4a8000 0x1000>; /* SROT */
364 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
365 nvmem-cell-names = "calib", "calib_sel";
367 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "uplow";
371 #thermal-sensor-cells = <1>;
375 #include <dt-bindings/interrupt-controller/arm-gic.h>
376 // Example 2 (for any platform containing v1 of the TSENS IP):
377 tsens2: thermal-sensor@4a9000 {
378 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
379 reg = <0x004a9000 0x1000>, /* TM */
380 <0x004a8000 0x1000>; /* SROT */
382 nvmem-cells = <&tsens_caldata>;
383 nvmem-cell-names = "calib";
385 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
386 interrupt-names = "uplow";
388 #qcom,sensors = <10>;
389 #thermal-sensor-cells = <1>;
393 #include <dt-bindings/interrupt-controller/arm-gic.h>
394 // Example 3 (for any platform containing v2 of the TSENS IP):
395 tsens3: thermal-sensor@c263000 {
396 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
397 reg = <0xc263000 0x1ff>,
400 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "uplow", "critical";
404 #qcom,sensors = <13>;
405 #thermal-sensor-cells = <1>;
409 #include <dt-bindings/interrupt-controller/arm-gic.h>
410 // Example 4 (for any IPQ8074 based SoC-s):
411 tsens4: thermal-sensor@4a9000 {
412 compatible = "qcom,ipq8074-tsens";
413 reg = <0x4a9000 0x1000>,
416 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
417 interrupt-names = "combined";
419 #qcom,sensors = <16>;
420 #thermal-sensor-cells = <1>;