1 /* BFD back-end for Hitachi Super-H COFF binaries.
2 Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <sac@cygnus.com>.
5 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7 This file is part of BFD, the Binary File Descriptor library.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
28 #include "coff/internal.h"
31 /* Internal functions. */
32 static bfd_reloc_status_type sh_reloc
33 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
34 static long get_symbol_value PARAMS ((asymbol *));
35 static boolean sh_relax_section
36 PARAMS ((bfd *, asection *, struct bfd_link_info *, boolean *));
37 static boolean sh_relax_delete_bytes
38 PARAMS ((bfd *, asection *, bfd_vma, int));
39 static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
40 static boolean sh_align_loads
41 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *, boolean *));
42 static boolean sh_swap_insns
43 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
44 static boolean sh_relocate_section
45 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
46 struct internal_reloc *, struct internal_syment *, asection **));
47 static bfd_byte *sh_coff_get_relocated_section_contents
48 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
49 bfd_byte *, boolean, asymbol **));
51 /* Default section alignment to 2**4. */
52 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (4)
54 /* Generate long file names. */
55 #define COFF_LONG_FILENAMES
57 /* The supported relocations. There are a lot of relocations defined
58 in coff/internal.h which we do not expect to ever see. */
59 static reloc_howto_type sh_coff_howtos[] =
64 { 3 }, /* R_SH_PCREL8 */
65 { 4 }, /* R_SH_PCREL16 */
66 { 5 }, /* R_SH_HIGH8 */
67 { 6 }, /* R_SH_IMM24 */
68 { 7 }, /* R_SH_LOW16 */
70 { 9 }, /* R_SH_PCDISP8BY4 */
72 HOWTO (R_SH_PCDISP8BY2, /* type */
74 1, /* size (0 = byte, 1 = short, 2 = long) */
76 true, /* pc_relative */
78 complain_overflow_signed, /* complain_on_overflow */
79 sh_reloc, /* special_function */
80 "r_pcdisp8by2", /* name */
81 true, /* partial_inplace */
84 true), /* pcrel_offset */
86 { 11 }, /* R_SH_PCDISP8 */
88 HOWTO (R_SH_PCDISP, /* type */
90 1, /* size (0 = byte, 1 = short, 2 = long) */
92 true, /* pc_relative */
94 complain_overflow_signed, /* complain_on_overflow */
95 sh_reloc, /* special_function */
96 "r_pcdisp12by2", /* name */
97 true, /* partial_inplace */
100 true), /* pcrel_offset */
104 HOWTO (R_SH_IMM32, /* type */
106 2, /* size (0 = byte, 1 = short, 2 = long) */
108 false, /* pc_relative */
110 complain_overflow_bitfield, /* complain_on_overflow */
111 sh_reloc, /* special_function */
112 "r_imm32", /* name */
113 true, /* partial_inplace */
114 0xffffffff, /* src_mask */
115 0xffffffff, /* dst_mask */
116 false), /* pcrel_offset */
119 { 16 }, /* R_SH_IMM8 */
120 { 17 }, /* R_SH_IMM8BY2 */
121 { 18 }, /* R_SH_IMM8BY4 */
122 { 19 }, /* R_SH_IMM4 */
123 { 20 }, /* R_SH_IMM4BY2 */
124 { 21 }, /* R_SH_IMM4BY4 */
126 HOWTO (R_SH_PCRELIMM8BY2, /* type */
128 1, /* size (0 = byte, 1 = short, 2 = long) */
130 true, /* pc_relative */
132 complain_overflow_unsigned, /* complain_on_overflow */
133 sh_reloc, /* special_function */
134 "r_pcrelimm8by2", /* name */
135 true, /* partial_inplace */
138 true), /* pcrel_offset */
140 HOWTO (R_SH_PCRELIMM8BY4, /* type */
142 1, /* size (0 = byte, 1 = short, 2 = long) */
144 true, /* pc_relative */
146 complain_overflow_unsigned, /* complain_on_overflow */
147 sh_reloc, /* special_function */
148 "r_pcrelimm8by4", /* name */
149 true, /* partial_inplace */
152 true), /* pcrel_offset */
154 HOWTO (R_SH_IMM16, /* type */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
158 false, /* pc_relative */
160 complain_overflow_bitfield, /* complain_on_overflow */
161 sh_reloc, /* special_function */
162 "r_imm16", /* name */
163 true, /* partial_inplace */
164 0xffff, /* src_mask */
165 0xffff, /* dst_mask */
166 false), /* pcrel_offset */
168 HOWTO (R_SH_SWITCH16, /* type */
170 1, /* size (0 = byte, 1 = short, 2 = long) */
172 false, /* pc_relative */
174 complain_overflow_bitfield, /* complain_on_overflow */
175 sh_reloc, /* special_function */
176 "r_switch16", /* name */
177 true, /* partial_inplace */
178 0xffff, /* src_mask */
179 0xffff, /* dst_mask */
180 false), /* pcrel_offset */
182 HOWTO (R_SH_SWITCH32, /* type */
184 2, /* size (0 = byte, 1 = short, 2 = long) */
186 false, /* pc_relative */
188 complain_overflow_bitfield, /* complain_on_overflow */
189 sh_reloc, /* special_function */
190 "r_switch32", /* name */
191 true, /* partial_inplace */
192 0xffffffff, /* src_mask */
193 0xffffffff, /* dst_mask */
194 false), /* pcrel_offset */
196 HOWTO (R_SH_USES, /* type */
198 1, /* size (0 = byte, 1 = short, 2 = long) */
200 false, /* pc_relative */
202 complain_overflow_bitfield, /* complain_on_overflow */
203 sh_reloc, /* special_function */
205 true, /* partial_inplace */
206 0xffff, /* src_mask */
207 0xffff, /* dst_mask */
208 false), /* pcrel_offset */
210 HOWTO (R_SH_COUNT, /* type */
212 2, /* size (0 = byte, 1 = short, 2 = long) */
214 false, /* pc_relative */
216 complain_overflow_bitfield, /* complain_on_overflow */
217 sh_reloc, /* special_function */
218 "r_count", /* name */
219 true, /* partial_inplace */
220 0xffffffff, /* src_mask */
221 0xffffffff, /* dst_mask */
222 false), /* pcrel_offset */
224 HOWTO (R_SH_ALIGN, /* type */
226 2, /* size (0 = byte, 1 = short, 2 = long) */
228 false, /* pc_relative */
230 complain_overflow_bitfield, /* complain_on_overflow */
231 sh_reloc, /* special_function */
232 "r_align", /* name */
233 true, /* partial_inplace */
234 0xffffffff, /* src_mask */
235 0xffffffff, /* dst_mask */
236 false), /* pcrel_offset */
238 HOWTO (R_SH_CODE, /* type */
240 2, /* size (0 = byte, 1 = short, 2 = long) */
242 false, /* pc_relative */
244 complain_overflow_bitfield, /* complain_on_overflow */
245 sh_reloc, /* special_function */
247 true, /* partial_inplace */
248 0xffffffff, /* src_mask */
249 0xffffffff, /* dst_mask */
250 false), /* pcrel_offset */
252 HOWTO (R_SH_DATA, /* type */
254 2, /* size (0 = byte, 1 = short, 2 = long) */
256 false, /* pc_relative */
258 complain_overflow_bitfield, /* complain_on_overflow */
259 sh_reloc, /* special_function */
261 true, /* partial_inplace */
262 0xffffffff, /* src_mask */
263 0xffffffff, /* dst_mask */
264 false), /* pcrel_offset */
266 HOWTO (R_SH_LABEL, /* type */
268 2, /* size (0 = byte, 1 = short, 2 = long) */
270 false, /* pc_relative */
272 complain_overflow_bitfield, /* complain_on_overflow */
273 sh_reloc, /* special_function */
274 "r_label", /* name */
275 true, /* partial_inplace */
276 0xffffffff, /* src_mask */
277 0xffffffff, /* dst_mask */
278 false) /* pcrel_offset */
281 #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
283 /* Check for a bad magic number. */
284 #define BADMAG(x) SHBADMAG(x)
286 /* Customize coffcode.h (this is not currently used). */
289 /* FIXME: This should not be set here. */
290 #define __A_MAGIC_SET__
292 /* Swap the r_offset field in and out. */
293 #define SWAP_IN_RELOC_OFFSET bfd_h_get_32
294 #define SWAP_OUT_RELOC_OFFSET bfd_h_put_32
296 /* Swap out extra information in the reloc structure. */
297 #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
300 dst->r_stuff[0] = 'S'; \
301 dst->r_stuff[1] = 'C'; \
305 /* Get the value of a symbol, when performing a relocation. */
308 get_symbol_value (symbol)
313 if (bfd_is_com_section (symbol->section))
316 relocation = (symbol->value +
317 symbol->section->output_section->vma +
318 symbol->section->output_offset);
323 /* This macro is used in coffcode.h to get the howto corresponding to
324 an internal reloc. */
326 #define RTYPE2HOWTO(relent, internal) \
328 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
329 ? &sh_coff_howtos[(internal)->r_type] \
330 : (reloc_howto_type *) NULL))
332 /* This is the same as the macro in coffcode.h, except that it copies
333 r_offset into reloc_entry->addend for some relocs. */
334 #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
336 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
337 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
338 coffsym = (obj_symbols (abfd) \
339 + (cache_ptr->sym_ptr_ptr - symbols)); \
341 coffsym = coff_symbol_from (abfd, ptr); \
342 if (coffsym != (coff_symbol_type *) NULL \
343 && coffsym->native->u.syment.n_scnum == 0) \
344 cache_ptr->addend = 0; \
345 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
346 && ptr->section != (asection *) NULL) \
347 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
349 cache_ptr->addend = 0; \
350 if ((reloc).r_type == R_SH_SWITCH16 \
351 || (reloc).r_type == R_SH_SWITCH32 \
352 || (reloc).r_type == R_SH_USES \
353 || (reloc).r_type == R_SH_COUNT \
354 || (reloc).r_type == R_SH_ALIGN) \
355 cache_ptr->addend = (reloc).r_offset; \
358 /* This is the howto function for the SH relocations. */
360 static bfd_reloc_status_type
361 sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
364 arelent *reloc_entry;
367 asection *input_section;
369 char **error_message;
373 unsigned short r_type;
374 bfd_vma addr = reloc_entry->address;
375 bfd_byte *hit_data = addr + (bfd_byte *) data;
377 r_type = reloc_entry->howto->type;
379 if (output_bfd != NULL)
381 /* Partial linking--do nothing. */
382 reloc_entry->address += input_section->output_offset;
386 /* Almost all relocs have to do with relaxing. If any work must be
387 done for them, it has been done in sh_relax_section. */
388 if (r_type != R_SH_IMM32
389 && (r_type != R_SH_PCDISP
390 || (symbol_in->flags & BSF_LOCAL) != 0))
393 if (symbol_in != NULL
394 && bfd_is_und_section (symbol_in->section))
395 return bfd_reloc_undefined;
397 sym_value = get_symbol_value (symbol_in);
402 insn = bfd_get_32 (abfd, hit_data);
403 insn += sym_value + reloc_entry->addend;
404 bfd_put_32 (abfd, insn, hit_data);
407 insn = bfd_get_16 (abfd, hit_data);
408 sym_value += reloc_entry->addend;
409 sym_value -= (input_section->output_section->vma
410 + input_section->output_offset
413 sym_value += (insn & 0xfff) << 1;
416 insn = (insn & 0xf000) | (sym_value & 0xfff);
417 bfd_put_16 (abfd, insn, hit_data);
418 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
419 return bfd_reloc_overflow;
429 /* We can do relaxing. */
430 #define coff_bfd_relax_section sh_relax_section
432 /* We use the special COFF backend linker. */
433 #define coff_relocate_section sh_relocate_section
435 /* When relaxing, we need to use special code to get the relocated
437 #define coff_bfd_get_relocated_section_contents \
438 sh_coff_get_relocated_section_contents
440 #include "coffcode.h"
442 /* This function handles relaxing on the SH.
444 Function calls on the SH look like this:
453 The compiler and assembler will cooperate to create R_SH_USES
454 relocs on the jsr instructions. The r_offset field of the
455 R_SH_USES reloc is the PC relative offset to the instruction which
456 loads the register (the r_offset field is computed as though it
457 were a jump instruction, so the offset value is actually from four
458 bytes past the instruction). The linker can use this reloc to
459 determine just which function is being called, and thus decide
460 whether it is possible to replace the jsr with a bsr.
462 If multiple function calls are all based on a single register load
463 (i.e., the same function is called multiple times), the compiler
464 guarantees that each function call will have an R_SH_USES reloc.
465 Therefore, if the linker is able to convert each R_SH_USES reloc
466 which refers to that address, it can safely eliminate the register
469 When the assembler creates an R_SH_USES reloc, it examines it to
470 determine which address is being loaded (L1 in the above example).
471 It then counts the number of references to that address, and
472 creates an R_SH_COUNT reloc at that address. The r_offset field of
473 the R_SH_COUNT reloc will be the number of references. If the
474 linker is able to eliminate a register load, it can use the
475 R_SH_COUNT reloc to see whether it can also eliminate the function
478 SH relaxing also handles another, unrelated, matter. On the SH, if
479 a load or store instruction is not aligned on a four byte boundary,
480 the memory cycle interferes with the 32 bit instruction fetch,
481 causing a one cycle bubble in the pipeline. Therefore, we try to
482 align load and store instructions on four byte boundaries if we
483 can, by swapping them with one of the adjacent instructions. */
486 sh_relax_section (abfd, sec, link_info, again)
489 struct bfd_link_info *link_info;
492 struct internal_reloc *internal_relocs;
493 struct internal_reloc *free_relocs = NULL;
495 struct internal_reloc *irel, *irelend;
496 bfd_byte *contents = NULL;
497 bfd_byte *free_contents = NULL;
501 if (link_info->relocateable
502 || (sec->flags & SEC_RELOC) == 0
503 || sec->reloc_count == 0)
506 /* If this is the first time we have been called for this section,
507 initialize the cooked size. */
508 if (sec->_cooked_size == 0)
509 sec->_cooked_size = sec->_raw_size;
511 internal_relocs = (_bfd_coff_read_internal_relocs
512 (abfd, sec, link_info->keep_memory,
513 (bfd_byte *) NULL, false,
514 (struct internal_reloc *) NULL));
515 if (internal_relocs == NULL)
517 if (! link_info->keep_memory)
518 free_relocs = internal_relocs;
522 irelend = internal_relocs + sec->reloc_count;
523 for (irel = internal_relocs; irel < irelend; irel++)
525 bfd_vma laddr, paddr, symval;
527 struct internal_reloc *irelfn, *irelscan, *irelcount;
528 struct internal_syment sym;
531 if (irel->r_type == R_SH_CODE)
534 if (irel->r_type != R_SH_USES)
537 /* Get the section contents. */
538 if (contents == NULL)
540 if (coff_section_data (abfd, sec) != NULL
541 && coff_section_data (abfd, sec)->contents != NULL)
542 contents = coff_section_data (abfd, sec)->contents;
545 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
546 if (contents == NULL)
548 free_contents = contents;
550 if (! bfd_get_section_contents (abfd, sec, contents,
551 (file_ptr) 0, sec->_raw_size))
556 /* The r_offset field of the R_SH_USES reloc will point us to
557 the register load. The 4 is because the r_offset field is
558 computed as though it were a jump offset, which are based
559 from 4 bytes after the jump instruction. */
560 laddr = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
561 if (laddr >= sec->_raw_size)
563 (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset",
564 bfd_get_filename (abfd),
565 (unsigned long) irel->r_vaddr);
568 insn = bfd_get_16 (abfd, contents + laddr);
570 /* If the instruction is not mov.l NN,rN, we don't know what to
572 if ((insn & 0xf000) != 0xd000)
574 ((*_bfd_error_handler)
575 ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
576 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr, insn));
580 /* Get the address from which the register is being loaded. The
581 displacement in the mov.l instruction is quadrupled. It is a
582 displacement from four bytes after the movl instruction, but,
583 before adding in the PC address, two least significant bits
584 of the PC are cleared. We assume that the section is aligned
585 on a four byte boundary. */
588 paddr += (laddr + 4) &~ 3;
589 if (paddr >= sec->_raw_size)
591 ((*_bfd_error_handler)
592 ("%s: 0x%lx: warning: bad R_SH_USES load offset",
593 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
597 /* Get the reloc for the address from which the register is
598 being loaded. This reloc will tell us which function is
599 actually being called. */
601 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
602 if (irelfn->r_vaddr == paddr
603 && irelfn->r_type == R_SH_IMM32)
605 if (irelfn >= irelend)
607 ((*_bfd_error_handler)
608 ("%s: 0x%lx: warning: could not find expected reloc",
609 bfd_get_filename (abfd), (unsigned long) paddr));
613 /* Get the value of the symbol referred to by the reloc. */
614 if (! _bfd_coff_get_external_symbols (abfd))
616 bfd_coff_swap_sym_in (abfd,
617 ((bfd_byte *) obj_coff_external_syms (abfd)
619 * bfd_coff_symesz (abfd))),
621 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
623 ((*_bfd_error_handler)
624 ("%s: 0x%lx: warning: symbol in unexpected section",
625 bfd_get_filename (abfd), (unsigned long) paddr));
629 if (sym.n_sclass != C_EXT)
631 symval = (sym.n_value
633 + sec->output_section->vma
634 + sec->output_offset);
638 struct coff_link_hash_entry *h;
640 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
641 BFD_ASSERT (h != NULL);
642 if (h->root.type != bfd_link_hash_defined
643 && h->root.type != bfd_link_hash_defweak)
645 /* This appears to be a reference to an undefined
646 symbol. Just ignore it--it will be caught by the
647 regular reloc processing. */
651 symval = (h->root.u.def.value
652 + h->root.u.def.section->output_section->vma
653 + h->root.u.def.section->output_offset);
656 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
658 /* See if this function call can be shortened. */
662 + sec->output_section->vma
665 if (foff < -0x1000 || foff >= 0x1000)
667 /* After all that work, we can't shorten this function call. */
671 /* Shorten the function call. */
673 /* For simplicity of coding, we are going to modify the section
674 contents, the section relocs, and the BFD symbol table. We
675 must tell the rest of the code not to free up this
676 information. It would be possible to instead create a table
677 of changes which have to be made, as is done in coff-mips.c;
678 that would be more work, but would require less memory when
679 the linker is run. */
681 if (coff_section_data (abfd, sec) == NULL)
684 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
685 if (sec->used_by_bfd == NULL)
689 coff_section_data (abfd, sec)->relocs = internal_relocs;
690 coff_section_data (abfd, sec)->keep_relocs = true;
693 coff_section_data (abfd, sec)->contents = contents;
694 coff_section_data (abfd, sec)->keep_contents = true;
695 free_contents = NULL;
697 obj_coff_keep_syms (abfd) = true;
699 /* Replace the jsr with a bsr. */
701 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
702 replace the jsr with a bsr. */
703 irel->r_type = R_SH_PCDISP;
704 irel->r_symndx = irelfn->r_symndx;
705 if (sym.n_sclass != C_EXT)
707 /* If this needs to be changed because of future relaxing,
708 it will be handled here like other internal PCDISP
711 0xb000 | ((foff >> 1) & 0xfff),
712 contents + irel->r_vaddr - sec->vma);
716 /* We can't fully resolve this yet, because the external
717 symbol value may be changed by future relaxing. We let
718 the final link phase handle it. */
719 bfd_put_16 (abfd, 0xb000, contents + irel->r_vaddr - sec->vma);
722 /* See if there is another R_SH_USES reloc referring to the same
724 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
725 if (irelscan->r_type == R_SH_USES
726 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
728 if (irelscan < irelend)
730 /* Some other function call depends upon this register load,
731 and we have not yet converted that function call.
732 Indeed, we may never be able to convert it. There is
733 nothing else we can do at this point. */
737 /* Look for a R_SH_COUNT reloc on the location where the
738 function address is stored. Do this before deleting any
739 bytes, to avoid confusion about the address. */
740 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
741 if (irelcount->r_vaddr == paddr
742 && irelcount->r_type == R_SH_COUNT)
745 /* Delete the register load. */
746 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
749 /* That will change things, so, just in case it permits some
750 other function call to come within range, we should relax
751 again. Note that this is not required, and it may be slow. */
754 /* Now check whether we got a COUNT reloc. */
755 if (irelcount >= irelend)
757 ((*_bfd_error_handler)
758 ("%s: 0x%lx: warning: could not find expected COUNT reloc",
759 bfd_get_filename (abfd), (unsigned long) paddr));
763 /* The number of uses is stored in the r_offset field. We've
765 if (irelcount->r_offset == 0)
767 ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count",
768 bfd_get_filename (abfd),
769 (unsigned long) paddr));
773 --irelcount->r_offset;
775 /* If there are no more uses, we can delete the address. Reload
776 the address from irelfn, in case it was changed by the
777 previous call to sh_relax_delete_bytes. */
778 if (irelcount->r_offset == 0)
780 if (! sh_relax_delete_bytes (abfd, sec,
781 irelfn->r_vaddr - sec->vma, 4))
785 /* We've done all we can with that function call. */
788 /* Look for load and store instructions that we can align on four
794 /* Get the section contents. */
795 if (contents == NULL)
797 if (coff_section_data (abfd, sec) != NULL
798 && coff_section_data (abfd, sec)->contents != NULL)
799 contents = coff_section_data (abfd, sec)->contents;
802 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
803 if (contents == NULL)
805 free_contents = contents;
807 if (! bfd_get_section_contents (abfd, sec, contents,
808 (file_ptr) 0, sec->_raw_size))
813 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
818 if (coff_section_data (abfd, sec) == NULL)
821 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
822 if (sec->used_by_bfd == NULL)
826 coff_section_data (abfd, sec)->relocs = internal_relocs;
827 coff_section_data (abfd, sec)->keep_relocs = true;
830 coff_section_data (abfd, sec)->contents = contents;
831 coff_section_data (abfd, sec)->keep_contents = true;
832 free_contents = NULL;
834 obj_coff_keep_syms (abfd) = true;
838 if (free_relocs != NULL)
844 if (free_contents != NULL)
846 if (! link_info->keep_memory)
847 free (free_contents);
850 /* Cache the section contents for coff_link_input_bfd. */
851 if (coff_section_data (abfd, sec) == NULL)
854 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
855 if (sec->used_by_bfd == NULL)
857 coff_section_data (abfd, sec)->relocs = NULL;
859 coff_section_data (abfd, sec)->contents = contents;
866 if (free_relocs != NULL)
868 if (free_contents != NULL)
869 free (free_contents);
873 /* Delete some bytes from a section while relaxing. */
876 sh_relax_delete_bytes (abfd, sec, addr, count)
883 struct internal_reloc *irel, *irelend;
884 struct internal_reloc *irelalign;
886 bfd_byte *esym, *esymend;
887 bfd_size_type symesz;
888 struct coff_link_hash_entry **sym_hash;
891 contents = coff_section_data (abfd, sec)->contents;
893 /* The deletion must stop at the next ALIGN reloc for an aligment
894 power larger than the number of bytes we are deleting. */
897 toaddr = sec->_cooked_size;
899 irel = coff_section_data (abfd, sec)->relocs;
900 irelend = irel + sec->reloc_count;
901 for (; irel < irelend; irel++)
903 if (irel->r_type == R_SH_ALIGN
904 && irel->r_vaddr - sec->vma > addr
905 && count < (1 << irel->r_offset))
908 toaddr = irel->r_vaddr - sec->vma;
913 /* Actually delete the bytes. */
914 memmove (contents + addr, contents + addr + count, toaddr - addr - count);
915 if (irelalign == NULL)
916 sec->_cooked_size -= count;
921 #define NOP_OPCODE (0x0009)
923 BFD_ASSERT ((count & 1) == 0);
924 for (i = 0; i < count; i += 2)
925 bfd_put_16 (abfd, NOP_OPCODE, contents + toaddr - count + i);
928 /* Adjust all the relocs. */
929 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
931 bfd_vma nraddr, start, stop;
933 struct internal_syment sym;
934 int off, adjust, oinsn;
938 /* Get the new reloc address. */
939 nraddr = irel->r_vaddr - sec->vma;
940 if ((irel->r_vaddr - sec->vma > addr
941 && irel->r_vaddr - sec->vma < toaddr)
942 || (irel->r_type == R_SH_ALIGN
943 && irel->r_vaddr - sec->vma == toaddr))
946 /* See if this reloc was for the bytes we have deleted, in which
947 case we no longer care about it. Don't delete relocs which
948 represent addresses, though. */
949 if (irel->r_vaddr - sec->vma >= addr
950 && irel->r_vaddr - sec->vma < addr + count
951 && irel->r_type != R_SH_ALIGN
952 && irel->r_type != R_SH_CODE
953 && irel->r_type != R_SH_DATA)
954 irel->r_type = R_SH_UNUSED;
956 /* If this is a PC relative reloc, see if the range it covers
957 includes the bytes we have deleted. */
958 switch (irel->r_type)
963 case R_SH_PCDISP8BY2:
965 case R_SH_PCRELIMM8BY2:
966 case R_SH_PCRELIMM8BY4:
967 start = irel->r_vaddr - sec->vma;
968 insn = bfd_get_16 (abfd, contents + nraddr);
972 switch (irel->r_type)
979 /* If this reloc is against a symbol defined in this
980 section, and the symbol will not be adjusted below, we
981 must check the addend to see it will put the value in
982 range to be adjusted, and hence must be changed. */
983 bfd_coff_swap_sym_in (abfd,
984 ((bfd_byte *) obj_coff_external_syms (abfd)
986 * bfd_coff_symesz (abfd))),
988 if (sym.n_sclass != C_EXT
989 && sym.n_scnum == sec->target_index
990 && ((bfd_vma) sym.n_value <= addr
991 || (bfd_vma) sym.n_value >= toaddr))
995 val = bfd_get_32 (abfd, contents + nraddr);
997 if (val >= addr && val < toaddr)
998 bfd_put_32 (abfd, val - count, contents + nraddr);
1000 start = stop = addr;
1003 case R_SH_PCDISP8BY2:
1007 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1011 bfd_coff_swap_sym_in (abfd,
1012 ((bfd_byte *) obj_coff_external_syms (abfd)
1014 * bfd_coff_symesz (abfd))),
1016 if (sym.n_sclass == C_EXT)
1017 start = stop = addr;
1023 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1027 case R_SH_PCRELIMM8BY2:
1029 stop = start + 4 + off * 2;
1032 case R_SH_PCRELIMM8BY4:
1034 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1039 /* These relocs types represent
1041 The r_offset field holds the difference between the reloc
1042 address and L1. That is the start of the reloc, and
1043 adding in the contents gives us the top. We must adjust
1044 both the r_offset field and the section contents. */
1046 start = irel->r_vaddr - sec->vma;
1047 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1051 && (stop <= addr || stop >= toaddr))
1052 irel->r_offset += count;
1053 else if (stop > addr
1055 && (start <= addr || start >= toaddr))
1056 irel->r_offset -= count;
1060 if (irel->r_type == R_SH_SWITCH16)
1061 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1063 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1064 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1069 start = irel->r_vaddr - sec->vma;
1070 stop = (bfd_vma) ((bfd_signed_vma) start
1071 + (long) irel->r_offset
1078 && (stop <= addr || stop >= toaddr))
1080 else if (stop > addr
1082 && (start <= addr || start >= toaddr))
1091 switch (irel->r_type)
1097 case R_SH_PCDISP8BY2:
1098 case R_SH_PCRELIMM8BY2:
1100 if ((oinsn & 0xff00) != (insn & 0xff00))
1102 bfd_put_16 (abfd, insn, contents + nraddr);
1107 if ((oinsn & 0xf000) != (insn & 0xf000))
1109 bfd_put_16 (abfd, insn, contents + nraddr);
1112 case R_SH_PCRELIMM8BY4:
1113 BFD_ASSERT (adjust == count || count >= 4);
1118 if ((irel->r_vaddr & 3) == 0)
1121 if ((oinsn & 0xff00) != (insn & 0xff00))
1123 bfd_put_16 (abfd, insn, contents + nraddr);
1128 if (voff < - 0x8000 || voff >= 0x8000)
1130 bfd_put_signed_16 (abfd, voff, contents + nraddr);
1135 bfd_put_signed_32 (abfd, voff, contents + nraddr);
1139 irel->r_offset += adjust;
1145 ((*_bfd_error_handler)
1146 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
1147 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
1148 bfd_set_error (bfd_error_bad_value);
1153 irel->r_vaddr = nraddr + sec->vma;
1156 /* Look through all the other sections. If there contain any IMM32
1157 relocs against internal symbols which we are not going to adjust
1158 below, we may need to adjust the addends. */
1159 for (o = abfd->sections; o != NULL; o = o->next)
1161 struct internal_reloc *internal_relocs;
1162 struct internal_reloc *irelscan, *irelscanend;
1163 bfd_byte *ocontents;
1166 || (o->flags & SEC_RELOC) == 0
1167 || o->reloc_count == 0)
1170 /* We always cache the relocs. Perhaps, if info->keep_memory is
1171 false, we should free them, if we are permitted to, when we
1172 leave sh_coff_relax_section. */
1173 internal_relocs = (_bfd_coff_read_internal_relocs
1174 (abfd, o, true, (bfd_byte *) NULL, false,
1175 (struct internal_reloc *) NULL));
1176 if (internal_relocs == NULL)
1180 irelscanend = internal_relocs + o->reloc_count;
1181 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1183 struct internal_syment sym;
1185 if (irelscan->r_type != R_SH_IMM32)
1188 bfd_coff_swap_sym_in (abfd,
1189 ((bfd_byte *) obj_coff_external_syms (abfd)
1190 + (irelscan->r_symndx
1191 * bfd_coff_symesz (abfd))),
1193 if (sym.n_sclass != C_EXT
1194 && sym.n_scnum == sec->target_index
1195 && ((bfd_vma) sym.n_value <= addr
1196 || (bfd_vma) sym.n_value >= toaddr))
1200 if (ocontents == NULL)
1202 if (coff_section_data (abfd, o)->contents != NULL)
1203 ocontents = coff_section_data (abfd, o)->contents;
1206 /* We always cache the section contents.
1207 Perhaps, if info->keep_memory is false, we
1208 should free them, if we are permitted to,
1209 when we leave sh_coff_relax_section. */
1210 ocontents = (bfd_byte *) bfd_malloc (o->_raw_size);
1211 if (ocontents == NULL)
1213 if (! bfd_get_section_contents (abfd, o, ocontents,
1217 coff_section_data (abfd, o)->contents = ocontents;
1221 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1223 if (val >= addr && val < toaddr)
1224 bfd_put_32 (abfd, val - count,
1225 ocontents + irelscan->r_vaddr - o->vma);
1227 coff_section_data (abfd, o)->keep_contents = true;
1232 /* Adjusting the internal symbols will not work if something has
1233 already retrieved the generic symbols. It would be possible to
1234 make this work by adjusting the generic symbols at the same time.
1235 However, this case should not arise in normal usage. */
1236 if (obj_symbols (abfd) != NULL
1237 || obj_raw_syments (abfd) != NULL)
1239 ((*_bfd_error_handler)
1240 ("%s: fatal: generic symbols retrieved before relaxing",
1241 bfd_get_filename (abfd)));
1242 bfd_set_error (bfd_error_invalid_operation);
1246 /* Adjust all the symbols. */
1247 sym_hash = obj_coff_sym_hashes (abfd);
1248 symesz = bfd_coff_symesz (abfd);
1249 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1250 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1251 while (esym < esymend)
1253 struct internal_syment isym;
1255 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1257 if (isym.n_scnum == sec->target_index
1258 && (bfd_vma) isym.n_value > addr
1259 && (bfd_vma) isym.n_value < toaddr)
1261 isym.n_value -= count;
1263 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1265 if (*sym_hash != NULL)
1267 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1268 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1269 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1270 && (*sym_hash)->root.u.def.value < toaddr);
1271 (*sym_hash)->root.u.def.value -= count;
1275 esym += (isym.n_numaux + 1) * symesz;
1276 sym_hash += isym.n_numaux + 1;
1279 /* See if we can move the ALIGN reloc forward. We have adjusted
1280 r_vaddr for it already. */
1281 if (irelalign != NULL)
1283 bfd_vma alignto, alignaddr;
1285 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1286 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1287 1 << irelalign->r_offset);
1288 if (alignto != alignaddr)
1290 /* Tail recursion. */
1291 return sh_relax_delete_bytes (abfd, sec, alignaddr,
1292 alignto - alignaddr);
1299 /* This is yet another version of the SH opcode table, used to rapidly
1300 get information about a particular instruction. */
1302 /* The opcode map is represented by an array of these structures. The
1303 array is indexed by the high order four bits in the instruction. */
1305 struct sh_major_opcode
1307 /* A pointer to the instruction list. This is an array which
1308 contains all the instructions with this major opcode. */
1309 const struct sh_minor_opcode *minor_opcodes;
1310 /* The number of elements in minor_opcodes. */
1311 unsigned short count;
1314 /* This structure holds information for a set of SH opcodes. The
1315 instruction code is anded with the mask value, and the resulting
1316 value is used to search the order opcode list. */
1318 struct sh_minor_opcode
1320 /* The sorted opcode list. */
1321 const struct sh_opcode *opcodes;
1322 /* The number of elements in opcodes. */
1323 unsigned short count;
1324 /* The mask value to use when searching the opcode list. */
1325 unsigned short mask;
1328 /* This structure holds information for an SH instruction. An array
1329 of these structures is sorted in order by opcode. */
1333 /* The code for this instruction, after it has been anded with the
1334 mask value in the sh_major_opcode structure. */
1335 unsigned short opcode;
1336 /* Flags for this instruction. */
1337 unsigned short flags;
1340 /* Flag which appear in the sh_opcode structure. */
1342 /* This instruction loads a value from memory. */
1345 /* This instruction stores a value to memory. */
1348 /* This instruction is a branch. */
1349 #define BRANCH (0x4)
1351 /* This instruction has a delay slot. */
1354 /* This instruction uses the value in the register in the field at
1355 mask 0x0f00 of the instruction. */
1356 #define USES1 (0x10)
1358 /* This instruction uses the value in the register in the field at
1359 mask 0x00f0 of the instruction. */
1360 #define USES2 (0x20)
1362 /* This instruction uses the value in register 0. */
1363 #define USESR0 (0x40)
1365 /* This instruction sets the value in the register in the field at
1366 mask 0x0f00 of the instruction. */
1367 #define SETS1 (0x80)
1369 /* This instruction sets the value in the register in the field at
1370 mask 0x00f0 of the instruction. */
1371 #define SETS2 (0x100)
1373 /* This instruction sets register 0. */
1374 #define SETSR0 (0x200)
1376 /* This instruction sets a special register. */
1377 #define SETSSP (0x400)
1379 /* This instruction uses a special register. */
1380 #define USESSP (0x800)
1382 /* This instruction uses the floating point register in the field at
1383 mask 0x0f00 of the instruction. */
1384 #define USESF1 (0x1000)
1386 /* This instruction uses the floating point register in the field at
1387 mask 0x00f0 of the instruction. */
1388 #define USESF2 (0x2000)
1390 /* This instruction uses floating point register 0. */
1391 #define USESF0 (0x4000)
1393 /* This instruction sets the floating point register in the field at
1394 mask 0x0f00 of the instruction. */
1395 #define SETSF1 (0x8000)
1397 static boolean sh_insn_uses_reg
1398 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1399 static boolean sh_insn_uses_freg
1400 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1401 static boolean sh_insns_conflict
1402 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1403 const struct sh_opcode *));
1404 static boolean sh_load_use
1405 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1406 const struct sh_opcode *));
1408 /* The opcode maps. */
1410 #define MAP(a) a, sizeof a / sizeof a[0]
1412 static const struct sh_opcode sh_opcode00[] =
1414 { 0x0008, SETSSP }, /* clrt */
1415 { 0x0009, 0 }, /* nop */
1416 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1417 { 0x0018, SETSSP }, /* sett */
1418 { 0x0019, SETSSP }, /* div0u */
1419 { 0x001b, 0 }, /* sleep */
1420 { 0x0028, SETSSP }, /* clrmac */
1421 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1422 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1423 { 0x0048, SETSSP }, /* clrs */
1424 { 0x0058, SETSSP } /* sets */
1427 static const struct sh_opcode sh_opcode01[] =
1429 { 0x0002, SETS1 | USESSP }, /* stc sr,rn */
1430 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1431 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
1432 { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */
1433 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
1434 { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */
1435 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1436 { 0x0029, SETS1 | USESSP }, /* movt rn */
1437 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
1438 { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */
1439 { 0x0042, SETS1 | USESSP }, /* stc spc,rn */
1440 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1441 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn */
1442 { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */
1443 { 0x0083, LOAD | USES1 }, /* pref @rn */
1444 { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */
1445 { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */
1446 { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */
1447 { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */
1448 { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */
1449 { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */
1450 { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */
1453 static const struct sh_opcode sh_opcode02[] =
1455 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1456 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1457 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1458 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1459 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1460 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1461 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1462 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1465 static const struct sh_minor_opcode sh_opcode0[] =
1467 { MAP (sh_opcode00), 0xffff },
1468 { MAP (sh_opcode01), 0xf0ff },
1469 { MAP (sh_opcode02), 0xf00f }
1472 static const struct sh_opcode sh_opcode10[] =
1474 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1477 static const struct sh_minor_opcode sh_opcode1[] =
1479 { MAP (sh_opcode10), 0xf000 }
1482 static const struct sh_opcode sh_opcode20[] =
1484 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1485 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1486 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1487 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1488 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1489 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1490 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1491 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1492 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1493 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1494 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1495 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1496 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1497 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1498 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1501 static const struct sh_minor_opcode sh_opcode2[] =
1503 { MAP (sh_opcode20), 0xf00f }
1506 static const struct sh_opcode sh_opcode30[] =
1508 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1509 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1510 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1511 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1512 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1513 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1514 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1515 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1516 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1517 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1518 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1519 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1520 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1521 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1524 static const struct sh_minor_opcode sh_opcode3[] =
1526 { MAP (sh_opcode30), 0xf00f }
1529 static const struct sh_opcode sh_opcode40[] =
1531 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1532 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1533 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
1534 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */
1535 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1536 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1537 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
1538 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */
1539 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1540 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1541 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1542 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
1543 { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */
1544 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1545 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1546 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
1547 { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */
1548 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1549 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
1550 { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */
1551 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1552 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1553 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1554 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
1555 { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */
1556 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1557 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1558 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
1559 { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */
1560 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1561 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1562 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
1563 { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */
1564 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1565 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1566 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1567 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
1568 { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */
1569 { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */
1570 { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */
1571 { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */
1572 { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */
1573 { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */
1574 { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */
1575 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1576 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1577 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1578 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr,@-rn */
1579 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr */
1580 { 0x406a, SETSSP | USES1 } /* lds rm,fpscr */
1583 static const struct sh_opcode sh_opcode41[] =
1585 { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l rx_bank,@-rn */
1586 { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rx_bank */
1587 { 0x408e, SETSSP | USES1 } /* ldc rm,rx_bank */
1590 static const struct sh_opcode sh_opcode42[] =
1592 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1593 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1594 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1597 static const struct sh_minor_opcode sh_opcode4[] =
1599 { MAP (sh_opcode40), 0xf0ff },
1600 { MAP (sh_opcode41), 0xf08f },
1601 { MAP (sh_opcode42), 0xf00f }
1604 static const struct sh_opcode sh_opcode50[] =
1606 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1609 static const struct sh_minor_opcode sh_opcode5[] =
1611 { MAP (sh_opcode50), 0xf000 }
1614 static const struct sh_opcode sh_opcode60[] =
1616 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1617 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1618 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1619 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1620 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1621 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1622 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1623 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1624 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1625 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1626 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1627 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1628 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1629 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1630 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1631 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1634 static const struct sh_minor_opcode sh_opcode6[] =
1636 { MAP (sh_opcode60), 0xf00f }
1639 static const struct sh_opcode sh_opcode70[] =
1641 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1644 static const struct sh_minor_opcode sh_opcode7[] =
1646 { MAP (sh_opcode70), 0xf000 }
1649 static const struct sh_opcode sh_opcode80[] =
1651 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1652 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
1653 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1654 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1655 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1656 { 0x8900, BRANCH | USESSP }, /* bt label */
1657 { 0x8b00, BRANCH | USESSP }, /* bf label */
1658 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
1659 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1662 static const struct sh_minor_opcode sh_opcode8[] =
1664 { MAP (sh_opcode80), 0xff00 }
1667 static const struct sh_opcode sh_opcode90[] =
1669 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1672 static const struct sh_minor_opcode sh_opcode9[] =
1674 { MAP (sh_opcode90), 0xf000 }
1677 static const struct sh_opcode sh_opcodea0[] =
1679 { 0xa000, BRANCH | DELAY } /* bra label */
1682 static const struct sh_minor_opcode sh_opcodea[] =
1684 { MAP (sh_opcodea0), 0xf000 }
1687 static const struct sh_opcode sh_opcodeb0[] =
1689 { 0xb000, BRANCH | DELAY } /* bsr label */
1692 static const struct sh_minor_opcode sh_opcodeb[] =
1694 { MAP (sh_opcodeb0), 0xf000 }
1697 static const struct sh_opcode sh_opcodec0[] =
1699 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1700 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1701 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1702 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1703 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1704 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1705 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1706 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1707 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1708 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1709 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1710 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1711 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1712 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1713 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1714 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1717 static const struct sh_minor_opcode sh_opcodec[] =
1719 { MAP (sh_opcodec0), 0xff00 }
1722 static const struct sh_opcode sh_opcoded0[] =
1724 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1727 static const struct sh_minor_opcode sh_opcoded[] =
1729 { MAP (sh_opcoded0), 0xf000 }
1732 static const struct sh_opcode sh_opcodee0[] =
1734 { 0xe000, SETS1 } /* mov #imm,rn */
1737 static const struct sh_minor_opcode sh_opcodee[] =
1739 { MAP (sh_opcodee0), 0xf000 }
1742 static const struct sh_opcode sh_opcodef0[] =
1744 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1745 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1746 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1747 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1748 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1749 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1750 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1751 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1752 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1753 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1754 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1755 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1756 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1757 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1760 static const struct sh_opcode sh_opcodef1[] =
1762 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1763 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1764 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1765 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1766 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1767 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1768 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1769 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1770 { 0xf08d, SETSF1 }, /* fldi0 fn */
1771 { 0xf09d, SETSF1 } /* fldi1 fn */
1774 static const struct sh_minor_opcode sh_opcodef[] =
1776 { MAP (sh_opcodef0), 0xf00f },
1777 { MAP (sh_opcodef1), 0xf0ff }
1780 static const struct sh_major_opcode sh_opcodes[] =
1782 { MAP (sh_opcode0) },
1783 { MAP (sh_opcode1) },
1784 { MAP (sh_opcode2) },
1785 { MAP (sh_opcode3) },
1786 { MAP (sh_opcode4) },
1787 { MAP (sh_opcode5) },
1788 { MAP (sh_opcode6) },
1789 { MAP (sh_opcode7) },
1790 { MAP (sh_opcode8) },
1791 { MAP (sh_opcode9) },
1792 { MAP (sh_opcodea) },
1793 { MAP (sh_opcodeb) },
1794 { MAP (sh_opcodec) },
1795 { MAP (sh_opcoded) },
1796 { MAP (sh_opcodee) },
1797 { MAP (sh_opcodef) }
1800 /* Given an instruction, return a pointer to the corresponding
1801 sh_opcode structure. Return NULL if the instruction is not
1804 static const struct sh_opcode *
1808 const struct sh_major_opcode *maj;
1809 const struct sh_minor_opcode *min, *minend;
1811 maj = &sh_opcodes[(insn & 0xf000) >> 12];
1812 min = maj->minor_opcodes;
1813 minend = min + maj->count;
1814 for (; min < minend; min++)
1817 const struct sh_opcode *op, *opend;
1819 l = insn & min->mask;
1821 opend = op + min->count;
1823 /* Since the opcodes tables are sorted, we could use a binary
1824 search here if the count were above some cutoff value. */
1825 for (; op < opend; op++)
1826 if (op->opcode == l)
1833 /* See whether an instruction uses a general purpose register. */
1836 sh_insn_uses_reg (insn, op, reg)
1838 const struct sh_opcode *op;
1845 if ((f & USES1) != 0
1846 && ((insn & 0x0f00) >> 8) == reg)
1848 if ((f & USES2) != 0
1849 && ((insn & 0x00f0) >> 4) == reg)
1851 if ((f & USESR0) != 0
1858 /* See whether an instruction uses a floating point register. */
1861 sh_insn_uses_freg (insn, op, freg)
1863 const struct sh_opcode *op;
1870 if ((f & USESF1) != 0
1871 && ((insn & 0x0f00) >> 8) == freg)
1873 if ((f & USESF2) != 0
1874 && ((insn & 0x00f0) >> 4) == freg)
1876 if ((f & USESF0) != 0
1883 /* See whether instructions I1 and I2 conflict, assuming I1 comes
1884 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
1885 This should return true if there is a conflict, or false if the
1886 instructions can be swapped safely. */
1889 sh_insns_conflict (i1, op1, i2, op2)
1891 const struct sh_opcode *op1;
1893 const struct sh_opcode *op2;
1895 unsigned int f1, f2;
1900 if ((f1 & (BRANCH | DELAY)) != 0
1901 || (f2 & (BRANCH | DELAY)) != 0)
1904 if ((f1 & SETSSP) != 0 && (f2 & USESSP) != 0)
1906 if ((f2 & SETSSP) != 0 && (f1 & USESSP) != 0)
1909 if ((f1 & SETS1) != 0
1910 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
1912 if ((f1 & SETS2) != 0
1913 && sh_insn_uses_reg (i2, op2, (i1 & 0x00f0) >> 4))
1915 if ((f1 & SETSR0) != 0
1916 && sh_insn_uses_reg (i2, op2, 0))
1918 if ((f1 & SETSF1) != 0
1919 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
1922 if ((f2 & SETS1) != 0
1923 && sh_insn_uses_reg (i1, op1, (i2 & 0x0f00) >> 8))
1925 if ((f2 & SETS2) != 0
1926 && sh_insn_uses_reg (i1, op1, (i2 & 0x00f0) >> 4))
1928 if ((f2 & SETSR0) != 0
1929 && sh_insn_uses_reg (i1, op1, 0))
1931 if ((f2 & SETSF1) != 0
1932 && sh_insn_uses_freg (i1, op1, (i2 & 0x0f00) >> 8))
1935 /* The instructions do not conflict. */
1939 /* I1 is a load instruction, and I2 is some other instruction. Return
1940 true if I1 loads a register which I2 uses. */
1943 sh_load_use (i1, op1, i2, op2)
1945 const struct sh_opcode *op1;
1947 const struct sh_opcode *op2;
1953 if ((f1 & LOAD) == 0)
1956 /* If both SETS1 and SETSSP are set, that means a load to a special
1957 register using postincrement addressing mode, which we don't care
1959 if ((f1 & SETS1) != 0
1960 && (f1 & SETSSP) == 0
1961 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
1964 if ((f1 & SETSR0) != 0
1965 && sh_insn_uses_reg (i2, op2, 0))
1968 if ((f1 & SETSF1) != 0
1969 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
1975 /* Try to align loads and stores within a span of memory. This is
1976 called by both the ELF and the COFF sh targets. ABFD and SEC are
1977 the BFD and section we are examining. CONTENTS is the contents of
1978 the section. SWAP is the routine to call to swap two instructions.
1979 RELOCS is a pointer to the internal relocation information, to be
1980 passed to SWAP. PLABEL is a pointer to the current label in a
1981 sorted list of labels; LABEL_END is the end of the list. START and
1982 STOP are the range of memory to examine. If a swap is made,
1983 *PSWAPPED is set to true. */
1986 _bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
1987 plabel, label_end, start, stop, pswapped)
1991 boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
2001 /* Instructions should be aligned on 2 byte boundaries. */
2002 if ((start & 1) == 1)
2005 /* Now look through the unaligned addresses. */
2009 for (; i < stop; i += 4)
2012 const struct sh_opcode *op;
2013 unsigned int prev_insn = 0;
2014 const struct sh_opcode *prev_op = NULL;
2016 insn = bfd_get_16 (abfd, contents + i);
2017 op = sh_insn_info (insn);
2019 || (op->flags & (LOAD | STORE)) == 0)
2022 /* This is a load or store which is not on a four byte boundary. */
2024 while (*plabel < label_end && **plabel < i)
2029 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2030 prev_op = sh_insn_info (prev_insn);
2032 /* If the load/store instruction is in a delay slot, we
2035 || (prev_op->flags & DELAY) != 0)
2039 && (*plabel >= label_end || **plabel != i)
2041 && (prev_op->flags & (LOAD | STORE)) == 0
2042 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2046 /* The load/store instruction does not have a label, and
2047 there is a previous instruction; PREV_INSN is not
2048 itself a load/store instruction, and PREV_INSN and
2049 INSN do not conflict. */
2055 unsigned int prev2_insn;
2056 const struct sh_opcode *prev2_op;
2058 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2059 prev2_op = sh_insn_info (prev2_insn);
2061 /* If the instruction before PREV_INSN has a delay
2062 slot--that is, PREV_INSN is in a delay slot--we
2064 if (prev2_op == NULL
2065 || (prev2_op->flags & DELAY) != 0)
2068 /* If the instruction before PREV_INSN is a load,
2069 and it sets a register which INSN uses, then
2070 putting INSN immediately after PREV_INSN will
2071 cause a pipeline bubble, so there is no point to
2074 && (prev2_op->flags & LOAD) != 0
2075 && sh_load_use (prev2_insn, prev2_op, insn, op))
2081 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
2088 while (*plabel < label_end && **plabel < i + 2)
2092 && (*plabel >= label_end || **plabel != i + 2))
2094 unsigned int next_insn;
2095 const struct sh_opcode *next_op;
2097 /* There is an instruction after the load/store
2098 instruction, and it does not have a label. */
2099 next_insn = bfd_get_16 (abfd, contents + i + 2);
2100 next_op = sh_insn_info (next_insn);
2102 && (next_op->flags & (LOAD | STORE)) == 0
2103 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2107 /* NEXT_INSN is not itself a load/store instruction,
2108 and it does not conflict with INSN. */
2112 /* If PREV_INSN is a load, and it sets a register
2113 which NEXT_INSN uses, then putting NEXT_INSN
2114 immediately after PREV_INSN will cause a pipeline
2115 bubble, so there is no reason to make this swap. */
2117 && (prev_op->flags & LOAD) != 0
2118 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
2121 /* If INSN is a load, and it sets a register which
2122 the insn after NEXT_INSN uses, then doing the
2123 swap will cause a pipeline bubble, so there is no
2124 reason to make the swap. However, if the insn
2125 after NEXT_INSN is itself a load or store
2126 instruction, then it is misaligned, so
2127 optimistically hope that it will be swapped
2128 itself, and just live with the pipeline bubble if
2132 && (op->flags & LOAD) != 0)
2134 unsigned int next2_insn;
2135 const struct sh_opcode *next2_op;
2137 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2138 next2_op = sh_insn_info (next2_insn);
2139 if ((next2_op->flags & (LOAD | STORE)) == 0
2140 && sh_load_use (insn, op, next2_insn, next2_op))
2146 if (! (*swap) (abfd, sec, relocs, contents, i))
2158 /* Look for loads and stores which we can align to four byte
2159 boundaries. See the longer comment above sh_relax_section for why
2160 this is desirable. This sets *PSWAPPED if some instruction was
2164 sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2167 struct internal_reloc *internal_relocs;
2171 struct internal_reloc *irel, *irelend;
2172 bfd_vma *labels = NULL;
2173 bfd_vma *label, *label_end;
2177 irelend = internal_relocs + sec->reloc_count;
2179 /* Get all the addresses with labels on them. */
2180 labels = (bfd_vma *) bfd_malloc (sec->reloc_count * sizeof (bfd_vma));
2184 for (irel = internal_relocs; irel < irelend; irel++)
2186 if (irel->r_type == R_SH_LABEL)
2188 *label_end = irel->r_vaddr - sec->vma;
2193 /* Note that the assembler currently always outputs relocs in
2194 address order. If that ever changes, this code will need to sort
2195 the label values and the relocs. */
2199 for (irel = internal_relocs; irel < irelend; irel++)
2201 bfd_vma start, stop;
2203 if (irel->r_type != R_SH_CODE)
2206 start = irel->r_vaddr - sec->vma;
2208 for (irel++; irel < irelend; irel++)
2209 if (irel->r_type == R_SH_DATA)
2212 stop = irel->r_vaddr - sec->vma;
2214 stop = sec->_cooked_size;
2216 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2217 (PTR) internal_relocs, &label,
2218 label_end, start, stop, pswapped))
2232 /* Swap two SH instructions. */
2235 sh_swap_insns (abfd, sec, relocs, contents, addr)
2242 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2243 unsigned short i1, i2;
2244 struct internal_reloc *irel, *irelend;
2246 /* Swap the instructions themselves. */
2247 i1 = bfd_get_16 (abfd, contents + addr);
2248 i2 = bfd_get_16 (abfd, contents + addr + 2);
2249 bfd_put_16 (abfd, i2, contents + addr);
2250 bfd_put_16 (abfd, i1, contents + addr + 2);
2252 /* Adjust all reloc addresses. */
2253 irelend = internal_relocs + sec->reloc_count;
2254 for (irel = internal_relocs; irel < irelend; irel++)
2258 /* There are a few special types of relocs that we don't want to
2259 adjust. These relocs do not apply to the instruction itself,
2260 but are only associated with the address. */
2261 type = irel->r_type;
2262 if (type == R_SH_ALIGN
2263 || type == R_SH_CODE
2264 || type == R_SH_DATA
2265 || type == R_SH_LABEL)
2268 /* If an R_SH_USES reloc points to one of the addresses being
2269 swapped, we must adjust it. It would be incorrect to do this
2270 for a jump, though, since we want to execute both
2271 instructions after the jump. (We have avoided swapping
2272 around a label, so the jump will not wind up executing an
2273 instruction it shouldn't). */
2274 if (type == R_SH_USES)
2278 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2280 irel->r_offset += 2;
2281 else if (off == addr + 2)
2282 irel->r_offset -= 2;
2285 if (irel->r_vaddr - sec->vma == addr)
2290 else if (irel->r_vaddr - sec->vma == addr + 2)
2301 unsigned short insn, oinsn;
2304 loc = contents + irel->r_vaddr - sec->vma;
2311 case R_SH_PCDISP8BY2:
2312 case R_SH_PCRELIMM8BY2:
2313 insn = bfd_get_16 (abfd, loc);
2316 if ((oinsn & 0xff00) != (insn & 0xff00))
2318 bfd_put_16 (abfd, insn, loc);
2322 insn = bfd_get_16 (abfd, loc);
2325 if ((oinsn & 0xf000) != (insn & 0xf000))
2327 bfd_put_16 (abfd, insn, loc);
2330 case R_SH_PCRELIMM8BY4:
2331 /* This reloc ignores the least significant 3 bits of
2332 the program counter before adding in the offset.
2333 This means that if ADDR is at an even address, the
2334 swap will not affect the offset. If ADDR is an at an
2335 odd address, then the instruction will be crossing a
2336 four byte boundary, and must be adjusted. */
2337 if ((addr & 3) != 0)
2339 insn = bfd_get_16 (abfd, loc);
2342 if ((oinsn & 0xff00) != (insn & 0xff00))
2344 bfd_put_16 (abfd, insn, loc);
2352 ((*_bfd_error_handler)
2353 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
2354 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
2355 bfd_set_error (bfd_error_bad_value);
2364 /* This is a modification of _bfd_coff_generic_relocate_section, which
2365 will handle SH relaxing. */
2368 sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2369 relocs, syms, sections)
2371 struct bfd_link_info *info;
2373 asection *input_section;
2375 struct internal_reloc *relocs;
2376 struct internal_syment *syms;
2377 asection **sections;
2379 struct internal_reloc *rel;
2380 struct internal_reloc *relend;
2383 relend = rel + input_section->reloc_count;
2384 for (; rel < relend; rel++)
2387 struct coff_link_hash_entry *h;
2388 struct internal_syment *sym;
2391 reloc_howto_type *howto;
2392 bfd_reloc_status_type rstat;
2394 /* Almost all relocs have to do with relaxing. If any work must
2395 be done for them, it has been done in sh_relax_section. */
2396 if (rel->r_type != R_SH_IMM32
2397 && rel->r_type != R_SH_PCDISP)
2400 symndx = rel->r_symndx;
2409 if (symndx < 0 || symndx >= obj_raw_syment_count (input_bfd))
2411 (*_bfd_error_handler)
2412 ("%s: illegal symbol index %ld in relocs",
2413 bfd_get_filename (input_bfd), symndx);
2414 bfd_set_error (bfd_error_bad_value);
2417 h = obj_coff_sym_hashes (input_bfd)[symndx];
2418 sym = syms + symndx;
2421 if (sym != NULL && sym->n_scnum != 0)
2422 addend = - sym->n_value;
2426 if (rel->r_type == R_SH_PCDISP)
2429 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2432 howto = &sh_coff_howtos[rel->r_type];
2436 bfd_set_error (bfd_error_bad_value);
2446 /* There is nothing to do for an internal PCDISP reloc. */
2447 if (rel->r_type == R_SH_PCDISP)
2452 sec = bfd_abs_section_ptr;
2457 sec = sections[symndx];
2458 val = (sec->output_section->vma
2459 + sec->output_offset
2466 if (h->root.type == bfd_link_hash_defined
2467 || h->root.type == bfd_link_hash_defweak)
2471 sec = h->root.u.def.section;
2472 val = (h->root.u.def.value
2473 + sec->output_section->vma
2474 + sec->output_offset);
2476 else if (! info->relocateable)
2478 if (! ((*info->callbacks->undefined_symbol)
2479 (info, h->root.root.string, input_bfd, input_section,
2480 rel->r_vaddr - input_section->vma)))
2485 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2487 rel->r_vaddr - input_section->vma,
2496 case bfd_reloc_overflow:
2499 char buf[SYMNMLEN + 1];
2504 name = h->root.root.string;
2505 else if (sym->_n._n_n._n_zeroes == 0
2506 && sym->_n._n_n._n_offset != 0)
2507 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2510 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2511 buf[SYMNMLEN] = '\0';
2515 if (! ((*info->callbacks->reloc_overflow)
2516 (info, name, howto->name, (bfd_vma) 0, input_bfd,
2517 input_section, rel->r_vaddr - input_section->vma)))
2526 /* This is a version of bfd_generic_get_relocated_section_contents
2527 which uses sh_relocate_section. */
2530 sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
2531 data, relocateable, symbols)
2533 struct bfd_link_info *link_info;
2534 struct bfd_link_order *link_order;
2536 boolean relocateable;
2539 asection *input_section = link_order->u.indirect.section;
2540 bfd *input_bfd = input_section->owner;
2541 asection **sections = NULL;
2542 struct internal_reloc *internal_relocs = NULL;
2543 struct internal_syment *internal_syms = NULL;
2545 /* We only need to handle the case of relaxing, or of having a
2546 particular set of section contents, specially. */
2548 || coff_section_data (input_bfd, input_section) == NULL
2549 || coff_section_data (input_bfd, input_section)->contents == NULL)
2550 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2555 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
2556 input_section->_raw_size);
2558 if ((input_section->flags & SEC_RELOC) != 0
2559 && input_section->reloc_count > 0)
2561 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2562 bfd_byte *esym, *esymend;
2563 struct internal_syment *isymp;
2566 if (! _bfd_coff_get_external_symbols (input_bfd))
2569 internal_relocs = (_bfd_coff_read_internal_relocs
2570 (input_bfd, input_section, false, (bfd_byte *) NULL,
2571 false, (struct internal_reloc *) NULL));
2572 if (internal_relocs == NULL)
2575 internal_syms = ((struct internal_syment *)
2576 bfd_malloc (obj_raw_syment_count (input_bfd)
2577 * sizeof (struct internal_syment)));
2578 if (internal_syms == NULL)
2581 sections = (asection **) bfd_malloc (obj_raw_syment_count (input_bfd)
2582 * sizeof (asection *));
2583 if (sections == NULL)
2586 isymp = internal_syms;
2588 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
2589 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
2590 while (esym < esymend)
2592 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
2594 if (isymp->n_scnum != 0)
2595 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
2598 if (isymp->n_value == 0)
2599 *secpp = bfd_und_section_ptr;
2601 *secpp = bfd_com_section_ptr;
2604 esym += (isymp->n_numaux + 1) * symesz;
2605 secpp += isymp->n_numaux + 1;
2606 isymp += isymp->n_numaux + 1;
2609 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
2610 input_section, data, internal_relocs,
2611 internal_syms, sections))
2616 free (internal_syms);
2617 internal_syms = NULL;
2618 free (internal_relocs);
2619 internal_relocs = NULL;
2625 if (internal_relocs != NULL)
2626 free (internal_relocs);
2627 if (internal_syms != NULL)
2628 free (internal_syms);
2629 if (sections != NULL)
2634 /* The target vectors. */
2636 const bfd_target shcoff_vec =
2638 "coff-sh", /* name */
2639 bfd_target_coff_flavour,
2640 BFD_ENDIAN_BIG, /* data byte order is big */
2641 BFD_ENDIAN_BIG, /* header byte order is big */
2643 (HAS_RELOC | EXEC_P | /* object flags */
2644 HAS_LINENO | HAS_DEBUG |
2645 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
2647 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
2648 '_', /* leading symbol underscore */
2649 '/', /* ar_pad_char */
2650 15, /* ar_max_namelen */
2651 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2652 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2653 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
2654 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2655 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2656 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
2658 {_bfd_dummy_target, coff_object_p, /* bfd_check_format */
2659 bfd_generic_archive_p, _bfd_dummy_target},
2660 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
2662 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
2663 _bfd_write_archive_contents, bfd_false},
2665 BFD_JUMP_TABLE_GENERIC (coff),
2666 BFD_JUMP_TABLE_COPY (coff),
2667 BFD_JUMP_TABLE_CORE (_bfd_nocore),
2668 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
2669 BFD_JUMP_TABLE_SYMBOLS (coff),
2670 BFD_JUMP_TABLE_RELOCS (coff),
2671 BFD_JUMP_TABLE_WRITE (coff),
2672 BFD_JUMP_TABLE_LINK (coff),
2673 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
2678 const bfd_target shlcoff_vec =
2680 "coff-shl", /* name */
2681 bfd_target_coff_flavour,
2682 BFD_ENDIAN_LITTLE, /* data byte order is little */
2683 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
2685 (HAS_RELOC | EXEC_P | /* object flags */
2686 HAS_LINENO | HAS_DEBUG |
2687 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
2689 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
2690 '_', /* leading symbol underscore */
2691 '/', /* ar_pad_char */
2692 15, /* ar_max_namelen */
2693 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2694 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2695 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
2696 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2697 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2698 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
2700 {_bfd_dummy_target, coff_object_p, /* bfd_check_format */
2701 bfd_generic_archive_p, _bfd_dummy_target},
2702 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
2704 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
2705 _bfd_write_archive_contents, bfd_false},
2707 BFD_JUMP_TABLE_GENERIC (coff),
2708 BFD_JUMP_TABLE_COPY (coff),
2709 BFD_JUMP_TABLE_CORE (_bfd_nocore),
2710 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
2711 BFD_JUMP_TABLE_SYMBOLS (coff),
2712 BFD_JUMP_TABLE_RELOCS (coff),
2713 BFD_JUMP_TABLE_WRITE (coff),
2714 BFD_JUMP_TABLE_LINK (coff),
2715 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),