1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency = 0;
100 /* Types of processor to assemble for. */
102 #if defined __XSCALE__
103 #define CPU_DEFAULT ARM_ARCH_XSCALE
105 #if defined __thumb__
106 #define CPU_DEFAULT ARM_ARCH_V5T
113 # define FPU_DEFAULT FPU_ARCH_FPA
114 # elif defined (TE_NetBSD)
116 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
118 /* Legacy a.out format. */
119 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
121 # elif defined (TE_VXWORKS)
122 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
124 /* For backwards compatibility, default to FPA. */
125 # define FPU_DEFAULT FPU_ARCH_FPA
127 #endif /* ifndef FPU_DEFAULT */
129 #define streq(a, b) (strcmp (a, b) == 0)
131 static arm_feature_set cpu_variant;
132 static arm_feature_set arm_arch_used;
133 static arm_feature_set thumb_arch_used;
135 /* Flags stored in private area of BFD structure. */
136 static int uses_apcs_26 = FALSE;
137 static int atpcs = FALSE;
138 static int support_interwork = FALSE;
139 static int uses_apcs_float = FALSE;
140 static int pic_code = FALSE;
142 /* Variables that we set while parsing command-line options. Once all
143 options have been read we re-process these values to set the real
145 static const arm_feature_set *legacy_cpu = NULL;
146 static const arm_feature_set *legacy_fpu = NULL;
148 static const arm_feature_set *mcpu_cpu_opt = NULL;
149 static const arm_feature_set *mcpu_fpu_opt = NULL;
150 static const arm_feature_set *march_cpu_opt = NULL;
151 static const arm_feature_set *march_fpu_opt = NULL;
152 static const arm_feature_set *mfpu_opt = NULL;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
159 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
160 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
161 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
164 static const arm_feature_set cpu_default = CPU_DEFAULT;
167 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
168 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
169 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
170 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
171 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
172 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
173 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
174 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
175 static const arm_feature_set arm_ext_v4t_5 =
176 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
178 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
179 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
180 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
181 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
182 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
183 static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
184 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
185 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
186 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
187 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
188 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
189 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
190 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
192 static const arm_feature_set arm_arch_any = ARM_ANY;
193 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
194 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
195 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
197 static const arm_feature_set arm_cext_iwmmxt =
198 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
199 static const arm_feature_set arm_cext_xscale =
200 ARM_FEATURE (0, ARM_CEXT_XSCALE);
201 static const arm_feature_set arm_cext_maverick =
202 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
203 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
204 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
205 static const arm_feature_set fpu_vfp_ext_v1xd =
206 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
207 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
208 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
210 static int mfloat_abi_opt = -1;
211 /* Record user cpu selection for object attributes. */
212 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
213 /* Must be long enough to hold any of the names in arm_cpus. */
214 static char selected_cpu_name[16];
217 static int meabi_flags = EABI_DEFAULT;
219 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
224 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
225 symbolS * GOT_symbol;
228 /* 0: assemble for ARM,
229 1: assemble for Thumb,
230 2: assemble for Thumb even though target CPU does not support thumb
232 static int thumb_mode = 0;
234 /* If unified_syntax is true, we are processing the new unified
235 ARM/Thumb syntax. Important differences from the old ARM mode:
237 - Immediate operands do not require a # prefix.
238 - Conditional affixes always appear at the end of the
239 instruction. (For backward compatibility, those instructions
240 that formerly had them in the middle, continue to accept them
242 - The IT instruction may appear, and if it does is validated
243 against subsequent conditional affixes. It does not generate
246 Important differences from the old Thumb mode:
248 - Immediate operands do not require a # prefix.
249 - Most of the V6T2 instructions are only available in unified mode.
250 - The .N and .W suffixes are recognized and honored (it is an error
251 if they cannot be honored).
252 - All instructions set the flags if and only if they have an 's' affix.
253 - Conditional affixes may be used. They are validated against
254 preceding IT instructions. Unlike ARM mode, you cannot use a
255 conditional affix except in the scope of an IT instruction. */
257 static bfd_boolean unified_syntax = FALSE;
262 unsigned long instruction;
266 /* Set to the opcode if the instruction needs relaxation.
267 Zero if the instruction is not relaxed. */
271 bfd_reloc_code_real_type type;
280 unsigned present : 1; /* Operand present. */
281 unsigned isreg : 1; /* Operand was a register. */
282 unsigned immisreg : 1; /* .imm field is a second register. */
283 unsigned hasreloc : 1; /* Operand has relocation suffix. */
284 unsigned writeback : 1; /* Operand has trailing ! */
285 unsigned preind : 1; /* Preindexed address. */
286 unsigned postind : 1; /* Postindexed address. */
287 unsigned negative : 1; /* Index register was negated. */
288 unsigned shifted : 1; /* Shift applied to operation. */
289 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
293 static struct arm_it inst;
295 #define NUM_FLOAT_VALS 8
297 const char * fp_const[] =
299 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
302 /* Number of littlenums required to hold an extended precision number. */
303 #define MAX_LITTLENUMS 6
305 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
315 #define CP_T_X 0x00008000
316 #define CP_T_Y 0x00400000
318 #define CONDS_BIT 0x00100000
319 #define LOAD_BIT 0x00100000
321 #define DOUBLE_LOAD_FLAG 0x00000001
325 const char * template;
329 #define COND_ALWAYS 0xE
333 const char *template;
337 struct asm_barrier_opt
339 const char *template;
343 /* The bit that distinguishes CPSR and SPSR. */
344 #define SPSR_BIT (1 << 22)
346 /* The individual PSR flag bits. */
347 #define PSR_c (1 << 16)
348 #define PSR_x (1 << 17)
349 #define PSR_s (1 << 18)
350 #define PSR_f (1 << 19)
355 bfd_reloc_code_real_type reloc;
360 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
365 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
368 /* ARM register categories. This includes coprocessor numbers and various
369 architecture extensions' registers. */
391 /* Structure for a hash table entry for a register. */
395 unsigned char number;
397 unsigned char builtin;
400 /* Diagnostics used when we don't get a register of the expected type. */
401 const char *const reg_expected_msgs[] =
403 N_("ARM register expected"),
404 N_("bad or missing co-processor number"),
405 N_("co-processor register expected"),
406 N_("FPA register expected"),
407 N_("VFP single precision register expected"),
408 N_("VFP double precision register expected"),
409 N_("VFP system register expected"),
410 N_("Maverick MVF register expected"),
411 N_("Maverick MVD register expected"),
412 N_("Maverick MVFX register expected"),
413 N_("Maverick MVDX register expected"),
414 N_("Maverick MVAX register expected"),
415 N_("Maverick DSPSC register expected"),
416 N_("iWMMXt data register expected"),
417 N_("iWMMXt control register expected"),
418 N_("iWMMXt scalar register expected"),
419 N_("XScale accumulator register expected"),
422 /* Some well known registers that we refer to directly elsewhere. */
427 /* ARM instructions take 4bytes in the object file, Thumb instructions
433 /* Basic string to match. */
434 const char *template;
436 /* Parameters to instruction. */
437 unsigned char operands[8];
439 /* Conditional tag - see opcode_lookup. */
440 unsigned int tag : 4;
442 /* Basic instruction code. */
443 unsigned int avalue : 28;
445 /* Thumb-format instruction code. */
448 /* Which architecture variant provides this instruction. */
449 const arm_feature_set *avariant;
450 const arm_feature_set *tvariant;
452 /* Function to call to encode instruction in ARM format. */
453 void (* aencode) (void);
455 /* Function to call to encode instruction in Thumb format. */
456 void (* tencode) (void);
459 /* Defines for various bits that we will want to toggle. */
460 #define INST_IMMEDIATE 0x02000000
461 #define OFFSET_REG 0x02000000
462 #define HWOFFSET_IMM 0x00400000
463 #define SHIFT_BY_REG 0x00000010
464 #define PRE_INDEX 0x01000000
465 #define INDEX_UP 0x00800000
466 #define WRITE_BACK 0x00200000
467 #define LDM_TYPE_2_OR_3 0x00400000
469 #define LITERAL_MASK 0xf000f000
470 #define OPCODE_MASK 0xfe1fffff
471 #define V4_STR_BIT 0x00000020
473 #define DATA_OP_SHIFT 21
475 #define T2_OPCODE_MASK 0xfe1fffff
476 #define T2_DATA_OP_SHIFT 21
478 /* Codes to distinguish the arithmetic instructions. */
489 #define OPCODE_CMP 10
490 #define OPCODE_CMN 11
491 #define OPCODE_ORR 12
492 #define OPCODE_MOV 13
493 #define OPCODE_BIC 14
494 #define OPCODE_MVN 15
496 #define T2_OPCODE_AND 0
497 #define T2_OPCODE_BIC 1
498 #define T2_OPCODE_ORR 2
499 #define T2_OPCODE_ORN 3
500 #define T2_OPCODE_EOR 4
501 #define T2_OPCODE_ADD 8
502 #define T2_OPCODE_ADC 10
503 #define T2_OPCODE_SBC 11
504 #define T2_OPCODE_SUB 13
505 #define T2_OPCODE_RSB 14
507 #define T_OPCODE_MUL 0x4340
508 #define T_OPCODE_TST 0x4200
509 #define T_OPCODE_CMN 0x42c0
510 #define T_OPCODE_NEG 0x4240
511 #define T_OPCODE_MVN 0x43c0
513 #define T_OPCODE_ADD_R3 0x1800
514 #define T_OPCODE_SUB_R3 0x1a00
515 #define T_OPCODE_ADD_HI 0x4400
516 #define T_OPCODE_ADD_ST 0xb000
517 #define T_OPCODE_SUB_ST 0xb080
518 #define T_OPCODE_ADD_SP 0xa800
519 #define T_OPCODE_ADD_PC 0xa000
520 #define T_OPCODE_ADD_I8 0x3000
521 #define T_OPCODE_SUB_I8 0x3800
522 #define T_OPCODE_ADD_I3 0x1c00
523 #define T_OPCODE_SUB_I3 0x1e00
525 #define T_OPCODE_ASR_R 0x4100
526 #define T_OPCODE_LSL_R 0x4080
527 #define T_OPCODE_LSR_R 0x40c0
528 #define T_OPCODE_ROR_R 0x41c0
529 #define T_OPCODE_ASR_I 0x1000
530 #define T_OPCODE_LSL_I 0x0000
531 #define T_OPCODE_LSR_I 0x0800
533 #define T_OPCODE_MOV_I8 0x2000
534 #define T_OPCODE_CMP_I8 0x2800
535 #define T_OPCODE_CMP_LR 0x4280
536 #define T_OPCODE_MOV_HR 0x4600
537 #define T_OPCODE_CMP_HR 0x4500
539 #define T_OPCODE_LDR_PC 0x4800
540 #define T_OPCODE_LDR_SP 0x9800
541 #define T_OPCODE_STR_SP 0x9000
542 #define T_OPCODE_LDR_IW 0x6800
543 #define T_OPCODE_STR_IW 0x6000
544 #define T_OPCODE_LDR_IH 0x8800
545 #define T_OPCODE_STR_IH 0x8000
546 #define T_OPCODE_LDR_IB 0x7800
547 #define T_OPCODE_STR_IB 0x7000
548 #define T_OPCODE_LDR_RW 0x5800
549 #define T_OPCODE_STR_RW 0x5000
550 #define T_OPCODE_LDR_RH 0x5a00
551 #define T_OPCODE_STR_RH 0x5200
552 #define T_OPCODE_LDR_RB 0x5c00
553 #define T_OPCODE_STR_RB 0x5400
555 #define T_OPCODE_PUSH 0xb400
556 #define T_OPCODE_POP 0xbc00
558 #define T_OPCODE_BRANCH 0xe000
560 #define THUMB_SIZE 2 /* Size of thumb instruction. */
561 #define THUMB_PP_PC_LR 0x0100
562 #define THUMB_LOAD_BIT 0x0800
563 #define THUMB2_LOAD_BIT 0x00100000
565 #define BAD_ARGS _("bad arguments to instruction")
566 #define BAD_PC _("r15 not allowed here")
567 #define BAD_COND _("instruction cannot be conditional")
568 #define BAD_OVERLAP _("registers may not be the same")
569 #define BAD_HIREG _("lo register required")
570 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
571 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
572 #define BAD_BRANCH _("branch must be last instruction in IT block")
573 #define BAD_NOT_IT _("instruction not allowed in IT block")
575 static struct hash_control *arm_ops_hsh;
576 static struct hash_control *arm_cond_hsh;
577 static struct hash_control *arm_shift_hsh;
578 static struct hash_control *arm_psr_hsh;
579 static struct hash_control *arm_v7m_psr_hsh;
580 static struct hash_control *arm_reg_hsh;
581 static struct hash_control *arm_reloc_hsh;
582 static struct hash_control *arm_barrier_opt_hsh;
584 /* Stuff needed to resolve the label ambiguity
594 symbolS * last_label_seen;
595 static int label_is_thumb_function_name = FALSE;
597 /* Literal pool structure. Held on a per-section
598 and per-sub-section basis. */
600 #define MAX_LITERAL_POOL_SIZE 1024
601 typedef struct literal_pool
603 expressionS literals [MAX_LITERAL_POOL_SIZE];
604 unsigned int next_free_entry;
609 struct literal_pool * next;
612 /* Pointer to a linked list of literal pools. */
613 literal_pool * list_of_pools = NULL;
615 /* State variables for IT block handling. */
616 static bfd_boolean current_it_mask = 0;
617 static int current_cc;
622 /* This array holds the chars that always start a comment. If the
623 pre-processor is disabled, these aren't very useful. */
624 const char comment_chars[] = "@";
626 /* This array holds the chars that only start a comment at the beginning of
627 a line. If the line seems to have the form '# 123 filename'
628 .line and .file directives will appear in the pre-processed output. */
629 /* Note that input_file.c hand checks for '#' at the beginning of the
630 first line of the input file. This is because the compiler outputs
631 #NO_APP at the beginning of its output. */
632 /* Also note that comments like this one will always work. */
633 const char line_comment_chars[] = "#";
635 const char line_separator_chars[] = ";";
637 /* Chars that can be used to separate mant
638 from exp in floating point numbers. */
639 const char EXP_CHARS[] = "eE";
641 /* Chars that mean this number is a floating point constant. */
645 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
647 /* Prefix characters that indicate the start of an immediate
649 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
651 /* Separator character handling. */
653 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
656 skip_past_char (char ** str, char c)
666 #define skip_past_comma(str) skip_past_char (str, ',')
668 /* Arithmetic expressions (possibly involving symbols). */
670 /* Return TRUE if anything in the expression is a bignum. */
673 walk_no_bignums (symbolS * sp)
675 if (symbol_get_value_expression (sp)->X_op == O_big)
678 if (symbol_get_value_expression (sp)->X_add_symbol)
680 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
681 || (symbol_get_value_expression (sp)->X_op_symbol
682 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
688 static int in_my_get_expression = 0;
690 /* Third argument to my_get_expression. */
691 #define GE_NO_PREFIX 0
692 #define GE_IMM_PREFIX 1
693 #define GE_OPT_PREFIX 2
696 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
701 /* In unified syntax, all prefixes are optional. */
703 prefix_mode = GE_OPT_PREFIX;
707 case GE_NO_PREFIX: break;
709 if (!is_immediate_prefix (**str))
711 inst.error = _("immediate expression requires a # prefix");
717 if (is_immediate_prefix (**str))
723 memset (ep, 0, sizeof (expressionS));
725 save_in = input_line_pointer;
726 input_line_pointer = *str;
727 in_my_get_expression = 1;
728 seg = expression (ep);
729 in_my_get_expression = 0;
731 if (ep->X_op == O_illegal)
733 /* We found a bad expression in md_operand(). */
734 *str = input_line_pointer;
735 input_line_pointer = save_in;
736 if (inst.error == NULL)
737 inst.error = _("bad expression");
742 if (seg != absolute_section
743 && seg != text_section
744 && seg != data_section
745 && seg != bss_section
746 && seg != undefined_section)
748 inst.error = _("bad segment");
749 *str = input_line_pointer;
750 input_line_pointer = save_in;
755 /* Get rid of any bignums now, so that we don't generate an error for which
756 we can't establish a line number later on. Big numbers are never valid
757 in instructions, which is where this routine is always called. */
758 if (ep->X_op == O_big
760 && (walk_no_bignums (ep->X_add_symbol)
762 && walk_no_bignums (ep->X_op_symbol)))))
764 inst.error = _("invalid constant");
765 *str = input_line_pointer;
766 input_line_pointer = save_in;
770 *str = input_line_pointer;
771 input_line_pointer = save_in;
775 /* Turn a string in input_line_pointer into a floating point constant
776 of type TYPE, and store the appropriate bytes in *LITP. The number
777 of LITTLENUMS emitted is stored in *SIZEP. An error message is
778 returned, or NULL on OK.
780 Note that fp constants aren't represent in the normal way on the ARM.
781 In big endian mode, things are as expected. However, in little endian
782 mode fp constants are big-endian word-wise, and little-endian byte-wise
783 within the words. For example, (double) 1.1 in big endian mode is
784 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
785 the byte sequence 99 99 f1 3f 9a 99 99 99.
787 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
790 md_atof (int type, char * litP, int * sizeP)
793 LITTLENUM_TYPE words[MAX_LITTLENUMS];
825 return _("bad call to MD_ATOF()");
828 t = atof_ieee (input_line_pointer, type, words);
830 input_line_pointer = t;
833 if (target_big_endian)
835 for (i = 0; i < prec; i++)
837 md_number_to_chars (litP, (valueT) words[i], 2);
843 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
844 for (i = prec - 1; i >= 0; i--)
846 md_number_to_chars (litP, (valueT) words[i], 2);
850 /* For a 4 byte float the order of elements in `words' is 1 0.
851 For an 8 byte float the order is 1 0 3 2. */
852 for (i = 0; i < prec; i += 2)
854 md_number_to_chars (litP, (valueT) words[i + 1], 2);
855 md_number_to_chars (litP + 2, (valueT) words[i], 2);
863 /* We handle all bad expressions here, so that we can report the faulty
864 instruction in the error message. */
866 md_operand (expressionS * expr)
868 if (in_my_get_expression)
869 expr->X_op = O_illegal;
872 /* Immediate values. */
874 /* Generic immediate-value read function for use in directives.
875 Accepts anything that 'expression' can fold to a constant.
876 *val receives the number. */
879 immediate_for_directive (int *val)
882 exp.X_op = O_illegal;
884 if (is_immediate_prefix (*input_line_pointer))
886 input_line_pointer++;
890 if (exp.X_op != O_constant)
892 as_bad (_("expected #constant"));
893 ignore_rest_of_line ();
896 *val = exp.X_add_number;
901 /* Register parsing. */
903 /* Generic register parser. CCP points to what should be the
904 beginning of a register name. If it is indeed a valid register
905 name, advance CCP over it and return the reg_entry structure;
906 otherwise return NULL. Does not issue diagnostics. */
908 static struct reg_entry *
909 arm_reg_parse_multi (char **ccp)
913 struct reg_entry *reg;
915 #ifdef REGISTER_PREFIX
916 if (*start != REGISTER_PREFIX)
920 #ifdef OPTIONAL_REGISTER_PREFIX
921 if (*start == OPTIONAL_REGISTER_PREFIX)
926 if (!ISALPHA (*p) || !is_name_beginner (*p))
931 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
933 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
942 /* As above, but the register must be of type TYPE, and the return
943 value is the register number or FAIL. */
946 arm_reg_parse (char **ccp, enum arm_reg_type type)
949 struct reg_entry *reg = arm_reg_parse_multi (ccp);
951 if (reg && reg->type == type)
954 /* Alternative syntaxes are accepted for a few register classes. */
961 /* Generic coprocessor register names are allowed for these. */
962 if (reg && reg->type == REG_TYPE_CN)
967 /* For backward compatibility, a bare number is valid here. */
969 unsigned long processor = strtoul (start, ccp, 10);
970 if (*ccp != start && processor <= 15)
975 /* WC includes WCG. ??? I'm not sure this is true for all
976 instructions that take WC registers. */
977 if (reg && reg->type == REG_TYPE_MMXWCG)
989 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
991 parse_reg_list (char ** strp)
997 /* We come back here if we get ranges concatenated by '+' or '|'. */
1012 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1014 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
1024 inst.error = _("bad range in register list");
1028 for (i = cur_reg + 1; i < reg; i++)
1030 if (range & (1 << i))
1032 (_("Warning: duplicated register (r%d) in register list"),
1040 if (range & (1 << reg))
1041 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1043 else if (reg <= cur_reg)
1044 as_tsktsk (_("Warning: register range not in ascending order"));
1049 while (skip_past_comma (&str) != FAIL
1050 || (in_range = 1, *str++ == '-'));
1055 inst.error = _("missing `}'");
1063 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1066 if (expr.X_op == O_constant)
1068 if (expr.X_add_number
1069 != (expr.X_add_number & 0x0000ffff))
1071 inst.error = _("invalid register mask");
1075 if ((range & expr.X_add_number) != 0)
1077 int regno = range & expr.X_add_number;
1080 regno = (1 << regno) - 1;
1082 (_("Warning: duplicated register (r%d) in register list"),
1086 range |= expr.X_add_number;
1090 if (inst.reloc.type != 0)
1092 inst.error = _("expression too complex");
1096 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1097 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1098 inst.reloc.pc_rel = 0;
1102 if (*str == '|' || *str == '+')
1108 while (another_range);
1114 /* Parse a VFP register list. If the string is invalid return FAIL.
1115 Otherwise return the number of registers, and set PBASE to the first
1116 register. Double precision registers are matched if DP is nonzero. */
1119 parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
1127 unsigned long mask = 0;
1137 regtype = REG_TYPE_VFD;
1142 regtype = REG_TYPE_VFS;
1146 base_reg = max_regs;
1150 new_base = arm_reg_parse (str, regtype);
1151 if (new_base == FAIL)
1153 inst.error = gettext (reg_expected_msgs[regtype]);
1157 if (new_base < base_reg)
1158 base_reg = new_base;
1160 if (mask & (1 << new_base))
1162 inst.error = _("invalid register list");
1166 if ((mask >> new_base) != 0 && ! warned)
1168 as_tsktsk (_("register list not in ascending order"));
1172 mask |= 1 << new_base;
1175 if (**str == '-') /* We have the start of a range expression */
1181 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1183 inst.error = gettext (reg_expected_msgs[regtype]);
1187 if (high_range <= new_base)
1189 inst.error = _("register range not in ascending order");
1193 for (new_base++; new_base <= high_range; new_base++)
1195 if (mask & (1 << new_base))
1197 inst.error = _("invalid register list");
1201 mask |= 1 << new_base;
1206 while (skip_past_comma (str) != FAIL);
1210 /* Sanity check -- should have raised a parse error above. */
1211 if (count == 0 || count > max_regs)
1216 /* Final test -- the registers must be consecutive. */
1218 for (i = 0; i < count; i++)
1220 if ((mask & (1u << i)) == 0)
1222 inst.error = _("non-contiguous register range");
1230 /* Parse an explicit relocation suffix on an expression. This is
1231 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1232 arm_reloc_hsh contains no entries, so this function can only
1233 succeed if there is no () after the word. Returns -1 on error,
1234 BFD_RELOC_UNUSED if there wasn't any suffix. */
1236 parse_reloc (char **str)
1238 struct reloc_entry *r;
1242 return BFD_RELOC_UNUSED;
1247 while (*q && *q != ')' && *q != ',')
1252 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1259 /* Directives: register aliases. */
1262 insert_reg_alias (char *str, int number, int type)
1264 struct reg_entry *new;
1267 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1270 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1272 /* Only warn about a redefinition if it's not defined as the
1274 else if (new->number != number || new->type != type)
1275 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1280 name = xstrdup (str);
1281 new = xmalloc (sizeof (struct reg_entry));
1284 new->number = number;
1286 new->builtin = FALSE;
1288 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1292 /* Look for the .req directive. This is of the form:
1294 new_register_name .req existing_register_name
1296 If we find one, or if it looks sufficiently like one that we want to
1297 handle any error here, return non-zero. Otherwise return zero. */
1300 create_register_alias (char * newname, char *p)
1302 struct reg_entry *old;
1303 char *oldname, *nbuf;
1306 /* The input scrubber ensures that whitespace after the mnemonic is
1307 collapsed to single spaces. */
1309 if (strncmp (oldname, " .req ", 6) != 0)
1313 if (*oldname == '\0')
1316 old = hash_find (arm_reg_hsh, oldname);
1319 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1323 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1324 the desired alias name, and p points to its end. If not, then
1325 the desired alias name is in the global original_case_string. */
1326 #ifdef TC_CASE_SENSITIVE
1329 newname = original_case_string;
1330 nlen = strlen (newname);
1333 nbuf = alloca (nlen + 1);
1334 memcpy (nbuf, newname, nlen);
1337 /* Create aliases under the new name as stated; an all-lowercase
1338 version of the new name; and an all-uppercase version of the new
1340 insert_reg_alias (nbuf, old->number, old->type);
1342 for (p = nbuf; *p; p++)
1345 if (strncmp (nbuf, newname, nlen))
1346 insert_reg_alias (nbuf, old->number, old->type);
1348 for (p = nbuf; *p; p++)
1351 if (strncmp (nbuf, newname, nlen))
1352 insert_reg_alias (nbuf, old->number, old->type);
1357 /* Should never be called, as .req goes between the alias and the
1358 register name, not at the beginning of the line. */
1360 s_req (int a ATTRIBUTE_UNUSED)
1362 as_bad (_("invalid syntax for .req directive"));
1365 /* The .unreq directive deletes an alias which was previously defined
1366 by .req. For example:
1372 s_unreq (int a ATTRIBUTE_UNUSED)
1377 name = input_line_pointer;
1379 while (*input_line_pointer != 0
1380 && *input_line_pointer != ' '
1381 && *input_line_pointer != '\n')
1382 ++input_line_pointer;
1384 saved_char = *input_line_pointer;
1385 *input_line_pointer = 0;
1388 as_bad (_("invalid syntax for .unreq directive"));
1391 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1394 as_bad (_("unknown register alias '%s'"), name);
1395 else if (reg->builtin)
1396 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1400 hash_delete (arm_reg_hsh, name);
1401 free ((char *) reg->name);
1406 *input_line_pointer = saved_char;
1407 demand_empty_rest_of_line ();
1410 /* Directives: Instruction set selection. */
1413 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1414 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1415 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1416 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1418 static enum mstate mapstate = MAP_UNDEFINED;
1421 mapping_state (enum mstate state)
1424 const char * symname;
1427 if (mapstate == state)
1428 /* The mapping symbol has already been emitted.
1429 There is nothing else to do. */
1438 type = BSF_NO_FLAGS;
1442 type = BSF_NO_FLAGS;
1446 type = BSF_NO_FLAGS;
1454 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1456 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1457 symbol_table_insert (symbolP);
1458 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1463 THUMB_SET_FUNC (symbolP, 0);
1464 ARM_SET_THUMB (symbolP, 0);
1465 ARM_SET_INTERWORK (symbolP, support_interwork);
1469 THUMB_SET_FUNC (symbolP, 1);
1470 ARM_SET_THUMB (symbolP, 1);
1471 ARM_SET_INTERWORK (symbolP, support_interwork);
1480 #define mapping_state(x) /* nothing */
1483 /* Find the real, Thumb encoded start of a Thumb function. */
1486 find_real_start (symbolS * symbolP)
1489 const char * name = S_GET_NAME (symbolP);
1490 symbolS * new_target;
1492 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1493 #define STUB_NAME ".real_start_of"
1498 /* The compiler may generate BL instructions to local labels because
1499 it needs to perform a branch to a far away location. These labels
1500 do not have a corresponding ".real_start_of" label. We check
1501 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1502 the ".real_start_of" convention for nonlocal branches. */
1503 if (S_IS_LOCAL (symbolP) || name[0] == '.')
1506 real_start = ACONCAT ((STUB_NAME, name, NULL));
1507 new_target = symbol_find (real_start);
1509 if (new_target == NULL)
1511 as_warn ("Failed to find real start of function: %s\n", name);
1512 new_target = symbolP;
1519 opcode_select (int width)
1526 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
1527 as_bad (_("selected processor does not support THUMB opcodes"));
1530 /* No need to force the alignment, since we will have been
1531 coming from ARM mode, which is word-aligned. */
1532 record_alignment (now_seg, 1);
1534 mapping_state (MAP_THUMB);
1540 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
1541 as_bad (_("selected processor does not support ARM opcodes"));
1546 frag_align (2, 0, 0);
1548 record_alignment (now_seg, 1);
1550 mapping_state (MAP_ARM);
1554 as_bad (_("invalid instruction size selected (%d)"), width);
1559 s_arm (int ignore ATTRIBUTE_UNUSED)
1562 demand_empty_rest_of_line ();
1566 s_thumb (int ignore ATTRIBUTE_UNUSED)
1569 demand_empty_rest_of_line ();
1573 s_code (int unused ATTRIBUTE_UNUSED)
1577 temp = get_absolute_expression ();
1582 opcode_select (temp);
1586 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1591 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1593 /* If we are not already in thumb mode go into it, EVEN if
1594 the target processor does not support thumb instructions.
1595 This is used by gcc/config/arm/lib1funcs.asm for example
1596 to compile interworking support functions even if the
1597 target processor should not support interworking. */
1601 record_alignment (now_seg, 1);
1604 demand_empty_rest_of_line ();
1608 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1612 /* The following label is the name/address of the start of a Thumb function.
1613 We need to know this for the interworking support. */
1614 label_is_thumb_function_name = TRUE;
1617 /* Perform a .set directive, but also mark the alias as
1618 being a thumb function. */
1621 s_thumb_set (int equiv)
1623 /* XXX the following is a duplicate of the code for s_set() in read.c
1624 We cannot just call that code as we need to get at the symbol that
1631 /* Especial apologies for the random logic:
1632 This just grew, and could be parsed much more simply!
1634 name = input_line_pointer;
1635 delim = get_symbol_end ();
1636 end_name = input_line_pointer;
1639 if (*input_line_pointer != ',')
1642 as_bad (_("expected comma after name \"%s\""), name);
1644 ignore_rest_of_line ();
1648 input_line_pointer++;
1651 if (name[0] == '.' && name[1] == '\0')
1653 /* XXX - this should not happen to .thumb_set. */
1657 if ((symbolP = symbol_find (name)) == NULL
1658 && (symbolP = md_undefined_symbol (name)) == NULL)
1661 /* When doing symbol listings, play games with dummy fragments living
1662 outside the normal fragment chain to record the file and line info
1664 if (listing & LISTING_SYMBOLS)
1666 extern struct list_info_struct * listing_tail;
1667 fragS * dummy_frag = xmalloc (sizeof (fragS));
1669 memset (dummy_frag, 0, sizeof (fragS));
1670 dummy_frag->fr_type = rs_fill;
1671 dummy_frag->line = listing_tail;
1672 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1673 dummy_frag->fr_symbol = symbolP;
1677 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1680 /* "set" symbols are local unless otherwise specified. */
1681 SF_SET_LOCAL (symbolP);
1682 #endif /* OBJ_COFF */
1683 } /* Make a new symbol. */
1685 symbol_table_insert (symbolP);
1690 && S_IS_DEFINED (symbolP)
1691 && S_GET_SEGMENT (symbolP) != reg_section)
1692 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1694 pseudo_set (symbolP);
1696 demand_empty_rest_of_line ();
1698 /* XXX Now we come to the Thumb specific bit of code. */
1700 THUMB_SET_FUNC (symbolP, 1);
1701 ARM_SET_THUMB (symbolP, 1);
1702 #if defined OBJ_ELF || defined OBJ_COFF
1703 ARM_SET_INTERWORK (symbolP, support_interwork);
1707 /* Directives: Mode selection. */
1709 /* .syntax [unified|divided] - choose the new unified syntax
1710 (same for Arm and Thumb encoding, modulo slight differences in what
1711 can be represented) or the old divergent syntax for each mode. */
1713 s_syntax (int unused ATTRIBUTE_UNUSED)
1717 name = input_line_pointer;
1718 delim = get_symbol_end ();
1720 if (!strcasecmp (name, "unified"))
1721 unified_syntax = TRUE;
1722 else if (!strcasecmp (name, "divided"))
1723 unified_syntax = FALSE;
1726 as_bad (_("unrecognized syntax mode \"%s\""), name);
1729 *input_line_pointer = delim;
1730 demand_empty_rest_of_line ();
1733 /* Directives: sectioning and alignment. */
1735 /* Same as s_align_ptwo but align 0 => align 2. */
1738 s_align (int unused ATTRIBUTE_UNUSED)
1742 long max_alignment = 15;
1744 temp = get_absolute_expression ();
1745 if (temp > max_alignment)
1746 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1749 as_bad (_("alignment negative. 0 assumed."));
1753 if (*input_line_pointer == ',')
1755 input_line_pointer++;
1756 temp_fill = get_absolute_expression ();
1764 /* Only make a frag if we HAVE to. */
1765 if (temp && !need_pass_2)
1766 frag_align (temp, (int) temp_fill, 0);
1767 demand_empty_rest_of_line ();
1769 record_alignment (now_seg, temp);
1773 s_bss (int ignore ATTRIBUTE_UNUSED)
1775 /* We don't support putting frags in the BSS segment, we fake it by
1776 marking in_bss, then looking at s_skip for clues. */
1777 subseg_set (bss_section, 0);
1778 demand_empty_rest_of_line ();
1779 mapping_state (MAP_DATA);
1783 s_even (int ignore ATTRIBUTE_UNUSED)
1785 /* Never make frag if expect extra pass. */
1787 frag_align (1, 0, 0);
1789 record_alignment (now_seg, 1);
1791 demand_empty_rest_of_line ();
1794 /* Directives: Literal pools. */
1796 static literal_pool *
1797 find_literal_pool (void)
1799 literal_pool * pool;
1801 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1803 if (pool->section == now_seg
1804 && pool->sub_section == now_subseg)
1811 static literal_pool *
1812 find_or_make_literal_pool (void)
1814 /* Next literal pool ID number. */
1815 static unsigned int latest_pool_num = 1;
1816 literal_pool * pool;
1818 pool = find_literal_pool ();
1822 /* Create a new pool. */
1823 pool = xmalloc (sizeof (* pool));
1827 pool->next_free_entry = 0;
1828 pool->section = now_seg;
1829 pool->sub_section = now_subseg;
1830 pool->next = list_of_pools;
1831 pool->symbol = NULL;
1833 /* Add it to the list. */
1834 list_of_pools = pool;
1837 /* New pools, and emptied pools, will have a NULL symbol. */
1838 if (pool->symbol == NULL)
1840 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1841 (valueT) 0, &zero_address_frag);
1842 pool->id = latest_pool_num ++;
1849 /* Add the literal in the global 'inst'
1850 structure to the relevent literal pool. */
1853 add_to_lit_pool (void)
1855 literal_pool * pool;
1858 pool = find_or_make_literal_pool ();
1860 /* Check if this literal value is already in the pool. */
1861 for (entry = 0; entry < pool->next_free_entry; entry ++)
1863 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1864 && (inst.reloc.exp.X_op == O_constant)
1865 && (pool->literals[entry].X_add_number
1866 == inst.reloc.exp.X_add_number)
1867 && (pool->literals[entry].X_unsigned
1868 == inst.reloc.exp.X_unsigned))
1871 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1872 && (inst.reloc.exp.X_op == O_symbol)
1873 && (pool->literals[entry].X_add_number
1874 == inst.reloc.exp.X_add_number)
1875 && (pool->literals[entry].X_add_symbol
1876 == inst.reloc.exp.X_add_symbol)
1877 && (pool->literals[entry].X_op_symbol
1878 == inst.reloc.exp.X_op_symbol))
1882 /* Do we need to create a new entry? */
1883 if (entry == pool->next_free_entry)
1885 if (entry >= MAX_LITERAL_POOL_SIZE)
1887 inst.error = _("literal pool overflow");
1891 pool->literals[entry] = inst.reloc.exp;
1892 pool->next_free_entry += 1;
1895 inst.reloc.exp.X_op = O_symbol;
1896 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1897 inst.reloc.exp.X_add_symbol = pool->symbol;
1902 /* Can't use symbol_new here, so have to create a symbol and then at
1903 a later date assign it a value. Thats what these functions do. */
1906 symbol_locate (symbolS * symbolP,
1907 const char * name, /* It is copied, the caller can modify. */
1908 segT segment, /* Segment identifier (SEG_<something>). */
1909 valueT valu, /* Symbol value. */
1910 fragS * frag) /* Associated fragment. */
1912 unsigned int name_length;
1913 char * preserved_copy_of_name;
1915 name_length = strlen (name) + 1; /* +1 for \0. */
1916 obstack_grow (¬es, name, name_length);
1917 preserved_copy_of_name = obstack_finish (¬es);
1919 #ifdef tc_canonicalize_symbol_name
1920 preserved_copy_of_name =
1921 tc_canonicalize_symbol_name (preserved_copy_of_name);
1924 S_SET_NAME (symbolP, preserved_copy_of_name);
1926 S_SET_SEGMENT (symbolP, segment);
1927 S_SET_VALUE (symbolP, valu);
1928 symbol_clear_list_pointers (symbolP);
1930 symbol_set_frag (symbolP, frag);
1932 /* Link to end of symbol chain. */
1934 extern int symbol_table_frozen;
1936 if (symbol_table_frozen)
1940 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1942 obj_symbol_new_hook (symbolP);
1944 #ifdef tc_symbol_new_hook
1945 tc_symbol_new_hook (symbolP);
1949 verify_symbol_chain (symbol_rootP, symbol_lastP);
1950 #endif /* DEBUG_SYMS */
1955 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1958 literal_pool * pool;
1961 pool = find_literal_pool ();
1963 || pool->symbol == NULL
1964 || pool->next_free_entry == 0)
1967 mapping_state (MAP_DATA);
1969 /* Align pool as you have word accesses.
1970 Only make a frag if we have to. */
1972 frag_align (2, 0, 0);
1974 record_alignment (now_seg, 2);
1976 sprintf (sym_name, "$$lit_\002%x", pool->id);
1978 symbol_locate (pool->symbol, sym_name, now_seg,
1979 (valueT) frag_now_fix (), frag_now);
1980 symbol_table_insert (pool->symbol);
1982 ARM_SET_THUMB (pool->symbol, thumb_mode);
1984 #if defined OBJ_COFF || defined OBJ_ELF
1985 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1988 for (entry = 0; entry < pool->next_free_entry; entry ++)
1989 /* First output the expression in the instruction to the pool. */
1990 emit_expr (&(pool->literals[entry]), 4); /* .word */
1992 /* Mark the pool as empty. */
1993 pool->next_free_entry = 0;
1994 pool->symbol = NULL;
1998 /* Forward declarations for functions below, in the MD interface
2000 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
2001 static valueT create_unwind_entry (int);
2002 static void start_unwind_section (const segT, int);
2003 static void add_unwind_opcode (valueT, int);
2004 static void flush_pending_unwind (void);
2006 /* Directives: Data. */
2009 s_arm_elf_cons (int nbytes)
2013 #ifdef md_flush_pending_output
2014 md_flush_pending_output ();
2017 if (is_it_end_of_statement ())
2019 demand_empty_rest_of_line ();
2023 #ifdef md_cons_align
2024 md_cons_align (nbytes);
2027 mapping_state (MAP_DATA);
2031 char *base = input_line_pointer;
2035 if (exp.X_op != O_symbol)
2036 emit_expr (&exp, (unsigned int) nbytes);
2039 char *before_reloc = input_line_pointer;
2040 reloc = parse_reloc (&input_line_pointer);
2043 as_bad (_("unrecognized relocation suffix"));
2044 ignore_rest_of_line ();
2047 else if (reloc == BFD_RELOC_UNUSED)
2048 emit_expr (&exp, (unsigned int) nbytes);
2051 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2052 int size = bfd_get_reloc_size (howto);
2054 if (reloc == BFD_RELOC_ARM_PLT32)
2056 as_bad (_("(plt) is only valid on branch targets"));
2057 reloc = BFD_RELOC_UNUSED;
2062 as_bad (_("%s relocations do not fit in %d bytes"),
2063 howto->name, nbytes);
2066 /* We've parsed an expression stopping at O_symbol.
2067 But there may be more expression left now that we
2068 have parsed the relocation marker. Parse it again.
2069 XXX Surely there is a cleaner way to do this. */
2070 char *p = input_line_pointer;
2072 char *save_buf = alloca (input_line_pointer - base);
2073 memcpy (save_buf, base, input_line_pointer - base);
2074 memmove (base + (input_line_pointer - before_reloc),
2075 base, before_reloc - base);
2077 input_line_pointer = base + (input_line_pointer-before_reloc);
2079 memcpy (base, save_buf, p - base);
2081 offset = nbytes - size;
2082 p = frag_more ((int) nbytes);
2083 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2084 size, &exp, 0, reloc);
2089 while (*input_line_pointer++ == ',');
2091 /* Put terminator back into stream. */
2092 input_line_pointer --;
2093 demand_empty_rest_of_line ();
2097 /* Parse a .rel31 directive. */
2100 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2107 if (*input_line_pointer == '1')
2108 highbit = 0x80000000;
2109 else if (*input_line_pointer != '0')
2110 as_bad (_("expected 0 or 1"));
2112 input_line_pointer++;
2113 if (*input_line_pointer != ',')
2114 as_bad (_("missing comma"));
2115 input_line_pointer++;
2117 #ifdef md_flush_pending_output
2118 md_flush_pending_output ();
2121 #ifdef md_cons_align
2125 mapping_state (MAP_DATA);
2130 md_number_to_chars (p, highbit, 4);
2131 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2132 BFD_RELOC_ARM_PREL31);
2134 demand_empty_rest_of_line ();
2137 /* Directives: AEABI stack-unwind tables. */
2139 /* Parse an unwind_fnstart directive. Simply records the current location. */
2142 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2144 demand_empty_rest_of_line ();
2145 /* Mark the start of the function. */
2146 unwind.proc_start = expr_build_dot ();
2148 /* Reset the rest of the unwind info. */
2149 unwind.opcode_count = 0;
2150 unwind.table_entry = NULL;
2151 unwind.personality_routine = NULL;
2152 unwind.personality_index = -1;
2153 unwind.frame_size = 0;
2154 unwind.fp_offset = 0;
2157 unwind.sp_restored = 0;
2161 /* Parse a handlerdata directive. Creates the exception handling table entry
2162 for the function. */
2165 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2167 demand_empty_rest_of_line ();
2168 if (unwind.table_entry)
2169 as_bad (_("dupicate .handlerdata directive"));
2171 create_unwind_entry (1);
2174 /* Parse an unwind_fnend directive. Generates the index table entry. */
2177 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2183 demand_empty_rest_of_line ();
2185 /* Add eh table entry. */
2186 if (unwind.table_entry == NULL)
2187 val = create_unwind_entry (0);
2191 /* Add index table entry. This is two words. */
2192 start_unwind_section (unwind.saved_seg, 1);
2193 frag_align (2, 0, 0);
2194 record_alignment (now_seg, 2);
2196 ptr = frag_more (8);
2197 where = frag_now_fix () - 8;
2199 /* Self relative offset of the function start. */
2200 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2201 BFD_RELOC_ARM_PREL31);
2203 /* Indicate dependency on EHABI-defined personality routines to the
2204 linker, if it hasn't been done already. */
2205 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2206 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2208 static const char *const name[] = {
2209 "__aeabi_unwind_cpp_pr0",
2210 "__aeabi_unwind_cpp_pr1",
2211 "__aeabi_unwind_cpp_pr2"
2213 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2214 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2215 marked_pr_dependency |= 1 << unwind.personality_index;
2216 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2217 = marked_pr_dependency;
2221 /* Inline exception table entry. */
2222 md_number_to_chars (ptr + 4, val, 4);
2224 /* Self relative offset of the table entry. */
2225 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2226 BFD_RELOC_ARM_PREL31);
2228 /* Restore the original section. */
2229 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2233 /* Parse an unwind_cantunwind directive. */
2236 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2238 demand_empty_rest_of_line ();
2239 if (unwind.personality_routine || unwind.personality_index != -1)
2240 as_bad (_("personality routine specified for cantunwind frame"));
2242 unwind.personality_index = -2;
2246 /* Parse a personalityindex directive. */
2249 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2253 if (unwind.personality_routine || unwind.personality_index != -1)
2254 as_bad (_("duplicate .personalityindex directive"));
2258 if (exp.X_op != O_constant
2259 || exp.X_add_number < 0 || exp.X_add_number > 15)
2261 as_bad (_("bad personality routine number"));
2262 ignore_rest_of_line ();
2266 unwind.personality_index = exp.X_add_number;
2268 demand_empty_rest_of_line ();
2272 /* Parse a personality directive. */
2275 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2279 if (unwind.personality_routine || unwind.personality_index != -1)
2280 as_bad (_("duplicate .personality directive"));
2282 name = input_line_pointer;
2283 c = get_symbol_end ();
2284 p = input_line_pointer;
2285 unwind.personality_routine = symbol_find_or_make (name);
2287 demand_empty_rest_of_line ();
2291 /* Parse a directive saving core registers. */
2294 s_arm_unwind_save_core (void)
2300 range = parse_reg_list (&input_line_pointer);
2303 as_bad (_("expected register list"));
2304 ignore_rest_of_line ();
2308 demand_empty_rest_of_line ();
2310 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2311 into .unwind_save {..., sp...}. We aren't bothered about the value of
2312 ip because it is clobbered by calls. */
2313 if (unwind.sp_restored && unwind.fp_reg == 12
2314 && (range & 0x3000) == 0x1000)
2316 unwind.opcode_count--;
2317 unwind.sp_restored = 0;
2318 range = (range | 0x2000) & ~0x1000;
2319 unwind.pending_offset = 0;
2325 /* See if we can use the short opcodes. These pop a block of up to 8
2326 registers starting with r4, plus maybe r14. */
2327 for (n = 0; n < 8; n++)
2329 /* Break at the first non-saved register. */
2330 if ((range & (1 << (n + 4))) == 0)
2333 /* See if there are any other bits set. */
2334 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
2336 /* Use the long form. */
2337 op = 0x8000 | ((range >> 4) & 0xfff);
2338 add_unwind_opcode (op, 2);
2342 /* Use the short form. */
2344 op = 0xa8; /* Pop r14. */
2346 op = 0xa0; /* Do not pop r14. */
2348 add_unwind_opcode (op, 1);
2355 op = 0xb100 | (range & 0xf);
2356 add_unwind_opcode (op, 2);
2359 /* Record the number of bytes pushed. */
2360 for (n = 0; n < 16; n++)
2362 if (range & (1 << n))
2363 unwind.frame_size += 4;
2368 /* Parse a directive saving FPA registers. */
2371 s_arm_unwind_save_fpa (int reg)
2377 /* Get Number of registers to transfer. */
2378 if (skip_past_comma (&input_line_pointer) != FAIL)
2381 exp.X_op = O_illegal;
2383 if (exp.X_op != O_constant)
2385 as_bad (_("expected , <constant>"));
2386 ignore_rest_of_line ();
2390 num_regs = exp.X_add_number;
2392 if (num_regs < 1 || num_regs > 4)
2394 as_bad (_("number of registers must be in the range [1:4]"));
2395 ignore_rest_of_line ();
2399 demand_empty_rest_of_line ();
2404 op = 0xb4 | (num_regs - 1);
2405 add_unwind_opcode (op, 1);
2410 op = 0xc800 | (reg << 4) | (num_regs - 1);
2411 add_unwind_opcode (op, 2);
2413 unwind.frame_size += num_regs * 12;
2417 /* Parse a directive saving VFP registers. */
2420 s_arm_unwind_save_vfp (void)
2426 count = parse_vfp_reg_list (&input_line_pointer, ®, 1);
2429 as_bad (_("expected register list"));
2430 ignore_rest_of_line ();
2434 demand_empty_rest_of_line ();
2439 op = 0xb8 | (count - 1);
2440 add_unwind_opcode (op, 1);
2445 op = 0xb300 | (reg << 4) | (count - 1);
2446 add_unwind_opcode (op, 2);
2448 unwind.frame_size += count * 8 + 4;
2452 /* Parse a directive saving iWMMXt data registers. */
2455 s_arm_unwind_save_mmxwr (void)
2463 if (*input_line_pointer == '{')
2464 input_line_pointer++;
2468 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2472 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2477 as_tsktsk (_("register list not in ascending order"));
2480 if (*input_line_pointer == '-')
2482 input_line_pointer++;
2483 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2486 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2489 else if (reg >= hi_reg)
2491 as_bad (_("bad register range"));
2494 for (; reg < hi_reg; reg++)
2498 while (skip_past_comma (&input_line_pointer) != FAIL);
2500 if (*input_line_pointer == '}')
2501 input_line_pointer++;
2503 demand_empty_rest_of_line ();
2505 /* Generate any deferred opcodes becuuse we're going to be looking at
2507 flush_pending_unwind ();
2509 for (i = 0; i < 16; i++)
2511 if (mask & (1 << i))
2512 unwind.frame_size += 8;
2515 /* Attempt to combine with a previous opcode. We do this because gcc
2516 likes to output separate unwind directives for a single block of
2518 if (unwind.opcode_count > 0)
2520 i = unwind.opcodes[unwind.opcode_count - 1];
2521 if ((i & 0xf8) == 0xc0)
2524 /* Only merge if the blocks are contiguous. */
2527 if ((mask & 0xfe00) == (1 << 9))
2529 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2530 unwind.opcode_count--;
2533 else if (i == 6 && unwind.opcode_count >= 2)
2535 i = unwind.opcodes[unwind.opcode_count - 2];
2539 op = 0xffff << (reg - 1);
2541 || ((mask & op) == (1u << (reg - 1))))
2543 op = (1 << (reg + i + 1)) - 1;
2544 op &= ~((1 << reg) - 1);
2546 unwind.opcode_count -= 2;
2553 /* We want to generate opcodes in the order the registers have been
2554 saved, ie. descending order. */
2555 for (reg = 15; reg >= -1; reg--)
2557 /* Save registers in blocks. */
2559 || !(mask & (1 << reg)))
2561 /* We found an unsaved reg. Generate opcodes to save the
2562 preceeding block. */
2568 op = 0xc0 | (hi_reg - 10);
2569 add_unwind_opcode (op, 1);
2574 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2575 add_unwind_opcode (op, 2);
2584 ignore_rest_of_line ();
2588 s_arm_unwind_save_mmxwcg (void)
2595 if (*input_line_pointer == '{')
2596 input_line_pointer++;
2600 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2604 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2610 as_tsktsk (_("register list not in ascending order"));
2613 if (*input_line_pointer == '-')
2615 input_line_pointer++;
2616 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2619 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2622 else if (reg >= hi_reg)
2624 as_bad (_("bad register range"));
2627 for (; reg < hi_reg; reg++)
2631 while (skip_past_comma (&input_line_pointer) != FAIL);
2633 if (*input_line_pointer == '}')
2634 input_line_pointer++;
2636 demand_empty_rest_of_line ();
2638 /* Generate any deferred opcodes becuuse we're going to be looking at
2640 flush_pending_unwind ();
2642 for (reg = 0; reg < 16; reg++)
2644 if (mask & (1 << reg))
2645 unwind.frame_size += 4;
2648 add_unwind_opcode (op, 2);
2651 ignore_rest_of_line ();
2655 /* Parse an unwind_save directive. */
2658 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
2661 struct reg_entry *reg;
2662 bfd_boolean had_brace = FALSE;
2664 /* Figure out what sort of save we have. */
2665 peek = input_line_pointer;
2673 reg = arm_reg_parse_multi (&peek);
2677 as_bad (_("register expected"));
2678 ignore_rest_of_line ();
2687 as_bad (_("FPA .unwind_save does not take a register list"));
2688 ignore_rest_of_line ();
2691 s_arm_unwind_save_fpa (reg->number);
2694 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2695 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2696 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2697 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2700 as_bad (_(".unwind_save does not support this kind of register"));
2701 ignore_rest_of_line ();
2706 /* Parse an unwind_movsp directive. */
2709 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2714 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2717 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2718 ignore_rest_of_line ();
2721 demand_empty_rest_of_line ();
2723 if (reg == REG_SP || reg == REG_PC)
2725 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2729 if (unwind.fp_reg != REG_SP)
2730 as_bad (_("unexpected .unwind_movsp directive"));
2732 /* Generate opcode to restore the value. */
2734 add_unwind_opcode (op, 1);
2736 /* Record the information for later. */
2737 unwind.fp_reg = reg;
2738 unwind.fp_offset = unwind.frame_size;
2739 unwind.sp_restored = 1;
2742 /* Parse an unwind_pad directive. */
2745 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
2749 if (immediate_for_directive (&offset) == FAIL)
2754 as_bad (_("stack increment must be multiple of 4"));
2755 ignore_rest_of_line ();
2759 /* Don't generate any opcodes, just record the details for later. */
2760 unwind.frame_size += offset;
2761 unwind.pending_offset += offset;
2763 demand_empty_rest_of_line ();
2766 /* Parse an unwind_setfp directive. */
2769 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
2775 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2776 if (skip_past_comma (&input_line_pointer) == FAIL)
2779 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2781 if (fp_reg == FAIL || sp_reg == FAIL)
2783 as_bad (_("expected <reg>, <reg>"));
2784 ignore_rest_of_line ();
2788 /* Optional constant. */
2789 if (skip_past_comma (&input_line_pointer) != FAIL)
2791 if (immediate_for_directive (&offset) == FAIL)
2797 demand_empty_rest_of_line ();
2799 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
2801 as_bad (_("register must be either sp or set by a previous"
2802 "unwind_movsp directive"));
2806 /* Don't generate any opcodes, just record the information for later. */
2807 unwind.fp_reg = fp_reg;
2810 unwind.fp_offset = unwind.frame_size - offset;
2812 unwind.fp_offset -= offset;
2815 /* Parse an unwind_raw directive. */
2818 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
2821 /* This is an arbitary limit. */
2822 unsigned char op[16];
2826 if (exp.X_op == O_constant
2827 && skip_past_comma (&input_line_pointer) != FAIL)
2829 unwind.frame_size += exp.X_add_number;
2833 exp.X_op = O_illegal;
2835 if (exp.X_op != O_constant)
2837 as_bad (_("expected <offset>, <opcode>"));
2838 ignore_rest_of_line ();
2844 /* Parse the opcode. */
2849 as_bad (_("unwind opcode too long"));
2850 ignore_rest_of_line ();
2852 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
2854 as_bad (_("invalid unwind opcode"));
2855 ignore_rest_of_line ();
2858 op[count++] = exp.X_add_number;
2860 /* Parse the next byte. */
2861 if (skip_past_comma (&input_line_pointer) == FAIL)
2867 /* Add the opcode bytes in reverse order. */
2869 add_unwind_opcode (op[count], 1);
2871 demand_empty_rest_of_line ();
2875 /* Parse a .eabi_attribute directive. */
2878 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
2881 bfd_boolean is_string;
2888 if (exp.X_op != O_constant)
2891 tag = exp.X_add_number;
2892 if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
2897 if (skip_past_comma (&input_line_pointer) == FAIL)
2899 if (tag == 32 || !is_string)
2902 if (exp.X_op != O_constant)
2904 as_bad (_("expected numeric constant"));
2905 ignore_rest_of_line ();
2908 i = exp.X_add_number;
2910 if (tag == Tag_compatibility
2911 && skip_past_comma (&input_line_pointer) == FAIL)
2913 as_bad (_("expected comma"));
2914 ignore_rest_of_line ();
2919 skip_whitespace(input_line_pointer);
2920 if (*input_line_pointer != '"')
2922 input_line_pointer++;
2923 s = input_line_pointer;
2924 while (*input_line_pointer && *input_line_pointer != '"')
2925 input_line_pointer++;
2926 if (*input_line_pointer != '"')
2928 saved_char = *input_line_pointer;
2929 *input_line_pointer = 0;
2937 if (tag == Tag_compatibility)
2938 elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
2940 elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
2942 elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
2946 *input_line_pointer = saved_char;
2947 input_line_pointer++;
2949 demand_empty_rest_of_line ();
2952 as_bad (_("bad string constant"));
2953 ignore_rest_of_line ();
2956 as_bad (_("expected <tag> , <value>"));
2957 ignore_rest_of_line ();
2960 static void s_arm_arch (int);
2961 static void s_arm_cpu (int);
2962 static void s_arm_fpu (int);
2963 #endif /* OBJ_ELF */
2965 /* This table describes all the machine specific pseudo-ops the assembler
2966 has to support. The fields are:
2967 pseudo-op name without dot
2968 function to call to execute this pseudo-op
2969 Integer arg to pass to the function. */
2971 const pseudo_typeS md_pseudo_table[] =
2973 /* Never called because '.req' does not start a line. */
2974 { "req", s_req, 0 },
2975 { "unreq", s_unreq, 0 },
2976 { "bss", s_bss, 0 },
2977 { "align", s_align, 0 },
2978 { "arm", s_arm, 0 },
2979 { "thumb", s_thumb, 0 },
2980 { "code", s_code, 0 },
2981 { "force_thumb", s_force_thumb, 0 },
2982 { "thumb_func", s_thumb_func, 0 },
2983 { "thumb_set", s_thumb_set, 0 },
2984 { "even", s_even, 0 },
2985 { "ltorg", s_ltorg, 0 },
2986 { "pool", s_ltorg, 0 },
2987 { "syntax", s_syntax, 0 },
2989 { "word", s_arm_elf_cons, 4 },
2990 { "long", s_arm_elf_cons, 4 },
2991 { "rel31", s_arm_rel31, 0 },
2992 { "fnstart", s_arm_unwind_fnstart, 0 },
2993 { "fnend", s_arm_unwind_fnend, 0 },
2994 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2995 { "personality", s_arm_unwind_personality, 0 },
2996 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2997 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2998 { "save", s_arm_unwind_save, 0 },
2999 { "movsp", s_arm_unwind_movsp, 0 },
3000 { "pad", s_arm_unwind_pad, 0 },
3001 { "setfp", s_arm_unwind_setfp, 0 },
3002 { "unwind_raw", s_arm_unwind_raw, 0 },
3003 { "cpu", s_arm_cpu, 0 },
3004 { "arch", s_arm_arch, 0 },
3005 { "fpu", s_arm_fpu, 0 },
3006 { "eabi_attribute", s_arm_eabi_attribute, 0 },
3010 { "extend", float_cons, 'x' },
3011 { "ldouble", float_cons, 'x' },
3012 { "packed", float_cons, 'p' },
3016 /* Parser functions used exclusively in instruction operands. */
3018 /* Generic immediate-value read function for use in insn parsing.
3019 STR points to the beginning of the immediate (the leading #);
3020 VAL receives the value; if the value is outside [MIN, MAX]
3021 issue an error. PREFIX_OPT is true if the immediate prefix is
3025 parse_immediate (char **str, int *val, int min, int max,
3026 bfd_boolean prefix_opt)
3029 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3030 if (exp.X_op != O_constant)
3032 inst.error = _("constant expression required");
3036 if (exp.X_add_number < min || exp.X_add_number > max)
3038 inst.error = _("immediate value out of range");
3042 *val = exp.X_add_number;
3046 /* Returns the pseudo-register number of an FPA immediate constant,
3047 or FAIL if there isn't a valid constant here. */
3050 parse_fpa_immediate (char ** str)
3052 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3058 /* First try and match exact strings, this is to guarantee
3059 that some formats will work even for cross assembly. */
3061 for (i = 0; fp_const[i]; i++)
3063 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
3067 *str += strlen (fp_const[i]);
3068 if (is_end_of_line[(unsigned char) **str])
3074 /* Just because we didn't get a match doesn't mean that the constant
3075 isn't valid, just that it is in a format that we don't
3076 automatically recognize. Try parsing it with the standard
3077 expression routines. */
3079 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
3081 /* Look for a raw floating point number. */
3082 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
3083 && is_end_of_line[(unsigned char) *save_in])
3085 for (i = 0; i < NUM_FLOAT_VALS; i++)
3087 for (j = 0; j < MAX_LITTLENUMS; j++)
3089 if (words[j] != fp_values[i][j])
3093 if (j == MAX_LITTLENUMS)
3101 /* Try and parse a more complex expression, this will probably fail
3102 unless the code uses a floating point prefix (eg "0f"). */
3103 save_in = input_line_pointer;
3104 input_line_pointer = *str;
3105 if (expression (&exp) == absolute_section
3106 && exp.X_op == O_big
3107 && exp.X_add_number < 0)
3109 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3111 if (gen_to_words (words, 5, (long) 15) == 0)
3113 for (i = 0; i < NUM_FLOAT_VALS; i++)
3115 for (j = 0; j < MAX_LITTLENUMS; j++)
3117 if (words[j] != fp_values[i][j])
3121 if (j == MAX_LITTLENUMS)
3123 *str = input_line_pointer;
3124 input_line_pointer = save_in;
3131 *str = input_line_pointer;
3132 input_line_pointer = save_in;
3133 inst.error = _("invalid FPA immediate expression");
3137 /* Shift operands. */
3140 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
3143 struct asm_shift_name
3146 enum shift_kind kind;
3149 /* Third argument to parse_shift. */
3150 enum parse_shift_mode
3152 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
3153 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
3154 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
3155 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
3156 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
3159 /* Parse a <shift> specifier on an ARM data processing instruction.
3160 This has three forms:
3162 (LSL|LSR|ASL|ASR|ROR) Rs
3163 (LSL|LSR|ASL|ASR|ROR) #imm
3166 Note that ASL is assimilated to LSL in the instruction encoding, and
3167 RRX to ROR #0 (which cannot be written as such). */
3170 parse_shift (char **str, int i, enum parse_shift_mode mode)
3172 const struct asm_shift_name *shift_name;
3173 enum shift_kind shift;
3178 for (p = *str; ISALPHA (*p); p++)
3183 inst.error = _("shift expression expected");
3187 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3189 if (shift_name == NULL)
3191 inst.error = _("shift expression expected");
3195 shift = shift_name->kind;
3199 case NO_SHIFT_RESTRICT:
3200 case SHIFT_IMMEDIATE: break;
3202 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3203 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3205 inst.error = _("'LSL' or 'ASR' required");
3210 case SHIFT_LSL_IMMEDIATE:
3211 if (shift != SHIFT_LSL)
3213 inst.error = _("'LSL' required");
3218 case SHIFT_ASR_IMMEDIATE:
3219 if (shift != SHIFT_ASR)
3221 inst.error = _("'ASR' required");
3229 if (shift != SHIFT_RRX)
3231 /* Whitespace can appear here if the next thing is a bare digit. */
3232 skip_whitespace (p);
3234 if (mode == NO_SHIFT_RESTRICT
3235 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3237 inst.operands[i].imm = reg;
3238 inst.operands[i].immisreg = 1;
3240 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3243 inst.operands[i].shift_kind = shift;
3244 inst.operands[i].shifted = 1;
3249 /* Parse a <shifter_operand> for an ARM data processing instruction:
3252 #<immediate>, <rotate>
3256 where <shift> is defined by parse_shift above, and <rotate> is a
3257 multiple of 2 between 0 and 30. Validation of immediate operands
3258 is deferred to md_apply_fix. */
3261 parse_shifter_operand (char **str, int i)
3266 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3268 inst.operands[i].reg = value;
3269 inst.operands[i].isreg = 1;
3271 /* parse_shift will override this if appropriate */
3272 inst.reloc.exp.X_op = O_constant;
3273 inst.reloc.exp.X_add_number = 0;
3275 if (skip_past_comma (str) == FAIL)
3278 /* Shift operation on register. */
3279 return parse_shift (str, i, NO_SHIFT_RESTRICT);
3282 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3285 if (skip_past_comma (str) == SUCCESS)
3287 /* #x, y -- ie explicit rotation by Y. */
3288 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3291 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3293 inst.error = _("constant expression expected");
3297 value = expr.X_add_number;
3298 if (value < 0 || value > 30 || value % 2 != 0)
3300 inst.error = _("invalid rotation");
3303 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3305 inst.error = _("invalid constant");
3309 /* Convert to decoded value. md_apply_fix will put it back. */
3310 inst.reloc.exp.X_add_number
3311 = (((inst.reloc.exp.X_add_number << (32 - value))
3312 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
3315 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3316 inst.reloc.pc_rel = 0;
3320 /* Parse all forms of an ARM address expression. Information is written
3321 to inst.operands[i] and/or inst.reloc.
3323 Preindexed addressing (.preind=1):
3325 [Rn, #offset] .reg=Rn .reloc.exp=offset
3326 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3327 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3328 .shift_kind=shift .reloc.exp=shift_imm
3330 These three may have a trailing ! which causes .writeback to be set also.
3332 Postindexed addressing (.postind=1, .writeback=1):
3334 [Rn], #offset .reg=Rn .reloc.exp=offset
3335 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3336 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3337 .shift_kind=shift .reloc.exp=shift_imm
3339 Unindexed addressing (.preind=0, .postind=0):
3341 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3345 [Rn]{!} shorthand for [Rn,#0]{!}
3346 =immediate .isreg=0 .reloc.exp=immediate
3347 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3349 It is the caller's responsibility to check for addressing modes not
3350 supported by the instruction, and to set inst.reloc.type. */
3353 parse_address (char **str, int i)
3358 if (skip_past_char (&p, '[') == FAIL)
3360 if (skip_past_char (&p, '=') == FAIL)
3362 /* bare address - translate to PC-relative offset */
3363 inst.reloc.pc_rel = 1;
3364 inst.operands[i].reg = REG_PC;
3365 inst.operands[i].isreg = 1;
3366 inst.operands[i].preind = 1;
3368 /* else a load-constant pseudo op, no special treatment needed here */
3370 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3377 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3379 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3382 inst.operands[i].reg = reg;
3383 inst.operands[i].isreg = 1;
3385 if (skip_past_comma (&p) == SUCCESS)
3387 inst.operands[i].preind = 1;
3390 else if (*p == '-') p++, inst.operands[i].negative = 1;
3392 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3394 inst.operands[i].imm = reg;
3395 inst.operands[i].immisreg = 1;
3397 if (skip_past_comma (&p) == SUCCESS)
3398 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3403 if (inst.operands[i].negative)
3405 inst.operands[i].negative = 0;
3408 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3413 if (skip_past_char (&p, ']') == FAIL)
3415 inst.error = _("']' expected");
3419 if (skip_past_char (&p, '!') == SUCCESS)
3420 inst.operands[i].writeback = 1;
3422 else if (skip_past_comma (&p) == SUCCESS)
3424 if (skip_past_char (&p, '{') == SUCCESS)
3426 /* [Rn], {expr} - unindexed, with option */
3427 if (parse_immediate (&p, &inst.operands[i].imm,
3428 0, 255, TRUE) == FAIL)
3431 if (skip_past_char (&p, '}') == FAIL)
3433 inst.error = _("'}' expected at end of 'option' field");
3436 if (inst.operands[i].preind)
3438 inst.error = _("cannot combine index with option");
3446 inst.operands[i].postind = 1;
3447 inst.operands[i].writeback = 1;
3449 if (inst.operands[i].preind)
3451 inst.error = _("cannot combine pre- and post-indexing");
3456 else if (*p == '-') p++, inst.operands[i].negative = 1;
3458 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3460 inst.operands[i].imm = reg;
3461 inst.operands[i].immisreg = 1;
3463 if (skip_past_comma (&p) == SUCCESS)
3464 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3469 if (inst.operands[i].negative)
3471 inst.operands[i].negative = 0;
3474 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3480 /* If at this point neither .preind nor .postind is set, we have a
3481 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3482 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3484 inst.operands[i].preind = 1;
3485 inst.reloc.exp.X_op = O_constant;
3486 inst.reloc.exp.X_add_number = 0;
3492 /* Miscellaneous. */
3494 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3495 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3497 parse_psr (char **str)
3500 unsigned long psr_field;
3501 const struct asm_psr *psr;
3504 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3505 feature for ease of use and backwards compatibility. */
3507 if (strncasecmp (p, "SPSR", 4) == 0)
3508 psr_field = SPSR_BIT;
3509 else if (strncasecmp (p, "CPSR", 4) == 0)
3516 while (ISALNUM (*p) || *p == '_');
3518 psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
3529 /* A suffix follows. */
3535 while (ISALNUM (*p) || *p == '_');
3537 psr = hash_find_n (arm_psr_hsh, start, p - start);
3541 psr_field |= psr->field;
3546 goto error; /* Garbage after "[CS]PSR". */
3548 psr_field |= (PSR_c | PSR_f);
3554 inst.error = _("flag for {c}psr instruction expected");
3558 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3559 value suitable for splatting into the AIF field of the instruction. */
3562 parse_cps_flags (char **str)
3571 case '\0': case ',':
3574 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3575 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3576 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
3579 inst.error = _("unrecognized CPS flag");
3584 if (saw_a_flag == 0)
3586 inst.error = _("missing CPS flags");
3594 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3595 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3598 parse_endian_specifier (char **str)
3603 if (strncasecmp (s, "BE", 2))
3605 else if (strncasecmp (s, "LE", 2))
3609 inst.error = _("valid endian specifiers are be or le");
3613 if (ISALNUM (s[2]) || s[2] == '_')
3615 inst.error = _("valid endian specifiers are be or le");
3620 return little_endian;
3623 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3624 value suitable for poking into the rotate field of an sxt or sxta
3625 instruction, or FAIL on error. */
3628 parse_ror (char **str)
3633 if (strncasecmp (s, "ROR", 3) == 0)
3637 inst.error = _("missing rotation field after comma");
3641 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3646 case 0: *str = s; return 0x0;
3647 case 8: *str = s; return 0x1;
3648 case 16: *str = s; return 0x2;
3649 case 24: *str = s; return 0x3;
3652 inst.error = _("rotation can only be 0, 8, 16, or 24");
3657 /* Parse a conditional code (from conds[] below). The value returned is in the
3658 range 0 .. 14, or FAIL. */
3660 parse_cond (char **str)
3663 const struct asm_cond *c;
3666 while (ISALPHA (*q))
3669 c = hash_find_n (arm_cond_hsh, p, q - p);
3672 inst.error = _("condition required");
3680 /* Parse an option for a barrier instruction. Returns the encoding for the
3683 parse_barrier (char **str)
3686 const struct asm_barrier_opt *o;
3689 while (ISALPHA (*q))
3692 o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
3700 /* Parse the operands of a table branch instruction. Similar to a memory
3703 parse_tb (char **str)
3708 if (skip_past_char (&p, '[') == FAIL)
3710 inst.error = _("'[' expected");
3714 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3716 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3719 inst.operands[0].reg = reg;
3721 if (skip_past_comma (&p) == FAIL)
3723 inst.error = _("',' expected");
3727 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3729 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3732 inst.operands[0].imm = reg;
3734 if (skip_past_comma (&p) == SUCCESS)
3736 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
3738 if (inst.reloc.exp.X_add_number != 1)
3740 inst.error = _("invalid shift");
3743 inst.operands[0].shifted = 1;
3746 if (skip_past_char (&p, ']') == FAIL)
3748 inst.error = _("']' expected");
3755 /* Matcher codes for parse_operands. */
3756 enum operand_parse_code
3758 OP_stop, /* end of line */
3760 OP_RR, /* ARM register */
3761 OP_RRnpc, /* ARM register, not r15 */
3762 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3763 OP_RRw, /* ARM register, not r15, optional trailing ! */
3764 OP_RCP, /* Coprocessor number */
3765 OP_RCN, /* Coprocessor register */
3766 OP_RF, /* FPA register */
3767 OP_RVS, /* VFP single precision register */
3768 OP_RVD, /* VFP double precision register */
3769 OP_RVC, /* VFP control register */
3770 OP_RMF, /* Maverick F register */
3771 OP_RMD, /* Maverick D register */
3772 OP_RMFX, /* Maverick FX register */
3773 OP_RMDX, /* Maverick DX register */
3774 OP_RMAX, /* Maverick AX register */
3775 OP_RMDS, /* Maverick DSPSC register */
3776 OP_RIWR, /* iWMMXt wR register */
3777 OP_RIWC, /* iWMMXt wC register */
3778 OP_RIWG, /* iWMMXt wCG register */
3779 OP_RXA, /* XScale accumulator register */
3781 OP_REGLST, /* ARM register list */
3782 OP_VRSLST, /* VFP single-precision register list */
3783 OP_VRDLST, /* VFP double-precision register list */
3785 OP_I7, /* immediate value 0 .. 7 */
3786 OP_I15, /* 0 .. 15 */
3787 OP_I16, /* 1 .. 16 */
3788 OP_I31, /* 0 .. 31 */
3789 OP_I31w, /* 0 .. 31, optional trailing ! */
3790 OP_I32, /* 1 .. 32 */
3791 OP_I63s, /* -64 .. 63 */
3792 OP_I255, /* 0 .. 255 */
3793 OP_Iffff, /* 0 .. 65535 */
3795 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3796 OP_I7b, /* 0 .. 7 */
3797 OP_I15b, /* 0 .. 15 */
3798 OP_I31b, /* 0 .. 31 */
3800 OP_SH, /* shifter operand */
3801 OP_ADDR, /* Memory address expression (any mode) */
3802 OP_EXP, /* arbitrary expression */
3803 OP_EXPi, /* same, with optional immediate prefix */
3804 OP_EXPr, /* same, with optional relocation suffix */
3806 OP_CPSF, /* CPS flags */
3807 OP_ENDI, /* Endianness specifier */
3808 OP_PSR, /* CPSR/SPSR mask for msr */
3809 OP_COND, /* conditional code */
3810 OP_TB, /* Table branch. */
3812 OP_RRnpc_I0, /* ARM register or literal 0 */
3813 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3814 OP_RR_EXi, /* ARM register or expression with imm prefix */
3815 OP_RF_IF, /* FPA register or immediate */
3816 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3818 /* Optional operands. */
3819 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3820 OP_oI31b, /* 0 .. 31 */
3821 OP_oIffffb, /* 0 .. 65535 */
3822 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3824 OP_oRR, /* ARM register */
3825 OP_oRRnpc, /* ARM register, not the PC */
3826 OP_oSHll, /* LSL immediate */
3827 OP_oSHar, /* ASR immediate */
3828 OP_oSHllar, /* LSL or ASR immediate */
3829 OP_oROR, /* ROR 0/8/16/24 */
3830 OP_oBARRIER, /* Option argument for a barrier instruction. */
3832 OP_FIRST_OPTIONAL = OP_oI7b
3835 /* Generic instruction operand parser. This does no encoding and no
3836 semantic validation; it merely squirrels values away in the inst
3837 structure. Returns SUCCESS or FAIL depending on whether the
3838 specified grammar matched. */
3840 parse_operands (char *str, const unsigned char *pattern)
3842 unsigned const char *upat = pattern;
3843 char *backtrack_pos = 0;
3844 const char *backtrack_error = 0;
3845 int i, val, backtrack_index = 0;
3847 #define po_char_or_fail(chr) do { \
3848 if (skip_past_char (&str, chr) == FAIL) \
3852 #define po_reg_or_fail(regtype) do { \
3853 val = arm_reg_parse (&str, regtype); \
3856 inst.error = _(reg_expected_msgs[regtype]); \
3859 inst.operands[i].reg = val; \
3860 inst.operands[i].isreg = 1; \
3863 #define po_reg_or_goto(regtype, label) do { \
3864 val = arm_reg_parse (&str, regtype); \
3868 inst.operands[i].reg = val; \
3869 inst.operands[i].isreg = 1; \
3872 #define po_imm_or_fail(min, max, popt) do { \
3873 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3875 inst.operands[i].imm = val; \
3878 #define po_misc_or_fail(expr) do { \
3883 skip_whitespace (str);
3885 for (i = 0; upat[i] != OP_stop; i++)
3887 if (upat[i] >= OP_FIRST_OPTIONAL)
3889 /* Remember where we are in case we need to backtrack. */
3890 assert (!backtrack_pos);
3891 backtrack_pos = str;
3892 backtrack_error = inst.error;
3893 backtrack_index = i;
3897 po_char_or_fail (',');
3905 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3906 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3907 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3908 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3909 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3910 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3911 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3912 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3913 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3914 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3915 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3916 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3917 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3918 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3919 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3920 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3921 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3924 po_char_or_fail ('[');
3925 po_reg_or_fail (REG_TYPE_RN);
3926 po_char_or_fail (']');
3930 po_reg_or_fail (REG_TYPE_RN);
3931 if (skip_past_char (&str, '!') == SUCCESS)
3932 inst.operands[i].writeback = 1;
3936 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3937 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3938 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3939 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3940 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3941 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3942 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3943 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3945 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3947 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3948 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3950 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3951 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3953 /* Immediate variants */
3955 po_char_or_fail ('{');
3956 po_imm_or_fail (0, 255, TRUE);
3957 po_char_or_fail ('}');
3961 /* The expression parser chokes on a trailing !, so we have
3962 to find it first and zap it. */
3965 while (*s && *s != ',')
3970 inst.operands[i].writeback = 1;
3972 po_imm_or_fail (0, 31, TRUE);
3980 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3985 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3990 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3992 if (inst.reloc.exp.X_op == O_symbol)
3994 val = parse_reloc (&str);
3997 inst.error = _("unrecognized relocation suffix");
4000 else if (val != BFD_RELOC_UNUSED)
4002 inst.operands[i].imm = val;
4003 inst.operands[i].hasreloc = 1;
4008 /* Register or expression */
4009 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
4010 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
4012 /* Register or immediate */
4013 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
4014 I0: po_imm_or_fail (0, 0, FALSE); break;
4016 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
4018 if (!is_immediate_prefix (*str))
4021 val = parse_fpa_immediate (&str);
4024 /* FPA immediates are encoded as registers 8-15.
4025 parse_fpa_immediate has already applied the offset. */
4026 inst.operands[i].reg = val;
4027 inst.operands[i].isreg = 1;
4030 /* Two kinds of register */
4033 struct reg_entry *rege = arm_reg_parse_multi (&str);
4034 if (rege->type != REG_TYPE_MMXWR
4035 && rege->type != REG_TYPE_MMXWC
4036 && rege->type != REG_TYPE_MMXWCG)
4038 inst.error = _("iWMMXt data or control register expected");
4041 inst.operands[i].reg = rege->number;
4042 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
4047 case OP_CPSF: val = parse_cps_flags (&str); break;
4048 case OP_ENDI: val = parse_endian_specifier (&str); break;
4049 case OP_oROR: val = parse_ror (&str); break;
4050 case OP_PSR: val = parse_psr (&str); break;
4051 case OP_COND: val = parse_cond (&str); break;
4052 case OP_oBARRIER:val = parse_barrier (&str); break;
4055 po_misc_or_fail (parse_tb (&str));
4058 /* Register lists */
4060 val = parse_reg_list (&str);
4063 inst.operands[1].writeback = 1;
4069 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
4073 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
4076 /* Addressing modes */
4078 po_misc_or_fail (parse_address (&str, i));
4082 po_misc_or_fail (parse_shifter_operand (&str, i));
4086 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
4090 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
4094 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
4098 as_fatal ("unhandled operand code %d", upat[i]);
4101 /* Various value-based sanity checks and shared operations. We
4102 do not signal immediate failures for the register constraints;
4103 this allows a syntax error to take precedence. */
4111 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
4112 inst.error = BAD_PC;
4126 inst.operands[i].imm = val;
4133 /* If we get here, this operand was successfully parsed. */
4134 inst.operands[i].present = 1;
4138 inst.error = BAD_ARGS;
4143 /* The parse routine should already have set inst.error, but set a
4144 defaut here just in case. */
4146 inst.error = _("syntax error");
4150 /* Do not backtrack over a trailing optional argument that
4151 absorbed some text. We will only fail again, with the
4152 'garbage following instruction' error message, which is
4153 probably less helpful than the current one. */
4154 if (backtrack_index == i && backtrack_pos != str
4155 && upat[i+1] == OP_stop)
4158 inst.error = _("syntax error");
4162 /* Try again, skipping the optional argument at backtrack_pos. */
4163 str = backtrack_pos;
4164 inst.error = backtrack_error;
4165 inst.operands[backtrack_index].present = 0;
4166 i = backtrack_index;
4170 /* Check that we have parsed all the arguments. */
4171 if (*str != '\0' && !inst.error)
4172 inst.error = _("garbage following instruction");
4174 return inst.error ? FAIL : SUCCESS;
4177 #undef po_char_or_fail
4178 #undef po_reg_or_fail
4179 #undef po_reg_or_goto
4180 #undef po_imm_or_fail
4182 /* Shorthand macro for instruction encoding functions issuing errors. */
4183 #define constraint(expr, err) do { \
4191 /* Functions for operand encoding. ARM, then Thumb. */
4193 #define rotate_left(v, n) (v << n | v >> (32 - n))
4195 /* If VAL can be encoded in the immediate field of an ARM instruction,
4196 return the encoded form. Otherwise, return FAIL. */
4199 encode_arm_immediate (unsigned int val)
4203 for (i = 0; i < 32; i += 2)
4204 if ((a = rotate_left (val, i)) <= 0xff)
4205 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
4210 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
4211 return the encoded form. Otherwise, return FAIL. */
4213 encode_thumb32_immediate (unsigned int val)
4220 for (i = 1; i <= 24; i++)
4223 if ((val & ~(0xff << i)) == 0)
4224 return ((val >> i) & 0x7f) | ((32 - i) << 7);
4228 if (val == ((a << 16) | a))
4230 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
4234 if (val == ((a << 16) | a))
4235 return 0x200 | (a >> 8);
4239 /* Encode a VFP SP register number into inst.instruction. */
4242 encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
4247 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
4251 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
4255 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
4263 /* Encode a <shift> in an ARM-format instruction. The immediate,
4264 if any, is handled by md_apply_fix. */
4266 encode_arm_shift (int i)
4268 if (inst.operands[i].shift_kind == SHIFT_RRX)
4269 inst.instruction |= SHIFT_ROR << 5;
4272 inst.instruction |= inst.operands[i].shift_kind << 5;
4273 if (inst.operands[i].immisreg)
4275 inst.instruction |= SHIFT_BY_REG;
4276 inst.instruction |= inst.operands[i].imm << 8;
4279 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4284 encode_arm_shifter_operand (int i)
4286 if (inst.operands[i].isreg)
4288 inst.instruction |= inst.operands[i].reg;
4289 encode_arm_shift (i);
4292 inst.instruction |= INST_IMMEDIATE;
4295 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4297 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
4299 assert (inst.operands[i].isreg);
4300 inst.instruction |= inst.operands[i].reg << 16;
4302 if (inst.operands[i].preind)
4306 inst.error = _("instruction does not accept preindexed addressing");
4309 inst.instruction |= PRE_INDEX;
4310 if (inst.operands[i].writeback)
4311 inst.instruction |= WRITE_BACK;
4314 else if (inst.operands[i].postind)
4316 assert (inst.operands[i].writeback);
4318 inst.instruction |= WRITE_BACK;
4320 else /* unindexed - only for coprocessor */
4322 inst.error = _("instruction does not accept unindexed addressing");
4326 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4327 && (((inst.instruction & 0x000f0000) >> 16)
4328 == ((inst.instruction & 0x0000f000) >> 12)))
4329 as_warn ((inst.instruction & LOAD_BIT)
4330 ? _("destination register same as write-back base")
4331 : _("source register same as write-back base"));
4334 /* inst.operands[i] was set up by parse_address. Encode it into an
4335 ARM-format mode 2 load or store instruction. If is_t is true,
4336 reject forms that cannot be used with a T instruction (i.e. not
4339 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
4341 encode_arm_addr_mode_common (i, is_t);
4343 if (inst.operands[i].immisreg)
4345 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4346 inst.instruction |= inst.operands[i].imm;
4347 if (!inst.operands[i].negative)
4348 inst.instruction |= INDEX_UP;
4349 if (inst.operands[i].shifted)
4351 if (inst.operands[i].shift_kind == SHIFT_RRX)
4352 inst.instruction |= SHIFT_ROR << 5;
4355 inst.instruction |= inst.operands[i].shift_kind << 5;
4356 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4360 else /* immediate offset in inst.reloc */
4362 if (inst.reloc.type == BFD_RELOC_UNUSED)
4363 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4367 /* inst.operands[i] was set up by parse_address. Encode it into an
4368 ARM-format mode 3 load or store instruction. Reject forms that
4369 cannot be used with such instructions. If is_t is true, reject
4370 forms that cannot be used with a T instruction (i.e. not
4373 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
4375 if (inst.operands[i].immisreg && inst.operands[i].shifted)
4377 inst.error = _("instruction does not accept scaled register index");
4381 encode_arm_addr_mode_common (i, is_t);
4383 if (inst.operands[i].immisreg)
4385 inst.instruction |= inst.operands[i].imm;
4386 if (!inst.operands[i].negative)
4387 inst.instruction |= INDEX_UP;
4389 else /* immediate offset in inst.reloc */
4391 inst.instruction |= HWOFFSET_IMM;
4392 if (inst.reloc.type == BFD_RELOC_UNUSED)
4393 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4397 /* inst.operands[i] was set up by parse_address. Encode it into an
4398 ARM-format instruction. Reject all forms which cannot be encoded
4399 into a coprocessor load/store instruction. If wb_ok is false,
4400 reject use of writeback; if unind_ok is false, reject use of
4401 unindexed addressing. If reloc_override is not 0, use it instead
4402 of BFD_ARM_CP_OFF_IMM. */
4405 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
4407 inst.instruction |= inst.operands[i].reg << 16;
4409 assert (!(inst.operands[i].preind && inst.operands[i].postind));
4411 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
4413 assert (!inst.operands[i].writeback);
4416 inst.error = _("instruction does not support unindexed addressing");
4419 inst.instruction |= inst.operands[i].imm;
4420 inst.instruction |= INDEX_UP;
4424 if (inst.operands[i].preind)
4425 inst.instruction |= PRE_INDEX;
4427 if (inst.operands[i].writeback)
4429 if (inst.operands[i].reg == REG_PC)
4431 inst.error = _("pc may not be used with write-back");
4436 inst.error = _("instruction does not support writeback");
4439 inst.instruction |= WRITE_BACK;
4443 inst.reloc.type = reloc_override;
4444 else if (thumb_mode)
4445 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
4447 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4451 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4452 Determine whether it can be performed with a move instruction; if
4453 it can, convert inst.instruction to that move instruction and
4454 return 1; if it can't, convert inst.instruction to a literal-pool
4455 load and return 0. If this is not a valid thing to do in the
4456 current context, set inst.error and return 1.
4458 inst.operands[i] describes the destination register. */
4461 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4466 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
4470 if ((inst.instruction & tbit) == 0)
4472 inst.error = _("invalid pseudo operation");
4475 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
4477 inst.error = _("constant expression expected");
4480 if (inst.reloc.exp.X_op == O_constant)
4484 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
4486 /* This can be done with a mov(1) instruction. */
4487 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4488 inst.instruction |= inst.reloc.exp.X_add_number;
4494 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4497 /* This can be done with a mov instruction. */
4498 inst.instruction &= LITERAL_MASK;
4499 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4500 inst.instruction |= value & 0xfff;
4504 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4507 /* This can be done with a mvn instruction. */
4508 inst.instruction &= LITERAL_MASK;
4509 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4510 inst.instruction |= value & 0xfff;
4516 if (add_to_lit_pool () == FAIL)
4518 inst.error = _("literal pool insertion failed");
4521 inst.operands[1].reg = REG_PC;
4522 inst.operands[1].isreg = 1;
4523 inst.operands[1].preind = 1;
4524 inst.reloc.pc_rel = 1;
4525 inst.reloc.type = (thumb_p
4526 ? BFD_RELOC_ARM_THUMB_OFFSET
4528 ? BFD_RELOC_ARM_HWLITERAL
4529 : BFD_RELOC_ARM_LITERAL));
4533 /* Functions for instruction encoding, sorted by subarchitecture.
4534 First some generics; their names are taken from the conventional
4535 bit positions for register arguments in ARM format instructions. */
4545 inst.instruction |= inst.operands[0].reg << 12;
4551 inst.instruction |= inst.operands[0].reg << 12;
4552 inst.instruction |= inst.operands[1].reg;
4558 inst.instruction |= inst.operands[0].reg << 12;
4559 inst.instruction |= inst.operands[1].reg << 16;
4565 inst.instruction |= inst.operands[0].reg << 16;
4566 inst.instruction |= inst.operands[1].reg << 12;
4572 unsigned Rn = inst.operands[2].reg;
4573 /* Enforce resutrictions on SWP instruction. */
4574 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
4575 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
4576 _("Rn must not overlap other operands"));
4577 inst.instruction |= inst.operands[0].reg << 12;
4578 inst.instruction |= inst.operands[1].reg;
4579 inst.instruction |= Rn << 16;
4585 inst.instruction |= inst.operands[0].reg << 12;
4586 inst.instruction |= inst.operands[1].reg << 16;
4587 inst.instruction |= inst.operands[2].reg;
4593 inst.instruction |= inst.operands[0].reg;
4594 inst.instruction |= inst.operands[1].reg << 12;
4595 inst.instruction |= inst.operands[2].reg << 16;
4601 inst.instruction |= inst.operands[0].imm;
4607 inst.instruction |= inst.operands[0].reg << 12;
4608 encode_arm_cp_address (1, TRUE, TRUE, 0);
4611 /* ARM instructions, in alphabetical order by function name (except
4612 that wrapper functions appear immediately after the function they
4615 /* This is a pseudo-op of the form "adr rd, label" to be converted
4616 into a relative address of the form "add rd, pc, #label-.-8". */
4621 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4623 /* Frag hacking will turn this into a sub instruction if the offset turns
4624 out to be negative. */
4625 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4626 inst.reloc.pc_rel = 1;
4627 inst.reloc.exp.X_add_number -= 8;
4630 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4631 into a relative address of the form:
4632 add rd, pc, #low(label-.-8)"
4633 add rd, rd, #high(label-.-8)" */
4638 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4640 /* Frag hacking will turn this into a sub instruction if the offset turns
4641 out to be negative. */
4642 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4643 inst.reloc.pc_rel = 1;
4644 inst.size = INSN_SIZE * 2;
4645 inst.reloc.exp.X_add_number -= 8;
4651 if (!inst.operands[1].present)
4652 inst.operands[1].reg = inst.operands[0].reg;
4653 inst.instruction |= inst.operands[0].reg << 12;
4654 inst.instruction |= inst.operands[1].reg << 16;
4655 encode_arm_shifter_operand (2);
4661 if (inst.operands[0].present)
4663 constraint ((inst.instruction & 0xf0) != 0x40
4664 && inst.operands[0].imm != 0xf,
4665 "bad barrier type");
4666 inst.instruction |= inst.operands[0].imm;
4669 inst.instruction |= 0xf;
4675 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4676 constraint (msb > 32, _("bit-field extends past end of register"));
4677 /* The instruction encoding stores the LSB and MSB,
4678 not the LSB and width. */
4679 inst.instruction |= inst.operands[0].reg << 12;
4680 inst.instruction |= inst.operands[1].imm << 7;
4681 inst.instruction |= (msb - 1) << 16;
4689 /* #0 in second position is alternative syntax for bfc, which is
4690 the same instruction but with REG_PC in the Rm field. */
4691 if (!inst.operands[1].isreg)
4692 inst.operands[1].reg = REG_PC;
4694 msb = inst.operands[2].imm + inst.operands[3].imm;
4695 constraint (msb > 32, _("bit-field extends past end of register"));
4696 /* The instruction encoding stores the LSB and MSB,
4697 not the LSB and width. */
4698 inst.instruction |= inst.operands[0].reg << 12;
4699 inst.instruction |= inst.operands[1].reg;
4700 inst.instruction |= inst.operands[2].imm << 7;
4701 inst.instruction |= (msb - 1) << 16;
4707 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4708 _("bit-field extends past end of register"));
4709 inst.instruction |= inst.operands[0].reg << 12;
4710 inst.instruction |= inst.operands[1].reg;
4711 inst.instruction |= inst.operands[2].imm << 7;
4712 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4715 /* ARM V5 breakpoint instruction (argument parse)
4716 BKPT <16 bit unsigned immediate>
4717 Instruction is not conditional.
4718 The bit pattern given in insns[] has the COND_ALWAYS condition,
4719 and it is an error if the caller tried to override that. */
4724 /* Top 12 of 16 bits to bits 19:8. */
4725 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
4727 /* Bottom 4 of 16 bits to bits 3:0. */
4728 inst.instruction |= inst.operands[0].imm & 0xf;
4732 encode_branch (int default_reloc)
4734 if (inst.operands[0].hasreloc)
4736 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4737 _("the only suffix valid here is '(plt)'"));
4738 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4742 inst.reloc.type = default_reloc;
4744 inst.reloc.pc_rel = 1;
4751 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4752 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4755 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4762 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4764 if (inst.cond == COND_ALWAYS)
4765 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4767 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4771 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4774 /* ARM V5 branch-link-exchange instruction (argument parse)
4775 BLX <target_addr> ie BLX(1)
4776 BLX{<condition>} <Rm> ie BLX(2)
4777 Unfortunately, there are two different opcodes for this mnemonic.
4778 So, the insns[].value is not used, and the code here zaps values
4779 into inst.instruction.
4780 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4785 if (inst.operands[0].isreg)
4787 /* Arg is a register; the opcode provided by insns[] is correct.
4788 It is not illegal to do "blx pc", just useless. */
4789 if (inst.operands[0].reg == REG_PC)
4790 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4792 inst.instruction |= inst.operands[0].reg;
4796 /* Arg is an address; this instruction cannot be executed
4797 conditionally, and the opcode must be adjusted. */
4798 constraint (inst.cond != COND_ALWAYS, BAD_COND);
4799 inst.instruction = 0xfa000000;
4801 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4802 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4805 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
4812 if (inst.operands[0].reg == REG_PC)
4813 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4815 inst.instruction |= inst.operands[0].reg;
4819 /* ARM v5TEJ. Jump to Jazelle code. */
4824 if (inst.operands[0].reg == REG_PC)
4825 as_tsktsk (_("use of r15 in bxj is not really useful"));
4827 inst.instruction |= inst.operands[0].reg;
4830 /* Co-processor data operation:
4831 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4832 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4836 inst.instruction |= inst.operands[0].reg << 8;
4837 inst.instruction |= inst.operands[1].imm << 20;
4838 inst.instruction |= inst.operands[2].reg << 12;
4839 inst.instruction |= inst.operands[3].reg << 16;
4840 inst.instruction |= inst.operands[4].reg;
4841 inst.instruction |= inst.operands[5].imm << 5;
4847 inst.instruction |= inst.operands[0].reg << 16;
4848 encode_arm_shifter_operand (1);
4851 /* Transfer between coprocessor and ARM registers.
4852 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4857 No special properties. */
4862 inst.instruction |= inst.operands[0].reg << 8;
4863 inst.instruction |= inst.operands[1].imm << 21;
4864 inst.instruction |= inst.operands[2].reg << 12;
4865 inst.instruction |= inst.operands[3].reg << 16;
4866 inst.instruction |= inst.operands[4].reg;
4867 inst.instruction |= inst.operands[5].imm << 5;
4870 /* Transfer between coprocessor register and pair of ARM registers.
4871 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4876 Two XScale instructions are special cases of these:
4878 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4879 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4881 Result unpredicatable if Rd or Rn is R15. */
4886 inst.instruction |= inst.operands[0].reg << 8;
4887 inst.instruction |= inst.operands[1].imm << 4;
4888 inst.instruction |= inst.operands[2].reg << 12;
4889 inst.instruction |= inst.operands[3].reg << 16;
4890 inst.instruction |= inst.operands[4].reg;
4896 inst.instruction |= inst.operands[0].imm << 6;
4897 inst.instruction |= inst.operands[1].imm;
4903 inst.instruction |= inst.operands[0].imm;
4909 /* There is no IT instruction in ARM mode. We
4910 process it but do not generate code for it. */
4917 int base_reg = inst.operands[0].reg;
4918 int range = inst.operands[1].imm;
4920 inst.instruction |= base_reg << 16;
4921 inst.instruction |= range;
4923 if (inst.operands[1].writeback)
4924 inst.instruction |= LDM_TYPE_2_OR_3;
4926 if (inst.operands[0].writeback)
4928 inst.instruction |= WRITE_BACK;
4929 /* Check for unpredictable uses of writeback. */
4930 if (inst.instruction & LOAD_BIT)
4932 /* Not allowed in LDM type 2. */
4933 if ((inst.instruction & LDM_TYPE_2_OR_3)
4934 && ((range & (1 << REG_PC)) == 0))
4935 as_warn (_("writeback of base register is UNPREDICTABLE"));
4936 /* Only allowed if base reg not in list for other types. */
4937 else if (range & (1 << base_reg))
4938 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4942 /* Not allowed for type 2. */
4943 if (inst.instruction & LDM_TYPE_2_OR_3)
4944 as_warn (_("writeback of base register is UNPREDICTABLE"));
4945 /* Only allowed if base reg not in list, or first in list. */
4946 else if ((range & (1 << base_reg))
4947 && (range & ((1 << base_reg) - 1)))
4948 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4953 /* ARMv5TE load-consecutive (argument parse)
4962 constraint (inst.operands[0].reg % 2 != 0,
4963 _("first destination register must be even"));
4964 constraint (inst.operands[1].present
4965 && inst.operands[1].reg != inst.operands[0].reg + 1,
4966 _("can only load two consecutive registers"));
4967 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4968 constraint (!inst.operands[2].isreg, _("'[' expected"));
4970 if (!inst.operands[1].present)
4971 inst.operands[1].reg = inst.operands[0].reg + 1;
4973 if (inst.instruction & LOAD_BIT)
4975 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4976 register and the first register written; we have to diagnose
4977 overlap between the base and the second register written here. */
4979 if (inst.operands[2].reg == inst.operands[1].reg
4980 && (inst.operands[2].writeback || inst.operands[2].postind))
4981 as_warn (_("base register written back, and overlaps "
4982 "second destination register"));
4984 /* For an index-register load, the index register must not overlap the
4985 destination (even if not write-back). */
4986 else if (inst.operands[2].immisreg
4987 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
4988 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
4989 as_warn (_("index register overlaps destination register"));
4992 inst.instruction |= inst.operands[0].reg << 12;
4993 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
4999 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
5000 || inst.operands[1].postind || inst.operands[1].writeback
5001 || inst.operands[1].immisreg || inst.operands[1].shifted
5002 || inst.operands[1].negative
5003 /* This can arise if the programmer has written
5005 or if they have mistakenly used a register name as the last
5008 It is very difficult to distinguish between these two cases
5009 because "rX" might actually be a label. ie the register
5010 name has been occluded by a symbol of the same name. So we
5011 just generate a general 'bad addressing mode' type error
5012 message and leave it up to the programmer to discover the
5013 true cause and fix their mistake. */
5014 || (inst.operands[1].reg == REG_PC),
5017 constraint (inst.reloc.exp.X_op != O_constant
5018 || inst.reloc.exp.X_add_number != 0,
5019 _("offset must be zero in ARM encoding"));
5021 inst.instruction |= inst.operands[0].reg << 12;
5022 inst.instruction |= inst.operands[1].reg << 16;
5023 inst.reloc.type = BFD_RELOC_UNUSED;
5029 constraint (inst.operands[0].reg % 2 != 0,
5030 _("even register required"));
5031 constraint (inst.operands[1].present
5032 && inst.operands[1].reg != inst.operands[0].reg + 1,
5033 _("can only load two consecutive registers"));
5034 /* If op 1 were present and equal to PC, this function wouldn't
5035 have been called in the first place. */
5036 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
5038 inst.instruction |= inst.operands[0].reg << 12;
5039 inst.instruction |= inst.operands[2].reg << 16;
5045 inst.instruction |= inst.operands[0].reg << 12;
5046 if (!inst.operands[1].isreg)
5047 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
5049 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
5055 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
5057 if (inst.operands[1].preind)
5059 constraint (inst.reloc.exp.X_op != O_constant ||
5060 inst.reloc.exp.X_add_number != 0,
5061 _("this instruction requires a post-indexed address"));
5063 inst.operands[1].preind = 0;
5064 inst.operands[1].postind = 1;
5065 inst.operands[1].writeback = 1;
5067 inst.instruction |= inst.operands[0].reg << 12;
5068 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
5071 /* Halfword and signed-byte load/store operations. */
5076 inst.instruction |= inst.operands[0].reg << 12;
5077 if (!inst.operands[1].isreg)
5078 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
5080 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
5086 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
5088 if (inst.operands[1].preind)
5090 constraint (inst.reloc.exp.X_op != O_constant ||
5091 inst.reloc.exp.X_add_number != 0,
5092 _("this instruction requires a post-indexed address"));
5094 inst.operands[1].preind = 0;
5095 inst.operands[1].postind = 1;
5096 inst.operands[1].writeback = 1;
5098 inst.instruction |= inst.operands[0].reg << 12;
5099 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
5102 /* Co-processor register load/store.
5103 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
5107 inst.instruction |= inst.operands[0].reg << 8;
5108 inst.instruction |= inst.operands[1].reg << 12;
5109 encode_arm_cp_address (2, TRUE, TRUE, 0);
5115 /* This restriction does not apply to mls (nor to mla in v6, but
5116 that's hard to detect at present). */
5117 if (inst.operands[0].reg == inst.operands[1].reg
5118 && !(inst.instruction & 0x00400000))
5119 as_tsktsk (_("rd and rm should be different in mla"));
5121 inst.instruction |= inst.operands[0].reg << 16;
5122 inst.instruction |= inst.operands[1].reg;
5123 inst.instruction |= inst.operands[2].reg << 8;
5124 inst.instruction |= inst.operands[3].reg << 12;
5131 inst.instruction |= inst.operands[0].reg << 12;
5132 encode_arm_shifter_operand (1);
5135 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
5139 inst.instruction |= inst.operands[0].reg << 12;
5140 /* The value is in two pieces: 0:11, 16:19. */
5141 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
5142 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
5148 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
5149 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
5151 _("'CPSR' or 'SPSR' expected"));
5152 inst.instruction |= inst.operands[0].reg << 12;
5153 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
5156 /* Two possible forms:
5157 "{C|S}PSR_<field>, Rm",
5158 "{C|S}PSR_f, #expression". */
5163 inst.instruction |= inst.operands[0].imm;
5164 if (inst.operands[1].isreg)
5165 inst.instruction |= inst.operands[1].reg;
5168 inst.instruction |= INST_IMMEDIATE;
5169 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5170 inst.reloc.pc_rel = 0;
5177 if (!inst.operands[2].present)
5178 inst.operands[2].reg = inst.operands[0].reg;
5179 inst.instruction |= inst.operands[0].reg << 16;
5180 inst.instruction |= inst.operands[1].reg;
5181 inst.instruction |= inst.operands[2].reg << 8;
5183 if (inst.operands[0].reg == inst.operands[1].reg)
5184 as_tsktsk (_("rd and rm should be different in mul"));
5187 /* Long Multiply Parser
5188 UMULL RdLo, RdHi, Rm, Rs
5189 SMULL RdLo, RdHi, Rm, Rs
5190 UMLAL RdLo, RdHi, Rm, Rs
5191 SMLAL RdLo, RdHi, Rm, Rs. */
5196 inst.instruction |= inst.operands[0].reg << 12;
5197 inst.instruction |= inst.operands[1].reg << 16;
5198 inst.instruction |= inst.operands[2].reg;
5199 inst.instruction |= inst.operands[3].reg << 8;
5201 /* rdhi, rdlo and rm must all be different. */
5202 if (inst.operands[0].reg == inst.operands[1].reg
5203 || inst.operands[0].reg == inst.operands[2].reg
5204 || inst.operands[1].reg == inst.operands[2].reg)
5205 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
5211 if (inst.operands[0].present)
5213 /* Architectural NOP hints are CPSR sets with no bits selected. */
5214 inst.instruction &= 0xf0000000;
5215 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
5219 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
5220 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
5221 Condition defaults to COND_ALWAYS.
5222 Error if Rd, Rn or Rm are R15. */
5227 inst.instruction |= inst.operands[0].reg << 12;
5228 inst.instruction |= inst.operands[1].reg << 16;
5229 inst.instruction |= inst.operands[2].reg;
5230 if (inst.operands[3].present)
5231 encode_arm_shift (3);
5234 /* ARM V6 PKHTB (Argument Parse). */
5239 if (!inst.operands[3].present)
5241 /* If the shift specifier is omitted, turn the instruction
5242 into pkhbt rd, rm, rn. */
5243 inst.instruction &= 0xfff00010;
5244 inst.instruction |= inst.operands[0].reg << 12;
5245 inst.instruction |= inst.operands[1].reg;
5246 inst.instruction |= inst.operands[2].reg << 16;
5250 inst.instruction |= inst.operands[0].reg << 12;
5251 inst.instruction |= inst.operands[1].reg << 16;
5252 inst.instruction |= inst.operands[2].reg;
5253 encode_arm_shift (3);
5257 /* ARMv5TE: Preload-Cache
5261 Syntactically, like LDR with B=1, W=0, L=1. */
5266 constraint (!inst.operands[0].isreg,
5267 _("'[' expected after PLD mnemonic"));
5268 constraint (inst.operands[0].postind,
5269 _("post-indexed expression used in preload instruction"));
5270 constraint (inst.operands[0].writeback,
5271 _("writeback used in preload instruction"));
5272 constraint (!inst.operands[0].preind,
5273 _("unindexed addressing used in preload instruction"));
5274 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
5277 /* ARMv7: PLI <addr_mode> */
5281 constraint (!inst.operands[0].isreg,
5282 _("'[' expected after PLI mnemonic"));
5283 constraint (inst.operands[0].postind,
5284 _("post-indexed expression used in preload instruction"));
5285 constraint (inst.operands[0].writeback,
5286 _("writeback used in preload instruction"));
5287 constraint (!inst.operands[0].preind,
5288 _("unindexed addressing used in preload instruction"));
5289 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
5290 inst.instruction &= ~PRE_INDEX;
5296 inst.operands[1] = inst.operands[0];
5297 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
5298 inst.operands[0].isreg = 1;
5299 inst.operands[0].writeback = 1;
5300 inst.operands[0].reg = REG_SP;
5304 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
5305 word at the specified address and the following word
5307 Unconditionally executed.
5308 Error if Rn is R15. */
5313 inst.instruction |= inst.operands[0].reg << 16;
5314 if (inst.operands[0].writeback)
5315 inst.instruction |= WRITE_BACK;
5318 /* ARM V6 ssat (argument parse). */
5323 inst.instruction |= inst.operands[0].reg << 12;
5324 inst.instruction |= (inst.operands[1].imm - 1) << 16;
5325 inst.instruction |= inst.operands[2].reg;
5327 if (inst.operands[3].present)
5328 encode_arm_shift (3);
5331 /* ARM V6 usat (argument parse). */
5336 inst.instruction |= inst.operands[0].reg << 12;
5337 inst.instruction |= inst.operands[1].imm << 16;
5338 inst.instruction |= inst.operands[2].reg;
5340 if (inst.operands[3].present)
5341 encode_arm_shift (3);
5344 /* ARM V6 ssat16 (argument parse). */
5349 inst.instruction |= inst.operands[0].reg << 12;
5350 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
5351 inst.instruction |= inst.operands[2].reg;
5357 inst.instruction |= inst.operands[0].reg << 12;
5358 inst.instruction |= inst.operands[1].imm << 16;
5359 inst.instruction |= inst.operands[2].reg;
5362 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5363 preserving the other bits.
5365 setend <endian_specifier>, where <endian_specifier> is either
5371 if (inst.operands[0].imm)
5372 inst.instruction |= 0x200;
5378 unsigned int Rm = (inst.operands[1].present
5379 ? inst.operands[1].reg
5380 : inst.operands[0].reg);
5382 inst.instruction |= inst.operands[0].reg << 12;
5383 inst.instruction |= Rm;
5384 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
5386 inst.instruction |= inst.operands[2].reg << 8;
5387 inst.instruction |= SHIFT_BY_REG;
5390 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
5396 inst.reloc.type = BFD_RELOC_ARM_SMC;
5397 inst.reloc.pc_rel = 0;
5403 inst.reloc.type = BFD_RELOC_ARM_SWI;
5404 inst.reloc.pc_rel = 0;
5407 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5408 SMLAxy{cond} Rd,Rm,Rs,Rn
5409 SMLAWy{cond} Rd,Rm,Rs,Rn
5410 Error if any register is R15. */
5415 inst.instruction |= inst.operands[0].reg << 16;
5416 inst.instruction |= inst.operands[1].reg;
5417 inst.instruction |= inst.operands[2].reg << 8;
5418 inst.instruction |= inst.operands[3].reg << 12;
5421 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5422 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5423 Error if any register is R15.
5424 Warning if Rdlo == Rdhi. */
5429 inst.instruction |= inst.operands[0].reg << 12;
5430 inst.instruction |= inst.operands[1].reg << 16;
5431 inst.instruction |= inst.operands[2].reg;
5432 inst.instruction |= inst.operands[3].reg << 8;
5434 if (inst.operands[0].reg == inst.operands[1].reg)
5435 as_tsktsk (_("rdhi and rdlo must be different"));
5438 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5439 SMULxy{cond} Rd,Rm,Rs
5440 Error if any register is R15. */
5445 inst.instruction |= inst.operands[0].reg << 16;
5446 inst.instruction |= inst.operands[1].reg;
5447 inst.instruction |= inst.operands[2].reg << 8;
5450 /* ARM V6 srs (argument parse). */
5455 inst.instruction |= inst.operands[0].imm;
5456 if (inst.operands[0].writeback)
5457 inst.instruction |= WRITE_BACK;
5460 /* ARM V6 strex (argument parse). */
5465 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5466 || inst.operands[2].postind || inst.operands[2].writeback
5467 || inst.operands[2].immisreg || inst.operands[2].shifted
5468 || inst.operands[2].negative
5469 /* See comment in do_ldrex(). */
5470 || (inst.operands[2].reg == REG_PC),
5473 constraint (inst.operands[0].reg == inst.operands[1].reg
5474 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
5476 constraint (inst.reloc.exp.X_op != O_constant
5477 || inst.reloc.exp.X_add_number != 0,
5478 _("offset must be zero in ARM encoding"));
5480 inst.instruction |= inst.operands[0].reg << 12;
5481 inst.instruction |= inst.operands[1].reg;
5482 inst.instruction |= inst.operands[2].reg << 16;
5483 inst.reloc.type = BFD_RELOC_UNUSED;
5489 constraint (inst.operands[1].reg % 2 != 0,
5490 _("even register required"));
5491 constraint (inst.operands[2].present
5492 && inst.operands[2].reg != inst.operands[1].reg + 1,
5493 _("can only store two consecutive registers"));
5494 /* If op 2 were present and equal to PC, this function wouldn't
5495 have been called in the first place. */
5496 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
5498 constraint (inst.operands[0].reg == inst.operands[1].reg
5499 || inst.operands[0].reg == inst.operands[1].reg + 1
5500 || inst.operands[0].reg == inst.operands[3].reg,
5503 inst.instruction |= inst.operands[0].reg << 12;
5504 inst.instruction |= inst.operands[1].reg;
5505 inst.instruction |= inst.operands[3].reg << 16;
5508 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5509 extends it to 32-bits, and adds the result to a value in another
5510 register. You can specify a rotation by 0, 8, 16, or 24 bits
5511 before extracting the 16-bit value.
5512 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5513 Condition defaults to COND_ALWAYS.
5514 Error if any register uses R15. */
5519 inst.instruction |= inst.operands[0].reg << 12;
5520 inst.instruction |= inst.operands[1].reg << 16;
5521 inst.instruction |= inst.operands[2].reg;
5522 inst.instruction |= inst.operands[3].imm << 10;
5527 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5528 Condition defaults to COND_ALWAYS.
5529 Error if any register uses R15. */
5534 inst.instruction |= inst.operands[0].reg << 12;
5535 inst.instruction |= inst.operands[1].reg;
5536 inst.instruction |= inst.operands[2].imm << 10;
5539 /* VFP instructions. In a logical order: SP variant first, monad
5540 before dyad, arithmetic then move then load/store. */
5543 do_vfp_sp_monadic (void)
5545 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5546 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5550 do_vfp_sp_dyadic (void)
5552 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5553 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5554 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5558 do_vfp_sp_compare_z (void)
5560 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5564 do_vfp_dp_sp_cvt (void)
5566 inst.instruction |= inst.operands[0].reg << 12;
5567 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5571 do_vfp_sp_dp_cvt (void)
5573 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5574 inst.instruction |= inst.operands[1].reg;
5578 do_vfp_reg_from_sp (void)
5580 inst.instruction |= inst.operands[0].reg << 12;
5581 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5585 do_vfp_reg2_from_sp2 (void)
5587 constraint (inst.operands[2].imm != 2,
5588 _("only two consecutive VFP SP registers allowed here"));
5589 inst.instruction |= inst.operands[0].reg << 12;
5590 inst.instruction |= inst.operands[1].reg << 16;
5591 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5595 do_vfp_sp_from_reg (void)
5597 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5598 inst.instruction |= inst.operands[1].reg << 12;
5602 do_vfp_sp2_from_reg2 (void)
5604 constraint (inst.operands[0].imm != 2,
5605 _("only two consecutive VFP SP registers allowed here"));
5606 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5607 inst.instruction |= inst.operands[1].reg << 12;
5608 inst.instruction |= inst.operands[2].reg << 16;
5612 do_vfp_sp_ldst (void)
5614 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5615 encode_arm_cp_address (1, FALSE, TRUE, 0);
5619 do_vfp_dp_ldst (void)
5621 inst.instruction |= inst.operands[0].reg << 12;
5622 encode_arm_cp_address (1, FALSE, TRUE, 0);
5627 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
5629 if (inst.operands[0].writeback)
5630 inst.instruction |= WRITE_BACK;
5632 constraint (ldstm_type != VFP_LDSTMIA,
5633 _("this addressing mode requires base-register writeback"));
5634 inst.instruction |= inst.operands[0].reg << 16;
5635 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5636 inst.instruction |= inst.operands[1].imm;
5640 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
5644 if (inst.operands[0].writeback)
5645 inst.instruction |= WRITE_BACK;
5647 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5648 _("this addressing mode requires base-register writeback"));
5650 inst.instruction |= inst.operands[0].reg << 16;
5651 inst.instruction |= inst.operands[1].reg << 12;
5653 count = inst.operands[1].imm << 1;
5654 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5657 inst.instruction |= count;
5661 do_vfp_sp_ldstmia (void)
5663 vfp_sp_ldstm (VFP_LDSTMIA);
5667 do_vfp_sp_ldstmdb (void)
5669 vfp_sp_ldstm (VFP_LDSTMDB);
5673 do_vfp_dp_ldstmia (void)
5675 vfp_dp_ldstm (VFP_LDSTMIA);
5679 do_vfp_dp_ldstmdb (void)
5681 vfp_dp_ldstm (VFP_LDSTMDB);
5685 do_vfp_xp_ldstmia (void)
5687 vfp_dp_ldstm (VFP_LDSTMIAX);
5691 do_vfp_xp_ldstmdb (void)
5693 vfp_dp_ldstm (VFP_LDSTMDBX);
5696 /* FPA instructions. Also in a logical order. */
5701 inst.instruction |= inst.operands[0].reg << 16;
5702 inst.instruction |= inst.operands[1].reg;
5706 do_fpa_ldmstm (void)
5708 inst.instruction |= inst.operands[0].reg << 12;
5709 switch (inst.operands[1].imm)
5711 case 1: inst.instruction |= CP_T_X; break;
5712 case 2: inst.instruction |= CP_T_Y; break;
5713 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5718 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5720 /* The instruction specified "ea" or "fd", so we can only accept
5721 [Rn]{!}. The instruction does not really support stacking or
5722 unstacking, so we have to emulate these by setting appropriate
5723 bits and offsets. */
5724 constraint (inst.reloc.exp.X_op != O_constant
5725 || inst.reloc.exp.X_add_number != 0,
5726 _("this instruction does not support indexing"));
5728 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5729 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
5731 if (!(inst.instruction & INDEX_UP))
5732 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
5734 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5736 inst.operands[2].preind = 0;
5737 inst.operands[2].postind = 1;
5741 encode_arm_cp_address (2, TRUE, TRUE, 0);
5744 /* iWMMXt instructions: strictly in alphabetical order. */
5747 do_iwmmxt_tandorc (void)
5749 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5753 do_iwmmxt_textrc (void)
5755 inst.instruction |= inst.operands[0].reg << 12;
5756 inst.instruction |= inst.operands[1].imm;
5760 do_iwmmxt_textrm (void)
5762 inst.instruction |= inst.operands[0].reg << 12;
5763 inst.instruction |= inst.operands[1].reg << 16;
5764 inst.instruction |= inst.operands[2].imm;
5768 do_iwmmxt_tinsr (void)
5770 inst.instruction |= inst.operands[0].reg << 16;
5771 inst.instruction |= inst.operands[1].reg << 12;
5772 inst.instruction |= inst.operands[2].imm;
5776 do_iwmmxt_tmia (void)
5778 inst.instruction |= inst.operands[0].reg << 5;
5779 inst.instruction |= inst.operands[1].reg;
5780 inst.instruction |= inst.operands[2].reg << 12;
5784 do_iwmmxt_waligni (void)
5786 inst.instruction |= inst.operands[0].reg << 12;
5787 inst.instruction |= inst.operands[1].reg << 16;
5788 inst.instruction |= inst.operands[2].reg;
5789 inst.instruction |= inst.operands[3].imm << 20;
5793 do_iwmmxt_wmov (void)
5795 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5796 inst.instruction |= inst.operands[0].reg << 12;
5797 inst.instruction |= inst.operands[1].reg << 16;
5798 inst.instruction |= inst.operands[1].reg;
5802 do_iwmmxt_wldstbh (void)
5805 inst.instruction |= inst.operands[0].reg << 12;
5807 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
5809 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
5810 encode_arm_cp_address (1, TRUE, FALSE, reloc);
5814 do_iwmmxt_wldstw (void)
5816 /* RIWR_RIWC clears .isreg for a control register. */
5817 if (!inst.operands[0].isreg)
5819 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5820 inst.instruction |= 0xf0000000;
5823 inst.instruction |= inst.operands[0].reg << 12;
5824 encode_arm_cp_address (1, TRUE, TRUE, 0);
5828 do_iwmmxt_wldstd (void)
5830 inst.instruction |= inst.operands[0].reg << 12;
5831 encode_arm_cp_address (1, TRUE, FALSE, 0);
5835 do_iwmmxt_wshufh (void)
5837 inst.instruction |= inst.operands[0].reg << 12;
5838 inst.instruction |= inst.operands[1].reg << 16;
5839 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5840 inst.instruction |= (inst.operands[2].imm & 0x0f);
5844 do_iwmmxt_wzero (void)
5846 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5847 inst.instruction |= inst.operands[0].reg;
5848 inst.instruction |= inst.operands[0].reg << 12;
5849 inst.instruction |= inst.operands[0].reg << 16;
5852 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5853 operations first, then control, shift, and load/store. */
5855 /* Insns like "foo X,Y,Z". */
5858 do_mav_triple (void)
5860 inst.instruction |= inst.operands[0].reg << 16;
5861 inst.instruction |= inst.operands[1].reg;
5862 inst.instruction |= inst.operands[2].reg << 12;
5865 /* Insns like "foo W,X,Y,Z".
5866 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5871 inst.instruction |= inst.operands[0].reg << 5;
5872 inst.instruction |= inst.operands[1].reg << 12;
5873 inst.instruction |= inst.operands[2].reg << 16;
5874 inst.instruction |= inst.operands[3].reg;
5877 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5881 inst.instruction |= inst.operands[1].reg << 12;
5884 /* Maverick shift immediate instructions.
5885 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5886 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5891 int imm = inst.operands[2].imm;
5893 inst.instruction |= inst.operands[0].reg << 12;
5894 inst.instruction |= inst.operands[1].reg << 16;
5896 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5897 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5898 Bit 4 should be 0. */
5899 imm = (imm & 0xf) | ((imm & 0x70) << 1);
5901 inst.instruction |= imm;
5904 /* XScale instructions. Also sorted arithmetic before move. */
5906 /* Xscale multiply-accumulate (argument parse)
5909 MIAxycc acc0,Rm,Rs. */
5914 inst.instruction |= inst.operands[1].reg;
5915 inst.instruction |= inst.operands[2].reg << 12;
5918 /* Xscale move-accumulator-register (argument parse)
5920 MARcc acc0,RdLo,RdHi. */
5925 inst.instruction |= inst.operands[1].reg << 12;
5926 inst.instruction |= inst.operands[2].reg << 16;
5929 /* Xscale move-register-accumulator (argument parse)
5931 MRAcc RdLo,RdHi,acc0. */
5936 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5937 inst.instruction |= inst.operands[0].reg << 12;
5938 inst.instruction |= inst.operands[1].reg << 16;
5941 /* Encoding functions relevant only to Thumb. */
5943 /* inst.operands[i] is a shifted-register operand; encode
5944 it into inst.instruction in the format used by Thumb32. */
5947 encode_thumb32_shifted_operand (int i)
5949 unsigned int value = inst.reloc.exp.X_add_number;
5950 unsigned int shift = inst.operands[i].shift_kind;
5952 constraint (inst.operands[i].immisreg,
5953 _("shift by register not allowed in thumb mode"));
5954 inst.instruction |= inst.operands[i].reg;
5955 if (shift == SHIFT_RRX)
5956 inst.instruction |= SHIFT_ROR << 4;
5959 constraint (inst.reloc.exp.X_op != O_constant,
5960 _("expression too complex"));
5962 constraint (value > 32
5963 || (value == 32 && (shift == SHIFT_LSL
5964 || shift == SHIFT_ROR)),
5965 _("shift expression is too large"));
5969 else if (value == 32)
5972 inst.instruction |= shift << 4;
5973 inst.instruction |= (value & 0x1c) << 10;
5974 inst.instruction |= (value & 0x03) << 6;
5979 /* inst.operands[i] was set up by parse_address. Encode it into a
5980 Thumb32 format load or store instruction. Reject forms that cannot
5981 be used with such instructions. If is_t is true, reject forms that
5982 cannot be used with a T instruction; if is_d is true, reject forms
5983 that cannot be used with a D instruction. */
5986 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5988 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5990 constraint (!inst.operands[i].isreg,
5991 _("Instruction does not support =N addresses"));
5993 inst.instruction |= inst.operands[i].reg << 16;
5994 if (inst.operands[i].immisreg)
5996 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5997 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5998 constraint (inst.operands[i].negative,
5999 _("Thumb does not support negative register indexing"));
6000 constraint (inst.operands[i].postind,
6001 _("Thumb does not support register post-indexing"));
6002 constraint (inst.operands[i].writeback,
6003 _("Thumb does not support register indexing with writeback"));
6004 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
6005 _("Thumb supports only LSL in shifted register indexing"));
6007 inst.instruction |= inst.operands[i].imm;
6008 if (inst.operands[i].shifted)
6010 constraint (inst.reloc.exp.X_op != O_constant,
6011 _("expression too complex"));
6012 constraint (inst.reloc.exp.X_add_number < 0
6013 || inst.reloc.exp.X_add_number > 3,
6014 _("shift out of range"));
6015 inst.instruction |= inst.reloc.exp.X_add_number << 4;
6017 inst.reloc.type = BFD_RELOC_UNUSED;
6019 else if (inst.operands[i].preind)
6021 constraint (is_pc && inst.operands[i].writeback,
6022 _("cannot use writeback with PC-relative addressing"));
6023 constraint (is_t && inst.operands[i].writeback,
6024 _("cannot use writeback with this instruction"));
6028 inst.instruction |= 0x01000000;
6029 if (inst.operands[i].writeback)
6030 inst.instruction |= 0x00200000;
6034 inst.instruction |= 0x00000c00;
6035 if (inst.operands[i].writeback)
6036 inst.instruction |= 0x00000100;
6038 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
6040 else if (inst.operands[i].postind)
6042 assert (inst.operands[i].writeback);
6043 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
6044 constraint (is_t, _("cannot use post-indexing with this instruction"));
6047 inst.instruction |= 0x00200000;
6049 inst.instruction |= 0x00000900;
6050 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
6052 else /* unindexed - only for coprocessor */
6053 inst.error = _("instruction does not accept unindexed addressing");
6056 /* Table of Thumb instructions which exist in both 16- and 32-bit
6057 encodings (the latter only in post-V6T2 cores). The index is the
6058 value used in the insns table below. When there is more than one
6059 possible 16-bit encoding for the instruction, this table always
6061 Also contains several pseudo-instructions used during relaxation. */
6062 #define T16_32_TAB \
6063 X(adc, 4140, eb400000), \
6064 X(adcs, 4140, eb500000), \
6065 X(add, 1c00, eb000000), \
6066 X(adds, 1c00, eb100000), \
6067 X(addi, 0000, f1000000), \
6068 X(addis, 0000, f1100000), \
6069 X(add_pc,000f, f20f0000), \
6070 X(add_sp,000d, f10d0000), \
6071 X(adr, 000f, f20f0000), \
6072 X(and, 4000, ea000000), \
6073 X(ands, 4000, ea100000), \
6074 X(asr, 1000, fa40f000), \
6075 X(asrs, 1000, fa50f000), \
6076 X(b, e000, f000b000), \
6077 X(bcond, d000, f0008000), \
6078 X(bic, 4380, ea200000), \
6079 X(bics, 4380, ea300000), \
6080 X(cmn, 42c0, eb100f00), \
6081 X(cmp, 2800, ebb00f00), \
6082 X(cpsie, b660, f3af8400), \
6083 X(cpsid, b670, f3af8600), \
6084 X(cpy, 4600, ea4f0000), \
6085 X(dec_sp,80dd, f1bd0d00), \
6086 X(eor, 4040, ea800000), \
6087 X(eors, 4040, ea900000), \
6088 X(inc_sp,00dd, f10d0d00), \
6089 X(ldmia, c800, e8900000), \
6090 X(ldr, 6800, f8500000), \
6091 X(ldrb, 7800, f8100000), \
6092 X(ldrh, 8800, f8300000), \
6093 X(ldrsb, 5600, f9100000), \
6094 X(ldrsh, 5e00, f9300000), \
6095 X(ldr_pc,4800, f85f0000), \
6096 X(ldr_pc2,4800, f85f0000), \
6097 X(ldr_sp,9800, f85d0000), \
6098 X(lsl, 0000, fa00f000), \
6099 X(lsls, 0000, fa10f000), \
6100 X(lsr, 0800, fa20f000), \
6101 X(lsrs, 0800, fa30f000), \
6102 X(mov, 2000, ea4f0000), \
6103 X(movs, 2000, ea5f0000), \
6104 X(mul, 4340, fb00f000), \
6105 X(muls, 4340, ffffffff), /* no 32b muls */ \
6106 X(mvn, 43c0, ea6f0000), \
6107 X(mvns, 43c0, ea7f0000), \
6108 X(neg, 4240, f1c00000), /* rsb #0 */ \
6109 X(negs, 4240, f1d00000), /* rsbs #0 */ \
6110 X(orr, 4300, ea400000), \
6111 X(orrs, 4300, ea500000), \
6112 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
6113 X(push, b400, e92d0000), /* stmdb sp!,... */ \
6114 X(rev, ba00, fa90f080), \
6115 X(rev16, ba40, fa90f090), \
6116 X(revsh, bac0, fa90f0b0), \
6117 X(ror, 41c0, fa60f000), \
6118 X(rors, 41c0, fa70f000), \
6119 X(sbc, 4180, eb600000), \
6120 X(sbcs, 4180, eb700000), \
6121 X(stmia, c000, e8800000), \
6122 X(str, 6000, f8400000), \
6123 X(strb, 7000, f8000000), \
6124 X(strh, 8000, f8200000), \
6125 X(str_sp,9000, f84d0000), \
6126 X(sub, 1e00, eba00000), \
6127 X(subs, 1e00, ebb00000), \
6128 X(subi, 8000, f1a00000), \
6129 X(subis, 8000, f1b00000), \
6130 X(sxtb, b240, fa4ff080), \
6131 X(sxth, b200, fa0ff080), \
6132 X(tst, 4200, ea100f00), \
6133 X(uxtb, b2c0, fa5ff080), \
6134 X(uxth, b280, fa1ff080), \
6135 X(nop, bf00, f3af8000), \
6136 X(yield, bf10, f3af8001), \
6137 X(wfe, bf20, f3af8002), \
6138 X(wfi, bf30, f3af8003), \
6139 X(sev, bf40, f3af9004), /* typo, 8004? */
6141 /* To catch errors in encoding functions, the codes are all offset by
6142 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
6143 as 16-bit instructions. */
6144 #define X(a,b,c) T_MNEM_##a
6145 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
6148 #define X(a,b,c) 0x##b
6149 static const unsigned short thumb_op16[] = { T16_32_TAB };
6150 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
6153 #define X(a,b,c) 0x##c
6154 static const unsigned int thumb_op32[] = { T16_32_TAB };
6155 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
6156 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
6160 /* Thumb instruction encoders, in alphabetical order. */
6164 do_t_add_sub_w (void)
6168 Rd = inst.operands[0].reg;
6169 Rn = inst.operands[1].reg;
6171 constraint (Rd == 15, _("PC not allowed as destination"));
6172 inst.instruction |= (Rn << 16) | (Rd << 8);
6173 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
6176 /* Parse an add or subtract instruction. We get here with inst.instruction
6177 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
6184 Rd = inst.operands[0].reg;
6185 Rs = (inst.operands[1].present
6186 ? inst.operands[1].reg /* Rd, Rs, foo */
6187 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6195 flags = (inst.instruction == T_MNEM_adds
6196 || inst.instruction == T_MNEM_subs);
6198 narrow = (current_it_mask == 0);
6200 narrow = (current_it_mask != 0);
6201 if (!inst.operands[2].isreg)
6204 if (inst.size_req != 4)
6208 add = (inst.instruction == T_MNEM_add
6209 || inst.instruction == T_MNEM_adds);
6210 /* Attempt to use a narrow opcode, with relaxation if
6212 if (Rd == REG_SP && Rs == REG_SP && !flags)
6213 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
6214 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
6215 opcode = T_MNEM_add_sp;
6216 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
6217 opcode = T_MNEM_add_pc;
6218 else if (Rd <= 7 && Rs <= 7 && narrow)
6221 opcode = add ? T_MNEM_addis : T_MNEM_subis;
6223 opcode = add ? T_MNEM_addi : T_MNEM_subi;
6227 inst.instruction = THUMB_OP16(opcode);
6228 inst.instruction |= (Rd << 4) | Rs;
6229 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6230 if (inst.size_req != 2)
6231 inst.relax = opcode;
6234 constraint (inst.size_req == 2, BAD_HIREG);
6236 if (inst.size_req == 4
6237 || (inst.size_req != 2 && !opcode))
6239 /* ??? Convert large immediates to addw/subw. */
6240 inst.instruction = THUMB_OP32 (inst.instruction);
6241 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6242 inst.instruction |= inst.operands[0].reg << 8;
6243 inst.instruction |= inst.operands[1].reg << 16;
6244 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6249 Rn = inst.operands[2].reg;
6250 /* See if we can do this with a 16-bit instruction. */
6251 if (!inst.operands[2].shifted && inst.size_req != 4)
6253 if (Rd > 7 || Rs > 7 || Rn > 7)
6258 inst.instruction = ((inst.instruction == T_MNEM_adds
6259 || inst.instruction == T_MNEM_add)
6262 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6266 if (inst.instruction == T_MNEM_add)
6270 inst.instruction = T_OPCODE_ADD_HI;
6271 inst.instruction |= (Rd & 8) << 4;
6272 inst.instruction |= (Rd & 7);
6273 inst.instruction |= Rn << 3;
6276 /* ... because addition is commutative! */
6279 inst.instruction = T_OPCODE_ADD_HI;
6280 inst.instruction |= (Rd & 8) << 4;
6281 inst.instruction |= (Rd & 7);
6282 inst.instruction |= Rs << 3;
6287 /* If we get here, it can't be done in 16 bits. */
6288 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
6289 _("shift must be constant"));
6290 inst.instruction = THUMB_OP32 (inst.instruction);
6291 inst.instruction |= Rd << 8;
6292 inst.instruction |= Rs << 16;
6293 encode_thumb32_shifted_operand (2);
6298 constraint (inst.instruction == T_MNEM_adds
6299 || inst.instruction == T_MNEM_subs,
6302 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
6304 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
6305 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
6308 inst.instruction = (inst.instruction == T_MNEM_add
6310 inst.instruction |= (Rd << 4) | Rs;
6311 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6315 Rn = inst.operands[2].reg;
6316 constraint (inst.operands[2].shifted, _("unshifted register required"));
6318 /* We now have Rd, Rs, and Rn set to registers. */
6319 if (Rd > 7 || Rs > 7 || Rn > 7)
6321 /* Can't do this for SUB. */
6322 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
6323 inst.instruction = T_OPCODE_ADD_HI;
6324 inst.instruction |= (Rd & 8) << 4;
6325 inst.instruction |= (Rd & 7);
6327 inst.instruction |= Rn << 3;
6329 inst.instruction |= Rs << 3;
6331 constraint (1, _("dest must overlap one source register"));
6335 inst.instruction = (inst.instruction == T_MNEM_add
6336 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
6337 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6345 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
6347 /* Defer to section relaxation. */
6348 inst.relax = inst.instruction;
6349 inst.instruction = THUMB_OP16 (inst.instruction);
6350 inst.instruction |= inst.operands[0].reg << 4;
6352 else if (unified_syntax && inst.size_req != 2)
6354 /* Generate a 32-bit opcode. */
6355 inst.instruction = THUMB_OP32 (inst.instruction);
6356 inst.instruction |= inst.operands[0].reg << 8;
6357 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
6358 inst.reloc.pc_rel = 1;
6362 /* Generate a 16-bit opcode. */
6363 inst.instruction = THUMB_OP16 (inst.instruction);
6364 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6365 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
6366 inst.reloc.pc_rel = 1;
6368 inst.instruction |= inst.operands[0].reg << 4;
6372 /* Arithmetic instructions for which there is just one 16-bit
6373 instruction encoding, and it allows only two low registers.
6374 For maximal compatibility with ARM syntax, we allow three register
6375 operands even when Thumb-32 instructions are not available, as long
6376 as the first two are identical. For instance, both "sbc r0,r1" and
6377 "sbc r0,r0,r1" are allowed. */
6383 Rd = inst.operands[0].reg;
6384 Rs = (inst.operands[1].present
6385 ? inst.operands[1].reg /* Rd, Rs, foo */
6386 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6387 Rn = inst.operands[2].reg;
6391 if (!inst.operands[2].isreg)
6393 /* For an immediate, we always generate a 32-bit opcode;
6394 section relaxation will shrink it later if possible. */
6395 inst.instruction = THUMB_OP32 (inst.instruction);
6396 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6397 inst.instruction |= Rd << 8;
6398 inst.instruction |= Rs << 16;
6399 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6405 /* See if we can do this with a 16-bit instruction. */
6406 if (THUMB_SETS_FLAGS (inst.instruction))
6407 narrow = current_it_mask == 0;
6409 narrow = current_it_mask != 0;
6411 if (Rd > 7 || Rn > 7 || Rs > 7)
6413 if (inst.operands[2].shifted)
6415 if (inst.size_req == 4)
6421 inst.instruction = THUMB_OP16 (inst.instruction);
6422 inst.instruction |= Rd;
6423 inst.instruction |= Rn << 3;
6427 /* If we get here, it can't be done in 16 bits. */
6428 constraint (inst.operands[2].shifted
6429 && inst.operands[2].immisreg,
6430 _("shift must be constant"));
6431 inst.instruction = THUMB_OP32 (inst.instruction);
6432 inst.instruction |= Rd << 8;
6433 inst.instruction |= Rs << 16;
6434 encode_thumb32_shifted_operand (2);
6439 /* On its face this is a lie - the instruction does set the
6440 flags. However, the only supported mnemonic in this mode
6442 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6444 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6445 _("unshifted register required"));
6446 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6447 constraint (Rd != Rs,
6448 _("dest and source1 must be the same register"));
6450 inst.instruction = THUMB_OP16 (inst.instruction);
6451 inst.instruction |= Rd;
6452 inst.instruction |= Rn << 3;
6456 /* Similarly, but for instructions where the arithmetic operation is
6457 commutative, so we can allow either of them to be different from
6458 the destination operand in a 16-bit instruction. For instance, all
6459 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6466 Rd = inst.operands[0].reg;
6467 Rs = (inst.operands[1].present
6468 ? inst.operands[1].reg /* Rd, Rs, foo */
6469 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6470 Rn = inst.operands[2].reg;
6474 if (!inst.operands[2].isreg)
6476 /* For an immediate, we always generate a 32-bit opcode;
6477 section relaxation will shrink it later if possible. */
6478 inst.instruction = THUMB_OP32 (inst.instruction);
6479 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6480 inst.instruction |= Rd << 8;
6481 inst.instruction |= Rs << 16;
6482 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6488 /* See if we can do this with a 16-bit instruction. */
6489 if (THUMB_SETS_FLAGS (inst.instruction))
6490 narrow = current_it_mask == 0;
6492 narrow = current_it_mask != 0;
6494 if (Rd > 7 || Rn > 7 || Rs > 7)
6496 if (inst.operands[2].shifted)
6498 if (inst.size_req == 4)
6505 inst.instruction = THUMB_OP16 (inst.instruction);
6506 inst.instruction |= Rd;
6507 inst.instruction |= Rn << 3;
6512 inst.instruction = THUMB_OP16 (inst.instruction);
6513 inst.instruction |= Rd;
6514 inst.instruction |= Rs << 3;
6519 /* If we get here, it can't be done in 16 bits. */
6520 constraint (inst.operands[2].shifted
6521 && inst.operands[2].immisreg,
6522 _("shift must be constant"));
6523 inst.instruction = THUMB_OP32 (inst.instruction);
6524 inst.instruction |= Rd << 8;
6525 inst.instruction |= Rs << 16;
6526 encode_thumb32_shifted_operand (2);
6531 /* On its face this is a lie - the instruction does set the
6532 flags. However, the only supported mnemonic in this mode
6534 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6536 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6537 _("unshifted register required"));
6538 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6540 inst.instruction = THUMB_OP16 (inst.instruction);
6541 inst.instruction |= Rd;
6544 inst.instruction |= Rn << 3;
6546 inst.instruction |= Rs << 3;
6548 constraint (1, _("dest must overlap one source register"));
6555 if (inst.operands[0].present)
6557 constraint ((inst.instruction & 0xf0) != 0x40
6558 && inst.operands[0].imm != 0xf,
6559 "bad barrier type");
6560 inst.instruction |= inst.operands[0].imm;
6563 inst.instruction |= 0xf;
6569 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6570 constraint (msb > 32, _("bit-field extends past end of register"));
6571 /* The instruction encoding stores the LSB and MSB,
6572 not the LSB and width. */
6573 inst.instruction |= inst.operands[0].reg << 8;
6574 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6575 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6576 inst.instruction |= msb - 1;
6584 /* #0 in second position is alternative syntax for bfc, which is
6585 the same instruction but with REG_PC in the Rm field. */
6586 if (!inst.operands[1].isreg)
6587 inst.operands[1].reg = REG_PC;
6589 msb = inst.operands[2].imm + inst.operands[3].imm;
6590 constraint (msb > 32, _("bit-field extends past end of register"));
6591 /* The instruction encoding stores the LSB and MSB,
6592 not the LSB and width. */
6593 inst.instruction |= inst.operands[0].reg << 8;
6594 inst.instruction |= inst.operands[1].reg << 16;
6595 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6596 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6597 inst.instruction |= msb - 1;
6603 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6604 _("bit-field extends past end of register"));
6605 inst.instruction |= inst.operands[0].reg << 8;
6606 inst.instruction |= inst.operands[1].reg << 16;
6607 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6608 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6609 inst.instruction |= inst.operands[3].imm - 1;
6612 /* ARM V5 Thumb BLX (argument parse)
6613 BLX <target_addr> which is BLX(1)
6614 BLX <Rm> which is BLX(2)
6615 Unfortunately, there are two different opcodes for this mnemonic.
6616 So, the insns[].value is not used, and the code here zaps values
6617 into inst.instruction.
6619 ??? How to take advantage of the additional two bits of displacement
6620 available in Thumb32 mode? Need new relocation? */
6625 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
6626 if (inst.operands[0].isreg)
6627 /* We have a register, so this is BLX(2). */
6628 inst.instruction |= inst.operands[0].reg << 3;
6631 /* No register. This must be BLX(1). */
6632 inst.instruction = 0xf000e800;
6634 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6635 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6638 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6639 inst.reloc.pc_rel = 1;
6649 if (current_it_mask)
6651 /* Conditional branches inside IT blocks are encoded as unconditional
6654 /* A branch must be the last instruction in an IT block. */
6655 constraint (current_it_mask != 0x10, BAD_BRANCH);
6660 if (cond != COND_ALWAYS)
6661 opcode = T_MNEM_bcond;
6663 opcode = inst.instruction;
6665 if (unified_syntax && inst.size_req == 4)
6667 inst.instruction = THUMB_OP32(opcode);
6668 if (cond == COND_ALWAYS)
6669 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
6672 assert (cond != 0xF);
6673 inst.instruction |= cond << 22;
6674 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6679 inst.instruction = THUMB_OP16(opcode);
6680 if (cond == COND_ALWAYS)
6681 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6684 inst.instruction |= cond << 8;
6685 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6687 /* Allow section relaxation. */
6688 if (unified_syntax && inst.size_req != 2)
6689 inst.relax = opcode;
6692 inst.reloc.pc_rel = 1;
6698 constraint (inst.cond != COND_ALWAYS,
6699 _("instruction is always unconditional"));
6700 if (inst.operands[0].present)
6702 constraint (inst.operands[0].imm > 255,
6703 _("immediate value out of range"));
6704 inst.instruction |= inst.operands[0].imm;
6709 do_t_branch23 (void)
6711 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
6712 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6713 inst.reloc.pc_rel = 1;
6715 /* If the destination of the branch is a defined symbol which does not have
6716 the THUMB_FUNC attribute, then we must be calling a function which has
6717 the (interfacearm) attribute. We look for the Thumb entry point to that
6718 function and change the branch to refer to that function instead. */
6719 if ( inst.reloc.exp.X_op == O_symbol
6720 && inst.reloc.exp.X_add_symbol != NULL
6721 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6722 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6723 inst.reloc.exp.X_add_symbol =
6724 find_real_start (inst.reloc.exp.X_add_symbol);
6730 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
6731 inst.instruction |= inst.operands[0].reg << 3;
6732 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6733 should cause the alignment to be checked once it is known. This is
6734 because BX PC only works if the instruction is word aligned. */
6740 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
6741 if (inst.operands[0].reg == REG_PC)
6742 as_tsktsk (_("use of r15 in bxj is not really useful"));
6744 inst.instruction |= inst.operands[0].reg << 16;
6750 inst.instruction |= inst.operands[0].reg << 8;
6751 inst.instruction |= inst.operands[1].reg << 16;
6752 inst.instruction |= inst.operands[1].reg;
6758 constraint (current_it_mask, BAD_NOT_IT);
6759 inst.instruction |= inst.operands[0].imm;
6765 constraint (current_it_mask, BAD_NOT_IT);
6767 && (inst.operands[1].present || inst.size_req == 4)
6768 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
6770 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6771 inst.instruction = 0xf3af8000;
6772 inst.instruction |= imod << 9;
6773 inst.instruction |= inst.operands[0].imm << 5;
6774 if (inst.operands[1].present)
6775 inst.instruction |= 0x100 | inst.operands[1].imm;
6779 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
6780 && (inst.operands[0].imm & 4),
6781 _("selected processor does not support 'A' form "
6782 "of this instruction"));
6783 constraint (inst.operands[1].present || inst.size_req == 4,
6784 _("Thumb does not support the 2-argument "
6785 "form of this instruction"));
6786 inst.instruction |= inst.operands[0].imm;
6790 /* THUMB CPY instruction (argument parse). */
6795 if (inst.size_req == 4)
6797 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6798 inst.instruction |= inst.operands[0].reg << 8;
6799 inst.instruction |= inst.operands[1].reg;
6803 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6804 inst.instruction |= (inst.operands[0].reg & 0x7);
6805 inst.instruction |= inst.operands[1].reg << 3;
6812 constraint (current_it_mask, BAD_NOT_IT);
6813 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6814 inst.instruction |= inst.operands[0].reg;
6815 inst.reloc.pc_rel = 1;
6816 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6822 inst.instruction |= inst.operands[0].imm;
6828 if (!inst.operands[1].present)
6829 inst.operands[1].reg = inst.operands[0].reg;
6830 inst.instruction |= inst.operands[0].reg << 8;
6831 inst.instruction |= inst.operands[1].reg << 16;
6832 inst.instruction |= inst.operands[2].reg;
6838 if (unified_syntax && inst.size_req == 4)
6839 inst.instruction = THUMB_OP32 (inst.instruction);
6841 inst.instruction = THUMB_OP16 (inst.instruction);
6847 unsigned int cond = inst.operands[0].imm;
6849 constraint (current_it_mask, BAD_NOT_IT);
6850 current_it_mask = (inst.instruction & 0xf) | 0x10;
6853 /* If the condition is a negative condition, invert the mask. */
6854 if ((cond & 0x1) == 0x0)
6856 unsigned int mask = inst.instruction & 0x000f;
6858 if ((mask & 0x7) == 0)
6859 /* no conversion needed */;
6860 else if ((mask & 0x3) == 0)
6862 else if ((mask & 0x1) == 0)
6867 inst.instruction &= 0xfff0;
6868 inst.instruction |= mask;
6871 inst.instruction |= cond << 4;
6877 /* This really doesn't seem worth it. */
6878 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6879 _("expression too complex"));
6880 constraint (inst.operands[1].writeback,
6881 _("Thumb load/store multiple does not support {reglist}^"));
6885 /* See if we can use a 16-bit instruction. */
6886 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6887 && inst.size_req != 4
6888 && inst.operands[0].reg <= 7
6889 && !(inst.operands[1].imm & ~0xff)
6890 && (inst.instruction == T_MNEM_stmia
6891 ? inst.operands[0].writeback
6892 : (inst.operands[0].writeback
6893 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
6895 if (inst.instruction == T_MNEM_stmia
6896 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6897 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6898 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6899 inst.operands[0].reg);
6901 inst.instruction = THUMB_OP16 (inst.instruction);
6902 inst.instruction |= inst.operands[0].reg << 8;
6903 inst.instruction |= inst.operands[1].imm;
6907 if (inst.operands[1].imm & (1 << 13))
6908 as_warn (_("SP should not be in register list"));
6909 if (inst.instruction == T_MNEM_stmia)
6911 if (inst.operands[1].imm & (1 << 15))
6912 as_warn (_("PC should not be in register list"));
6913 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6914 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6915 inst.operands[0].reg);
6919 if (inst.operands[1].imm & (1 << 14)
6920 && inst.operands[1].imm & (1 << 15))
6921 as_warn (_("LR and PC should not both be in register list"));
6922 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6923 && inst.operands[0].writeback)
6924 as_warn (_("base register should not be in register list "
6925 "when written back"));
6927 if (inst.instruction < 0xffff)
6928 inst.instruction = THUMB_OP32 (inst.instruction);
6929 inst.instruction |= inst.operands[0].reg << 16;
6930 inst.instruction |= inst.operands[1].imm;
6931 if (inst.operands[0].writeback)
6932 inst.instruction |= WRITE_BACK;
6937 constraint (inst.operands[0].reg > 7
6938 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6939 if (inst.instruction == T_MNEM_stmia)
6941 if (!inst.operands[0].writeback)
6942 as_warn (_("this instruction will write back the base register"));
6943 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6944 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6945 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6946 inst.operands[0].reg);
6950 if (!inst.operands[0].writeback
6951 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6952 as_warn (_("this instruction will write back the base register"));
6953 else if (inst.operands[0].writeback
6954 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6955 as_warn (_("this instruction will not write back the base register"));
6958 inst.instruction = THUMB_OP16 (inst.instruction);
6959 inst.instruction |= inst.operands[0].reg << 8;
6960 inst.instruction |= inst.operands[1].imm;
6967 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6968 || inst.operands[1].postind || inst.operands[1].writeback
6969 || inst.operands[1].immisreg || inst.operands[1].shifted
6970 || inst.operands[1].negative,
6973 inst.instruction |= inst.operands[0].reg << 12;
6974 inst.instruction |= inst.operands[1].reg << 16;
6975 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6981 if (!inst.operands[1].present)
6983 constraint (inst.operands[0].reg == REG_LR,
6984 _("r14 not allowed as first register "
6985 "when second register is omitted"));
6986 inst.operands[1].reg = inst.operands[0].reg + 1;
6988 constraint (inst.operands[0].reg == inst.operands[1].reg,
6991 inst.instruction |= inst.operands[0].reg << 12;
6992 inst.instruction |= inst.operands[1].reg << 8;
6993 inst.instruction |= inst.operands[2].reg << 16;
6999 unsigned long opcode;
7002 opcode = inst.instruction;
7005 if (!inst.operands[1].isreg)
7007 if (opcode <= 0xffff)
7008 inst.instruction = THUMB_OP32 (opcode);
7009 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
7012 if (inst.operands[1].isreg
7013 && !inst.operands[1].writeback
7014 && !inst.operands[1].shifted && !inst.operands[1].postind
7015 && !inst.operands[1].negative && inst.operands[0].reg <= 7
7017 && inst.size_req != 4)
7019 /* Insn may have a 16-bit form. */
7020 Rn = inst.operands[1].reg;
7021 if (inst.operands[1].immisreg)
7023 inst.instruction = THUMB_OP16 (opcode);
7025 if (Rn <= 7 && inst.operands[1].imm <= 7)
7028 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
7029 && opcode != T_MNEM_ldrsb)
7030 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
7031 || (Rn == REG_SP && opcode == T_MNEM_str))
7038 if (inst.reloc.pc_rel)
7039 opcode = T_MNEM_ldr_pc2;
7041 opcode = T_MNEM_ldr_pc;
7045 if (opcode == T_MNEM_ldr)
7046 opcode = T_MNEM_ldr_sp;
7048 opcode = T_MNEM_str_sp;
7050 inst.instruction = inst.operands[0].reg << 8;
7054 inst.instruction = inst.operands[0].reg;
7055 inst.instruction |= inst.operands[1].reg << 3;
7057 inst.instruction |= THUMB_OP16 (opcode);
7058 if (inst.size_req == 2)
7059 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
7061 inst.relax = opcode;
7065 /* Definitely a 32-bit variant. */
7066 inst.instruction = THUMB_OP32 (opcode);
7067 inst.instruction |= inst.operands[0].reg << 12;
7068 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
7072 constraint (inst.operands[0].reg > 7, BAD_HIREG);
7074 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
7076 /* Only [Rn,Rm] is acceptable. */
7077 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
7078 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
7079 || inst.operands[1].postind || inst.operands[1].shifted
7080 || inst.operands[1].negative,
7081 _("Thumb does not support this addressing mode"));
7082 inst.instruction = THUMB_OP16 (inst.instruction);
7086 inst.instruction = THUMB_OP16 (inst.instruction);
7087 if (!inst.operands[1].isreg)
7088 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
7091 constraint (!inst.operands[1].preind
7092 || inst.operands[1].shifted
7093 || inst.operands[1].writeback,
7094 _("Thumb does not support this addressing mode"));
7095 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
7097 constraint (inst.instruction & 0x0600,
7098 _("byte or halfword not valid for base register"));
7099 constraint (inst.operands[1].reg == REG_PC
7100 && !(inst.instruction & THUMB_LOAD_BIT),
7101 _("r15 based store not allowed"));
7102 constraint (inst.operands[1].immisreg,
7103 _("invalid base register for register offset"));
7105 if (inst.operands[1].reg == REG_PC)
7106 inst.instruction = T_OPCODE_LDR_PC;
7107 else if (inst.instruction & THUMB_LOAD_BIT)
7108 inst.instruction = T_OPCODE_LDR_SP;
7110 inst.instruction = T_OPCODE_STR_SP;
7112 inst.instruction |= inst.operands[0].reg << 8;
7113 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
7117 constraint (inst.operands[1].reg > 7, BAD_HIREG);
7118 if (!inst.operands[1].immisreg)
7120 /* Immediate offset. */
7121 inst.instruction |= inst.operands[0].reg;
7122 inst.instruction |= inst.operands[1].reg << 3;
7123 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
7127 /* Register offset. */
7128 constraint (inst.operands[1].imm > 7, BAD_HIREG);
7129 constraint (inst.operands[1].negative,
7130 _("Thumb does not support this addressing mode"));
7133 switch (inst.instruction)
7135 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
7136 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
7137 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
7138 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
7139 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
7140 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
7141 case 0x5600 /* ldrsb */:
7142 case 0x5e00 /* ldrsh */: break;
7146 inst.instruction |= inst.operands[0].reg;
7147 inst.instruction |= inst.operands[1].reg << 3;
7148 inst.instruction |= inst.operands[1].imm << 6;
7154 if (!inst.operands[1].present)
7156 inst.operands[1].reg = inst.operands[0].reg + 1;
7157 constraint (inst.operands[0].reg == REG_LR,
7158 _("r14 not allowed here"));
7160 inst.instruction |= inst.operands[0].reg << 12;
7161 inst.instruction |= inst.operands[1].reg << 8;
7162 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
7169 inst.instruction |= inst.operands[0].reg << 12;
7170 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
7176 inst.instruction |= inst.operands[0].reg << 8;
7177 inst.instruction |= inst.operands[1].reg << 16;
7178 inst.instruction |= inst.operands[2].reg;
7179 inst.instruction |= inst.operands[3].reg << 12;
7185 inst.instruction |= inst.operands[0].reg << 12;
7186 inst.instruction |= inst.operands[1].reg << 8;
7187 inst.instruction |= inst.operands[2].reg << 16;
7188 inst.instruction |= inst.operands[3].reg;
7196 int r0off = (inst.instruction == T_MNEM_mov
7197 || inst.instruction == T_MNEM_movs) ? 8 : 16;
7198 unsigned long opcode;
7200 bfd_boolean low_regs;
7202 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
7203 opcode = inst.instruction;
7204 if (current_it_mask)
7205 narrow = opcode != T_MNEM_movs;
7207 narrow = opcode != T_MNEM_movs || low_regs;
7208 if (inst.size_req == 4
7209 || inst.operands[1].shifted)
7212 if (!inst.operands[1].isreg)
7214 /* Immediate operand. */
7215 if (current_it_mask == 0 && opcode == T_MNEM_mov)
7217 if (low_regs && narrow)
7219 inst.instruction = THUMB_OP16 (opcode);
7220 inst.instruction |= inst.operands[0].reg << 8;
7221 if (inst.size_req == 2)
7222 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
7224 inst.relax = opcode;
7228 inst.instruction = THUMB_OP32 (inst.instruction);
7229 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7230 inst.instruction |= inst.operands[0].reg << r0off;
7231 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7236 inst.instruction = THUMB_OP32 (inst.instruction);
7237 inst.instruction |= inst.operands[0].reg << r0off;
7238 encode_thumb32_shifted_operand (1);
7241 switch (inst.instruction)
7244 inst.instruction = T_OPCODE_MOV_HR;
7245 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7246 inst.instruction |= (inst.operands[0].reg & 0x7);
7247 inst.instruction |= inst.operands[1].reg << 3;
7251 /* We know we have low registers at this point.
7252 Generate ADD Rd, Rs, #0. */
7253 inst.instruction = T_OPCODE_ADD_I3;
7254 inst.instruction |= inst.operands[0].reg;
7255 inst.instruction |= inst.operands[1].reg << 3;
7261 inst.instruction = T_OPCODE_CMP_LR;
7262 inst.instruction |= inst.operands[0].reg;
7263 inst.instruction |= inst.operands[1].reg << 3;
7267 inst.instruction = T_OPCODE_CMP_HR;
7268 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7269 inst.instruction |= (inst.operands[0].reg & 0x7);
7270 inst.instruction |= inst.operands[1].reg << 3;
7277 inst.instruction = THUMB_OP16 (inst.instruction);
7278 if (inst.operands[1].isreg)
7280 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
7282 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
7283 since a MOV instruction produces unpredictable results. */
7284 if (inst.instruction == T_OPCODE_MOV_I8)
7285 inst.instruction = T_OPCODE_ADD_I3;
7287 inst.instruction = T_OPCODE_CMP_LR;
7289 inst.instruction |= inst.operands[0].reg;
7290 inst.instruction |= inst.operands[1].reg << 3;
7294 if (inst.instruction == T_OPCODE_MOV_I8)
7295 inst.instruction = T_OPCODE_MOV_HR;
7297 inst.instruction = T_OPCODE_CMP_HR;
7303 constraint (inst.operands[0].reg > 7,
7304 _("only lo regs allowed with immediate"));
7305 inst.instruction |= inst.operands[0].reg << 8;
7306 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
7313 inst.instruction |= inst.operands[0].reg << 8;
7314 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
7315 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
7316 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
7317 inst.instruction |= (inst.operands[1].imm & 0x00ff);
7325 int r0off = (inst.instruction == T_MNEM_mvn
7326 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
7329 if (inst.size_req == 4
7330 || inst.instruction > 0xffff
7331 || inst.operands[1].shifted
7332 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7334 else if (inst.instruction == T_MNEM_cmn)
7336 else if (THUMB_SETS_FLAGS (inst.instruction))
7337 narrow = (current_it_mask == 0);
7339 narrow = (current_it_mask != 0);
7341 if (!inst.operands[1].isreg)
7343 /* For an immediate, we always generate a 32-bit opcode;
7344 section relaxation will shrink it later if possible. */
7345 if (inst.instruction < 0xffff)
7346 inst.instruction = THUMB_OP32 (inst.instruction);
7347 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7348 inst.instruction |= inst.operands[0].reg << r0off;
7349 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7353 /* See if we can do this with a 16-bit instruction. */
7356 inst.instruction = THUMB_OP16 (inst.instruction);
7357 inst.instruction |= inst.operands[0].reg;
7358 inst.instruction |= inst.operands[1].reg << 3;
7362 constraint (inst.operands[1].shifted
7363 && inst.operands[1].immisreg,
7364 _("shift must be constant"));
7365 if (inst.instruction < 0xffff)
7366 inst.instruction = THUMB_OP32 (inst.instruction);
7367 inst.instruction |= inst.operands[0].reg << r0off;
7368 encode_thumb32_shifted_operand (1);
7374 constraint (inst.instruction > 0xffff
7375 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
7376 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
7377 _("unshifted register required"));
7378 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7381 inst.instruction = THUMB_OP16 (inst.instruction);
7382 inst.instruction |= inst.operands[0].reg;
7383 inst.instruction |= inst.operands[1].reg << 3;
7391 flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
7394 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
7395 _("selected processor does not support "
7396 "requested special purpose register"));
7400 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
7401 _("selected processor does not support "
7402 "requested special purpose register %x"));
7403 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7404 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
7405 _("'CPSR' or 'SPSR' expected"));
7408 inst.instruction |= inst.operands[0].reg << 8;
7409 inst.instruction |= (flags & SPSR_BIT) >> 2;
7410 inst.instruction |= inst.operands[1].imm & 0xff;
7418 constraint (!inst.operands[1].isreg,
7419 _("Thumb encoding does not support an immediate here"));
7420 flags = inst.operands[0].imm;
7423 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
7424 _("selected processor does not support "
7425 "requested special purpose register"));
7429 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
7430 _("selected processor does not support "
7431 "requested special purpose register"));
7434 inst.instruction |= (flags & SPSR_BIT) >> 2;
7435 inst.instruction |= (flags & ~SPSR_BIT) >> 8;
7436 inst.instruction |= (flags & 0xff);
7437 inst.instruction |= inst.operands[1].reg << 16;
7443 if (!inst.operands[2].present)
7444 inst.operands[2].reg = inst.operands[0].reg;
7446 /* There is no 32-bit MULS and no 16-bit MUL. */
7447 if (unified_syntax && inst.instruction == T_MNEM_mul)
7449 inst.instruction = THUMB_OP32 (inst.instruction);
7450 inst.instruction |= inst.operands[0].reg << 8;
7451 inst.instruction |= inst.operands[1].reg << 16;
7452 inst.instruction |= inst.operands[2].reg << 0;
7456 constraint (!unified_syntax
7457 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
7458 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7461 inst.instruction = THUMB_OP16 (inst.instruction);
7462 inst.instruction |= inst.operands[0].reg;
7464 if (inst.operands[0].reg == inst.operands[1].reg)
7465 inst.instruction |= inst.operands[2].reg << 3;
7466 else if (inst.operands[0].reg == inst.operands[2].reg)
7467 inst.instruction |= inst.operands[1].reg << 3;
7469 constraint (1, _("dest must overlap one source register"));
7476 inst.instruction |= inst.operands[0].reg << 12;
7477 inst.instruction |= inst.operands[1].reg << 8;
7478 inst.instruction |= inst.operands[2].reg << 16;
7479 inst.instruction |= inst.operands[3].reg;
7481 if (inst.operands[0].reg == inst.operands[1].reg)
7482 as_tsktsk (_("rdhi and rdlo must be different"));
7490 if (inst.size_req == 4 || inst.operands[0].imm > 15)
7492 inst.instruction = THUMB_OP32 (inst.instruction);
7493 inst.instruction |= inst.operands[0].imm;
7497 inst.instruction = THUMB_OP16 (inst.instruction);
7498 inst.instruction |= inst.operands[0].imm << 4;
7503 constraint (inst.operands[0].present,
7504 _("Thumb does not support NOP with hints"));
7505 inst.instruction = 0x46c0;
7516 if (THUMB_SETS_FLAGS (inst.instruction))
7517 narrow = (current_it_mask == 0);
7519 narrow = (current_it_mask != 0);
7520 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7522 if (inst.size_req == 4)
7527 inst.instruction = THUMB_OP32 (inst.instruction);
7528 inst.instruction |= inst.operands[0].reg << 8;
7529 inst.instruction |= inst.operands[1].reg << 16;
7533 inst.instruction = THUMB_OP16 (inst.instruction);
7534 inst.instruction |= inst.operands[0].reg;
7535 inst.instruction |= inst.operands[1].reg << 3;
7540 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7542 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7544 inst.instruction = THUMB_OP16 (inst.instruction);
7545 inst.instruction |= inst.operands[0].reg;
7546 inst.instruction |= inst.operands[1].reg << 3;
7553 inst.instruction |= inst.operands[0].reg << 8;
7554 inst.instruction |= inst.operands[1].reg << 16;
7555 inst.instruction |= inst.operands[2].reg;
7556 if (inst.operands[3].present)
7558 unsigned int val = inst.reloc.exp.X_add_number;
7559 constraint (inst.reloc.exp.X_op != O_constant,
7560 _("expression too complex"));
7561 inst.instruction |= (val & 0x1c) << 10;
7562 inst.instruction |= (val & 0x03) << 6;
7569 if (!inst.operands[3].present)
7570 inst.instruction &= ~0x00000020;
7577 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
7581 do_t_push_pop (void)
7585 constraint (inst.operands[0].writeback,
7586 _("push/pop do not support {reglist}^"));
7587 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
7588 _("expression too complex"));
7590 mask = inst.operands[0].imm;
7591 if ((mask & ~0xff) == 0)
7592 inst.instruction = THUMB_OP16 (inst.instruction);
7593 else if ((inst.instruction == T_MNEM_push
7594 && (mask & ~0xff) == 1 << REG_LR)
7595 || (inst.instruction == T_MNEM_pop
7596 && (mask & ~0xff) == 1 << REG_PC))
7598 inst.instruction = THUMB_OP16 (inst.instruction);
7599 inst.instruction |= THUMB_PP_PC_LR;
7602 else if (unified_syntax)
7604 if (mask & (1 << 13))
7605 inst.error = _("SP not allowed in register list");
7606 if (inst.instruction == T_MNEM_push)
7608 if (mask & (1 << 15))
7609 inst.error = _("PC not allowed in register list");
7613 if (mask & (1 << 14)
7614 && mask & (1 << 15))
7615 inst.error = _("LR and PC should not both be in register list");
7617 if ((mask & (mask - 1)) == 0)
7619 /* Single register push/pop implemented as str/ldr. */
7620 if (inst.instruction == T_MNEM_push)
7621 inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
7623 inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
7624 mask = ffs(mask) - 1;
7628 inst.instruction = THUMB_OP32 (inst.instruction);
7632 inst.error = _("invalid register list to push/pop instruction");
7636 inst.instruction |= mask;
7642 inst.instruction |= inst.operands[0].reg << 8;
7643 inst.instruction |= inst.operands[1].reg << 16;
7649 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7650 && inst.size_req != 4)
7652 inst.instruction = THUMB_OP16 (inst.instruction);
7653 inst.instruction |= inst.operands[0].reg;
7654 inst.instruction |= inst.operands[1].reg << 3;
7656 else if (unified_syntax)
7658 inst.instruction = THUMB_OP32 (inst.instruction);
7659 inst.instruction |= inst.operands[0].reg << 8;
7660 inst.instruction |= inst.operands[1].reg << 16;
7661 inst.instruction |= inst.operands[1].reg;
7664 inst.error = BAD_HIREG;
7672 Rd = inst.operands[0].reg;
7673 Rs = (inst.operands[1].present
7674 ? inst.operands[1].reg /* Rd, Rs, foo */
7675 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
7677 inst.instruction |= Rd << 8;
7678 inst.instruction |= Rs << 16;
7679 if (!inst.operands[2].isreg)
7681 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7682 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7685 encode_thumb32_shifted_operand (2);
7691 constraint (current_it_mask, BAD_NOT_IT);
7692 if (inst.operands[0].imm)
7693 inst.instruction |= 0x8;
7699 if (!inst.operands[1].present)
7700 inst.operands[1].reg = inst.operands[0].reg;
7707 switch (inst.instruction)
7710 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
7712 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
7714 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
7716 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
7720 if (THUMB_SETS_FLAGS (inst.instruction))
7721 narrow = (current_it_mask == 0);
7723 narrow = (current_it_mask != 0);
7724 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7726 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
7728 if (inst.operands[2].isreg
7729 && (inst.operands[1].reg != inst.operands[0].reg
7730 || inst.operands[2].reg > 7))
7732 if (inst.size_req == 4)
7737 if (inst.operands[2].isreg)
7739 inst.instruction = THUMB_OP32 (inst.instruction);
7740 inst.instruction |= inst.operands[0].reg << 8;
7741 inst.instruction |= inst.operands[1].reg << 16;
7742 inst.instruction |= inst.operands[2].reg;
7746 inst.operands[1].shifted = 1;
7747 inst.operands[1].shift_kind = shift_kind;
7748 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7749 ? T_MNEM_movs : T_MNEM_mov);
7750 inst.instruction |= inst.operands[0].reg << 8;
7751 encode_thumb32_shifted_operand (1);
7752 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7753 inst.reloc.type = BFD_RELOC_UNUSED;
7758 if (inst.operands[2].isreg)
7762 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
7763 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
7764 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
7765 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
7769 inst.instruction |= inst.operands[0].reg;
7770 inst.instruction |= inst.operands[2].reg << 3;
7776 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
7777 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
7778 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
7781 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7782 inst.instruction |= inst.operands[0].reg;
7783 inst.instruction |= inst.operands[1].reg << 3;
7789 constraint (inst.operands[0].reg > 7
7790 || inst.operands[1].reg > 7, BAD_HIREG);
7791 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7793 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7795 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7796 constraint (inst.operands[0].reg != inst.operands[1].reg,
7797 _("source1 and dest must be same register"));
7799 switch (inst.instruction)
7801 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7802 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7803 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7804 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7808 inst.instruction |= inst.operands[0].reg;
7809 inst.instruction |= inst.operands[2].reg << 3;
7813 switch (inst.instruction)
7815 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7816 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7817 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7818 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7821 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7822 inst.instruction |= inst.operands[0].reg;
7823 inst.instruction |= inst.operands[1].reg << 3;
7831 inst.instruction |= inst.operands[0].reg << 8;
7832 inst.instruction |= inst.operands[1].reg << 16;
7833 inst.instruction |= inst.operands[2].reg;
7839 unsigned int value = inst.reloc.exp.X_add_number;
7840 constraint (inst.reloc.exp.X_op != O_constant,
7841 _("expression too complex"));
7842 inst.reloc.type = BFD_RELOC_UNUSED;
7843 inst.instruction |= (value & 0xf000) >> 12;
7844 inst.instruction |= (value & 0x0ff0);
7845 inst.instruction |= (value & 0x000f) << 16;
7851 inst.instruction |= inst.operands[0].reg << 8;
7852 inst.instruction |= inst.operands[1].imm - 1;
7853 inst.instruction |= inst.operands[2].reg << 16;
7855 if (inst.operands[3].present)
7857 constraint (inst.reloc.exp.X_op != O_constant,
7858 _("expression too complex"));
7860 if (inst.reloc.exp.X_add_number != 0)
7862 if (inst.operands[3].shift_kind == SHIFT_ASR)
7863 inst.instruction |= 0x00200000; /* sh bit */
7864 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7865 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7867 inst.reloc.type = BFD_RELOC_UNUSED;
7874 inst.instruction |= inst.operands[0].reg << 8;
7875 inst.instruction |= inst.operands[1].imm - 1;
7876 inst.instruction |= inst.operands[2].reg << 16;
7882 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7883 || inst.operands[2].postind || inst.operands[2].writeback
7884 || inst.operands[2].immisreg || inst.operands[2].shifted
7885 || inst.operands[2].negative,
7888 inst.instruction |= inst.operands[0].reg << 8;
7889 inst.instruction |= inst.operands[1].reg << 12;
7890 inst.instruction |= inst.operands[2].reg << 16;
7891 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
7897 if (!inst.operands[2].present)
7898 inst.operands[2].reg = inst.operands[1].reg + 1;
7900 constraint (inst.operands[0].reg == inst.operands[1].reg
7901 || inst.operands[0].reg == inst.operands[2].reg
7902 || inst.operands[0].reg == inst.operands[3].reg
7903 || inst.operands[1].reg == inst.operands[2].reg,
7906 inst.instruction |= inst.operands[0].reg;
7907 inst.instruction |= inst.operands[1].reg << 12;
7908 inst.instruction |= inst.operands[2].reg << 8;
7909 inst.instruction |= inst.operands[3].reg << 16;
7915 inst.instruction |= inst.operands[0].reg << 8;
7916 inst.instruction |= inst.operands[1].reg << 16;
7917 inst.instruction |= inst.operands[2].reg;
7918 inst.instruction |= inst.operands[3].imm << 4;
7924 if (inst.instruction <= 0xffff && inst.size_req != 4
7925 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7926 && (!inst.operands[2].present || inst.operands[2].imm == 0))
7928 inst.instruction = THUMB_OP16 (inst.instruction);
7929 inst.instruction |= inst.operands[0].reg;
7930 inst.instruction |= inst.operands[1].reg << 3;
7932 else if (unified_syntax)
7934 if (inst.instruction <= 0xffff)
7935 inst.instruction = THUMB_OP32 (inst.instruction);
7936 inst.instruction |= inst.operands[0].reg << 8;
7937 inst.instruction |= inst.operands[1].reg;
7938 inst.instruction |= inst.operands[2].imm << 4;
7942 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7943 _("Thumb encoding does not support rotation"));
7944 constraint (1, BAD_HIREG);
7951 inst.reloc.type = BFD_RELOC_ARM_SWI;
7959 half = (inst.instruction & 0x10) != 0;
7960 constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
7961 constraint (inst.operands[0].immisreg,
7962 _("instruction requires register index"));
7963 constraint (inst.operands[0].imm == 15,
7964 _("PC is not a valid index register"));
7965 constraint (!half && inst.operands[0].shifted,
7966 _("instruction does not allow shifted index"));
7967 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
7973 inst.instruction |= inst.operands[0].reg << 8;
7974 inst.instruction |= inst.operands[1].imm;
7975 inst.instruction |= inst.operands[2].reg << 16;
7977 if (inst.operands[3].present)
7979 constraint (inst.reloc.exp.X_op != O_constant,
7980 _("expression too complex"));
7981 if (inst.reloc.exp.X_add_number != 0)
7983 if (inst.operands[3].shift_kind == SHIFT_ASR)
7984 inst.instruction |= 0x00200000; /* sh bit */
7986 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7987 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7989 inst.reloc.type = BFD_RELOC_UNUSED;
7996 inst.instruction |= inst.operands[0].reg << 8;
7997 inst.instruction |= inst.operands[1].imm;
7998 inst.instruction |= inst.operands[2].reg << 16;
8001 /* Overall per-instruction processing. */
8003 /* We need to be able to fix up arbitrary expressions in some statements.
8004 This is so that we can handle symbols that are an arbitrary distance from
8005 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
8006 which returns part of an address in a form which will be valid for
8007 a data instruction. We do this by pushing the expression into a symbol
8008 in the expr_section, and creating a fix for that. */
8011 fix_new_arm (fragS * frag,
8026 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
8030 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
8035 /* Mark whether the fix is to a THUMB instruction, or an ARM
8037 new_fix->tc_fix_data = thumb_mode;
8040 /* Create a frg for an instruction requiring relaxation. */
8042 output_relax_insn (void)
8049 /* The size of the instruction is unknown, so tie the debug info to the
8050 start of the instruction. */
8051 dwarf2_emit_insn (0);
8054 switch (inst.reloc.exp.X_op)
8057 sym = inst.reloc.exp.X_add_symbol;
8058 offset = inst.reloc.exp.X_add_number;
8062 offset = inst.reloc.exp.X_add_number;
8065 sym = make_expr_symbol (&inst.reloc.exp);
8069 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
8070 inst.relax, sym, offset, NULL/*offset, opcode*/);
8071 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
8074 /* Write a 32-bit thumb instruction to buf. */
8076 put_thumb32_insn (char * buf, unsigned long insn)
8078 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
8079 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
8083 output_inst (const char * str)
8089 as_bad ("%s -- `%s'", inst.error, str);
8093 output_relax_insn();
8099 to = frag_more (inst.size);
8101 if (thumb_mode && (inst.size > THUMB_SIZE))
8103 assert (inst.size == (2 * THUMB_SIZE));
8104 put_thumb32_insn (to, inst.instruction);
8106 else if (inst.size > INSN_SIZE)
8108 assert (inst.size == (2 * INSN_SIZE));
8109 md_number_to_chars (to, inst.instruction, INSN_SIZE);
8110 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
8113 md_number_to_chars (to, inst.instruction, inst.size);
8115 if (inst.reloc.type != BFD_RELOC_UNUSED)
8116 fix_new_arm (frag_now, to - frag_now->fr_literal,
8117 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
8121 dwarf2_emit_insn (inst.size);
8125 /* Tag values used in struct asm_opcode's tag field. */
8128 OT_unconditional, /* Instruction cannot be conditionalized.
8129 The ARM condition field is still 0xE. */
8130 OT_unconditionalF, /* Instruction cannot be conditionalized
8131 and carries 0xF in its ARM condition field. */
8132 OT_csuffix, /* Instruction takes a conditional suffix. */
8133 OT_cinfix3, /* Instruction takes a conditional infix,
8134 beginning at character index 3. (In
8135 unified mode, it becomes a suffix.) */
8136 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
8137 character index 3, even in unified mode. Used for
8138 legacy instructions where suffix and infix forms
8139 may be ambiguous. */
8140 OT_csuf_or_in3, /* Instruction takes either a conditional
8141 suffix or an infix at character index 3. */
8142 OT_odd_infix_unc, /* This is the unconditional variant of an
8143 instruction that takes a conditional infix
8144 at an unusual position. In unified mode,
8145 this variant will accept a suffix. */
8146 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
8147 are the conditional variants of instructions that
8148 take conditional infixes in unusual positions.
8149 The infix appears at character index
8150 (tag - OT_odd_infix_0). These are not accepted
8154 /* Subroutine of md_assemble, responsible for looking up the primary
8155 opcode from the mnemonic the user wrote. STR points to the
8156 beginning of the mnemonic.
8158 This is not simply a hash table lookup, because of conditional
8159 variants. Most instructions have conditional variants, which are
8160 expressed with a _conditional affix_ to the mnemonic. If we were
8161 to encode each conditional variant as a literal string in the opcode
8162 table, it would have approximately 20,000 entries.
8164 Most mnemonics take this affix as a suffix, and in unified syntax,
8165 'most' is upgraded to 'all'. However, in the divided syntax, some
8166 instructions take the affix as an infix, notably the s-variants of
8167 the arithmetic instructions. Of those instructions, all but six
8168 have the infix appear after the third character of the mnemonic.
8170 Accordingly, the algorithm for looking up primary opcodes given
8173 1. Look up the identifier in the opcode table.
8174 If we find a match, go to step U.
8176 2. Look up the last two characters of the identifier in the
8177 conditions table. If we find a match, look up the first N-2
8178 characters of the identifier in the opcode table. If we
8179 find a match, go to step CE.
8181 3. Look up the fourth and fifth characters of the identifier in
8182 the conditions table. If we find a match, extract those
8183 characters from the identifier, and look up the remaining
8184 characters in the opcode table. If we find a match, go
8189 U. Examine the tag field of the opcode structure, in case this is
8190 one of the six instructions with its conditional infix in an
8191 unusual place. If it is, the tag tells us where to find the
8192 infix; look it up in the conditions table and set inst.cond
8193 accordingly. Otherwise, this is an unconditional instruction.
8194 Again set inst.cond accordingly. Return the opcode structure.
8196 CE. Examine the tag field to make sure this is an instruction that
8197 should receive a conditional suffix. If it is not, fail.
8198 Otherwise, set inst.cond from the suffix we already looked up,
8199 and return the opcode structure.
8201 CM. Examine the tag field to make sure this is an instruction that
8202 should receive a conditional infix after the third character.
8203 If it is not, fail. Otherwise, undo the edits to the current
8204 line of input and proceed as for case CE. */
8206 static const struct asm_opcode *
8207 opcode_lookup (char **str)
8211 const struct asm_opcode *opcode;
8212 const struct asm_cond *cond;
8215 /* Scan up to the end of the mnemonic, which must end in white space,
8216 '.' (in unified mode only), or end of string. */
8217 for (base = end = *str; *end != '\0'; end++)
8218 if (*end == ' ' || (unified_syntax && *end == '.'))
8224 /* Handle a possible width suffix. */
8227 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
8229 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
8239 /* Look for unaffixed or special-case affixed mnemonic. */
8240 opcode = hash_find_n (arm_ops_hsh, base, end - base);
8244 if (opcode->tag < OT_odd_infix_0)
8246 inst.cond = COND_ALWAYS;
8251 as_warn (_("conditional infixes are deprecated in unified syntax"));
8252 affix = base + (opcode->tag - OT_odd_infix_0);
8253 cond = hash_find_n (arm_cond_hsh, affix, 2);
8256 inst.cond = cond->value;
8260 /* Cannot have a conditional suffix on a mnemonic of less than two
8265 /* Look for suffixed mnemonic. */
8267 cond = hash_find_n (arm_cond_hsh, affix, 2);
8268 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
8272 switch (opcode->tag)
8274 case OT_cinfix3_legacy:
8275 /* Ignore conditional suffixes matched on infix only mnemonics. */
8279 case OT_odd_infix_unc:
8280 if (!unified_syntax)
8282 /* else fall through */
8285 case OT_csuf_or_in3:
8286 inst.cond = cond->value;
8289 case OT_unconditional:
8290 case OT_unconditionalF:
8293 inst.cond = cond->value;
8297 /* delayed diagnostic */
8298 inst.error = BAD_COND;
8299 inst.cond = COND_ALWAYS;
8308 /* Cannot have a usual-position infix on a mnemonic of less than
8309 six characters (five would be a suffix). */
8313 /* Look for infixed mnemonic in the usual position. */
8315 cond = hash_find_n (arm_cond_hsh, affix, 2);
8319 memcpy (save, affix, 2);
8320 memmove (affix, affix + 2, (end - affix) - 2);
8321 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
8322 memmove (affix + 2, affix, (end - affix) - 2);
8323 memcpy (affix, save, 2);
8325 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3
8326 || opcode->tag == OT_cinfix3_legacy))
8329 if (unified_syntax && opcode->tag == OT_cinfix3)
8330 as_warn (_("conditional infixes are deprecated in unified syntax"));
8332 inst.cond = cond->value;
8340 md_assemble (char *str)
8343 const struct asm_opcode * opcode;
8345 /* Align the previous label if needed. */
8346 if (last_label_seen != NULL)
8348 symbol_set_frag (last_label_seen, frag_now);
8349 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
8350 S_SET_SEGMENT (last_label_seen, now_seg);
8353 memset (&inst, '\0', sizeof (inst));
8354 inst.reloc.type = BFD_RELOC_UNUSED;
8356 opcode = opcode_lookup (&p);
8359 /* It wasn't an instruction, but it might be a register alias of
8360 the form alias .req reg. */
8361 if (!create_register_alias (str, p))
8362 as_bad (_("bad instruction `%s'"), str);
8369 arm_feature_set variant;
8371 variant = cpu_variant;
8372 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
8373 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
8374 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
8375 /* Check that this instruction is supported for this CPU. */
8376 if (!opcode->tvariant
8378 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
8380 as_bad (_("selected processor does not support `%s'"), str);
8383 if (inst.cond != COND_ALWAYS && !unified_syntax
8384 && opcode->tencode != do_t_branch)
8386 as_bad (_("Thumb does not support conditional execution"));
8390 /* Check conditional suffixes. */
8391 if (current_it_mask)
8394 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
8395 current_it_mask <<= 1;
8396 current_it_mask &= 0x1f;
8397 /* The BKPT instruction is unconditional even in an IT block. */
8399 && cond != inst.cond && opcode->tencode != do_t_bkpt)
8401 as_bad (_("incorrect condition in IT block"));
8405 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
8407 as_bad (_("thumb conditional instrunction not in IT block"));
8411 mapping_state (MAP_THUMB);
8412 inst.instruction = opcode->tvalue;
8414 if (!parse_operands (p, opcode->operands))
8417 /* Clear current_it_mask at the end of an IT block. */
8418 if (current_it_mask == 0x10)
8419 current_it_mask = 0;
8421 if (!(inst.error || inst.relax))
8423 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
8424 inst.size = (inst.instruction > 0xffff ? 4 : 2);
8425 if (inst.size_req && inst.size_req != inst.size)
8427 as_bad (_("cannot honor width suffix -- `%s'"), str);
8431 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8433 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
8434 set those bits when Thumb-2 32-bit instuctions are seen. ie.
8435 anything other than bl/blx.
8436 This is overly pessimistic for relaxable instructions. */
8437 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
8439 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8444 /* Check that this instruction is supported for this CPU. */
8445 if (!opcode->avariant ||
8446 !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
8448 as_bad (_("selected processor does not support `%s'"), str);
8453 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
8457 mapping_state (MAP_ARM);
8458 inst.instruction = opcode->avalue;
8459 if (opcode->tag == OT_unconditionalF)
8460 inst.instruction |= 0xF << 28;
8462 inst.instruction |= inst.cond << 28;
8463 inst.size = INSN_SIZE;
8464 if (!parse_operands (p, opcode->operands))
8466 /* Arm mode bx is marked as both v4T and v5 because it's still required
8467 on a hypothetical non-thumb v5 core. */
8468 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
8469 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
8470 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
8472 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8478 /* Various frobbings of labels and their addresses. */
8481 arm_start_line_hook (void)
8483 last_label_seen = NULL;
8487 arm_frob_label (symbolS * sym)
8489 last_label_seen = sym;
8491 ARM_SET_THUMB (sym, thumb_mode);
8493 #if defined OBJ_COFF || defined OBJ_ELF
8494 ARM_SET_INTERWORK (sym, support_interwork);
8497 /* Note - do not allow local symbols (.Lxxx) to be labeled
8498 as Thumb functions. This is because these labels, whilst
8499 they exist inside Thumb code, are not the entry points for
8500 possible ARM->Thumb calls. Also, these labels can be used
8501 as part of a computed goto or switch statement. eg gcc
8502 can generate code that looks like this:
8514 The first instruction loads the address of the jump table.
8515 The second instruction converts a table index into a byte offset.
8516 The third instruction gets the jump address out of the table.
8517 The fourth instruction performs the jump.
8519 If the address stored at .Laaa is that of a symbol which has the
8520 Thumb_Func bit set, then the linker will arrange for this address
8521 to have the bottom bit set, which in turn would mean that the
8522 address computation performed by the third instruction would end
8523 up with the bottom bit set. Since the ARM is capable of unaligned
8524 word loads, the instruction would then load the incorrect address
8525 out of the jump table, and chaos would ensue. */
8526 if (label_is_thumb_function_name
8527 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
8528 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
8530 /* When the address of a Thumb function is taken the bottom
8531 bit of that address should be set. This will allow
8532 interworking between Arm and Thumb functions to work
8535 THUMB_SET_FUNC (sym, 1);
8537 label_is_thumb_function_name = FALSE;
8541 dwarf2_emit_label (sym);
8546 arm_data_in_code (void)
8548 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
8550 *input_line_pointer = '/';
8551 input_line_pointer += 5;
8552 *input_line_pointer = 0;
8560 arm_canonicalize_symbol_name (char * name)
8564 if (thumb_mode && (len = strlen (name)) > 5
8565 && streq (name + len - 5, "/data"))
8566 *(name + len - 5) = 0;
8571 /* Table of all register names defined by default. The user can
8572 define additional names with .req. Note that all register names
8573 should appear in both upper and lowercase variants. Some registers
8574 also have mixed-case names. */
8576 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
8577 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8578 #define REGSET(p,t) \
8579 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8580 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8581 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8582 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8584 static const struct reg_entry reg_names[] =
8586 /* ARM integer registers. */
8587 REGSET(r, RN), REGSET(R, RN),
8589 /* ATPCS synonyms. */
8590 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
8591 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
8592 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
8594 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
8595 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
8596 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
8598 /* Well-known aliases. */
8599 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
8600 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
8602 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
8603 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
8605 /* Coprocessor numbers. */
8606 REGSET(p, CP), REGSET(P, CP),
8608 /* Coprocessor register numbers. The "cr" variants are for backward
8610 REGSET(c, CN), REGSET(C, CN),
8611 REGSET(cr, CN), REGSET(CR, CN),
8613 /* FPA registers. */
8614 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
8615 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
8617 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
8618 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
8620 /* VFP SP registers. */
8622 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
8623 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
8624 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
8625 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
8628 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
8629 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
8630 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
8631 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
8633 /* VFP DP Registers. */
8634 REGSET(d,VFD), REGSET(D,VFS),
8636 /* VFP control registers. */
8637 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
8638 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
8640 /* Maverick DSP coprocessor registers. */
8641 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
8642 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
8644 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
8645 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
8646 REGDEF(dspsc,0,DSPSC),
8648 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
8649 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
8650 REGDEF(DSPSC,0,DSPSC),
8652 /* iWMMXt data registers - p0, c0-15. */
8653 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
8655 /* iWMMXt control registers - p1, c0-3. */
8656 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
8657 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
8658 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
8659 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
8661 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
8662 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
8663 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
8664 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
8665 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
8667 /* XScale accumulator registers. */
8668 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
8674 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
8675 within psr_required_here. */
8676 static const struct asm_psr psrs[] =
8678 /* Backward compatibility notation. Note that "all" is no longer
8679 truly all possible PSR bits. */
8680 {"all", PSR_c | PSR_f},
8684 /* Individual flags. */
8689 /* Combinations of flags. */
8690 {"fs", PSR_f | PSR_s},
8691 {"fx", PSR_f | PSR_x},
8692 {"fc", PSR_f | PSR_c},
8693 {"sf", PSR_s | PSR_f},
8694 {"sx", PSR_s | PSR_x},
8695 {"sc", PSR_s | PSR_c},
8696 {"xf", PSR_x | PSR_f},
8697 {"xs", PSR_x | PSR_s},
8698 {"xc", PSR_x | PSR_c},
8699 {"cf", PSR_c | PSR_f},
8700 {"cs", PSR_c | PSR_s},
8701 {"cx", PSR_c | PSR_x},
8702 {"fsx", PSR_f | PSR_s | PSR_x},
8703 {"fsc", PSR_f | PSR_s | PSR_c},
8704 {"fxs", PSR_f | PSR_x | PSR_s},
8705 {"fxc", PSR_f | PSR_x | PSR_c},
8706 {"fcs", PSR_f | PSR_c | PSR_s},
8707 {"fcx", PSR_f | PSR_c | PSR_x},
8708 {"sfx", PSR_s | PSR_f | PSR_x},
8709 {"sfc", PSR_s | PSR_f | PSR_c},
8710 {"sxf", PSR_s | PSR_x | PSR_f},
8711 {"sxc", PSR_s | PSR_x | PSR_c},
8712 {"scf", PSR_s | PSR_c | PSR_f},
8713 {"scx", PSR_s | PSR_c | PSR_x},
8714 {"xfs", PSR_x | PSR_f | PSR_s},
8715 {"xfc", PSR_x | PSR_f | PSR_c},
8716 {"xsf", PSR_x | PSR_s | PSR_f},
8717 {"xsc", PSR_x | PSR_s | PSR_c},
8718 {"xcf", PSR_x | PSR_c | PSR_f},
8719 {"xcs", PSR_x | PSR_c | PSR_s},
8720 {"cfs", PSR_c | PSR_f | PSR_s},
8721 {"cfx", PSR_c | PSR_f | PSR_x},
8722 {"csf", PSR_c | PSR_s | PSR_f},
8723 {"csx", PSR_c | PSR_s | PSR_x},
8724 {"cxf", PSR_c | PSR_x | PSR_f},
8725 {"cxs", PSR_c | PSR_x | PSR_s},
8726 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
8727 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
8728 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
8729 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
8730 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
8731 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
8732 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
8733 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
8734 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
8735 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
8736 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
8737 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
8738 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
8739 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
8740 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
8741 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
8742 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
8743 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
8744 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
8745 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
8746 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
8747 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
8748 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
8749 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
8752 /* Table of V7M psr names. */
8753 static const struct asm_psr v7m_psrs[] =
8766 {"basepri_max", 18},
8771 /* Table of all shift-in-operand names. */
8772 static const struct asm_shift_name shift_names [] =
8774 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
8775 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
8776 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
8777 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
8778 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
8779 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
8782 /* Table of all explicit relocation names. */
8784 static struct reloc_entry reloc_names[] =
8786 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
8787 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
8788 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
8789 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
8790 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
8791 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
8792 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
8793 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
8794 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
8795 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
8796 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
8800 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8801 static const struct asm_cond conds[] =
8805 {"cs", 0x2}, {"hs", 0x2},
8806 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8820 static struct asm_barrier_opt barrier_opt_names[] =
8828 /* Table of ARM-format instructions. */
8830 /* Macros for gluing together operand strings. N.B. In all cases
8831 other than OPS0, the trailing OP_stop comes from default
8832 zero-initialization of the unspecified elements of the array. */
8833 #define OPS0() { OP_stop, }
8834 #define OPS1(a) { OP_##a, }
8835 #define OPS2(a,b) { OP_##a,OP_##b, }
8836 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8837 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8838 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8839 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8841 /* These macros abstract out the exact format of the mnemonic table and
8842 save some repeated characters. */
8844 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8845 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8846 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8847 THUMB_VARIANT, do_##ae, do_##te }
8849 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8850 a T_MNEM_xyz enumerator. */
8851 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8852 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8853 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8854 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8856 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8857 infix after the third character. */
8858 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8859 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8860 THUMB_VARIANT, do_##ae, do_##te }
8861 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8862 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8863 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8864 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8866 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8867 appear in the condition table. */
8868 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8869 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8870 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8872 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8873 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8874 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8875 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8876 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8877 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8878 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8879 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8880 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8881 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8882 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8883 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8884 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8885 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8886 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8887 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8888 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8889 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8890 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8891 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8893 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8894 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8895 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8896 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8898 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8899 field is still 0xE. Many of the Thumb variants can be executed
8900 conditionally, so this is checked separately. */
8901 #define TUE(mnem, op, top, nops, ops, ae, te) \
8902 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8903 THUMB_VARIANT, do_##ae, do_##te }
8905 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8906 condition code field. */
8907 #define TUF(mnem, op, top, nops, ops, ae, te) \
8908 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8909 THUMB_VARIANT, do_##ae, do_##te }
8911 /* ARM-only variants of all the above. */
8912 #define CE(mnem, op, nops, ops, ae) \
8913 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8915 #define C3(mnem, op, nops, ops, ae) \
8916 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8918 /* Legacy mnemonics that always have conditional infix after the third
8920 #define CL(mnem, op, nops, ops, ae) \
8921 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8922 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8924 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
8925 #define cCE(mnem, op, nops, ops, ae) \
8926 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8928 /* Legacy coprocessor instructions where conditional infix and conditional
8929 suffix are ambiguous. For consistency this includes all FPA instructions,
8930 not just the potentially ambiguous ones. */
8931 #define cCL(mnem, op, nops, ops, ae) \
8932 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8933 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8935 /* Coprocessor, takes either a suffix or a position-3 infix
8936 (for an FPA corner case). */
8937 #define C3E(mnem, op, nops, ops, ae) \
8938 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
8939 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8941 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8942 { #m1 #m2 #m3, OPS##nops ops, \
8943 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8944 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8946 #define CM(m1, m2, op, nops, ops, ae) \
8947 xCM_(m1, , m2, op, nops, ops, ae), \
8948 xCM_(m1, eq, m2, op, nops, ops, ae), \
8949 xCM_(m1, ne, m2, op, nops, ops, ae), \
8950 xCM_(m1, cs, m2, op, nops, ops, ae), \
8951 xCM_(m1, hs, m2, op, nops, ops, ae), \
8952 xCM_(m1, cc, m2, op, nops, ops, ae), \
8953 xCM_(m1, ul, m2, op, nops, ops, ae), \
8954 xCM_(m1, lo, m2, op, nops, ops, ae), \
8955 xCM_(m1, mi, m2, op, nops, ops, ae), \
8956 xCM_(m1, pl, m2, op, nops, ops, ae), \
8957 xCM_(m1, vs, m2, op, nops, ops, ae), \
8958 xCM_(m1, vc, m2, op, nops, ops, ae), \
8959 xCM_(m1, hi, m2, op, nops, ops, ae), \
8960 xCM_(m1, ls, m2, op, nops, ops, ae), \
8961 xCM_(m1, ge, m2, op, nops, ops, ae), \
8962 xCM_(m1, lt, m2, op, nops, ops, ae), \
8963 xCM_(m1, gt, m2, op, nops, ops, ae), \
8964 xCM_(m1, le, m2, op, nops, ops, ae), \
8965 xCM_(m1, al, m2, op, nops, ops, ae)
8967 #define UE(mnem, op, nops, ops, ae) \
8968 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8970 #define UF(mnem, op, nops, ops, ae) \
8971 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8975 /* Thumb-only, unconditional. */
8976 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8978 static const struct asm_opcode insns[] =
8980 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
8981 #define THUMB_VARIANT &arm_ext_v4t
8982 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8983 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8984 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8985 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8986 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8987 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8988 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8989 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8990 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8991 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8992 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8993 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8994 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8995 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8996 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8997 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8999 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
9000 for setting PSR flag bits. They are obsolete in V6 and do not
9001 have Thumb equivalents. */
9002 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
9003 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
9004 CL(tstp, 110f000, 2, (RR, SH), cmp),
9005 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
9006 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
9007 CL(cmpp, 150f000, 2, (RR, SH), cmp),
9008 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
9009 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
9010 CL(cmnp, 170f000, 2, (RR, SH), cmp),
9012 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
9013 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
9014 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
9015 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
9017 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
9018 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
9019 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
9020 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
9022 tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9023 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9024 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9025 tCE(ldm, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9026 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9027 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9029 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
9030 TCE(svc, f000000, df00, 1, (EXPi), swi, t_swi),
9031 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
9032 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
9035 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
9036 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
9037 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
9039 /* Thumb-compatibility pseudo ops. */
9040 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
9041 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
9042 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
9043 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
9044 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
9045 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
9046 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
9047 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
9048 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
9049 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
9050 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
9051 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
9053 #undef THUMB_VARIANT
9054 #define THUMB_VARIANT &arm_ext_v6
9055 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
9057 /* V1 instructions with no Thumb analogue prior to V6T2. */
9058 #undef THUMB_VARIANT
9059 #define THUMB_VARIANT &arm_ext_v6t2
9060 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
9061 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
9062 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
9063 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
9064 CL(teqp, 130f000, 2, (RR, SH), cmp),
9066 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
9067 TC3(ldrbt, 4700000, f8100e00, 2, (RR, ADDR), ldstt, t_ldstt),
9068 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
9069 TC3(strbt, 4600000, f8000e00, 2, (RR, ADDR), ldstt, t_ldstt),
9071 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9072 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9074 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9075 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
9077 /* V1 instructions with no Thumb analogue at all. */
9078 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
9079 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
9081 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
9082 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
9083 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
9084 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
9085 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
9086 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
9087 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
9088 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
9091 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
9092 #undef THUMB_VARIANT
9093 #define THUMB_VARIANT &arm_ext_v4t
9094 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
9095 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
9097 #undef THUMB_VARIANT
9098 #define THUMB_VARIANT &arm_ext_v6t2
9099 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
9100 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
9102 /* Generic coprocessor instructions. */
9103 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
9104 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
9105 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
9106 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
9107 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
9108 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9109 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9112 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
9113 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
9114 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
9117 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
9118 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
9119 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
9122 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
9123 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
9124 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
9125 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
9126 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
9127 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
9128 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
9129 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
9130 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
9133 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
9134 #undef THUMB_VARIANT
9135 #define THUMB_VARIANT &arm_ext_v4t
9136 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
9137 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
9138 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
9139 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
9140 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
9141 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
9144 #define ARM_VARIANT &arm_ext_v4t_5
9145 /* ARM Architecture 4T. */
9146 /* Note: bx (and blx) are required on V5, even if the processor does
9147 not support Thumb. */
9148 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
9151 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
9152 #undef THUMB_VARIANT
9153 #define THUMB_VARIANT &arm_ext_v5t
9154 /* Note: blx has 2 variants; the .value coded here is for
9155 BLX(2). Only this variant has conditional execution. */
9156 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
9157 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
9159 #undef THUMB_VARIANT
9160 #define THUMB_VARIANT &arm_ext_v6t2
9161 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
9162 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
9163 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
9164 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
9165 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
9166 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
9167 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9168 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
9171 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
9172 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9173 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9174 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9175 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9177 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9178 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
9180 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
9181 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
9182 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
9183 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
9185 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9186 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9187 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9188 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9190 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9191 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9193 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
9194 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
9195 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
9196 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
9199 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
9200 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
9201 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
9202 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
9204 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
9205 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
9208 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
9209 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
9212 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
9213 #undef THUMB_VARIANT
9214 #define THUMB_VARIANT &arm_ext_v6
9215 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
9216 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
9217 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
9218 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
9219 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
9220 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9221 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9222 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9223 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9224 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
9226 #undef THUMB_VARIANT
9227 #define THUMB_VARIANT &arm_ext_v6t2
9228 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
9229 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
9230 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
9232 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
9233 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
9235 /* ARM V6 not included in V7M (eg. integer SIMD). */
9236 #undef THUMB_VARIANT
9237 #define THUMB_VARIANT &arm_ext_v6_notm
9238 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, t_cps),
9239 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
9240 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
9241 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9242 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9243 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9244 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9245 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9246 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9247 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9248 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9249 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9250 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9251 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9252 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9253 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9254 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9255 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9256 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9257 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9258 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9259 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9260 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9261 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9262 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9263 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9264 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9265 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9266 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9267 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9268 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9269 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9270 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9271 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9272 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9273 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9274 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9275 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9276 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9277 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
9278 UF(rfeib, 9900a00, 1, (RRw), rfe),
9279 UF(rfeda, 8100a00, 1, (RRw), rfe),
9280 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
9281 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
9282 UF(rfefa, 9900a00, 1, (RRw), rfe),
9283 UF(rfeea, 8100a00, 1, (RRw), rfe),
9284 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
9285 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9286 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9287 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9288 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9289 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9290 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9291 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9292 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9293 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9294 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9295 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9296 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9297 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9298 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9299 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9300 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9301 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9302 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9303 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9304 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9305 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9306 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9307 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9308 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9309 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9310 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9311 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9312 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
9313 UF(srsib, 9cd0500, 1, (I31w), srs),
9314 UF(srsda, 84d0500, 1, (I31w), srs),
9315 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
9316 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
9317 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
9318 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
9319 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9320 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9321 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
9324 #define ARM_VARIANT &arm_ext_v6k
9325 #undef THUMB_VARIANT
9326 #define THUMB_VARIANT &arm_ext_v6k
9327 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
9328 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
9329 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
9330 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
9332 #undef THUMB_VARIANT
9333 #define THUMB_VARIANT &arm_ext_v6_notm
9334 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
9335 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
9337 #undef THUMB_VARIANT
9338 #define THUMB_VARIANT &arm_ext_v6t2
9339 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9340 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9341 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9342 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9343 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
9346 #define ARM_VARIANT &arm_ext_v6z
9347 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
9350 #define ARM_VARIANT &arm_ext_v6t2
9351 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
9352 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
9353 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9354 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9356 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
9357 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
9358 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
9359 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
9361 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9362 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9363 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9364 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9366 UT(cbnz, b900, 2, (RR, EXP), t_czb),
9367 UT(cbz, b100, 2, (RR, EXP), t_czb),
9368 /* ARM does not really have an IT instruction. */
9369 TUE(it, 0, bf08, 1, (COND), it, t_it),
9370 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
9371 TUE(ite, 0, bf04, 1, (COND), it, t_it),
9372 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
9373 TUE(itet, 0, bf06, 1, (COND), it, t_it),
9374 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
9375 TUE(itee, 0, bf02, 1, (COND), it, t_it),
9376 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
9377 TUE(itett, 0, bf07, 1, (COND), it, t_it),
9378 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
9379 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
9380 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
9381 TUE(itete, 0, bf05, 1, (COND), it, t_it),
9382 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
9383 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
9385 /* Thumb2 only instructions. */
9387 #define ARM_VARIANT NULL
9389 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9390 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9391 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
9392 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
9394 /* Thumb-2 hardware division instructions (R and M profiles only). */
9395 #undef THUMB_VARIANT
9396 #define THUMB_VARIANT &arm_ext_div
9397 TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
9398 TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
9400 /* ARM V7 instructions. */
9402 #define ARM_VARIANT &arm_ext_v7
9403 #undef THUMB_VARIANT
9404 #define THUMB_VARIANT &arm_ext_v7
9405 TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld),
9406 TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
9407 TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
9408 TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
9409 TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
9412 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
9413 cCE(wfs, e200110, 1, (RR), rd),
9414 cCE(rfs, e300110, 1, (RR), rd),
9415 cCE(wfc, e400110, 1, (RR), rd),
9416 cCE(rfc, e500110, 1, (RR), rd),
9418 cCL(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
9419 cCL(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
9420 cCL(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
9421 cCL(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
9423 cCL(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
9424 cCL(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
9425 cCL(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
9426 cCL(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
9428 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
9429 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
9430 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
9431 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
9432 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
9433 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
9434 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
9435 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
9436 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
9437 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
9438 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
9439 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
9441 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
9442 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
9443 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
9444 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
9445 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
9446 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
9447 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
9448 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
9449 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
9450 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
9451 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
9452 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
9454 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
9455 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
9456 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
9457 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
9458 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
9459 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
9460 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
9461 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
9462 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
9463 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
9464 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
9465 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
9467 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
9468 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
9469 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
9470 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
9471 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
9472 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
9473 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
9474 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
9475 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
9476 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
9477 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
9478 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
9480 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
9481 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
9482 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
9483 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
9484 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
9485 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
9486 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
9487 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
9488 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
9489 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
9490 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
9491 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
9493 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
9494 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
9495 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
9496 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
9497 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
9498 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
9499 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
9500 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
9501 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
9502 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
9503 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
9504 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
9506 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
9507 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
9508 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
9509 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
9510 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
9511 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
9512 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
9513 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
9514 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
9515 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
9516 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
9517 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
9519 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
9520 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
9521 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
9522 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
9523 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
9524 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
9525 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
9526 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
9527 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
9528 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
9529 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
9530 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
9532 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
9533 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
9534 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
9535 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
9536 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
9537 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
9538 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
9539 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
9540 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
9541 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
9542 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
9543 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
9545 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
9546 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
9547 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
9548 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
9549 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
9550 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
9551 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
9552 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
9553 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
9554 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
9555 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
9556 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
9558 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
9559 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
9560 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
9561 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
9562 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
9563 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
9564 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
9565 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
9566 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
9567 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
9568 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
9569 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
9571 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
9572 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
9573 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
9574 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
9575 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
9576 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
9577 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
9578 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
9579 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
9580 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
9581 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
9582 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
9584 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
9585 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
9586 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
9587 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
9588 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
9589 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
9590 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
9591 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
9592 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
9593 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
9594 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
9595 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
9597 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
9598 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
9599 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
9600 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
9601 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
9602 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
9603 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
9604 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
9605 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
9606 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
9607 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
9608 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
9610 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
9611 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
9612 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
9613 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
9614 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
9615 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
9616 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
9617 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
9618 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
9619 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
9620 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
9621 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
9623 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
9624 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
9625 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
9626 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
9627 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
9628 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
9629 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
9630 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
9631 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
9632 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
9633 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
9634 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
9636 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
9637 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
9638 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
9639 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
9640 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
9641 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9642 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9643 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9644 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
9645 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
9646 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
9647 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
9649 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
9650 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
9651 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
9652 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
9653 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
9654 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9655 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9656 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9657 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
9658 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
9659 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
9660 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
9662 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
9663 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
9664 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
9665 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
9666 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
9667 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9668 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9669 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9670 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
9671 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
9672 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
9673 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
9675 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
9676 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
9677 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
9678 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
9679 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
9680 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9681 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9682 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9683 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
9684 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
9685 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
9686 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
9688 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
9689 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
9690 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
9691 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
9692 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
9693 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9694 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9695 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9696 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
9697 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
9698 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
9699 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
9701 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
9702 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
9703 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
9704 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
9705 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
9706 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9707 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9708 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9709 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
9710 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
9711 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
9712 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
9714 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
9715 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
9716 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
9717 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
9718 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
9719 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9720 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9721 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9722 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
9723 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
9724 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
9725 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
9727 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
9728 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
9729 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
9730 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
9731 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
9732 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9733 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9734 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9735 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
9736 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
9737 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
9738 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
9740 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
9741 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
9742 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
9743 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
9744 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
9745 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9746 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9747 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9748 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
9749 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
9750 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
9751 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
9753 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
9754 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
9755 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
9756 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
9757 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
9758 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9759 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9760 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9761 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
9762 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
9763 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
9764 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
9766 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9767 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9768 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9769 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9770 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9771 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9772 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9773 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9774 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9775 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9776 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9777 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9779 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9780 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9781 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9782 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9783 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9784 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9785 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9786 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9787 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9788 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9789 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9790 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9792 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9793 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9794 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9795 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9796 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9797 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9798 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9799 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9800 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9801 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9802 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9803 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9805 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
9806 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
9807 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
9808 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
9810 cCL(flts, e000110, 2, (RF, RR), rn_rd),
9811 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
9812 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
9813 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
9814 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
9815 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
9816 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
9817 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
9818 cCL(flte, e080110, 2, (RF, RR), rn_rd),
9819 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
9820 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
9821 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
9823 /* The implementation of the FIX instruction is broken on some
9824 assemblers, in that it accepts a precision specifier as well as a
9825 rounding specifier, despite the fact that this is meaningless.
9826 To be more compatible, we accept it as well, though of course it
9827 does not set any bits. */
9828 cCE(fix, e100110, 2, (RR, RF), rd_rm),
9829 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
9830 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
9831 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
9832 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
9833 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
9834 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
9835 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
9836 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
9837 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
9838 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
9839 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
9840 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
9842 /* Instructions that were new with the real FPA, call them V2. */
9844 #define ARM_VARIANT &fpu_fpa_ext_v2
9845 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9846 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9847 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9848 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9849 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9850 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9853 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
9854 /* Moves and type conversions. */
9855 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
9856 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
9857 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
9858 cCE(fmstat, ef1fa10, 0, (), noargs),
9859 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
9860 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
9861 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
9862 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9863 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
9864 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9865 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
9866 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
9868 /* Memory operations. */
9869 cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
9870 cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
9871 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9872 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9873 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9874 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9875 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9876 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9877 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9878 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9879 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9880 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9881 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9882 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9883 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9884 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9885 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9886 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9888 /* Monadic operations. */
9889 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
9890 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
9891 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
9893 /* Dyadic operations. */
9894 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9895 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9896 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9897 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9898 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9899 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9900 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9901 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9902 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9905 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
9906 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
9907 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
9908 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
9911 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
9912 /* Moves and type conversions. */
9913 cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
9914 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9915 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9916 cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
9917 cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
9918 cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
9919 cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
9920 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9921 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
9922 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9923 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9924 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9925 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9927 /* Memory operations. */
9928 cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
9929 cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
9930 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9931 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9932 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9933 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9934 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9935 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9936 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9937 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9939 /* Monadic operations. */
9940 cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
9941 cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
9942 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
9944 /* Dyadic operations. */
9945 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9946 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9947 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9948 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9949 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9950 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9951 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9952 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9953 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9956 cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
9957 cCE(fcmpzd, eb50b40, 1, (RVD), rd),
9958 cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
9959 cCE(fcmpezd, eb50bc0, 1, (RVD), rd),
9962 #define ARM_VARIANT &fpu_vfp_ext_v2
9963 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9964 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9965 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9966 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
9969 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
9970 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9971 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9972 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9973 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9974 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9975 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9976 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9977 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
9980 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
9981 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9982 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9983 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9984 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9985 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9986 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9987 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9988 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9989 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9990 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9991 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9992 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9993 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9994 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9995 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9996 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9997 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9998 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9999 cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
10000 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
10001 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
10002 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
10003 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
10004 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
10005 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
10006 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
10007 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
10008 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
10009 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
10010 cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
10011 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
10012 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
10013 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
10014 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
10015 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
10016 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
10017 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
10018 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10019 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10020 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10021 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10022 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10023 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10024 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10025 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10026 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10027 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
10028 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10029 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10030 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10031 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10032 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10033 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10034 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10035 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10036 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10037 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10038 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10039 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10040 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10041 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10042 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10043 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10044 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10045 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10046 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10047 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
10048 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
10049 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
10050 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
10051 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10052 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10053 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10054 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10055 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10056 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10057 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10058 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10059 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10060 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10061 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10062 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10063 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10064 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10065 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10066 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10067 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10068 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10069 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
10070 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10071 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10072 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10073 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10074 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10075 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10076 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10077 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10078 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10079 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10080 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10081 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10082 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10083 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10084 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10085 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10086 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10087 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10088 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10089 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10090 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10091 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
10092 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10093 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10094 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10095 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10096 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10097 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10098 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10099 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10100 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10101 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10102 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10103 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10104 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10105 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10106 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10107 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10108 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10109 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
10110 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
10111 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
10112 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
10113 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
10114 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10115 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10116 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10117 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10118 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10119 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10120 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10121 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10122 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10123 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
10124 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
10125 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
10126 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
10127 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
10128 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
10129 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10130 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10131 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10132 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
10133 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
10134 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
10135 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
10136 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
10137 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
10138 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10139 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10140 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10141 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
10142 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
10145 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
10146 cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
10147 cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
10148 cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
10149 cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
10150 cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
10151 cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
10152 cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
10153 cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
10154 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
10155 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
10156 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
10157 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
10158 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
10159 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
10160 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
10161 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
10162 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
10163 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
10164 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
10165 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
10166 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
10167 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
10168 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
10169 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
10170 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
10171 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
10172 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
10173 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
10174 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
10175 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
10176 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
10177 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
10178 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
10179 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
10180 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
10181 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
10182 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
10183 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
10184 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
10185 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
10186 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
10187 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
10188 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
10189 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
10190 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
10191 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
10192 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
10193 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
10194 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
10195 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
10196 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
10197 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
10198 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
10199 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
10200 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
10201 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
10202 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
10203 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
10204 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
10205 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
10206 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
10207 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
10208 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
10209 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
10210 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10211 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
10212 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10213 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
10214 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10215 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
10216 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10217 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
10218 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
10219 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
10220 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
10221 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
10224 #undef THUMB_VARIANT
10247 /* MD interface: bits in the object file. */
10249 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
10250 for use in the a.out file, and stores them in the array pointed to by buf.
10251 This knows about the endian-ness of the target machine and does
10252 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
10253 2 (short) and 4 (long) Floating numbers are put out as a series of
10254 LITTLENUMS (shorts, here at least). */
10257 md_number_to_chars (char * buf, valueT val, int n)
10259 if (target_big_endian)
10260 number_to_chars_bigendian (buf, val, n);
10262 number_to_chars_littleendian (buf, val, n);
10266 md_chars_to_number (char * buf, int n)
10269 unsigned char * where = (unsigned char *) buf;
10271 if (target_big_endian)
10276 result |= (*where++ & 255);
10284 result |= (where[n] & 255);
10291 /* MD interface: Sections. */
10293 /* Estimate the size of a frag before relaxing. Assume everything fits in
10297 md_estimate_size_before_relax (fragS * fragp,
10298 segT segtype ATTRIBUTE_UNUSED)
10304 /* Convert a machine dependent frag. */
10307 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
10309 unsigned long insn;
10310 unsigned long old_op;
10318 buf = fragp->fr_literal + fragp->fr_fix;
10320 old_op = bfd_get_16(abfd, buf);
10321 if (fragp->fr_symbol) {
10322 exp.X_op = O_symbol;
10323 exp.X_add_symbol = fragp->fr_symbol;
10325 exp.X_op = O_constant;
10327 exp.X_add_number = fragp->fr_offset;
10328 opcode = fragp->fr_subtype;
10331 case T_MNEM_ldr_pc:
10332 case T_MNEM_ldr_pc2:
10333 case T_MNEM_ldr_sp:
10334 case T_MNEM_str_sp:
10341 if (fragp->fr_var == 4)
10343 insn = THUMB_OP32(opcode);
10344 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
10346 insn |= (old_op & 0x700) << 4;
10350 insn |= (old_op & 7) << 12;
10351 insn |= (old_op & 0x38) << 13;
10353 insn |= 0x00000c00;
10354 put_thumb32_insn (buf, insn);
10355 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10359 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
10361 pc_rel = (opcode == T_MNEM_ldr_pc2);
10364 if (fragp->fr_var == 4)
10366 insn = THUMB_OP32 (opcode);
10367 insn |= (old_op & 0xf0) << 4;
10368 put_thumb32_insn (buf, insn);
10369 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
10373 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10374 exp.X_add_number -= 4;
10382 if (fragp->fr_var == 4)
10384 int r0off = (opcode == T_MNEM_mov
10385 || opcode == T_MNEM_movs) ? 0 : 8;
10386 insn = THUMB_OP32 (opcode);
10387 insn = (insn & 0xe1ffffff) | 0x10000000;
10388 insn |= (old_op & 0x700) << r0off;
10389 put_thumb32_insn (buf, insn);
10390 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10394 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
10399 if (fragp->fr_var == 4)
10401 insn = THUMB_OP32(opcode);
10402 put_thumb32_insn (buf, insn);
10403 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
10406 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
10410 if (fragp->fr_var == 4)
10412 insn = THUMB_OP32(opcode);
10413 insn |= (old_op & 0xf00) << 14;
10414 put_thumb32_insn (buf, insn);
10415 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
10418 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
10421 case T_MNEM_add_sp:
10422 case T_MNEM_add_pc:
10423 case T_MNEM_inc_sp:
10424 case T_MNEM_dec_sp:
10425 if (fragp->fr_var == 4)
10427 /* ??? Choose between add and addw. */
10428 insn = THUMB_OP32 (opcode);
10429 insn |= (old_op & 0xf0) << 4;
10430 put_thumb32_insn (buf, insn);
10431 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10434 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10442 if (fragp->fr_var == 4)
10444 insn = THUMB_OP32 (opcode);
10445 insn |= (old_op & 0xf0) << 4;
10446 insn |= (old_op & 0xf) << 16;
10447 put_thumb32_insn (buf, insn);
10448 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10451 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10457 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
10459 fixp->fx_file = fragp->fr_file;
10460 fixp->fx_line = fragp->fr_line;
10461 fragp->fr_fix += fragp->fr_var;
10464 /* Return the size of a relaxable immediate operand instruction.
10465 SHIFT and SIZE specify the form of the allowable immediate. */
10467 relax_immediate (fragS *fragp, int size, int shift)
10473 /* ??? Should be able to do better than this. */
10474 if (fragp->fr_symbol)
10477 low = (1 << shift) - 1;
10478 mask = (1 << (shift + size)) - (1 << shift);
10479 offset = fragp->fr_offset;
10480 /* Force misaligned offsets to 32-bit variant. */
10483 if (offset & ~mask)
10488 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
10491 relax_adr (fragS *fragp, asection *sec)
10496 /* Assume worst case for symbols not known to be in the same section. */
10497 if (!S_IS_DEFINED(fragp->fr_symbol)
10498 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10501 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10502 addr = fragp->fr_address + fragp->fr_fix;
10503 addr = (addr + 4) & ~3;
10504 /* Fix the insn as the 4-byte version if the target address is not
10505 sufficiently aligned. This is prevents an infinite loop when two
10506 instructions have contradictory range/alignment requirements. */
10510 if (val < 0 || val > 1020)
10515 /* Return the size of a relaxable add/sub immediate instruction. */
10517 relax_addsub (fragS *fragp, asection *sec)
10522 buf = fragp->fr_literal + fragp->fr_fix;
10523 op = bfd_get_16(sec->owner, buf);
10524 if ((op & 0xf) == ((op >> 4) & 0xf))
10525 return relax_immediate (fragp, 8, 0);
10527 return relax_immediate (fragp, 3, 0);
10531 /* Return the size of a relaxable branch instruction. BITS is the
10532 size of the offset field in the narrow instruction. */
10535 relax_branch (fragS *fragp, asection *sec, int bits)
10541 /* Assume worst case for symbols not known to be in the same section. */
10542 if (!S_IS_DEFINED(fragp->fr_symbol)
10543 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10546 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10547 addr = fragp->fr_address + fragp->fr_fix + 4;
10550 /* Offset is a signed value *2 */
10552 if (val >= limit || val < -limit)
10558 /* Relax a machine dependent frag. This returns the amount by which
10559 the current size of the frag should change. */
10562 arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
10567 oldsize = fragp->fr_var;
10568 switch (fragp->fr_subtype)
10570 case T_MNEM_ldr_pc2:
10571 newsize = relax_adr(fragp, sec);
10573 case T_MNEM_ldr_pc:
10574 case T_MNEM_ldr_sp:
10575 case T_MNEM_str_sp:
10576 newsize = relax_immediate(fragp, 8, 2);
10580 newsize = relax_immediate(fragp, 5, 2);
10584 newsize = relax_immediate(fragp, 5, 1);
10588 newsize = relax_immediate(fragp, 5, 0);
10591 newsize = relax_adr(fragp, sec);
10597 newsize = relax_immediate(fragp, 8, 0);
10600 newsize = relax_branch(fragp, sec, 11);
10603 newsize = relax_branch(fragp, sec, 8);
10605 case T_MNEM_add_sp:
10606 case T_MNEM_add_pc:
10607 newsize = relax_immediate (fragp, 8, 2);
10609 case T_MNEM_inc_sp:
10610 case T_MNEM_dec_sp:
10611 newsize = relax_immediate (fragp, 7, 2);
10617 newsize = relax_addsub (fragp, sec);
10624 fragp->fr_var = -newsize;
10625 md_convert_frag (sec->owner, sec, fragp);
10627 return -(newsize + oldsize);
10629 fragp->fr_var = newsize;
10630 return newsize - oldsize;
10633 /* Round up a section size to the appropriate boundary. */
10636 md_section_align (segT segment ATTRIBUTE_UNUSED,
10642 /* Round all sects to multiple of 4. */
10643 return (size + 3) & ~3;
10647 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10648 of an rs_align_code fragment. */
10651 arm_handle_align (fragS * fragP)
10653 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
10654 static char const thumb_noop[2] = { 0xc0, 0x46 };
10655 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
10656 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
10658 int bytes, fix, noop_size;
10662 if (fragP->fr_type != rs_align_code)
10665 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
10666 p = fragP->fr_literal + fragP->fr_fix;
10669 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
10670 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
10672 if (fragP->tc_frag_data)
10674 if (target_big_endian)
10675 noop = thumb_bigend_noop;
10678 noop_size = sizeof (thumb_noop);
10682 if (target_big_endian)
10683 noop = arm_bigend_noop;
10686 noop_size = sizeof (arm_noop);
10689 if (bytes & (noop_size - 1))
10691 fix = bytes & (noop_size - 1);
10692 memset (p, 0, fix);
10697 while (bytes >= noop_size)
10699 memcpy (p, noop, noop_size);
10701 bytes -= noop_size;
10705 fragP->fr_fix += fix;
10706 fragP->fr_var = noop_size;
10709 /* Called from md_do_align. Used to create an alignment
10710 frag in a code section. */
10713 arm_frag_align_code (int n, int max)
10717 /* We assume that there will never be a requirement
10718 to support alignments greater than 32 bytes. */
10719 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
10720 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
10722 p = frag_var (rs_align_code,
10723 MAX_MEM_FOR_RS_ALIGN_CODE,
10725 (relax_substateT) max,
10732 /* Perform target specific initialisation of a frag. */
10735 arm_init_frag (fragS * fragP)
10737 /* Record whether this frag is in an ARM or a THUMB area. */
10738 fragP->tc_frag_data = thumb_mode;
10742 /* When we change sections we need to issue a new mapping symbol. */
10745 arm_elf_change_section (void)
10748 segment_info_type *seginfo;
10750 /* Link an unlinked unwind index table section to the .text section. */
10751 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
10752 && elf_linked_to_section (now_seg) == NULL)
10753 elf_linked_to_section (now_seg) = text_section;
10755 if (!SEG_NORMAL (now_seg))
10758 flags = bfd_get_section_flags (stdoutput, now_seg);
10760 /* We can ignore sections that only contain debug info. */
10761 if ((flags & SEC_ALLOC) == 0)
10764 seginfo = seg_info (now_seg);
10765 mapstate = seginfo->tc_segment_info_data.mapstate;
10766 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
10770 arm_elf_section_type (const char * str, size_t len)
10772 if (len == 5 && strncmp (str, "exidx", 5) == 0)
10773 return SHT_ARM_EXIDX;
10778 /* Code to deal with unwinding tables. */
10780 static void add_unwind_adjustsp (offsetT);
10782 /* Cenerate and deferred unwind frame offset. */
10785 flush_pending_unwind (void)
10789 offset = unwind.pending_offset;
10790 unwind.pending_offset = 0;
10792 add_unwind_adjustsp (offset);
10795 /* Add an opcode to this list for this function. Two-byte opcodes should
10796 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
10800 add_unwind_opcode (valueT op, int length)
10802 /* Add any deferred stack adjustment. */
10803 if (unwind.pending_offset)
10804 flush_pending_unwind ();
10806 unwind.sp_restored = 0;
10808 if (unwind.opcode_count + length > unwind.opcode_alloc)
10810 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
10811 if (unwind.opcodes)
10812 unwind.opcodes = xrealloc (unwind.opcodes,
10813 unwind.opcode_alloc);
10815 unwind.opcodes = xmalloc (unwind.opcode_alloc);
10820 unwind.opcodes[unwind.opcode_count] = op & 0xff;
10822 unwind.opcode_count++;
10826 /* Add unwind opcodes to adjust the stack pointer. */
10829 add_unwind_adjustsp (offsetT offset)
10833 if (offset > 0x200)
10835 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
10840 /* Long form: 0xb2, uleb128. */
10841 /* This might not fit in a word so add the individual bytes,
10842 remembering the list is built in reverse order. */
10843 o = (valueT) ((offset - 0x204) >> 2);
10845 add_unwind_opcode (0, 1);
10847 /* Calculate the uleb128 encoding of the offset. */
10851 bytes[n] = o & 0x7f;
10857 /* Add the insn. */
10859 add_unwind_opcode (bytes[n - 1], 1);
10860 add_unwind_opcode (0xb2, 1);
10862 else if (offset > 0x100)
10864 /* Two short opcodes. */
10865 add_unwind_opcode (0x3f, 1);
10866 op = (offset - 0x104) >> 2;
10867 add_unwind_opcode (op, 1);
10869 else if (offset > 0)
10871 /* Short opcode. */
10872 op = (offset - 4) >> 2;
10873 add_unwind_opcode (op, 1);
10875 else if (offset < 0)
10878 while (offset > 0x100)
10880 add_unwind_opcode (0x7f, 1);
10883 op = ((offset - 4) >> 2) | 0x40;
10884 add_unwind_opcode (op, 1);
10888 /* Finish the list of unwind opcodes for this function. */
10890 finish_unwind_opcodes (void)
10894 if (unwind.fp_used)
10896 /* Adjust sp as neccessary. */
10897 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
10898 flush_pending_unwind ();
10900 /* After restoring sp from the frame pointer. */
10901 op = 0x90 | unwind.fp_reg;
10902 add_unwind_opcode (op, 1);
10905 flush_pending_unwind ();
10909 /* Start an exception table entry. If idx is nonzero this is an index table
10913 start_unwind_section (const segT text_seg, int idx)
10915 const char * text_name;
10916 const char * prefix;
10917 const char * prefix_once;
10918 const char * group_name;
10922 size_t sec_name_len;
10929 prefix = ELF_STRING_ARM_unwind;
10930 prefix_once = ELF_STRING_ARM_unwind_once;
10931 type = SHT_ARM_EXIDX;
10935 prefix = ELF_STRING_ARM_unwind_info;
10936 prefix_once = ELF_STRING_ARM_unwind_info_once;
10937 type = SHT_PROGBITS;
10940 text_name = segment_name (text_seg);
10941 if (streq (text_name, ".text"))
10944 if (strncmp (text_name, ".gnu.linkonce.t.",
10945 strlen (".gnu.linkonce.t.")) == 0)
10947 prefix = prefix_once;
10948 text_name += strlen (".gnu.linkonce.t.");
10951 prefix_len = strlen (prefix);
10952 text_len = strlen (text_name);
10953 sec_name_len = prefix_len + text_len;
10954 sec_name = xmalloc (sec_name_len + 1);
10955 memcpy (sec_name, prefix, prefix_len);
10956 memcpy (sec_name + prefix_len, text_name, text_len);
10957 sec_name[prefix_len + text_len] = '\0';
10963 /* Handle COMDAT group. */
10964 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
10966 group_name = elf_group_name (text_seg);
10967 if (group_name == NULL)
10969 as_bad ("Group section `%s' has no group signature",
10970 segment_name (text_seg));
10971 ignore_rest_of_line ();
10974 flags |= SHF_GROUP;
10978 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
10980 /* Set the setion link for index tables. */
10982 elf_linked_to_section (now_seg) = text_seg;
10986 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
10987 personality routine data. Returns zero, or the index table value for
10988 and inline entry. */
10991 create_unwind_entry (int have_data)
10996 /* The current word of data. */
10998 /* The number of bytes left in this word. */
11001 finish_unwind_opcodes ();
11003 /* Remember the current text section. */
11004 unwind.saved_seg = now_seg;
11005 unwind.saved_subseg = now_subseg;
11007 start_unwind_section (now_seg, 0);
11009 if (unwind.personality_routine == NULL)
11011 if (unwind.personality_index == -2)
11014 as_bad (_("handerdata in cantunwind frame"));
11015 return 1; /* EXIDX_CANTUNWIND. */
11018 /* Use a default personality routine if none is specified. */
11019 if (unwind.personality_index == -1)
11021 if (unwind.opcode_count > 3)
11022 unwind.personality_index = 1;
11024 unwind.personality_index = 0;
11027 /* Space for the personality routine entry. */
11028 if (unwind.personality_index == 0)
11030 if (unwind.opcode_count > 3)
11031 as_bad (_("too many unwind opcodes for personality routine 0"));
11035 /* All the data is inline in the index table. */
11038 while (unwind.opcode_count > 0)
11040 unwind.opcode_count--;
11041 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
11045 /* Pad with "finish" opcodes. */
11047 data = (data << 8) | 0xb0;
11054 /* We get two opcodes "free" in the first word. */
11055 size = unwind.opcode_count - 2;
11058 /* An extra byte is required for the opcode count. */
11059 size = unwind.opcode_count + 1;
11061 size = (size + 3) >> 2;
11063 as_bad (_("too many unwind opcodes"));
11065 frag_align (2, 0, 0);
11066 record_alignment (now_seg, 2);
11067 unwind.table_entry = expr_build_dot ();
11069 /* Allocate the table entry. */
11070 ptr = frag_more ((size << 2) + 4);
11071 where = frag_now_fix () - ((size << 2) + 4);
11073 switch (unwind.personality_index)
11076 /* ??? Should this be a PLT generating relocation? */
11077 /* Custom personality routine. */
11078 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
11079 BFD_RELOC_ARM_PREL31);
11084 /* Set the first byte to the number of additional words. */
11089 /* ABI defined personality routines. */
11091 /* Three opcodes bytes are packed into the first word. */
11098 /* The size and first two opcode bytes go in the first word. */
11099 data = ((0x80 + unwind.personality_index) << 8) | size;
11104 /* Should never happen. */
11108 /* Pack the opcodes into words (MSB first), reversing the list at the same
11110 while (unwind.opcode_count > 0)
11114 md_number_to_chars (ptr, data, 4);
11119 unwind.opcode_count--;
11121 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
11124 /* Finish off the last word. */
11127 /* Pad with "finish" opcodes. */
11129 data = (data << 8) | 0xb0;
11131 md_number_to_chars (ptr, data, 4);
11136 /* Add an empty descriptor if there is no user-specified data. */
11137 ptr = frag_more (4);
11138 md_number_to_chars (ptr, 0, 4);
11144 /* Convert REGNAME to a DWARF-2 register number. */
11147 tc_arm_regname_to_dw2regnum (const char *regname)
11149 int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN);
11157 /* Initialize the DWARF-2 unwind information for this procedure. */
11160 tc_arm_frame_initial_instructions (void)
11162 cfi_add_CFA_def_cfa (REG_SP, 0);
11164 #endif /* OBJ_ELF */
11167 /* MD interface: Symbol and relocation handling. */
11169 /* Return the address within the segment that a PC-relative fixup is
11170 relative to. For ARM, PC-relative fixups applied to instructions
11171 are generally relative to the location of the fixup plus 8 bytes.
11172 Thumb branches are offset by 4, and Thumb loads relative to PC
11173 require special handling. */
11176 md_pcrel_from_section (fixS * fixP, segT seg)
11178 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
11180 /* If this is pc-relative and we are going to emit a relocation
11181 then we just want to put out any pipeline compensation that the linker
11182 will need. Otherwise we want to use the calculated base. */
11184 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
11185 || arm_force_relocation (fixP)))
11188 switch (fixP->fx_r_type)
11190 /* PC relative addressing on the Thumb is slightly odd as the
11191 bottom two bits of the PC are forced to zero for the
11192 calculation. This happens *after* application of the
11193 pipeline offset. However, Thumb adrl already adjusts for
11194 this, so we need not do it again. */
11195 case BFD_RELOC_ARM_THUMB_ADD:
11198 case BFD_RELOC_ARM_THUMB_OFFSET:
11199 case BFD_RELOC_ARM_T32_OFFSET_IMM:
11200 case BFD_RELOC_ARM_T32_ADD_PC12:
11201 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
11202 return (base + 4) & ~3;
11204 /* Thumb branches are simply offset by +4. */
11205 case BFD_RELOC_THUMB_PCREL_BRANCH7:
11206 case BFD_RELOC_THUMB_PCREL_BRANCH9:
11207 case BFD_RELOC_THUMB_PCREL_BRANCH12:
11208 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11209 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11210 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11211 case BFD_RELOC_THUMB_PCREL_BLX:
11214 /* ARM mode branches are offset by +8. However, the Windows CE
11215 loader expects the relocation not to take this into account. */
11216 case BFD_RELOC_ARM_PCREL_BRANCH:
11217 case BFD_RELOC_ARM_PCREL_CALL:
11218 case BFD_RELOC_ARM_PCREL_JUMP:
11219 case BFD_RELOC_ARM_PCREL_BLX:
11220 case BFD_RELOC_ARM_PLT32:
11227 /* ARM mode loads relative to PC are also offset by +8. Unlike
11228 branches, the Windows CE loader *does* expect the relocation
11229 to take this into account. */
11230 case BFD_RELOC_ARM_OFFSET_IMM:
11231 case BFD_RELOC_ARM_OFFSET_IMM8:
11232 case BFD_RELOC_ARM_HWLITERAL:
11233 case BFD_RELOC_ARM_LITERAL:
11234 case BFD_RELOC_ARM_CP_OFF_IMM:
11238 /* Other PC-relative relocations are un-offset. */
11244 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
11245 Otherwise we have no need to default values of symbols. */
11248 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
11251 if (name[0] == '_' && name[1] == 'G'
11252 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
11256 if (symbol_find (name))
11257 as_bad ("GOT already in the symbol table");
11259 GOT_symbol = symbol_new (name, undefined_section,
11260 (valueT) 0, & zero_address_frag);
11270 /* Subroutine of md_apply_fix. Check to see if an immediate can be
11271 computed as two separate immediate values, added together. We
11272 already know that this value cannot be computed by just one ARM
11275 static unsigned int
11276 validate_immediate_twopart (unsigned int val,
11277 unsigned int * highpart)
11282 for (i = 0; i < 32; i += 2)
11283 if (((a = rotate_left (val, i)) & 0xff) != 0)
11289 * highpart = (a >> 8) | ((i + 24) << 7);
11291 else if (a & 0xff0000)
11293 if (a & 0xff000000)
11295 * highpart = (a >> 16) | ((i + 16) << 7);
11299 assert (a & 0xff000000);
11300 * highpart = (a >> 24) | ((i + 8) << 7);
11303 return (a & 0xff) | (i << 7);
11310 validate_offset_imm (unsigned int val, int hwse)
11312 if ((hwse && val > 255) || val > 4095)
11317 /* Subroutine of md_apply_fix. Do those data_ops which can take a
11318 negative immediate constant by altering the instruction. A bit of
11323 by inverting the second operand, and
11326 by negating the second operand. */
11329 negate_data_op (unsigned long * instruction,
11330 unsigned long value)
11333 unsigned long negated, inverted;
11335 negated = encode_arm_immediate (-value);
11336 inverted = encode_arm_immediate (~value);
11338 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
11341 /* First negates. */
11342 case OPCODE_SUB: /* ADD <-> SUB */
11343 new_inst = OPCODE_ADD;
11348 new_inst = OPCODE_SUB;
11352 case OPCODE_CMP: /* CMP <-> CMN */
11353 new_inst = OPCODE_CMN;
11358 new_inst = OPCODE_CMP;
11362 /* Now Inverted ops. */
11363 case OPCODE_MOV: /* MOV <-> MVN */
11364 new_inst = OPCODE_MVN;
11369 new_inst = OPCODE_MOV;
11373 case OPCODE_AND: /* AND <-> BIC */
11374 new_inst = OPCODE_BIC;
11379 new_inst = OPCODE_AND;
11383 case OPCODE_ADC: /* ADC <-> SBC */
11384 new_inst = OPCODE_SBC;
11389 new_inst = OPCODE_ADC;
11393 /* We cannot do anything. */
11398 if (value == (unsigned) FAIL)
11401 *instruction &= OPCODE_MASK;
11402 *instruction |= new_inst << DATA_OP_SHIFT;
11406 /* Like negate_data_op, but for Thumb-2. */
11408 static unsigned int
11409 thumb32_negate_data_op (offsetT *instruction, offsetT value)
11413 offsetT negated, inverted;
11415 negated = encode_thumb32_immediate (-value);
11416 inverted = encode_thumb32_immediate (~value);
11418 rd = (*instruction >> 8) & 0xf;
11419 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
11422 /* ADD <-> SUB. Includes CMP <-> CMN. */
11423 case T2_OPCODE_SUB:
11424 new_inst = T2_OPCODE_ADD;
11428 case T2_OPCODE_ADD:
11429 new_inst = T2_OPCODE_SUB;
11433 /* ORR <-> ORN. Includes MOV <-> MVN. */
11434 case T2_OPCODE_ORR:
11435 new_inst = T2_OPCODE_ORN;
11439 case T2_OPCODE_ORN:
11440 new_inst = T2_OPCODE_ORR;
11444 /* AND <-> BIC. TST has no inverted equivalent. */
11445 case T2_OPCODE_AND:
11446 new_inst = T2_OPCODE_BIC;
11453 case T2_OPCODE_BIC:
11454 new_inst = T2_OPCODE_AND;
11459 case T2_OPCODE_ADC:
11460 new_inst = T2_OPCODE_SBC;
11464 case T2_OPCODE_SBC:
11465 new_inst = T2_OPCODE_ADC;
11469 /* We cannot do anything. */
11477 *instruction &= T2_OPCODE_MASK;
11478 *instruction |= new_inst << T2_DATA_OP_SHIFT;
11482 /* Read a 32-bit thumb instruction from buf. */
11483 static unsigned long
11484 get_thumb32_insn (char * buf)
11486 unsigned long insn;
11487 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
11488 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11494 /* We usually want to set the low bit on the address of thumb function
11495 symbols. In particular .word foo - . should have the low bit set.
11496 Generic code tries to fold the difference of two symbols to
11497 a constant. Prevent this and force a relocation when the first symbols
11498 is a thumb function. */
11500 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
11502 if (op == O_subtract
11503 && l->X_op == O_symbol
11504 && r->X_op == O_symbol
11505 && THUMB_IS_FUNC (l->X_add_symbol))
11507 l->X_op = O_subtract;
11508 l->X_op_symbol = r->X_add_symbol;
11509 l->X_add_number -= r->X_add_number;
11512 /* Process as normal. */
11517 md_apply_fix (fixS * fixP,
11521 offsetT value = * valP;
11523 unsigned int newimm;
11524 unsigned long temp;
11526 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
11528 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
11530 /* Note whether this will delete the relocation. */
11531 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
11534 /* On a 64-bit host, silently truncate 'value' to 32 bits for
11535 consistency with the behavior on 32-bit hosts. Remember value
11537 value &= 0xffffffff;
11538 value ^= 0x80000000;
11539 value -= 0x80000000;
11542 fixP->fx_addnumber = value;
11544 /* Same treatment for fixP->fx_offset. */
11545 fixP->fx_offset &= 0xffffffff;
11546 fixP->fx_offset ^= 0x80000000;
11547 fixP->fx_offset -= 0x80000000;
11549 switch (fixP->fx_r_type)
11551 case BFD_RELOC_NONE:
11552 /* This will need to go in the object file. */
11556 case BFD_RELOC_ARM_IMMEDIATE:
11557 /* We claim that this fixup has been processed here,
11558 even if in fact we generate an error because we do
11559 not have a reloc for it, so tc_gen_reloc will reject it. */
11563 && ! S_IS_DEFINED (fixP->fx_addsy))
11565 as_bad_where (fixP->fx_file, fixP->fx_line,
11566 _("undefined symbol %s used as an immediate value"),
11567 S_GET_NAME (fixP->fx_addsy));
11571 newimm = encode_arm_immediate (value);
11572 temp = md_chars_to_number (buf, INSN_SIZE);
11574 /* If the instruction will fail, see if we can fix things up by
11575 changing the opcode. */
11576 if (newimm == (unsigned int) FAIL
11577 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
11579 as_bad_where (fixP->fx_file, fixP->fx_line,
11580 _("invalid constant (%lx) after fixup"),
11581 (unsigned long) value);
11585 newimm |= (temp & 0xfffff000);
11586 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11589 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11591 unsigned int highpart = 0;
11592 unsigned int newinsn = 0xe1a00000; /* nop. */
11594 newimm = encode_arm_immediate (value);
11595 temp = md_chars_to_number (buf, INSN_SIZE);
11597 /* If the instruction will fail, see if we can fix things up by
11598 changing the opcode. */
11599 if (newimm == (unsigned int) FAIL
11600 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
11602 /* No ? OK - try using two ADD instructions to generate
11604 newimm = validate_immediate_twopart (value, & highpart);
11606 /* Yes - then make sure that the second instruction is
11608 if (newimm != (unsigned int) FAIL)
11610 /* Still No ? Try using a negated value. */
11611 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
11612 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
11613 /* Otherwise - give up. */
11616 as_bad_where (fixP->fx_file, fixP->fx_line,
11617 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
11622 /* Replace the first operand in the 2nd instruction (which
11623 is the PC) with the destination register. We have
11624 already added in the PC in the first instruction and we
11625 do not want to do it again. */
11626 newinsn &= ~ 0xf0000;
11627 newinsn |= ((newinsn & 0x0f000) << 4);
11630 newimm |= (temp & 0xfffff000);
11631 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11633 highpart |= (newinsn & 0xfffff000);
11634 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
11638 case BFD_RELOC_ARM_OFFSET_IMM:
11639 if (!fixP->fx_done && seg->use_rela_p)
11642 case BFD_RELOC_ARM_LITERAL:
11648 if (validate_offset_imm (value, 0) == FAIL)
11650 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
11651 as_bad_where (fixP->fx_file, fixP->fx_line,
11652 _("invalid literal constant: pool needs to be closer"));
11654 as_bad_where (fixP->fx_file, fixP->fx_line,
11655 _("bad immediate value for offset (%ld)"),
11660 newval = md_chars_to_number (buf, INSN_SIZE);
11661 newval &= 0xff7ff000;
11662 newval |= value | (sign ? INDEX_UP : 0);
11663 md_number_to_chars (buf, newval, INSN_SIZE);
11666 case BFD_RELOC_ARM_OFFSET_IMM8:
11667 case BFD_RELOC_ARM_HWLITERAL:
11673 if (validate_offset_imm (value, 1) == FAIL)
11675 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
11676 as_bad_where (fixP->fx_file, fixP->fx_line,
11677 _("invalid literal constant: pool needs to be closer"));
11679 as_bad (_("bad immediate value for half-word offset (%ld)"),
11684 newval = md_chars_to_number (buf, INSN_SIZE);
11685 newval &= 0xff7ff0f0;
11686 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
11687 md_number_to_chars (buf, newval, INSN_SIZE);
11690 case BFD_RELOC_ARM_T32_OFFSET_U8:
11691 if (value < 0 || value > 1020 || value % 4 != 0)
11692 as_bad_where (fixP->fx_file, fixP->fx_line,
11693 _("bad immediate value for offset (%ld)"), (long) value);
11696 newval = md_chars_to_number (buf+2, THUMB_SIZE);
11698 md_number_to_chars (buf+2, newval, THUMB_SIZE);
11701 case BFD_RELOC_ARM_T32_OFFSET_IMM:
11702 /* This is a complicated relocation used for all varieties of Thumb32
11703 load/store instruction with immediate offset:
11705 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
11706 *4, optional writeback(W)
11707 (doubleword load/store)
11709 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
11710 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
11711 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
11712 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
11713 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
11715 Uppercase letters indicate bits that are already encoded at
11716 this point. Lowercase letters are our problem. For the
11717 second block of instructions, the secondary opcode nybble
11718 (bits 8..11) is present, and bit 23 is zero, even if this is
11719 a PC-relative operation. */
11720 newval = md_chars_to_number (buf, THUMB_SIZE);
11722 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
11724 if ((newval & 0xf0000000) == 0xe0000000)
11726 /* Doubleword load/store: 8-bit offset, scaled by 4. */
11728 newval |= (1 << 23);
11731 if (value % 4 != 0)
11733 as_bad_where (fixP->fx_file, fixP->fx_line,
11734 _("offset not a multiple of 4"));
11740 as_bad_where (fixP->fx_file, fixP->fx_line,
11741 _("offset out of range"));
11746 else if ((newval & 0x000f0000) == 0x000f0000)
11748 /* PC-relative, 12-bit offset. */
11750 newval |= (1 << 23);
11755 as_bad_where (fixP->fx_file, fixP->fx_line,
11756 _("offset out of range"));
11761 else if ((newval & 0x00000100) == 0x00000100)
11763 /* Writeback: 8-bit, +/- offset. */
11765 newval |= (1 << 9);
11770 as_bad_where (fixP->fx_file, fixP->fx_line,
11771 _("offset out of range"));
11776 else if ((newval & 0x00000f00) == 0x00000e00)
11778 /* T-instruction: positive 8-bit offset. */
11779 if (value < 0 || value > 0xff)
11781 as_bad_where (fixP->fx_file, fixP->fx_line,
11782 _("offset out of range"));
11790 /* Positive 12-bit or negative 8-bit offset. */
11794 newval |= (1 << 23);
11804 as_bad_where (fixP->fx_file, fixP->fx_line,
11805 _("offset out of range"));
11812 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
11813 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
11816 case BFD_RELOC_ARM_SHIFT_IMM:
11817 newval = md_chars_to_number (buf, INSN_SIZE);
11818 if (((unsigned long) value) > 32
11820 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
11822 as_bad_where (fixP->fx_file, fixP->fx_line,
11823 _("shift expression is too large"));
11828 /* Shifts of zero must be done as lsl. */
11830 else if (value == 32)
11832 newval &= 0xfffff07f;
11833 newval |= (value & 0x1f) << 7;
11834 md_number_to_chars (buf, newval, INSN_SIZE);
11837 case BFD_RELOC_ARM_T32_IMMEDIATE:
11838 case BFD_RELOC_ARM_T32_IMM12:
11839 case BFD_RELOC_ARM_T32_ADD_PC12:
11840 /* We claim that this fixup has been processed here,
11841 even if in fact we generate an error because we do
11842 not have a reloc for it, so tc_gen_reloc will reject it. */
11846 && ! S_IS_DEFINED (fixP->fx_addsy))
11848 as_bad_where (fixP->fx_file, fixP->fx_line,
11849 _("undefined symbol %s used as an immediate value"),
11850 S_GET_NAME (fixP->fx_addsy));
11854 newval = md_chars_to_number (buf, THUMB_SIZE);
11856 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
11858 /* FUTURE: Implement analogue of negate_data_op for T32. */
11859 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
11861 newimm = encode_thumb32_immediate (value);
11862 if (newimm == (unsigned int) FAIL)
11863 newimm = thumb32_negate_data_op (&newval, value);
11867 /* 12 bit immediate for addw/subw. */
11871 newval ^= 0x00a00000;
11874 newimm = (unsigned int) FAIL;
11879 if (newimm == (unsigned int)FAIL)
11881 as_bad_where (fixP->fx_file, fixP->fx_line,
11882 _("invalid constant (%lx) after fixup"),
11883 (unsigned long) value);
11887 newval |= (newimm & 0x800) << 15;
11888 newval |= (newimm & 0x700) << 4;
11889 newval |= (newimm & 0x0ff);
11891 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
11892 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
11895 case BFD_RELOC_ARM_SMC:
11896 if (((unsigned long) value) > 0xffff)
11897 as_bad_where (fixP->fx_file, fixP->fx_line,
11898 _("invalid smc expression"));
11899 newval = md_chars_to_number (buf, INSN_SIZE);
11900 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
11901 md_number_to_chars (buf, newval, INSN_SIZE);
11904 case BFD_RELOC_ARM_SWI:
11905 if (fixP->tc_fix_data != 0)
11907 if (((unsigned long) value) > 0xff)
11908 as_bad_where (fixP->fx_file, fixP->fx_line,
11909 _("invalid swi expression"));
11910 newval = md_chars_to_number (buf, THUMB_SIZE);
11912 md_number_to_chars (buf, newval, THUMB_SIZE);
11916 if (((unsigned long) value) > 0x00ffffff)
11917 as_bad_where (fixP->fx_file, fixP->fx_line,
11918 _("invalid swi expression"));
11919 newval = md_chars_to_number (buf, INSN_SIZE);
11921 md_number_to_chars (buf, newval, INSN_SIZE);
11925 case BFD_RELOC_ARM_MULTI:
11926 if (((unsigned long) value) > 0xffff)
11927 as_bad_where (fixP->fx_file, fixP->fx_line,
11928 _("invalid expression in load/store multiple"));
11929 newval = value | md_chars_to_number (buf, INSN_SIZE);
11930 md_number_to_chars (buf, newval, INSN_SIZE);
11934 case BFD_RELOC_ARM_PCREL_CALL:
11935 newval = md_chars_to_number (buf, INSN_SIZE);
11936 if ((newval & 0xf0000000) == 0xf0000000)
11940 goto arm_branch_common;
11942 case BFD_RELOC_ARM_PCREL_JUMP:
11943 case BFD_RELOC_ARM_PLT32:
11945 case BFD_RELOC_ARM_PCREL_BRANCH:
11947 goto arm_branch_common;
11949 case BFD_RELOC_ARM_PCREL_BLX:
11952 /* We are going to store value (shifted right by two) in the
11953 instruction, in a 24 bit, signed field. Bits 26 through 32 either
11954 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
11955 also be be clear. */
11957 as_bad_where (fixP->fx_file, fixP->fx_line,
11958 _("misaligned branch destination"));
11959 if ((value & (offsetT)0xfe000000) != (offsetT)0
11960 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
11961 as_bad_where (fixP->fx_file, fixP->fx_line,
11962 _("branch out of range"));
11964 if (fixP->fx_done || !seg->use_rela_p)
11966 newval = md_chars_to_number (buf, INSN_SIZE);
11967 newval |= (value >> 2) & 0x00ffffff;
11968 /* Set the H bit on BLX instructions. */
11972 newval |= 0x01000000;
11974 newval &= ~0x01000000;
11976 md_number_to_chars (buf, newval, INSN_SIZE);
11980 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
11981 /* CZB can only branch forward. */
11983 as_bad_where (fixP->fx_file, fixP->fx_line,
11984 _("branch out of range"));
11986 if (fixP->fx_done || !seg->use_rela_p)
11988 newval = md_chars_to_number (buf, THUMB_SIZE);
11989 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
11990 md_number_to_chars (buf, newval, THUMB_SIZE);
11994 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
11995 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
11996 as_bad_where (fixP->fx_file, fixP->fx_line,
11997 _("branch out of range"));
11999 if (fixP->fx_done || !seg->use_rela_p)
12001 newval = md_chars_to_number (buf, THUMB_SIZE);
12002 newval |= (value & 0x1ff) >> 1;
12003 md_number_to_chars (buf, newval, THUMB_SIZE);
12007 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
12008 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
12009 as_bad_where (fixP->fx_file, fixP->fx_line,
12010 _("branch out of range"));
12012 if (fixP->fx_done || !seg->use_rela_p)
12014 newval = md_chars_to_number (buf, THUMB_SIZE);
12015 newval |= (value & 0xfff) >> 1;
12016 md_number_to_chars (buf, newval, THUMB_SIZE);
12020 case BFD_RELOC_THUMB_PCREL_BRANCH20:
12021 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
12022 as_bad_where (fixP->fx_file, fixP->fx_line,
12023 _("conditional branch out of range"));
12025 if (fixP->fx_done || !seg->use_rela_p)
12028 addressT S, J1, J2, lo, hi;
12030 S = (value & 0x00100000) >> 20;
12031 J2 = (value & 0x00080000) >> 19;
12032 J1 = (value & 0x00040000) >> 18;
12033 hi = (value & 0x0003f000) >> 12;
12034 lo = (value & 0x00000ffe) >> 1;
12036 newval = md_chars_to_number (buf, THUMB_SIZE);
12037 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
12038 newval |= (S << 10) | hi;
12039 newval2 |= (J1 << 13) | (J2 << 11) | lo;
12040 md_number_to_chars (buf, newval, THUMB_SIZE);
12041 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
12045 case BFD_RELOC_THUMB_PCREL_BLX:
12046 case BFD_RELOC_THUMB_PCREL_BRANCH23:
12047 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
12048 as_bad_where (fixP->fx_file, fixP->fx_line,
12049 _("branch out of range"));
12051 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
12052 /* For a BLX instruction, make sure that the relocation is rounded up
12053 to a word boundary. This follows the semantics of the instruction
12054 which specifies that bit 1 of the target address will come from bit
12055 1 of the base address. */
12056 value = (value + 1) & ~ 1;
12058 if (fixP->fx_done || !seg->use_rela_p)
12062 newval = md_chars_to_number (buf, THUMB_SIZE);
12063 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
12064 newval |= (value & 0x7fffff) >> 12;
12065 newval2 |= (value & 0xfff) >> 1;
12066 md_number_to_chars (buf, newval, THUMB_SIZE);
12067 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
12071 case BFD_RELOC_THUMB_PCREL_BRANCH25:
12072 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
12073 as_bad_where (fixP->fx_file, fixP->fx_line,
12074 _("branch out of range"));
12076 if (fixP->fx_done || !seg->use_rela_p)
12079 addressT S, I1, I2, lo, hi;
12081 S = (value & 0x01000000) >> 24;
12082 I1 = (value & 0x00800000) >> 23;
12083 I2 = (value & 0x00400000) >> 22;
12084 hi = (value & 0x003ff000) >> 12;
12085 lo = (value & 0x00000ffe) >> 1;
12090 newval = md_chars_to_number (buf, THUMB_SIZE);
12091 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
12092 newval |= (S << 10) | hi;
12093 newval2 |= (I1 << 13) | (I2 << 11) | lo;
12094 md_number_to_chars (buf, newval, THUMB_SIZE);
12095 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
12100 if (fixP->fx_done || !seg->use_rela_p)
12101 md_number_to_chars (buf, value, 1);
12105 if (fixP->fx_done || !seg->use_rela_p)
12106 md_number_to_chars (buf, value, 2);
12110 case BFD_RELOC_ARM_TLS_GD32:
12111 case BFD_RELOC_ARM_TLS_LE32:
12112 case BFD_RELOC_ARM_TLS_IE32:
12113 case BFD_RELOC_ARM_TLS_LDM32:
12114 case BFD_RELOC_ARM_TLS_LDO32:
12115 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12118 case BFD_RELOC_ARM_GOT32:
12119 case BFD_RELOC_ARM_GOTOFF:
12120 case BFD_RELOC_ARM_TARGET2:
12121 if (fixP->fx_done || !seg->use_rela_p)
12122 md_number_to_chars (buf, 0, 4);
12126 case BFD_RELOC_RVA:
12128 case BFD_RELOC_ARM_TARGET1:
12129 case BFD_RELOC_ARM_ROSEGREL32:
12130 case BFD_RELOC_ARM_SBREL32:
12131 case BFD_RELOC_32_PCREL:
12132 if (fixP->fx_done || !seg->use_rela_p)
12133 md_number_to_chars (buf, value, 4);
12137 case BFD_RELOC_ARM_PREL31:
12138 if (fixP->fx_done || !seg->use_rela_p)
12140 newval = md_chars_to_number (buf, 4) & 0x80000000;
12141 if ((value ^ (value >> 1)) & 0x40000000)
12143 as_bad_where (fixP->fx_file, fixP->fx_line,
12144 _("rel31 relocation overflow"));
12146 newval |= value & 0x7fffffff;
12147 md_number_to_chars (buf, newval, 4);
12152 case BFD_RELOC_ARM_CP_OFF_IMM:
12153 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
12154 if (value < -1023 || value > 1023 || (value & 3))
12155 as_bad_where (fixP->fx_file, fixP->fx_line,
12156 _("co-processor offset out of range"));
12161 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
12162 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
12163 newval = md_chars_to_number (buf, INSN_SIZE);
12165 newval = get_thumb32_insn (buf);
12166 newval &= 0xff7fff00;
12167 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
12169 newval &= ~WRITE_BACK;
12170 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
12171 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
12172 md_number_to_chars (buf, newval, INSN_SIZE);
12174 put_thumb32_insn (buf, newval);
12177 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
12178 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
12179 if (value < -255 || value > 255)
12180 as_bad_where (fixP->fx_file, fixP->fx_line,
12181 _("co-processor offset out of range"));
12183 goto cp_off_common;
12185 case BFD_RELOC_ARM_THUMB_OFFSET:
12186 newval = md_chars_to_number (buf, THUMB_SIZE);
12187 /* Exactly what ranges, and where the offset is inserted depends
12188 on the type of instruction, we can establish this from the
12190 switch (newval >> 12)
12192 case 4: /* PC load. */
12193 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
12194 forced to zero for these loads; md_pcrel_from has already
12195 compensated for this. */
12197 as_bad_where (fixP->fx_file, fixP->fx_line,
12198 _("invalid offset, target not word aligned (0x%08lX)"),
12199 (((unsigned long) fixP->fx_frag->fr_address
12200 + (unsigned long) fixP->fx_where) & ~3)
12201 + (unsigned long) value);
12203 if (value & ~0x3fc)
12204 as_bad_where (fixP->fx_file, fixP->fx_line,
12205 _("invalid offset, value too big (0x%08lX)"),
12208 newval |= value >> 2;
12211 case 9: /* SP load/store. */
12212 if (value & ~0x3fc)
12213 as_bad_where (fixP->fx_file, fixP->fx_line,
12214 _("invalid offset, value too big (0x%08lX)"),
12216 newval |= value >> 2;
12219 case 6: /* Word load/store. */
12221 as_bad_where (fixP->fx_file, fixP->fx_line,
12222 _("invalid offset, value too big (0x%08lX)"),
12224 newval |= value << 4; /* 6 - 2. */
12227 case 7: /* Byte load/store. */
12229 as_bad_where (fixP->fx_file, fixP->fx_line,
12230 _("invalid offset, value too big (0x%08lX)"),
12232 newval |= value << 6;
12235 case 8: /* Halfword load/store. */
12237 as_bad_where (fixP->fx_file, fixP->fx_line,
12238 _("invalid offset, value too big (0x%08lX)"),
12240 newval |= value << 5; /* 6 - 1. */
12244 as_bad_where (fixP->fx_file, fixP->fx_line,
12245 "Unable to process relocation for thumb opcode: %lx",
12246 (unsigned long) newval);
12249 md_number_to_chars (buf, newval, THUMB_SIZE);
12252 case BFD_RELOC_ARM_THUMB_ADD:
12253 /* This is a complicated relocation, since we use it for all of
12254 the following immediate relocations:
12258 9bit ADD/SUB SP word-aligned
12259 10bit ADD PC/SP word-aligned
12261 The type of instruction being processed is encoded in the
12268 newval = md_chars_to_number (buf, THUMB_SIZE);
12270 int rd = (newval >> 4) & 0xf;
12271 int rs = newval & 0xf;
12272 int subtract = !!(newval & 0x8000);
12274 /* Check for HI regs, only very restricted cases allowed:
12275 Adjusting SP, and using PC or SP to get an address. */
12276 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
12277 || (rs > 7 && rs != REG_SP && rs != REG_PC))
12278 as_bad_where (fixP->fx_file, fixP->fx_line,
12279 _("invalid Hi register with immediate"));
12281 /* If value is negative, choose the opposite instruction. */
12285 subtract = !subtract;
12287 as_bad_where (fixP->fx_file, fixP->fx_line,
12288 _("immediate value out of range"));
12293 if (value & ~0x1fc)
12294 as_bad_where (fixP->fx_file, fixP->fx_line,
12295 _("invalid immediate for stack address calculation"));
12296 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
12297 newval |= value >> 2;
12299 else if (rs == REG_PC || rs == REG_SP)
12301 if (subtract || value & ~0x3fc)
12302 as_bad_where (fixP->fx_file, fixP->fx_line,
12303 _("invalid immediate for address calculation (value = 0x%08lX)"),
12304 (unsigned long) value);
12305 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
12307 newval |= value >> 2;
12312 as_bad_where (fixP->fx_file, fixP->fx_line,
12313 _("immediate value out of range"));
12314 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
12315 newval |= (rd << 8) | value;
12320 as_bad_where (fixP->fx_file, fixP->fx_line,
12321 _("immediate value out of range"));
12322 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
12323 newval |= rd | (rs << 3) | (value << 6);
12326 md_number_to_chars (buf, newval, THUMB_SIZE);
12329 case BFD_RELOC_ARM_THUMB_IMM:
12330 newval = md_chars_to_number (buf, THUMB_SIZE);
12331 if (value < 0 || value > 255)
12332 as_bad_where (fixP->fx_file, fixP->fx_line,
12333 _("invalid immediate: %ld is too large"),
12336 md_number_to_chars (buf, newval, THUMB_SIZE);
12339 case BFD_RELOC_ARM_THUMB_SHIFT:
12340 /* 5bit shift value (0..32). LSL cannot take 32. */
12341 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
12342 temp = newval & 0xf800;
12343 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
12344 as_bad_where (fixP->fx_file, fixP->fx_line,
12345 _("invalid shift value: %ld"), (long) value);
12346 /* Shifts of zero must be encoded as LSL. */
12348 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
12349 /* Shifts of 32 are encoded as zero. */
12350 else if (value == 32)
12352 newval |= value << 6;
12353 md_number_to_chars (buf, newval, THUMB_SIZE);
12356 case BFD_RELOC_VTABLE_INHERIT:
12357 case BFD_RELOC_VTABLE_ENTRY:
12361 case BFD_RELOC_UNUSED:
12363 as_bad_where (fixP->fx_file, fixP->fx_line,
12364 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
12368 /* Translate internal representation of relocation info to BFD target
12372 tc_gen_reloc (asection *section, fixS *fixp)
12375 bfd_reloc_code_real_type code;
12377 reloc = xmalloc (sizeof (arelent));
12379 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
12380 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12381 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12383 if (fixp->fx_pcrel)
12385 if (section->use_rela_p)
12386 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
12388 fixp->fx_offset = reloc->address;
12390 reloc->addend = fixp->fx_offset;
12392 switch (fixp->fx_r_type)
12395 if (fixp->fx_pcrel)
12397 code = BFD_RELOC_8_PCREL;
12402 if (fixp->fx_pcrel)
12404 code = BFD_RELOC_16_PCREL;
12409 if (fixp->fx_pcrel)
12411 code = BFD_RELOC_32_PCREL;
12415 case BFD_RELOC_NONE:
12416 case BFD_RELOC_ARM_PCREL_BRANCH:
12417 case BFD_RELOC_ARM_PCREL_BLX:
12418 case BFD_RELOC_RVA:
12419 case BFD_RELOC_THUMB_PCREL_BRANCH7:
12420 case BFD_RELOC_THUMB_PCREL_BRANCH9:
12421 case BFD_RELOC_THUMB_PCREL_BRANCH12:
12422 case BFD_RELOC_THUMB_PCREL_BRANCH20:
12423 case BFD_RELOC_THUMB_PCREL_BRANCH23:
12424 case BFD_RELOC_THUMB_PCREL_BRANCH25:
12425 case BFD_RELOC_THUMB_PCREL_BLX:
12426 case BFD_RELOC_VTABLE_ENTRY:
12427 case BFD_RELOC_VTABLE_INHERIT:
12428 code = fixp->fx_r_type;
12431 case BFD_RELOC_ARM_LITERAL:
12432 case BFD_RELOC_ARM_HWLITERAL:
12433 /* If this is called then the a literal has
12434 been referenced across a section boundary. */
12435 as_bad_where (fixp->fx_file, fixp->fx_line,
12436 _("literal referenced across section boundary"));
12440 case BFD_RELOC_ARM_GOT32:
12441 case BFD_RELOC_ARM_GOTOFF:
12442 case BFD_RELOC_ARM_PLT32:
12443 case BFD_RELOC_ARM_TARGET1:
12444 case BFD_RELOC_ARM_ROSEGREL32:
12445 case BFD_RELOC_ARM_SBREL32:
12446 case BFD_RELOC_ARM_PREL31:
12447 case BFD_RELOC_ARM_TARGET2:
12448 case BFD_RELOC_ARM_TLS_LE32:
12449 case BFD_RELOC_ARM_TLS_LDO32:
12450 case BFD_RELOC_ARM_PCREL_CALL:
12451 case BFD_RELOC_ARM_PCREL_JUMP:
12452 code = fixp->fx_r_type;
12455 case BFD_RELOC_ARM_TLS_GD32:
12456 case BFD_RELOC_ARM_TLS_IE32:
12457 case BFD_RELOC_ARM_TLS_LDM32:
12458 /* BFD will include the symbol's address in the addend.
12459 But we don't want that, so subtract it out again here. */
12460 if (!S_IS_COMMON (fixp->fx_addsy))
12461 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
12462 code = fixp->fx_r_type;
12466 case BFD_RELOC_ARM_IMMEDIATE:
12467 as_bad_where (fixp->fx_file, fixp->fx_line,
12468 _("internal relocation (type: IMMEDIATE) not fixed up"));
12471 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
12472 as_bad_where (fixp->fx_file, fixp->fx_line,
12473 _("ADRL used for a symbol not defined in the same file"));
12476 case BFD_RELOC_ARM_OFFSET_IMM:
12477 if (section->use_rela_p)
12479 code = fixp->fx_r_type;
12483 if (fixp->fx_addsy != NULL
12484 && !S_IS_DEFINED (fixp->fx_addsy)
12485 && S_IS_LOCAL (fixp->fx_addsy))
12487 as_bad_where (fixp->fx_file, fixp->fx_line,
12488 _("undefined local label `%s'"),
12489 S_GET_NAME (fixp->fx_addsy));
12493 as_bad_where (fixp->fx_file, fixp->fx_line,
12494 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
12501 switch (fixp->fx_r_type)
12503 case BFD_RELOC_NONE: type = "NONE"; break;
12504 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
12505 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
12506 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
12507 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
12508 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
12509 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
12510 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
12511 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
12512 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
12513 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
12514 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
12515 default: type = _("<unknown>"); break;
12517 as_bad_where (fixp->fx_file, fixp->fx_line,
12518 _("cannot represent %s relocation in this object file format"),
12525 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
12527 && fixp->fx_addsy == GOT_symbol)
12529 code = BFD_RELOC_ARM_GOTPC;
12530 reloc->addend = fixp->fx_offset = reloc->address;
12534 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12536 if (reloc->howto == NULL)
12538 as_bad_where (fixp->fx_file, fixp->fx_line,
12539 _("cannot represent %s relocation in this object file format"),
12540 bfd_get_reloc_code_name (code));
12544 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
12545 vtable entry to be used in the relocation's section offset. */
12546 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12547 reloc->address = fixp->fx_offset;
12552 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
12555 cons_fix_new_arm (fragS * frag,
12560 bfd_reloc_code_real_type type;
12564 FIXME: @@ Should look at CPU word size. */
12568 type = BFD_RELOC_8;
12571 type = BFD_RELOC_16;
12575 type = BFD_RELOC_32;
12578 type = BFD_RELOC_64;
12582 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
12585 #if defined OBJ_COFF || defined OBJ_ELF
12587 arm_validate_fix (fixS * fixP)
12589 /* If the destination of the branch is a defined symbol which does not have
12590 the THUMB_FUNC attribute, then we must be calling a function which has
12591 the (interfacearm) attribute. We look for the Thumb entry point to that
12592 function and change the branch to refer to that function instead. */
12593 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
12594 && fixP->fx_addsy != NULL
12595 && S_IS_DEFINED (fixP->fx_addsy)
12596 && ! THUMB_IS_FUNC (fixP->fx_addsy))
12598 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
12604 arm_force_relocation (struct fix * fixp)
12606 #if defined (OBJ_COFF) && defined (TE_PE)
12607 if (fixp->fx_r_type == BFD_RELOC_RVA)
12611 /* Resolve these relocations even if the symbol is extern or weak. */
12612 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
12613 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
12614 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
12615 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
12616 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
12617 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
12620 return generic_force_reloc (fixp);
12624 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
12625 local labels from being added to the output symbol table when they
12626 are used with the ADRL pseudo op. The ADRL relocation should always
12627 be resolved before the binbary is emitted, so it is safe to say that
12628 it is adjustable. */
12631 arm_fix_adjustable (fixS * fixP)
12633 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
12640 /* Relocations against Thumb function names must be left unadjusted,
12641 so that the linker can use this information to correctly set the
12642 bottom bit of their addresses. The MIPS version of this function
12643 also prevents relocations that are mips-16 specific, but I do not
12644 know why it does this.
12647 There is one other problem that ought to be addressed here, but
12648 which currently is not: Taking the address of a label (rather
12649 than a function) and then later jumping to that address. Such
12650 addresses also ought to have their bottom bit set (assuming that
12651 they reside in Thumb code), but at the moment they will not. */
12654 arm_fix_adjustable (fixS * fixP)
12656 if (fixP->fx_addsy == NULL)
12659 if (THUMB_IS_FUNC (fixP->fx_addsy)
12660 && fixP->fx_subsy == NULL)
12663 /* We need the symbol name for the VTABLE entries. */
12664 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12665 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12668 /* Don't allow symbols to be discarded on GOT related relocs. */
12669 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
12670 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
12671 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
12672 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
12673 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
12674 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
12675 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
12676 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
12677 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
12684 elf32_arm_target_format (void)
12687 return (target_big_endian
12688 ? "elf32-bigarm-symbian"
12689 : "elf32-littlearm-symbian");
12690 #elif defined (TE_VXWORKS)
12691 return (target_big_endian
12692 ? "elf32-bigarm-vxworks"
12693 : "elf32-littlearm-vxworks");
12695 if (target_big_endian)
12696 return "elf32-bigarm";
12698 return "elf32-littlearm";
12703 armelf_frob_symbol (symbolS * symp,
12706 elf_frob_symbol (symp, puntp);
12710 /* MD interface: Finalization. */
12712 /* A good place to do this, although this was probably not intended
12713 for this kind of use. We need to dump the literal pool before
12714 references are made to a null symbol pointer. */
12719 literal_pool * pool;
12721 for (pool = list_of_pools; pool; pool = pool->next)
12723 /* Put it at the end of the relevent section. */
12724 subseg_set (pool->section, pool->sub_section);
12726 arm_elf_change_section ();
12732 /* Adjust the symbol table. This marks Thumb symbols as distinct from
12736 arm_adjust_symtab (void)
12741 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12743 if (ARM_IS_THUMB (sym))
12745 if (THUMB_IS_FUNC (sym))
12747 /* Mark the symbol as a Thumb function. */
12748 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
12749 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
12750 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
12752 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
12753 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
12755 as_bad (_("%s: unexpected function type: %d"),
12756 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
12758 else switch (S_GET_STORAGE_CLASS (sym))
12761 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
12764 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
12767 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
12775 if (ARM_IS_INTERWORK (sym))
12776 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
12783 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12785 if (ARM_IS_THUMB (sym))
12787 elf_symbol_type * elf_sym;
12789 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
12790 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
12792 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
12794 /* If it's a .thumb_func, declare it as so,
12795 otherwise tag label as .code 16. */
12796 if (THUMB_IS_FUNC (sym))
12797 elf_sym->internal_elf_sym.st_info =
12798 ELF_ST_INFO (bind, STT_ARM_TFUNC);
12800 elf_sym->internal_elf_sym.st_info =
12801 ELF_ST_INFO (bind, STT_ARM_16BIT);
12808 /* MD interface: Initialization. */
12811 set_constant_flonums (void)
12815 for (i = 0; i < NUM_FLOAT_VALS; i++)
12816 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
12826 if ( (arm_ops_hsh = hash_new ()) == NULL
12827 || (arm_cond_hsh = hash_new ()) == NULL
12828 || (arm_shift_hsh = hash_new ()) == NULL
12829 || (arm_psr_hsh = hash_new ()) == NULL
12830 || (arm_v7m_psr_hsh = hash_new ()) == NULL
12831 || (arm_reg_hsh = hash_new ()) == NULL
12832 || (arm_reloc_hsh = hash_new ()) == NULL
12833 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
12834 as_fatal (_("virtual memory exhausted"));
12836 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
12837 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
12838 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
12839 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
12840 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
12841 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
12842 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
12843 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
12844 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
12845 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i));
12846 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
12847 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
12849 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
12851 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template,
12852 (PTR) (barrier_opt_names + i));
12854 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
12855 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
12858 set_constant_flonums ();
12860 /* Set the cpu variant based on the command-line options. We prefer
12861 -mcpu= over -march= if both are set (as for GCC); and we prefer
12862 -mfpu= over any other way of setting the floating point unit.
12863 Use of legacy options with new options are faulted. */
12866 if (mcpu_cpu_opt || march_cpu_opt)
12867 as_bad (_("use of old and new-style options to set CPU type"));
12869 mcpu_cpu_opt = legacy_cpu;
12871 else if (!mcpu_cpu_opt)
12872 mcpu_cpu_opt = march_cpu_opt;
12877 as_bad (_("use of old and new-style options to set FPU type"));
12879 mfpu_opt = legacy_fpu;
12881 else if (!mfpu_opt)
12883 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
12884 /* Some environments specify a default FPU. If they don't, infer it
12885 from the processor. */
12887 mfpu_opt = mcpu_fpu_opt;
12889 mfpu_opt = march_fpu_opt;
12891 mfpu_opt = &fpu_default;
12898 mfpu_opt = &fpu_default;
12899 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
12900 mfpu_opt = &fpu_arch_vfp_v2;
12902 mfpu_opt = &fpu_arch_fpa;
12908 mcpu_cpu_opt = &cpu_default;
12909 selected_cpu = cpu_default;
12913 selected_cpu = *mcpu_cpu_opt;
12915 mcpu_cpu_opt = &arm_arch_any;
12918 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
12920 arm_arch_used = thumb_arch_used = arm_arch_none;
12922 #if defined OBJ_COFF || defined OBJ_ELF
12924 unsigned int flags = 0;
12926 #if defined OBJ_ELF
12927 flags = meabi_flags;
12929 switch (meabi_flags)
12931 case EF_ARM_EABI_UNKNOWN:
12933 /* Set the flags in the private structure. */
12934 if (uses_apcs_26) flags |= F_APCS26;
12935 if (support_interwork) flags |= F_INTERWORK;
12936 if (uses_apcs_float) flags |= F_APCS_FLOAT;
12937 if (pic_code) flags |= F_PIC;
12938 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
12939 flags |= F_SOFT_FLOAT;
12941 switch (mfloat_abi_opt)
12943 case ARM_FLOAT_ABI_SOFT:
12944 case ARM_FLOAT_ABI_SOFTFP:
12945 flags |= F_SOFT_FLOAT;
12948 case ARM_FLOAT_ABI_HARD:
12949 if (flags & F_SOFT_FLOAT)
12950 as_bad (_("hard-float conflicts with specified fpu"));
12954 /* Using pure-endian doubles (even if soft-float). */
12955 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
12956 flags |= F_VFP_FLOAT;
12958 #if defined OBJ_ELF
12959 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
12960 flags |= EF_ARM_MAVERICK_FLOAT;
12963 case EF_ARM_EABI_VER4:
12964 case EF_ARM_EABI_VER5:
12965 /* No additional flags to set. */
12972 bfd_set_private_flags (stdoutput, flags);
12974 /* We have run out flags in the COFF header to encode the
12975 status of ATPCS support, so instead we create a dummy,
12976 empty, debug section called .arm.atpcs. */
12981 sec = bfd_make_section (stdoutput, ".arm.atpcs");
12985 bfd_set_section_flags
12986 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
12987 bfd_set_section_size (stdoutput, sec, 0);
12988 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
12994 /* Record the CPU type as well. */
12995 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
12996 mach = bfd_mach_arm_iWMMXt;
12997 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
12998 mach = bfd_mach_arm_XScale;
12999 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
13000 mach = bfd_mach_arm_ep9312;
13001 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
13002 mach = bfd_mach_arm_5TE;
13003 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
13005 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
13006 mach = bfd_mach_arm_5T;
13008 mach = bfd_mach_arm_5;
13010 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
13012 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
13013 mach = bfd_mach_arm_4T;
13015 mach = bfd_mach_arm_4;
13017 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
13018 mach = bfd_mach_arm_3M;
13019 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
13020 mach = bfd_mach_arm_3;
13021 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
13022 mach = bfd_mach_arm_2a;
13023 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
13024 mach = bfd_mach_arm_2;
13026 mach = bfd_mach_arm_unknown;
13028 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
13031 /* Command line processing. */
13034 Invocation line includes a switch not recognized by the base assembler.
13035 See if it's a processor-specific option.
13037 This routine is somewhat complicated by the need for backwards
13038 compatibility (since older releases of gcc can't be changed).
13039 The new options try to make the interface as compatible as
13042 New options (supported) are:
13044 -mcpu=<cpu name> Assemble for selected processor
13045 -march=<architecture name> Assemble for selected architecture
13046 -mfpu=<fpu architecture> Assemble for selected FPU.
13047 -EB/-mbig-endian Big-endian
13048 -EL/-mlittle-endian Little-endian
13049 -k Generate PIC code
13050 -mthumb Start in Thumb mode
13051 -mthumb-interwork Code supports ARM/Thumb interworking
13053 For now we will also provide support for:
13055 -mapcs-32 32-bit Program counter
13056 -mapcs-26 26-bit Program counter
13057 -macps-float Floats passed in FP registers
13058 -mapcs-reentrant Reentrant code
13060 (sometime these will probably be replaced with -mapcs=<list of options>
13061 and -matpcs=<list of options>)
13063 The remaining options are only supported for back-wards compatibility.
13064 Cpu variants, the arm part is optional:
13065 -m[arm]1 Currently not supported.
13066 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
13067 -m[arm]3 Arm 3 processor
13068 -m[arm]6[xx], Arm 6 processors
13069 -m[arm]7[xx][t][[d]m] Arm 7 processors
13070 -m[arm]8[10] Arm 8 processors
13071 -m[arm]9[20][tdmi] Arm 9 processors
13072 -mstrongarm[110[0]] StrongARM processors
13073 -mxscale XScale processors
13074 -m[arm]v[2345[t[e]]] Arm architectures
13075 -mall All (except the ARM1)
13077 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
13078 -mfpe-old (No float load/store multiples)
13079 -mvfpxd VFP Single precision
13081 -mno-fpu Disable all floating point instructions
13083 The following CPU names are recognized:
13084 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
13085 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
13086 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
13087 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
13088 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
13089 arm10t arm10e, arm1020t, arm1020e, arm10200e,
13090 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
13094 const char * md_shortopts = "m:k";
13096 #ifdef ARM_BI_ENDIAN
13097 #define OPTION_EB (OPTION_MD_BASE + 0)
13098 #define OPTION_EL (OPTION_MD_BASE + 1)
13100 #if TARGET_BYTES_BIG_ENDIAN
13101 #define OPTION_EB (OPTION_MD_BASE + 0)
13103 #define OPTION_EL (OPTION_MD_BASE + 1)
13107 struct option md_longopts[] =
13110 {"EB", no_argument, NULL, OPTION_EB},
13113 {"EL", no_argument, NULL, OPTION_EL},
13115 {NULL, no_argument, NULL, 0}
13118 size_t md_longopts_size = sizeof (md_longopts);
13120 struct arm_option_table
13122 char *option; /* Option name to match. */
13123 char *help; /* Help information. */
13124 int *var; /* Variable to change. */
13125 int value; /* What to change it to. */
13126 char *deprecated; /* If non-null, print this message. */
13129 struct arm_option_table arm_opts[] =
13131 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
13132 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
13133 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
13134 &support_interwork, 1, NULL},
13135 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
13136 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
13137 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
13139 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
13140 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
13141 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
13142 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
13145 /* These are recognized by the assembler, but have no affect on code. */
13146 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
13147 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
13148 {NULL, NULL, NULL, 0, NULL}
13151 struct arm_legacy_option_table
13153 char *option; /* Option name to match. */
13154 const arm_feature_set **var; /* Variable to change. */
13155 const arm_feature_set value; /* What to change it to. */
13156 char *deprecated; /* If non-null, print this message. */
13159 const struct arm_legacy_option_table arm_legacy_opts[] =
13161 /* DON'T add any new processors to this list -- we want the whole list
13162 to go away... Add them to the processors table instead. */
13163 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
13164 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
13165 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
13166 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
13167 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
13168 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
13169 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
13170 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
13171 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
13172 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
13173 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
13174 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
13175 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
13176 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
13177 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
13178 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
13179 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
13180 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
13181 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
13182 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
13183 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
13184 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
13185 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
13186 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
13187 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
13188 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
13189 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
13190 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
13191 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
13192 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
13193 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
13194 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
13195 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
13196 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
13197 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
13198 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
13199 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
13200 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
13201 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
13202 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
13203 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
13204 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
13205 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
13206 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
13207 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
13208 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
13209 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
13210 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
13211 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
13212 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
13213 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
13214 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
13215 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
13216 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
13217 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
13218 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
13219 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
13220 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
13221 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
13222 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
13223 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
13224 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
13225 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
13226 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
13227 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
13228 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
13229 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
13230 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
13231 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
13232 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
13233 N_("use -mcpu=strongarm110")},
13234 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
13235 N_("use -mcpu=strongarm1100")},
13236 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
13237 N_("use -mcpu=strongarm1110")},
13238 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
13239 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
13240 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
13242 /* Architecture variants -- don't add any more to this list either. */
13243 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
13244 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
13245 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
13246 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
13247 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
13248 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
13249 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
13250 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
13251 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
13252 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
13253 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
13254 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
13255 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
13256 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
13257 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
13258 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
13259 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
13260 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
13262 /* Floating point variants -- don't add any more to this list either. */
13263 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
13264 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
13265 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
13266 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
13267 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
13269 {NULL, NULL, ARM_ARCH_NONE, NULL}
13272 struct arm_cpu_option_table
13275 const arm_feature_set value;
13276 /* For some CPUs we assume an FPU unless the user explicitly sets
13278 const arm_feature_set default_fpu;
13279 /* The canonical name of the CPU, or NULL to use NAME converted to upper
13281 const char *canonical_name;
13284 /* This list should, at a minimum, contain all the cpu names
13285 recognized by GCC. */
13286 static const struct arm_cpu_option_table arm_cpus[] =
13288 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
13289 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
13290 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
13291 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
13292 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
13293 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13294 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13295 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13296 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13297 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13298 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13299 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
13300 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13301 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
13302 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13303 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
13304 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13305 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13306 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13307 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13308 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13309 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13310 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13311 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13312 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13313 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13314 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13315 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
13316 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13317 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13318 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13319 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13320 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13321 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13322 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13323 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13324 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13325 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
13326 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13327 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
13328 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13329 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13330 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13331 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13332 /* For V5 or later processors we default to using VFP; but the user
13333 should really set the FPU type explicitly. */
13334 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13335 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13336 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
13337 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
13338 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
13339 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13340 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
13341 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13342 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13343 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
13344 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13345 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13346 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13347 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13348 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13349 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
13350 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13351 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13352 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13353 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
13354 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
13355 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
13356 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
13357 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
13358 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
13359 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
13360 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
13361 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
13362 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
13363 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
13364 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
13365 {"cortex-a8", ARM_ARCH_V7A, FPU_ARCH_VFP_V2, NULL},
13366 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL},
13367 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL},
13368 /* ??? XSCALE is really an architecture. */
13369 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
13370 /* ??? iwmmxt is not a processor. */
13371 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
13372 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
13374 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
13375 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
13378 struct arm_arch_option_table
13381 const arm_feature_set value;
13382 const arm_feature_set default_fpu;
13385 /* This list should, at a minimum, contain all the architecture names
13386 recognized by GCC. */
13387 static const struct arm_arch_option_table arm_archs[] =
13389 {"all", ARM_ANY, FPU_ARCH_FPA},
13390 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
13391 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
13392 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
13393 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
13394 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
13395 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
13396 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
13397 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
13398 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
13399 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
13400 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
13401 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
13402 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
13403 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
13404 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
13405 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
13406 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
13407 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
13408 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
13409 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
13410 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
13411 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
13412 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
13413 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
13414 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
13415 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
13416 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
13417 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
13418 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
13419 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
13420 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
13421 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
13424 /* ISA extensions in the co-processor space. */
13425 struct arm_option_cpu_value_table
13428 const arm_feature_set value;
13431 static const struct arm_option_cpu_value_table arm_extensions[] =
13433 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
13434 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)},
13435 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
13436 {NULL, ARM_ARCH_NONE}
13439 /* This list should, at a minimum, contain all the fpu names
13440 recognized by GCC. */
13441 static const struct arm_option_cpu_value_table arm_fpus[] =
13443 {"softfpa", FPU_NONE},
13444 {"fpe", FPU_ARCH_FPE},
13445 {"fpe2", FPU_ARCH_FPE},
13446 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
13447 {"fpa", FPU_ARCH_FPA},
13448 {"fpa10", FPU_ARCH_FPA},
13449 {"fpa11", FPU_ARCH_FPA},
13450 {"arm7500fe", FPU_ARCH_FPA},
13451 {"softvfp", FPU_ARCH_VFP},
13452 {"softvfp+vfp", FPU_ARCH_VFP_V2},
13453 {"vfp", FPU_ARCH_VFP_V2},
13454 {"vfp9", FPU_ARCH_VFP_V2},
13455 {"vfp10", FPU_ARCH_VFP_V2},
13456 {"vfp10-r0", FPU_ARCH_VFP_V1},
13457 {"vfpxd", FPU_ARCH_VFP_V1xD},
13458 {"arm1020t", FPU_ARCH_VFP_V1},
13459 {"arm1020e", FPU_ARCH_VFP_V2},
13460 {"arm1136jfs", FPU_ARCH_VFP_V2},
13461 {"arm1136jf-s", FPU_ARCH_VFP_V2},
13462 {"maverick", FPU_ARCH_MAVERICK},
13463 {NULL, ARM_ARCH_NONE}
13466 struct arm_option_value_table
13472 static const struct arm_option_value_table arm_float_abis[] =
13474 {"hard", ARM_FLOAT_ABI_HARD},
13475 {"softfp", ARM_FLOAT_ABI_SOFTFP},
13476 {"soft", ARM_FLOAT_ABI_SOFT},
13481 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
13482 static const struct arm_option_value_table arm_eabis[] =
13484 {"gnu", EF_ARM_EABI_UNKNOWN},
13485 {"4", EF_ARM_EABI_VER4},
13486 {"5", EF_ARM_EABI_VER5},
13491 struct arm_long_option_table
13493 char * option; /* Substring to match. */
13494 char * help; /* Help information. */
13495 int (* func) (char * subopt); /* Function to decode sub-option. */
13496 char * deprecated; /* If non-null, print this message. */
13500 arm_parse_extension (char * str, const arm_feature_set **opt_p)
13502 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set));
13504 /* Copy the feature set, so that we can modify it. */
13505 *ext_set = **opt_p;
13508 while (str != NULL && *str != 0)
13510 const struct arm_option_cpu_value_table * opt;
13516 as_bad (_("invalid architectural extension"));
13521 ext = strchr (str, '+');
13524 optlen = ext - str;
13526 optlen = strlen (str);
13530 as_bad (_("missing architectural extension"));
13534 for (opt = arm_extensions; opt->name != NULL; opt++)
13535 if (strncmp (opt->name, str, optlen) == 0)
13537 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
13541 if (opt->name == NULL)
13543 as_bad (_("unknown architectural extnsion `%s'"), str);
13554 arm_parse_cpu (char * str)
13556 const struct arm_cpu_option_table * opt;
13557 char * ext = strchr (str, '+');
13561 optlen = ext - str;
13563 optlen = strlen (str);
13567 as_bad (_("missing cpu name `%s'"), str);
13571 for (opt = arm_cpus; opt->name != NULL; opt++)
13572 if (strncmp (opt->name, str, optlen) == 0)
13574 mcpu_cpu_opt = &opt->value;
13575 mcpu_fpu_opt = &opt->default_fpu;
13576 if (opt->canonical_name)
13577 strcpy(selected_cpu_name, opt->canonical_name);
13581 for (i = 0; i < optlen; i++)
13582 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13583 selected_cpu_name[i] = 0;
13587 return arm_parse_extension (ext, &mcpu_cpu_opt);
13592 as_bad (_("unknown cpu `%s'"), str);
13597 arm_parse_arch (char * str)
13599 const struct arm_arch_option_table *opt;
13600 char *ext = strchr (str, '+');
13604 optlen = ext - str;
13606 optlen = strlen (str);
13610 as_bad (_("missing architecture name `%s'"), str);
13614 for (opt = arm_archs; opt->name != NULL; opt++)
13615 if (streq (opt->name, str))
13617 march_cpu_opt = &opt->value;
13618 march_fpu_opt = &opt->default_fpu;
13619 strcpy(selected_cpu_name, opt->name);
13622 return arm_parse_extension (ext, &march_cpu_opt);
13627 as_bad (_("unknown architecture `%s'\n"), str);
13632 arm_parse_fpu (char * str)
13634 const struct arm_option_cpu_value_table * opt;
13636 for (opt = arm_fpus; opt->name != NULL; opt++)
13637 if (streq (opt->name, str))
13639 mfpu_opt = &opt->value;
13643 as_bad (_("unknown floating point format `%s'\n"), str);
13648 arm_parse_float_abi (char * str)
13650 const struct arm_option_value_table * opt;
13652 for (opt = arm_float_abis; opt->name != NULL; opt++)
13653 if (streq (opt->name, str))
13655 mfloat_abi_opt = opt->value;
13659 as_bad (_("unknown floating point abi `%s'\n"), str);
13665 arm_parse_eabi (char * str)
13667 const struct arm_option_value_table *opt;
13669 for (opt = arm_eabis; opt->name != NULL; opt++)
13670 if (streq (opt->name, str))
13672 meabi_flags = opt->value;
13675 as_bad (_("unknown EABI `%s'\n"), str);
13680 struct arm_long_option_table arm_long_opts[] =
13682 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
13683 arm_parse_cpu, NULL},
13684 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
13685 arm_parse_arch, NULL},
13686 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
13687 arm_parse_fpu, NULL},
13688 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
13689 arm_parse_float_abi, NULL},
13691 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
13692 arm_parse_eabi, NULL},
13694 {NULL, NULL, 0, NULL}
13698 md_parse_option (int c, char * arg)
13700 struct arm_option_table *opt;
13701 const struct arm_legacy_option_table *fopt;
13702 struct arm_long_option_table *lopt;
13708 target_big_endian = 1;
13714 target_big_endian = 0;
13719 /* Listing option. Just ignore these, we don't support additional
13724 for (opt = arm_opts; opt->option != NULL; opt++)
13726 if (c == opt->option[0]
13727 && ((arg == NULL && opt->option[1] == 0)
13728 || streq (arg, opt->option + 1)))
13730 #if WARN_DEPRECATED
13731 /* If the option is deprecated, tell the user. */
13732 if (opt->deprecated != NULL)
13733 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13734 arg ? arg : "", _(opt->deprecated));
13737 if (opt->var != NULL)
13738 *opt->var = opt->value;
13744 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
13746 if (c == fopt->option[0]
13747 && ((arg == NULL && fopt->option[1] == 0)
13748 || streq (arg, fopt->option + 1)))
13750 #if WARN_DEPRECATED
13751 /* If the option is deprecated, tell the user. */
13752 if (fopt->deprecated != NULL)
13753 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13754 arg ? arg : "", _(fopt->deprecated));
13757 if (fopt->var != NULL)
13758 *fopt->var = &fopt->value;
13764 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13766 /* These options are expected to have an argument. */
13767 if (c == lopt->option[0]
13769 && strncmp (arg, lopt->option + 1,
13770 strlen (lopt->option + 1)) == 0)
13772 #if WARN_DEPRECATED
13773 /* If the option is deprecated, tell the user. */
13774 if (lopt->deprecated != NULL)
13775 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
13776 _(lopt->deprecated));
13779 /* Call the sup-option parser. */
13780 return lopt->func (arg + strlen (lopt->option) - 1);
13791 md_show_usage (FILE * fp)
13793 struct arm_option_table *opt;
13794 struct arm_long_option_table *lopt;
13796 fprintf (fp, _(" ARM-specific assembler options:\n"));
13798 for (opt = arm_opts; opt->option != NULL; opt++)
13799 if (opt->help != NULL)
13800 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
13802 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13803 if (lopt->help != NULL)
13804 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
13808 -EB assemble code for a big-endian cpu\n"));
13813 -EL assemble code for a little-endian cpu\n"));
13822 arm_feature_set flags;
13823 } cpu_arch_ver_table;
13825 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
13826 least features first. */
13827 static const cpu_arch_ver_table cpu_arch_ver[] =
13832 {4, ARM_ARCH_V5TE},
13833 {5, ARM_ARCH_V5TEJ},
13837 {9, ARM_ARCH_V6T2},
13838 {10, ARM_ARCH_V7A},
13839 {10, ARM_ARCH_V7R},
13840 {10, ARM_ARCH_V7M},
13844 /* Set the public EABI object attributes. */
13846 aeabi_set_public_attributes (void)
13849 arm_feature_set flags;
13850 arm_feature_set tmp;
13851 const cpu_arch_ver_table *p;
13853 /* Choose the architecture based on the capabilities of the requested cpu
13854 (if any) and/or the instructions actually used. */
13855 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
13856 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
13857 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
13861 for (p = cpu_arch_ver; p->val; p++)
13863 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
13866 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
13870 /* Tag_CPU_name. */
13871 if (selected_cpu_name[0])
13875 p = selected_cpu_name;
13876 if (strncmp(p, "armv", 4) == 0)
13881 for (i = 0; p[i]; i++)
13882 p[i] = TOUPPER (p[i]);
13884 elf32_arm_add_eabi_attr_string (stdoutput, 5, p);
13886 /* Tag_CPU_arch. */
13887 elf32_arm_add_eabi_attr_int (stdoutput, 6, arch);
13888 /* Tag_CPU_arch_profile. */
13889 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
13890 elf32_arm_add_eabi_attr_int (stdoutput, 7, 'A');
13891 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
13892 elf32_arm_add_eabi_attr_int (stdoutput, 7, 'R');
13893 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
13894 elf32_arm_add_eabi_attr_int (stdoutput, 7, 'M');
13895 /* Tag_ARM_ISA_use. */
13896 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
13897 elf32_arm_add_eabi_attr_int (stdoutput, 8, 1);
13898 /* Tag_THUMB_ISA_use. */
13899 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
13900 elf32_arm_add_eabi_attr_int (stdoutput, 9,
13901 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
13902 /* Tag_VFP_arch. */
13903 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v2)
13904 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v2))
13905 elf32_arm_add_eabi_attr_int (stdoutput, 10, 2);
13906 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v1)
13907 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v1))
13908 elf32_arm_add_eabi_attr_int (stdoutput, 10, 1);
13909 /* Tag_WMMX_arch. */
13910 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
13911 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
13912 elf32_arm_add_eabi_attr_int (stdoutput, 11, 1);
13915 /* Add the .ARM.attributes section. */
13924 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
13927 aeabi_set_public_attributes ();
13928 size = elf32_arm_eabi_attr_size (stdoutput);
13929 s = subseg_new (".ARM.attributes", 0);
13930 bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
13931 addr = frag_now_fix ();
13932 p = frag_more (size);
13933 elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size);
13937 /* Parse a .cpu directive. */
13940 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
13942 const struct arm_cpu_option_table *opt;
13946 name = input_line_pointer;
13947 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13948 input_line_pointer++;
13949 saved_char = *input_line_pointer;
13950 *input_line_pointer = 0;
13952 /* Skip the first "all" entry. */
13953 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
13954 if (streq (opt->name, name))
13956 mcpu_cpu_opt = &opt->value;
13957 selected_cpu = opt->value;
13958 if (opt->canonical_name)
13959 strcpy(selected_cpu_name, opt->canonical_name);
13963 for (i = 0; opt->name[i]; i++)
13964 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13965 selected_cpu_name[i] = 0;
13967 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13968 *input_line_pointer = saved_char;
13969 demand_empty_rest_of_line ();
13972 as_bad (_("unknown cpu `%s'"), name);
13973 *input_line_pointer = saved_char;
13974 ignore_rest_of_line ();
13978 /* Parse a .arch directive. */
13981 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
13983 const struct arm_arch_option_table *opt;
13987 name = input_line_pointer;
13988 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13989 input_line_pointer++;
13990 saved_char = *input_line_pointer;
13991 *input_line_pointer = 0;
13993 /* Skip the first "all" entry. */
13994 for (opt = arm_archs + 1; opt->name != NULL; opt++)
13995 if (streq (opt->name, name))
13997 mcpu_cpu_opt = &opt->value;
13998 selected_cpu = opt->value;
13999 strcpy(selected_cpu_name, opt->name);
14000 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
14001 *input_line_pointer = saved_char;
14002 demand_empty_rest_of_line ();
14006 as_bad (_("unknown architecture `%s'\n"), name);
14007 *input_line_pointer = saved_char;
14008 ignore_rest_of_line ();
14012 /* Parse a .fpu directive. */
14015 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
14017 const struct arm_option_cpu_value_table *opt;
14021 name = input_line_pointer;
14022 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
14023 input_line_pointer++;
14024 saved_char = *input_line_pointer;
14025 *input_line_pointer = 0;
14027 for (opt = arm_fpus; opt->name != NULL; opt++)
14028 if (streq (opt->name, name))
14030 mfpu_opt = &opt->value;
14031 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
14032 *input_line_pointer = saved_char;
14033 demand_empty_rest_of_line ();
14037 as_bad (_("unknown floating point format `%s'\n"), name);
14038 *input_line_pointer = saved_char;
14039 ignore_rest_of_line ();
14041 #endif /* OBJ_ELF */