1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug = -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr = FALSE;
83 int mips_flag_pdr = TRUE;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi = NO_ABI;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls = FALSE;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32 = -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32 = -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts =
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask;
211 unsigned long mips_cprmask[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa = ISA_UNKNOWN;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch = CPU_UNKNOWN;
230 static const char *mips_arch_string;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune = CPU_UNKNOWN;
235 static const char *mips_tune_string;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode = 0;
240 /* True if the given ABI requires 32-bit registers. */
241 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
243 /* Likewise 64-bit registers. */
244 #define ABI_NEEDS_64BIT_REGS(ABI) \
246 || (ABI) == N64_ABI \
249 /* Return true if ISA supports 64 bit gp register instructions. */
250 #define ISA_HAS_64BIT_REGS(ISA) ( \
252 || (ISA) == ISA_MIPS4 \
253 || (ISA) == ISA_MIPS5 \
254 || (ISA) == ISA_MIPS64 \
255 || (ISA) == ISA_MIPS64R2 \
258 /* Return true if ISA supports 64-bit right rotate (dror et al.)
260 #define ISA_HAS_DROR(ISA) ( \
261 (ISA) == ISA_MIPS64R2 \
264 /* Return true if ISA supports 32-bit right rotate (ror et al.)
266 #define ISA_HAS_ROR(ISA) ( \
267 (ISA) == ISA_MIPS32R2 \
268 || (ISA) == ISA_MIPS64R2 \
271 #define HAVE_32BIT_GPRS \
272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
274 #define HAVE_32BIT_FPRS \
275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
277 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
278 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
280 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
282 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
284 /* True if relocations are stored in-place. */
285 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
287 /* We can only have 64bit addresses if the object file format
289 #define HAVE_32BIT_ADDRESSES \
291 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
292 || ! HAVE_64BIT_OBJECTS) \
293 && mips_pic != EMBEDDED_PIC))
295 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
297 /* Addresses are loaded in different ways, depending on the address size
298 in use. The n32 ABI Documentation also mandates the use of additions
299 with overflow checking, but existing implementations don't follow it. */
300 #define ADDRESS_ADD_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
303 #define ADDRESS_ADDI_INSN \
304 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
306 #define ADDRESS_LOAD_INSN \
307 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
309 #define ADDRESS_STORE_INSN \
310 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
312 /* Return true if the given CPU supports the MIPS16 ASE. */
313 #define CPU_HAS_MIPS16(cpu) \
314 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
315 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
317 /* Return true if the given CPU supports the MIPS3D ASE. */
318 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
321 /* Return true if the given CPU supports the MDMX ASE. */
322 #define CPU_HAS_MDMX(cpu) (FALSE \
325 /* True if CPU has a dror instruction. */
326 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
328 /* True if CPU has a ror instruction. */
329 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
331 /* True if mflo and mfhi can be immediately followed by instructions
332 which write to the HI and LO registers.
334 According to MIPS specifications, MIPS ISAs I, II, and III need
335 (at least) two instructions between the reads of HI/LO and
336 instructions which write them, and later ISAs do not. Contradicting
337 the MIPS specifications, some MIPS IV processor user manuals (e.g.
338 the UM for the NEC Vr5000) document needing the instructions between
339 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
340 MIPS64 and later ISAs to have the interlocks, plus any specific
341 earlier-ISA CPUs for which CPU documentation declares that the
342 instructions are really interlocked. */
343 #define hilo_interlocks \
344 (mips_opts.isa == ISA_MIPS32 \
345 || mips_opts.isa == ISA_MIPS32R2 \
346 || mips_opts.isa == ISA_MIPS64 \
347 || mips_opts.isa == ISA_MIPS64R2 \
348 || mips_opts.arch == CPU_R4010 \
349 || mips_opts.arch == CPU_R10000 \
350 || mips_opts.arch == CPU_R12000 \
351 || mips_opts.arch == CPU_RM7000 \
352 || mips_opts.arch == CPU_SB1 \
353 || mips_opts.arch == CPU_VR5500 \
356 /* Whether the processor uses hardware interlocks to protect reads
357 from the GPRs after they are loaded from memory, and thus does not
358 require nops to be inserted. This applies to instructions marked
359 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
361 #define gpr_interlocks \
362 (mips_opts.isa != ISA_MIPS1 \
363 || mips_opts.arch == CPU_VR5400 \
364 || mips_opts.arch == CPU_VR5500 \
365 || mips_opts.arch == CPU_R3900)
367 /* Whether the processor uses hardware interlocks to avoid delays
368 required by coprocessor instructions, and thus does not require
369 nops to be inserted. This applies to instructions marked
370 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
371 between instructions marked INSN_WRITE_COND_CODE and ones marked
372 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
373 levels I, II, and III. */
374 /* Itbl support may require additional care here. */
375 #define cop_interlocks \
376 ((mips_opts.isa != ISA_MIPS1 \
377 && mips_opts.isa != ISA_MIPS2 \
378 && mips_opts.isa != ISA_MIPS3) \
379 || mips_opts.arch == CPU_R4300 \
380 || mips_opts.arch == CPU_VR5400 \
381 || mips_opts.arch == CPU_VR5500 \
382 || mips_opts.arch == CPU_SB1 \
385 /* Whether the processor uses hardware interlocks to protect reads
386 from coprocessor registers after they are loaded from memory, and
387 thus does not require nops to be inserted. This applies to
388 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
389 requires at MIPS ISA level I. */
390 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
392 /* Is this a mfhi or mflo instruction? */
393 #define MF_HILO_INSN(PINFO) \
394 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
396 /* MIPS PIC level. */
398 enum mips_pic_level mips_pic;
400 /* 1 if we should generate 32 bit offsets from the $gp register in
401 SVR4_PIC mode. Currently has no meaning in other modes. */
402 static int mips_big_got = 0;
404 /* 1 if trap instructions should used for overflow rather than break
406 static int mips_trap = 0;
408 /* 1 if double width floating point constants should not be constructed
409 by assembling two single width halves into two single width floating
410 point registers which just happen to alias the double width destination
411 register. On some architectures this aliasing can be disabled by a bit
412 in the status register, and the setting of this bit cannot be determined
413 automatically at assemble time. */
414 static int mips_disable_float_construction;
416 /* Non-zero if any .set noreorder directives were used. */
418 static int mips_any_noreorder;
420 /* Non-zero if nops should be inserted when the register referenced in
421 an mfhi/mflo instruction is read in the next two instructions. */
422 static int mips_7000_hilo_fix;
424 /* The size of the small data section. */
425 static unsigned int g_switch_value = 8;
426 /* Whether the -G option was used. */
427 static int g_switch_seen = 0;
432 /* If we can determine in advance that GP optimization won't be
433 possible, we can skip the relaxation stuff that tries to produce
434 GP-relative references. This makes delay slot optimization work
437 This function can only provide a guess, but it seems to work for
438 gcc output. It needs to guess right for gcc, otherwise gcc
439 will put what it thinks is a GP-relative instruction in a branch
442 I don't know if a fix is needed for the SVR4_PIC mode. I've only
443 fixed it for the non-PIC mode. KR 95/04/07 */
444 static int nopic_need_relax (symbolS *, int);
446 /* handle of the OPCODE hash table */
447 static struct hash_control *op_hash = NULL;
449 /* The opcode hash table we use for the mips16. */
450 static struct hash_control *mips16_op_hash = NULL;
452 /* This array holds the chars that always start a comment. If the
453 pre-processor is disabled, these aren't very useful */
454 const char comment_chars[] = "#";
456 /* This array holds the chars that only start a comment at the beginning of
457 a line. If the line seems to have the form '# 123 filename'
458 .line and .file directives will appear in the pre-processed output */
459 /* Note that input_file.c hand checks for '#' at the beginning of the
460 first line of the input file. This is because the compiler outputs
461 #NO_APP at the beginning of its output. */
462 /* Also note that C style comments are always supported. */
463 const char line_comment_chars[] = "#";
465 /* This array holds machine specific line separator characters. */
466 const char line_separator_chars[] = ";";
468 /* Chars that can be used to separate mant from exp in floating point nums */
469 const char EXP_CHARS[] = "eE";
471 /* Chars that mean this number is a floating point constant */
474 const char FLT_CHARS[] = "rRsSfFdDxXpP";
476 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
477 changed in read.c . Ideally it shouldn't have to know about it at all,
478 but nothing is ideal around here.
481 static char *insn_error;
483 static int auto_align = 1;
485 /* When outputting SVR4 PIC code, the assembler needs to know the
486 offset in the stack frame from which to restore the $gp register.
487 This is set by the .cprestore pseudo-op, and saved in this
489 static offsetT mips_cprestore_offset = -1;
491 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
492 more optimizations, it can use a register value instead of a memory-saved
493 offset and even an other register than $gp as global pointer. */
494 static offsetT mips_cpreturn_offset = -1;
495 static int mips_cpreturn_register = -1;
496 static int mips_gp_register = GP;
497 static int mips_gprel_offset = 0;
499 /* Whether mips_cprestore_offset has been set in the current function
500 (or whether it has already been warned about, if not). */
501 static int mips_cprestore_valid = 0;
503 /* This is the register which holds the stack frame, as set by the
504 .frame pseudo-op. This is needed to implement .cprestore. */
505 static int mips_frame_reg = SP;
507 /* Whether mips_frame_reg has been set in the current function
508 (or whether it has already been warned about, if not). */
509 static int mips_frame_reg_valid = 0;
511 /* To output NOP instructions correctly, we need to keep information
512 about the previous two instructions. */
514 /* Whether we are optimizing. The default value of 2 means to remove
515 unneeded NOPs and swap branch instructions when possible. A value
516 of 1 means to not swap branches. A value of 0 means to always
518 static int mips_optimize = 2;
520 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
521 equivalent to seeing no -g option at all. */
522 static int mips_debug = 0;
524 /* The previous instruction. */
525 static struct mips_cl_insn prev_insn;
527 /* The instruction before prev_insn. */
528 static struct mips_cl_insn prev_prev_insn;
530 /* If we don't want information for prev_insn or prev_prev_insn, we
531 point the insn_mo field at this dummy integer. */
532 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
534 /* Non-zero if prev_insn is valid. */
535 static int prev_insn_valid;
537 /* The frag for the previous instruction. */
538 static struct frag *prev_insn_frag;
540 /* The offset into prev_insn_frag for the previous instruction. */
541 static long prev_insn_where;
543 /* The reloc type for the previous instruction, if any. */
544 static bfd_reloc_code_real_type prev_insn_reloc_type[3];
546 /* The reloc for the previous instruction, if any. */
547 static fixS *prev_insn_fixp[3];
549 /* Non-zero if the previous instruction was in a delay slot. */
550 static int prev_insn_is_delay_slot;
552 /* Non-zero if the previous instruction was in a .set noreorder. */
553 static int prev_insn_unreordered;
555 /* Non-zero if the previous instruction uses an extend opcode (if
557 static int prev_insn_extended;
559 /* Non-zero if the previous previous instruction was in a .set
561 static int prev_prev_insn_unreordered;
563 /* If this is set, it points to a frag holding nop instructions which
564 were inserted before the start of a noreorder section. If those
565 nops turn out to be unnecessary, the size of the frag can be
567 static fragS *prev_nop_frag;
569 /* The number of nop instructions we created in prev_nop_frag. */
570 static int prev_nop_frag_holds;
572 /* The number of nop instructions that we know we need in
574 static int prev_nop_frag_required;
576 /* The number of instructions we've seen since prev_nop_frag. */
577 static int prev_nop_frag_since;
579 /* For ECOFF and ELF, relocations against symbols are done in two
580 parts, with a HI relocation and a LO relocation. Each relocation
581 has only 16 bits of space to store an addend. This means that in
582 order for the linker to handle carries correctly, it must be able
583 to locate both the HI and the LO relocation. This means that the
584 relocations must appear in order in the relocation table.
586 In order to implement this, we keep track of each unmatched HI
587 relocation. We then sort them so that they immediately precede the
588 corresponding LO relocation. */
593 struct mips_hi_fixup *next;
596 /* The section this fixup is in. */
600 /* The list of unmatched HI relocs. */
602 static struct mips_hi_fixup *mips_hi_fixup_list;
604 /* The frag containing the last explicit relocation operator.
605 Null if explicit relocations have not been used. */
607 static fragS *prev_reloc_op_frag;
609 /* Map normal MIPS register numbers to mips16 register numbers. */
611 #define X ILLEGAL_REG
612 static const int mips32_to_16_reg_map[] =
614 X, X, 2, 3, 4, 5, 6, 7,
615 X, X, X, X, X, X, X, X,
616 0, 1, X, X, X, X, X, X,
617 X, X, X, X, X, X, X, X
621 /* Map mips16 register numbers to normal MIPS register numbers. */
623 static const unsigned int mips16_to_32_reg_map[] =
625 16, 17, 2, 3, 4, 5, 6, 7
628 static int mips_fix_vr4120;
630 /* We don't relax branches by default, since this causes us to expand
631 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
632 fail to compute the offset before expanding the macro to the most
633 efficient expansion. */
635 static int mips_relax_branch;
637 /* The expansion of many macros depends on the type of symbol that
638 they refer to. For example, when generating position-dependent code,
639 a macro that refers to a symbol may have two different expansions,
640 one which uses GP-relative addresses and one which uses absolute
641 addresses. When generating SVR4-style PIC, a macro may have
642 different expansions for local and global symbols.
644 We handle these situations by generating both sequences and putting
645 them in variant frags. In position-dependent code, the first sequence
646 will be the GP-relative one and the second sequence will be the
647 absolute one. In SVR4 PIC, the first sequence will be for global
648 symbols and the second will be for local symbols.
650 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
651 SECOND are the lengths of the two sequences in bytes. These fields
652 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
653 the subtype has the following flags:
656 Set if it has been decided that we should use the second
657 sequence instead of the first.
660 Set in the first variant frag if the macro's second implementation
661 is longer than its first. This refers to the macro as a whole,
662 not an individual relaxation.
665 Set in the first variant frag if the macro appeared in a .set nomacro
666 block and if one alternative requires a warning but the other does not.
669 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
672 The frag's "opcode" points to the first fixup for relaxable code.
674 Relaxable macros are generated using a sequence such as:
676 relax_start (SYMBOL);
677 ... generate first expansion ...
679 ... generate second expansion ...
682 The code and fixups for the unwanted alternative are discarded
683 by md_convert_frag. */
684 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
686 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
687 #define RELAX_SECOND(X) ((X) & 0xff)
688 #define RELAX_USE_SECOND 0x10000
689 #define RELAX_SECOND_LONGER 0x20000
690 #define RELAX_NOMACRO 0x40000
691 #define RELAX_DELAY_SLOT 0x80000
693 /* Branch without likely bit. If label is out of range, we turn:
695 beq reg1, reg2, label
705 with the following opcode replacements:
712 bltzal <-> bgezal (with jal label instead of j label)
714 Even though keeping the delay slot instruction in the delay slot of
715 the branch would be more efficient, it would be very tricky to do
716 correctly, because we'd have to introduce a variable frag *after*
717 the delay slot instruction, and expand that instead. Let's do it
718 the easy way for now, even if the branch-not-taken case now costs
719 one additional instruction. Out-of-range branches are not supposed
720 to be common, anyway.
722 Branch likely. If label is out of range, we turn:
724 beql reg1, reg2, label
725 delay slot (annulled if branch not taken)
734 delay slot (executed only if branch taken)
737 It would be possible to generate a shorter sequence by losing the
738 likely bit, generating something like:
743 delay slot (executed only if branch taken)
755 bltzall -> bgezal (with jal label instead of j label)
756 bgezall -> bltzal (ditto)
759 but it's not clear that it would actually improve performance. */
760 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
763 | ((toofar) ? 1 : 0) \
765 | ((likely) ? 4 : 0) \
766 | ((uncond) ? 8 : 0)))
767 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
768 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
769 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
770 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
771 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
773 /* For mips16 code, we use an entirely different form of relaxation.
774 mips16 supports two versions of most instructions which take
775 immediate values: a small one which takes some small value, and a
776 larger one which takes a 16 bit value. Since branches also follow
777 this pattern, relaxing these values is required.
779 We can assemble both mips16 and normal MIPS code in a single
780 object. Therefore, we need to support this type of relaxation at
781 the same time that we support the relaxation described above. We
782 use the high bit of the subtype field to distinguish these cases.
784 The information we store for this type of relaxation is the
785 argument code found in the opcode file for this relocation, whether
786 the user explicitly requested a small or extended form, and whether
787 the relocation is in a jump or jal delay slot. That tells us the
788 size of the value, and how it should be stored. We also store
789 whether the fragment is considered to be extended or not. We also
790 store whether this is known to be a branch to a different section,
791 whether we have tried to relax this frag yet, and whether we have
792 ever extended a PC relative fragment because of a shift count. */
793 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
796 | ((small) ? 0x100 : 0) \
797 | ((ext) ? 0x200 : 0) \
798 | ((dslot) ? 0x400 : 0) \
799 | ((jal_dslot) ? 0x800 : 0))
800 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
801 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
802 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
803 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
804 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
805 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
806 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
807 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
808 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
809 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
810 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
811 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
813 /* Is the given value a sign-extended 32-bit value? */
814 #define IS_SEXT_32BIT_NUM(x) \
815 (((x) &~ (offsetT) 0x7fffffff) == 0 \
816 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
818 /* Is the given value a sign-extended 16-bit value? */
819 #define IS_SEXT_16BIT_NUM(x) \
820 (((x) &~ (offsetT) 0x7fff) == 0 \
821 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
824 /* Global variables used when generating relaxable macros. See the
825 comment above RELAX_ENCODE for more details about how relaxation
828 /* 0 if we're not emitting a relaxable macro.
829 1 if we're emitting the first of the two relaxation alternatives.
830 2 if we're emitting the second alternative. */
833 /* The first relaxable fixup in the current frag. (In other words,
834 the first fixup that refers to relaxable code.) */
837 /* sizes[0] says how many bytes of the first alternative are stored in
838 the current frag. Likewise sizes[1] for the second alternative. */
839 unsigned int sizes[2];
841 /* The symbol on which the choice of sequence depends. */
845 /* Global variables used to decide whether a macro needs a warning. */
847 /* True if the macro is in a branch delay slot. */
848 bfd_boolean delay_slot_p;
850 /* For relaxable macros, sizes[0] is the length of the first alternative
851 in bytes and sizes[1] is the length of the second alternative.
852 For non-relaxable macros, both elements give the length of the
854 unsigned int sizes[2];
856 /* The first variant frag for this macro. */
858 } mips_macro_warning;
860 /* Prototypes for static functions. */
862 #define internalError() \
863 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
865 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
867 static void append_insn
868 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
869 static void mips_no_prev_insn (int);
870 static void mips16_macro_build
871 (expressionS *, const char *, const char *, va_list);
872 static void load_register (int, expressionS *, int);
873 static void macro_start (void);
874 static void macro_end (void);
875 static void macro (struct mips_cl_insn * ip);
876 static void mips16_macro (struct mips_cl_insn * ip);
877 #ifdef LOSING_COMPILER
878 static void macro2 (struct mips_cl_insn * ip);
880 static void mips_ip (char *str, struct mips_cl_insn * ip);
881 static void mips16_ip (char *str, struct mips_cl_insn * ip);
882 static void mips16_immed
883 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
884 unsigned long *, bfd_boolean *, unsigned short *);
885 static size_t my_getSmallExpression
886 (expressionS *, bfd_reloc_code_real_type *, char *);
887 static void my_getExpression (expressionS *, char *);
888 static void s_align (int);
889 static void s_change_sec (int);
890 static void s_change_section (int);
891 static void s_cons (int);
892 static void s_float_cons (int);
893 static void s_mips_globl (int);
894 static void s_option (int);
895 static void s_mipsset (int);
896 static void s_abicalls (int);
897 static void s_cpload (int);
898 static void s_cpsetup (int);
899 static void s_cplocal (int);
900 static void s_cprestore (int);
901 static void s_cpreturn (int);
902 static void s_gpvalue (int);
903 static void s_gpword (int);
904 static void s_gpdword (int);
905 static void s_cpadd (int);
906 static void s_insn (int);
907 static void md_obj_begin (void);
908 static void md_obj_end (void);
909 static void s_mips_ent (int);
910 static void s_mips_end (int);
911 static void s_mips_frame (int);
912 static void s_mips_mask (int reg_type);
913 static void s_mips_stab (int);
914 static void s_mips_weakext (int);
915 static void s_mips_file (int);
916 static void s_mips_loc (int);
917 static bfd_boolean pic_need_relax (symbolS *, asection *);
918 static int relaxed_branch_length (fragS *, asection *, int);
919 static int validate_mips_insn (const struct mips_opcode *);
921 /* Table and functions used to map between CPU/ISA names, and
922 ISA levels, and CPU numbers. */
926 const char *name; /* CPU or ISA name. */
927 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
928 int isa; /* ISA level. */
929 int cpu; /* CPU number (default CPU if ISA). */
932 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
933 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
934 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
938 The following pseudo-ops from the Kane and Heinrich MIPS book
939 should be defined here, but are currently unsupported: .alias,
940 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
942 The following pseudo-ops from the Kane and Heinrich MIPS book are
943 specific to the type of debugging information being generated, and
944 should be defined by the object format: .aent, .begin, .bend,
945 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
948 The following pseudo-ops from the Kane and Heinrich MIPS book are
949 not MIPS CPU specific, but are also not specific to the object file
950 format. This file is probably the best place to define them, but
951 they are not currently supported: .asm0, .endr, .lab, .repeat,
954 static const pseudo_typeS mips_pseudo_table[] =
956 /* MIPS specific pseudo-ops. */
957 {"option", s_option, 0},
958 {"set", s_mipsset, 0},
959 {"rdata", s_change_sec, 'r'},
960 {"sdata", s_change_sec, 's'},
961 {"livereg", s_ignore, 0},
962 {"abicalls", s_abicalls, 0},
963 {"cpload", s_cpload, 0},
964 {"cpsetup", s_cpsetup, 0},
965 {"cplocal", s_cplocal, 0},
966 {"cprestore", s_cprestore, 0},
967 {"cpreturn", s_cpreturn, 0},
968 {"gpvalue", s_gpvalue, 0},
969 {"gpword", s_gpword, 0},
970 {"gpdword", s_gpdword, 0},
971 {"cpadd", s_cpadd, 0},
974 /* Relatively generic pseudo-ops that happen to be used on MIPS
976 {"asciiz", stringer, 1},
977 {"bss", s_change_sec, 'b'},
980 {"dword", s_cons, 3},
981 {"weakext", s_mips_weakext, 0},
983 /* These pseudo-ops are defined in read.c, but must be overridden
984 here for one reason or another. */
985 {"align", s_align, 0},
987 {"data", s_change_sec, 'd'},
988 {"double", s_float_cons, 'd'},
989 {"float", s_float_cons, 'f'},
990 {"globl", s_mips_globl, 0},
991 {"global", s_mips_globl, 0},
992 {"hword", s_cons, 1},
997 {"section", s_change_section, 0},
998 {"short", s_cons, 1},
999 {"single", s_float_cons, 'f'},
1000 {"stabn", s_mips_stab, 'n'},
1001 {"text", s_change_sec, 't'},
1002 {"word", s_cons, 2},
1004 { "extern", ecoff_directive_extern, 0},
1009 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1011 /* These pseudo-ops should be defined by the object file format.
1012 However, a.out doesn't support them, so we have versions here. */
1013 {"aent", s_mips_ent, 1},
1014 {"bgnb", s_ignore, 0},
1015 {"end", s_mips_end, 0},
1016 {"endb", s_ignore, 0},
1017 {"ent", s_mips_ent, 0},
1018 {"file", s_mips_file, 0},
1019 {"fmask", s_mips_mask, 'F'},
1020 {"frame", s_mips_frame, 0},
1021 {"loc", s_mips_loc, 0},
1022 {"mask", s_mips_mask, 'R'},
1023 {"verstamp", s_ignore, 0},
1027 extern void pop_insert (const pseudo_typeS *);
1030 mips_pop_insert (void)
1032 pop_insert (mips_pseudo_table);
1033 if (! ECOFF_DEBUGGING)
1034 pop_insert (mips_nonecoff_pseudo_table);
1037 /* Symbols labelling the current insn. */
1039 struct insn_label_list
1041 struct insn_label_list *next;
1045 static struct insn_label_list *insn_labels;
1046 static struct insn_label_list *free_insn_labels;
1048 static void mips_clear_insn_labels (void);
1051 mips_clear_insn_labels (void)
1053 register struct insn_label_list **pl;
1055 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1061 static char *expr_end;
1063 /* Expressions which appear in instructions. These are set by
1066 static expressionS imm_expr;
1067 static expressionS imm2_expr;
1068 static expressionS offset_expr;
1070 /* Relocs associated with imm_expr and offset_expr. */
1072 static bfd_reloc_code_real_type imm_reloc[3]
1073 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1074 static bfd_reloc_code_real_type offset_reloc[3]
1075 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1077 /* These are set by mips16_ip if an explicit extension is used. */
1079 static bfd_boolean mips16_small, mips16_ext;
1082 /* The pdr segment for per procedure frame/regmask info. Not used for
1085 static segT pdr_seg;
1088 /* The default target format to use. */
1091 mips_target_format (void)
1093 switch (OUTPUT_FLAVOR)
1095 case bfd_target_aout_flavour:
1096 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1097 case bfd_target_ecoff_flavour:
1098 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1099 case bfd_target_coff_flavour:
1101 case bfd_target_elf_flavour:
1103 /* This is traditional mips. */
1104 return (target_big_endian
1105 ? (HAVE_64BIT_OBJECTS
1106 ? "elf64-tradbigmips"
1108 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1109 : (HAVE_64BIT_OBJECTS
1110 ? "elf64-tradlittlemips"
1112 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1114 return (target_big_endian
1115 ? (HAVE_64BIT_OBJECTS
1118 ? "elf32-nbigmips" : "elf32-bigmips"))
1119 : (HAVE_64BIT_OBJECTS
1120 ? "elf64-littlemips"
1122 ? "elf32-nlittlemips" : "elf32-littlemips")));
1130 /* This function is called once, at assembler startup time. It should
1131 set up all the tables, etc. that the MD part of the assembler will need. */
1136 register const char *retval = NULL;
1140 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1141 as_warn (_("Could not set architecture and machine"));
1143 op_hash = hash_new ();
1145 for (i = 0; i < NUMOPCODES;)
1147 const char *name = mips_opcodes[i].name;
1149 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1152 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1153 mips_opcodes[i].name, retval);
1154 /* Probably a memory allocation problem? Give up now. */
1155 as_fatal (_("Broken assembler. No assembly attempted."));
1159 if (mips_opcodes[i].pinfo != INSN_MACRO)
1161 if (!validate_mips_insn (&mips_opcodes[i]))
1166 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1169 mips16_op_hash = hash_new ();
1172 while (i < bfd_mips16_num_opcodes)
1174 const char *name = mips16_opcodes[i].name;
1176 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1178 as_fatal (_("internal: can't hash `%s': %s"),
1179 mips16_opcodes[i].name, retval);
1182 if (mips16_opcodes[i].pinfo != INSN_MACRO
1183 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1184 != mips16_opcodes[i].match))
1186 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1187 mips16_opcodes[i].name, mips16_opcodes[i].args);
1192 while (i < bfd_mips16_num_opcodes
1193 && strcmp (mips16_opcodes[i].name, name) == 0);
1197 as_fatal (_("Broken assembler. No assembly attempted."));
1199 /* We add all the general register names to the symbol table. This
1200 helps us detect invalid uses of them. */
1201 for (i = 0; i < 32; i++)
1205 sprintf (buf, "$%d", i);
1206 symbol_table_insert (symbol_new (buf, reg_section, i,
1207 &zero_address_frag));
1209 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1210 &zero_address_frag));
1211 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1212 &zero_address_frag));
1213 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1214 &zero_address_frag));
1215 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1216 &zero_address_frag));
1217 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1218 &zero_address_frag));
1219 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1220 &zero_address_frag));
1221 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1222 &zero_address_frag));
1223 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1224 &zero_address_frag));
1225 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1226 &zero_address_frag));
1228 /* If we don't add these register names to the symbol table, they
1229 may end up being added as regular symbols by operand(), and then
1230 make it to the object file as undefined in case they're not
1231 regarded as local symbols. They're local in o32, since `$' is a
1232 local symbol prefix, but not in n32 or n64. */
1233 for (i = 0; i < 8; i++)
1237 sprintf (buf, "$fcc%i", i);
1238 symbol_table_insert (symbol_new (buf, reg_section, -1,
1239 &zero_address_frag));
1242 mips_no_prev_insn (FALSE);
1245 mips_cprmask[0] = 0;
1246 mips_cprmask[1] = 0;
1247 mips_cprmask[2] = 0;
1248 mips_cprmask[3] = 0;
1250 /* set the default alignment for the text section (2**2) */
1251 record_alignment (text_section, 2);
1253 if (USE_GLOBAL_POINTER_OPT)
1254 bfd_set_gp_size (stdoutput, g_switch_value);
1256 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1258 /* On a native system, sections must be aligned to 16 byte
1259 boundaries. When configured for an embedded ELF target, we
1261 if (strcmp (TARGET_OS, "elf") != 0)
1263 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1264 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1265 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1268 /* Create a .reginfo section for register masks and a .mdebug
1269 section for debugging information. */
1277 subseg = now_subseg;
1279 /* The ABI says this section should be loaded so that the
1280 running program can access it. However, we don't load it
1281 if we are configured for an embedded target */
1282 flags = SEC_READONLY | SEC_DATA;
1283 if (strcmp (TARGET_OS, "elf") != 0)
1284 flags |= SEC_ALLOC | SEC_LOAD;
1286 if (mips_abi != N64_ABI)
1288 sec = subseg_new (".reginfo", (subsegT) 0);
1290 bfd_set_section_flags (stdoutput, sec, flags);
1291 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1294 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1299 /* The 64-bit ABI uses a .MIPS.options section rather than
1300 .reginfo section. */
1301 sec = subseg_new (".MIPS.options", (subsegT) 0);
1302 bfd_set_section_flags (stdoutput, sec, flags);
1303 bfd_set_section_alignment (stdoutput, sec, 3);
1306 /* Set up the option header. */
1308 Elf_Internal_Options opthdr;
1311 opthdr.kind = ODK_REGINFO;
1312 opthdr.size = (sizeof (Elf_External_Options)
1313 + sizeof (Elf64_External_RegInfo));
1316 f = frag_more (sizeof (Elf_External_Options));
1317 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1318 (Elf_External_Options *) f);
1320 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1325 if (ECOFF_DEBUGGING)
1327 sec = subseg_new (".mdebug", (subsegT) 0);
1328 (void) bfd_set_section_flags (stdoutput, sec,
1329 SEC_HAS_CONTENTS | SEC_READONLY);
1330 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1333 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1335 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1336 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1337 SEC_READONLY | SEC_RELOC
1339 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1343 subseg_set (seg, subseg);
1347 if (! ECOFF_DEBUGGING)
1354 if (! ECOFF_DEBUGGING)
1359 md_assemble (char *str)
1361 struct mips_cl_insn insn;
1362 bfd_reloc_code_real_type unused_reloc[3]
1363 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1365 imm_expr.X_op = O_absent;
1366 imm2_expr.X_op = O_absent;
1367 offset_expr.X_op = O_absent;
1368 imm_reloc[0] = BFD_RELOC_UNUSED;
1369 imm_reloc[1] = BFD_RELOC_UNUSED;
1370 imm_reloc[2] = BFD_RELOC_UNUSED;
1371 offset_reloc[0] = BFD_RELOC_UNUSED;
1372 offset_reloc[1] = BFD_RELOC_UNUSED;
1373 offset_reloc[2] = BFD_RELOC_UNUSED;
1375 if (mips_opts.mips16)
1376 mips16_ip (str, &insn);
1379 mips_ip (str, &insn);
1380 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1381 str, insn.insn_opcode));
1386 as_bad ("%s `%s'", insn_error, str);
1390 if (insn.insn_mo->pinfo == INSN_MACRO)
1393 if (mips_opts.mips16)
1394 mips16_macro (&insn);
1401 if (imm_expr.X_op != O_absent)
1402 append_insn (&insn, &imm_expr, imm_reloc);
1403 else if (offset_expr.X_op != O_absent)
1404 append_insn (&insn, &offset_expr, offset_reloc);
1406 append_insn (&insn, NULL, unused_reloc);
1410 /* Return true if the given relocation might need a matching %lo().
1411 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1412 applied to local symbols. */
1414 static inline bfd_boolean
1415 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1417 return (reloc == BFD_RELOC_HI16_S
1418 || reloc == BFD_RELOC_MIPS_GOT16);
1421 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1424 static inline bfd_boolean
1425 fixup_has_matching_lo_p (fixS *fixp)
1427 return (fixp->fx_next != NULL
1428 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
1429 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1430 && fixp->fx_offset == fixp->fx_next->fx_offset);
1433 /* See whether instruction IP reads register REG. CLASS is the type
1437 insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1438 enum mips_regclass class)
1440 if (class == MIPS16_REG)
1442 assert (mips_opts.mips16);
1443 reg = mips16_to_32_reg_map[reg];
1444 class = MIPS_GR_REG;
1447 /* Don't report on general register ZERO, since it never changes. */
1448 if (class == MIPS_GR_REG && reg == ZERO)
1451 if (class == MIPS_FP_REG)
1453 assert (! mips_opts.mips16);
1454 /* If we are called with either $f0 or $f1, we must check $f0.
1455 This is not optimal, because it will introduce an unnecessary
1456 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1457 need to distinguish reading both $f0 and $f1 or just one of
1458 them. Note that we don't have to check the other way,
1459 because there is no instruction that sets both $f0 and $f1
1460 and requires a delay. */
1461 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1462 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1463 == (reg &~ (unsigned) 1)))
1465 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1466 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1467 == (reg &~ (unsigned) 1)))
1470 else if (! mips_opts.mips16)
1472 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1473 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1475 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1476 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1481 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1482 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1483 & MIPS16OP_MASK_RX)]
1486 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1487 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1488 & MIPS16OP_MASK_RY)]
1491 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1492 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1493 & MIPS16OP_MASK_MOVE32Z)]
1496 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1498 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1500 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1502 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1503 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1504 & MIPS16OP_MASK_REGR32) == reg)
1511 /* This function returns true if modifying a register requires a
1515 reg_needs_delay (unsigned int reg)
1517 unsigned long prev_pinfo;
1519 prev_pinfo = prev_insn.insn_mo->pinfo;
1520 if (! mips_opts.noreorder
1521 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1522 && ! gpr_interlocks)
1523 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1524 && ! cop_interlocks)))
1526 /* A load from a coprocessor or from memory. All load delays
1527 delay the use of general register rt for one instruction. */
1528 /* Itbl support may require additional care here. */
1529 know (prev_pinfo & INSN_WRITE_GPR_T);
1530 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1537 /* Mark instruction labels in mips16 mode. This permits the linker to
1538 handle them specially, such as generating jalx instructions when
1539 needed. We also make them odd for the duration of the assembly, in
1540 order to generate the right sort of code. We will make them even
1541 in the adjust_symtab routine, while leaving them marked. This is
1542 convenient for the debugger and the disassembler. The linker knows
1543 to make them odd again. */
1546 mips16_mark_labels (void)
1548 if (mips_opts.mips16)
1550 struct insn_label_list *l;
1553 for (l = insn_labels; l != NULL; l = l->next)
1556 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1557 S_SET_OTHER (l->label, STO_MIPS16);
1559 val = S_GET_VALUE (l->label);
1561 S_SET_VALUE (l->label, val + 1);
1566 /* End the current frag. Make it a variant frag and record the
1570 relax_close_frag (void)
1572 mips_macro_warning.first_frag = frag_now;
1573 frag_var (rs_machine_dependent, 0, 0,
1574 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
1575 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
1577 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
1578 mips_relax.first_fixup = 0;
1581 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1582 See the comment above RELAX_ENCODE for more details. */
1585 relax_start (symbolS *symbol)
1587 assert (mips_relax.sequence == 0);
1588 mips_relax.sequence = 1;
1589 mips_relax.symbol = symbol;
1592 /* Start generating the second version of a relaxable sequence.
1593 See the comment above RELAX_ENCODE for more details. */
1598 assert (mips_relax.sequence == 1);
1599 mips_relax.sequence = 2;
1602 /* End the current relaxable sequence. */
1607 assert (mips_relax.sequence == 2);
1608 relax_close_frag ();
1609 mips_relax.sequence = 0;
1612 /* Output an instruction. IP is the instruction information.
1613 ADDRESS_EXPR is an operand of the instruction to be used with
1617 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1618 bfd_reloc_code_real_type *reloc_type)
1620 register unsigned long prev_pinfo, pinfo;
1624 relax_stateT prev_insn_frag_type = 0;
1625 bfd_boolean relaxed_branch = FALSE;
1626 bfd_boolean force_new_frag = FALSE;
1628 /* Mark instruction labels in mips16 mode. */
1629 mips16_mark_labels ();
1631 prev_pinfo = prev_insn.insn_mo->pinfo;
1632 pinfo = ip->insn_mo->pinfo;
1634 if (mips_relax.sequence != 2
1635 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1639 /* If the previous insn required any delay slots, see if we need
1640 to insert a NOP or two. There are eight kinds of possible
1641 hazards, of which an instruction can have at most one type.
1642 (1) a load from memory delay
1643 (2) a load from a coprocessor delay
1644 (3) an unconditional branch delay
1645 (4) a conditional branch delay
1646 (5) a move to coprocessor register delay
1647 (6) a load coprocessor register from memory delay
1648 (7) a coprocessor condition code delay
1649 (8) a HI/LO special register delay
1651 There are a lot of optimizations we could do that we don't.
1652 In particular, we do not, in general, reorder instructions.
1653 If you use gcc with optimization, it will reorder
1654 instructions and generally do much more optimization then we
1655 do here; repeating all that work in the assembler would only
1656 benefit hand written assembly code, and does not seem worth
1659 /* This is how a NOP is emitted. */
1660 #define emit_nop() \
1662 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1663 : md_number_to_chars (frag_more (4), 0, 4))
1665 /* The previous insn might require a delay slot, depending upon
1666 the contents of the current insn. */
1667 if (! mips_opts.mips16
1668 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1669 && ! gpr_interlocks)
1670 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1671 && ! cop_interlocks)))
1673 /* A load from a coprocessor or from memory. All load
1674 delays delay the use of general register rt for one
1676 /* Itbl support may require additional care here. */
1677 know (prev_pinfo & INSN_WRITE_GPR_T);
1678 if (mips_optimize == 0
1679 || insn_uses_reg (ip,
1680 ((prev_insn.insn_opcode >> OP_SH_RT)
1685 else if (! mips_opts.mips16
1686 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1687 && ! cop_interlocks)
1688 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1689 && ! cop_mem_interlocks)))
1691 /* A generic coprocessor delay. The previous instruction
1692 modified a coprocessor general or control register. If
1693 it modified a control register, we need to avoid any
1694 coprocessor instruction (this is probably not always
1695 required, but it sometimes is). If it modified a general
1696 register, we avoid using that register.
1698 This case is not handled very well. There is no special
1699 knowledge of CP0 handling, and the coprocessors other
1700 than the floating point unit are not distinguished at
1702 /* Itbl support may require additional care here. FIXME!
1703 Need to modify this to include knowledge about
1704 user specified delays! */
1705 if (prev_pinfo & INSN_WRITE_FPR_T)
1707 if (mips_optimize == 0
1708 || insn_uses_reg (ip,
1709 ((prev_insn.insn_opcode >> OP_SH_FT)
1714 else if (prev_pinfo & INSN_WRITE_FPR_S)
1716 if (mips_optimize == 0
1717 || insn_uses_reg (ip,
1718 ((prev_insn.insn_opcode >> OP_SH_FS)
1725 /* We don't know exactly what the previous instruction
1726 does. If the current instruction uses a coprocessor
1727 register, we must insert a NOP. If previous
1728 instruction may set the condition codes, and the
1729 current instruction uses them, we must insert two
1731 /* Itbl support may require additional care here. */
1732 if (mips_optimize == 0
1733 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1734 && (pinfo & INSN_READ_COND_CODE)))
1736 else if (pinfo & INSN_COP)
1740 else if (! mips_opts.mips16
1741 && (prev_pinfo & INSN_WRITE_COND_CODE)
1742 && ! cop_interlocks)
1744 /* The previous instruction sets the coprocessor condition
1745 codes, but does not require a general coprocessor delay
1746 (this means it is a floating point comparison
1747 instruction). If this instruction uses the condition
1748 codes, we need to insert a single NOP. */
1749 /* Itbl support may require additional care here. */
1750 if (mips_optimize == 0
1751 || (pinfo & INSN_READ_COND_CODE))
1755 /* If we're fixing up mfhi/mflo for the r7000 and the
1756 previous insn was an mfhi/mflo and the current insn
1757 reads the register that the mfhi/mflo wrote to, then
1760 else if (mips_7000_hilo_fix
1761 && MF_HILO_INSN (prev_pinfo)
1762 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1769 /* If we're fixing up mfhi/mflo for the r7000 and the
1770 2nd previous insn was an mfhi/mflo and the current insn
1771 reads the register that the mfhi/mflo wrote to, then
1774 else if (mips_7000_hilo_fix
1775 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1776 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1784 else if (prev_pinfo & INSN_READ_LO)
1786 /* The previous instruction reads the LO register; if the
1787 current instruction writes to the LO register, we must
1788 insert two NOPS. Some newer processors have interlocks.
1789 Also the tx39's multiply instructions can be executed
1790 immediately after a read from HI/LO (without the delay),
1791 though the tx39's divide insns still do require the
1793 if (! (hilo_interlocks
1794 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1795 && (mips_optimize == 0
1796 || (pinfo & INSN_WRITE_LO)))
1798 /* Most mips16 branch insns don't have a delay slot.
1799 If a read from LO is immediately followed by a branch
1800 to a write to LO we have a read followed by a write
1801 less than 2 insns away. We assume the target of
1802 a branch might be a write to LO, and insert a nop
1803 between a read and an immediately following branch. */
1804 else if (mips_opts.mips16
1805 && (mips_optimize == 0
1806 || (pinfo & MIPS16_INSN_BRANCH)))
1809 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1811 /* The previous instruction reads the HI register; if the
1812 current instruction writes to the HI register, we must
1813 insert a NOP. Some newer processors have interlocks.
1814 Also the note tx39's multiply above. */
1815 if (! (hilo_interlocks
1816 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1817 && (mips_optimize == 0
1818 || (pinfo & INSN_WRITE_HI)))
1820 /* Most mips16 branch insns don't have a delay slot.
1821 If a read from HI is immediately followed by a branch
1822 to a write to HI we have a read followed by a write
1823 less than 2 insns away. We assume the target of
1824 a branch might be a write to HI, and insert a nop
1825 between a read and an immediately following branch. */
1826 else if (mips_opts.mips16
1827 && (mips_optimize == 0
1828 || (pinfo & MIPS16_INSN_BRANCH)))
1832 /* If the previous instruction was in a noreorder section, then
1833 we don't want to insert the nop after all. */
1834 /* Itbl support may require additional care here. */
1835 if (prev_insn_unreordered)
1838 /* There are two cases which require two intervening
1839 instructions: 1) setting the condition codes using a move to
1840 coprocessor instruction which requires a general coprocessor
1841 delay and then reading the condition codes 2) reading the HI
1842 or LO register and then writing to it (except on processors
1843 which have interlocks). If we are not already emitting a NOP
1844 instruction, we must check for these cases compared to the
1845 instruction previous to the previous instruction. */
1846 if ((! mips_opts.mips16
1847 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1848 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1849 && (pinfo & INSN_READ_COND_CODE)
1850 && ! cop_interlocks)
1851 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1852 && (pinfo & INSN_WRITE_LO)
1853 && ! (hilo_interlocks
1854 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1855 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1856 && (pinfo & INSN_WRITE_HI)
1857 && ! (hilo_interlocks
1858 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1863 if (prev_prev_insn_unreordered)
1866 if (prev_prev_nop && nops == 0)
1869 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
1871 /* We're out of bits in pinfo, so we must resort to string
1872 ops here. Shortcuts are selected based on opcodes being
1873 limited to the VR4120 instruction set. */
1875 const char *pn = prev_insn.insn_mo->name;
1876 const char *tn = ip->insn_mo->name;
1877 if (strncmp(pn, "macc", 4) == 0
1878 || strncmp(pn, "dmacc", 5) == 0)
1880 /* Errata 21 - [D]DIV[U] after [D]MACC */
1881 if (strstr (tn, "div"))
1886 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1887 if (pn[0] == 'd' /* dmacc */
1888 && (strncmp(tn, "dmult", 5) == 0
1889 || strncmp(tn, "dmacc", 5) == 0))
1894 /* Errata 24 - MT{LO,HI} after [D]MACC */
1895 if (strcmp (tn, "mtlo") == 0
1896 || strcmp (tn, "mthi") == 0)
1902 else if (strncmp(pn, "dmult", 5) == 0
1903 && (strncmp(tn, "dmult", 5) == 0
1904 || strncmp(tn, "dmacc", 5) == 0))
1906 /* Here is the rest of errata 23. */
1909 if (nops < min_nops)
1913 /* If we are being given a nop instruction, don't bother with
1914 one of the nops we would otherwise output. This will only
1915 happen when a nop instruction is used with mips_optimize set
1918 && ! mips_opts.noreorder
1919 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1922 /* Now emit the right number of NOP instructions. */
1923 if (nops > 0 && ! mips_opts.noreorder)
1926 unsigned long old_frag_offset;
1928 struct insn_label_list *l;
1930 old_frag = frag_now;
1931 old_frag_offset = frag_now_fix ();
1933 for (i = 0; i < nops; i++)
1938 listing_prev_line ();
1939 /* We may be at the start of a variant frag. In case we
1940 are, make sure there is enough space for the frag
1941 after the frags created by listing_prev_line. The
1942 argument to frag_grow here must be at least as large
1943 as the argument to all other calls to frag_grow in
1944 this file. We don't have to worry about being in the
1945 middle of a variant frag, because the variants insert
1946 all needed nop instructions themselves. */
1950 for (l = insn_labels; l != NULL; l = l->next)
1954 assert (S_GET_SEGMENT (l->label) == now_seg);
1955 symbol_set_frag (l->label, frag_now);
1956 val = (valueT) frag_now_fix ();
1957 /* mips16 text labels are stored as odd. */
1958 if (mips_opts.mips16)
1960 S_SET_VALUE (l->label, val);
1963 #ifndef NO_ECOFF_DEBUGGING
1964 if (ECOFF_DEBUGGING)
1965 ecoff_fix_loc (old_frag, old_frag_offset);
1968 else if (prev_nop_frag != NULL)
1970 /* We have a frag holding nops we may be able to remove. If
1971 we don't need any nops, we can decrease the size of
1972 prev_nop_frag by the size of one instruction. If we do
1973 need some nops, we count them in prev_nops_required. */
1974 if (prev_nop_frag_since == 0)
1978 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1979 --prev_nop_frag_holds;
1982 prev_nop_frag_required += nops;
1986 if (prev_prev_nop == 0)
1988 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1989 --prev_nop_frag_holds;
1992 ++prev_nop_frag_required;
1995 if (prev_nop_frag_holds <= prev_nop_frag_required)
1996 prev_nop_frag = NULL;
1998 ++prev_nop_frag_since;
2000 /* Sanity check: by the time we reach the second instruction
2001 after prev_nop_frag, we should have used up all the nops
2002 one way or another. */
2003 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2007 /* Record the frag type before frag_var. */
2009 prev_insn_frag_type = prev_insn_frag->fr_type;
2012 && *reloc_type == BFD_RELOC_16_PCREL_S2
2013 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2014 || pinfo & INSN_COND_BRANCH_LIKELY)
2015 && mips_relax_branch
2016 /* Don't try branch relaxation within .set nomacro, or within
2017 .set noat if we use $at for PIC computations. If it turns
2018 out that the branch was out-of-range, we'll get an error. */
2019 && !mips_opts.warn_about_macros
2020 && !(mips_opts.noat && mips_pic != NO_PIC)
2021 && !mips_opts.mips16)
2023 relaxed_branch = TRUE;
2024 f = frag_var (rs_machine_dependent,
2025 relaxed_branch_length
2027 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2028 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2030 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2031 pinfo & INSN_COND_BRANCH_LIKELY,
2032 pinfo & INSN_WRITE_GPR_31,
2034 address_expr->X_add_symbol,
2035 address_expr->X_add_number,
2037 *reloc_type = BFD_RELOC_UNUSED;
2039 else if (*reloc_type > BFD_RELOC_UNUSED)
2041 /* We need to set up a variant frag. */
2042 assert (mips_opts.mips16 && address_expr != NULL);
2043 f = frag_var (rs_machine_dependent, 4, 0,
2044 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2045 mips16_small, mips16_ext,
2047 & INSN_UNCOND_BRANCH_DELAY),
2048 (*prev_insn_reloc_type
2049 == BFD_RELOC_MIPS16_JMP)),
2050 make_expr_symbol (address_expr), 0, NULL);
2052 else if (mips_opts.mips16
2054 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2056 /* Make sure there is enough room to swap this instruction with
2057 a following jump instruction. */
2063 if (mips_opts.mips16
2064 && mips_opts.noreorder
2065 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2066 as_warn (_("extended instruction in delay slot"));
2068 if (mips_relax.sequence)
2070 /* If we've reached the end of this frag, turn it into a variant
2071 frag and record the information for the instructions we've
2073 if (frag_room () < 4)
2074 relax_close_frag ();
2075 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2078 if (mips_relax.sequence != 2)
2079 mips_macro_warning.sizes[0] += 4;
2080 if (mips_relax.sequence != 1)
2081 mips_macro_warning.sizes[1] += 4;
2086 fixp[0] = fixp[1] = fixp[2] = NULL;
2087 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2089 if (address_expr->X_op == O_constant)
2093 switch (*reloc_type)
2096 ip->insn_opcode |= address_expr->X_add_number;
2099 case BFD_RELOC_MIPS_HIGHEST:
2100 tmp = (address_expr->X_add_number
2101 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2103 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2106 case BFD_RELOC_MIPS_HIGHER:
2107 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2108 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2111 case BFD_RELOC_HI16_S:
2112 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2116 case BFD_RELOC_HI16:
2117 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2120 case BFD_RELOC_LO16:
2121 case BFD_RELOC_MIPS_GOT_DISP:
2122 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2125 case BFD_RELOC_MIPS_JMP:
2126 if ((address_expr->X_add_number & 3) != 0)
2127 as_bad (_("jump to misaligned address (0x%lx)"),
2128 (unsigned long) address_expr->X_add_number);
2129 if (address_expr->X_add_number & ~0xfffffff)
2130 as_bad (_("jump address range overflow (0x%lx)"),
2131 (unsigned long) address_expr->X_add_number);
2132 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2135 case BFD_RELOC_MIPS16_JMP:
2136 if ((address_expr->X_add_number & 3) != 0)
2137 as_bad (_("jump to misaligned address (0x%lx)"),
2138 (unsigned long) address_expr->X_add_number);
2139 if (address_expr->X_add_number & ~0xfffffff)
2140 as_bad (_("jump address range overflow (0x%lx)"),
2141 (unsigned long) address_expr->X_add_number);
2143 (((address_expr->X_add_number & 0x7c0000) << 3)
2144 | ((address_expr->X_add_number & 0xf800000) >> 7)
2145 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2148 case BFD_RELOC_16_PCREL_S2:
2158 reloc_howto_type *howto;
2161 /* In a compound relocation, it is the final (outermost)
2162 operator that determines the relocated field. */
2163 for (i = 1; i < 3; i++)
2164 if (reloc_type[i] == BFD_RELOC_UNUSED)
2167 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2168 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2169 bfd_get_reloc_size(howto),
2171 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2174 /* These relocations can have an addend that won't fit in
2175 4 octets for 64bit assembly. */
2177 && ! howto->partial_inplace
2178 && (reloc_type[0] == BFD_RELOC_16
2179 || reloc_type[0] == BFD_RELOC_32
2180 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2181 || reloc_type[0] == BFD_RELOC_HI16_S
2182 || reloc_type[0] == BFD_RELOC_LO16
2183 || reloc_type[0] == BFD_RELOC_GPREL16
2184 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2185 || reloc_type[0] == BFD_RELOC_GPREL32
2186 || reloc_type[0] == BFD_RELOC_64
2187 || reloc_type[0] == BFD_RELOC_CTOR
2188 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2189 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2190 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2191 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2192 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2193 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2194 fixp[0]->fx_no_overflow = 1;
2196 if (mips_relax.sequence)
2198 if (mips_relax.first_fixup == 0)
2199 mips_relax.first_fixup = fixp[0];
2201 else if (reloc_needs_lo_p (*reloc_type))
2203 struct mips_hi_fixup *hi_fixup;
2205 /* Reuse the last entry if it already has a matching %lo. */
2206 hi_fixup = mips_hi_fixup_list;
2208 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2210 hi_fixup = ((struct mips_hi_fixup *)
2211 xmalloc (sizeof (struct mips_hi_fixup)));
2212 hi_fixup->next = mips_hi_fixup_list;
2213 mips_hi_fixup_list = hi_fixup;
2215 hi_fixup->fixp = fixp[0];
2216 hi_fixup->seg = now_seg;
2219 /* Add fixups for the second and third relocations, if given.
2220 Note that the ABI allows the second relocation to be
2221 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2222 moment we only use RSS_UNDEF, but we could add support
2223 for the others if it ever becomes necessary. */
2224 for (i = 1; i < 3; i++)
2225 if (reloc_type[i] != BFD_RELOC_UNUSED)
2227 address_expr->X_op = O_absent;
2228 address_expr->X_add_symbol = 0;
2229 address_expr->X_add_number = 0;
2231 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2232 fixp[0]->fx_size, address_expr,
2233 FALSE, reloc_type[i]);
2238 if (! mips_opts.mips16)
2240 md_number_to_chars (f, ip->insn_opcode, 4);
2242 dwarf2_emit_insn (4);
2245 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2247 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2248 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2250 dwarf2_emit_insn (4);
2257 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2260 md_number_to_chars (f, ip->insn_opcode, 2);
2262 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2266 /* Update the register mask information. */
2267 if (! mips_opts.mips16)
2269 if (pinfo & INSN_WRITE_GPR_D)
2270 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2271 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2272 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2273 if (pinfo & INSN_READ_GPR_S)
2274 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2275 if (pinfo & INSN_WRITE_GPR_31)
2276 mips_gprmask |= 1 << RA;
2277 if (pinfo & INSN_WRITE_FPR_D)
2278 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2279 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2280 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2281 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2282 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2283 if ((pinfo & INSN_READ_FPR_R) != 0)
2284 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2285 if (pinfo & INSN_COP)
2287 /* We don't keep enough information to sort these cases out.
2288 The itbl support does keep this information however, although
2289 we currently don't support itbl fprmats as part of the cop
2290 instruction. May want to add this support in the future. */
2292 /* Never set the bit for $0, which is always zero. */
2293 mips_gprmask &= ~1 << 0;
2297 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2298 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2299 & MIPS16OP_MASK_RX);
2300 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2301 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2302 & MIPS16OP_MASK_RY);
2303 if (pinfo & MIPS16_INSN_WRITE_Z)
2304 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2305 & MIPS16OP_MASK_RZ);
2306 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2307 mips_gprmask |= 1 << TREG;
2308 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2309 mips_gprmask |= 1 << SP;
2310 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2311 mips_gprmask |= 1 << RA;
2312 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2313 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2314 if (pinfo & MIPS16_INSN_READ_Z)
2315 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2316 & MIPS16OP_MASK_MOVE32Z);
2317 if (pinfo & MIPS16_INSN_READ_GPR_X)
2318 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2319 & MIPS16OP_MASK_REGR32);
2322 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2324 /* Filling the branch delay slot is more complex. We try to
2325 switch the branch with the previous instruction, which we can
2326 do if the previous instruction does not set up a condition
2327 that the branch tests and if the branch is not itself the
2328 target of any branch. */
2329 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2330 || (pinfo & INSN_COND_BRANCH_DELAY))
2332 if (mips_optimize < 2
2333 /* If we have seen .set volatile or .set nomove, don't
2335 || mips_opts.nomove != 0
2336 /* If we had to emit any NOP instructions, then we
2337 already know we can not swap. */
2339 /* If we don't even know the previous insn, we can not
2341 || ! prev_insn_valid
2342 /* If the previous insn is already in a branch delay
2343 slot, then we can not swap. */
2344 || prev_insn_is_delay_slot
2345 /* If the previous previous insn was in a .set
2346 noreorder, we can't swap. Actually, the MIPS
2347 assembler will swap in this situation. However, gcc
2348 configured -with-gnu-as will generate code like
2354 in which we can not swap the bne and INSN. If gcc is
2355 not configured -with-gnu-as, it does not output the
2356 .set pseudo-ops. We don't have to check
2357 prev_insn_unreordered, because prev_insn_valid will
2358 be 0 in that case. We don't want to use
2359 prev_prev_insn_valid, because we do want to be able
2360 to swap at the start of a function. */
2361 || prev_prev_insn_unreordered
2362 /* If the branch is itself the target of a branch, we
2363 can not swap. We cheat on this; all we check for is
2364 whether there is a label on this instruction. If
2365 there are any branches to anything other than a
2366 label, users must use .set noreorder. */
2367 || insn_labels != NULL
2368 /* If the previous instruction is in a variant frag
2369 other than this branch's one, we cannot do the swap.
2370 This does not apply to the mips16, which uses variant
2371 frags for different purposes. */
2372 || (! mips_opts.mips16
2373 && prev_insn_frag_type == rs_machine_dependent)
2374 /* If the branch reads the condition codes, we don't
2375 even try to swap, because in the sequence
2380 we can not swap, and I don't feel like handling that
2382 || (! mips_opts.mips16
2383 && (pinfo & INSN_READ_COND_CODE)
2384 && ! cop_interlocks)
2385 /* We can not swap with an instruction that requires a
2386 delay slot, because the target of the branch might
2387 interfere with that instruction. */
2388 || (! mips_opts.mips16
2390 /* Itbl support may require additional care here. */
2391 & (INSN_LOAD_COPROC_DELAY
2392 | INSN_COPROC_MOVE_DELAY
2393 | INSN_WRITE_COND_CODE))
2394 && ! cop_interlocks)
2395 || (! (hilo_interlocks
2396 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2400 || (! mips_opts.mips16
2401 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2402 && ! gpr_interlocks)
2403 || (! mips_opts.mips16
2404 /* Itbl support may require additional care here. */
2405 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2406 && ! cop_mem_interlocks)
2407 /* We can not swap with a branch instruction. */
2409 & (INSN_UNCOND_BRANCH_DELAY
2410 | INSN_COND_BRANCH_DELAY
2411 | INSN_COND_BRANCH_LIKELY))
2412 /* We do not swap with a trap instruction, since it
2413 complicates trap handlers to have the trap
2414 instruction be in a delay slot. */
2415 || (prev_pinfo & INSN_TRAP)
2416 /* If the branch reads a register that the previous
2417 instruction sets, we can not swap. */
2418 || (! mips_opts.mips16
2419 && (prev_pinfo & INSN_WRITE_GPR_T)
2420 && insn_uses_reg (ip,
2421 ((prev_insn.insn_opcode >> OP_SH_RT)
2424 || (! mips_opts.mips16
2425 && (prev_pinfo & INSN_WRITE_GPR_D)
2426 && insn_uses_reg (ip,
2427 ((prev_insn.insn_opcode >> OP_SH_RD)
2430 || (mips_opts.mips16
2431 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2432 && insn_uses_reg (ip,
2433 ((prev_insn.insn_opcode
2435 & MIPS16OP_MASK_RX),
2437 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2438 && insn_uses_reg (ip,
2439 ((prev_insn.insn_opcode
2441 & MIPS16OP_MASK_RY),
2443 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2444 && insn_uses_reg (ip,
2445 ((prev_insn.insn_opcode
2447 & MIPS16OP_MASK_RZ),
2449 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2450 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2451 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2452 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2453 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2454 && insn_uses_reg (ip,
2455 MIPS16OP_EXTRACT_REG32R (prev_insn.
2458 /* If the branch writes a register that the previous
2459 instruction sets, we can not swap (we know that
2460 branches write only to RD or to $31). */
2461 || (! mips_opts.mips16
2462 && (prev_pinfo & INSN_WRITE_GPR_T)
2463 && (((pinfo & INSN_WRITE_GPR_D)
2464 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2465 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2466 || ((pinfo & INSN_WRITE_GPR_31)
2467 && (((prev_insn.insn_opcode >> OP_SH_RT)
2470 || (! mips_opts.mips16
2471 && (prev_pinfo & INSN_WRITE_GPR_D)
2472 && (((pinfo & INSN_WRITE_GPR_D)
2473 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2474 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2475 || ((pinfo & INSN_WRITE_GPR_31)
2476 && (((prev_insn.insn_opcode >> OP_SH_RD)
2479 || (mips_opts.mips16
2480 && (pinfo & MIPS16_INSN_WRITE_31)
2481 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2482 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2483 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2485 /* If the branch writes a register that the previous
2486 instruction reads, we can not swap (we know that
2487 branches only write to RD or to $31). */
2488 || (! mips_opts.mips16
2489 && (pinfo & INSN_WRITE_GPR_D)
2490 && insn_uses_reg (&prev_insn,
2491 ((ip->insn_opcode >> OP_SH_RD)
2494 || (! mips_opts.mips16
2495 && (pinfo & INSN_WRITE_GPR_31)
2496 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2497 || (mips_opts.mips16
2498 && (pinfo & MIPS16_INSN_WRITE_31)
2499 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2500 /* If we are generating embedded PIC code, the branch
2501 might be expanded into a sequence which uses $at, so
2502 we can't swap with an instruction which reads it. */
2503 || (mips_pic == EMBEDDED_PIC
2504 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2505 /* If the previous previous instruction has a load
2506 delay, and sets a register that the branch reads, we
2508 || (! mips_opts.mips16
2509 /* Itbl support may require additional care here. */
2510 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2511 && ! cop_interlocks)
2512 || ((prev_prev_insn.insn_mo->pinfo
2513 & INSN_LOAD_MEMORY_DELAY)
2514 && ! gpr_interlocks))
2515 && insn_uses_reg (ip,
2516 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2519 /* If one instruction sets a condition code and the
2520 other one uses a condition code, we can not swap. */
2521 || ((pinfo & INSN_READ_COND_CODE)
2522 && (prev_pinfo & INSN_WRITE_COND_CODE))
2523 || ((pinfo & INSN_WRITE_COND_CODE)
2524 && (prev_pinfo & INSN_READ_COND_CODE))
2525 /* If the previous instruction uses the PC, we can not
2527 || (mips_opts.mips16
2528 && (prev_pinfo & MIPS16_INSN_READ_PC))
2529 /* If the previous instruction was extended, we can not
2531 || (mips_opts.mips16 && prev_insn_extended)
2532 /* If the previous instruction had a fixup in mips16
2533 mode, we can not swap. This normally means that the
2534 previous instruction was a 4 byte branch anyhow. */
2535 || (mips_opts.mips16 && prev_insn_fixp[0])
2536 /* If the previous instruction is a sync, sync.l, or
2537 sync.p, we can not swap. */
2538 || (prev_pinfo & INSN_SYNC))
2540 /* We could do even better for unconditional branches to
2541 portions of this object file; we could pick up the
2542 instruction at the destination, put it in the delay
2543 slot, and bump the destination address. */
2545 /* Update the previous insn information. */
2546 prev_prev_insn = *ip;
2547 prev_insn.insn_mo = &dummy_opcode;
2551 /* It looks like we can actually do the swap. */
2552 if (! mips_opts.mips16)
2557 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2558 if (!relaxed_branch)
2560 /* If this is not a relaxed branch, then just
2561 swap the instructions. */
2562 memcpy (temp, prev_f, 4);
2563 memcpy (prev_f, f, 4);
2564 memcpy (f, temp, 4);
2568 /* If this is a relaxed branch, then we move the
2569 instruction to be placed in the delay slot to
2570 the current frag, shrinking the fixed part of
2571 the originating frag. If the branch occupies
2572 the tail of the latter, we move it backwards,
2573 into the space freed by the moved instruction. */
2575 memcpy (f, prev_f, 4);
2576 prev_insn_frag->fr_fix -= 4;
2577 if (prev_insn_frag->fr_type == rs_machine_dependent)
2578 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2581 if (prev_insn_fixp[0])
2583 prev_insn_fixp[0]->fx_frag = frag_now;
2584 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2586 if (prev_insn_fixp[1])
2588 prev_insn_fixp[1]->fx_frag = frag_now;
2589 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2591 if (prev_insn_fixp[2])
2593 prev_insn_fixp[2]->fx_frag = frag_now;
2594 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2596 if (prev_insn_fixp[0] && HAVE_NEWABI
2597 && prev_insn_frag != frag_now
2598 && (prev_insn_fixp[0]->fx_r_type
2599 == BFD_RELOC_MIPS_GOT_DISP
2600 || (prev_insn_fixp[0]->fx_r_type
2601 == BFD_RELOC_MIPS_CALL16)))
2603 /* To avoid confusion in tc_gen_reloc, we must
2604 ensure that this does not become a variant
2606 force_new_frag = TRUE;
2609 if (!relaxed_branch)
2613 fixp[0]->fx_frag = prev_insn_frag;
2614 fixp[0]->fx_where = prev_insn_where;
2618 fixp[1]->fx_frag = prev_insn_frag;
2619 fixp[1]->fx_where = prev_insn_where;
2623 fixp[2]->fx_frag = prev_insn_frag;
2624 fixp[2]->fx_where = prev_insn_where;
2627 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2630 fixp[0]->fx_where -= 4;
2632 fixp[1]->fx_where -= 4;
2634 fixp[2]->fx_where -= 4;
2642 assert (prev_insn_fixp[0] == NULL);
2643 assert (prev_insn_fixp[1] == NULL);
2644 assert (prev_insn_fixp[2] == NULL);
2645 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2646 memcpy (temp, prev_f, 2);
2647 memcpy (prev_f, f, 2);
2648 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2650 assert (*reloc_type == BFD_RELOC_UNUSED);
2651 memcpy (f, temp, 2);
2655 memcpy (f, f + 2, 2);
2656 memcpy (f + 2, temp, 2);
2660 fixp[0]->fx_frag = prev_insn_frag;
2661 fixp[0]->fx_where = prev_insn_where;
2665 fixp[1]->fx_frag = prev_insn_frag;
2666 fixp[1]->fx_where = prev_insn_where;
2670 fixp[2]->fx_frag = prev_insn_frag;
2671 fixp[2]->fx_where = prev_insn_where;
2675 /* Update the previous insn information; leave prev_insn
2677 prev_prev_insn = *ip;
2679 prev_insn_is_delay_slot = 1;
2681 /* If that was an unconditional branch, forget the previous
2682 insn information. */
2683 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2685 prev_prev_insn.insn_mo = &dummy_opcode;
2686 prev_insn.insn_mo = &dummy_opcode;
2689 prev_insn_fixp[0] = NULL;
2690 prev_insn_fixp[1] = NULL;
2691 prev_insn_fixp[2] = NULL;
2692 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2693 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2694 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2695 prev_insn_extended = 0;
2697 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2699 /* We don't yet optimize a branch likely. What we should do
2700 is look at the target, copy the instruction found there
2701 into the delay slot, and increment the branch to jump to
2702 the next instruction. */
2704 /* Update the previous insn information. */
2705 prev_prev_insn = *ip;
2706 prev_insn.insn_mo = &dummy_opcode;
2707 prev_insn_fixp[0] = NULL;
2708 prev_insn_fixp[1] = NULL;
2709 prev_insn_fixp[2] = NULL;
2710 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2711 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2712 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2713 prev_insn_extended = 0;
2717 /* Update the previous insn information. */
2719 prev_prev_insn.insn_mo = &dummy_opcode;
2721 prev_prev_insn = prev_insn;
2724 /* Any time we see a branch, we always fill the delay slot
2725 immediately; since this insn is not a branch, we know it
2726 is not in a delay slot. */
2727 prev_insn_is_delay_slot = 0;
2729 prev_insn_fixp[0] = fixp[0];
2730 prev_insn_fixp[1] = fixp[1];
2731 prev_insn_fixp[2] = fixp[2];
2732 prev_insn_reloc_type[0] = reloc_type[0];
2733 prev_insn_reloc_type[1] = reloc_type[1];
2734 prev_insn_reloc_type[2] = reloc_type[2];
2735 if (mips_opts.mips16)
2736 prev_insn_extended = (ip->use_extend
2737 || *reloc_type > BFD_RELOC_UNUSED);
2740 prev_prev_insn_unreordered = prev_insn_unreordered;
2741 prev_insn_unreordered = 0;
2742 prev_insn_frag = frag_now;
2743 prev_insn_where = f - frag_now->fr_literal;
2744 prev_insn_valid = 1;
2746 else if (mips_relax.sequence != 2)
2748 /* We need to record a bit of information even when we are not
2749 reordering, in order to determine the base address for mips16
2750 PC relative relocs. */
2751 prev_prev_insn = prev_insn;
2753 prev_insn_reloc_type[0] = reloc_type[0];
2754 prev_insn_reloc_type[1] = reloc_type[1];
2755 prev_insn_reloc_type[2] = reloc_type[2];
2756 prev_prev_insn_unreordered = prev_insn_unreordered;
2757 prev_insn_unreordered = 1;
2760 /* We just output an insn, so the next one doesn't have a label. */
2761 mips_clear_insn_labels ();
2764 /* This function forgets that there was any previous instruction or
2765 label. If PRESERVE is non-zero, it remembers enough information to
2766 know whether nops are needed before a noreorder section. */
2769 mips_no_prev_insn (int preserve)
2773 prev_insn.insn_mo = &dummy_opcode;
2774 prev_prev_insn.insn_mo = &dummy_opcode;
2775 prev_nop_frag = NULL;
2776 prev_nop_frag_holds = 0;
2777 prev_nop_frag_required = 0;
2778 prev_nop_frag_since = 0;
2780 prev_insn_valid = 0;
2781 prev_insn_is_delay_slot = 0;
2782 prev_insn_unreordered = 0;
2783 prev_insn_extended = 0;
2784 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2785 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2786 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2787 prev_prev_insn_unreordered = 0;
2788 mips_clear_insn_labels ();
2791 /* This function must be called whenever we turn on noreorder or emit
2792 something other than instructions. It inserts any NOPS which might
2793 be needed by the previous instruction, and clears the information
2794 kept for the previous instructions. The INSNS parameter is true if
2795 instructions are to follow. */
2798 mips_emit_delays (bfd_boolean insns)
2800 if (! mips_opts.noreorder)
2805 if ((! mips_opts.mips16
2806 && ((prev_insn.insn_mo->pinfo
2807 & (INSN_LOAD_COPROC_DELAY
2808 | INSN_COPROC_MOVE_DELAY
2809 | INSN_WRITE_COND_CODE))
2810 && ! cop_interlocks))
2811 || (! hilo_interlocks
2812 && (prev_insn.insn_mo->pinfo
2815 || (! mips_opts.mips16
2816 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2817 && ! gpr_interlocks)
2818 || (! mips_opts.mips16
2819 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2820 && ! cop_mem_interlocks))
2822 /* Itbl support may require additional care here. */
2824 if ((! mips_opts.mips16
2825 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2826 && ! cop_interlocks))
2827 || (! hilo_interlocks
2828 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2829 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2832 if (prev_insn_unreordered)
2835 else if ((! mips_opts.mips16
2836 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2837 && ! cop_interlocks))
2838 || (! hilo_interlocks
2839 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2840 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2842 /* Itbl support may require additional care here. */
2843 if (! prev_prev_insn_unreordered)
2847 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
2850 const char *pn = prev_insn.insn_mo->name;
2851 if (strncmp(pn, "macc", 4) == 0
2852 || strncmp(pn, "dmacc", 5) == 0
2853 || strncmp(pn, "dmult", 5) == 0)
2857 if (nops < min_nops)
2863 struct insn_label_list *l;
2867 /* Record the frag which holds the nop instructions, so
2868 that we can remove them if we don't need them. */
2869 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2870 prev_nop_frag = frag_now;
2871 prev_nop_frag_holds = nops;
2872 prev_nop_frag_required = 0;
2873 prev_nop_frag_since = 0;
2876 for (; nops > 0; --nops)
2881 /* Move on to a new frag, so that it is safe to simply
2882 decrease the size of prev_nop_frag. */
2883 frag_wane (frag_now);
2887 for (l = insn_labels; l != NULL; l = l->next)
2891 assert (S_GET_SEGMENT (l->label) == now_seg);
2892 symbol_set_frag (l->label, frag_now);
2893 val = (valueT) frag_now_fix ();
2894 /* mips16 text labels are stored as odd. */
2895 if (mips_opts.mips16)
2897 S_SET_VALUE (l->label, val);
2902 /* Mark instruction labels in mips16 mode. */
2904 mips16_mark_labels ();
2906 mips_no_prev_insn (insns);
2909 /* Set up global variables for the start of a new macro. */
2914 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2915 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2916 && (prev_insn.insn_mo->pinfo
2917 & (INSN_UNCOND_BRANCH_DELAY
2918 | INSN_COND_BRANCH_DELAY
2919 | INSN_COND_BRANCH_LIKELY)) != 0);
2922 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2923 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2924 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2927 macro_warning (relax_substateT subtype)
2929 if (subtype & RELAX_DELAY_SLOT)
2930 return _("Macro instruction expanded into multiple instructions"
2931 " in a branch delay slot");
2932 else if (subtype & RELAX_NOMACRO)
2933 return _("Macro instruction expanded into multiple instructions");
2938 /* Finish up a macro. Emit warnings as appropriate. */
2943 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
2945 relax_substateT subtype;
2947 /* Set up the relaxation warning flags. */
2949 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
2950 subtype |= RELAX_SECOND_LONGER;
2951 if (mips_opts.warn_about_macros)
2952 subtype |= RELAX_NOMACRO;
2953 if (mips_macro_warning.delay_slot_p)
2954 subtype |= RELAX_DELAY_SLOT;
2956 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
2958 /* Either the macro has a single implementation or both
2959 implementations are longer than 4 bytes. Emit the
2961 const char *msg = macro_warning (subtype);
2967 /* One implementation might need a warning but the other
2968 definitely doesn't. */
2969 mips_macro_warning.first_frag->fr_subtype |= subtype;
2974 /* Build an instruction created by a macro expansion. This is passed
2975 a pointer to the count of instructions created so far, an
2976 expression, the name of the instruction to build, an operand format
2977 string, and corresponding arguments. */
2980 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
2982 struct mips_cl_insn insn;
2983 bfd_reloc_code_real_type r[3];
2986 va_start (args, fmt);
2988 if (mips_opts.mips16)
2990 mips16_macro_build (ep, name, fmt, args);
2995 r[0] = BFD_RELOC_UNUSED;
2996 r[1] = BFD_RELOC_UNUSED;
2997 r[2] = BFD_RELOC_UNUSED;
2998 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2999 assert (insn.insn_mo);
3000 assert (strcmp (name, insn.insn_mo->name) == 0);
3002 /* Search until we get a match for NAME. */
3005 /* It is assumed here that macros will never generate
3006 MDMX or MIPS-3D instructions. */
3007 if (strcmp (fmt, insn.insn_mo->args) == 0
3008 && insn.insn_mo->pinfo != INSN_MACRO
3009 && OPCODE_IS_MEMBER (insn.insn_mo,
3011 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3013 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3017 assert (insn.insn_mo->name);
3018 assert (strcmp (name, insn.insn_mo->name) == 0);
3021 insn.insn_opcode = insn.insn_mo->match;
3039 insn.insn_opcode |= (va_arg (args, int)
3040 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3045 /* Note that in the macro case, these arguments are already
3046 in MSB form. (When handling the instruction in the
3047 non-macro case, these arguments are sizes from which
3048 MSB values must be calculated.) */
3049 insn.insn_opcode |= (va_arg (args, int)
3050 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3056 /* Note that in the macro case, these arguments are already
3057 in MSBD form. (When handling the instruction in the
3058 non-macro case, these arguments are sizes from which
3059 MSBD values must be calculated.) */
3060 insn.insn_opcode |= (va_arg (args, int)
3061 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3072 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3076 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3081 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3087 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3092 int tmp = va_arg (args, int);
3094 insn.insn_opcode |= tmp << OP_SH_RT;
3095 insn.insn_opcode |= tmp << OP_SH_RD;
3101 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3108 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3112 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3116 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3120 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3124 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3131 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3137 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3138 assert (*r == BFD_RELOC_GPREL16
3139 || *r == BFD_RELOC_MIPS_LITERAL
3140 || *r == BFD_RELOC_MIPS_HIGHER
3141 || *r == BFD_RELOC_HI16_S
3142 || *r == BFD_RELOC_LO16
3143 || *r == BFD_RELOC_MIPS_GOT16
3144 || *r == BFD_RELOC_MIPS_CALL16
3145 || *r == BFD_RELOC_MIPS_GOT_DISP
3146 || *r == BFD_RELOC_MIPS_GOT_PAGE
3147 || *r == BFD_RELOC_MIPS_GOT_OFST
3148 || *r == BFD_RELOC_MIPS_GOT_LO16
3149 || *r == BFD_RELOC_MIPS_CALL_LO16
3150 || (ep->X_op == O_subtract
3151 && *r == BFD_RELOC_PCREL_LO16));
3155 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3157 && (ep->X_op == O_constant
3158 || (ep->X_op == O_symbol
3159 && (*r == BFD_RELOC_MIPS_HIGHEST
3160 || *r == BFD_RELOC_HI16_S
3161 || *r == BFD_RELOC_HI16
3162 || *r == BFD_RELOC_GPREL16
3163 || *r == BFD_RELOC_MIPS_GOT_HI16
3164 || *r == BFD_RELOC_MIPS_CALL_HI16))
3165 || (ep->X_op == O_subtract
3166 && *r == BFD_RELOC_PCREL_HI16_S)));
3170 assert (ep != NULL);
3172 * This allows macro() to pass an immediate expression for
3173 * creating short branches without creating a symbol.
3174 * Note that the expression still might come from the assembly
3175 * input, in which case the value is not checked for range nor
3176 * is a relocation entry generated (yuck).
3178 if (ep->X_op == O_constant)
3180 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3184 *r = BFD_RELOC_16_PCREL_S2;
3188 assert (ep != NULL);
3189 *r = BFD_RELOC_MIPS_JMP;
3193 insn.insn_opcode |= va_arg (args, unsigned long);
3202 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3204 append_insn (&insn, ep, r);
3208 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3211 struct mips_cl_insn insn;
3212 bfd_reloc_code_real_type r[3]
3213 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3215 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3216 assert (insn.insn_mo);
3217 assert (strcmp (name, insn.insn_mo->name) == 0);
3219 while (strcmp (fmt, insn.insn_mo->args) != 0
3220 || insn.insn_mo->pinfo == INSN_MACRO)
3223 assert (insn.insn_mo->name);
3224 assert (strcmp (name, insn.insn_mo->name) == 0);
3227 insn.insn_opcode = insn.insn_mo->match;
3228 insn.use_extend = FALSE;
3247 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3252 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3256 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3260 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3270 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3277 regno = va_arg (args, int);
3278 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3279 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3300 assert (ep != NULL);
3302 if (ep->X_op != O_constant)
3303 *r = (int) BFD_RELOC_UNUSED + c;
3306 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
3307 FALSE, &insn.insn_opcode, &insn.use_extend,
3310 *r = BFD_RELOC_UNUSED;
3316 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3323 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3325 append_insn (&insn, ep, r);
3329 * Generate a "jalr" instruction with a relocation hint to the called
3330 * function. This occurs in NewABI PIC code.
3333 macro_build_jalr (expressionS *ep)
3342 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
3344 fix_new_exp (frag_now, f - frag_now->fr_literal,
3345 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
3349 * Generate a "lui" instruction.
3352 macro_build_lui (expressionS *ep, int regnum)
3354 expressionS high_expr;
3355 struct mips_cl_insn insn;
3356 bfd_reloc_code_real_type r[3]
3357 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3358 const char *name = "lui";
3359 const char *fmt = "t,u";
3361 assert (! mips_opts.mips16);
3365 if (high_expr.X_op == O_constant)
3367 /* we can compute the instruction now without a relocation entry */
3368 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3370 *r = BFD_RELOC_UNUSED;
3374 assert (ep->X_op == O_symbol);
3375 /* _gp_disp is a special case, used from s_cpload. */
3376 assert (mips_pic == NO_PIC
3378 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3379 *r = BFD_RELOC_HI16_S;
3382 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3383 assert (insn.insn_mo);
3384 assert (strcmp (name, insn.insn_mo->name) == 0);
3385 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3387 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3388 if (*r == BFD_RELOC_UNUSED)
3390 insn.insn_opcode |= high_expr.X_add_number;
3391 append_insn (&insn, NULL, r);
3394 append_insn (&insn, &high_expr, r);
3397 /* Generate a sequence of instructions to do a load or store from a constant
3398 offset off of a base register (breg) into/from a target register (treg),
3399 using AT if necessary. */
3401 macro_build_ldst_constoffset (expressionS *ep, const char *op,
3402 int treg, int breg, int dbl)
3404 assert (ep->X_op == O_constant);
3406 /* Sign-extending 32-bit constants makes their handling easier. */
3407 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3408 == ~((bfd_vma) 0x7fffffff)))
3410 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3411 as_bad (_("constant too large"));
3413 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3417 /* Right now, this routine can only handle signed 32-bit constants. */
3418 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3419 as_warn (_("operand overflow"));
3421 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3423 /* Signed 16-bit offset will fit in the op. Easy! */
3424 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
3428 /* 32-bit offset, need multiple instructions and AT, like:
3429 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3430 addu $tempreg,$tempreg,$breg
3431 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3432 to handle the complete offset. */
3433 macro_build_lui (ep, AT);
3434 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3435 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3438 as_warn (_("Macro used $at after \".set noat\""));
3443 * Generates code to set the $at register to true (one)
3444 * if reg is less than the immediate expression.
3447 set_at (int reg, int unsignedp)
3449 if (imm_expr.X_op == O_constant
3450 && imm_expr.X_add_number >= -0x8000
3451 && imm_expr.X_add_number < 0x8000)
3452 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
3453 AT, reg, BFD_RELOC_LO16);
3456 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3457 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3462 normalize_constant_expr (expressionS *ex)
3464 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3465 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3469 /* Warn if an expression is not a constant. */
3472 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3474 if (ex->X_op == O_big)
3475 as_bad (_("unsupported large constant"));
3476 else if (ex->X_op != O_constant)
3477 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3479 normalize_constant_expr (ex);
3482 /* Count the leading zeroes by performing a binary chop. This is a
3483 bulky bit of source, but performance is a LOT better for the
3484 majority of values than a simple loop to count the bits:
3485 for (lcnt = 0; (lcnt < 32); lcnt++)
3486 if ((v) & (1 << (31 - lcnt)))
3488 However it is not code size friendly, and the gain will drop a bit
3489 on certain cached systems.
3491 #define COUNT_TOP_ZEROES(v) \
3492 (((v) & ~0xffff) == 0 \
3493 ? ((v) & ~0xff) == 0 \
3494 ? ((v) & ~0xf) == 0 \
3495 ? ((v) & ~0x3) == 0 \
3496 ? ((v) & ~0x1) == 0 \
3501 : ((v) & ~0x7) == 0 \
3504 : ((v) & ~0x3f) == 0 \
3505 ? ((v) & ~0x1f) == 0 \
3508 : ((v) & ~0x7f) == 0 \
3511 : ((v) & ~0xfff) == 0 \
3512 ? ((v) & ~0x3ff) == 0 \
3513 ? ((v) & ~0x1ff) == 0 \
3516 : ((v) & ~0x7ff) == 0 \
3519 : ((v) & ~0x3fff) == 0 \
3520 ? ((v) & ~0x1fff) == 0 \
3523 : ((v) & ~0x7fff) == 0 \
3526 : ((v) & ~0xffffff) == 0 \
3527 ? ((v) & ~0xfffff) == 0 \
3528 ? ((v) & ~0x3ffff) == 0 \
3529 ? ((v) & ~0x1ffff) == 0 \
3532 : ((v) & ~0x7ffff) == 0 \
3535 : ((v) & ~0x3fffff) == 0 \
3536 ? ((v) & ~0x1fffff) == 0 \
3539 : ((v) & ~0x7fffff) == 0 \
3542 : ((v) & ~0xfffffff) == 0 \
3543 ? ((v) & ~0x3ffffff) == 0 \
3544 ? ((v) & ~0x1ffffff) == 0 \
3547 : ((v) & ~0x7ffffff) == 0 \
3550 : ((v) & ~0x3fffffff) == 0 \
3551 ? ((v) & ~0x1fffffff) == 0 \
3554 : ((v) & ~0x7fffffff) == 0 \
3559 * This routine generates the least number of instructions necessary to load
3560 * an absolute expression value into a register.
3563 load_register (int reg, expressionS *ep, int dbl)
3566 expressionS hi32, lo32;
3568 if (ep->X_op != O_big)
3570 assert (ep->X_op == O_constant);
3572 /* Sign-extending 32-bit constants makes their handling easier. */
3573 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3574 == ~((bfd_vma) 0x7fffffff)))
3576 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3577 as_bad (_("constant too large"));
3579 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3583 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3585 /* We can handle 16 bit signed values with an addiu to
3586 $zero. No need to ever use daddiu here, since $zero and
3587 the result are always correct in 32 bit mode. */
3588 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3591 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3593 /* We can handle 16 bit unsigned values with an ori to
3595 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3598 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
3600 /* 32 bit values require an lui. */
3601 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
3602 if ((ep->X_add_number & 0xffff) != 0)
3603 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3608 /* The value is larger than 32 bits. */
3610 if (HAVE_32BIT_GPRS)
3612 as_bad (_("Number (0x%lx) larger than 32 bits"),
3613 (unsigned long) ep->X_add_number);
3614 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3618 if (ep->X_op != O_big)
3621 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3622 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3623 hi32.X_add_number &= 0xffffffff;
3625 lo32.X_add_number &= 0xffffffff;
3629 assert (ep->X_add_number > 2);
3630 if (ep->X_add_number == 3)
3631 generic_bignum[3] = 0;
3632 else if (ep->X_add_number > 4)
3633 as_bad (_("Number larger than 64 bits"));
3634 lo32.X_op = O_constant;
3635 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3636 hi32.X_op = O_constant;
3637 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3640 if (hi32.X_add_number == 0)
3645 unsigned long hi, lo;
3647 if (hi32.X_add_number == (offsetT) 0xffffffff)
3649 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3651 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3654 if (lo32.X_add_number & 0x80000000)
3656 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3657 if (lo32.X_add_number & 0xffff)
3658 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3663 /* Check for 16bit shifted constant. We know that hi32 is
3664 non-zero, so start the mask on the first bit of the hi32
3669 unsigned long himask, lomask;
3673 himask = 0xffff >> (32 - shift);
3674 lomask = (0xffff << shift) & 0xffffffff;
3678 himask = 0xffff << (shift - 32);
3681 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3682 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3686 tmp.X_op = O_constant;
3688 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3689 | (lo32.X_add_number >> shift));
3691 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3692 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
3693 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
3694 reg, reg, (shift >= 32) ? shift - 32 : shift);
3699 while (shift <= (64 - 16));
3701 /* Find the bit number of the lowest one bit, and store the
3702 shifted value in hi/lo. */
3703 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3704 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3708 while ((lo & 1) == 0)
3713 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3719 while ((hi & 1) == 0)
3728 /* Optimize if the shifted value is a (power of 2) - 1. */
3729 if ((hi == 0 && ((lo + 1) & lo) == 0)
3730 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3732 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3737 /* This instruction will set the register to be all
3739 tmp.X_op = O_constant;
3740 tmp.X_add_number = (offsetT) -1;
3741 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3745 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
3746 reg, reg, (bit >= 32) ? bit - 32 : bit);
3748 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
3749 reg, reg, (shift >= 32) ? shift - 32 : shift);
3754 /* Sign extend hi32 before calling load_register, because we can
3755 generally get better code when we load a sign extended value. */
3756 if ((hi32.X_add_number & 0x80000000) != 0)
3757 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3758 load_register (reg, &hi32, 0);
3761 if ((lo32.X_add_number & 0xffff0000) == 0)
3765 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
3773 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
3775 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
3776 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
3782 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
3786 mid16.X_add_number >>= 16;
3787 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3788 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3791 if ((lo32.X_add_number & 0xffff) != 0)
3792 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3795 /* Load an address into a register. */
3798 load_address (int reg, expressionS *ep, int *used_at)
3800 if (ep->X_op != O_constant
3801 && ep->X_op != O_symbol)
3803 as_bad (_("expression too complex"));
3804 ep->X_op = O_constant;
3807 if (ep->X_op == O_constant)
3809 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
3813 if (mips_pic == NO_PIC)
3815 /* If this is a reference to a GP relative symbol, we want
3816 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3818 lui $reg,<sym> (BFD_RELOC_HI16_S)
3819 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3820 If we have an addend, we always use the latter form.
3822 With 64bit address space and a usable $at we want
3823 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3824 lui $at,<sym> (BFD_RELOC_HI16_S)
3825 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3826 daddiu $at,<sym> (BFD_RELOC_LO16)
3830 If $at is already in use, we use a path which is suboptimal
3831 on superscalar processors.
3832 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3833 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3835 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3837 daddiu $reg,<sym> (BFD_RELOC_LO16)
3839 if (HAVE_64BIT_ADDRESSES)
3841 /* ??? We don't provide a GP-relative alternative for these macros.
3842 It used not to be possible with the original relaxation code,
3843 but it could be done now. */
3845 if (*used_at == 0 && ! mips_opts.noat)
3847 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3848 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3849 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3850 BFD_RELOC_MIPS_HIGHER);
3851 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3852 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3853 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
3858 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3859 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3860 BFD_RELOC_MIPS_HIGHER);
3861 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3862 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3863 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3864 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3869 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3870 && ! nopic_need_relax (ep->X_add_symbol, 1))
3872 relax_start (ep->X_add_symbol);
3873 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3874 mips_gp_register, BFD_RELOC_GPREL16);
3877 macro_build_lui (ep, reg);
3878 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3879 reg, reg, BFD_RELOC_LO16);
3880 if (mips_relax.sequence)
3884 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3888 /* If this is a reference to an external symbol, we want
3889 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3891 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3893 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3894 If there is a constant, it must be added in after.
3896 If we have NewABI, we want
3897 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3898 unless we're referencing a global symbol with a non-zero
3899 offset, in which case cst must be added separately. */
3902 if (ep->X_add_number)
3904 ex.X_add_number = ep->X_add_number;
3905 ep->X_add_number = 0;
3906 relax_start (ep->X_add_symbol);
3907 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3908 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3909 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3910 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3911 ex.X_op = O_constant;
3912 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3913 reg, reg, BFD_RELOC_LO16);
3914 ep->X_add_number = ex.X_add_number;
3917 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3918 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
3919 if (mips_relax.sequence)
3924 ex.X_add_number = ep->X_add_number;
3925 ep->X_add_number = 0;
3926 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3927 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3928 macro_build (NULL, "nop", "");
3929 relax_start (ep->X_add_symbol);
3931 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3935 if (ex.X_add_number != 0)
3937 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3938 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3939 ex.X_op = O_constant;
3940 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3941 reg, reg, BFD_RELOC_LO16);
3945 else if (mips_pic == SVR4_PIC)
3949 /* This is the large GOT case. If this is a reference to an
3950 external symbol, we want
3951 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3953 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3955 Otherwise, for a reference to a local symbol in old ABI, we want
3956 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3958 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3959 If there is a constant, it must be added in after.
3961 In the NewABI, for local symbols, with or without offsets, we want:
3962 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3963 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3967 ex.X_add_number = ep->X_add_number;
3968 ep->X_add_number = 0;
3969 relax_start (ep->X_add_symbol);
3970 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3971 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3972 reg, reg, mips_gp_register);
3973 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
3974 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
3975 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3976 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3977 else if (ex.X_add_number)
3979 ex.X_op = O_constant;
3980 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3984 ep->X_add_number = ex.X_add_number;
3986 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3987 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
3988 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3989 BFD_RELOC_MIPS_GOT_OFST);
3994 ex.X_add_number = ep->X_add_number;
3995 ep->X_add_number = 0;
3996 relax_start (ep->X_add_symbol);
3997 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
3998 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
3999 reg, reg, mips_gp_register);
4000 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4001 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4003 if (reg_needs_delay (mips_gp_register))
4005 /* We need a nop before loading from $gp. This special
4006 check is required because the lui which starts the main
4007 instruction stream does not refer to $gp, and so will not
4008 insert the nop which may be required. */
4009 macro_build (NULL, "nop", "");
4011 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4012 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4013 macro_build (NULL, "nop", "");
4014 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4018 if (ex.X_add_number != 0)
4020 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4021 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4022 ex.X_op = O_constant;
4023 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4028 else if (mips_pic == EMBEDDED_PIC)
4031 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4033 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4034 reg, mips_gp_register, BFD_RELOC_GPREL16);
4040 /* Move the contents of register SOURCE into register DEST. */
4043 move_register (int dest, int source)
4045 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
4049 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4050 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4051 The two alternatives are:
4053 Global symbol Local sybmol
4054 ------------- ------------
4055 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4057 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4059 load_got_offset emits the first instruction and add_got_offset
4060 emits the second for a 16-bit offset or add_got_offset_hilo emits
4061 a sequence to add a 32-bit offset using a scratch register. */
4064 load_got_offset (int dest, expressionS *local)
4069 global.X_add_number = 0;
4071 relax_start (local->X_add_symbol);
4072 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4073 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4075 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
4076 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4081 add_got_offset (int dest, expressionS *local)
4085 global.X_op = O_constant;
4086 global.X_op_symbol = NULL;
4087 global.X_add_symbol = NULL;
4088 global.X_add_number = local->X_add_number;
4090 relax_start (local->X_add_symbol);
4091 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
4092 dest, dest, BFD_RELOC_LO16);
4094 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
4099 add_got_offset_hilo (int dest, expressionS *local, int tmp)
4102 int hold_mips_optimize;
4104 global.X_op = O_constant;
4105 global.X_op_symbol = NULL;
4106 global.X_add_symbol = NULL;
4107 global.X_add_number = local->X_add_number;
4109 relax_start (local->X_add_symbol);
4110 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
4112 /* Set mips_optimize around the lui instruction to avoid
4113 inserting an unnecessary nop after the lw. */
4114 hold_mips_optimize = mips_optimize;
4116 macro_build_lui (&global, tmp);
4117 mips_optimize = hold_mips_optimize;
4118 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
4121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
4126 * This routine implements the seemingly endless macro or synthesized
4127 * instructions and addressing modes in the mips assembly language. Many
4128 * of these macros are simple and are similar to each other. These could
4129 * probably be handled by some kind of table or grammar approach instead of
4130 * this verbose method. Others are not simple macros but are more like
4131 * optimizing code generation.
4132 * One interesting optimization is when several store macros appear
4133 * consecutively that would load AT with the upper half of the same address.
4134 * The ensuing load upper instructions are ommited. This implies some kind
4135 * of global optimization. We currently only optimize within a single macro.
4136 * For many of the load and store macros if the address is specified as a
4137 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4138 * first load register 'at' with zero and use it as the base register. The
4139 * mips assembler simply uses register $zero. Just one tiny optimization
4143 macro (struct mips_cl_insn *ip)
4145 register int treg, sreg, dreg, breg;
4161 bfd_reloc_code_real_type r;
4162 int hold_mips_optimize;
4164 assert (! mips_opts.mips16);
4166 treg = (ip->insn_opcode >> 16) & 0x1f;
4167 dreg = (ip->insn_opcode >> 11) & 0x1f;
4168 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
4169 mask = ip->insn_mo->mask;
4171 expr1.X_op = O_constant;
4172 expr1.X_op_symbol = NULL;
4173 expr1.X_add_symbol = NULL;
4174 expr1.X_add_number = 1;
4186 mips_emit_delays (TRUE);
4187 ++mips_opts.noreorder;
4188 mips_any_noreorder = 1;
4190 expr1.X_add_number = 8;
4191 macro_build (&expr1, "bgez", "s,p", sreg);
4193 macro_build (NULL, "nop", "", 0);
4195 move_register (dreg, sreg);
4196 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4198 --mips_opts.noreorder;
4219 if (imm_expr.X_op == O_constant
4220 && imm_expr.X_add_number >= -0x8000
4221 && imm_expr.X_add_number < 0x8000)
4223 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4226 load_register (AT, &imm_expr, dbl);
4227 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4246 if (imm_expr.X_op == O_constant
4247 && imm_expr.X_add_number >= 0
4248 && imm_expr.X_add_number < 0x10000)
4250 if (mask != M_NOR_I)
4251 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4254 macro_build (&imm_expr, "ori", "t,r,i",
4255 treg, sreg, BFD_RELOC_LO16);
4256 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4261 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4262 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4279 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4281 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4284 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4285 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4293 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4298 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4301 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4302 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4308 /* check for > max integer */
4309 maxnum = 0x7fffffff;
4310 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4317 if (imm_expr.X_op == O_constant
4318 && imm_expr.X_add_number >= maxnum
4319 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4322 /* result is always false */
4324 macro_build (NULL, "nop", "", 0);
4326 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4329 if (imm_expr.X_op != O_constant)
4330 as_bad (_("Unsupported large constant"));
4331 ++imm_expr.X_add_number;
4335 if (mask == M_BGEL_I)
4337 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4339 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4342 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4344 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4347 maxnum = 0x7fffffff;
4348 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4355 maxnum = - maxnum - 1;
4356 if (imm_expr.X_op == O_constant
4357 && imm_expr.X_add_number <= maxnum
4358 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4361 /* result is always true */
4362 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4363 macro_build (&offset_expr, "b", "p");
4367 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4377 macro_build (&offset_expr, likely ? "beql" : "beq",
4381 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4382 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4390 && imm_expr.X_op == O_constant
4391 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4393 if (imm_expr.X_op != O_constant)
4394 as_bad (_("Unsupported large constant"));
4395 ++imm_expr.X_add_number;
4399 if (mask == M_BGEUL_I)
4401 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4403 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4405 macro_build (&offset_expr, likely ? "bnel" : "bne",
4410 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4418 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4423 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4426 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4427 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4435 macro_build (&offset_expr, likely ? "bnel" : "bne",
4441 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4442 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4450 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4455 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4458 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4459 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4465 maxnum = 0x7fffffff;
4466 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4473 if (imm_expr.X_op == O_constant
4474 && imm_expr.X_add_number >= maxnum
4475 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4477 if (imm_expr.X_op != O_constant)
4478 as_bad (_("Unsupported large constant"));
4479 ++imm_expr.X_add_number;
4483 if (mask == M_BLTL_I)
4485 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4487 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4490 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4492 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4496 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4504 macro_build (&offset_expr, likely ? "beql" : "beq",
4510 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4511 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4519 && imm_expr.X_op == O_constant
4520 && imm_expr.X_add_number == (offsetT) 0xffffffff))
4522 if (imm_expr.X_op != O_constant)
4523 as_bad (_("Unsupported large constant"));
4524 ++imm_expr.X_add_number;
4528 if (mask == M_BLTUL_I)
4530 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4532 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4534 macro_build (&offset_expr, likely ? "beql" : "beq",
4539 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4547 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4552 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4555 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4556 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4566 macro_build (&offset_expr, likely ? "bnel" : "bne",
4570 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4571 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4579 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4581 as_bad (_("Unsupported large constant"));
4586 pos = (unsigned long) imm_expr.X_add_number;
4587 size = (unsigned long) imm2_expr.X_add_number;
4592 as_bad (_("Improper position (%lu)"), pos);
4595 if (size == 0 || size > 64
4596 || (pos + size - 1) > 63)
4598 as_bad (_("Improper extract size (%lu, position %lu)"),
4603 if (size <= 32 && pos < 32)
4608 else if (size <= 32)
4618 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4627 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4629 as_bad (_("Unsupported large constant"));
4634 pos = (unsigned long) imm_expr.X_add_number;
4635 size = (unsigned long) imm2_expr.X_add_number;
4640 as_bad (_("Improper position (%lu)"), pos);
4643 if (size == 0 || size > 64
4644 || (pos + size - 1) > 63)
4646 as_bad (_("Improper insert size (%lu, position %lu)"),
4651 if (pos < 32 && (pos + size - 1) < 32)
4666 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4683 as_warn (_("Divide by zero."));
4685 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4687 macro_build (NULL, "break", "c", 7);
4691 mips_emit_delays (TRUE);
4692 ++mips_opts.noreorder;
4693 mips_any_noreorder = 1;
4696 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4697 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4701 expr1.X_add_number = 8;
4702 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4703 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4704 macro_build (NULL, "break", "c", 7);
4706 expr1.X_add_number = -1;
4707 load_register (AT, &expr1, dbl);
4708 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4709 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4712 expr1.X_add_number = 1;
4713 load_register (AT, &expr1, dbl);
4714 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4718 expr1.X_add_number = 0x80000000;
4719 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4723 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4724 /* We want to close the noreorder block as soon as possible, so
4725 that later insns are available for delay slot filling. */
4726 --mips_opts.noreorder;
4730 expr1.X_add_number = 8;
4731 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4732 macro_build (NULL, "nop", "", 0);
4734 /* We want to close the noreorder block as soon as possible, so
4735 that later insns are available for delay slot filling. */
4736 --mips_opts.noreorder;
4738 macro_build (NULL, "break", "c", 6);
4740 macro_build (NULL, s, "d", dreg);
4779 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4781 as_warn (_("Divide by zero."));
4783 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4785 macro_build (NULL, "break", "c", 7);
4788 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4790 if (strcmp (s2, "mflo") == 0)
4791 move_register (dreg, sreg);
4793 move_register (dreg, 0);
4796 if (imm_expr.X_op == O_constant
4797 && imm_expr.X_add_number == -1
4798 && s[strlen (s) - 1] != 'u')
4800 if (strcmp (s2, "mflo") == 0)
4802 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4805 move_register (dreg, 0);
4809 load_register (AT, &imm_expr, dbl);
4810 macro_build (NULL, s, "z,s,t", sreg, AT);
4811 macro_build (NULL, s2, "d", dreg);
4830 mips_emit_delays (TRUE);
4831 ++mips_opts.noreorder;
4832 mips_any_noreorder = 1;
4835 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4836 macro_build (NULL, s, "z,s,t", sreg, treg);
4837 /* We want to close the noreorder block as soon as possible, so
4838 that later insns are available for delay slot filling. */
4839 --mips_opts.noreorder;
4843 expr1.X_add_number = 8;
4844 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4845 macro_build (NULL, s, "z,s,t", sreg, treg);
4847 /* We want to close the noreorder block as soon as possible, so
4848 that later insns are available for delay slot filling. */
4849 --mips_opts.noreorder;
4850 macro_build (NULL, "break", "c", 7);
4852 macro_build (NULL, s2, "d", dreg);
4864 /* Load the address of a symbol into a register. If breg is not
4865 zero, we then add a base register to it. */
4867 if (dbl && HAVE_32BIT_GPRS)
4868 as_warn (_("dla used to load 32-bit register"));
4870 if (! dbl && HAVE_64BIT_OBJECTS)
4871 as_warn (_("la used to load 64-bit address"));
4873 if (offset_expr.X_op == O_constant
4874 && offset_expr.X_add_number >= -0x8000
4875 && offset_expr.X_add_number < 0x8000)
4877 macro_build (&offset_expr,
4878 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4879 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4894 /* When generating embedded PIC code, we permit expressions of
4897 la $treg,foo-bar($breg)
4898 where bar is an address in the current section. These are used
4899 when getting the addresses of functions. We don't permit
4900 X_add_number to be non-zero, because if the symbol is
4901 external the relaxing code needs to know that any addend is
4902 purely the offset to X_op_symbol. */
4903 if (mips_pic == EMBEDDED_PIC
4904 && offset_expr.X_op == O_subtract
4905 && (symbol_constant_p (offset_expr.X_op_symbol)
4906 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4907 : (symbol_equated_p (offset_expr.X_op_symbol)
4909 (symbol_get_value_expression (offset_expr.X_op_symbol)
4912 && (offset_expr.X_add_number == 0
4913 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4919 macro_build (&offset_expr, "lui", "t,u",
4920 tempreg, BFD_RELOC_PCREL_HI16_S);
4924 macro_build (&offset_expr, "lui", "t,u",
4925 tempreg, BFD_RELOC_PCREL_HI16_S);
4927 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4928 "d,v,t", tempreg, tempreg, breg);
4930 macro_build (&offset_expr,
4931 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4932 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4938 if (offset_expr.X_op != O_symbol
4939 && offset_expr.X_op != O_constant)
4941 as_bad (_("expression too complex"));
4942 offset_expr.X_op = O_constant;
4945 if (offset_expr.X_op == O_constant)
4946 load_register (tempreg, &offset_expr,
4947 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4948 ? (dbl || HAVE_64BIT_ADDRESSES)
4949 : HAVE_64BIT_ADDRESSES));
4950 else if (mips_pic == NO_PIC)
4952 /* If this is a reference to a GP relative symbol, we want
4953 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4955 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4956 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4957 If we have a constant, we need two instructions anyhow,
4958 so we may as well always use the latter form.
4960 With 64bit address space and a usable $at we want
4961 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4962 lui $at,<sym> (BFD_RELOC_HI16_S)
4963 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4964 daddiu $at,<sym> (BFD_RELOC_LO16)
4966 daddu $tempreg,$tempreg,$at
4968 If $at is already in use, we use a path which is suboptimal
4969 on superscalar processors.
4970 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4971 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4973 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4975 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4977 if (HAVE_64BIT_ADDRESSES)
4979 /* ??? We don't provide a GP-relative alternative for
4980 these macros. It used not to be possible with the
4981 original relaxation code, but it could be done now. */
4983 if (used_at == 0 && ! mips_opts.noat)
4985 macro_build (&offset_expr, "lui", "t,u",
4986 tempreg, BFD_RELOC_MIPS_HIGHEST);
4987 macro_build (&offset_expr, "lui", "t,u",
4988 AT, BFD_RELOC_HI16_S);
4989 macro_build (&offset_expr, "daddiu", "t,r,j",
4990 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4991 macro_build (&offset_expr, "daddiu", "t,r,j",
4992 AT, AT, BFD_RELOC_LO16);
4993 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
4994 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
4999 macro_build (&offset_expr, "lui", "t,u",
5000 tempreg, BFD_RELOC_MIPS_HIGHEST);
5001 macro_build (&offset_expr, "daddiu", "t,r,j",
5002 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5003 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5004 macro_build (&offset_expr, "daddiu", "t,r,j",
5005 tempreg, tempreg, BFD_RELOC_HI16_S);
5006 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5007 macro_build (&offset_expr, "daddiu", "t,r,j",
5008 tempreg, tempreg, BFD_RELOC_LO16);
5013 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5014 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
5016 relax_start (offset_expr.X_add_symbol);
5017 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5018 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5021 macro_build_lui (&offset_expr, tempreg);
5022 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5023 tempreg, tempreg, BFD_RELOC_LO16);
5024 if (mips_relax.sequence)
5028 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
5030 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5032 /* If this is a reference to an external symbol, and there
5033 is no constant, we want
5034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5035 or for lca or if tempreg is PIC_CALL_REG
5036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5037 For a local symbol, we want
5038 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5040 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5042 If we have a small constant, and this is a reference to
5043 an external symbol, we want
5044 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5046 addiu $tempreg,$tempreg,<constant>
5047 For a local symbol, we want the same instruction
5048 sequence, but we output a BFD_RELOC_LO16 reloc on the
5051 If we have a large constant, and this is a reference to
5052 an external symbol, we want
5053 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5054 lui $at,<hiconstant>
5055 addiu $at,$at,<loconstant>
5056 addu $tempreg,$tempreg,$at
5057 For a local symbol, we want the same instruction
5058 sequence, but we output a BFD_RELOC_LO16 reloc on the
5062 if (offset_expr.X_add_number == 0)
5064 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5065 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5067 relax_start (offset_expr.X_add_symbol);
5068 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5069 lw_reloc_type, mips_gp_register);
5072 /* We're going to put in an addu instruction using
5073 tempreg, so we may as well insert the nop right
5075 macro_build (NULL, "nop", "");
5078 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5079 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5080 macro_build (NULL, "nop", "");
5081 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5082 tempreg, tempreg, BFD_RELOC_LO16);
5084 /* FIXME: If breg == 0, and the next instruction uses
5085 $tempreg, then if this variant case is used an extra
5086 nop will be generated. */
5088 else if (offset_expr.X_add_number >= -0x8000
5089 && offset_expr.X_add_number < 0x8000)
5091 load_got_offset (tempreg, &offset_expr);
5092 macro_build (NULL, "nop", "");
5093 add_got_offset (tempreg, &offset_expr);
5097 expr1.X_add_number = offset_expr.X_add_number;
5098 offset_expr.X_add_number =
5099 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5100 load_got_offset (tempreg, &offset_expr);
5101 offset_expr.X_add_number = expr1.X_add_number;
5102 /* If we are going to add in a base register, and the
5103 target register and the base register are the same,
5104 then we are using AT as a temporary register. Since
5105 we want to load the constant into AT, we add our
5106 current AT (from the global offset table) and the
5107 register into the register now, and pretend we were
5108 not using a base register. */
5111 macro_build (NULL, "nop", "");
5112 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5117 add_got_offset_hilo (tempreg, &offset_expr, AT);
5121 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5123 int add_breg_early = 0;
5125 /* If this is a reference to an external, and there is no
5126 constant, or local symbol (*), with or without a
5128 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5129 or for lca or if tempreg is PIC_CALL_REG
5130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5132 If we have a small constant, and this is a reference to
5133 an external symbol, we want
5134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5135 addiu $tempreg,$tempreg,<constant>
5137 If we have a large constant, and this is a reference to
5138 an external symbol, we want
5139 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5140 lui $at,<hiconstant>
5141 addiu $at,$at,<loconstant>
5142 addu $tempreg,$tempreg,$at
5144 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5145 local symbols, even though it introduces an additional
5148 if (offset_expr.X_add_number)
5150 expr1.X_add_number = offset_expr.X_add_number;
5151 offset_expr.X_add_number = 0;
5153 relax_start (offset_expr.X_add_symbol);
5154 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5155 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5157 if (expr1.X_add_number >= -0x8000
5158 && expr1.X_add_number < 0x8000)
5160 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5161 tempreg, tempreg, BFD_RELOC_LO16);
5163 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5167 /* If we are going to add in a base register, and the
5168 target register and the base register are the same,
5169 then we are using AT as a temporary register. Since
5170 we want to load the constant into AT, we add our
5171 current AT (from the global offset table) and the
5172 register into the register now, and pretend we were
5173 not using a base register. */
5178 assert (tempreg == AT);
5179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5185 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5186 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5192 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5195 offset_expr.X_add_number = expr1.X_add_number;
5197 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5198 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5201 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5202 treg, tempreg, breg);
5208 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5210 relax_start (offset_expr.X_add_symbol);
5211 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5212 BFD_RELOC_MIPS_CALL16, mips_gp_register);
5214 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5215 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5220 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5221 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5224 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5227 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5228 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5229 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5231 /* This is the large GOT case. If this is a reference to an
5232 external symbol, and there is no constant, we want
5233 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5234 addu $tempreg,$tempreg,$gp
5235 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5236 or for lca or if tempreg is PIC_CALL_REG
5237 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5238 addu $tempreg,$tempreg,$gp
5239 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5240 For a local symbol, we want
5241 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5243 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5245 If we have a small constant, and this is a reference to
5246 an external symbol, we want
5247 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5248 addu $tempreg,$tempreg,$gp
5249 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5251 addiu $tempreg,$tempreg,<constant>
5252 For a local symbol, we want
5253 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5255 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5257 If we have a large constant, and this is a reference to
5258 an external symbol, we want
5259 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5260 addu $tempreg,$tempreg,$gp
5261 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5262 lui $at,<hiconstant>
5263 addiu $at,$at,<loconstant>
5264 addu $tempreg,$tempreg,$at
5265 For a local symbol, we want
5266 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5267 lui $at,<hiconstant>
5268 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5269 addu $tempreg,$tempreg,$at
5272 expr1.X_add_number = offset_expr.X_add_number;
5273 offset_expr.X_add_number = 0;
5274 relax_start (offset_expr.X_add_symbol);
5275 gpdelay = reg_needs_delay (mips_gp_register);
5276 if (expr1.X_add_number == 0 && breg == 0
5277 && (call || tempreg == PIC_CALL_REG))
5279 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5280 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5282 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5283 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5284 tempreg, tempreg, mips_gp_register);
5285 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5286 tempreg, lw_reloc_type, tempreg);
5287 if (expr1.X_add_number == 0)
5291 /* We're going to put in an addu instruction using
5292 tempreg, so we may as well insert the nop right
5294 macro_build (NULL, "nop", "");
5297 else if (expr1.X_add_number >= -0x8000
5298 && expr1.X_add_number < 0x8000)
5300 macro_build (NULL, "nop", "");
5301 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5302 tempreg, tempreg, BFD_RELOC_LO16);
5308 /* If we are going to add in a base register, and the
5309 target register and the base register are the same,
5310 then we are using AT as a temporary register. Since
5311 we want to load the constant into AT, we add our
5312 current AT (from the global offset table) and the
5313 register into the register now, and pretend we were
5314 not using a base register. */
5319 assert (tempreg == AT);
5320 macro_build (NULL, "nop", "");
5321 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5326 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5331 offset_expr.X_add_number =
5332 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
5337 /* This is needed because this instruction uses $gp, but
5338 the first instruction on the main stream does not. */
5339 macro_build (NULL, "nop", "");
5342 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5343 local_reloc_type, mips_gp_register);
5344 if (expr1.X_add_number >= -0x8000
5345 && expr1.X_add_number < 0x8000)
5347 macro_build (NULL, "nop", "");
5348 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5349 tempreg, tempreg, BFD_RELOC_LO16);
5350 /* FIXME: If add_number is 0, and there was no base
5351 register, the external symbol case ended with a load,
5352 so if the symbol turns out to not be external, and
5353 the next instruction uses tempreg, an unnecessary nop
5354 will be inserted. */
5360 /* We must add in the base register now, as in the
5361 external symbol case. */
5362 assert (tempreg == AT);
5363 macro_build (NULL, "nop", "");
5364 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5367 /* We set breg to 0 because we have arranged to add
5368 it in in both cases. */
5372 macro_build_lui (&expr1, AT);
5373 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5374 AT, AT, BFD_RELOC_LO16);
5375 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5376 tempreg, tempreg, AT);
5380 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5382 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5383 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5384 int add_breg_early = 0;
5386 /* This is the large GOT case. If this is a reference to an
5387 external symbol, and there is no constant, we want
5388 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5389 add $tempreg,$tempreg,$gp
5390 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5391 or for lca or if tempreg is PIC_CALL_REG
5392 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5393 add $tempreg,$tempreg,$gp
5394 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5396 If we have a small constant, and this is a reference to
5397 an external symbol, we want
5398 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5399 add $tempreg,$tempreg,$gp
5400 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5401 addi $tempreg,$tempreg,<constant>
5403 If we have a large constant, and this is a reference to
5404 an external symbol, we want
5405 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5406 addu $tempreg,$tempreg,$gp
5407 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5408 lui $at,<hiconstant>
5409 addi $at,$at,<loconstant>
5410 add $tempreg,$tempreg,$at
5412 If we have NewABI, and we know it's a local symbol, we want
5413 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5414 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5415 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5417 relax_start (offset_expr.X_add_symbol);
5419 expr1.X_add_number = offset_expr.X_add_number;
5420 offset_expr.X_add_number = 0;
5422 if (expr1.X_add_number == 0 && breg == 0
5423 && (call || tempreg == PIC_CALL_REG))
5425 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
5426 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
5428 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
5429 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5430 tempreg, tempreg, mips_gp_register);
5431 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5432 tempreg, lw_reloc_type, tempreg);
5434 if (expr1.X_add_number == 0)
5436 else if (expr1.X_add_number >= -0x8000
5437 && expr1.X_add_number < 0x8000)
5439 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5440 tempreg, tempreg, BFD_RELOC_LO16);
5442 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
5446 /* If we are going to add in a base register, and the
5447 target register and the base register are the same,
5448 then we are using AT as a temporary register. Since
5449 we want to load the constant into AT, we add our
5450 current AT (from the global offset table) and the
5451 register into the register now, and pretend we were
5452 not using a base register. */
5457 assert (tempreg == AT);
5458 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5464 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5465 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5470 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5473 offset_expr.X_add_number = expr1.X_add_number;
5474 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5475 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
5476 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5477 tempreg, BFD_RELOC_MIPS_GOT_OFST);
5480 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5481 treg, tempreg, breg);
5487 else if (mips_pic == EMBEDDED_PIC)
5490 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5492 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5493 mips_gp_register, BFD_RELOC_GPREL16);
5502 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5503 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5505 s = ADDRESS_ADD_INSN;
5507 macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
5516 /* The j instruction may not be used in PIC code, since it
5517 requires an absolute address. We convert it to a b
5519 if (mips_pic == NO_PIC)
5520 macro_build (&offset_expr, "j", "a");
5522 macro_build (&offset_expr, "b", "p");
5525 /* The jal instructions must be handled as macros because when
5526 generating PIC code they expand to multi-instruction
5527 sequences. Normally they are simple instructions. */
5532 if (mips_pic == NO_PIC
5533 || mips_pic == EMBEDDED_PIC)
5534 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5535 else if (mips_pic == SVR4_PIC)
5537 if (sreg != PIC_CALL_REG)
5538 as_warn (_("MIPS PIC call to register other than $25"));
5540 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5543 if (mips_cprestore_offset < 0)
5544 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5547 if (! mips_frame_reg_valid)
5549 as_warn (_("No .frame pseudo-op used in PIC code"));
5550 /* Quiet this warning. */
5551 mips_frame_reg_valid = 1;
5553 if (! mips_cprestore_valid)
5555 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5556 /* Quiet this warning. */
5557 mips_cprestore_valid = 1;
5559 expr1.X_add_number = mips_cprestore_offset;
5560 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5563 HAVE_64BIT_ADDRESSES);
5573 if (mips_pic == NO_PIC)
5574 macro_build (&offset_expr, "jal", "a");
5575 else if (mips_pic == SVR4_PIC)
5577 /* If this is a reference to an external symbol, and we are
5578 using a small GOT, we want
5579 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5583 lw $gp,cprestore($sp)
5584 The cprestore value is set using the .cprestore
5585 pseudo-op. If we are using a big GOT, we want
5586 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5588 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5592 lw $gp,cprestore($sp)
5593 If the symbol is not external, we want
5594 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5596 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5599 lw $gp,cprestore($sp)
5601 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5602 sequences above, minus nops, unless the symbol is local,
5603 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5609 relax_start (offset_expr.X_add_symbol);
5610 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5611 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5614 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5615 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
5621 relax_start (offset_expr.X_add_symbol);
5622 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5623 BFD_RELOC_MIPS_CALL_HI16);
5624 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5625 PIC_CALL_REG, mips_gp_register);
5626 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5627 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5630 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5631 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
5633 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5634 PIC_CALL_REG, PIC_CALL_REG,
5635 BFD_RELOC_MIPS_GOT_OFST);
5639 macro_build_jalr (&offset_expr);
5643 relax_start (offset_expr.X_add_symbol);
5646 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5647 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5649 macro_build (NULL, "nop", "");
5656 gpdelay = reg_needs_delay (mips_gp_register);
5657 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5658 BFD_RELOC_MIPS_CALL_HI16);
5659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5660 PIC_CALL_REG, mips_gp_register);
5661 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5662 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5664 macro_build (NULL, "nop", "");
5667 macro_build (NULL, "nop", "");
5669 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5670 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5672 macro_build (NULL, "nop", "");
5673 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5674 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5676 macro_build_jalr (&offset_expr);
5678 if (mips_cprestore_offset < 0)
5679 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5682 if (! mips_frame_reg_valid)
5684 as_warn (_("No .frame pseudo-op used in PIC code"));
5685 /* Quiet this warning. */
5686 mips_frame_reg_valid = 1;
5688 if (! mips_cprestore_valid)
5690 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5691 /* Quiet this warning. */
5692 mips_cprestore_valid = 1;
5694 if (mips_opts.noreorder)
5695 macro_build (NULL, "nop", "");
5696 expr1.X_add_number = mips_cprestore_offset;
5697 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5700 HAVE_64BIT_ADDRESSES);
5704 else if (mips_pic == EMBEDDED_PIC)
5706 macro_build (&offset_expr, "bal", "p");
5707 /* The linker may expand the call to a longer sequence which
5708 uses $at, so we must break rather than return. */
5733 /* Itbl support may require additional care here. */
5738 /* Itbl support may require additional care here. */
5743 /* Itbl support may require additional care here. */
5748 /* Itbl support may require additional care here. */
5760 if (mips_opts.arch == CPU_R4650)
5762 as_bad (_("opcode not supported on this processor"));
5766 /* Itbl support may require additional care here. */
5771 /* Itbl support may require additional care here. */
5776 /* Itbl support may require additional care here. */
5796 if (breg == treg || coproc || lr)
5818 /* Itbl support may require additional care here. */
5823 /* Itbl support may require additional care here. */
5828 /* Itbl support may require additional care here. */
5833 /* Itbl support may require additional care here. */
5849 if (mips_opts.arch == CPU_R4650)
5851 as_bad (_("opcode not supported on this processor"));
5856 /* Itbl support may require additional care here. */
5860 /* Itbl support may require additional care here. */
5865 /* Itbl support may require additional care here. */
5877 /* Itbl support may require additional care here. */
5878 if (mask == M_LWC1_AB
5879 || mask == M_SWC1_AB
5880 || mask == M_LDC1_AB
5881 || mask == M_SDC1_AB
5890 /* Sign-extending 32-bit constants makes their handling easier.
5891 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5893 if ((! HAVE_64BIT_ADDRESSES
5894 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5895 && (offset_expr.X_op == O_constant)
5896 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5897 == ~((bfd_vma) 0x7fffffff)))
5899 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5900 as_bad (_("constant too large"));
5902 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5903 ^ 0x80000000) - 0x80000000);
5906 /* For embedded PIC, we allow loads where the offset is calculated
5907 by subtracting a symbol in the current segment from an unknown
5908 symbol, relative to a base register, e.g.:
5909 <op> $treg, <sym>-<localsym>($breg)
5910 This is used by the compiler for switch statements. */
5911 if (mips_pic == EMBEDDED_PIC
5912 && offset_expr.X_op == O_subtract
5913 && (symbol_constant_p (offset_expr.X_op_symbol)
5914 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5915 : (symbol_equated_p (offset_expr.X_op_symbol)
5917 (symbol_get_value_expression (offset_expr.X_op_symbol)
5921 && (offset_expr.X_add_number == 0
5922 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5924 /* For this case, we output the instructions:
5925 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5926 addiu $tempreg,$tempreg,$breg
5927 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5928 If the relocation would fit entirely in 16 bits, it would be
5930 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5931 instead, but that seems quite difficult. */
5932 macro_build (&offset_expr, "lui", "t,u", tempreg,
5933 BFD_RELOC_PCREL_HI16_S);
5935 ((bfd_arch_bits_per_address (stdoutput) == 32
5936 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5937 ? "addu" : "daddu"),
5938 "d,v,t", tempreg, tempreg, breg);
5939 macro_build (&offset_expr, s, fmt, treg,
5940 BFD_RELOC_PCREL_LO16, tempreg);
5946 if (offset_expr.X_op != O_constant
5947 && offset_expr.X_op != O_symbol)
5949 as_bad (_("expression too complex"));
5950 offset_expr.X_op = O_constant;
5953 /* A constant expression in PIC code can be handled just as it
5954 is in non PIC code. */
5955 if (mips_pic == NO_PIC
5956 || offset_expr.X_op == O_constant)
5958 /* If this is a reference to a GP relative symbol, and there
5959 is no base register, we want
5960 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5961 Otherwise, if there is no base register, we want
5962 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5963 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5964 If we have a constant, we need two instructions anyhow,
5965 so we always use the latter form.
5967 If we have a base register, and this is a reference to a
5968 GP relative symbol, we want
5969 addu $tempreg,$breg,$gp
5970 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5972 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5973 addu $tempreg,$tempreg,$breg
5974 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5975 With a constant we always use the latter case.
5977 With 64bit address space and no base register and $at usable,
5979 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5980 lui $at,<sym> (BFD_RELOC_HI16_S)
5981 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5984 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5985 If we have a base register, we want
5986 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5987 lui $at,<sym> (BFD_RELOC_HI16_S)
5988 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5992 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5994 Without $at we can't generate the optimal path for superscalar
5995 processors here since this would require two temporary registers.
5996 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5997 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5999 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6001 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6002 If we have a base register, we want
6003 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6004 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6006 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6008 daddu $tempreg,$tempreg,$breg
6009 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6011 If we have 64-bit addresses, as an optimization, for
6012 addresses which are 32-bit constants (e.g. kseg0/kseg1
6013 addresses) we fall back to the 32-bit address generation
6014 mechanism since it is more efficient. Note that due to
6015 the signed offset used by memory operations, the 32-bit
6016 range is shifted down by 32768 here. This code should
6017 probably attempt to generate 64-bit constants more
6018 efficiently in general.
6020 As an extension for architectures with 64-bit registers,
6021 we don't truncate 64-bit addresses given as literal
6022 constants down to 32 bits, to support existing practice
6023 in the mips64 Linux (the kernel), that compiles source
6024 files with -mabi=64, assembling them as o32 or n32 (with
6025 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6026 the whole kernel is loaded into a memory region that is
6027 addressable with sign-extended 32-bit addresses, it is
6028 wasteful to compute the upper 32 bits of every
6029 non-literal address, that takes more space and time.
6030 Some day this should probably be implemented as an
6031 assembler option, such that the kernel doesn't have to
6032 use such ugly hacks, even though it will still have to
6033 end up converting the binary to ELF32 for a number of
6034 platforms whose boot loaders don't support ELF64
6036 if ((HAVE_64BIT_ADDRESSES
6037 && ! (offset_expr.X_op == O_constant
6038 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6040 && offset_expr.X_op == O_constant
6041 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6043 /* ??? We don't provide a GP-relative alternative for
6044 these macros. It used not to be possible with the
6045 original relaxation code, but it could be done now. */
6047 if (used_at == 0 && ! mips_opts.noat)
6049 macro_build (&offset_expr, "lui", "t,u", tempreg,
6050 BFD_RELOC_MIPS_HIGHEST);
6051 macro_build (&offset_expr, "lui", "t,u", AT,
6053 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6054 tempreg, BFD_RELOC_MIPS_HIGHER);
6056 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6057 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6058 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6059 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6065 macro_build (&offset_expr, "lui", "t,u", tempreg,
6066 BFD_RELOC_MIPS_HIGHEST);
6067 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6068 tempreg, BFD_RELOC_MIPS_HIGHER);
6069 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6070 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6071 tempreg, BFD_RELOC_HI16_S);
6072 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6074 macro_build (NULL, "daddu", "d,v,t",
6075 tempreg, tempreg, breg);
6076 macro_build (&offset_expr, s, fmt, treg,
6077 BFD_RELOC_LO16, tempreg);
6083 if (offset_expr.X_op == O_constant
6084 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
6085 as_bad (_("load/store address overflow (max 32 bits)"));
6089 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6090 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6092 relax_start (offset_expr.X_add_symbol);
6093 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6098 macro_build_lui (&offset_expr, tempreg);
6099 macro_build (&offset_expr, s, fmt, treg,
6100 BFD_RELOC_LO16, tempreg);
6101 if (mips_relax.sequence)
6106 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6107 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6109 relax_start (offset_expr.X_add_symbol);
6110 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6111 tempreg, breg, mips_gp_register);
6112 macro_build (&offset_expr, s, fmt, treg,
6113 BFD_RELOC_GPREL16, tempreg);
6116 macro_build_lui (&offset_expr, tempreg);
6117 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6118 tempreg, tempreg, breg);
6119 macro_build (&offset_expr, s, fmt, treg,
6120 BFD_RELOC_LO16, tempreg);
6121 if (mips_relax.sequence)
6125 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6127 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6129 /* If this is a reference to an external symbol, we want
6130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6132 <op> $treg,0($tempreg)
6134 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6136 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6137 <op> $treg,0($tempreg)
6140 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6141 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6143 If there is a base register, we add it to $tempreg before
6144 the <op>. If there is a constant, we stick it in the
6145 <op> instruction. We don't handle constants larger than
6146 16 bits, because we have no way to load the upper 16 bits
6147 (actually, we could handle them for the subset of cases
6148 in which we are not using $at). */
6149 assert (offset_expr.X_op == O_symbol);
6152 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6153 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6156 tempreg, tempreg, breg);
6157 macro_build (&offset_expr, s, fmt, treg,
6158 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6165 expr1.X_add_number = offset_expr.X_add_number;
6166 offset_expr.X_add_number = 0;
6167 if (expr1.X_add_number < -0x8000
6168 || expr1.X_add_number >= 0x8000)
6169 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6170 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6171 lw_reloc_type, mips_gp_register);
6172 macro_build (NULL, "nop", "");
6173 relax_start (offset_expr.X_add_symbol);
6175 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6176 tempreg, BFD_RELOC_LO16);
6179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6180 tempreg, tempreg, breg);
6181 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6183 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6187 /* If this is a reference to an external symbol, we want
6188 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6189 addu $tempreg,$tempreg,$gp
6190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6191 <op> $treg,0($tempreg)
6193 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6195 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6196 <op> $treg,0($tempreg)
6197 If there is a base register, we add it to $tempreg before
6198 the <op>. If there is a constant, we stick it in the
6199 <op> instruction. We don't handle constants larger than
6200 16 bits, because we have no way to load the upper 16 bits
6201 (actually, we could handle them for the subset of cases
6202 in which we are not using $at). */
6203 assert (offset_expr.X_op == O_symbol);
6204 expr1.X_add_number = offset_expr.X_add_number;
6205 offset_expr.X_add_number = 0;
6206 if (expr1.X_add_number < -0x8000
6207 || expr1.X_add_number >= 0x8000)
6208 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6209 gpdelay = reg_needs_delay (mips_gp_register);
6210 relax_start (offset_expr.X_add_symbol);
6211 macro_build (&offset_expr, "lui", "t,u", tempreg,
6212 BFD_RELOC_MIPS_GOT_HI16);
6213 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6215 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6216 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6219 macro_build (NULL, "nop", "");
6220 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6221 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6222 macro_build (NULL, "nop", "");
6223 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6224 tempreg, BFD_RELOC_LO16);
6228 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6229 tempreg, tempreg, breg);
6230 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6232 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6234 /* If this is a reference to an external symbol, we want
6235 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6236 add $tempreg,$tempreg,$gp
6237 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6238 <op> $treg,<ofst>($tempreg)
6239 Otherwise, for local symbols, we want:
6240 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6241 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6242 assert (offset_expr.X_op == O_symbol);
6243 expr1.X_add_number = offset_expr.X_add_number;
6244 offset_expr.X_add_number = 0;
6245 if (expr1.X_add_number < -0x8000
6246 || expr1.X_add_number >= 0x8000)
6247 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6248 relax_start (offset_expr.X_add_symbol);
6249 macro_build (&offset_expr, "lui", "t,u", tempreg,
6250 BFD_RELOC_MIPS_GOT_HI16);
6251 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
6253 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6254 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6256 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6257 tempreg, tempreg, breg);
6258 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6261 offset_expr.X_add_number = expr1.X_add_number;
6262 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6263 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6265 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6266 tempreg, tempreg, breg);
6267 macro_build (&offset_expr, s, fmt, treg,
6268 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6271 else if (mips_pic == EMBEDDED_PIC)
6273 /* If there is no base register, we want
6274 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6275 If there is a base register, we want
6276 addu $tempreg,$breg,$gp
6277 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6279 assert (offset_expr.X_op == O_symbol);
6282 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6288 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6289 tempreg, breg, mips_gp_register);
6290 macro_build (&offset_expr, s, fmt, treg,
6291 BFD_RELOC_GPREL16, tempreg);
6304 load_register (treg, &imm_expr, 0);
6308 load_register (treg, &imm_expr, 1);
6312 if (imm_expr.X_op == O_constant)
6314 load_register (AT, &imm_expr, 0);
6315 macro_build (NULL, "mtc1", "t,G", AT, treg);
6320 assert (offset_expr.X_op == O_symbol
6321 && strcmp (segment_name (S_GET_SEGMENT
6322 (offset_expr.X_add_symbol)),
6324 && offset_expr.X_add_number == 0);
6325 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6326 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6331 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6332 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6333 order 32 bits of the value and the low order 32 bits are either
6334 zero or in OFFSET_EXPR. */
6335 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6337 if (HAVE_64BIT_GPRS)
6338 load_register (treg, &imm_expr, 1);
6343 if (target_big_endian)
6355 load_register (hreg, &imm_expr, 0);
6358 if (offset_expr.X_op == O_absent)
6359 move_register (lreg, 0);
6362 assert (offset_expr.X_op == O_constant);
6363 load_register (lreg, &offset_expr, 0);
6370 /* We know that sym is in the .rdata section. First we get the
6371 upper 16 bits of the address. */
6372 if (mips_pic == NO_PIC)
6374 macro_build_lui (&offset_expr, AT);
6376 else if (mips_pic == SVR4_PIC)
6378 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6379 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6381 else if (mips_pic == EMBEDDED_PIC)
6383 /* For embedded PIC we pick up the entire address off $gp in
6384 a single instruction. */
6385 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT,
6386 mips_gp_register, BFD_RELOC_GPREL16);
6387 offset_expr.X_op = O_constant;
6388 offset_expr.X_add_number = 0;
6393 /* Now we load the register(s). */
6394 if (HAVE_64BIT_GPRS)
6395 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6398 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6401 /* FIXME: How in the world do we deal with the possible
6403 offset_expr.X_add_number += 4;
6404 macro_build (&offset_expr, "lw", "t,o(b)",
6405 treg + 1, BFD_RELOC_LO16, AT);
6411 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6412 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6413 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6414 the value and the low order 32 bits are either zero or in
6416 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6418 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6419 if (HAVE_64BIT_FPRS)
6421 assert (HAVE_64BIT_GPRS);
6422 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6426 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
6427 if (offset_expr.X_op == O_absent)
6428 macro_build (NULL, "mtc1", "t,G", 0, treg);
6431 assert (offset_expr.X_op == O_constant);
6432 load_register (AT, &offset_expr, 0);
6433 macro_build (NULL, "mtc1", "t,G", AT, treg);
6439 assert (offset_expr.X_op == O_symbol
6440 && offset_expr.X_add_number == 0);
6441 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6442 if (strcmp (s, ".lit8") == 0)
6444 if (mips_opts.isa != ISA_MIPS1)
6446 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6447 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6450 breg = mips_gp_register;
6451 r = BFD_RELOC_MIPS_LITERAL;
6456 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6457 if (mips_pic == SVR4_PIC)
6458 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6459 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6462 /* FIXME: This won't work for a 64 bit address. */
6463 macro_build_lui (&offset_expr, AT);
6466 if (mips_opts.isa != ISA_MIPS1)
6468 macro_build (&offset_expr, "ldc1", "T,o(b)",
6469 treg, BFD_RELOC_LO16, AT);
6478 if (mips_opts.arch == CPU_R4650)
6480 as_bad (_("opcode not supported on this processor"));
6483 /* Even on a big endian machine $fn comes before $fn+1. We have
6484 to adjust when loading from memory. */
6487 assert (mips_opts.isa == ISA_MIPS1);
6488 macro_build (&offset_expr, "lwc1", "T,o(b)",
6489 target_big_endian ? treg + 1 : treg, r, breg);
6490 /* FIXME: A possible overflow which I don't know how to deal
6492 offset_expr.X_add_number += 4;
6493 macro_build (&offset_expr, "lwc1", "T,o(b)",
6494 target_big_endian ? treg : treg + 1, r, breg);
6502 * The MIPS assembler seems to check for X_add_number not
6503 * being double aligned and generating:
6506 * addiu at,at,%lo(foo+1)
6509 * But, the resulting address is the same after relocation so why
6510 * generate the extra instruction?
6512 if (mips_opts.arch == CPU_R4650)
6514 as_bad (_("opcode not supported on this processor"));
6517 /* Itbl support may require additional care here. */
6519 if (mips_opts.isa != ISA_MIPS1)
6530 if (mips_opts.arch == CPU_R4650)
6532 as_bad (_("opcode not supported on this processor"));
6536 if (mips_opts.isa != ISA_MIPS1)
6544 /* Itbl support may require additional care here. */
6549 if (HAVE_64BIT_GPRS)
6560 if (HAVE_64BIT_GPRS)
6570 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6571 loads for the case of doing a pair of loads to simulate an 'ld'.
6572 This is not currently done by the compiler, and assembly coders
6573 writing embedded-pic code can cope. */
6575 if (offset_expr.X_op != O_symbol
6576 && offset_expr.X_op != O_constant)
6578 as_bad (_("expression too complex"));
6579 offset_expr.X_op = O_constant;
6582 /* Even on a big endian machine $fn comes before $fn+1. We have
6583 to adjust when loading from memory. We set coproc if we must
6584 load $fn+1 first. */
6585 /* Itbl support may require additional care here. */
6586 if (! target_big_endian)
6589 if (mips_pic == NO_PIC
6590 || offset_expr.X_op == O_constant)
6592 /* If this is a reference to a GP relative symbol, we want
6593 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6594 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6595 If we have a base register, we use this
6597 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6598 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6599 If this is not a GP relative symbol, we want
6600 lui $at,<sym> (BFD_RELOC_HI16_S)
6601 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6602 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6603 If there is a base register, we add it to $at after the
6604 lui instruction. If there is a constant, we always use
6606 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6607 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6611 relax_start (offset_expr.X_add_symbol);
6614 tempreg = mips_gp_register;
6619 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6620 AT, breg, mips_gp_register);
6625 /* Itbl support may require additional care here. */
6626 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6627 BFD_RELOC_GPREL16, tempreg);
6628 offset_expr.X_add_number += 4;
6630 /* Set mips_optimize to 2 to avoid inserting an
6632 hold_mips_optimize = mips_optimize;
6634 /* Itbl support may require additional care here. */
6635 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6636 BFD_RELOC_GPREL16, tempreg);
6637 mips_optimize = hold_mips_optimize;
6641 /* We just generated two relocs. When tc_gen_reloc
6642 handles this case, it will skip the first reloc and
6643 handle the second. The second reloc already has an
6644 extra addend of 4, which we added above. We must
6645 subtract it out, and then subtract another 4 to make
6646 the first reloc come out right. The second reloc
6647 will come out right because we are going to add 4 to
6648 offset_expr when we build its instruction below.
6650 If we have a symbol, then we don't want to include
6651 the offset, because it will wind up being included
6652 when we generate the reloc. */
6654 if (offset_expr.X_op == O_constant)
6655 offset_expr.X_add_number -= 8;
6658 offset_expr.X_add_number = -4;
6659 offset_expr.X_op = O_constant;
6662 macro_build_lui (&offset_expr, AT);
6664 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6665 /* Itbl support may require additional care here. */
6666 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6667 BFD_RELOC_LO16, AT);
6668 /* FIXME: How do we handle overflow here? */
6669 offset_expr.X_add_number += 4;
6670 /* Itbl support may require additional care here. */
6671 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6672 BFD_RELOC_LO16, AT);
6673 if (mips_relax.sequence)
6676 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6678 /* If this is a reference to an external symbol, we want
6679 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6684 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6686 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6687 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6688 If there is a base register we add it to $at before the
6689 lwc1 instructions. If there is a constant we include it
6690 in the lwc1 instructions. */
6692 expr1.X_add_number = offset_expr.X_add_number;
6693 if (expr1.X_add_number < -0x8000
6694 || expr1.X_add_number >= 0x8000 - 4)
6695 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6696 load_got_offset (AT, &offset_expr);
6697 macro_build (NULL, "nop", "");
6699 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6701 /* Set mips_optimize to 2 to avoid inserting an undesired
6703 hold_mips_optimize = mips_optimize;
6706 /* Itbl support may require additional care here. */
6707 relax_start (offset_expr.X_add_symbol);
6708 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6709 BFD_RELOC_LO16, AT);
6710 expr1.X_add_number += 4;
6711 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6712 BFD_RELOC_LO16, AT);
6714 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6715 BFD_RELOC_LO16, AT);
6716 offset_expr.X_add_number += 4;
6717 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6718 BFD_RELOC_LO16, AT);
6721 mips_optimize = hold_mips_optimize;
6723 else if (mips_pic == SVR4_PIC)
6727 /* If this is a reference to an external symbol, we want
6728 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6730 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6735 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6737 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6738 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6739 If there is a base register we add it to $at before the
6740 lwc1 instructions. If there is a constant we include it
6741 in the lwc1 instructions. */
6743 expr1.X_add_number = offset_expr.X_add_number;
6744 offset_expr.X_add_number = 0;
6745 if (expr1.X_add_number < -0x8000
6746 || expr1.X_add_number >= 0x8000 - 4)
6747 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6748 gpdelay = reg_needs_delay (mips_gp_register);
6749 relax_start (offset_expr.X_add_symbol);
6750 macro_build (&offset_expr, "lui", "t,u",
6751 AT, BFD_RELOC_MIPS_GOT_HI16);
6752 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6753 AT, AT, mips_gp_register);
6754 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6755 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6756 macro_build (NULL, "nop", "");
6758 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6759 /* Itbl support may require additional care here. */
6760 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6761 BFD_RELOC_LO16, AT);
6762 expr1.X_add_number += 4;
6764 /* Set mips_optimize to 2 to avoid inserting an undesired
6766 hold_mips_optimize = mips_optimize;
6768 /* Itbl support may require additional care here. */
6769 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
6770 BFD_RELOC_LO16, AT);
6771 mips_optimize = hold_mips_optimize;
6772 expr1.X_add_number -= 4;
6775 offset_expr.X_add_number = expr1.X_add_number;
6777 macro_build (NULL, "nop", "");
6778 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6779 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6780 macro_build (NULL, "nop", "");
6782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6783 /* Itbl support may require additional care here. */
6784 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6785 BFD_RELOC_LO16, AT);
6786 offset_expr.X_add_number += 4;
6788 /* Set mips_optimize to 2 to avoid inserting an undesired
6790 hold_mips_optimize = mips_optimize;
6792 /* Itbl support may require additional care here. */
6793 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6794 BFD_RELOC_LO16, AT);
6795 mips_optimize = hold_mips_optimize;
6798 else if (mips_pic == EMBEDDED_PIC)
6800 /* If there is no base register, we use
6801 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6802 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6803 If we have a base register, we use
6805 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6806 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6810 tempreg = mips_gp_register;
6815 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6816 AT, breg, mips_gp_register);
6821 /* Itbl support may require additional care here. */
6822 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6823 BFD_RELOC_GPREL16, tempreg);
6824 offset_expr.X_add_number += 4;
6825 /* Itbl support may require additional care here. */
6826 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6827 BFD_RELOC_GPREL16, tempreg);
6843 assert (HAVE_32BIT_ADDRESSES);
6844 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6845 offset_expr.X_add_number += 4;
6846 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6849 /* New code added to support COPZ instructions.
6850 This code builds table entries out of the macros in mip_opcodes.
6851 R4000 uses interlocks to handle coproc delays.
6852 Other chips (like the R3000) require nops to be inserted for delays.
6854 FIXME: Currently, we require that the user handle delays.
6855 In order to fill delay slots for non-interlocked chips,
6856 we must have a way to specify delays based on the coprocessor.
6857 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6858 What are the side-effects of the cop instruction?
6859 What cache support might we have and what are its effects?
6860 Both coprocessor & memory require delays. how long???
6861 What registers are read/set/modified?
6863 If an itbl is provided to interpret cop instructions,
6864 this knowledge can be encoded in the itbl spec. */
6878 /* For now we just do C (same as Cz). The parameter will be
6879 stored in insn_opcode by mips_ip. */
6880 macro_build (NULL, s, "C", ip->insn_opcode);
6884 move_register (dreg, sreg);
6887 #ifdef LOSING_COMPILER
6889 /* Try and see if this is a new itbl instruction.
6890 This code builds table entries out of the macros in mip_opcodes.
6891 FIXME: For now we just assemble the expression and pass it's
6892 value along as a 32-bit immediate.
6893 We may want to have the assembler assemble this value,
6894 so that we gain the assembler's knowledge of delay slots,
6896 Would it be more efficient to use mask (id) here? */
6897 if (itbl_have_entries
6898 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6900 s = ip->insn_mo->name;
6902 coproc = ITBL_DECODE_PNUM (immed_expr);;
6903 macro_build (&immed_expr, s, "C");
6910 as_warn (_("Macro used $at after \".set noat\""));
6914 macro2 (struct mips_cl_insn *ip)
6916 register int treg, sreg, dreg, breg;
6931 bfd_reloc_code_real_type r;
6933 treg = (ip->insn_opcode >> 16) & 0x1f;
6934 dreg = (ip->insn_opcode >> 11) & 0x1f;
6935 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
6936 mask = ip->insn_mo->mask;
6938 expr1.X_op = O_constant;
6939 expr1.X_op_symbol = NULL;
6940 expr1.X_add_symbol = NULL;
6941 expr1.X_add_number = 1;
6945 #endif /* LOSING_COMPILER */
6950 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6951 macro_build (NULL, "mflo", "d", dreg);
6957 /* The MIPS assembler some times generates shifts and adds. I'm
6958 not trying to be that fancy. GCC should do this for us
6960 load_register (AT, &imm_expr, dbl);
6961 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6962 macro_build (NULL, "mflo", "d", dreg);
6975 mips_emit_delays (TRUE);
6976 ++mips_opts.noreorder;
6977 mips_any_noreorder = 1;
6979 load_register (AT, &imm_expr, dbl);
6980 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6981 macro_build (NULL, "mflo", "d", dreg);
6982 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6983 macro_build (NULL, "mfhi", "d", AT);
6985 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6988 expr1.X_add_number = 8;
6989 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6990 macro_build (NULL, "nop", "", 0);
6991 macro_build (NULL, "break", "c", 6);
6993 --mips_opts.noreorder;
6994 macro_build (NULL, "mflo", "d", dreg);
7007 mips_emit_delays (TRUE);
7008 ++mips_opts.noreorder;
7009 mips_any_noreorder = 1;
7011 load_register (AT, &imm_expr, dbl);
7012 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7013 sreg, imm ? AT : treg);
7014 macro_build (NULL, "mfhi", "d", AT);
7015 macro_build (NULL, "mflo", "d", dreg);
7017 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7020 expr1.X_add_number = 8;
7021 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7022 macro_build (NULL, "nop", "", 0);
7023 macro_build (NULL, "break", "c", 6);
7025 --mips_opts.noreorder;
7029 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7041 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7042 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7047 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7048 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7049 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7050 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7054 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7066 macro_build (NULL, "negu", "d,w", tempreg, treg);
7067 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7072 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7073 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7074 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7075 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7083 if (imm_expr.X_op != O_constant)
7084 as_bad (_("Improper rotate count"));
7085 rot = imm_expr.X_add_number & 0x3f;
7086 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7088 rot = (64 - rot) & 0x3f;
7090 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7092 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7097 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7100 l = (rot < 0x20) ? "dsll" : "dsll32";
7101 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7103 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7104 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7105 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7113 if (imm_expr.X_op != O_constant)
7114 as_bad (_("Improper rotate count"));
7115 rot = imm_expr.X_add_number & 0x1f;
7116 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7118 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7123 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7126 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7127 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7128 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7133 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7135 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7138 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7139 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7140 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7141 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7145 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7147 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7150 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7151 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7152 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7153 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7161 if (imm_expr.X_op != O_constant)
7162 as_bad (_("Improper rotate count"));
7163 rot = imm_expr.X_add_number & 0x3f;
7164 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7167 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7169 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7174 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7177 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7178 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7180 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7181 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7182 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7190 if (imm_expr.X_op != O_constant)
7191 as_bad (_("Improper rotate count"));
7192 rot = imm_expr.X_add_number & 0x1f;
7193 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7195 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7200 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7203 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7204 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7205 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7210 if (mips_opts.arch == CPU_R4650)
7212 as_bad (_("opcode not supported on this processor"));
7215 assert (mips_opts.isa == ISA_MIPS1);
7216 /* Even on a big endian machine $fn comes before $fn+1. We have
7217 to adjust when storing to memory. */
7218 macro_build (&offset_expr, "swc1", "T,o(b)",
7219 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7220 offset_expr.X_add_number += 4;
7221 macro_build (&offset_expr, "swc1", "T,o(b)",
7222 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7227 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7229 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7232 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7233 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7238 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7240 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7245 as_warn (_("Instruction %s: result is always false"),
7247 move_register (dreg, 0);
7250 if (imm_expr.X_op == O_constant
7251 && imm_expr.X_add_number >= 0
7252 && imm_expr.X_add_number < 0x10000)
7254 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7257 else if (imm_expr.X_op == O_constant
7258 && imm_expr.X_add_number > -0x8000
7259 && imm_expr.X_add_number < 0)
7261 imm_expr.X_add_number = -imm_expr.X_add_number;
7262 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7263 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7268 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7269 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7272 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7277 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7283 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7284 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7287 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7289 if (imm_expr.X_op == O_constant
7290 && imm_expr.X_add_number >= -0x8000
7291 && imm_expr.X_add_number < 0x8000)
7293 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7294 dreg, sreg, BFD_RELOC_LO16);
7299 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7300 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7304 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7309 case M_SGT: /* sreg > treg <==> treg < sreg */
7315 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7318 case M_SGT_I: /* sreg > I <==> I < sreg */
7324 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7325 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7328 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7334 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7335 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7338 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7344 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7345 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7346 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7350 if (imm_expr.X_op == O_constant
7351 && imm_expr.X_add_number >= -0x8000
7352 && imm_expr.X_add_number < 0x8000)
7354 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7357 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7358 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7362 if (imm_expr.X_op == O_constant
7363 && imm_expr.X_add_number >= -0x8000
7364 && imm_expr.X_add_number < 0x8000)
7366 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7370 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7371 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7376 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7378 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7381 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7382 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7387 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7389 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7394 as_warn (_("Instruction %s: result is always true"),
7396 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7397 dreg, 0, BFD_RELOC_LO16);
7400 if (imm_expr.X_op == O_constant
7401 && imm_expr.X_add_number >= 0
7402 && imm_expr.X_add_number < 0x10000)
7404 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7407 else if (imm_expr.X_op == O_constant
7408 && imm_expr.X_add_number > -0x8000
7409 && imm_expr.X_add_number < 0)
7411 imm_expr.X_add_number = -imm_expr.X_add_number;
7412 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7413 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7418 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7419 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7422 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7430 if (imm_expr.X_op == O_constant
7431 && imm_expr.X_add_number > -0x8000
7432 && imm_expr.X_add_number <= 0x8000)
7434 imm_expr.X_add_number = -imm_expr.X_add_number;
7435 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7436 dreg, sreg, BFD_RELOC_LO16);
7439 load_register (AT, &imm_expr, dbl);
7440 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7446 if (imm_expr.X_op == O_constant
7447 && imm_expr.X_add_number > -0x8000
7448 && imm_expr.X_add_number <= 0x8000)
7450 imm_expr.X_add_number = -imm_expr.X_add_number;
7451 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7452 dreg, sreg, BFD_RELOC_LO16);
7455 load_register (AT, &imm_expr, dbl);
7456 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7477 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7478 macro_build (NULL, s, "s,t", sreg, AT);
7483 assert (mips_opts.isa == ISA_MIPS1);
7484 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7485 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7488 * Is the double cfc1 instruction a bug in the mips assembler;
7489 * or is there a reason for it?
7491 mips_emit_delays (TRUE);
7492 ++mips_opts.noreorder;
7493 mips_any_noreorder = 1;
7494 macro_build (NULL, "cfc1", "t,G", treg, RA);
7495 macro_build (NULL, "cfc1", "t,G", treg, RA);
7496 macro_build (NULL, "nop", "");
7497 expr1.X_add_number = 3;
7498 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7499 expr1.X_add_number = 2;
7500 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7501 macro_build (NULL, "ctc1", "t,G", AT, RA);
7502 macro_build (NULL, "nop", "");
7503 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7505 macro_build (NULL, "ctc1", "t,G", treg, RA);
7506 macro_build (NULL, "nop", "");
7507 --mips_opts.noreorder;
7516 if (offset_expr.X_add_number >= 0x7fff)
7517 as_bad (_("operand overflow"));
7518 if (! target_big_endian)
7519 ++offset_expr.X_add_number;
7520 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7521 if (! target_big_endian)
7522 --offset_expr.X_add_number;
7524 ++offset_expr.X_add_number;
7525 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7526 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7527 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7540 if (offset_expr.X_add_number >= 0x8000 - off)
7541 as_bad (_("operand overflow"));
7546 if (! target_big_endian)
7547 offset_expr.X_add_number += off;
7548 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7549 if (! target_big_endian)
7550 offset_expr.X_add_number -= off;
7552 offset_expr.X_add_number += off;
7553 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7555 /* If necessary, move the result in tempreg the final destination. */
7556 if (treg == tempreg)
7558 /* Protect second load's delay slot. */
7559 if (!gpr_interlocks)
7560 macro_build (NULL, "nop", "");
7561 move_register (treg, tempreg);
7575 load_address (AT, &offset_expr, &used_at);
7577 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7578 if (! target_big_endian)
7579 expr1.X_add_number = off;
7581 expr1.X_add_number = 0;
7582 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7583 if (! target_big_endian)
7584 expr1.X_add_number = 0;
7586 expr1.X_add_number = off;
7587 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7593 load_address (AT, &offset_expr, &used_at);
7595 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7596 if (target_big_endian)
7597 expr1.X_add_number = 0;
7598 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7599 treg, BFD_RELOC_LO16, AT);
7600 if (target_big_endian)
7601 expr1.X_add_number = 1;
7603 expr1.X_add_number = 0;
7604 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7605 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7606 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7610 if (offset_expr.X_add_number >= 0x7fff)
7611 as_bad (_("operand overflow"));
7612 if (target_big_endian)
7613 ++offset_expr.X_add_number;
7614 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7615 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7616 if (target_big_endian)
7617 --offset_expr.X_add_number;
7619 ++offset_expr.X_add_number;
7620 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
7633 if (offset_expr.X_add_number >= 0x8000 - off)
7634 as_bad (_("operand overflow"));
7635 if (! target_big_endian)
7636 offset_expr.X_add_number += off;
7637 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7638 if (! target_big_endian)
7639 offset_expr.X_add_number -= off;
7641 offset_expr.X_add_number += off;
7642 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7656 load_address (AT, &offset_expr, &used_at);
7658 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7659 if (! target_big_endian)
7660 expr1.X_add_number = off;
7662 expr1.X_add_number = 0;
7663 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7664 if (! target_big_endian)
7665 expr1.X_add_number = 0;
7667 expr1.X_add_number = off;
7668 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7673 load_address (AT, &offset_expr, &used_at);
7675 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7676 if (! target_big_endian)
7677 expr1.X_add_number = 0;
7678 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7679 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
7680 if (! target_big_endian)
7681 expr1.X_add_number = 1;
7683 expr1.X_add_number = 0;
7684 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7685 if (! target_big_endian)
7686 expr1.X_add_number = 0;
7688 expr1.X_add_number = 1;
7689 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7690 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7691 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7695 /* FIXME: Check if this is one of the itbl macros, since they
7696 are added dynamically. */
7697 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7701 as_warn (_("Macro used $at after \".set noat\""));
7704 /* Implement macros in mips16 mode. */
7707 mips16_macro (struct mips_cl_insn *ip)
7710 int xreg, yreg, zreg, tmp;
7713 const char *s, *s2, *s3;
7715 mask = ip->insn_mo->mask;
7717 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7718 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7719 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7721 expr1.X_op = O_constant;
7722 expr1.X_op_symbol = NULL;
7723 expr1.X_add_symbol = NULL;
7724 expr1.X_add_number = 1;
7743 mips_emit_delays (TRUE);
7744 ++mips_opts.noreorder;
7745 mips_any_noreorder = 1;
7746 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7747 expr1.X_add_number = 2;
7748 macro_build (&expr1, "bnez", "x,p", yreg);
7749 macro_build (NULL, "break", "6", 7);
7751 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7752 since that causes an overflow. We should do that as well,
7753 but I don't see how to do the comparisons without a temporary
7755 --mips_opts.noreorder;
7756 macro_build (NULL, s, "x", zreg);
7775 mips_emit_delays (TRUE);
7776 ++mips_opts.noreorder;
7777 mips_any_noreorder = 1;
7778 macro_build (NULL, s, "0,x,y", xreg, yreg);
7779 expr1.X_add_number = 2;
7780 macro_build (&expr1, "bnez", "x,p", yreg);
7781 macro_build (NULL, "break", "6", 7);
7782 --mips_opts.noreorder;
7783 macro_build (NULL, s2, "x", zreg);
7789 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7790 macro_build (NULL, "mflo", "x", zreg);
7798 if (imm_expr.X_op != O_constant)
7799 as_bad (_("Unsupported large constant"));
7800 imm_expr.X_add_number = -imm_expr.X_add_number;
7801 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
7805 if (imm_expr.X_op != O_constant)
7806 as_bad (_("Unsupported large constant"));
7807 imm_expr.X_add_number = -imm_expr.X_add_number;
7808 macro_build (&imm_expr, "addiu", "x,k", xreg);
7812 if (imm_expr.X_op != O_constant)
7813 as_bad (_("Unsupported large constant"));
7814 imm_expr.X_add_number = -imm_expr.X_add_number;
7815 macro_build (&imm_expr, "daddiu", "y,j", yreg);
7837 goto do_reverse_branch;
7841 goto do_reverse_branch;
7853 goto do_reverse_branch;
7864 macro_build (NULL, s, "x,y", xreg, yreg);
7865 macro_build (&offset_expr, s2, "p");
7892 goto do_addone_branch_i;
7897 goto do_addone_branch_i;
7912 goto do_addone_branch_i;
7919 if (imm_expr.X_op != O_constant)
7920 as_bad (_("Unsupported large constant"));
7921 ++imm_expr.X_add_number;
7924 macro_build (&imm_expr, s, s3, xreg);
7925 macro_build (&offset_expr, s2, "p");
7929 expr1.X_add_number = 0;
7930 macro_build (&expr1, "slti", "x,8", yreg);
7932 move_register (xreg, yreg);
7933 expr1.X_add_number = 2;
7934 macro_build (&expr1, "bteqz", "p");
7935 macro_build (NULL, "neg", "x,w", xreg, xreg);
7939 /* For consistency checking, verify that all bits are specified either
7940 by the match/mask part of the instruction definition, or by the
7943 validate_mips_insn (const struct mips_opcode *opc)
7945 const char *p = opc->args;
7947 unsigned long used_bits = opc->mask;
7949 if ((used_bits & opc->match) != opc->match)
7951 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7952 opc->name, opc->args);
7955 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7965 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7966 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7967 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7968 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7969 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7970 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7971 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7972 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7973 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7976 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7977 c, opc->name, opc->args);
7981 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7982 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7984 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
7985 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
7986 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
7987 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7989 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7990 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7992 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
7993 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
7995 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
7996 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
7997 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
7998 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
7999 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8000 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8001 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8002 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8003 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8004 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8005 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8006 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8007 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8008 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8009 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8010 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8011 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8013 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8014 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8015 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8016 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8018 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8019 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8020 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8021 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8022 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8023 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8024 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8025 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8026 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8029 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8030 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8031 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8032 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8033 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8037 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8038 c, opc->name, opc->args);
8042 if (used_bits != 0xffffffff)
8044 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8045 ~used_bits & 0xffffffff, opc->name, opc->args);
8051 /* This routine assembles an instruction into its binary format. As a
8052 side effect, it sets one of the global variables imm_reloc or
8053 offset_reloc to the type of relocation to do if one of the operands
8054 is an address expression. */
8057 mips_ip (char *str, struct mips_cl_insn *ip)
8062 struct mips_opcode *insn;
8065 unsigned int lastregno = 0;
8066 unsigned int lastpos = 0;
8067 unsigned int limlo, limhi;
8073 /* If the instruction contains a '.', we first try to match an instruction
8074 including the '.'. Then we try again without the '.'. */
8076 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8079 /* If we stopped on whitespace, then replace the whitespace with null for
8080 the call to hash_find. Save the character we replaced just in case we
8081 have to re-parse the instruction. */
8088 insn = (struct mips_opcode *) hash_find (op_hash, str);
8090 /* If we didn't find the instruction in the opcode table, try again, but
8091 this time with just the instruction up to, but not including the
8095 /* Restore the character we overwrite above (if any). */
8099 /* Scan up to the first '.' or whitespace. */
8101 *s != '\0' && *s != '.' && !ISSPACE (*s);
8105 /* If we did not find a '.', then we can quit now. */
8108 insn_error = "unrecognized opcode";
8112 /* Lookup the instruction in the hash table. */
8114 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8116 insn_error = "unrecognized opcode";
8126 assert (strcmp (insn->name, str) == 0);
8128 if (OPCODE_IS_MEMBER (insn,
8130 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8131 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8132 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8138 if (insn->pinfo != INSN_MACRO)
8140 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8146 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8147 && strcmp (insn->name, insn[1].name) == 0)
8156 static char buf[100];
8158 _("opcode not supported on this processor: %s (%s)"),
8159 mips_cpu_info_from_arch (mips_opts.arch)->name,
8160 mips_cpu_info_from_isa (mips_opts.isa)->name);
8170 ip->insn_opcode = insn->match;
8172 for (args = insn->args;; ++args)
8176 s += strspn (s, " \t");
8180 case '\0': /* end of args */
8193 ip->insn_opcode |= lastregno << OP_SH_RS;
8197 ip->insn_opcode |= lastregno << OP_SH_RT;
8201 ip->insn_opcode |= lastregno << OP_SH_FT;
8205 ip->insn_opcode |= lastregno << OP_SH_FS;
8211 /* Handle optional base register.
8212 Either the base register is omitted or
8213 we must have a left paren. */
8214 /* This is dependent on the next operand specifier
8215 is a base register specification. */
8216 assert (args[1] == 'b' || args[1] == '5'
8217 || args[1] == '-' || args[1] == '4');
8221 case ')': /* these must match exactly */
8228 case '+': /* Opcode extension character. */
8231 case 'A': /* ins/ext position, becomes LSB. */
8240 my_getExpression (&imm_expr, s);
8241 check_absolute_expr (ip, &imm_expr);
8242 if ((unsigned long) imm_expr.X_add_number < limlo
8243 || (unsigned long) imm_expr.X_add_number > limhi)
8245 as_bad (_("Improper position (%lu)"),
8246 (unsigned long) imm_expr.X_add_number);
8247 imm_expr.X_add_number = limlo;
8249 lastpos = imm_expr.X_add_number;
8250 ip->insn_opcode |= (imm_expr.X_add_number
8251 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8252 imm_expr.X_op = O_absent;
8256 case 'B': /* ins size, becomes MSB. */
8265 my_getExpression (&imm_expr, s);
8266 check_absolute_expr (ip, &imm_expr);
8267 /* Check for negative input so that small negative numbers
8268 will not succeed incorrectly. The checks against
8269 (pos+size) transitively check "size" itself,
8270 assuming that "pos" is reasonable. */
8271 if ((long) imm_expr.X_add_number < 0
8272 || ((unsigned long) imm_expr.X_add_number
8274 || ((unsigned long) imm_expr.X_add_number
8277 as_bad (_("Improper insert size (%lu, position %lu)"),
8278 (unsigned long) imm_expr.X_add_number,
8279 (unsigned long) lastpos);
8280 imm_expr.X_add_number = limlo - lastpos;
8282 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8283 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8284 imm_expr.X_op = O_absent;
8288 case 'C': /* ext size, becomes MSBD. */
8301 my_getExpression (&imm_expr, s);
8302 check_absolute_expr (ip, &imm_expr);
8303 /* Check for negative input so that small negative numbers
8304 will not succeed incorrectly. The checks against
8305 (pos+size) transitively check "size" itself,
8306 assuming that "pos" is reasonable. */
8307 if ((long) imm_expr.X_add_number < 0
8308 || ((unsigned long) imm_expr.X_add_number
8310 || ((unsigned long) imm_expr.X_add_number
8313 as_bad (_("Improper extract size (%lu, position %lu)"),
8314 (unsigned long) imm_expr.X_add_number,
8315 (unsigned long) lastpos);
8316 imm_expr.X_add_number = limlo - lastpos;
8318 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8319 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8320 imm_expr.X_op = O_absent;
8325 /* +D is for disassembly only; never match. */
8329 /* "+I" is like "I", except that imm2_expr is used. */
8330 my_getExpression (&imm2_expr, s);
8331 if (imm2_expr.X_op != O_big
8332 && imm2_expr.X_op != O_constant)
8333 insn_error = _("absolute expression required");
8334 normalize_constant_expr (&imm2_expr);
8339 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8340 *args, insn->name, insn->args);
8341 /* Further processing is fruitless. */
8346 case '<': /* must be at least one digit */
8348 * According to the manual, if the shift amount is greater
8349 * than 31 or less than 0, then the shift amount should be
8350 * mod 32. In reality the mips assembler issues an error.
8351 * We issue a warning and mask out all but the low 5 bits.
8353 my_getExpression (&imm_expr, s);
8354 check_absolute_expr (ip, &imm_expr);
8355 if ((unsigned long) imm_expr.X_add_number > 31)
8357 as_warn (_("Improper shift amount (%lu)"),
8358 (unsigned long) imm_expr.X_add_number);
8359 imm_expr.X_add_number &= OP_MASK_SHAMT;
8361 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8362 imm_expr.X_op = O_absent;
8366 case '>': /* shift amount minus 32 */
8367 my_getExpression (&imm_expr, s);
8368 check_absolute_expr (ip, &imm_expr);
8369 if ((unsigned long) imm_expr.X_add_number < 32
8370 || (unsigned long) imm_expr.X_add_number > 63)
8372 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8373 imm_expr.X_op = O_absent;
8377 case 'k': /* cache code */
8378 case 'h': /* prefx code */
8379 my_getExpression (&imm_expr, s);
8380 check_absolute_expr (ip, &imm_expr);
8381 if ((unsigned long) imm_expr.X_add_number > 31)
8383 as_warn (_("Invalid value for `%s' (%lu)"),
8385 (unsigned long) imm_expr.X_add_number);
8386 imm_expr.X_add_number &= 0x1f;
8389 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8391 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8392 imm_expr.X_op = O_absent;
8396 case 'c': /* break code */
8397 my_getExpression (&imm_expr, s);
8398 check_absolute_expr (ip, &imm_expr);
8399 if ((unsigned long) imm_expr.X_add_number > 1023)
8401 as_warn (_("Illegal break code (%lu)"),
8402 (unsigned long) imm_expr.X_add_number);
8403 imm_expr.X_add_number &= OP_MASK_CODE;
8405 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8406 imm_expr.X_op = O_absent;
8410 case 'q': /* lower break code */
8411 my_getExpression (&imm_expr, s);
8412 check_absolute_expr (ip, &imm_expr);
8413 if ((unsigned long) imm_expr.X_add_number > 1023)
8415 as_warn (_("Illegal lower break code (%lu)"),
8416 (unsigned long) imm_expr.X_add_number);
8417 imm_expr.X_add_number &= OP_MASK_CODE2;
8419 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8420 imm_expr.X_op = O_absent;
8424 case 'B': /* 20-bit syscall/break code. */
8425 my_getExpression (&imm_expr, s);
8426 check_absolute_expr (ip, &imm_expr);
8427 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8428 as_warn (_("Illegal 20-bit code (%lu)"),
8429 (unsigned long) imm_expr.X_add_number);
8430 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8431 imm_expr.X_op = O_absent;
8435 case 'C': /* Coprocessor code */
8436 my_getExpression (&imm_expr, s);
8437 check_absolute_expr (ip, &imm_expr);
8438 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
8440 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8441 (unsigned long) imm_expr.X_add_number);
8442 imm_expr.X_add_number &= ((1 << 25) - 1);
8444 ip->insn_opcode |= imm_expr.X_add_number;
8445 imm_expr.X_op = O_absent;
8449 case 'J': /* 19-bit wait code. */
8450 my_getExpression (&imm_expr, s);
8451 check_absolute_expr (ip, &imm_expr);
8452 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8453 as_warn (_("Illegal 19-bit code (%lu)"),
8454 (unsigned long) imm_expr.X_add_number);
8455 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8456 imm_expr.X_op = O_absent;
8460 case 'P': /* Performance register */
8461 my_getExpression (&imm_expr, s);
8462 check_absolute_expr (ip, &imm_expr);
8463 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8465 as_warn (_("Invalid performance register (%lu)"),
8466 (unsigned long) imm_expr.X_add_number);
8467 imm_expr.X_add_number &= OP_MASK_PERFREG;
8469 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8470 imm_expr.X_op = O_absent;
8474 case 'b': /* base register */
8475 case 'd': /* destination register */
8476 case 's': /* source register */
8477 case 't': /* target register */
8478 case 'r': /* both target and source */
8479 case 'v': /* both dest and source */
8480 case 'w': /* both dest and target */
8481 case 'E': /* coprocessor target register */
8482 case 'G': /* coprocessor destination register */
8483 case 'K': /* 'rdhwr' destination register */
8484 case 'x': /* ignore register name */
8485 case 'z': /* must be zero register */
8486 case 'U': /* destination register (clo/clz). */
8501 while (ISDIGIT (*s));
8503 as_bad (_("Invalid register number (%d)"), regno);
8505 else if (*args == 'E' || *args == 'G' || *args == 'K')
8509 if (s[1] == 'r' && s[2] == 'a')
8514 else if (s[1] == 'f' && s[2] == 'p')
8519 else if (s[1] == 's' && s[2] == 'p')
8524 else if (s[1] == 'g' && s[2] == 'p')
8529 else if (s[1] == 'a' && s[2] == 't')
8534 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8539 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8544 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8549 else if (itbl_have_entries)
8554 p = s + 1; /* advance past '$' */
8555 n = itbl_get_field (&p); /* n is name */
8557 /* See if this is a register defined in an
8559 if (itbl_get_reg_val (n, &r))
8561 /* Get_field advances to the start of
8562 the next field, so we need to back
8563 rack to the end of the last field. */
8567 s = strchr (s, '\0');
8581 as_warn (_("Used $at without \".set noat\""));
8587 if (c == 'r' || c == 'v' || c == 'w')
8594 /* 'z' only matches $0. */
8595 if (c == 'z' && regno != 0)
8598 /* Now that we have assembled one operand, we use the args string
8599 * to figure out where it goes in the instruction. */
8606 ip->insn_opcode |= regno << OP_SH_RS;
8611 ip->insn_opcode |= regno << OP_SH_RD;
8614 ip->insn_opcode |= regno << OP_SH_RD;
8615 ip->insn_opcode |= regno << OP_SH_RT;
8620 ip->insn_opcode |= regno << OP_SH_RT;
8623 /* This case exists because on the r3000 trunc
8624 expands into a macro which requires a gp
8625 register. On the r6000 or r4000 it is
8626 assembled into a single instruction which
8627 ignores the register. Thus the insn version
8628 is MIPS_ISA2 and uses 'x', and the macro
8629 version is MIPS_ISA1 and uses 't'. */
8632 /* This case is for the div instruction, which
8633 acts differently if the destination argument
8634 is $0. This only matches $0, and is checked
8635 outside the switch. */
8638 /* Itbl operand; not yet implemented. FIXME ?? */
8640 /* What about all other operands like 'i', which
8641 can be specified in the opcode table? */
8651 ip->insn_opcode |= lastregno << OP_SH_RS;
8654 ip->insn_opcode |= lastregno << OP_SH_RT;
8659 case 'O': /* MDMX alignment immediate constant. */
8660 my_getExpression (&imm_expr, s);
8661 check_absolute_expr (ip, &imm_expr);
8662 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8664 as_warn ("Improper align amount (%ld), using low bits",
8665 (long) imm_expr.X_add_number);
8666 imm_expr.X_add_number &= OP_MASK_ALN;
8668 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
8669 imm_expr.X_op = O_absent;
8673 case 'Q': /* MDMX vector, element sel, or const. */
8676 /* MDMX Immediate. */
8677 my_getExpression (&imm_expr, s);
8678 check_absolute_expr (ip, &imm_expr);
8679 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8681 as_warn (_("Invalid MDMX Immediate (%ld)"),
8682 (long) imm_expr.X_add_number);
8683 imm_expr.X_add_number &= OP_MASK_FT;
8685 imm_expr.X_add_number &= OP_MASK_FT;
8686 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8687 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8689 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8690 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8691 imm_expr.X_op = O_absent;
8695 /* Not MDMX Immediate. Fall through. */
8696 case 'X': /* MDMX destination register. */
8697 case 'Y': /* MDMX source register. */
8698 case 'Z': /* MDMX target register. */
8700 case 'D': /* floating point destination register */
8701 case 'S': /* floating point source register */
8702 case 'T': /* floating point target register */
8703 case 'R': /* floating point source register */
8707 /* Accept $fN for FP and MDMX register numbers, and in
8708 addition accept $vN for MDMX register numbers. */
8709 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8710 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8721 while (ISDIGIT (*s));
8724 as_bad (_("Invalid float register number (%d)"), regno);
8726 if ((regno & 1) != 0
8728 && ! (strcmp (str, "mtc1") == 0
8729 || strcmp (str, "mfc1") == 0
8730 || strcmp (str, "lwc1") == 0
8731 || strcmp (str, "swc1") == 0
8732 || strcmp (str, "l.s") == 0
8733 || strcmp (str, "s.s") == 0))
8734 as_warn (_("Float register should be even, was %d"),
8742 if (c == 'V' || c == 'W')
8753 ip->insn_opcode |= regno << OP_SH_FD;
8758 ip->insn_opcode |= regno << OP_SH_FS;
8761 /* This is like 'Z', but also needs to fix the MDMX
8762 vector/scalar select bits. Note that the
8763 scalar immediate case is handled above. */
8766 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
8767 int max_el = (is_qh ? 3 : 7);
8769 my_getExpression(&imm_expr, s);
8770 check_absolute_expr (ip, &imm_expr);
8772 if (imm_expr.X_add_number > max_el)
8773 as_bad(_("Bad element selector %ld"),
8774 (long) imm_expr.X_add_number);
8775 imm_expr.X_add_number &= max_el;
8776 ip->insn_opcode |= (imm_expr.X_add_number
8780 as_warn(_("Expecting ']' found '%s'"), s);
8786 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8787 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8790 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8797 ip->insn_opcode |= regno << OP_SH_FT;
8800 ip->insn_opcode |= regno << OP_SH_FR;
8810 ip->insn_opcode |= lastregno << OP_SH_FS;
8813 ip->insn_opcode |= lastregno << OP_SH_FT;
8819 my_getExpression (&imm_expr, s);
8820 if (imm_expr.X_op != O_big
8821 && imm_expr.X_op != O_constant)
8822 insn_error = _("absolute expression required");
8823 normalize_constant_expr (&imm_expr);
8828 my_getExpression (&offset_expr, s);
8829 *imm_reloc = BFD_RELOC_32;
8842 unsigned char temp[8];
8844 unsigned int length;
8849 /* These only appear as the last operand in an
8850 instruction, and every instruction that accepts
8851 them in any variant accepts them in all variants.
8852 This means we don't have to worry about backing out
8853 any changes if the instruction does not match.
8855 The difference between them is the size of the
8856 floating point constant and where it goes. For 'F'
8857 and 'L' the constant is 64 bits; for 'f' and 'l' it
8858 is 32 bits. Where the constant is placed is based
8859 on how the MIPS assembler does things:
8862 f -- immediate value
8865 The .lit4 and .lit8 sections are only used if
8866 permitted by the -G argument.
8868 When generating embedded PIC code, we use the
8869 .lit8 section but not the .lit4 section (we can do
8870 .lit4 inline easily; we need to put .lit8
8871 somewhere in the data segment, and using .lit8
8872 permits the linker to eventually combine identical
8875 The code below needs to know whether the target register
8876 is 32 or 64 bits wide. It relies on the fact 'f' and
8877 'F' are used with GPR-based instructions and 'l' and
8878 'L' are used with FPR-based instructions. */
8880 f64 = *args == 'F' || *args == 'L';
8881 using_gprs = *args == 'F' || *args == 'f';
8883 save_in = input_line_pointer;
8884 input_line_pointer = s;
8885 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
8887 s = input_line_pointer;
8888 input_line_pointer = save_in;
8889 if (err != NULL && *err != '\0')
8891 as_bad (_("Bad floating point constant: %s"), err);
8892 memset (temp, '\0', sizeof temp);
8893 length = f64 ? 8 : 4;
8896 assert (length == (unsigned) (f64 ? 8 : 4));
8900 && (! USE_GLOBAL_POINTER_OPT
8901 || mips_pic == EMBEDDED_PIC
8902 || g_switch_value < 4
8903 || (temp[0] == 0 && temp[1] == 0)
8904 || (temp[2] == 0 && temp[3] == 0))))
8906 imm_expr.X_op = O_constant;
8907 if (! target_big_endian)
8908 imm_expr.X_add_number = bfd_getl32 (temp);
8910 imm_expr.X_add_number = bfd_getb32 (temp);
8913 && ! mips_disable_float_construction
8914 /* Constants can only be constructed in GPRs and
8915 copied to FPRs if the GPRs are at least as wide
8916 as the FPRs. Force the constant into memory if
8917 we are using 64-bit FPRs but the GPRs are only
8920 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
8921 && ((temp[0] == 0 && temp[1] == 0)
8922 || (temp[2] == 0 && temp[3] == 0))
8923 && ((temp[4] == 0 && temp[5] == 0)
8924 || (temp[6] == 0 && temp[7] == 0)))
8926 /* The value is simple enough to load with a couple of
8927 instructions. If using 32-bit registers, set
8928 imm_expr to the high order 32 bits and offset_expr to
8929 the low order 32 bits. Otherwise, set imm_expr to
8930 the entire 64 bit constant. */
8931 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
8933 imm_expr.X_op = O_constant;
8934 offset_expr.X_op = O_constant;
8935 if (! target_big_endian)
8937 imm_expr.X_add_number = bfd_getl32 (temp + 4);
8938 offset_expr.X_add_number = bfd_getl32 (temp);
8942 imm_expr.X_add_number = bfd_getb32 (temp);
8943 offset_expr.X_add_number = bfd_getb32 (temp + 4);
8945 if (offset_expr.X_add_number == 0)
8946 offset_expr.X_op = O_absent;
8948 else if (sizeof (imm_expr.X_add_number) > 4)
8950 imm_expr.X_op = O_constant;
8951 if (! target_big_endian)
8952 imm_expr.X_add_number = bfd_getl64 (temp);
8954 imm_expr.X_add_number = bfd_getb64 (temp);
8958 imm_expr.X_op = O_big;
8959 imm_expr.X_add_number = 4;
8960 if (! target_big_endian)
8962 generic_bignum[0] = bfd_getl16 (temp);
8963 generic_bignum[1] = bfd_getl16 (temp + 2);
8964 generic_bignum[2] = bfd_getl16 (temp + 4);
8965 generic_bignum[3] = bfd_getl16 (temp + 6);
8969 generic_bignum[0] = bfd_getb16 (temp + 6);
8970 generic_bignum[1] = bfd_getb16 (temp + 4);
8971 generic_bignum[2] = bfd_getb16 (temp + 2);
8972 generic_bignum[3] = bfd_getb16 (temp);
8978 const char *newname;
8981 /* Switch to the right section. */
8983 subseg = now_subseg;
8986 default: /* unused default case avoids warnings. */
8988 newname = RDATA_SECTION_NAME;
8989 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8990 || mips_pic == EMBEDDED_PIC)
8994 if (mips_pic == EMBEDDED_PIC)
8997 newname = RDATA_SECTION_NAME;
9000 assert (!USE_GLOBAL_POINTER_OPT
9001 || g_switch_value >= 4);
9005 new_seg = subseg_new (newname, (subsegT) 0);
9006 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9007 bfd_set_section_flags (stdoutput, new_seg,
9012 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9013 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9014 && strcmp (TARGET_OS, "elf") != 0)
9015 record_alignment (new_seg, 4);
9017 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9019 as_bad (_("Can't use floating point insn in this section"));
9021 /* Set the argument to the current address in the
9023 offset_expr.X_op = O_symbol;
9024 offset_expr.X_add_symbol =
9025 symbol_new ("L0\001", now_seg,
9026 (valueT) frag_now_fix (), frag_now);
9027 offset_expr.X_add_number = 0;
9029 /* Put the floating point number into the section. */
9030 p = frag_more ((int) length);
9031 memcpy (p, temp, length);
9033 /* Switch back to the original section. */
9034 subseg_set (seg, subseg);
9039 case 'i': /* 16 bit unsigned immediate */
9040 case 'j': /* 16 bit signed immediate */
9041 *imm_reloc = BFD_RELOC_LO16;
9042 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
9045 offsetT minval, maxval;
9047 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
9048 && strcmp (insn->name, insn[1].name) == 0);
9050 /* If the expression was written as an unsigned number,
9051 only treat it as signed if there are no more
9055 && sizeof (imm_expr.X_add_number) <= 4
9056 && imm_expr.X_op == O_constant
9057 && imm_expr.X_add_number < 0
9058 && imm_expr.X_unsigned
9062 /* For compatibility with older assemblers, we accept
9063 0x8000-0xffff as signed 16-bit numbers when only
9064 signed numbers are allowed. */
9066 minval = 0, maxval = 0xffff;
9068 minval = -0x8000, maxval = 0x7fff;
9070 minval = -0x8000, maxval = 0xffff;
9072 if (imm_expr.X_op != O_constant
9073 || imm_expr.X_add_number < minval
9074 || imm_expr.X_add_number > maxval)
9078 if (imm_expr.X_op == O_constant
9079 || imm_expr.X_op == O_big)
9080 as_bad (_("expression out of range"));
9086 case 'o': /* 16 bit offset */
9087 /* Check whether there is only a single bracketed expression
9088 left. If so, it must be the base register and the
9089 constant must be zero. */
9090 if (*s == '(' && strchr (s + 1, '(') == 0)
9092 offset_expr.X_op = O_constant;
9093 offset_expr.X_add_number = 0;
9097 /* If this value won't fit into a 16 bit offset, then go
9098 find a macro that will generate the 32 bit offset
9100 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
9101 && (offset_expr.X_op != O_constant
9102 || offset_expr.X_add_number >= 0x8000
9103 || offset_expr.X_add_number < -0x8000))
9109 case 'p': /* pc relative offset */
9110 *offset_reloc = BFD_RELOC_16_PCREL_S2;
9111 my_getExpression (&offset_expr, s);
9115 case 'u': /* upper 16 bits */
9116 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
9117 && imm_expr.X_op == O_constant
9118 && (imm_expr.X_add_number < 0
9119 || imm_expr.X_add_number >= 0x10000))
9120 as_bad (_("lui expression not in range 0..65535"));
9124 case 'a': /* 26 bit address */
9125 my_getExpression (&offset_expr, s);
9127 *offset_reloc = BFD_RELOC_MIPS_JMP;
9130 case 'N': /* 3 bit branch condition code */
9131 case 'M': /* 3 bit compare condition code */
9132 if (strncmp (s, "$fcc", 4) != 0)
9142 while (ISDIGIT (*s));
9144 as_bad (_("Invalid condition code register $fcc%d"), regno);
9145 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9146 || strcmp(str + strlen(str) - 5, "any2f") == 0
9147 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9148 && (regno & 1) != 0)
9149 as_warn(_("Condition code register should be even for %s, was %d"),
9151 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9152 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9153 && (regno & 3) != 0)
9154 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9157 ip->insn_opcode |= regno << OP_SH_BCC;
9159 ip->insn_opcode |= regno << OP_SH_CCC;
9163 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9174 while (ISDIGIT (*s));
9177 c = 8; /* Invalid sel value. */
9180 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9181 ip->insn_opcode |= c;
9185 /* Must be at least one digit. */
9186 my_getExpression (&imm_expr, s);
9187 check_absolute_expr (ip, &imm_expr);
9189 if ((unsigned long) imm_expr.X_add_number
9190 > (unsigned long) OP_MASK_VECBYTE)
9192 as_bad (_("bad byte vector index (%ld)"),
9193 (long) imm_expr.X_add_number);
9194 imm_expr.X_add_number = 0;
9197 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9198 imm_expr.X_op = O_absent;
9203 my_getExpression (&imm_expr, s);
9204 check_absolute_expr (ip, &imm_expr);
9206 if ((unsigned long) imm_expr.X_add_number
9207 > (unsigned long) OP_MASK_VECALIGN)
9209 as_bad (_("bad byte vector index (%ld)"),
9210 (long) imm_expr.X_add_number);
9211 imm_expr.X_add_number = 0;
9214 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9215 imm_expr.X_op = O_absent;
9220 as_bad (_("bad char = '%c'\n"), *args);
9225 /* Args don't match. */
9226 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
9227 !strcmp (insn->name, insn[1].name))
9231 insn_error = _("illegal operands");
9236 insn_error = _("illegal operands");
9241 /* This routine assembles an instruction into its binary format when
9242 assembling for the mips16. As a side effect, it sets one of the
9243 global variables imm_reloc or offset_reloc to the type of
9244 relocation to do if one of the operands is an address expression.
9245 It also sets mips16_small and mips16_ext if the user explicitly
9246 requested a small or extended instruction. */
9249 mips16_ip (char *str, struct mips_cl_insn *ip)
9253 struct mips_opcode *insn;
9256 unsigned int lastregno = 0;
9261 mips16_small = FALSE;
9264 for (s = str; ISLOWER (*s); ++s)
9276 if (s[1] == 't' && s[2] == ' ')
9279 mips16_small = TRUE;
9283 else if (s[1] == 'e' && s[2] == ' ')
9292 insn_error = _("unknown opcode");
9296 if (mips_opts.noautoextend && ! mips16_ext)
9297 mips16_small = TRUE;
9299 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
9301 insn_error = _("unrecognized opcode");
9308 assert (strcmp (insn->name, str) == 0);
9311 ip->insn_opcode = insn->match;
9312 ip->use_extend = FALSE;
9313 imm_expr.X_op = O_absent;
9314 imm_reloc[0] = BFD_RELOC_UNUSED;
9315 imm_reloc[1] = BFD_RELOC_UNUSED;
9316 imm_reloc[2] = BFD_RELOC_UNUSED;
9317 imm2_expr.X_op = O_absent;
9318 offset_expr.X_op = O_absent;
9319 offset_reloc[0] = BFD_RELOC_UNUSED;
9320 offset_reloc[1] = BFD_RELOC_UNUSED;
9321 offset_reloc[2] = BFD_RELOC_UNUSED;
9322 for (args = insn->args; 1; ++args)
9329 /* In this switch statement we call break if we did not find
9330 a match, continue if we did find a match, or return if we
9339 /* Stuff the immediate value in now, if we can. */
9340 if (imm_expr.X_op == O_constant
9341 && *imm_reloc > BFD_RELOC_UNUSED
9342 && insn->pinfo != INSN_MACRO)
9344 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9345 imm_expr.X_add_number, TRUE, mips16_small,
9346 mips16_ext, &ip->insn_opcode,
9347 &ip->use_extend, &ip->extend);
9348 imm_expr.X_op = O_absent;
9349 *imm_reloc = BFD_RELOC_UNUSED;
9363 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9366 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9382 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9384 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9411 while (ISDIGIT (*s));
9414 as_bad (_("invalid register number (%d)"), regno);
9420 if (s[1] == 'r' && s[2] == 'a')
9425 else if (s[1] == 'f' && s[2] == 'p')
9430 else if (s[1] == 's' && s[2] == 'p')
9435 else if (s[1] == 'g' && s[2] == 'p')
9440 else if (s[1] == 'a' && s[2] == 't')
9445 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9450 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9455 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9468 if (c == 'v' || c == 'w')
9470 regno = mips16_to_32_reg_map[lastregno];
9484 regno = mips32_to_16_reg_map[regno];
9489 regno = ILLEGAL_REG;
9494 regno = ILLEGAL_REG;
9499 regno = ILLEGAL_REG;
9504 if (regno == AT && ! mips_opts.noat)
9505 as_warn (_("used $at without \".set noat\""));
9512 if (regno == ILLEGAL_REG)
9519 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9523 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9526 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9529 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9535 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9538 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9539 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9549 if (strncmp (s, "$pc", 3) == 0)
9573 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9575 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9576 and generate the appropriate reloc. If the text
9577 inside %gprel is not a symbol name with an
9578 optional offset, then we generate a normal reloc
9579 and will probably fail later. */
9580 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9581 if (imm_expr.X_op == O_symbol)
9584 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9586 ip->use_extend = TRUE;
9593 /* Just pick up a normal expression. */
9594 my_getExpression (&imm_expr, s);
9597 if (imm_expr.X_op == O_register)
9599 /* What we thought was an expression turned out to
9602 if (s[0] == '(' && args[1] == '(')
9604 /* It looks like the expression was omitted
9605 before a register indirection, which means
9606 that the expression is implicitly zero. We
9607 still set up imm_expr, so that we handle
9608 explicit extensions correctly. */
9609 imm_expr.X_op = O_constant;
9610 imm_expr.X_add_number = 0;
9611 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9618 /* We need to relax this instruction. */
9619 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9628 /* We use offset_reloc rather than imm_reloc for the PC
9629 relative operands. This lets macros with both
9630 immediate and address operands work correctly. */
9631 my_getExpression (&offset_expr, s);
9633 if (offset_expr.X_op == O_register)
9636 /* We need to relax this instruction. */
9637 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9641 case '6': /* break code */
9642 my_getExpression (&imm_expr, s);
9643 check_absolute_expr (ip, &imm_expr);
9644 if ((unsigned long) imm_expr.X_add_number > 63)
9646 as_warn (_("Invalid value for `%s' (%lu)"),
9648 (unsigned long) imm_expr.X_add_number);
9649 imm_expr.X_add_number &= 0x3f;
9651 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
9652 imm_expr.X_op = O_absent;
9656 case 'a': /* 26 bit address */
9657 my_getExpression (&offset_expr, s);
9659 *offset_reloc = BFD_RELOC_MIPS16_JMP;
9660 ip->insn_opcode <<= 16;
9663 case 'l': /* register list for entry macro */
9664 case 'L': /* register list for exit macro */
9674 int freg, reg1, reg2;
9676 while (*s == ' ' || *s == ',')
9680 as_bad (_("can't parse register list"));
9692 while (ISDIGIT (*s))
9714 as_bad (_("invalid register list"));
9719 while (ISDIGIT (*s))
9726 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
9731 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
9736 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
9737 mask |= (reg2 - 3) << 3;
9738 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
9739 mask |= (reg2 - 15) << 1;
9740 else if (reg1 == RA && reg2 == RA)
9744 as_bad (_("invalid register list"));
9748 /* The mask is filled in in the opcode table for the
9749 benefit of the disassembler. We remove it before
9750 applying the actual mask. */
9751 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9752 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9756 case 'e': /* extend code */
9757 my_getExpression (&imm_expr, s);
9758 check_absolute_expr (ip, &imm_expr);
9759 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9761 as_warn (_("Invalid value for `%s' (%lu)"),
9763 (unsigned long) imm_expr.X_add_number);
9764 imm_expr.X_add_number &= 0x7ff;
9766 ip->insn_opcode |= imm_expr.X_add_number;
9767 imm_expr.X_op = O_absent;
9777 /* Args don't match. */
9778 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
9779 strcmp (insn->name, insn[1].name) == 0)
9786 insn_error = _("illegal operands");
9792 /* This structure holds information we know about a mips16 immediate
9795 struct mips16_immed_operand
9797 /* The type code used in the argument string in the opcode table. */
9799 /* The number of bits in the short form of the opcode. */
9801 /* The number of bits in the extended form of the opcode. */
9803 /* The amount by which the short form is shifted when it is used;
9804 for example, the sw instruction has a shift count of 2. */
9806 /* The amount by which the short form is shifted when it is stored
9807 into the instruction code. */
9809 /* Non-zero if the short form is unsigned. */
9811 /* Non-zero if the extended form is unsigned. */
9813 /* Non-zero if the value is PC relative. */
9817 /* The mips16 immediate operand types. */
9819 static const struct mips16_immed_operand mips16_immed_operands[] =
9821 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9822 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9823 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
9824 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
9825 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
9826 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
9827 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
9828 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
9829 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
9830 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
9831 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
9832 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
9833 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
9834 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
9835 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
9836 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
9837 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9838 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
9839 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
9840 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
9841 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
9844 #define MIPS16_NUM_IMMED \
9845 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9847 /* Handle a mips16 instruction with an immediate value. This or's the
9848 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9849 whether an extended value is needed; if one is needed, it sets
9850 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9851 If SMALL is true, an unextended opcode was explicitly requested.
9852 If EXT is true, an extended opcode was explicitly requested. If
9853 WARN is true, warn if EXT does not match reality. */
9856 mips16_immed (char *file, unsigned int line, int type, offsetT val,
9857 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
9858 unsigned long *insn, bfd_boolean *use_extend,
9859 unsigned short *extend)
9861 register const struct mips16_immed_operand *op;
9862 int mintiny, maxtiny;
9863 bfd_boolean needext;
9865 op = mips16_immed_operands;
9866 while (op->type != type)
9869 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
9874 if (type == '<' || type == '>' || type == '[' || type == ']')
9877 maxtiny = 1 << op->nbits;
9882 maxtiny = (1 << op->nbits) - 1;
9887 mintiny = - (1 << (op->nbits - 1));
9888 maxtiny = (1 << (op->nbits - 1)) - 1;
9891 /* Branch offsets have an implicit 0 in the lowest bit. */
9892 if (type == 'p' || type == 'q')
9895 if ((val & ((1 << op->shift) - 1)) != 0
9896 || val < (mintiny << op->shift)
9897 || val > (maxtiny << op->shift))
9902 if (warn && ext && ! needext)
9903 as_warn_where (file, line,
9904 _("extended operand requested but not required"));
9905 if (small && needext)
9906 as_bad_where (file, line, _("invalid unextended operand value"));
9908 if (small || (! ext && ! needext))
9912 *use_extend = FALSE;
9913 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
9914 insnval <<= op->op_shift;
9919 long minext, maxext;
9925 maxext = (1 << op->extbits) - 1;
9929 minext = - (1 << (op->extbits - 1));
9930 maxext = (1 << (op->extbits - 1)) - 1;
9932 if (val < minext || val > maxext)
9933 as_bad_where (file, line,
9934 _("operand value out of range for instruction"));
9937 if (op->extbits == 16)
9939 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
9942 else if (op->extbits == 15)
9944 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
9949 extval = ((val & 0x1f) << 6) | (val & 0x20);
9953 *extend = (unsigned short) extval;
9958 static const struct percent_op_match
9961 bfd_reloc_code_real_type reloc;
9964 {"%lo", BFD_RELOC_LO16},
9966 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9967 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9968 {"%call16", BFD_RELOC_MIPS_CALL16},
9969 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9970 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
9971 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
9972 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
9973 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
9974 {"%got", BFD_RELOC_MIPS_GOT16},
9975 {"%gp_rel", BFD_RELOC_GPREL16},
9976 {"%half", BFD_RELOC_16},
9977 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9978 {"%higher", BFD_RELOC_MIPS_HIGHER},
9979 {"%neg", BFD_RELOC_MIPS_SUB},
9981 {"%hi", BFD_RELOC_HI16_S}
9985 /* Return true if *STR points to a relocation operator. When returning true,
9986 move *STR over the operator and store its relocation code in *RELOC.
9987 Leave both *STR and *RELOC alone when returning false. */
9990 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
9994 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
9995 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
9997 *str += strlen (percent_op[i].str);
9998 *reloc = percent_op[i].reloc;
10000 /* Check whether the output BFD supports this relocation.
10001 If not, issue an error and fall back on something safe. */
10002 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10004 as_bad ("relocation %s isn't supported by the current ABI",
10005 percent_op[i].str);
10006 *reloc = BFD_RELOC_LO16;
10014 /* Parse string STR as a 16-bit relocatable operand. Store the
10015 expression in *EP and the relocations in the array starting
10016 at RELOC. Return the number of relocation operators used.
10018 On exit, EXPR_END points to the first character after the expression.
10019 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10022 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10025 bfd_reloc_code_real_type reversed_reloc[3];
10026 size_t reloc_index, i;
10027 int crux_depth, str_depth;
10030 /* Search for the start of the main expression, recoding relocations
10031 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10032 of the main expression and with CRUX_DEPTH containing the number
10033 of open brackets at that point. */
10040 crux_depth = str_depth;
10042 /* Skip over whitespace and brackets, keeping count of the number
10044 while (*str == ' ' || *str == '\t' || *str == '(')
10049 && reloc_index < (HAVE_NEWABI ? 3 : 1)
10050 && parse_relocation (&str, &reversed_reloc[reloc_index]));
10052 my_getExpression (ep, crux);
10055 /* Match every open bracket. */
10056 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
10060 if (crux_depth > 0)
10061 as_bad ("unclosed '('");
10065 if (reloc_index == 0)
10066 reloc[0] = BFD_RELOC_LO16;
10069 prev_reloc_op_frag = frag_now;
10070 for (i = 0; i < reloc_index; i++)
10071 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10074 return reloc_index;
10078 my_getExpression (expressionS *ep, char *str)
10083 save_in = input_line_pointer;
10084 input_line_pointer = str;
10086 expr_end = input_line_pointer;
10087 input_line_pointer = save_in;
10089 /* If we are in mips16 mode, and this is an expression based on `.',
10090 then we bump the value of the symbol by 1 since that is how other
10091 text symbols are handled. We don't bother to handle complex
10092 expressions, just `.' plus or minus a constant. */
10093 if (mips_opts.mips16
10094 && ep->X_op == O_symbol
10095 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
10096 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
10097 && symbol_get_frag (ep->X_add_symbol) == frag_now
10098 && symbol_constant_p (ep->X_add_symbol)
10099 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
10100 S_SET_VALUE (ep->X_add_symbol, val + 1);
10103 /* Turn a string in input_line_pointer into a floating point constant
10104 of type TYPE, and store the appropriate bytes in *LITP. The number
10105 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10106 returned, or NULL on OK. */
10109 md_atof (int type, char *litP, int *sizeP)
10112 LITTLENUM_TYPE words[4];
10128 return _("bad call to md_atof");
10131 t = atof_ieee (input_line_pointer, type, words);
10133 input_line_pointer = t;
10137 if (! target_big_endian)
10139 for (i = prec - 1; i >= 0; i--)
10141 md_number_to_chars (litP, words[i], 2);
10147 for (i = 0; i < prec; i++)
10149 md_number_to_chars (litP, words[i], 2);
10158 md_number_to_chars (char *buf, valueT val, int n)
10160 if (target_big_endian)
10161 number_to_chars_bigendian (buf, val, n);
10163 number_to_chars_littleendian (buf, val, n);
10167 static int support_64bit_objects(void)
10169 const char **list, **l;
10172 list = bfd_target_list ();
10173 for (l = list; *l != NULL; l++)
10175 /* This is traditional mips */
10176 if (strcmp (*l, "elf64-tradbigmips") == 0
10177 || strcmp (*l, "elf64-tradlittlemips") == 0)
10179 if (strcmp (*l, "elf64-bigmips") == 0
10180 || strcmp (*l, "elf64-littlemips") == 0)
10183 yes = (*l != NULL);
10187 #endif /* OBJ_ELF */
10189 const char *md_shortopts = "O::g::G:";
10191 struct option md_longopts[] =
10193 /* Options which specify architecture. */
10194 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10195 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10196 {"march", required_argument, NULL, OPTION_MARCH},
10197 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10198 {"mtune", required_argument, NULL, OPTION_MTUNE},
10199 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10200 {"mips0", no_argument, NULL, OPTION_MIPS1},
10201 {"mips1", no_argument, NULL, OPTION_MIPS1},
10202 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10203 {"mips2", no_argument, NULL, OPTION_MIPS2},
10204 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10205 {"mips3", no_argument, NULL, OPTION_MIPS3},
10206 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10207 {"mips4", no_argument, NULL, OPTION_MIPS4},
10208 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10209 {"mips5", no_argument, NULL, OPTION_MIPS5},
10210 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10211 {"mips32", no_argument, NULL, OPTION_MIPS32},
10212 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10213 {"mips64", no_argument, NULL, OPTION_MIPS64},
10214 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10215 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
10216 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10217 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
10219 /* Options which specify Application Specific Extensions (ASEs). */
10220 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10221 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10222 {"mips16", no_argument, NULL, OPTION_MIPS16},
10223 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10224 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
10225 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10226 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10227 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10228 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10229 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10230 {"mdmx", no_argument, NULL, OPTION_MDMX},
10231 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10232 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10234 /* Old-style architecture options. Don't add more of these. */
10235 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10236 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10237 {"m4650", no_argument, NULL, OPTION_M4650},
10238 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10239 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10240 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10241 {"m4010", no_argument, NULL, OPTION_M4010},
10242 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10243 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
10244 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10245 {"m4100", no_argument, NULL, OPTION_M4100},
10246 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10247 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
10248 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10249 {"m3900", no_argument, NULL, OPTION_M3900},
10250 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10251 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
10253 /* Options which enable bug fixes. */
10254 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10255 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10256 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10257 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10258 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10259 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10260 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10261 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10262 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10263 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10265 /* Miscellaneous options. */
10266 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10267 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10268 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10269 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10270 {"trap", no_argument, NULL, OPTION_TRAP},
10271 {"no-break", no_argument, NULL, OPTION_TRAP},
10272 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10273 {"break", no_argument, NULL, OPTION_BREAK},
10274 {"no-trap", no_argument, NULL, OPTION_BREAK},
10275 #define OPTION_EB (OPTION_MISC_BASE + 3)
10276 {"EB", no_argument, NULL, OPTION_EB},
10277 #define OPTION_EL (OPTION_MISC_BASE + 4)
10278 {"EL", no_argument, NULL, OPTION_EL},
10279 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10280 {"mfp32", no_argument, NULL, OPTION_FP32},
10281 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10282 {"mgp32", no_argument, NULL, OPTION_GP32},
10283 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10284 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10285 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10286 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10287 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10288 {"mfp64", no_argument, NULL, OPTION_FP64},
10289 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10290 {"mgp64", no_argument, NULL, OPTION_GP64},
10291 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10292 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10293 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10294 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10296 /* ELF-specific options. */
10298 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10299 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10300 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10301 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10302 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10303 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10304 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10305 {"xgot", no_argument, NULL, OPTION_XGOT},
10306 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10307 {"mabi", required_argument, NULL, OPTION_MABI},
10308 #define OPTION_32 (OPTION_ELF_BASE + 4)
10309 {"32", no_argument, NULL, OPTION_32},
10310 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10311 {"n32", no_argument, NULL, OPTION_N32},
10312 #define OPTION_64 (OPTION_ELF_BASE + 6)
10313 {"64", no_argument, NULL, OPTION_64},
10314 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10315 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10316 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10317 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10318 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10319 {"mpdr", no_argument, NULL, OPTION_PDR},
10320 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10321 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10322 #endif /* OBJ_ELF */
10324 {NULL, no_argument, NULL, 0}
10326 size_t md_longopts_size = sizeof (md_longopts);
10328 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10329 NEW_VALUE. Warn if another value was already specified. Note:
10330 we have to defer parsing the -march and -mtune arguments in order
10331 to handle 'from-abi' correctly, since the ABI might be specified
10332 in a later argument. */
10335 mips_set_option_string (const char **string_ptr, const char *new_value)
10337 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
10338 as_warn (_("A different %s was already specified, is now %s"),
10339 string_ptr == &mips_arch_string ? "-march" : "-mtune",
10342 *string_ptr = new_value;
10346 md_parse_option (int c, char *arg)
10350 case OPTION_CONSTRUCT_FLOATS:
10351 mips_disable_float_construction = 0;
10354 case OPTION_NO_CONSTRUCT_FLOATS:
10355 mips_disable_float_construction = 1;
10367 target_big_endian = 1;
10371 target_big_endian = 0;
10375 if (arg && arg[1] == '0')
10385 mips_debug = atoi (arg);
10386 /* When the MIPS assembler sees -g or -g2, it does not do
10387 optimizations which limit full symbolic debugging. We take
10388 that to be equivalent to -O0. */
10389 if (mips_debug == 2)
10394 file_mips_isa = ISA_MIPS1;
10398 file_mips_isa = ISA_MIPS2;
10402 file_mips_isa = ISA_MIPS3;
10406 file_mips_isa = ISA_MIPS4;
10410 file_mips_isa = ISA_MIPS5;
10413 case OPTION_MIPS32:
10414 file_mips_isa = ISA_MIPS32;
10417 case OPTION_MIPS32R2:
10418 file_mips_isa = ISA_MIPS32R2;
10421 case OPTION_MIPS64R2:
10422 file_mips_isa = ISA_MIPS64R2;
10425 case OPTION_MIPS64:
10426 file_mips_isa = ISA_MIPS64;
10430 mips_set_option_string (&mips_tune_string, arg);
10434 mips_set_option_string (&mips_arch_string, arg);
10438 mips_set_option_string (&mips_arch_string, "4650");
10439 mips_set_option_string (&mips_tune_string, "4650");
10442 case OPTION_NO_M4650:
10446 mips_set_option_string (&mips_arch_string, "4010");
10447 mips_set_option_string (&mips_tune_string, "4010");
10450 case OPTION_NO_M4010:
10454 mips_set_option_string (&mips_arch_string, "4100");
10455 mips_set_option_string (&mips_tune_string, "4100");
10458 case OPTION_NO_M4100:
10462 mips_set_option_string (&mips_arch_string, "3900");
10463 mips_set_option_string (&mips_tune_string, "3900");
10466 case OPTION_NO_M3900:
10470 mips_opts.ase_mdmx = 1;
10473 case OPTION_NO_MDMX:
10474 mips_opts.ase_mdmx = 0;
10477 case OPTION_MIPS16:
10478 mips_opts.mips16 = 1;
10479 mips_no_prev_insn (FALSE);
10482 case OPTION_NO_MIPS16:
10483 mips_opts.mips16 = 0;
10484 mips_no_prev_insn (FALSE);
10487 case OPTION_MIPS3D:
10488 mips_opts.ase_mips3d = 1;
10491 case OPTION_NO_MIPS3D:
10492 mips_opts.ase_mips3d = 0;
10495 case OPTION_MEMBEDDED_PIC:
10496 mips_pic = EMBEDDED_PIC;
10497 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10499 as_bad (_("-G may not be used with embedded PIC code"));
10502 g_switch_value = 0x7fffffff;
10505 case OPTION_FIX_VR4120:
10506 mips_fix_vr4120 = 1;
10509 case OPTION_NO_FIX_VR4120:
10510 mips_fix_vr4120 = 0;
10513 case OPTION_RELAX_BRANCH:
10514 mips_relax_branch = 1;
10517 case OPTION_NO_RELAX_BRANCH:
10518 mips_relax_branch = 0;
10522 /* When generating ELF code, we permit -KPIC and -call_shared to
10523 select SVR4_PIC, and -non_shared to select no PIC. This is
10524 intended to be compatible with Irix 5. */
10525 case OPTION_CALL_SHARED:
10526 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10528 as_bad (_("-call_shared is supported only for ELF format"));
10531 mips_pic = SVR4_PIC;
10532 mips_abicalls = TRUE;
10533 if (g_switch_seen && g_switch_value != 0)
10535 as_bad (_("-G may not be used with SVR4 PIC code"));
10538 g_switch_value = 0;
10541 case OPTION_NON_SHARED:
10542 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10544 as_bad (_("-non_shared is supported only for ELF format"));
10548 mips_abicalls = FALSE;
10551 /* The -xgot option tells the assembler to use 32 offsets when
10552 accessing the got in SVR4_PIC mode. It is for Irix
10557 #endif /* OBJ_ELF */
10560 if (! USE_GLOBAL_POINTER_OPT)
10562 as_bad (_("-G is not supported for this configuration"));
10565 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10567 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10571 g_switch_value = atoi (arg);
10576 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10579 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10581 as_bad (_("-32 is supported for ELF format only"));
10584 mips_abi = O32_ABI;
10588 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10590 as_bad (_("-n32 is supported for ELF format only"));
10593 mips_abi = N32_ABI;
10597 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10599 as_bad (_("-64 is supported for ELF format only"));
10602 mips_abi = N64_ABI;
10603 if (! support_64bit_objects())
10604 as_fatal (_("No compiled in support for 64 bit object file format"));
10606 #endif /* OBJ_ELF */
10609 file_mips_gp32 = 1;
10613 file_mips_gp32 = 0;
10617 file_mips_fp32 = 1;
10621 file_mips_fp32 = 0;
10626 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10628 as_bad (_("-mabi is supported for ELF format only"));
10631 if (strcmp (arg, "32") == 0)
10632 mips_abi = O32_ABI;
10633 else if (strcmp (arg, "o64") == 0)
10634 mips_abi = O64_ABI;
10635 else if (strcmp (arg, "n32") == 0)
10636 mips_abi = N32_ABI;
10637 else if (strcmp (arg, "64") == 0)
10639 mips_abi = N64_ABI;
10640 if (! support_64bit_objects())
10641 as_fatal (_("No compiled in support for 64 bit object file "
10644 else if (strcmp (arg, "eabi") == 0)
10645 mips_abi = EABI_ABI;
10648 as_fatal (_("invalid abi -mabi=%s"), arg);
10652 #endif /* OBJ_ELF */
10654 case OPTION_M7000_HILO_FIX:
10655 mips_7000_hilo_fix = TRUE;
10658 case OPTION_MNO_7000_HILO_FIX:
10659 mips_7000_hilo_fix = FALSE;
10663 case OPTION_MDEBUG:
10664 mips_flag_mdebug = TRUE;
10667 case OPTION_NO_MDEBUG:
10668 mips_flag_mdebug = FALSE;
10672 mips_flag_pdr = TRUE;
10675 case OPTION_NO_PDR:
10676 mips_flag_pdr = FALSE;
10678 #endif /* OBJ_ELF */
10687 /* Set up globals to generate code for the ISA or processor
10688 described by INFO. */
10691 mips_set_architecture (const struct mips_cpu_info *info)
10695 file_mips_arch = info->cpu;
10696 mips_opts.arch = info->cpu;
10697 mips_opts.isa = info->isa;
10702 /* Likewise for tuning. */
10705 mips_set_tune (const struct mips_cpu_info *info)
10708 mips_tune = info->cpu;
10713 mips_after_parse_args (void)
10715 const struct mips_cpu_info *arch_info = 0;
10716 const struct mips_cpu_info *tune_info = 0;
10718 /* GP relative stuff not working for PE */
10719 if (strncmp (TARGET_OS, "pe", 2) == 0
10720 && g_switch_value != 0)
10723 as_bad (_("-G not supported in this configuration."));
10724 g_switch_value = 0;
10727 if (mips_abi == NO_ABI)
10728 mips_abi = MIPS_DEFAULT_ABI;
10730 /* The following code determines the architecture and register size.
10731 Similar code was added to GCC 3.3 (see override_options() in
10732 config/mips/mips.c). The GAS and GCC code should be kept in sync
10733 as much as possible. */
10735 if (mips_arch_string != 0)
10736 arch_info = mips_parse_cpu ("-march", mips_arch_string);
10738 if (file_mips_isa != ISA_UNKNOWN)
10740 /* Handle -mipsN. At this point, file_mips_isa contains the
10741 ISA level specified by -mipsN, while arch_info->isa contains
10742 the -march selection (if any). */
10743 if (arch_info != 0)
10745 /* -march takes precedence over -mipsN, since it is more descriptive.
10746 There's no harm in specifying both as long as the ISA levels
10748 if (file_mips_isa != arch_info->isa)
10749 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10750 mips_cpu_info_from_isa (file_mips_isa)->name,
10751 mips_cpu_info_from_isa (arch_info->isa)->name);
10754 arch_info = mips_cpu_info_from_isa (file_mips_isa);
10757 if (arch_info == 0)
10758 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
10760 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
10761 as_bad ("-march=%s is not compatible with the selected ABI",
10764 mips_set_architecture (arch_info);
10766 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10767 if (mips_tune_string != 0)
10768 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
10770 if (tune_info == 0)
10771 mips_set_tune (arch_info);
10773 mips_set_tune (tune_info);
10775 if (file_mips_gp32 >= 0)
10777 /* The user specified the size of the integer registers. Make sure
10778 it agrees with the ABI and ISA. */
10779 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
10780 as_bad (_("-mgp64 used with a 32-bit processor"));
10781 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
10782 as_bad (_("-mgp32 used with a 64-bit ABI"));
10783 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
10784 as_bad (_("-mgp64 used with a 32-bit ABI"));
10788 /* Infer the integer register size from the ABI and processor.
10789 Restrict ourselves to 32-bit registers if that's all the
10790 processor has, or if the ABI cannot handle 64-bit registers. */
10791 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
10792 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
10795 /* ??? GAS treats single-float processors as though they had 64-bit
10796 float registers (although it complains when double-precision
10797 instructions are used). As things stand, saying they have 32-bit
10798 registers would lead to spurious "register must be even" messages.
10799 So here we assume float registers are always the same size as
10800 integer ones, unless the user says otherwise. */
10801 if (file_mips_fp32 < 0)
10802 file_mips_fp32 = file_mips_gp32;
10804 /* End of GCC-shared inference code. */
10806 /* This flag is set when we have a 64-bit capable CPU but use only
10807 32-bit wide registers. Note that EABI does not use it. */
10808 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
10809 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
10810 || mips_abi == O32_ABI))
10811 mips_32bitmode = 1;
10813 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
10814 as_bad (_("trap exception not supported at ISA 1"));
10816 /* If the selected architecture includes support for ASEs, enable
10817 generation of code for them. */
10818 if (mips_opts.mips16 == -1)
10819 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10820 if (mips_opts.ase_mips3d == -1)
10821 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10822 if (mips_opts.ase_mdmx == -1)
10823 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
10825 file_mips_isa = mips_opts.isa;
10826 file_ase_mips16 = mips_opts.mips16;
10827 file_ase_mips3d = mips_opts.ase_mips3d;
10828 file_ase_mdmx = mips_opts.ase_mdmx;
10829 mips_opts.gp32 = file_mips_gp32;
10830 mips_opts.fp32 = file_mips_fp32;
10832 if (mips_flag_mdebug < 0)
10834 #ifdef OBJ_MAYBE_ECOFF
10835 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10836 mips_flag_mdebug = 1;
10838 #endif /* OBJ_MAYBE_ECOFF */
10839 mips_flag_mdebug = 0;
10844 mips_init_after_args (void)
10846 /* initialize opcodes */
10847 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
10848 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
10852 md_pcrel_from (fixS *fixP)
10854 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
10855 switch (fixP->fx_r_type)
10857 case BFD_RELOC_16_PCREL_S2:
10858 case BFD_RELOC_MIPS_JMP:
10859 /* Return the address of the delay slot. */
10866 /* This is called before the symbol table is processed. In order to
10867 work with gcc when using mips-tfile, we must keep all local labels.
10868 However, in other cases, we want to discard them. If we were
10869 called with -g, but we didn't see any debugging information, it may
10870 mean that gcc is smuggling debugging information through to
10871 mips-tfile, in which case we must generate all local labels. */
10874 mips_frob_file_before_adjust (void)
10876 #ifndef NO_ECOFF_DEBUGGING
10877 if (ECOFF_DEBUGGING
10879 && ! ecoff_debugging_seen)
10880 flag_keep_locals = 1;
10884 /* Sort any unmatched HI16_S relocs so that they immediately precede
10885 the corresponding LO reloc. This is called before md_apply_fix3 and
10886 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10887 explicit use of the %hi modifier. */
10890 mips_frob_file (void)
10892 struct mips_hi_fixup *l;
10894 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10896 segment_info_type *seginfo;
10899 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10901 /* If a GOT16 relocation turns out to be against a global symbol,
10902 there isn't supposed to be a matching LO. */
10903 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10904 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10907 /* Check quickly whether the next fixup happens to be a matching %lo. */
10908 if (fixup_has_matching_lo_p (l->fixp))
10911 /* Look through the fixups for this segment for a matching %lo.
10912 When we find one, move the %hi just in front of it. We do
10913 this in two passes. In the first pass, we try to find a
10914 unique %lo. In the second pass, we permit multiple %hi
10915 relocs for a single %lo (this is a GNU extension). */
10916 seginfo = seg_info (l->seg);
10917 for (pass = 0; pass < 2; pass++)
10922 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10924 /* Check whether this is a %lo fixup which matches l->fixp. */
10925 if (f->fx_r_type == BFD_RELOC_LO16
10926 && f->fx_addsy == l->fixp->fx_addsy
10927 && f->fx_offset == l->fixp->fx_offset
10930 || !reloc_needs_lo_p (prev->fx_r_type)
10931 || !fixup_has_matching_lo_p (prev)))
10935 /* Move l->fixp before f. */
10936 for (pf = &seginfo->fix_root;
10938 pf = &(*pf)->fx_next)
10939 assert (*pf != NULL);
10941 *pf = l->fixp->fx_next;
10943 l->fixp->fx_next = f;
10945 seginfo->fix_root = l->fixp;
10947 prev->fx_next = l->fixp;
10958 #if 0 /* GCC code motion plus incomplete dead code elimination
10959 can leave a %hi without a %lo. */
10961 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10962 _("Unmatched %%hi reloc"));
10968 /* When generating embedded PIC code we need to use a special
10969 relocation to represent the difference of two symbols in the .text
10970 section (switch tables use a difference of this sort). See
10971 include/coff/mips.h for details. This macro checks whether this
10972 fixup requires the special reloc. */
10973 #define SWITCH_TABLE(fixp) \
10974 ((fixp)->fx_r_type == BFD_RELOC_32 \
10975 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10976 && (fixp)->fx_addsy != NULL \
10977 && (fixp)->fx_subsy != NULL \
10978 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10979 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10981 /* When generating embedded PIC code we must keep all PC relative
10982 relocations, in case the linker has to relax a call. We also need
10983 to keep relocations for switch table entries.
10985 We may have combined relocations without symbols in the N32/N64 ABI.
10986 We have to prevent gas from dropping them. */
10989 mips_force_relocation (fixS *fixp)
10991 if (generic_force_reloc (fixp))
10995 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10996 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10997 || fixp->fx_r_type == BFD_RELOC_HI16_S
10998 || fixp->fx_r_type == BFD_RELOC_LO16))
11001 return (mips_pic == EMBEDDED_PIC
11003 || SWITCH_TABLE (fixp)
11004 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11005 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11008 /* This hook is called before a fix is simplified. We don't really
11009 decide whether to skip a fix here. Rather, we turn global symbols
11010 used as branch targets into local symbols, such that they undergo
11011 simplification. We can only do this if the symbol is defined and
11012 it is in the same section as the branch. If this doesn't hold, we
11013 emit a better error message than just saying the relocation is not
11014 valid for the selected object format.
11016 FIXP is the fix-up we're going to try to simplify, SEG is the
11017 segment in which the fix up occurs. The return value should be
11018 non-zero to indicate the fix-up is valid for further
11019 simplifications. */
11022 mips_validate_fix (struct fix *fixP, asection *seg)
11024 /* There's a lot of discussion on whether it should be possible to
11025 use R_MIPS_PC16 to represent branch relocations. The outcome
11026 seems to be that it can, but gas/bfd are very broken in creating
11027 RELA relocations for this, so for now we only accept branches to
11028 symbols in the same section. Anything else is of dubious value,
11029 since there's no guarantee that at link time the symbol would be
11030 in range. Even for branches to local symbols this is arguably
11031 wrong, since it we assume the symbol is not going to be
11032 overridden, which should be possible per ELF library semantics,
11033 but then, there isn't a dynamic relocation that could be used to
11034 this effect, and the target would likely be out of range as well.
11036 Unfortunately, it seems that there is too much code out there
11037 that relies on branches to symbols that are global to be resolved
11038 as if they were local, like the IRIX tools do, so we do it as
11039 well, but with a warning so that people are reminded to fix their
11040 code. If we ever get back to using R_MIPS_PC16 for branch
11041 targets, this entire block should go away (and probably the
11042 whole function). */
11044 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11045 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11046 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11047 && mips_pic != EMBEDDED_PIC)
11048 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11051 if (! S_IS_DEFINED (fixP->fx_addsy))
11053 as_bad_where (fixP->fx_file, fixP->fx_line,
11054 _("Cannot branch to undefined symbol."));
11055 /* Avoid any further errors about this fixup. */
11058 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11060 as_bad_where (fixP->fx_file, fixP->fx_line,
11061 _("Cannot branch to symbol in another section."));
11064 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11066 symbolS *sym = fixP->fx_addsy;
11068 if (mips_pic == SVR4_PIC)
11069 as_warn_where (fixP->fx_file, fixP->fx_line,
11070 _("Pretending global symbol used as branch target is local."));
11072 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11073 S_GET_SEGMENT (sym),
11075 symbol_get_frag (sym));
11076 copy_symbol_attributes (fixP->fx_addsy, sym);
11077 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11078 assert (symbol_resolved_p (sym));
11079 symbol_mark_resolved (fixP->fx_addsy);
11086 /* Apply a fixup to the object file. */
11089 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11093 static int previous_fx_r_type = 0;
11094 reloc_howto_type *howto;
11096 /* We ignore generic BFD relocations we don't know about. */
11097 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11101 assert (fixP->fx_size == 4
11102 || fixP->fx_r_type == BFD_RELOC_16
11103 || fixP->fx_r_type == BFD_RELOC_64
11104 || fixP->fx_r_type == BFD_RELOC_CTOR
11105 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11106 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11107 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11109 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11111 /* We are not done if this is a composite relocation to set up gp. */
11112 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11113 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11114 || (fixP->fx_r_type == BFD_RELOC_64
11115 && (previous_fx_r_type == BFD_RELOC_GPREL32
11116 || previous_fx_r_type == BFD_RELOC_GPREL16))
11117 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11118 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11119 || fixP->fx_r_type == BFD_RELOC_LO16))))
11121 previous_fx_r_type = fixP->fx_r_type;
11123 switch (fixP->fx_r_type)
11125 case BFD_RELOC_MIPS_JMP:
11126 case BFD_RELOC_MIPS_SHIFT5:
11127 case BFD_RELOC_MIPS_SHIFT6:
11128 case BFD_RELOC_MIPS_GOT_DISP:
11129 case BFD_RELOC_MIPS_GOT_PAGE:
11130 case BFD_RELOC_MIPS_GOT_OFST:
11131 case BFD_RELOC_MIPS_SUB:
11132 case BFD_RELOC_MIPS_INSERT_A:
11133 case BFD_RELOC_MIPS_INSERT_B:
11134 case BFD_RELOC_MIPS_DELETE:
11135 case BFD_RELOC_MIPS_HIGHEST:
11136 case BFD_RELOC_MIPS_HIGHER:
11137 case BFD_RELOC_MIPS_SCN_DISP:
11138 case BFD_RELOC_MIPS_REL16:
11139 case BFD_RELOC_MIPS_RELGOT:
11140 case BFD_RELOC_MIPS_JALR:
11141 case BFD_RELOC_HI16:
11142 case BFD_RELOC_HI16_S:
11143 case BFD_RELOC_GPREL16:
11144 case BFD_RELOC_MIPS_LITERAL:
11145 case BFD_RELOC_MIPS_CALL16:
11146 case BFD_RELOC_MIPS_GOT16:
11147 case BFD_RELOC_GPREL32:
11148 case BFD_RELOC_MIPS_GOT_HI16:
11149 case BFD_RELOC_MIPS_GOT_LO16:
11150 case BFD_RELOC_MIPS_CALL_HI16:
11151 case BFD_RELOC_MIPS_CALL_LO16:
11152 case BFD_RELOC_MIPS16_GPREL:
11153 if (fixP->fx_pcrel)
11154 as_bad_where (fixP->fx_file, fixP->fx_line,
11155 _("Invalid PC relative reloc"));
11156 /* Nothing needed to do. The value comes from the reloc entry */
11159 case BFD_RELOC_MIPS16_JMP:
11160 /* We currently always generate a reloc against a symbol, which
11161 means that we don't want an addend even if the symbol is
11166 case BFD_RELOC_PCREL_HI16_S:
11167 /* The addend for this is tricky if it is internal, so we just
11168 do everything here rather than in bfd_install_relocation. */
11169 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11172 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11174 /* For an external symbol adjust by the address to make it
11175 pcrel_offset. We use the address of the RELLO reloc
11176 which follows this one. */
11177 *valP += (fixP->fx_next->fx_frag->fr_address
11178 + fixP->fx_next->fx_where);
11180 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11181 if (target_big_endian)
11183 md_number_to_chars (buf, *valP, 2);
11186 case BFD_RELOC_PCREL_LO16:
11187 /* The addend for this is tricky if it is internal, so we just
11188 do everything here rather than in bfd_install_relocation. */
11189 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11192 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11193 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11194 if (target_big_endian)
11196 md_number_to_chars (buf, *valP, 2);
11200 /* This is handled like BFD_RELOC_32, but we output a sign
11201 extended value if we are only 32 bits. */
11203 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11205 if (8 <= sizeof (valueT))
11206 md_number_to_chars (buf, *valP, 8);
11211 if ((*valP & 0x80000000) != 0)
11215 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11217 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11223 case BFD_RELOC_RVA:
11225 /* If we are deleting this reloc entry, we must fill in the
11226 value now. This can happen if we have a .word which is not
11227 resolved when it appears but is later defined. We also need
11228 to fill in the value if this is an embedded PIC switch table
11231 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11232 md_number_to_chars (buf, *valP, 4);
11236 /* If we are deleting this reloc entry, we must fill in the
11238 assert (fixP->fx_size == 2);
11240 md_number_to_chars (buf, *valP, 2);
11243 case BFD_RELOC_LO16:
11244 /* When handling an embedded PIC switch statement, we can wind
11245 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11248 if (*valP + 0x8000 > 0xffff)
11249 as_bad_where (fixP->fx_file, fixP->fx_line,
11250 _("relocation overflow"));
11251 if (target_big_endian)
11253 md_number_to_chars (buf, *valP, 2);
11257 case BFD_RELOC_16_PCREL_S2:
11258 if ((*valP & 0x3) != 0)
11259 as_bad_where (fixP->fx_file, fixP->fx_line,
11260 _("Branch to odd address (%lx)"), (long) *valP);
11263 * We need to save the bits in the instruction since fixup_segment()
11264 * might be deleting the relocation entry (i.e., a branch within
11265 * the current segment).
11267 if (! fixP->fx_done)
11270 /* update old instruction data */
11271 if (target_big_endian)
11272 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11274 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11276 if (*valP + 0x20000 <= 0x3ffff)
11278 insn |= (*valP >> 2) & 0xffff;
11279 md_number_to_chars (buf, insn, 4);
11281 else if (mips_pic == NO_PIC
11283 && fixP->fx_frag->fr_address >= text_section->vma
11284 && (fixP->fx_frag->fr_address
11285 < text_section->vma + text_section->_raw_size)
11286 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11287 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11288 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11290 /* The branch offset is too large. If this is an
11291 unconditional branch, and we are not generating PIC code,
11292 we can convert it to an absolute jump instruction. */
11293 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11294 insn = 0x0c000000; /* jal */
11296 insn = 0x08000000; /* j */
11297 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11299 fixP->fx_addsy = section_symbol (text_section);
11300 *valP += md_pcrel_from (fixP);
11301 md_number_to_chars (buf, insn, 4);
11305 /* If we got here, we have branch-relaxation disabled,
11306 and there's nothing we can do to fix this instruction
11307 without turning it into a longer sequence. */
11308 as_bad_where (fixP->fx_file, fixP->fx_line,
11309 _("Branch out of range"));
11313 case BFD_RELOC_VTABLE_INHERIT:
11316 && !S_IS_DEFINED (fixP->fx_addsy)
11317 && !S_IS_WEAK (fixP->fx_addsy))
11318 S_SET_WEAK (fixP->fx_addsy);
11321 case BFD_RELOC_VTABLE_ENTRY:
11329 /* Remember value for tc_gen_reloc. */
11330 fixP->fx_addnumber = *valP;
11335 printInsn (unsigned long oc)
11337 const struct mips_opcode *p;
11338 int treg, sreg, dreg, shamt;
11343 for (i = 0; i < NUMOPCODES; ++i)
11345 p = &mips_opcodes[i];
11346 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11348 printf ("%08lx %s\t", oc, p->name);
11349 treg = (oc >> 16) & 0x1f;
11350 sreg = (oc >> 21) & 0x1f;
11351 dreg = (oc >> 11) & 0x1f;
11352 shamt = (oc >> 6) & 0x1f;
11354 for (args = p->args;; ++args)
11365 printf ("%c", *args);
11369 assert (treg == sreg);
11370 printf ("$%d,$%d", treg, sreg);
11375 printf ("$%d", dreg);
11380 printf ("$%d", treg);
11384 printf ("0x%x", treg);
11389 printf ("$%d", sreg);
11393 printf ("0x%08lx", oc & 0x1ffffff);
11400 printf ("%d", imm);
11405 printf ("$%d", shamt);
11416 printf (_("%08lx UNDEFINED\n"), oc);
11427 name = input_line_pointer;
11428 c = get_symbol_end ();
11429 p = (symbolS *) symbol_find_or_make (name);
11430 *input_line_pointer = c;
11434 /* Align the current frag to a given power of two. The MIPS assembler
11435 also automatically adjusts any preceding label. */
11438 mips_align (int to, int fill, symbolS *label)
11440 mips_emit_delays (FALSE);
11441 frag_align (to, fill, 0);
11442 record_alignment (now_seg, to);
11445 assert (S_GET_SEGMENT (label) == now_seg);
11446 symbol_set_frag (label, frag_now);
11447 S_SET_VALUE (label, (valueT) frag_now_fix ());
11451 /* Align to a given power of two. .align 0 turns off the automatic
11452 alignment used by the data creating pseudo-ops. */
11455 s_align (int x ATTRIBUTE_UNUSED)
11458 register long temp_fill;
11459 long max_alignment = 15;
11463 o Note that the assembler pulls down any immediately preceding label
11464 to the aligned address.
11465 o It's not documented but auto alignment is reinstated by
11466 a .align pseudo instruction.
11467 o Note also that after auto alignment is turned off the mips assembler
11468 issues an error on attempt to assemble an improperly aligned data item.
11473 temp = get_absolute_expression ();
11474 if (temp > max_alignment)
11475 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11478 as_warn (_("Alignment negative: 0 assumed."));
11481 if (*input_line_pointer == ',')
11483 ++input_line_pointer;
11484 temp_fill = get_absolute_expression ();
11491 mips_align (temp, (int) temp_fill,
11492 insn_labels != NULL ? insn_labels->label : NULL);
11499 demand_empty_rest_of_line ();
11503 mips_flush_pending_output (void)
11505 mips_emit_delays (FALSE);
11506 mips_clear_insn_labels ();
11510 s_change_sec (int sec)
11514 /* When generating embedded PIC code, we only use the .text, .lit8,
11515 .sdata and .sbss sections. We change the .data and .rdata
11516 pseudo-ops to use .sdata. */
11517 if (mips_pic == EMBEDDED_PIC
11518 && (sec == 'd' || sec == 'r'))
11522 /* The ELF backend needs to know that we are changing sections, so
11523 that .previous works correctly. We could do something like check
11524 for an obj_section_change_hook macro, but that might be confusing
11525 as it would not be appropriate to use it in the section changing
11526 functions in read.c, since obj-elf.c intercepts those. FIXME:
11527 This should be cleaner, somehow. */
11528 obj_elf_section_change_hook ();
11531 mips_emit_delays (FALSE);
11541 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11542 demand_empty_rest_of_line ();
11546 if (USE_GLOBAL_POINTER_OPT)
11548 seg = subseg_new (RDATA_SECTION_NAME,
11549 (subsegT) get_absolute_expression ());
11550 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11552 bfd_set_section_flags (stdoutput, seg,
11558 if (strcmp (TARGET_OS, "elf") != 0)
11559 record_alignment (seg, 4);
11561 demand_empty_rest_of_line ();
11565 as_bad (_("No read only data section in this object file format"));
11566 demand_empty_rest_of_line ();
11572 if (USE_GLOBAL_POINTER_OPT)
11574 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11575 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11577 bfd_set_section_flags (stdoutput, seg,
11578 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11580 if (strcmp (TARGET_OS, "elf") != 0)
11581 record_alignment (seg, 4);
11583 demand_empty_rest_of_line ();
11588 as_bad (_("Global pointers not supported; recompile -G 0"));
11589 demand_empty_rest_of_line ();
11598 s_change_section (int ignore ATTRIBUTE_UNUSED)
11601 char *section_name;
11606 int section_entry_size;
11607 int section_alignment;
11609 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11612 section_name = input_line_pointer;
11613 c = get_symbol_end ();
11615 next_c = *(input_line_pointer + 1);
11617 /* Do we have .section Name<,"flags">? */
11618 if (c != ',' || (c == ',' && next_c == '"'))
11620 /* just after name is now '\0'. */
11621 *input_line_pointer = c;
11622 input_line_pointer = section_name;
11623 obj_elf_section (ignore);
11626 input_line_pointer++;
11628 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11630 section_type = get_absolute_expression ();
11633 if (*input_line_pointer++ == ',')
11634 section_flag = get_absolute_expression ();
11637 if (*input_line_pointer++ == ',')
11638 section_entry_size = get_absolute_expression ();
11640 section_entry_size = 0;
11641 if (*input_line_pointer++ == ',')
11642 section_alignment = get_absolute_expression ();
11644 section_alignment = 0;
11646 section_name = xstrdup (section_name);
11648 /* When using the generic form of .section (as implemented by obj-elf.c),
11649 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11650 traditionally had to fall back on the more common @progbits instead.
11652 There's nothing really harmful in this, since bfd will correct
11653 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11654 means that, for backwards compatibiltiy, the special_section entries
11655 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11657 Even so, we shouldn't force users of the MIPS .section syntax to
11658 incorrectly label the sections as SHT_PROGBITS. The best compromise
11659 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11660 generic type-checking code. */
11661 if (section_type == SHT_MIPS_DWARF)
11662 section_type = SHT_PROGBITS;
11664 obj_elf_change_section (section_name, section_type, section_flag,
11665 section_entry_size, 0, 0, 0);
11667 if (now_seg->name != section_name)
11668 free (section_name);
11669 #endif /* OBJ_ELF */
11673 mips_enable_auto_align (void)
11679 s_cons (int log_size)
11683 label = insn_labels != NULL ? insn_labels->label : NULL;
11684 mips_emit_delays (FALSE);
11685 if (log_size > 0 && auto_align)
11686 mips_align (log_size, 0, label);
11687 mips_clear_insn_labels ();
11688 cons (1 << log_size);
11692 s_float_cons (int type)
11696 label = insn_labels != NULL ? insn_labels->label : NULL;
11698 mips_emit_delays (FALSE);
11703 mips_align (3, 0, label);
11705 mips_align (2, 0, label);
11708 mips_clear_insn_labels ();
11713 /* Handle .globl. We need to override it because on Irix 5 you are
11716 where foo is an undefined symbol, to mean that foo should be
11717 considered to be the address of a function. */
11720 s_mips_globl (int x ATTRIBUTE_UNUSED)
11727 name = input_line_pointer;
11728 c = get_symbol_end ();
11729 symbolP = symbol_find_or_make (name);
11730 *input_line_pointer = c;
11731 SKIP_WHITESPACE ();
11733 /* On Irix 5, every global symbol that is not explicitly labelled as
11734 being a function is apparently labelled as being an object. */
11737 if (! is_end_of_line[(unsigned char) *input_line_pointer])
11742 secname = input_line_pointer;
11743 c = get_symbol_end ();
11744 sec = bfd_get_section_by_name (stdoutput, secname);
11746 as_bad (_("%s: no such section"), secname);
11747 *input_line_pointer = c;
11749 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11750 flag = BSF_FUNCTION;
11753 symbol_get_bfdsym (symbolP)->flags |= flag;
11755 S_SET_EXTERNAL (symbolP);
11756 demand_empty_rest_of_line ();
11760 s_option (int x ATTRIBUTE_UNUSED)
11765 opt = input_line_pointer;
11766 c = get_symbol_end ();
11770 /* FIXME: What does this mean? */
11772 else if (strncmp (opt, "pic", 3) == 0)
11776 i = atoi (opt + 3);
11781 mips_pic = SVR4_PIC;
11782 mips_abicalls = TRUE;
11785 as_bad (_(".option pic%d not supported"), i);
11787 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
11789 if (g_switch_seen && g_switch_value != 0)
11790 as_warn (_("-G may not be used with SVR4 PIC code"));
11791 g_switch_value = 0;
11792 bfd_set_gp_size (stdoutput, 0);
11796 as_warn (_("Unrecognized option \"%s\""), opt);
11798 *input_line_pointer = c;
11799 demand_empty_rest_of_line ();
11802 /* This structure is used to hold a stack of .set values. */
11804 struct mips_option_stack
11806 struct mips_option_stack *next;
11807 struct mips_set_options options;
11810 static struct mips_option_stack *mips_opts_stack;
11812 /* Handle the .set pseudo-op. */
11815 s_mipsset (int x ATTRIBUTE_UNUSED)
11817 char *name = input_line_pointer, ch;
11819 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11820 ++input_line_pointer;
11821 ch = *input_line_pointer;
11822 *input_line_pointer = '\0';
11824 if (strcmp (name, "reorder") == 0)
11826 if (mips_opts.noreorder && prev_nop_frag != NULL)
11828 /* If we still have pending nops, we can discard them. The
11829 usual nop handling will insert any that are still
11831 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11832 * (mips_opts.mips16 ? 2 : 4));
11833 prev_nop_frag = NULL;
11835 mips_opts.noreorder = 0;
11837 else if (strcmp (name, "noreorder") == 0)
11839 mips_emit_delays (TRUE);
11840 mips_opts.noreorder = 1;
11841 mips_any_noreorder = 1;
11843 else if (strcmp (name, "at") == 0)
11845 mips_opts.noat = 0;
11847 else if (strcmp (name, "noat") == 0)
11849 mips_opts.noat = 1;
11851 else if (strcmp (name, "macro") == 0)
11853 mips_opts.warn_about_macros = 0;
11855 else if (strcmp (name, "nomacro") == 0)
11857 if (mips_opts.noreorder == 0)
11858 as_bad (_("`noreorder' must be set before `nomacro'"));
11859 mips_opts.warn_about_macros = 1;
11861 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
11863 mips_opts.nomove = 0;
11865 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
11867 mips_opts.nomove = 1;
11869 else if (strcmp (name, "bopt") == 0)
11871 mips_opts.nobopt = 0;
11873 else if (strcmp (name, "nobopt") == 0)
11875 mips_opts.nobopt = 1;
11877 else if (strcmp (name, "mips16") == 0
11878 || strcmp (name, "MIPS-16") == 0)
11879 mips_opts.mips16 = 1;
11880 else if (strcmp (name, "nomips16") == 0
11881 || strcmp (name, "noMIPS-16") == 0)
11882 mips_opts.mips16 = 0;
11883 else if (strcmp (name, "mips3d") == 0)
11884 mips_opts.ase_mips3d = 1;
11885 else if (strcmp (name, "nomips3d") == 0)
11886 mips_opts.ase_mips3d = 0;
11887 else if (strcmp (name, "mdmx") == 0)
11888 mips_opts.ase_mdmx = 1;
11889 else if (strcmp (name, "nomdmx") == 0)
11890 mips_opts.ase_mdmx = 0;
11891 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11895 /* Permit the user to change the ISA and architecture on the fly.
11896 Needless to say, misuse can cause serious problems. */
11897 if (strcmp (name, "mips0") == 0)
11900 mips_opts.isa = file_mips_isa;
11902 else if (strcmp (name, "mips1") == 0)
11903 mips_opts.isa = ISA_MIPS1;
11904 else if (strcmp (name, "mips2") == 0)
11905 mips_opts.isa = ISA_MIPS2;
11906 else if (strcmp (name, "mips3") == 0)
11907 mips_opts.isa = ISA_MIPS3;
11908 else if (strcmp (name, "mips4") == 0)
11909 mips_opts.isa = ISA_MIPS4;
11910 else if (strcmp (name, "mips5") == 0)
11911 mips_opts.isa = ISA_MIPS5;
11912 else if (strcmp (name, "mips32") == 0)
11913 mips_opts.isa = ISA_MIPS32;
11914 else if (strcmp (name, "mips32r2") == 0)
11915 mips_opts.isa = ISA_MIPS32R2;
11916 else if (strcmp (name, "mips64") == 0)
11917 mips_opts.isa = ISA_MIPS64;
11918 else if (strcmp (name, "mips64r2") == 0)
11919 mips_opts.isa = ISA_MIPS64R2;
11920 else if (strcmp (name, "arch=default") == 0)
11923 mips_opts.arch = file_mips_arch;
11924 mips_opts.isa = file_mips_isa;
11926 else if (strncmp (name, "arch=", 5) == 0)
11928 const struct mips_cpu_info *p;
11930 p = mips_parse_cpu("internal use", name + 5);
11932 as_bad (_("unknown architecture %s"), name + 5);
11935 mips_opts.arch = p->cpu;
11936 mips_opts.isa = p->isa;
11940 as_bad (_("unknown ISA level %s"), name + 4);
11942 switch (mips_opts.isa)
11950 mips_opts.gp32 = 1;
11951 mips_opts.fp32 = 1;
11958 mips_opts.gp32 = 0;
11959 mips_opts.fp32 = 0;
11962 as_bad (_("unknown ISA level %s"), name + 4);
11967 mips_opts.gp32 = file_mips_gp32;
11968 mips_opts.fp32 = file_mips_fp32;
11971 else if (strcmp (name, "autoextend") == 0)
11972 mips_opts.noautoextend = 0;
11973 else if (strcmp (name, "noautoextend") == 0)
11974 mips_opts.noautoextend = 1;
11975 else if (strcmp (name, "push") == 0)
11977 struct mips_option_stack *s;
11979 s = (struct mips_option_stack *) xmalloc (sizeof *s);
11980 s->next = mips_opts_stack;
11981 s->options = mips_opts;
11982 mips_opts_stack = s;
11984 else if (strcmp (name, "pop") == 0)
11986 struct mips_option_stack *s;
11988 s = mips_opts_stack;
11990 as_bad (_(".set pop with no .set push"));
11993 /* If we're changing the reorder mode we need to handle
11994 delay slots correctly. */
11995 if (s->options.noreorder && ! mips_opts.noreorder)
11996 mips_emit_delays (TRUE);
11997 else if (! s->options.noreorder && mips_opts.noreorder)
11999 if (prev_nop_frag != NULL)
12001 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12002 * (mips_opts.mips16 ? 2 : 4));
12003 prev_nop_frag = NULL;
12007 mips_opts = s->options;
12008 mips_opts_stack = s->next;
12014 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12016 *input_line_pointer = ch;
12017 demand_empty_rest_of_line ();
12020 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12021 .option pic2. It means to generate SVR4 PIC calls. */
12024 s_abicalls (int ignore ATTRIBUTE_UNUSED)
12026 mips_pic = SVR4_PIC;
12027 mips_abicalls = TRUE;
12028 if (USE_GLOBAL_POINTER_OPT)
12030 if (g_switch_seen && g_switch_value != 0)
12031 as_warn (_("-G may not be used with SVR4 PIC code"));
12032 g_switch_value = 0;
12034 bfd_set_gp_size (stdoutput, 0);
12035 demand_empty_rest_of_line ();
12038 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12039 PIC code. It sets the $gp register for the function based on the
12040 function address, which is in the register named in the argument.
12041 This uses a relocation against _gp_disp, which is handled specially
12042 by the linker. The result is:
12043 lui $gp,%hi(_gp_disp)
12044 addiu $gp,$gp,%lo(_gp_disp)
12045 addu $gp,$gp,.cpload argument
12046 The .cpload argument is normally $25 == $t9. */
12049 s_cpload (int ignore ATTRIBUTE_UNUSED)
12053 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12054 .cpload is ignored. */
12055 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12061 /* .cpload should be in a .set noreorder section. */
12062 if (mips_opts.noreorder == 0)
12063 as_warn (_(".cpload not in noreorder section"));
12065 ex.X_op = O_symbol;
12066 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12067 ex.X_op_symbol = NULL;
12068 ex.X_add_number = 0;
12070 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12071 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12074 macro_build_lui (&ex, mips_gp_register);
12075 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12076 mips_gp_register, BFD_RELOC_LO16);
12077 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
12078 mips_gp_register, tc_get_register (0));
12081 demand_empty_rest_of_line ();
12084 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12085 .cpsetup $reg1, offset|$reg2, label
12087 If offset is given, this results in:
12088 sd $gp, offset($sp)
12089 lui $gp, %hi(%neg(%gp_rel(label)))
12090 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12091 daddu $gp, $gp, $reg1
12093 If $reg2 is given, this results in:
12094 daddu $reg2, $gp, $0
12095 lui $gp, %hi(%neg(%gp_rel(label)))
12096 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12097 daddu $gp, $gp, $reg1
12098 $reg1 is normally $25 == $t9. */
12100 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12102 expressionS ex_off;
12103 expressionS ex_sym;
12107 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12108 We also need NewABI support. */
12109 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12115 reg1 = tc_get_register (0);
12116 SKIP_WHITESPACE ();
12117 if (*input_line_pointer != ',')
12119 as_bad (_("missing argument separator ',' for .cpsetup"));
12123 ++input_line_pointer;
12124 SKIP_WHITESPACE ();
12125 if (*input_line_pointer == '$')
12127 mips_cpreturn_register = tc_get_register (0);
12128 mips_cpreturn_offset = -1;
12132 mips_cpreturn_offset = get_absolute_expression ();
12133 mips_cpreturn_register = -1;
12135 SKIP_WHITESPACE ();
12136 if (*input_line_pointer != ',')
12138 as_bad (_("missing argument separator ',' for .cpsetup"));
12142 ++input_line_pointer;
12143 SKIP_WHITESPACE ();
12144 expression (&ex_sym);
12147 if (mips_cpreturn_register == -1)
12149 ex_off.X_op = O_constant;
12150 ex_off.X_add_symbol = NULL;
12151 ex_off.X_op_symbol = NULL;
12152 ex_off.X_add_number = mips_cpreturn_offset;
12154 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
12155 BFD_RELOC_LO16, SP);
12158 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
12159 mips_gp_register, 0);
12161 /* Ensure there's room for the next two instructions, so that `f'
12162 doesn't end up with an address in the wrong frag. */
12165 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16);
12166 fix_new (frag_now, f - frag_now->fr_literal,
12167 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12168 fix_new (frag_now, f - frag_now->fr_literal,
12169 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12172 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
12173 mips_gp_register, BFD_RELOC_GPREL16);
12174 fix_new (frag_now, f - frag_now->fr_literal,
12175 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12176 fix_new (frag_now, f - frag_now->fr_literal,
12177 4, NULL, 0, 0, BFD_RELOC_LO16);
12179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12180 mips_gp_register, reg1);
12183 demand_empty_rest_of_line ();
12187 s_cplocal (int ignore ATTRIBUTE_UNUSED)
12189 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12190 .cplocal is ignored. */
12191 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12197 mips_gp_register = tc_get_register (0);
12198 demand_empty_rest_of_line ();
12201 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12202 offset from $sp. The offset is remembered, and after making a PIC
12203 call $gp is restored from that location. */
12206 s_cprestore (int ignore ATTRIBUTE_UNUSED)
12210 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12211 .cprestore is ignored. */
12212 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12218 mips_cprestore_offset = get_absolute_expression ();
12219 mips_cprestore_valid = 1;
12221 ex.X_op = O_constant;
12222 ex.X_add_symbol = NULL;
12223 ex.X_op_symbol = NULL;
12224 ex.X_add_number = mips_cprestore_offset;
12227 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
12228 SP, HAVE_64BIT_ADDRESSES);
12231 demand_empty_rest_of_line ();
12234 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12235 was given in the preceding .cpsetup, it results in:
12236 ld $gp, offset($sp)
12238 If a register $reg2 was given there, it results in:
12239 daddu $gp, $reg2, $0
12242 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12246 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12247 We also need NewABI support. */
12248 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12255 if (mips_cpreturn_register == -1)
12257 ex.X_op = O_constant;
12258 ex.X_add_symbol = NULL;
12259 ex.X_op_symbol = NULL;
12260 ex.X_add_number = mips_cpreturn_offset;
12262 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
12265 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
12266 mips_cpreturn_register, 0);
12269 demand_empty_rest_of_line ();
12272 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12273 code. It sets the offset to use in gp_rel relocations. */
12276 s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12278 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12279 We also need NewABI support. */
12280 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12286 mips_gprel_offset = get_absolute_expression ();
12288 demand_empty_rest_of_line ();
12291 /* Handle the .gpword pseudo-op. This is used when generating PIC
12292 code. It generates a 32 bit GP relative reloc. */
12295 s_gpword (int ignore ATTRIBUTE_UNUSED)
12301 /* When not generating PIC code, this is treated as .word. */
12302 if (mips_pic != SVR4_PIC)
12308 label = insn_labels != NULL ? insn_labels->label : NULL;
12309 mips_emit_delays (TRUE);
12311 mips_align (2, 0, label);
12312 mips_clear_insn_labels ();
12316 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12318 as_bad (_("Unsupported use of .gpword"));
12319 ignore_rest_of_line ();
12323 md_number_to_chars (p, 0, 4);
12324 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12325 BFD_RELOC_GPREL32);
12327 demand_empty_rest_of_line ();
12331 s_gpdword (int ignore ATTRIBUTE_UNUSED)
12337 /* When not generating PIC code, this is treated as .dword. */
12338 if (mips_pic != SVR4_PIC)
12344 label = insn_labels != NULL ? insn_labels->label : NULL;
12345 mips_emit_delays (TRUE);
12347 mips_align (3, 0, label);
12348 mips_clear_insn_labels ();
12352 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12354 as_bad (_("Unsupported use of .gpdword"));
12355 ignore_rest_of_line ();
12359 md_number_to_chars (p, 0, 8);
12360 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12361 BFD_RELOC_GPREL32);
12363 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12364 ex.X_op = O_absent;
12365 ex.X_add_symbol = 0;
12366 ex.X_add_number = 0;
12367 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12370 demand_empty_rest_of_line ();
12373 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12374 tables in SVR4 PIC code. */
12377 s_cpadd (int ignore ATTRIBUTE_UNUSED)
12381 /* This is ignored when not generating SVR4 PIC code. */
12382 if (mips_pic != SVR4_PIC)
12388 /* Add $gp to the register named as an argument. */
12390 reg = tc_get_register (0);
12391 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
12394 demand_empty_rest_of_line ();
12397 /* Handle the .insn pseudo-op. This marks instruction labels in
12398 mips16 mode. This permits the linker to handle them specially,
12399 such as generating jalx instructions when needed. We also make
12400 them odd for the duration of the assembly, in order to generate the
12401 right sort of code. We will make them even in the adjust_symtab
12402 routine, while leaving them marked. This is convenient for the
12403 debugger and the disassembler. The linker knows to make them odd
12407 s_insn (int ignore ATTRIBUTE_UNUSED)
12409 mips16_mark_labels ();
12411 demand_empty_rest_of_line ();
12414 /* Handle a .stabn directive. We need these in order to mark a label
12415 as being a mips16 text label correctly. Sometimes the compiler
12416 will emit a label, followed by a .stabn, and then switch sections.
12417 If the label and .stabn are in mips16 mode, then the label is
12418 really a mips16 text label. */
12421 s_mips_stab (int type)
12424 mips16_mark_labels ();
12429 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12433 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12440 name = input_line_pointer;
12441 c = get_symbol_end ();
12442 symbolP = symbol_find_or_make (name);
12443 S_SET_WEAK (symbolP);
12444 *input_line_pointer = c;
12446 SKIP_WHITESPACE ();
12448 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12450 if (S_IS_DEFINED (symbolP))
12452 as_bad ("ignoring attempt to redefine symbol %s",
12453 S_GET_NAME (symbolP));
12454 ignore_rest_of_line ();
12458 if (*input_line_pointer == ',')
12460 ++input_line_pointer;
12461 SKIP_WHITESPACE ();
12465 if (exp.X_op != O_symbol)
12467 as_bad ("bad .weakext directive");
12468 ignore_rest_of_line ();
12471 symbol_set_value_expression (symbolP, &exp);
12474 demand_empty_rest_of_line ();
12477 /* Parse a register string into a number. Called from the ECOFF code
12478 to parse .frame. The argument is non-zero if this is the frame
12479 register, so that we can record it in mips_frame_reg. */
12482 tc_get_register (int frame)
12486 SKIP_WHITESPACE ();
12487 if (*input_line_pointer++ != '$')
12489 as_warn (_("expected `$'"));
12492 else if (ISDIGIT (*input_line_pointer))
12494 reg = get_absolute_expression ();
12495 if (reg < 0 || reg >= 32)
12497 as_warn (_("Bad register number"));
12503 if (strncmp (input_line_pointer, "ra", 2) == 0)
12506 input_line_pointer += 2;
12508 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12511 input_line_pointer += 2;
12513 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12516 input_line_pointer += 2;
12518 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12521 input_line_pointer += 2;
12523 else if (strncmp (input_line_pointer, "at", 2) == 0)
12526 input_line_pointer += 2;
12528 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12531 input_line_pointer += 3;
12533 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12536 input_line_pointer += 3;
12538 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12541 input_line_pointer += 4;
12545 as_warn (_("Unrecognized register name"));
12547 while (ISALNUM(*input_line_pointer))
12548 input_line_pointer++;
12553 mips_frame_reg = reg != 0 ? reg : SP;
12554 mips_frame_reg_valid = 1;
12555 mips_cprestore_valid = 0;
12561 md_section_align (asection *seg, valueT addr)
12563 int align = bfd_get_section_alignment (stdoutput, seg);
12566 /* We don't need to align ELF sections to the full alignment.
12567 However, Irix 5 may prefer that we align them at least to a 16
12568 byte boundary. We don't bother to align the sections if we are
12569 targeted for an embedded system. */
12570 if (strcmp (TARGET_OS, "elf") == 0)
12576 return ((addr + (1 << align) - 1) & (-1 << align));
12579 /* Utility routine, called from above as well. If called while the
12580 input file is still being read, it's only an approximation. (For
12581 example, a symbol may later become defined which appeared to be
12582 undefined earlier.) */
12585 nopic_need_relax (symbolS *sym, int before_relaxing)
12590 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
12592 const char *symname;
12595 /* Find out whether this symbol can be referenced off the $gp
12596 register. It can be if it is smaller than the -G size or if
12597 it is in the .sdata or .sbss section. Certain symbols can
12598 not be referenced off the $gp, although it appears as though
12600 symname = S_GET_NAME (sym);
12601 if (symname != (const char *) NULL
12602 && (strcmp (symname, "eprol") == 0
12603 || strcmp (symname, "etext") == 0
12604 || strcmp (symname, "_gp") == 0
12605 || strcmp (symname, "edata") == 0
12606 || strcmp (symname, "_fbss") == 0
12607 || strcmp (symname, "_fdata") == 0
12608 || strcmp (symname, "_ftext") == 0
12609 || strcmp (symname, "end") == 0
12610 || strcmp (symname, "_gp_disp") == 0))
12612 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
12614 #ifndef NO_ECOFF_DEBUGGING
12615 || (symbol_get_obj (sym)->ecoff_extern_size != 0
12616 && (symbol_get_obj (sym)->ecoff_extern_size
12617 <= g_switch_value))
12619 /* We must defer this decision until after the whole
12620 file has been read, since there might be a .extern
12621 after the first use of this symbol. */
12622 || (before_relaxing
12623 #ifndef NO_ECOFF_DEBUGGING
12624 && symbol_get_obj (sym)->ecoff_extern_size == 0
12626 && S_GET_VALUE (sym) == 0)
12627 || (S_GET_VALUE (sym) != 0
12628 && S_GET_VALUE (sym) <= g_switch_value)))
12632 const char *segname;
12634 segname = segment_name (S_GET_SEGMENT (sym));
12635 assert (strcmp (segname, ".lit8") != 0
12636 && strcmp (segname, ".lit4") != 0);
12637 change = (strcmp (segname, ".sdata") != 0
12638 && strcmp (segname, ".sbss") != 0
12639 && strncmp (segname, ".sdata.", 7) != 0
12640 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
12645 /* We are not optimizing for the $gp register. */
12650 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12653 pic_need_relax (symbolS *sym, asection *segtype)
12656 bfd_boolean linkonce;
12658 /* Handle the case of a symbol equated to another symbol. */
12659 while (symbol_equated_reloc_p (sym))
12663 /* It's possible to get a loop here in a badly written
12665 n = symbol_get_value_expression (sym)->X_add_symbol;
12671 symsec = S_GET_SEGMENT (sym);
12673 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12675 if (symsec != segtype && ! S_IS_LOCAL (sym))
12677 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
12681 /* The GNU toolchain uses an extension for ELF: a section
12682 beginning with the magic string .gnu.linkonce is a linkonce
12684 if (strncmp (segment_name (symsec), ".gnu.linkonce",
12685 sizeof ".gnu.linkonce" - 1) == 0)
12689 /* This must duplicate the test in adjust_reloc_syms. */
12690 return (symsec != &bfd_und_section
12691 && symsec != &bfd_abs_section
12692 && ! bfd_is_com_section (symsec)
12695 /* A global or weak symbol is treated as external. */
12696 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12697 || (! S_IS_WEAK (sym)
12698 && (! S_IS_EXTERNAL (sym)
12699 || mips_pic == EMBEDDED_PIC)))
12705 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12706 extended opcode. SEC is the section the frag is in. */
12709 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
12712 register const struct mips16_immed_operand *op;
12714 int mintiny, maxtiny;
12718 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
12720 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
12723 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
12724 op = mips16_immed_operands;
12725 while (op->type != type)
12728 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
12733 if (type == '<' || type == '>' || type == '[' || type == ']')
12736 maxtiny = 1 << op->nbits;
12741 maxtiny = (1 << op->nbits) - 1;
12746 mintiny = - (1 << (op->nbits - 1));
12747 maxtiny = (1 << (op->nbits - 1)) - 1;
12750 sym_frag = symbol_get_frag (fragp->fr_symbol);
12751 val = S_GET_VALUE (fragp->fr_symbol);
12752 symsec = S_GET_SEGMENT (fragp->fr_symbol);
12758 /* We won't have the section when we are called from
12759 mips_relax_frag. However, we will always have been called
12760 from md_estimate_size_before_relax first. If this is a
12761 branch to a different section, we mark it as such. If SEC is
12762 NULL, and the frag is not marked, then it must be a branch to
12763 the same section. */
12766 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
12771 /* Must have been called from md_estimate_size_before_relax. */
12774 fragp->fr_subtype =
12775 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12777 /* FIXME: We should support this, and let the linker
12778 catch branches and loads that are out of range. */
12779 as_bad_where (fragp->fr_file, fragp->fr_line,
12780 _("unsupported PC relative reference to different section"));
12784 if (fragp != sym_frag && sym_frag->fr_address == 0)
12785 /* Assume non-extended on the first relaxation pass.
12786 The address we have calculated will be bogus if this is
12787 a forward branch to another frag, as the forward frag
12788 will have fr_address == 0. */
12792 /* In this case, we know for sure that the symbol fragment is in
12793 the same section. If the relax_marker of the symbol fragment
12794 differs from the relax_marker of this fragment, we have not
12795 yet adjusted the symbol fragment fr_address. We want to add
12796 in STRETCH in order to get a better estimate of the address.
12797 This particularly matters because of the shift bits. */
12799 && sym_frag->relax_marker != fragp->relax_marker)
12803 /* Adjust stretch for any alignment frag. Note that if have
12804 been expanding the earlier code, the symbol may be
12805 defined in what appears to be an earlier frag. FIXME:
12806 This doesn't handle the fr_subtype field, which specifies
12807 a maximum number of bytes to skip when doing an
12809 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
12811 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
12814 stretch = - ((- stretch)
12815 & ~ ((1 << (int) f->fr_offset) - 1));
12817 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
12826 addr = fragp->fr_address + fragp->fr_fix;
12828 /* The base address rules are complicated. The base address of
12829 a branch is the following instruction. The base address of a
12830 PC relative load or add is the instruction itself, but if it
12831 is in a delay slot (in which case it can not be extended) use
12832 the address of the instruction whose delay slot it is in. */
12833 if (type == 'p' || type == 'q')
12837 /* If we are currently assuming that this frag should be
12838 extended, then, the current address is two bytes
12840 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
12843 /* Ignore the low bit in the target, since it will be set
12844 for a text label. */
12845 if ((val & 1) != 0)
12848 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
12850 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
12853 val -= addr & ~ ((1 << op->shift) - 1);
12855 /* Branch offsets have an implicit 0 in the lowest bit. */
12856 if (type == 'p' || type == 'q')
12859 /* If any of the shifted bits are set, we must use an extended
12860 opcode. If the address depends on the size of this
12861 instruction, this can lead to a loop, so we arrange to always
12862 use an extended opcode. We only check this when we are in
12863 the main relaxation loop, when SEC is NULL. */
12864 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
12866 fragp->fr_subtype =
12867 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12871 /* If we are about to mark a frag as extended because the value
12872 is precisely maxtiny + 1, then there is a chance of an
12873 infinite loop as in the following code:
12878 In this case when the la is extended, foo is 0x3fc bytes
12879 away, so the la can be shrunk, but then foo is 0x400 away, so
12880 the la must be extended. To avoid this loop, we mark the
12881 frag as extended if it was small, and is about to become
12882 extended with a value of maxtiny + 1. */
12883 if (val == ((maxtiny + 1) << op->shift)
12884 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
12887 fragp->fr_subtype =
12888 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
12892 else if (symsec != absolute_section && sec != NULL)
12893 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
12895 if ((val & ((1 << op->shift) - 1)) != 0
12896 || val < (mintiny << op->shift)
12897 || val > (maxtiny << op->shift))
12903 /* Compute the length of a branch sequence, and adjust the
12904 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12905 worst-case length is computed, with UPDATE being used to indicate
12906 whether an unconditional (-1), branch-likely (+1) or regular (0)
12907 branch is to be computed. */
12909 relaxed_branch_length (fragS *fragp, asection *sec, int update)
12911 bfd_boolean toofar;
12915 && S_IS_DEFINED (fragp->fr_symbol)
12916 && sec == S_GET_SEGMENT (fragp->fr_symbol))
12921 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
12923 addr = fragp->fr_address + fragp->fr_fix + 4;
12927 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
12930 /* If the symbol is not defined or it's in a different segment,
12931 assume the user knows what's going on and emit a short
12937 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
12939 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp->fr_subtype),
12940 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
12941 RELAX_BRANCH_LINK (fragp->fr_subtype),
12947 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
12950 if (mips_pic != NO_PIC)
12952 /* Additional space for PIC loading of target address. */
12954 if (mips_opts.isa == ISA_MIPS1)
12955 /* Additional space for $at-stabilizing nop. */
12959 /* If branch is conditional. */
12960 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
12967 /* Estimate the size of a frag before relaxing. Unless this is the
12968 mips16, we are not really relaxing here, and the final size is
12969 encoded in the subtype information. For the mips16, we have to
12970 decide whether we are using an extended opcode or not. */
12973 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
12977 if (RELAX_BRANCH_P (fragp->fr_subtype))
12980 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
12982 return fragp->fr_var;
12985 if (RELAX_MIPS16_P (fragp->fr_subtype))
12986 /* We don't want to modify the EXTENDED bit here; it might get us
12987 into infinite loops. We change it only in mips_relax_frag(). */
12988 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
12990 if (mips_pic == NO_PIC)
12991 change = nopic_need_relax (fragp->fr_symbol, 0);
12992 else if (mips_pic == SVR4_PIC)
12993 change = pic_need_relax (fragp->fr_symbol, segtype);
12999 fragp->fr_subtype |= RELAX_USE_SECOND;
13000 return -RELAX_FIRST (fragp->fr_subtype);
13003 return -RELAX_SECOND (fragp->fr_subtype);
13006 /* This is called to see whether a reloc against a defined symbol
13007 should be converted into a reloc against a section. Don't adjust
13008 MIPS16 jump relocations, so we don't have to worry about the format
13009 of the offset in the .o file. Don't adjust relocations against
13010 mips16 symbols, so that the linker can find them if it needs to set
13014 mips_fix_adjustable (fixS *fixp)
13016 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13019 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13020 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13023 if (fixp->fx_addsy == NULL)
13026 /* If symbol SYM is in a mergeable section, relocations of the form
13027 SYM + 0 can usually be made section-relative. The mergeable data
13028 is then identified by the section offset rather than by the symbol.
13030 However, if we're generating REL LO16 relocations, the offset is split
13031 between the LO16 and parterning high part relocation. The linker will
13032 need to recalculate the complete offset in order to correctly identify
13035 The linker has traditionally not looked for the parterning high part
13036 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13037 placed anywhere. Rather than break backwards compatibility by changing
13038 this, it seems better not to force the issue, and instead keep the
13039 original symbol. This will work with either linker behavior. */
13040 if ((fixp->fx_r_type == BFD_RELOC_LO16
13041 || reloc_needs_lo_p (fixp->fx_r_type))
13042 && HAVE_IN_PLACE_ADDENDS
13043 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
13047 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13048 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13049 && fixp->fx_subsy == NULL)
13056 /* Translate internal representation of relocation info to BFD target
13060 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13062 static arelent *retval[4];
13064 bfd_reloc_code_real_type code;
13066 memset (retval, 0, sizeof(retval));
13067 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13068 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13069 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13070 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13072 if (mips_pic == EMBEDDED_PIC
13073 && SWITCH_TABLE (fixp))
13075 /* For a switch table entry we use a special reloc. The addend
13076 is actually the difference between the reloc address and the
13078 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13079 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13080 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13081 fixp->fx_r_type = BFD_RELOC_GPREL32;
13083 else if (fixp->fx_pcrel)
13085 bfd_vma pcrel_address;
13087 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13088 high-part relocs is the address of the low-part reloc. */
13089 if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13091 assert (fixp->fx_next != NULL
13092 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13093 pcrel_address = (fixp->fx_next->fx_where
13094 + fixp->fx_next->fx_frag->fr_address);
13097 pcrel_address = reloc->address;
13099 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13101 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13102 Relocations want only the symbol offset. */
13103 reloc->addend = fixp->fx_addnumber + pcrel_address;
13105 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
13106 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13108 /* We use a special addend for an internal RELLO or RELHI reloc. */
13109 if (symbol_section_p (fixp->fx_addsy))
13110 reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
13112 reloc->addend = fixp->fx_addnumber + pcrel_address;
13116 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13117 /* A gruesome hack which is a result of the gruesome gas reloc
13119 reloc->addend = pcrel_address;
13121 reloc->addend = -pcrel_address;
13125 reloc->addend = fixp->fx_addnumber;
13127 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13128 entry to be used in the relocation's section offset. */
13129 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13131 reloc->address = reloc->addend;
13135 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13136 fixup_segment converted a non-PC relative reloc into a PC
13137 relative reloc. In such a case, we need to convert the reloc
13139 code = fixp->fx_r_type;
13140 if (fixp->fx_pcrel)
13145 code = BFD_RELOC_8_PCREL;
13148 code = BFD_RELOC_16_PCREL;
13151 code = BFD_RELOC_32_PCREL;
13154 code = BFD_RELOC_64_PCREL;
13156 case BFD_RELOC_8_PCREL:
13157 case BFD_RELOC_16_PCREL:
13158 case BFD_RELOC_32_PCREL:
13159 case BFD_RELOC_64_PCREL:
13160 case BFD_RELOC_16_PCREL_S2:
13161 case BFD_RELOC_PCREL_HI16_S:
13162 case BFD_RELOC_PCREL_LO16:
13165 as_bad_where (fixp->fx_file, fixp->fx_line,
13166 _("Cannot make %s relocation PC relative"),
13167 bfd_get_reloc_code_name (code));
13171 /* To support a PC relative reloc when generating embedded PIC code
13172 for ECOFF, we use a Cygnus extension. We check for that here to
13173 make sure that we don't let such a reloc escape normally. */
13174 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13175 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13176 && code == BFD_RELOC_16_PCREL_S2
13177 && mips_pic != EMBEDDED_PIC)
13178 reloc->howto = NULL;
13180 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13182 if (reloc->howto == NULL)
13184 as_bad_where (fixp->fx_file, fixp->fx_line,
13185 _("Can not represent %s relocation in this object file format"),
13186 bfd_get_reloc_code_name (code));
13193 /* Relax a machine dependent frag. This returns the amount by which
13194 the current size of the frag should change. */
13197 mips_relax_frag (asection *sec, fragS *fragp, long stretch)
13199 if (RELAX_BRANCH_P (fragp->fr_subtype))
13201 offsetT old_var = fragp->fr_var;
13203 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
13205 return fragp->fr_var - old_var;
13208 if (! RELAX_MIPS16_P (fragp->fr_subtype))
13211 if (mips16_extended_frag (fragp, NULL, stretch))
13213 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13215 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
13220 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13222 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
13229 /* Convert a machine dependent frag. */
13232 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
13234 if (RELAX_BRANCH_P (fragp->fr_subtype))
13237 unsigned long insn;
13241 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
13243 if (target_big_endian)
13244 insn = bfd_getb32 (buf);
13246 insn = bfd_getl32 (buf);
13248 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
13250 /* We generate a fixup instead of applying it right now
13251 because, if there are linker relaxations, we're going to
13252 need the relocations. */
13253 exp.X_op = O_symbol;
13254 exp.X_add_symbol = fragp->fr_symbol;
13255 exp.X_add_number = fragp->fr_offset;
13257 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13259 BFD_RELOC_16_PCREL_S2);
13260 fixp->fx_file = fragp->fr_file;
13261 fixp->fx_line = fragp->fr_line;
13263 md_number_to_chars (buf, insn, 4);
13270 as_warn_where (fragp->fr_file, fragp->fr_line,
13271 _("relaxed out-of-range branch into a jump"));
13273 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
13276 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13278 /* Reverse the branch. */
13279 switch ((insn >> 28) & 0xf)
13282 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13283 have the condition reversed by tweaking a single
13284 bit, and their opcodes all have 0x4???????. */
13285 assert ((insn & 0xf1000000) == 0x41000000);
13286 insn ^= 0x00010000;
13290 /* bltz 0x04000000 bgez 0x04010000
13291 bltzal 0x04100000 bgezal 0x04110000 */
13292 assert ((insn & 0xfc0e0000) == 0x04000000);
13293 insn ^= 0x00010000;
13297 /* beq 0x10000000 bne 0x14000000
13298 blez 0x18000000 bgtz 0x1c000000 */
13299 insn ^= 0x04000000;
13307 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13309 /* Clear the and-link bit. */
13310 assert ((insn & 0xfc1c0000) == 0x04100000);
13312 /* bltzal 0x04100000 bgezal 0x04110000
13313 bltzall 0x04120000 bgezall 0x04130000 */
13314 insn &= ~0x00100000;
13317 /* Branch over the branch (if the branch was likely) or the
13318 full jump (not likely case). Compute the offset from the
13319 current instruction to branch to. */
13320 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13324 /* How many bytes in instructions we've already emitted? */
13325 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13326 /* How many bytes in instructions from here to the end? */
13327 i = fragp->fr_var - i;
13329 /* Convert to instruction count. */
13331 /* Branch counts from the next instruction. */
13334 /* Branch over the jump. */
13335 md_number_to_chars (buf, insn, 4);
13339 md_number_to_chars (buf, 0, 4);
13342 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13344 /* beql $0, $0, 2f */
13346 /* Compute the PC offset from the current instruction to
13347 the end of the variable frag. */
13348 /* How many bytes in instructions we've already emitted? */
13349 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13350 /* How many bytes in instructions from here to the end? */
13351 i = fragp->fr_var - i;
13352 /* Convert to instruction count. */
13354 /* Don't decrement i, because we want to branch over the
13358 md_number_to_chars (buf, insn, 4);
13361 md_number_to_chars (buf, 0, 4);
13366 if (mips_pic == NO_PIC)
13369 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13370 ? 0x0c000000 : 0x08000000);
13371 exp.X_op = O_symbol;
13372 exp.X_add_symbol = fragp->fr_symbol;
13373 exp.X_add_number = fragp->fr_offset;
13375 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13376 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13377 fixp->fx_file = fragp->fr_file;
13378 fixp->fx_line = fragp->fr_line;
13380 md_number_to_chars (buf, insn, 4);
13385 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13386 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13387 exp.X_op = O_symbol;
13388 exp.X_add_symbol = fragp->fr_symbol;
13389 exp.X_add_number = fragp->fr_offset;
13391 if (fragp->fr_offset)
13393 exp.X_add_symbol = make_expr_symbol (&exp);
13394 exp.X_add_number = 0;
13397 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13398 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13399 fixp->fx_file = fragp->fr_file;
13400 fixp->fx_line = fragp->fr_line;
13402 md_number_to_chars (buf, insn, 4);
13405 if (mips_opts.isa == ISA_MIPS1)
13408 md_number_to_chars (buf, 0, 4);
13412 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13413 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13415 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13416 4, &exp, 0, BFD_RELOC_LO16);
13417 fixp->fx_file = fragp->fr_file;
13418 fixp->fx_line = fragp->fr_line;
13420 md_number_to_chars (buf, insn, 4);
13424 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13429 md_number_to_chars (buf, insn, 4);
13434 assert (buf == (bfd_byte *)fragp->fr_literal
13435 + fragp->fr_fix + fragp->fr_var);
13437 fragp->fr_fix += fragp->fr_var;
13442 if (RELAX_MIPS16_P (fragp->fr_subtype))
13445 register const struct mips16_immed_operand *op;
13446 bfd_boolean small, ext;
13449 unsigned long insn;
13450 bfd_boolean use_extend;
13451 unsigned short extend;
13453 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
13454 op = mips16_immed_operands;
13455 while (op->type != type)
13458 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
13469 resolve_symbol_value (fragp->fr_symbol);
13470 val = S_GET_VALUE (fragp->fr_symbol);
13475 addr = fragp->fr_address + fragp->fr_fix;
13477 /* The rules for the base address of a PC relative reloc are
13478 complicated; see mips16_extended_frag. */
13479 if (type == 'p' || type == 'q')
13484 /* Ignore the low bit in the target, since it will be
13485 set for a text label. */
13486 if ((val & 1) != 0)
13489 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
13491 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
13494 addr &= ~ (addressT) ((1 << op->shift) - 1);
13497 /* Make sure the section winds up with the alignment we have
13500 record_alignment (asec, op->shift);
13504 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
13505 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
13506 as_warn_where (fragp->fr_file, fragp->fr_line,
13507 _("extended instruction in delay slot"));
13509 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
13511 if (target_big_endian)
13512 insn = bfd_getb16 (buf);
13514 insn = bfd_getl16 (buf);
13516 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13517 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13518 small, ext, &insn, &use_extend, &extend);
13522 md_number_to_chars (buf, 0xf000 | extend, 2);
13523 fragp->fr_fix += 2;
13527 md_number_to_chars (buf, insn, 2);
13528 fragp->fr_fix += 2;
13536 first = RELAX_FIRST (fragp->fr_subtype);
13537 second = RELAX_SECOND (fragp->fr_subtype);
13538 fixp = (fixS *) fragp->fr_opcode;
13540 /* Possibly emit a warning if we've chosen the longer option. */
13541 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
13542 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
13544 const char *msg = macro_warning (fragp->fr_subtype);
13546 as_warn_where (fragp->fr_file, fragp->fr_line, msg);
13549 /* Go through all the fixups for the first sequence. Disable them
13550 (by marking them as done) if we're going to use the second
13551 sequence instead. */
13553 && fixp->fx_frag == fragp
13554 && fixp->fx_where < fragp->fr_fix - second)
13556 if (fragp->fr_subtype & RELAX_USE_SECOND)
13558 fixp = fixp->fx_next;
13561 /* Go through the fixups for the second sequence. Disable them if
13562 we're going to use the first sequence, otherwise adjust their
13563 addresses to account for the relaxation. */
13564 while (fixp && fixp->fx_frag == fragp)
13566 if (fragp->fr_subtype & RELAX_USE_SECOND)
13567 fixp->fx_where -= first;
13570 fixp = fixp->fx_next;
13573 /* Now modify the frag contents. */
13574 if (fragp->fr_subtype & RELAX_USE_SECOND)
13578 start = fragp->fr_literal + fragp->fr_fix - first - second;
13579 memmove (start, start + first, second);
13580 fragp->fr_fix -= first;
13583 fragp->fr_fix -= second;
13589 /* This function is called after the relocs have been generated.
13590 We've been storing mips16 text labels as odd. Here we convert them
13591 back to even for the convenience of the debugger. */
13594 mips_frob_file_after_relocs (void)
13597 unsigned int count, i;
13599 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13602 syms = bfd_get_outsymbols (stdoutput);
13603 count = bfd_get_symcount (stdoutput);
13604 for (i = 0; i < count; i++, syms++)
13606 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13607 && ((*syms)->value & 1) != 0)
13609 (*syms)->value &= ~1;
13610 /* If the symbol has an odd size, it was probably computed
13611 incorrectly, so adjust that as well. */
13612 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
13613 ++elf_symbol (*syms)->internal_elf_sym.st_size;
13620 /* This function is called whenever a label is defined. It is used
13621 when handling branch delays; if a branch has a label, we assume we
13622 can not move it. */
13625 mips_define_label (symbolS *sym)
13627 struct insn_label_list *l;
13629 if (free_insn_labels == NULL)
13630 l = (struct insn_label_list *) xmalloc (sizeof *l);
13633 l = free_insn_labels;
13634 free_insn_labels = l->next;
13638 l->next = insn_labels;
13642 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13644 /* Some special processing for a MIPS ELF file. */
13647 mips_elf_final_processing (void)
13649 /* Write out the register information. */
13650 if (mips_abi != N64_ABI)
13654 s.ri_gprmask = mips_gprmask;
13655 s.ri_cprmask[0] = mips_cprmask[0];
13656 s.ri_cprmask[1] = mips_cprmask[1];
13657 s.ri_cprmask[2] = mips_cprmask[2];
13658 s.ri_cprmask[3] = mips_cprmask[3];
13659 /* The gp_value field is set by the MIPS ELF backend. */
13661 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
13662 ((Elf32_External_RegInfo *)
13663 mips_regmask_frag));
13667 Elf64_Internal_RegInfo s;
13669 s.ri_gprmask = mips_gprmask;
13671 s.ri_cprmask[0] = mips_cprmask[0];
13672 s.ri_cprmask[1] = mips_cprmask[1];
13673 s.ri_cprmask[2] = mips_cprmask[2];
13674 s.ri_cprmask[3] = mips_cprmask[3];
13675 /* The gp_value field is set by the MIPS ELF backend. */
13677 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
13678 ((Elf64_External_RegInfo *)
13679 mips_regmask_frag));
13682 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13683 sort of BFD interface for this. */
13684 if (mips_any_noreorder)
13685 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
13686 if (mips_pic != NO_PIC)
13688 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13689 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13692 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13694 /* Set MIPS ELF flags for ASEs. */
13695 if (file_ase_mips16)
13696 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13697 #if 0 /* XXX FIXME */
13698 if (file_ase_mips3d)
13699 elf_elfheader (stdoutput)->e_flags |= ???;
13702 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
13704 /* Set the MIPS ELF ABI flags. */
13705 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
13706 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
13707 else if (mips_abi == O64_ABI)
13708 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
13709 else if (mips_abi == EABI_ABI)
13711 if (!file_mips_gp32)
13712 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
13714 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
13716 else if (mips_abi == N32_ABI)
13717 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
13719 /* Nothing to do for N64_ABI. */
13721 if (mips_32bitmode)
13722 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13725 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13727 typedef struct proc {
13729 unsigned long reg_mask;
13730 unsigned long reg_offset;
13731 unsigned long fpreg_mask;
13732 unsigned long fpreg_offset;
13733 unsigned long frame_offset;
13734 unsigned long frame_reg;
13735 unsigned long pc_reg;
13738 static procS cur_proc;
13739 static procS *cur_proc_ptr;
13740 static int numprocs;
13742 /* Fill in an rs_align_code fragment. */
13745 mips_handle_align (fragS *fragp)
13747 if (fragp->fr_type != rs_align_code)
13750 if (mips_opts.mips16)
13752 static const unsigned char be_nop[] = { 0x65, 0x00 };
13753 static const unsigned char le_nop[] = { 0x00, 0x65 };
13758 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
13759 p = fragp->fr_literal + fragp->fr_fix;
13767 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
13771 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13775 md_obj_begin (void)
13782 /* check for premature end, nesting errors, etc */
13784 as_warn (_("missing .end at end of assembly"));
13793 if (*input_line_pointer == '-')
13795 ++input_line_pointer;
13798 if (!ISDIGIT (*input_line_pointer))
13799 as_bad (_("expected simple number"));
13800 if (input_line_pointer[0] == '0')
13802 if (input_line_pointer[1] == 'x')
13804 input_line_pointer += 2;
13805 while (ISXDIGIT (*input_line_pointer))
13808 val |= hex_value (*input_line_pointer++);
13810 return negative ? -val : val;
13814 ++input_line_pointer;
13815 while (ISDIGIT (*input_line_pointer))
13818 val |= *input_line_pointer++ - '0';
13820 return negative ? -val : val;
13823 if (!ISDIGIT (*input_line_pointer))
13825 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13826 *input_line_pointer, *input_line_pointer);
13827 as_warn (_("invalid number"));
13830 while (ISDIGIT (*input_line_pointer))
13833 val += *input_line_pointer++ - '0';
13835 return negative ? -val : val;
13838 /* The .file directive; just like the usual .file directive, but there
13839 is an initial number which is the ECOFF file index. In the non-ECOFF
13840 case .file implies DWARF-2. */
13843 s_mips_file (int x ATTRIBUTE_UNUSED)
13845 static int first_file_directive = 0;
13847 if (ECOFF_DEBUGGING)
13856 filename = dwarf2_directive_file (0);
13858 /* Versions of GCC up to 3.1 start files with a ".file"
13859 directive even for stabs output. Make sure that this
13860 ".file" is handled. Note that you need a version of GCC
13861 after 3.1 in order to support DWARF-2 on MIPS. */
13862 if (filename != NULL && ! first_file_directive)
13864 (void) new_logical_line (filename, -1);
13865 s_app_file_string (filename);
13867 first_file_directive = 1;
13871 /* The .loc directive, implying DWARF-2. */
13874 s_mips_loc (int x ATTRIBUTE_UNUSED)
13876 if (!ECOFF_DEBUGGING)
13877 dwarf2_directive_loc (0);
13880 /* The .end directive. */
13883 s_mips_end (int x ATTRIBUTE_UNUSED)
13887 /* Following functions need their own .frame and .cprestore directives. */
13888 mips_frame_reg_valid = 0;
13889 mips_cprestore_valid = 0;
13891 if (!is_end_of_line[(unsigned char) *input_line_pointer])
13894 demand_empty_rest_of_line ();
13899 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13900 as_warn (_(".end not in text section"));
13904 as_warn (_(".end directive without a preceding .ent directive."));
13905 demand_empty_rest_of_line ();
13911 assert (S_GET_NAME (p));
13912 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
13913 as_warn (_(".end symbol does not match .ent symbol."));
13915 if (debug_type == DEBUG_STABS)
13916 stabs_generate_asm_endfunc (S_GET_NAME (p),
13920 as_warn (_(".end directive missing or unknown symbol"));
13923 /* Generate a .pdr section. */
13924 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
13927 segT saved_seg = now_seg;
13928 subsegT saved_subseg = now_subseg;
13933 dot = frag_now_fix ();
13935 #ifdef md_flush_pending_output
13936 md_flush_pending_output ();
13940 subseg_set (pdr_seg, 0);
13942 /* Write the symbol. */
13943 exp.X_op = O_symbol;
13944 exp.X_add_symbol = p;
13945 exp.X_add_number = 0;
13946 emit_expr (&exp, 4);
13948 fragp = frag_more (7 * 4);
13950 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
13951 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
13952 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
13953 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
13954 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
13955 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
13956 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
13958 subseg_set (saved_seg, saved_subseg);
13960 #endif /* OBJ_ELF */
13962 cur_proc_ptr = NULL;
13965 /* The .aent and .ent directives. */
13968 s_mips_ent (int aent)
13972 symbolP = get_symbol ();
13973 if (*input_line_pointer == ',')
13974 ++input_line_pointer;
13975 SKIP_WHITESPACE ();
13976 if (ISDIGIT (*input_line_pointer)
13977 || *input_line_pointer == '-')
13980 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
13981 as_warn (_(".ent or .aent not in text section."));
13983 if (!aent && cur_proc_ptr)
13984 as_warn (_("missing .end"));
13988 /* This function needs its own .frame and .cprestore directives. */
13989 mips_frame_reg_valid = 0;
13990 mips_cprestore_valid = 0;
13992 cur_proc_ptr = &cur_proc;
13993 memset (cur_proc_ptr, '\0', sizeof (procS));
13995 cur_proc_ptr->isym = symbolP;
13997 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14001 if (debug_type == DEBUG_STABS)
14002 stabs_generate_asm_func (S_GET_NAME (symbolP),
14003 S_GET_NAME (symbolP));
14006 demand_empty_rest_of_line ();
14009 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14010 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14011 s_mips_frame is used so that we can set the PDR information correctly.
14012 We can't use the ecoff routines because they make reference to the ecoff
14013 symbol table (in the mdebug section). */
14016 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14019 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14023 if (cur_proc_ptr == (procS *) NULL)
14025 as_warn (_(".frame outside of .ent"));
14026 demand_empty_rest_of_line ();
14030 cur_proc_ptr->frame_reg = tc_get_register (1);
14032 SKIP_WHITESPACE ();
14033 if (*input_line_pointer++ != ','
14034 || get_absolute_expression_and_terminator (&val) != ',')
14036 as_warn (_("Bad .frame directive"));
14037 --input_line_pointer;
14038 demand_empty_rest_of_line ();
14042 cur_proc_ptr->frame_offset = val;
14043 cur_proc_ptr->pc_reg = tc_get_register (0);
14045 demand_empty_rest_of_line ();
14048 #endif /* OBJ_ELF */
14052 /* The .fmask and .mask directives. If the mdebug section is present
14053 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14054 embedded targets, s_mips_mask is used so that we can set the PDR
14055 information correctly. We can't use the ecoff routines because they
14056 make reference to the ecoff symbol table (in the mdebug section). */
14059 s_mips_mask (int reg_type)
14062 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14066 if (cur_proc_ptr == (procS *) NULL)
14068 as_warn (_(".mask/.fmask outside of .ent"));
14069 demand_empty_rest_of_line ();
14073 if (get_absolute_expression_and_terminator (&mask) != ',')
14075 as_warn (_("Bad .mask/.fmask directive"));
14076 --input_line_pointer;
14077 demand_empty_rest_of_line ();
14081 off = get_absolute_expression ();
14083 if (reg_type == 'F')
14085 cur_proc_ptr->fpreg_mask = mask;
14086 cur_proc_ptr->fpreg_offset = off;
14090 cur_proc_ptr->reg_mask = mask;
14091 cur_proc_ptr->reg_offset = off;
14094 demand_empty_rest_of_line ();
14097 #endif /* OBJ_ELF */
14098 s_ignore (reg_type);
14101 /* The .loc directive. */
14111 assert (now_seg == text_section);
14113 lineno = get_number ();
14114 addroff = frag_now_fix ();
14116 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14117 S_SET_TYPE (symbolP, N_SLINE);
14118 S_SET_OTHER (symbolP, 0);
14119 S_SET_DESC (symbolP, lineno);
14120 symbolP->sy_segment = now_seg;
14124 /* A table describing all the processors gas knows about. Names are
14125 matched in the order listed.
14127 To ease comparison, please keep this table in the same order as
14128 gcc's mips_cpu_info_table[]. */
14129 static const struct mips_cpu_info mips_cpu_info_table[] =
14131 /* Entries for generic ISAs */
14132 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14133 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14134 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14135 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14136 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14137 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14138 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14139 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14140 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
14143 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14144 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14145 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14148 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14151 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14152 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14153 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14154 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14155 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14156 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14157 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14158 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14159 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14160 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14161 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14162 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14165 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14166 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14167 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14168 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14169 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14170 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14171 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14172 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14173 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14174 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14175 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14176 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14177 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14180 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14181 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14182 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14185 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14186 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14188 /* Broadcom SB-1 CPU core */
14189 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14196 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14197 with a final "000" replaced by "k". Ignore case.
14199 Note: this function is shared between GCC and GAS. */
14202 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14204 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14205 given++, canonical++;
14207 return ((*given == 0 && *canonical == 0)
14208 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14212 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14213 CPU name. We've traditionally allowed a lot of variation here.
14215 Note: this function is shared between GCC and GAS. */
14218 mips_matching_cpu_name_p (const char *canonical, const char *given)
14220 /* First see if the name matches exactly, or with a final "000"
14221 turned into "k". */
14222 if (mips_strict_matching_cpu_name_p (canonical, given))
14225 /* If not, try comparing based on numerical designation alone.
14226 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14227 if (TOLOWER (*given) == 'r')
14229 if (!ISDIGIT (*given))
14232 /* Skip over some well-known prefixes in the canonical name,
14233 hoping to find a number there too. */
14234 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14236 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14238 else if (TOLOWER (canonical[0]) == 'r')
14241 return mips_strict_matching_cpu_name_p (canonical, given);
14245 /* Parse an option that takes the name of a processor as its argument.
14246 OPTION is the name of the option and CPU_STRING is the argument.
14247 Return the corresponding processor enumeration if the CPU_STRING is
14248 recognized, otherwise report an error and return null.
14250 A similar function exists in GCC. */
14252 static const struct mips_cpu_info *
14253 mips_parse_cpu (const char *option, const char *cpu_string)
14255 const struct mips_cpu_info *p;
14257 /* 'from-abi' selects the most compatible architecture for the given
14258 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14259 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14260 version. Look first at the -mgp options, if given, otherwise base
14261 the choice on MIPS_DEFAULT_64BIT.
14263 Treat NO_ABI like the EABIs. One reason to do this is that the
14264 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14265 architecture. This code picks MIPS I for 'mips' and MIPS III for
14266 'mips64', just as we did in the days before 'from-abi'. */
14267 if (strcasecmp (cpu_string, "from-abi") == 0)
14269 if (ABI_NEEDS_32BIT_REGS (mips_abi))
14270 return mips_cpu_info_from_isa (ISA_MIPS1);
14272 if (ABI_NEEDS_64BIT_REGS (mips_abi))
14273 return mips_cpu_info_from_isa (ISA_MIPS3);
14275 if (file_mips_gp32 >= 0)
14276 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
14278 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14283 /* 'default' has traditionally been a no-op. Probably not very useful. */
14284 if (strcasecmp (cpu_string, "default") == 0)
14287 for (p = mips_cpu_info_table; p->name != 0; p++)
14288 if (mips_matching_cpu_name_p (p->name, cpu_string))
14291 as_bad ("Bad value (%s) for %s", cpu_string, option);
14295 /* Return the canonical processor information for ISA (a member of the
14296 ISA_MIPS* enumeration). */
14298 static const struct mips_cpu_info *
14299 mips_cpu_info_from_isa (int isa)
14303 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14304 if (mips_cpu_info_table[i].is_isa
14305 && isa == mips_cpu_info_table[i].isa)
14306 return (&mips_cpu_info_table[i]);
14311 static const struct mips_cpu_info *
14312 mips_cpu_info_from_arch (int arch)
14316 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14317 if (arch == mips_cpu_info_table[i].cpu)
14318 return (&mips_cpu_info_table[i]);
14324 show (FILE *stream, const char *string, int *col_p, int *first_p)
14328 fprintf (stream, "%24s", "");
14333 fprintf (stream, ", ");
14337 if (*col_p + strlen (string) > 72)
14339 fprintf (stream, "\n%24s", "");
14343 fprintf (stream, "%s", string);
14344 *col_p += strlen (string);
14350 md_show_usage (FILE *stream)
14355 fprintf (stream, _("\
14357 -membedded-pic generate embedded position independent code\n\
14358 -EB generate big endian output\n\
14359 -EL generate little endian output\n\
14360 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14361 -G NUM allow referencing objects up to NUM bytes\n\
14362 implicitly with the gp register [default 8]\n"));
14363 fprintf (stream, _("\
14364 -mips1 generate MIPS ISA I instructions\n\
14365 -mips2 generate MIPS ISA II instructions\n\
14366 -mips3 generate MIPS ISA III instructions\n\
14367 -mips4 generate MIPS ISA IV instructions\n\
14368 -mips5 generate MIPS ISA V instructions\n\
14369 -mips32 generate MIPS32 ISA instructions\n\
14370 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14371 -mips64 generate MIPS64 ISA instructions\n\
14372 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14373 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14377 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14378 show (stream, mips_cpu_info_table[i].name, &column, &first);
14379 show (stream, "from-abi", &column, &first);
14380 fputc ('\n', stream);
14382 fprintf (stream, _("\
14383 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14384 -no-mCPU don't generate code specific to CPU.\n\
14385 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14389 show (stream, "3900", &column, &first);
14390 show (stream, "4010", &column, &first);
14391 show (stream, "4100", &column, &first);
14392 show (stream, "4650", &column, &first);
14393 fputc ('\n', stream);
14395 fprintf (stream, _("\
14396 -mips16 generate mips16 instructions\n\
14397 -no-mips16 do not generate mips16 instructions\n"));
14398 fprintf (stream, _("\
14399 -mfix-vr4120 work around certain VR4120 errata\n\
14400 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14401 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14402 -O0 remove unneeded NOPs, do not swap branches\n\
14403 -O remove unneeded NOPs and swap branches\n\
14404 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14405 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14406 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14408 fprintf (stream, _("\
14409 -KPIC, -call_shared generate SVR4 position independent code\n\
14410 -non_shared do not generate position independent code\n\
14411 -xgot assume a 32 bit GOT\n\
14412 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14413 -mabi=ABI create ABI conformant object file for:\n"));
14417 show (stream, "32", &column, &first);
14418 show (stream, "o64", &column, &first);
14419 show (stream, "n32", &column, &first);
14420 show (stream, "64", &column, &first);
14421 show (stream, "eabi", &column, &first);
14423 fputc ('\n', stream);
14425 fprintf (stream, _("\
14426 -32 create o32 ABI object file (default)\n\
14427 -n32 create n32 ABI object file\n\
14428 -64 create 64 ABI object file\n"));
14433 mips_dwarf2_format (void)
14435 if (mips_abi == N64_ABI)
14438 return dwarf2_format_64bit_irix;
14440 return dwarf2_format_64bit;
14444 return dwarf2_format_32bit;
14448 mips_dwarf2_addr_size (void)
14450 if (mips_abi == N64_ABI)