1 2006-05-26 Richard Sandiford <richard@codesourcery.com>
3 * m68k.h (mcf_mask): Define.
5 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
7 * avr.h (AVR_ISA_PWMx): New.
9 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
11 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
12 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
13 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
14 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
15 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
17 2006-03-10 Paul Brook <paul@codesourcery.com>
19 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
21 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
23 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
24 first. Correct mask of bb "B" opcode.
26 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
28 * i386.h (i386_optab): Support Intel Merom New Instructions.
30 2006-02-24 Paul Brook <paul@codesourcery.com>
32 * arm.h: Add V7 feature bits.
34 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
36 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
38 2006-01-31 Paul Brook <paul@codesourcery.com>
39 Richard Earnshaw <rearnsha@arm.com>
41 * arm.h: Use ARM_CPU_FEATURE.
42 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
43 (arm_feature_set): Change to a structure.
44 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
45 ARM_FEATURE): New macros.
47 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
49 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
50 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
51 (ADD_PC_INCR_OPCODE): Don't define.
53 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
56 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
58 2005-11-14 David Ung <davidu@mips.com>
60 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
61 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
62 save/restore encoding of the args field.
64 2005-10-28 Dave Brolley <brolley@redhat.com>
66 Contribute the following changes:
67 2005-02-16 Dave Brolley <brolley@redhat.com>
69 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
70 cgen_isa_mask_* to cgen_bitset_*.
73 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
75 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
76 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
77 (CGEN_CPU_TABLE): Make isas a ponter.
79 2003-09-29 Dave Brolley <brolley@redhat.com>
81 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
82 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
83 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
85 2002-12-13 Dave Brolley <brolley@redhat.com>
87 * cgen.h (symcat.h): #include it.
88 (cgen-bitset.h): #include it.
89 (CGEN_ATTR_VALUE_TYPE): Now a union.
90 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
91 (CGEN_ATTR_ENTRY): 'value' now unsigned.
92 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
93 * cgen-bitset.h: New file.
95 2005-09-30 Catherine Moore <clm@cm00re.com>
99 2005-10-24 Jan Beulich <jbeulich@novell.com>
101 * ia64.h (enum ia64_opnd): Move memory operand out of set of
104 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
106 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
107 Add FLAG_STRICT to pa10 ftest opcode.
109 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
111 * hppa.h (pa_opcodes): Remove lha entries.
113 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
115 * hppa.h (FLAG_STRICT): Revise comment.
116 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
117 before corresponding pa11 opcodes. Add strict pa10 register-immediate
120 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
122 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
124 2005-09-06 Chao-ying Fu <fu@mips.com>
126 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
127 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
129 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
130 (INSN_ASE_MASK): Update to include INSN_MT.
131 (INSN_MT): New define for MT ASE.
133 2005-08-25 Chao-ying Fu <fu@mips.com>
135 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
136 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
137 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
138 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
139 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
140 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
142 (INSN_DSP): New define for DSP ASE.
144 2005-08-18 Alan Modra <amodra@bigpond.net.au>
148 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
150 * ppc.h (PPC_OPCODE_E300): Define.
152 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
154 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
156 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
159 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
162 2005-07-27 Jan Beulich <jbeulich@novell.com>
164 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
165 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
166 Add movq-s as 64-bit variants of movd-s.
168 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
170 * hppa.h: Fix punctuation in comment.
172 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
173 implicit space-register addressing. Set space-register bits on opcodes
174 using implicit space-register addressing. Add various missing pa20
175 long-immediate opcodes. Remove various opcodes using implicit 3-bit
176 space-register addressing. Use "fE" instead of "fe" in various
179 2005-07-18 Jan Beulich <jbeulich@novell.com>
181 * i386.h (i386_optab): Operands of aam and aad are unsigned.
183 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
185 * i386.h (i386_optab): Support Intel VMX Instructions.
187 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
189 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
191 2005-07-05 Jan Beulich <jbeulich@novell.com>
193 * i386.h (i386_optab): Add new insns.
195 2005-07-01 Nick Clifton <nickc@redhat.com>
197 * sparc.h: Add typedefs to structure declarations.
199 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
202 * i386.h (i386_optab): Update comments for 64bit addressing on
203 mov. Allow 64bit addressing for mov and movq.
205 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
207 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
208 respectively, in various floating-point load and store patterns.
210 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
212 * hppa.h (FLAG_STRICT): Correct comment.
213 (pa_opcodes): Update load and store entries to allow both PA 1.X and
214 PA 2.0 mneumonics when equivalent. Entries with cache control
215 completers now require PA 1.1. Adjust whitespace.
217 2005-05-19 Anton Blanchard <anton@samba.org>
219 * ppc.h (PPC_OPCODE_POWER5): Define.
221 2005-05-10 Nick Clifton <nickc@redhat.com>
223 * Update the address and phone number of the FSF organization in
224 the GPL notices in the following files:
225 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
226 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
227 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
228 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
229 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
230 tic54x.h, tic80.h, v850.h, vax.h
232 2005-05-09 Jan Beulich <jbeulich@novell.com>
234 * i386.h (i386_optab): Add ht and hnt.
236 2005-04-18 Mark Kettenis <kettenis@gnu.org>
238 * i386.h: Insert hyphens into selected VIA PadLock extensions.
239 Add xcrypt-ctr. Provide aliases without hyphens.
241 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
243 Moved from ../ChangeLog
245 2005-04-12 Paul Brook <paul@codesourcery.com>
246 * m88k.h: Rename psr macros to avoid conflicts.
248 2005-03-12 Zack Weinberg <zack@codesourcery.com>
249 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
250 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
253 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
254 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
255 Remove redundant instruction types.
256 (struct argument): X_op - new field.
257 (struct cst4_entry): Remove.
258 (no_op_insn): Declare.
260 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
261 * crx.h (enum argtype): Rename types, remove unused types.
263 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
264 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
265 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
266 (enum operand_type): Rearrange operands, edit comments.
267 replace us<N> with ui<N> for unsigned immediate.
268 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
269 displacements (respectively).
270 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
271 (instruction type): Add NO_TYPE_INS.
272 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
273 (operand_entry): New field - 'flags'.
274 (operand flags): New.
276 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
277 * crx.h (operand_type): Remove redundant types i3, i4,
279 Add new unsigned immediate types us3, us4, us5, us16.
281 2005-04-12 Mark Kettenis <kettenis@gnu.org>
283 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
284 adjust them accordingly.
286 2005-04-01 Jan Beulich <jbeulich@novell.com>
288 * i386.h (i386_optab): Add rdtscp.
290 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
292 * i386.h (i386_optab): Don't allow the `l' suffix for moving
293 between memory and segment register. Allow movq for moving between
294 general-purpose register and segment register.
296 2005-02-09 Jan Beulich <jbeulich@novell.com>
299 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
300 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
303 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
305 * m68k.h (m68008, m68ec030, m68882): Remove.
307 (cpu_m68k, cpu_cf): New.
308 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
309 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
311 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
313 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
314 * cgen.h (enum cgen_parse_operand_type): Add
315 CGEN_PARSE_OPERAND_SYMBOLIC.
317 2005-01-21 Fred Fish <fnf@specifixinc.com>
319 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
320 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
321 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
323 2005-01-19 Fred Fish <fnf@specifixinc.com>
325 * mips.h (struct mips_opcode): Add new pinfo2 member.
326 (INSN_ALIAS): New define for opcode table entries that are
327 specific instances of another entry, such as 'move' for an 'or'
329 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
330 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
332 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
334 * mips.h (CPU_RM9000): Define.
335 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
337 2004-11-25 Jan Beulich <jbeulich@novell.com>
339 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
340 to/from test registers are illegal in 64-bit mode. Add missing
341 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
342 (previously one had to explicitly encode a rex64 prefix). Re-enable
343 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
344 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
346 2004-11-23 Jan Beulich <jbeulich@novell.com>
348 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
349 available only with SSE2. Change the MMX additions introduced by SSE
350 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
351 instructions by their now designated identifier (since combining i686
352 and 3DNow! does not really imply 3DNow!A).
354 2004-11-19 Alan Modra <amodra@bigpond.net.au>
356 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
357 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
359 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
360 Vineet Sharma <vineets@noida.hcltech.com>
362 * maxq.h: New file: Disassembly information for the maxq port.
364 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
366 * i386.h (i386_optab): Put back "movzb".
368 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
370 * cris.h (enum cris_insn_version_usage): Tweak formatting and
371 comments. Remove member cris_ver_sim. Add members
372 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
373 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
374 (struct cris_support_reg, struct cris_cond15): New types.
375 (cris_conds15): Declare.
376 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
377 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
378 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
379 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
380 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
383 2004-11-04 Jan Beulich <jbeulich@novell.com>
385 * i386.h (sldx_Suf): Remove.
386 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
387 (q_FP): Define, implying no REX64.
388 (x_FP, sl_FP): Imply FloatMF.
389 (i386_optab): Split reg and mem forms of moving from segment registers
390 so that the memory forms can ignore the 16-/32-bit operand size
391 distinction. Adjust a few others for Intel mode. Remove *FP uses from
392 all non-floating-point instructions. Unite 32- and 64-bit forms of
393 movsx, movzx, and movd. Adjust floating point operations for the above
394 changes to the *FP macros. Add DefaultSize to floating point control
395 insns operating on larger memory ranges. Remove left over comments
396 hinting at certain insns being Intel-syntax ones where the ones
397 actually meant are already gone.
399 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
401 * crx.h: Add COPS_REG_INS - Coprocessor Special register
404 2004-09-30 Paul Brook <paul@codesourcery.com>
406 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
407 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
409 2004-09-11 Theodore A. Roth <troth@openavr.org>
411 * avr.h: Add support for
412 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
414 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
416 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
418 2004-08-24 Dmitry Diky <diwil@spec.ru>
420 * msp430.h (msp430_opc): Add new instructions.
421 (msp430_rcodes): Declare new instructions.
422 (msp430_hcodes): Likewise..
424 2004-08-13 Nick Clifton <nickc@redhat.com>
427 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
430 2004-08-30 Michal Ludvig <mludvig@suse.cz>
432 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
434 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
436 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
438 2004-07-21 Jan Beulich <jbeulich@novell.com>
440 * i386.h: Adjust instruction descriptions to better match the
443 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
445 * arm.h: Remove all old content. Replace with architecture defines
446 from gas/config/tc-arm.c.
448 2004-07-09 Andreas Schwab <schwab@suse.de>
450 * m68k.h: Fix comment.
452 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
456 2004-06-24 Alan Modra <amodra@bigpond.net.au>
458 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
460 2004-05-24 Peter Barada <peter@the-baradas.com>
462 * m68k.h: Add 'size' to m68k_opcode.
464 2004-05-05 Peter Barada <peter@the-baradas.com>
466 * m68k.h: Switch from ColdFire chip name to core variant.
468 2004-04-22 Peter Barada <peter@the-baradas.com>
470 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
471 descriptions for new EMAC cases.
472 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
473 handle Motorola MAC syntax.
474 Allow disassembly of ColdFire V4e object files.
476 2004-03-16 Alan Modra <amodra@bigpond.net.au>
478 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
480 2004-03-12 Jakub Jelinek <jakub@redhat.com>
482 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
484 2004-03-12 Michal Ludvig <mludvig@suse.cz>
486 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
488 2004-03-12 Michal Ludvig <mludvig@suse.cz>
490 * i386.h (i386_optab): Added xstore/xcrypt insns.
492 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
494 * h8300.h (32bit ldc/stc): Add relaxing support.
496 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
498 * h8300.h (BITOP): Pass MEMRELAX flag.
500 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
502 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
505 For older changes see ChangeLog-9103
511 version-control: never