1 /* Instruction printing code for the ARC.
2 Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Doug Evans (dje@cygnus.com).
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #include "libiberty.h"
23 #include "opcode/arc.h"
37 #define BIT(word,n) ((word) & (1 << n))
38 #define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
39 #define OPCODE(word) (BITS ((word), 27, 31))
40 #define FIELDA(word) (BITS ((word), 21, 26))
41 #define FIELDB(word) (BITS ((word), 15, 20))
42 #define FIELDC(word) (BITS ((word), 9, 14))
44 /* FIELD D is signed in all of its uses, so we make sure argument is
45 treated as signed for bit shifting purposes: */
46 #define FIELDD(word) (BITS (((signed int)word), 0, 8))
48 #define PUT_NEXT_WORD_IN(a) \
51 if (is_limm == 1 && !NEXT_WORD (1)) \
52 mwerror (state, _("Illegal limm reference in last instruction!\n")); \
53 a = state->words[1]; \
57 #define CHECK_FLAG_COND_NULLIFY() \
62 flag = BIT (state->words[0], 8); \
63 state->nullifyMode = BITS (state->words[0], 5, 6); \
64 cond = BITS (state->words[0], 0, 4); \
69 #define CHECK_COND() \
73 cond = BITS (state->words[0], 0, 4); \
77 #define CHECK_FIELD(field) \
84 PUT_NEXT_WORD_IN (field); \
87 else if (field > 60) \
91 flag = (field == 61); \
92 field = FIELDD (state->words[0]); \
97 #define CHECK_FIELD_A() \
100 fieldA = FIELDA (state->words[0]); \
109 #define CHECK_FIELD_B() \
112 fieldB = FIELDB (state->words[0]); \
113 CHECK_FIELD (fieldB); \
117 #define CHECK_FIELD_C() \
120 fieldC = FIELDC (state->words[0]); \
121 CHECK_FIELD (fieldC); \
125 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
126 #define IS_REG(x) (field##x##isReg)
127 #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","")
128 #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[")
129 #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]")
130 #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]")
131 #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","")
132 #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",")
133 #define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","")
134 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
135 (IS_REG (x) ? cb1"%r"ca1 : \
136 usesAuxReg ? cb"%a"ca : \
137 IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
138 #define WRITE_FORMAT_RB() strcat (formatString, "]")
139 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
140 #define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
142 #define NEXT_WORD(x) (offset += 4, state->words[x])
144 #define add_target(x) (state->targets[state->tcnt++] = (x))
146 static char comment_prefix[] = "\t; ";
148 static const char *core_reg_name PARAMS ((struct arcDisState *, int));
149 static const char *aux_reg_name PARAMS ((struct arcDisState *, int));
150 static const char *cond_code_name PARAMS ((struct arcDisState *, int));
151 static const char *instruction_name
152 PARAMS ((struct arcDisState *, int, int, int *));
153 static void mwerror PARAMS ((struct arcDisState *, const char *));
154 static const char *post_address PARAMS ((struct arcDisState *, int));
155 static void write_comments_
156 PARAMS ((struct arcDisState *, int, int, long int));
157 static void write_instr_name_
158 PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int));
159 static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *));
160 static const char *_coreRegName PARAMS ((void *, int));
161 static int decodeInstr PARAMS ((bfd_vma, disassemble_info *));
164 core_reg_name (state, val)
165 struct arcDisState * state;
168 if (state->coreRegName)
169 return (*state->coreRegName)(state->_this, val);
174 aux_reg_name (state, val)
175 struct arcDisState * state;
178 if (state->auxRegName)
179 return (*state->auxRegName)(state->_this, val);
184 cond_code_name (state, val)
185 struct arcDisState * state;
188 if (state->condCodeName)
189 return (*state->condCodeName)(state->_this, val);
194 instruction_name (state, op1, op2, flags)
195 struct arcDisState * state;
201 return (*state->instName)(state->_this, op1, op2, flags);
207 struct arcDisState * state;
211 (*state->err)(state->_this, (msg));
215 post_address (state, addr)
216 struct arcDisState * state;
219 static char id[3 * ARRAY_SIZE (state->addresses)];
220 int j, i = state->acnt;
222 if (i < ((int) ARRAY_SIZE (state->addresses)))
224 state->addresses[i] = addr;
236 static void my_sprintf PARAMS ((struct arcDisState *, char *, const char *,
240 my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format,
245 int size, leading_zero, regMap[2];
248 VA_OPEN (ap, format);
249 VA_FIXEDARG (ap, struct arcDisState *, state);
250 VA_FIXEDARG (ap, char *, buf);
251 VA_FIXEDARG (ap, const char *, format);
264 goto DOCOMM; /* (return) */
288 leading_zero = 1; /* e.g. %08x */
289 while (*p >= '0' && *p <= '9')
291 size = size * 10 + *p - '0';
296 #define inc_bp() bp = bp + strlen (bp)
300 unsigned u = va_arg (ap, int);
302 /* Hex. We can change the format to 0x%08x in
303 one place, here, if we wish.
304 We add underscores for easy reading. */
306 sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
308 sprintf (bp, "0x%x", u);
314 int val = va_arg (ap, int);
318 sprintf (bp, "%0*x", size, val);
320 sprintf (bp, "%*x", size, val);
322 sprintf (bp, "%x", val);
328 int val = va_arg (ap, int);
331 sprintf (bp, "%*d", size, val);
333 sprintf (bp, "%d", val);
340 int val = va_arg (ap, int);
342 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
343 regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
350 REG2NAME (29, "ilink1");
351 REG2NAME (30, "ilink2");
352 REG2NAME (31, "blink");
353 REG2NAME (60, "lp_count");
358 ext = core_reg_name (state, val);
360 sprintf (bp, "%s", ext);
362 sprintf (bp,"r%d",val);
372 int val = va_arg (ap, int);
374 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
378 AUXREG2NAME (0x0, "status");
379 AUXREG2NAME (0x1, "semaphore");
380 AUXREG2NAME (0x2, "lp_start");
381 AUXREG2NAME (0x3, "lp_end");
382 AUXREG2NAME (0x4, "identity");
383 AUXREG2NAME (0x5, "debug");
388 ext = aux_reg_name (state, val);
390 sprintf (bp, "%s", ext);
392 my_sprintf (state, bp, "%h", val);
402 sprintf (bp, "%s", va_arg (ap, char *));
408 fprintf (stderr, "?? format %c\n", p[-1]);
418 write_comments_(state, shimm, is_limm, limm_value)
419 struct arcDisState * state;
424 if (state->commentBuffer != 0)
430 const char *name = post_address (state, limm_value + shimm);
433 WRITE_COMMENT (name);
435 for (i = 0; i < state->commNum; i++)
438 strcpy (state->commentBuffer, comment_prefix);
440 strcat (state->commentBuffer, ", ");
441 strncat (state->commentBuffer, state->comm[i],
442 sizeof (state->commentBuffer));
447 #define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
448 #define write_comments() write_comments2(0)
450 static const char *condName[] = {
452 "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
453 "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
457 write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
458 struct arcDisState * state;
459 const char * instrName;
461 int condCodeIsPartOfName;
467 strcpy (state->instrBuffer, instrName);
473 if (!condCodeIsPartOfName)
474 strcat (state->instrBuffer, ".");
479 cc = cond_code_name (state, cond);
484 strcat (state->instrBuffer, cc);
488 strcat (state->instrBuffer, ".f");
490 switch (state->nullifyMode)
493 strcat (state->instrBuffer, ".d");
495 case BR_exec_when_jump:
496 strcat (state->instrBuffer, ".jd");
501 strcat (state->instrBuffer, ".x");
504 strcat (state->instrBuffer, ".a");
507 strcat (state->instrBuffer, ".di");
510 #define write_instr_name() \
513 write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
514 flag, signExtend, addrWriteBack, directMem); \
515 formatString[0] = '\0'; \
520 op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
521 op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
522 op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
523 op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15
526 extern disassemble_info tm_print_insn_info;
529 dsmOneArcInst (addr, state)
531 struct arcDisState * state;
533 int condCodeIsPartOfName = 0;
535 const char * instrName;
549 int addrWriteBack = 0;
556 char formatString[60];
558 state->instructionLen = 4;
559 state->nullifyMode = BR_exec_when_no_jump;
563 state->_mem_load = 0;
564 state->_ea_present = 0;
565 state->_load_len = 0;
566 state->ea_reg1 = no_reg;
567 state->ea_reg2 = no_reg;
573 state->_opcode = OPCODE (state->words[0]);
575 decodingClass = 0; /* default! */
577 condCodeIsPartOfName=0;
581 state->flow = noflow;
584 if (state->commentBuffer)
585 state->commentBuffer[0] = '\0';
587 switch (state->_opcode)
590 switch (BITS (state->words[0],1,2))
594 state->_load_len = 4;
598 state->_load_len = 1;
602 state->_load_len = 2;
605 instrName = "??? (0[3])";
606 state->flow = invalid_instr;
613 if (BIT (state->words[0],13))
620 switch (BITS (state->words[0],10,11))
624 state->_load_len = 4;
628 state->_load_len = 1;
632 state->_load_len = 2;
635 instrName = "??? (1[3])";
636 state->flow = invalid_instr;
644 if (BIT (state->words[0],25))
651 switch (BITS (state->words[0],22,23))
663 instrName = "??? (2[3])";
664 state->flow = invalid_instr;
672 decodingClass = 1; /* default for opcode 3... */
673 switch (FIELDC (state->words[0]))
706 switch( FIELDD (state->words[0]) )
719 state->flow=invalid_instr;
725 /* ARC Extension Library Instructions
726 NOTE: We assume that extension codes are these instrs. */
728 instrName = instruction_name (state,
730 FIELDC (state->words[0]),
735 state->flow = invalid_instr;
737 if (flags & IGNORE_FIRST_OPD)
754 if (BITS (state->words[0],9,9))
765 condCodeIsPartOfName = 1;
766 decodingClass = ((state->_opcode == op_JC) ? 4 : 3);
773 repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
776 switch (state->_opcode)
779 instrName = (repeatsOp ? "asl" : "add");
782 instrName = (repeatsOp ? "rlc" : "adc");
785 instrName = (repeatsOp ? "mov" : "and");
790 case op_SUB: instrName = "sub";
792 case op_SBC: instrName = "sbc";
794 case op_OR: instrName = "or";
796 case op_BIC: instrName = "bic";
800 if (state->words[0] == 0x7fffffff)
802 /* nop encoded as xor -1, -1, -1 */
811 instrName = instruction_name (state,state->_opcode,0,&flags);
812 /* if (instrName) printf("FLAGS=0x%x\n", flags); */
816 state->flow=invalid_instr;
818 if (flags & IGNORE_FIRST_OPD)
823 fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
824 flag = cond = is_shimm = is_limm = 0;
825 state->nullifyMode = BR_exec_when_no_jump; /* 0 */
826 signExtend = addrWriteBack = directMem = 0;
829 switch (decodingClass)
836 CHECK_FLAG_COND_NULLIFY ();
842 WRITE_FORMAT_COMMA_x (B);
844 WRITE_FORMAT_COMMA_x (C);
845 WRITE_NOP_COMMENT ();
846 my_sprintf (state, state->operandBuffer, formatString,
847 fieldA, fieldB, fieldC);
853 WRITE_FORMAT_COMMA_x (C);
854 my_sprintf (state, state->operandBuffer, formatString,
863 CHECK_FLAG_COND_NULLIFY ();
869 WRITE_FORMAT_COMMA_x (B);
870 WRITE_NOP_COMMENT ();
871 my_sprintf (state, state->operandBuffer, formatString,
877 my_sprintf (state, state->operandBuffer, formatString, fieldB);
884 CHECK_FLAG_COND_NULLIFY ();
885 flag = 0; /* this is the FLAG instruction -- it's redundant */
889 my_sprintf (state, state->operandBuffer, formatString, fieldB);
894 fieldA = BITS (state->words[0],7,26) << 2;
895 fieldA = (fieldA << 10) >> 10; /* make it signed */
897 CHECK_FLAG_COND_NULLIFY ();
901 /* This address could be a label we know. Convert it. */
902 if (state->_opcode != op_LPC /* LP */)
904 add_target (fieldA); /* For debugger. */
905 state->flow = state->_opcode == op_BLC /* BL */
908 /* indirect calls are achieved by "lr blink,[status];
909 lr dest<- func addr; j [dest]" */
912 strcat (formatString, "%s"); /* address/label name */
913 my_sprintf (state, state->operandBuffer, formatString,
914 post_address (state, fieldA));
919 /* For op_JC -- jump to address specified.
920 Also covers jump and link--bit 9 of the instr. word
921 selects whether linked, thus "is_linked" is set above. */
924 CHECK_FLAG_COND_NULLIFY ();
929 fieldA = (fieldB >> 25) & 0x7F; /* flags */
930 fieldB = (fieldB & 0xFFFFFF) << 2;
931 state->flow = is_linked ? direct_call : direct_jump;
933 /* screwy JLcc requires .jd mode to execute correctly
934 * but we pretend it is .nd (no delay slot). */
935 if (is_linked && state->nullifyMode == BR_exec_when_jump)
936 state->nullifyMode = BR_exec_when_no_jump;
940 state->flow = is_linked ? indirect_call : indirect_jump;
941 /* We should also treat this as indirect call if NOT linked
942 * but the preceding instruction was a "lr blink,[status]"
943 * and we have a delay slot with "add blink,blink,2".
944 * For now we can't detect such. */
945 state->register_for_indirect_jump = fieldB;
949 strcat (formatString,
950 IS_REG (B) ? "[%r]" : "%s"); /* address/label name */
954 WRITE_FORMAT_COMMA_x (A);
957 my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
959 my_sprintf (state, state->operandBuffer, formatString,
960 post_address (state, fieldB), fieldA);
966 B and C can be regs, or one (both?) can be limm. */
971 printf ("5:b reg %d %d c reg %d %d \n",
972 fieldBisReg,fieldB,fieldCisReg,fieldC);
974 state->_ea_present = 1;
976 state->ea_reg1 = fieldB;
978 state->_offset += fieldB;
980 state->ea_reg2 = fieldC;
982 state->_offset += fieldC;
983 state->_mem_load = 1;
985 directMem = BIT (state->words[0],5);
986 addrWriteBack = BIT (state->words[0],3);
987 signExtend = BIT (state->words[0],0);
990 WRITE_FORMAT_x_COMMA_LB(A);
991 if (fieldBisReg || fieldB != 0)
992 WRITE_FORMAT_x_COMMA (B);
996 WRITE_FORMAT_x_RB (C);
997 my_sprintf (state, state->operandBuffer, formatString,
998 fieldA, fieldB, fieldC);
1003 /* LD instruction. */
1006 fieldC = FIELDD (state->words[0]);
1009 printf ("6:b reg %d %d c 0x%x \n",
1010 fieldBisReg, fieldB, fieldC);
1011 state->_ea_present = 1;
1012 state->_offset = fieldC;
1013 state->_mem_load = 1;
1015 state->ea_reg1 = fieldB;
1016 /* field B is either a shimm (same as fieldC) or limm (different!)
1017 Say ea is not present, so only one of us will do the name lookup. */
1019 state->_offset += fieldB, state->_ea_present = 0;
1021 directMem = BIT (state->words[0],14);
1022 addrWriteBack = BIT (state->words[0],12);
1023 signExtend = BIT (state->words[0],9);
1025 write_instr_name ();
1026 WRITE_FORMAT_x_COMMA_LB (A);
1029 fieldB = state->_offset;
1030 WRITE_FORMAT_x_RB (B);
1035 if (fieldC != 0 && !BIT (state->words[0],13))
1038 WRITE_FORMAT_COMMA_x_RB (C);
1043 my_sprintf (state, state->operandBuffer, formatString,
1044 fieldA, fieldB, fieldC);
1049 /* ST instruction. */
1052 fieldA = FIELDD(state->words[0]); /* shimm */
1055 if (dbg) printf("7:b reg %d %x off %x\n",
1056 fieldBisReg,fieldB,fieldA);
1057 state->_ea_present = 1;
1058 state->_offset = fieldA;
1060 state->ea_reg1 = fieldB;
1061 /* field B is either a shimm (same as fieldA) or limm (different!)
1062 Say ea is not present, so only one of us will do the name lookup.
1063 (for is_limm we do the name translation here). */
1065 state->_offset += fieldB, state->_ea_present = 0;
1067 directMem = BIT(state->words[0],26);
1068 addrWriteBack = BIT(state->words[0],24);
1071 WRITE_FORMAT_x_COMMA_LB(C);
1075 fieldB = state->_offset;
1076 WRITE_FORMAT_x_RB(B);
1081 if (fieldBisReg && fieldA != 0)
1084 WRITE_FORMAT_COMMA_x_RB(A);
1089 my_sprintf (state, state->operandBuffer, formatString,
1090 fieldC, fieldB, fieldA);
1091 write_comments2(fieldA);
1094 /* SR instruction */
1099 WRITE_FORMAT_x_COMMA_LB(C);
1100 /* Try to print B as an aux reg if it is not a core reg. */
1104 my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
1110 state->operandBuffer[0] = '\0';
1114 /* LR instruction */
1119 WRITE_FORMAT_x_COMMA_LB(A);
1120 /* Try to print B as an aux reg if it is not a core reg. */
1124 my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
1131 state->operandBuffer[0] = '\0';
1135 mwerror (state, "Bad decoding class in ARC disassembler");
1139 state->_cond = cond;
1140 return state->instructionLen = offset;
1144 /* Returns the name the user specified core extension register. */
1146 _coreRegName(arg, regval)
1147 void * arg ATTRIBUTE_UNUSED;
1150 return arcExtMap_coreRegName (regval);
1153 /* Returns the name the user specified AUX extension register. */
1155 _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
1157 return arcExtMap_auxRegName(regval);
1161 /* Returns the name the user specified condition code name. */
1163 _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
1165 return arcExtMap_condCodeName(regval);
1168 /* Returns the name the user specified extension instruction. */
1170 _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
1172 return arcExtMap_instName(majop, minop, flags);
1175 /* Decode an instruction returning the size of the instruction
1176 in bytes or zero if unrecognized. */
1178 decodeInstr (address, info)
1179 bfd_vma address; /* Address of this instruction. */
1180 disassemble_info * info;
1184 struct arcDisState s; /* ARC Disassembler state */
1185 void *stream = info->stream; /* output stream */
1186 fprintf_ftype func = info->fprintf_func;
1189 memset (&s, 0, sizeof(struct arcDisState));
1191 /* read first instruction */
1192 status = (*info->read_memory_func) (address, buffer, 4, info);
1195 (*info->memory_error_func) (status, address, info);
1198 if (info->endian == BFD_ENDIAN_LITTLE)
1199 s.words[0] = bfd_getl32(buffer);
1201 s.words[0] = bfd_getb32(buffer);
1202 /* always read second word in case of limm */
1204 /* we ignore the result since last insn may not have a limm */
1205 status = (*info->read_memory_func) (address + 4, buffer, 4, info);
1206 if (info->endian == BFD_ENDIAN_LITTLE)
1207 s.words[1] = bfd_getl32(buffer);
1209 s.words[1] = bfd_getb32(buffer);
1212 s.coreRegName = _coreRegName;
1213 s.auxRegName = _auxRegName;
1214 s.condCodeName = _condCodeName;
1215 s.instName = _instName;
1218 bytes = dsmOneArcInst(address, (void *)&s);
1220 /* display the disassembly instruction */
1221 (*func) (stream, "%08x ", s.words[0]);
1222 (*func) (stream, " ");
1224 (*func) (stream, "%-10s ", s.instrBuffer);
1226 if (__TRANSLATION_REQUIRED(s))
1228 bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
1229 (*info->print_address_func) ((bfd_vma) addr, info);
1230 (*func) (stream, "\n");
1233 (*func) (stream, "%s",s.operandBuffer);
1234 return s.instructionLen;
1237 /* Return the print_insn function to use.
1238 Side effect: load (possibly empty) extension section */
1241 arc_get_disassembler (void *ptr)
1244 build_ARC_extmap (ptr);