1 /* Opcode table for the ARC.
2 Copyright 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Doug Evans (dje@cygnus.com).
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #include "opcode/arc.h"
27 #define INSERT_FN(fn) \
28 static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
29 int, const struct arc_operand_value *, long, \
31 #define EXTRACT_FN(fn) \
32 static long fn PARAMS ((arc_insn *, const struct arc_operand *, \
33 int, const struct arc_operand_value **, int *))
35 INSERT_FN (insert_reg);
36 INSERT_FN (insert_shimmfinish);
37 INSERT_FN (insert_limmfinish);
38 INSERT_FN (insert_shimmoffset);
39 INSERT_FN (insert_shimmzero);
40 INSERT_FN (insert_flag);
41 INSERT_FN (insert_flagfinish);
42 INSERT_FN (insert_cond);
43 INSERT_FN (insert_forcelimm);
44 INSERT_FN (insert_reladdr);
45 INSERT_FN (insert_absaddr);
46 INSERT_FN (insert_unopmacro);
48 EXTRACT_FN (extract_reg);
49 EXTRACT_FN (extract_flag);
50 EXTRACT_FN (extract_cond);
51 EXTRACT_FN (extract_reladdr);
52 EXTRACT_FN (extract_unopmacro);
54 /* Various types of ARC operands, including insn suffixes. */
56 /* Insn format values:
58 'a' REGA register A field
59 'b' REGB register B field
60 'c' REGC register C field
61 'S' SHIMMFINISH finish inserting a shimm value
62 'L' LIMMFINISH finish inserting a limm value
63 'd' SHIMMOFFSET shimm offset in ld,st insns
64 '0' SHIMMZERO 0 shimm value in ld,st insns
66 'F' FLAGFINISH finish inserting the F flag
67 'G' FLAGINSN insert F flag in "flag" insn
68 'n' DELAY N field (nullify field)
69 'q' COND condition code field
70 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm
71 'B' BRANCH branch address (22 bit pc relative)
72 'J' JUMP jump address (26 bit absolute)
73 'z' SIZE1 size field in ld a,[b,c]
74 'Z' SIZE10 size field in ld a,[b,shimm]
75 'y' SIZE22 size field in st c,[b,shimm]
76 'x' SIGN0 sign extend field ld a,[b,c]
77 'X' SIGN9 sign extend field ld a,[b,shimm]
78 'w' ADDRESS3 write-back field in ld a,[b,c]
79 'W' ADDRESS12 write-back field in ld a,[b,shimm]
80 'v' ADDRESS24 write-back field in st c,[b,shimm]
81 'e' CACHEBYPASS5 cache bypass in ld a,[b,c]
82 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm]
83 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm]
84 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros
86 The following modifiers may appear between the % and char (eg: %.f):
88 '.' MODDOT '.' prefix must be present
89 'r' REG generic register value, for register table
90 'A' AUXREG auxiliary register in lr a,[b], sr c,[b]
94 CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN
97 const struct arc_operand arc_operands[] =
99 /* place holder (??? not sure if needed) */
103 /* register A or shimm/limm indicator */
104 #define REGA (UNUSED + 1)
105 { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
107 /* register B or shimm/limm indicator */
108 #define REGB (REGA + 1)
109 { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
111 /* register C or shimm/limm indicator */
112 #define REGC (REGB + 1)
113 { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
115 /* fake operand used to insert shimm value into most instructions */
116 #define SHIMMFINISH (REGC + 1)
117 { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
119 /* fake operand used to insert limm value into most instructions. */
120 #define LIMMFINISH (SHIMMFINISH + 1)
121 { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
123 /* shimm operand when there is no reg indicator (ld,st) */
124 #define SHIMMOFFSET (LIMMFINISH + 1)
125 { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 },
127 /* 0 shimm operand for ld,st insns */
128 #define SHIMMZERO (SHIMMOFFSET + 1)
129 { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 },
131 /* flag update bit (insertion is defered until we know how) */
132 #define FLAG (SHIMMZERO + 1)
133 { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
135 /* fake utility operand to finish 'f' suffix handling */
136 #define FLAGFINISH (FLAG + 1)
137 { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
139 /* fake utility operand to set the 'f' flag for the "flag" insn */
140 #define FLAGINSN (FLAGFINISH + 1)
141 { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
143 /* branch delay types */
144 #define DELAY (FLAGINSN + 1)
145 { 'n', 2, 5, ARC_OPERAND_SUFFIX },
148 #define COND (DELAY + 1)
149 { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
151 /* set `cond_p' to 1 to ensure a constant is treated as a limm */
152 #define FORCELIMM (COND + 1)
153 { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm },
155 /* branch address; b, bl, and lp insns */
156 #define BRANCH (FORCELIMM + 1)
157 { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr },
159 /* jump address; j insn (this is basically the same as 'L' except that the
160 value is right shifted by 2) */
161 #define JUMP (BRANCH + 1)
162 { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr },
164 /* size field, stored in bit 1,2 */
165 #define SIZE1 (JUMP + 1)
166 { 'z', 2, 1, ARC_OPERAND_SUFFIX },
168 /* size field, stored in bit 10,11 */
169 #define SIZE10 (SIZE1 + 1)
170 { 'Z', 2, 10, ARC_OPERAND_SUFFIX, },
172 /* size field, stored in bit 22,23 */
173 #define SIZE22 (SIZE10 + 1)
174 { 'y', 2, 22, ARC_OPERAND_SUFFIX, },
176 /* sign extend field, stored in bit 0 */
177 #define SIGN0 (SIZE22 + 1)
178 { 'x', 1, 0, ARC_OPERAND_SUFFIX },
180 /* sign extend field, stored in bit 9 */
181 #define SIGN9 (SIGN0 + 1)
182 { 'X', 1, 9, ARC_OPERAND_SUFFIX },
184 /* address write back, stored in bit 3 */
185 #define ADDRESS3 (SIGN9 + 1)
186 { 'w', 1, 3, ARC_OPERAND_SUFFIX },
188 /* address write back, stored in bit 12 */
189 #define ADDRESS12 (ADDRESS3 + 1)
190 { 'W', 1, 12, ARC_OPERAND_SUFFIX },
192 /* address write back, stored in bit 24 */
193 #define ADDRESS24 (ADDRESS12 + 1)
194 { 'v', 1, 24, ARC_OPERAND_SUFFIX },
196 /* cache bypass, stored in bit 5 */
197 #define CACHEBYPASS5 (ADDRESS24 + 1)
198 { 'e', 1, 5, ARC_OPERAND_SUFFIX },
200 /* cache bypass, stored in bit 14 */
201 #define CACHEBYPASS14 (CACHEBYPASS5 + 1)
202 { 'E', 1, 14, ARC_OPERAND_SUFFIX },
204 /* cache bypass, stored in bit 26 */
205 #define CACHEBYPASS26 (CACHEBYPASS14 + 1)
206 { 'D', 1, 26, ARC_OPERAND_SUFFIX },
208 /* unop macro, used to copy REGB to REGC */
209 #define UNOPMACRO (CACHEBYPASS26 + 1)
210 { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
212 /* '.' modifier ('.' required). */
213 #define MODDOT (UNOPMACRO + 1)
214 { '.', 1, 0, ARC_MOD_DOT },
216 /* Dummy 'r' modifier for the register table.
217 It's called a "dummy" because there's no point in inserting an 'r' into all
218 the %a/%b/%c occurrences in the insn table. */
219 #define REG (MODDOT + 1)
220 { 'r', 6, 0, ARC_MOD_REG },
222 /* Known auxiliary register modifier (stored in shimm field). */
223 #define AUXREG (REG + 1)
224 { 'A', 9, 0, ARC_MOD_AUXREG },
226 /* end of list place holder */
230 /* Given a format letter, yields the index into `arc_operands'.
231 eg: arc_operand_map['a'] = REGA. */
232 unsigned char arc_operand_map[256];
234 #define I(x) (((x) & 31) << 27)
235 #define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
236 #define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
237 #define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
238 #define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
242 Longer versions of insns must appear before shorter ones (if gas sees
243 "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
244 junk). This isn't necessary for `ld' because of the trailing ']'.
246 Instructions that are really macros based on other insns must appear
247 before the real insn so they're chosen when disassembling. Eg: The `mov'
248 insn is really the `and' insn.
250 This table is best viewed on a wide screen (161 columns). I'd prefer to
251 keep it this way. The rest of the file, however, should be viewable on an
252 80 column terminal. */
254 /* ??? This table also includes macros: asl, lsl, and mov. The ppc port has
255 a more general facility for dealing with macros which could be used if
258 /* This table can't be `const' because members `next_asm' and `next_dis' are
259 computed at run-time. We could split this into two, but that doesn't seem
262 struct arc_opcode arc_opcodes[] = {
264 /* Macros appear first. */
265 /* "mov" is really an "and". */
266 { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) },
267 /* "asl" is really an "add". */
268 { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
269 /* "lsl" is really an "add". */
270 { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
271 /* "nop" is really an "xor". */
272 { "nop", 0xffffffff, 0x7fffffff },
273 /* "rlc" is really an "adc". */
274 { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
276 /* The rest of these needn't be sorted, but it helps to find them if they are. */
277 { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) },
278 { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) },
279 { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) },
280 { "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) },
281 { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) },
282 { "b%q%.n %B", I(-1), I(4), ARC_OPCODE_COND_BRANCH },
283 { "bl%q%.n %B", I(-1), I(5), ARC_OPCODE_COND_BRANCH },
284 { "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) },
285 { "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) },
286 { "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) },
287 /* %Q: force cond_p=1 --> no shimm values */
288 /* ??? This insn allows an optional flags spec. */
289 { "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) },
290 /* Put opcode 1 ld insns first so shimm gets prefered over limm. */
291 /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
292 { "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) },
293 { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) },
294 { "ld%z%.x%.w%.e%Q %a,[%b,%c]%L", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) },
295 { "lp%q%.n %B", I(-1), I(6), },
296 { "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) },
297 { "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) },
298 { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) },
299 { "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) },
300 { "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) },
301 { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) },
302 { "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) },
303 { "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) },
304 { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) },
305 /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
306 { "st%y%.v%.D%Q %0%c,[%b]%L", I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) },
307 { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,1)+R(-1,21,1), I(2)+R(0,25,1)+R(0,21,1) },
308 { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) },
309 { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) }
311 const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
313 const struct arc_operand_value arc_reg_names[] =
315 /* Sort this so that the first 61 entries are sequential.
316 IE: For each i (i<61), arc_reg_names[i].value == i. */
318 { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG },
319 { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG },
320 { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG },
321 { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG },
322 { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG },
323 { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG },
324 { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG },
325 { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG },
326 { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG },
327 { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG },
328 { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG },
329 { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG },
330 { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG },
331 { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG },
332 { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG },
333 { "lp_count", 60, REG },
335 /* I'd prefer to output these as "fp" and "sp" by default, but we still need
336 to recognize the canonical values. */
337 { "r27", 27, REG }, { "r28", 28, REG },
339 /* Someone may wish to refer to these in this way, and it's probably a
340 good idea to reserve them as such anyway. */
341 { "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG },
343 /* Standard auxiliary registers. */
344 { "status", 0, AUXREG },
345 { "semaphore", 1, AUXREG },
346 { "lp_start", 2, AUXREG },
347 { "lp_end", 3, AUXREG },
348 { "identity", 4, AUXREG },
349 { "debug", 5, AUXREG },
351 const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
354 Operands with the same name must be stored together. */
356 const struct arc_operand_value arc_suffixes[] =
358 /* Entry 0 is special, default values aren't printed by the disassembler. */
388 { "nd", ARC_DELAY_NONE, DELAY },
389 { "d", ARC_DELAY_NORMAL, DELAY },
390 { "jd", ARC_DELAY_JUMP, DELAY },
391 /*{ "b", 7, SIZEEXT },*/
392 /*{ "b", 5, SIZESEX },*/
396 /*{ "w", 8, SIZEEXT },*/
397 /*{ "w", 6, SIZESEX },*/
403 { "a", 1, ADDRESS3 },
404 { "a", 1, ADDRESS12 },
405 { "a", 1, ADDRESS24 },
406 { "di", 1, CACHEBYPASS5 },
407 { "di", 1, CACHEBYPASS14 },
408 { "di", 1, CACHEBYPASS26 },
410 const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
412 /* Indexed by first letter of opcode. Points to chain of opcodes with same
414 static struct arc_opcode *opcode_map[26 + 1];
416 /* Indexed by insn code. Points to chain of opcodes with same insn code. */
417 static struct arc_opcode *icode_map[32];
419 /* Configuration flags. */
421 /* Various ARC_HAVE_XXX bits. */
424 /* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */
427 arc_get_opcode_mach (bfd_mach, big_p)
430 static int mach_type_map[] =
435 return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0);
438 /* Initialize any tables that need it.
439 Must be called once at start up (or when first needed).
441 FLAGS is a set of bits that say what version of the cpu we have,
442 and in particular at least (one of) ARC_MACH_XXX. */
445 arc_opcode_init_tables (flags)
448 static int init_p = 0;
452 /* We may be intentionally called more than once (for example gdb will call
453 us each time the user switches cpu). These tables only need to be init'd
455 /* ??? We can remove the need for arc_opcode_supported by taking it into
456 account here, but I'm not sure I want to do that yet (if ever). */
461 memset (arc_operand_map, 0, sizeof (arc_operand_map));
462 n = sizeof (arc_operands) / sizeof (arc_operands[0]);
463 for (i = 0; i < n; ++i)
464 arc_operand_map[arc_operands[i].fmt] = i;
466 memset (opcode_map, 0, sizeof (opcode_map));
467 memset (icode_map, 0, sizeof (icode_map));
468 /* Scan the table backwards so macros appear at the front. */
469 for (i = arc_opcodes_count - 1; i >= 0; --i)
471 int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
472 int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
474 arc_opcodes[i].next_asm = opcode_map[opcode_hash];
475 opcode_map[opcode_hash] = &arc_opcodes[i];
477 arc_opcodes[i].next_dis = icode_map[icode_hash];
478 icode_map[icode_hash] = &arc_opcodes[i];
485 /* Return non-zero if OPCODE is supported on the specified cpu.
486 Cpu selection is made when calling `arc_opcode_init_tables'. */
489 arc_opcode_supported (opcode)
490 const struct arc_opcode *opcode;
492 if (ARC_OPCODE_CPU (opcode->flags) == 0)
494 if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type))
499 /* Return non-zero if OPVAL is supported on the specified cpu.
500 Cpu selection is made when calling `arc_opcode_init_tables'. */
503 arc_opval_supported (opval)
504 const struct arc_operand_value *opval;
506 if (ARC_OPVAL_CPU (opval->flags) == 0)
508 if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type))
513 /* Return the first insn in the chain for assembling INSN. */
515 const struct arc_opcode *
516 arc_opcode_lookup_asm (insn)
519 return opcode_map[ARC_HASH_OPCODE (insn)];
522 /* Return the first insn in the chain for disassembling INSN. */
524 const struct arc_opcode *
525 arc_opcode_lookup_dis (insn)
528 return icode_map[ARC_HASH_ICODE (insn)];
531 /* Nonzero if we've seen an 'f' suffix (in certain insns). */
534 /* Nonzero if we've finished processing the 'f' suffix. */
535 static int flagshimm_handled_p;
537 /* Nonzero if we've seen a 'q' suffix (condition code). */
540 /* Nonzero if we've inserted a shimm. */
543 /* The value of the shimm we inserted (each insn only gets one but it can
544 appear multiple times. */
547 /* Nonzero if we've inserted a limm (during assembly) or seen a limm
548 (during disassembly). */
551 /* The value of the limm we inserted. Each insn only gets one but it can
552 appear multiple times. */
555 /* Insertion functions. */
557 /* Called by the assembler before parsing an instruction. */
560 arc_opcode_init_insert ()
563 flagshimm_handled_p = 0;
569 /* Called by the assembler to see if the insn has a limm operand.
570 Also called by the disassembler to see if the insn contains a limm. */
573 arc_opcode_limm_p (limmp)
581 /* Insert a value into a register field.
582 If REG is NULL, then this is actually a constant.
584 We must also handle auxiliary registers for lr/sr insns. */
587 insert_reg (insn, operand, mods, reg, value, errmsg)
589 const struct arc_operand *operand;
591 const struct arc_operand_value *reg;
595 static char buf[100];
599 /* We have a constant that also requires a value stored in a register
600 field. Handle these by updating the register field and saving the
601 value for later handling by either %S (shimm) or %L (limm). */
603 /* Try to use a shimm value before a limm one. */
604 if (ARC_SHIMM_CONST_P (value)
605 /* If we've seen a conditional suffix we have to use a limm. */
607 /* If we already have a shimm value that is different than ours
608 we have to use a limm. */
609 && (!shimm_p || shimm == value))
611 int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
612 flagshimm_handled_p = 1;
615 insn |= marker << operand->shift;
616 /* insn |= value & 511; - done later */
618 /* We have to use a limm. If we've already seen one they must match. */
619 else if (!limm_p || limm == value)
623 insn |= ARC_REG_LIMM << operand->shift;
624 /* The constant is stored later. */
628 *errmsg = "unable to fit different valued constants into instruction";
633 /* We have to handle both normal and auxiliary registers. */
635 if (reg->type == AUXREG)
637 if (!(mods & ARC_MOD_AUXREG))
638 *errmsg = "auxiliary register not allowed here";
641 insn |= ARC_REG_SHIMM << operand->shift;
642 insn |= reg->value << arc_operands[reg->type].shift;
647 /* We should never get an invalid register number here. */
648 if ((unsigned int) reg->value > 60)
650 sprintf (buf, "invalid register number `%d'", reg->value);
654 insn |= reg->value << operand->shift;
661 /* Called when we see an 'f' flag. */
664 insert_flag (insn, operand, mods, reg, value, errmsg)
666 const struct arc_operand *operand;
668 const struct arc_operand_value *reg;
672 /* We can't store anything in the insn until we've parsed the registers.
673 Just record the fact that we've got this flag. `insert_reg' will use it
674 to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */
680 /* Called after completely building an insn to ensure the 'f' flag gets set
681 properly. This is needed because we don't know how to set this flag until
682 we've parsed the registers. */
685 insert_flagfinish (insn, operand, mods, reg, value, errmsg)
687 const struct arc_operand *operand;
689 const struct arc_operand_value *reg;
693 if (flag_p && !flagshimm_handled_p)
697 flagshimm_handled_p = 1;
698 insn |= (1 << operand->shift);
703 /* Called when we see a conditional flag (eg: .eq). */
706 insert_cond (insn, operand, mods, reg, value, errmsg)
708 const struct arc_operand *operand;
710 const struct arc_operand_value *reg;
715 insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
719 /* Used in the "j" instruction to prevent constants from being interpreted as
720 shimm values (which the jump insn doesn't accept). This can also be used
721 to force the use of limm values in other situations (eg: ld r0,[foo] uses
723 ??? The mechanism is sound. Access to it is a bit klunky right now. */
726 insert_forcelimm (insn, operand, mods, reg, value, errmsg)
728 const struct arc_operand *operand;
730 const struct arc_operand_value *reg;
738 /* Used in ld/st insns to handle the shimm offset field. */
741 insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
743 const struct arc_operand *operand;
745 const struct arc_operand_value *reg;
750 static char buf[100];
754 *errmsg = "register appears where shimm value expected";
758 /* This is *way* more general than necessary, but maybe some day it'll
760 if (operand->flags & ARC_OPERAND_SIGNED)
762 minval = -(1 << (operand->bits - 1));
763 maxval = (1 << (operand->bits - 1)) - 1;
768 maxval = (1 << operand->bits) - 1;
770 if (value < minval || value > maxval)
772 sprintf (buf, "value won't fit in range %ld - %ld",
777 insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
782 /* Used in ld/st insns when the shimm offset is 0. */
785 insert_shimmzero (insn, operand, mods, reg, value, errmsg)
787 const struct arc_operand *operand;
789 const struct arc_operand_value *reg;
798 /* Called at the end of processing normal insns (eg: add) to insert a shimm
799 value (if present) into the insn. */
802 insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
804 const struct arc_operand *operand;
806 const struct arc_operand_value *reg;
811 insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
815 /* Called at the end of processing normal insns (eg: add) to insert a limm
816 value (if present) into the insn.
818 Note that this function is only intended to handle instructions (with 4 byte
819 immediate operands). It is not intended to handle data. */
821 /* ??? Actually, there's nothing for us to do as we can't call frag_more, the
822 caller must do that. The extract fns take a pointer to two words. The
823 insert fns could be converted and then we could do something useful, but
824 then the reloc handlers would have to know to work on the second word of
825 a 2 word quantity. That's too much so we don't handle them. */
828 insert_limmfinish (insn, operand, mods, reg, value, errmsg)
830 const struct arc_operand *operand;
832 const struct arc_operand_value *reg;
837 ; /* nothing to do, gas does it */
841 /* Called at the end of unary operand macros to copy the B field to C. */
844 insert_unopmacro (insn, operand, mods, reg, value, errmsg)
846 const struct arc_operand *operand;
848 const struct arc_operand_value *reg;
852 insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
856 /* Insert a relative address for a branch insn (b, bl, or lp). */
859 insert_reladdr (insn, operand, mods, reg, value, errmsg)
861 const struct arc_operand *operand;
863 const struct arc_operand_value *reg;
868 *errmsg = "branch address not on 4 byte boundary";
869 insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
873 /* Insert a limm value as a 26 bit address right shifted 2 into the insn.
875 Note that this function is only intended to handle instructions (with 4 byte
876 immediate operands). It is not intended to handle data. */
878 /* ??? Actually, there's nothing for us to do as we can't call frag_more, the
879 caller must do that. The extract fns take a pointer to two words. The
880 insert fns could be converted and then we could do something useful, but
881 then the reloc handlers would have to know to work on the second word of
882 a 2 word quantity. That's too much so we don't handle them. */
885 insert_absaddr (insn, operand, mods, reg, value, errmsg)
887 const struct arc_operand *operand;
889 const struct arc_operand_value *reg;
894 ; /* nothing to do */
898 /* Extraction functions.
900 The suffix extraction functions' return value is redundant since it can be
901 obtained from (*OPVAL)->value. However, the boolean suffixes don't have
902 a suffix table entry for the "false" case, so values of zero must be
903 obtained from the return value (*OPVAL == NULL). */
905 static const struct arc_operand_value *lookup_register (int type, long regno);
907 /* Called by the disassembler before printing an instruction. */
910 arc_opcode_init_extract ()
913 flagshimm_handled_p = 0;
918 /* As we're extracting registers, keep an eye out for the 'f' indicator
919 (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker,
920 like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register.
922 We must also handle auxiliary registers for lr/sr insns. They are just
923 constants with special names. */
926 extract_reg (insn, operand, mods, opval, invalid)
928 const struct arc_operand *operand;
930 const struct arc_operand_value **opval;
936 /* Get the register number. */
937 regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
939 /* Is it a constant marker? */
940 if (regno == ARC_REG_SHIMM)
942 value = insn[0] & 511;
943 if ((operand->flags & ARC_OPERAND_SIGNED)
946 flagshimm_handled_p = 1;
948 else if (regno == ARC_REG_SHIMM_UPDATE)
950 value = insn[0] & 511;
951 if ((operand->flags & ARC_OPERAND_SIGNED)
955 flagshimm_handled_p = 1;
957 else if (regno == ARC_REG_LIMM)
962 /* It's a register, set OPVAL (that's the only way we distinguish registers
963 from constants here). */
966 const struct arc_operand_value *reg = lookup_register (REG, regno);
975 /* If this field takes an auxiliary register, see if it's a known one. */
976 if ((mods & ARC_MOD_AUXREG)
977 && ARC_REG_CONSTANT_P (regno))
979 const struct arc_operand_value *reg = lookup_register (AUXREG, value);
981 /* This is really a constant, but tell the caller it has a special
983 if (reg != NULL && opval != NULL)
990 /* Return the value of the "flag update" field for shimm insns.
991 This value is actually stored in the register field. */
994 extract_flag (insn, operand, mods, opval, invalid)
996 const struct arc_operand *operand;
998 const struct arc_operand_value **opval;
1002 const struct arc_operand_value *val;
1004 if (flagshimm_handled_p)
1007 f = (insn[0] & (1 << operand->shift)) != 0;
1009 /* There is no text for zero values. */
1013 val = arc_opcode_lookup_suffix (operand, 1);
1014 if (opval != NULL && val != NULL)
1019 /* Extract the condition code (if it exists).
1020 If we've seen a shimm value in this insn (meaning that the insn can't have
1021 a condition code field), then we don't store anything in OPVAL and return
1025 extract_cond (insn, operand, mods, opval, invalid)
1027 const struct arc_operand *operand;
1029 const struct arc_operand_value **opval;
1033 const struct arc_operand_value *val;
1035 if (flagshimm_handled_p)
1038 cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
1039 val = arc_opcode_lookup_suffix (operand, cond);
1041 /* Ignore NULL values of `val'. Several condition code values are
1042 reserved for extensions. */
1043 if (opval != NULL && val != NULL)
1048 /* Extract a branch address.
1049 We return the value as a real address (not right shifted by 2). */
1052 extract_reladdr (insn, operand, mods, opval, invalid)
1054 const struct arc_operand *operand;
1056 const struct arc_operand_value **opval;
1061 addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
1062 if ((operand->flags & ARC_OPERAND_SIGNED)
1063 && (addr & (1 << (operand->bits - 1))))
1064 addr -= 1 << operand->bits;
1069 /* The only thing this does is set the `invalid' flag if B != C.
1070 This is needed because the "mov" macro appears before it's real insn "and"
1071 and we don't want the disassembler to confuse them. */
1074 extract_unopmacro (insn, operand, mods, opval, invalid)
1076 const struct arc_operand *operand;
1078 const struct arc_operand_value **opval;
1081 /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
1082 C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
1083 printed as "and"s. */
1084 if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG)
1085 != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG))
1086 if (invalid != NULL)
1092 /* Utility for the extraction functions to return the index into
1095 const struct arc_operand_value *
1096 arc_opcode_lookup_suffix (type, value)
1097 const struct arc_operand *type;
1100 register const struct arc_operand_value *v,*end;
1102 /* ??? This is a little slow and can be speeded up. */
1104 for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v)
1105 if (type == &arc_operands[v->type]
1106 && value == v->value)
1111 static const struct arc_operand_value *
1112 lookup_register (type, regno)
1116 register const struct arc_operand_value *r,*end;
1119 return &arc_reg_names[regno];
1121 /* ??? This is a little slow and can be speeded up. */
1123 for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count;
1125 if (type == r->type && regno == r->value)