1 /* ===-- clear_cache.c - Implement __clear_cache ---------------------------===
3 * The LLVM Compiler Infrastructure
5 * This file is dual licensed under the MIT and the University of Illinois Open
6 * Source Licenses. See LICENSE.TXT for details.
8 * ===----------------------------------------------------------------------===
15 #include <libkern/OSCacheControl.h>
17 #if defined(__FreeBSD__) && defined(__arm__)
18 #include <sys/types.h>
19 #include <machine/sysarch.h>
22 #if defined(__NetBSD__) && defined(__arm__)
23 #include <machine/sysarch.h>
26 #if defined(__mips__) && !defined(__FreeBSD__)
27 #include <sys/cachectl.h>
28 #include <sys/syscall.h>
29 #if defined(__ANDROID__) && defined(__LP64__)
31 * clear_mips_cache - Invalidates instruction cache for Mips.
33 static void clear_mips_cache(const void* Addr, size_t Size) {
38 "beq %[Size], $zero, 20f\n" /* If size == 0, branch around. */
40 "daddu %[Size], %[Addr], %[Size]\n" /* Calculate end address + 1 */
41 "rdhwr $v0, $1\n" /* Get step size for SYNCI.
42 $1 is $HW_SYNCI_Step */
43 "beq $v0, $zero, 20f\n" /* If no caches require
44 synchronization, branch
48 "synci 0(%[Addr])\n" /* Synchronize all caches around
50 "daddu %[Addr], %[Addr], $v0\n" /* Add step size. */
51 "sltu $at, %[Addr], %[Size]\n" /* Compare current with end
53 "bne $at, $zero, 10b\n" /* Branch if more to do. */
55 "sync\n" /* Clear memory hazards. */
60 "daddiu $ra, $ra, 12\n" /* $ra has a value of $pc here.
61 Add offset of 12 to point to the
62 instruction after the last nop.
64 "jr.hb $ra\n" /* Return, clearing instruction
68 : [Addr] "+r"(Addr), [Size] "+r"(Size)
69 :: "at", "ra", "v0", "memory"
75 #if defined(__ANDROID__) && defined(__arm__)
76 #include <asm/unistd.h>
80 * The compiler generates calls to __clear_cache() when creating
81 * trampoline functions on the stack for use with nested functions.
82 * It is expected to invalidate the instruction cache for the
86 void __clear_cache(void *start, void *end) {
87 #if __i386__ || __x86_64__
89 * Intel processors have a unified instruction and data cache
90 * so there is nothing to do
92 #elif defined(__arm__) && !defined(__APPLE__)
93 #if defined(__FreeBSD__) || defined(__NetBSD__)
94 struct arm_sync_icache_args arg;
96 arg.addr = (uintptr_t)start;
97 arg.len = (uintptr_t)end - (uintptr_t)start;
99 sysarch(ARM_SYNC_ICACHE, &arg);
100 #elif defined(__ANDROID__)
101 register int start_reg __asm("r0") = (int) (intptr_t) start;
102 const register int end_reg __asm("r1") = (int) (intptr_t) end;
103 const register int flags __asm("r2") = 0;
104 const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
105 __asm __volatile("svc 0x0" : "=r"(start_reg)
106 : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags) : "r0");
107 if (start_reg != 0) {
113 #elif defined(__mips__) && !defined(__FreeBSD__)
114 const uintptr_t start_int = (uintptr_t) start;
115 const uintptr_t end_int = (uintptr_t) end;
116 #if defined(__ANDROID__) && defined(__LP64__)
117 // Call synci implementation for short address range.
118 const uintptr_t address_range_limit = 256;
119 if ((end_int - start_int) <= address_range_limit) {
120 clear_mips_cache(start, (end_int - start_int));
122 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
125 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
127 #elif defined(__aarch64__) && !defined(__APPLE__)
128 uint64_t xstart = (uint64_t)(uintptr_t) start;
129 uint64_t xend = (uint64_t)(uintptr_t) end;
131 // Get Cache Type Info
133 __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
136 * dc & ic instructions must use 64bit registers so we don't use
137 * uintptr_t in case this runs in an IPL32 environment.
139 const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
140 for (uint64_t addr = xstart; addr < xend; addr += dcache_line_size)
141 __asm __volatile("dc cvau, %0" :: "r"(addr));
142 __asm __volatile("dsb ish");
144 const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
145 for (uint64_t addr = xstart; addr < xend; addr += icache_line_size)
146 __asm __volatile("ic ivau, %0" :: "r"(addr));
147 __asm __volatile("isb sy");
150 /* On Darwin, sys_icache_invalidate() provides this functionality */
151 sys_icache_invalidate(start, end-start);