1 /* ===-- clear_cache.c - Implement __clear_cache ---------------------------===
3 * The LLVM Compiler Infrastructure
5 * This file is dual licensed under the MIT and the University of Illinois Open
6 * Source Licenses. See LICENSE.TXT for details.
8 * ===----------------------------------------------------------------------===
15 #include <libkern/OSCacheControl.h>
19 /* Forward declare Win32 APIs since the GCC mode driver does not handle the
20 newer SDKs as well as needed. */
21 uint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress,
23 uintptr_t GetCurrentProcess(void);
26 #if (defined(__FreeBSD__) || defined(__Bitrig__)) && defined(__arm__)
27 #include <sys/types.h>
28 #include <machine/sysarch.h>
31 #if defined(__NetBSD__) && defined(__arm__)
32 #include <machine/sysarch.h>
35 #if defined(__mips__) && !defined(__FreeBSD__)
36 #include <sys/cachectl.h>
37 #include <sys/syscall.h>
39 #if defined(__ANDROID__) && defined(__LP64__)
41 * clear_mips_cache - Invalidates instruction cache for Mips.
43 static void clear_mips_cache(const void* Addr, size_t Size) {
48 "beq %[Size], $zero, 20f\n" /* If size == 0, branch around. */
50 "daddu %[Size], %[Addr], %[Size]\n" /* Calculate end address + 1 */
51 "rdhwr $v0, $1\n" /* Get step size for SYNCI.
52 $1 is $HW_SYNCI_Step */
53 "beq $v0, $zero, 20f\n" /* If no caches require
54 synchronization, branch
58 "synci 0(%[Addr])\n" /* Synchronize all caches around
60 "daddu %[Addr], %[Addr], $v0\n" /* Add step size. */
61 "sltu $at, %[Addr], %[Size]\n" /* Compare current with end
63 "bne $at, $zero, 10b\n" /* Branch if more to do. */
65 "sync\n" /* Clear memory hazards. */
70 "daddiu $ra, $ra, 12\n" /* $ra has a value of $pc here.
71 Add offset of 12 to point to the
72 instruction after the last nop.
74 "jr.hb $ra\n" /* Return, clearing instruction
78 : [Addr] "+r"(Addr), [Size] "+r"(Size)
79 :: "at", "ra", "v0", "memory"
86 * The compiler generates calls to __clear_cache() when creating
87 * trampoline functions on the stack for use with nested functions.
88 * It is expected to invalidate the instruction cache for the
92 void __clear_cache(void *start, void *end) {
93 #if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64)
95 * Intel processors have a unified instruction and data cache
96 * so there is nothing to do
98 #elif defined(__arm__) && !defined(__APPLE__)
99 #if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__Bitrig__)
100 struct arm_sync_icache_args arg;
102 arg.addr = (uintptr_t)start;
103 arg.len = (uintptr_t)end - (uintptr_t)start;
105 sysarch(ARM_SYNC_ICACHE, &arg);
106 #elif defined(__linux__)
108 * We used to include asm/unistd.h for the __ARM_NR_cacheflush define, but
109 * it also brought many other unused defines, as well as a dependency on
110 * kernel headers to be installed.
112 * This value is stable at least since Linux 3.13 and should remain so for
113 * compatibility reasons, warranting it's re-definition here.
115 #define __ARM_NR_cacheflush 0x0f0002
116 register int start_reg __asm("r0") = (int) (intptr_t) start;
117 const register int end_reg __asm("r1") = (int) (intptr_t) end;
118 const register int flags __asm("r2") = 0;
119 const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
120 __asm __volatile("svc 0x0"
122 : "r"(syscall_nr), "r"(start_reg), "r"(end_reg),
124 if (start_reg != 0) {
127 #elif defined(_WIN32)
128 FlushInstructionCache(GetCurrentProcess(), start, end - start);
132 #elif defined(__mips__) && !defined(__FreeBSD__)
133 const uintptr_t start_int = (uintptr_t) start;
134 const uintptr_t end_int = (uintptr_t) end;
135 #if defined(__ANDROID__) && defined(__LP64__)
136 // Call synci implementation for short address range.
137 const uintptr_t address_range_limit = 256;
138 if ((end_int - start_int) <= address_range_limit) {
139 clear_mips_cache(start, (end_int - start_int));
141 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
144 syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
146 #elif defined(__aarch64__) && !defined(__APPLE__)
147 uint64_t xstart = (uint64_t)(uintptr_t) start;
148 uint64_t xend = (uint64_t)(uintptr_t) end;
151 // Get Cache Type Info
153 __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
156 * dc & ic instructions must use 64bit registers so we don't use
157 * uintptr_t in case this runs in an IPL32 environment.
159 const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
160 for (addr = xstart; addr < xend; addr += dcache_line_size)
161 __asm __volatile("dc cvau, %0" :: "r"(addr));
162 __asm __volatile("dsb ish");
164 const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
165 for (addr = xstart; addr < xend; addr += icache_line_size)
166 __asm __volatile("ic ivau, %0" :: "r"(addr));
167 __asm __volatile("isb sy");
170 /* On Darwin, sys_icache_invalidate() provides this functionality */
171 sys_icache_invalidate(start, end-start);