1 /* Copyright (c) 2012, Linaro Limited
4 Redistribution and use in source and binary forms, with or without
5 modification, are permitted provided that the following conditions are met:
6 * Redistributions of source code must retain the above copyright
7 notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright
9 notice, this list of conditions and the following disclaimer in the
10 documentation and/or other materials provided with the distribution.
11 * Neither the name of the Linaro nor the
12 names of its contributors may be used to endorse or promote products
13 derived from this software without specific prior written permission.
15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28 * Copyright (c) 2015 ARM Ltd
29 * All rights reserved.
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
34 * 1. Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * 2. Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in the
38 * documentation and/or other materials provided with the distribution.
39 * 3. The name of the company may not be used to endorse or promote
40 * products derived from this software without specific prior written
43 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
46 * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
48 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
49 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
50 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
51 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
52 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * ARMv8-a, AArch64, unaligned accesses
77 .macro def_fn f p2align=0
85 def_fn memset p2align=6
88 add dstend, dstin, count
96 /* Set 0..15 bytes. */
104 str valw, [dstend, -4]
109 strh valw, [dstend, -2]
112 /* Set 17..96 bytes. */
115 tbnz count, 6, L(set96)
116 str q0, [dstend, -16]
119 str q0, [dstend, -32]
123 /* Set 64..96 bytes. Write 64 bytes from the start and
124 32 bytes from the end. */
127 stp q0, q0, [dstin, 32]
128 stp q0, q0, [dstend, -32]
141 sub count, dstend, dst /* Count is 16 too large. */
143 sub count, count, 64 + 16 /* Adjust count and bias for loop. */
144 1: stp q0, q0, [dst], 64
145 stp q0, q0, [dst, -32]
147 subs count, count, 64
149 2: stp q0, q0, [dstend, -64]
150 stp q0, q0, [dstend, -32]
156 tbnz tmp1w, 4, L(no_zva)
158 cmp tmp1w, 4 /* ZVA size is 64 bytes. */
161 /* Write the first and last 64 byte aligned block using stp rather
162 than using DC ZVA. This is faster on some cores.
166 stp q0, q0, [dst, 32]
168 stp q0, q0, [dst, 64]
169 stp q0, q0, [dst, 96]
170 sub count, dstend, dst /* Count is now 128 too large. */
171 sub count, count, 128+64+64 /* Adjust count and bias for loop. */
176 subs count, count, 64
179 stp q0, q0, [dst, 32]
180 stp q0, q0, [dstend, -64]
181 stp q0, q0, [dstend, -32]
186 cmp tmp1w, 5 /* ZVA size is 128 bytes. */
190 stp q0, q0, [dst, 32]
191 stp q0, q0, [dst, 64]
192 stp q0, q0, [dst, 96]
194 sub count, dstend, dst /* Count is now 128 too large. */
195 sub count, count, 128+128 /* Adjust count and bias for loop. */
199 subs count, count, 128
201 stp q0, q0, [dstend, -128]
202 stp q0, q0, [dstend, -96]
203 stp q0, q0, [dstend, -64]
204 stp q0, q0, [dstend, -32]
209 lsl zva_lenw, tmp2w, tmp1w
210 add tmp1, zva_len, 64 /* Max alignment bytes written. */
215 add tmp1, dst, zva_len
217 subs count, tmp1, dst /* Actual alignment bytes to write. */
218 bic tmp1, tmp1, tmp2 /* Aligned dc zva start address. */
220 1: stp q0, q0, [dst], 64
221 stp q0, q0, [dst, -32]
222 subs count, count, 64
225 sub count, dstend, tmp1 /* Remaining bytes to write. */
226 subs count, count, zva_len
229 add dst, dst, zva_len
230 subs count, count, zva_len
232 4: add count, count, zva_len
235 .size memset, . - memset