1 2007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r125346)
4 * doc/extend.texi: Document the 0b-prefixed binary integer
7 2007-05-03 Ian Lance Taylor <iant@google.com> (r124381)
9 * config/rs6000/rs6000.c (rs6000_override_options): Don't set
10 MASK_PPC_GFXOPT for 8540 or 8548.
12 2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341)
14 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
17 2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339)
19 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
20 and athlon64-sse3 as improved versions of k8, opteron and athlon64
21 with SSE3 instruction set support.
22 * doc/invoke.texi: Likewise.
24 2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330)
26 * config/i386/i386.c (override_options): Tuning 32-byte loop
27 alignment for amdfam10 architecture. Increasing the max loop
28 alignment to 24 bytes.
30 2007-04-16 Lawrence Crowl <crowl@google.com>
32 * doc/invoke.texi (Debugging Options): Add documentation for the
33 -femit-struct-debug options -femit-struct-debug-baseonly,
34 -femit-struct-debug-reduced, and
35 -femit-struct-debug-detailed[=...].
37 * c-opts.c (c_common_handle_option): Add
38 OPT_femit_struct_debug_baseonly, OPT_femit_struct_debug_reduced,
39 and OPT_femit_struct_debug_detailed_.
40 * c.opt: Add specifications for
41 -femit-struct-debug-baseonly, -femit-struct-debug-reduced,
42 and -femit-struct-debug-detailed[=...].
43 * opts.c (set_struct_debug_option): Parse the
44 -femit-struct-debug-... options.
45 * opts.c (matches_main_base, main_input_basename,
46 main_input_baselength, base_of_path, matches_main_base): Add
47 variables and functions to compare header base name to compilation
49 * opts.c (should_emit_struct_debug): Add to determine to emit a
50 structure based on the option.
51 (dump_struct_debug) Also disabled function to debug this
53 * opts.c (handle_options): Save the base name of the
56 * langhooks-def.h (LANG_HOOKS_GENERIC_TYPE_P): Define.
57 (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add.
58 This hook indicates if a type is generic. Set it by default
60 * langhooks.h (struct lang_hooks_for_types): Add a new hook
61 to determine if a struct type is generic or not.
62 * cp/cp-tree.h (class_tmpl_impl_spec_p): Declare a C++ hook.
63 * cp/tree.c (class_tmpl_impl_spec_p): Implement the C++ hook.
64 * cp/cp-lang.c (LANG_HOOKS_GENERIC_TYPE_P): Override null C hook
67 * flags.h (enum debug_info_usage): Add an enumeration to describe
68 a program's use of a structure type.
69 * dwarf2out.c (gen_struct_or_union_type_die): Add a new parameter
70 to indicate the program's usage of the type. Filter structs based
71 on the -femit-struct-debug-... specification.
72 (gen_type_die): Split into two routines, gen_type_die and
73 gen_type_die_with_usage. gen_type_die is now a wrapper
74 that assumes direct usage.
75 (gen_type_die_with_usage): Replace calls to gen_type_die
76 with gen_type_die_with_usage adding the program usage of
78 (dwarf2out_imported_module_or_decl): Suppress struct debug
79 information using should_emit_struct_debug when appropriate.
81 2007-04-12 Richard Guenther <rguenther@suse.de> (r123736)
83 PR tree-optimization/24689
84 PR tree-optimization/31307
85 * fold-const.c (operand_equal_p): Compare INTEGER_CST array
87 * gimplify.c (canonicalize_addr_expr): To be consistent with
88 gimplify_compound_lval only set operands two and three of
89 ARRAY_REFs if they are not gimple_min_invariant. This makes
90 it never at this place.
91 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise.
93 2007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639)
95 * config/i386/i386.c (ix86_handle_option): Handle SSSE3.
97 2007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313)
99 * config.gcc: Accept barcelona as a variant of amdfam10.
100 * config/i386/i386.c (override_options): Likewise.
101 * doc/invoke.texi: Likewise.
103 2007-03-12 Seongbae Park <seongbae.park@gmail.com>
105 * c-decl.c (warn_variable_length_array): New function.
106 Refactored from grokdeclarator to handle warn_vla
107 and handle unnamed array case.
108 (grokdeclarator): Refactored VLA warning case.
109 * c.opt (Wvla): New flag.
111 2007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial)
113 * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and
114 the *_DIV_EXPR codes correctly with overflow infinities.
116 2007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763)
118 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10.
121 2007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726)
123 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h
124 conditional to __SSE2__.
125 (Entries below should have been added to first ChangeLog
126 entry for amdfam10 dated 2007-02-05)
127 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not
129 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not
131 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not
134 2007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687)
136 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2.
138 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
140 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8,
141 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov,
142 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul,
143 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn,
144 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8,
145 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load,
146 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8,
147 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10.
149 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
151 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse,
152 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387,
153 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse,
154 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse,
155 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed,
156 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse,
157 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1,
158 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn,
159 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn,
160 umuldi3_highpart_rex64, umulsi3_highpart_insn,
161 umulsi3_highpart_zext, smuldi3_highpart_rex64,
162 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld,
163 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse,
164 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387,
165 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387,
166 sqrtextenddfxf2_i387): Added amdfam10_decode.
168 * config/i386/athlon.md (athlon_idirect_amdfam10,
169 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10,
170 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10,
171 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10,
172 athlon_ivector_store_amdfam10): New define_insn_reservation.
173 (athlon_idirect_loadmov, athlon_idirect_movstore): Added
176 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
178 * config/i386/athlon.md (athlon_call_amdfam10,
179 athlon_pop_amdfam10, athlon_lea_amdfam10): New
180 define_insn_reservation.
181 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8,
182 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI,
183 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10.
185 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
187 * config/i386/athlon.md (athlon_sseld_amdfam10,
188 athlon_mmxld_amdfam10, athlon_ssest_amdfam10,
189 athlon_mmxssest_short_amdfam10): New define_insn_reservation.
191 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
193 * config/i386/athlon.md (athlon_sseins_amdfam10): New
194 define_insn_reservation.
195 * config/i386/i386.md (sseins): Added sseins to define_attr type
196 and define_attr unit.
197 * config/i386/sse.md: Set type attribute to sseins for insertq
200 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
202 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10,
203 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10,
204 ssecomi_load_amdfam10, ssecomi_amdfam10,
205 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New
206 define_insn_reservation.
207 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10.
209 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
211 * config/i386/athlon.md (cvtss2sd_load_amdfam10,
212 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10,
213 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10,
214 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10,
215 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10,
216 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New
217 define_insn_reservation.
219 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si,
220 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq,
221 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq,
222 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd,
223 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute.
225 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
227 * config/i386/athlon.md (athlon_ssedivvector_amdfam10,
228 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10,
229 athlon_ssemulvector_load_amdfam10): New define_insn_reservation.
230 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul,
231 athlon_ssemul_load_k8): Added amdfam10.
233 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
235 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro.
236 (x86_sse_unaligned_move_optimal): New variable.
238 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for
240 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups
241 for unaligned vector SSE double/single precision loads for AMDFAM10.
243 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
245 * config/i386/i386.h (TARGET_AMDFAM10): New macro.
246 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10.
247 Define TARGET_CPU_DEFAULT_amdfam10.
248 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10.
249 (processor_type): Add PROCESSOR_AMDFAM10.
251 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match
252 processor_type in config/i386/i386.h.
253 Enable imul peepholes for TARGET_AMDFAM10.
255 * config.gcc: Add support for --with-cpu option for amdfam10.
257 * config/i386/i386.c (amdfam10_cost): New variable.
258 (m_AMDFAM10): New macro.
259 (m_ATHLON_K8_AMDFAM10): New macro.
260 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
261 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop,
262 x86_promote_QImode, x86_integer_DFmode_moves,
263 x86_partial_reg_dependency, x86_memory_mismatch_stall,
264 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387,
265 x86_sse_partial_reg_dependency, x86_sse_typeless_stores,
266 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit,
267 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns):
268 Enable/disable for amdfam10.
269 (override_options): Add amdfam10_cost to processor_target_table.
270 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in
271 processor_alias_table.
272 (ix86_issue_rate): Add PROCESSOR_AMDFAM10.
273 (ix86_adjust_cost): Add code for amdfam10.
275 2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
277 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm)
278 instruction set feature flag. Add new (-mpopcnt) flag for popcnt
279 instruction. Add new SSE4A (-msse4a) instruction set feature flag.
280 * config/i386/i386.h: Add builtin definition for SSE4A.
281 * config/i386/i386.md: Add support for ABM instructions
283 * config/i386/sse.md: Add support for SSE4A instructions
284 (movntss, movntsd, extrq, insertq).
285 * config/i386/i386.c: Add support for ABM and SSE4A builtins.
286 Add -march=amdfam10 flag.
287 * config/i386/ammintrin.h: Add support for SSE4A intrinsics.
288 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt
290 * doc/extend.texi: Add documentation for SSE4A builtins.
292 2007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140)
294 * config/i386/i386.h (x86_cmpxchg16b): Remove const.
295 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b.
296 * config/i386/i386.c (x86_cmpxchg16b): Remove const.
297 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b
298 for CPUs that have PTA_CX16 set.
300 2007-01-17 Eric Christopher <echristo@apple.com> (r120846)
302 * config.gcc: Support core2 processor.
304 2006-12-13 Ian Lance Taylor <iant@google.com> (r119855)
308 * c-typeck.c (parser_build_binary_op): Move parentheses warnings
309 to warn_about_parentheses in c-common.c.
310 * c-common.c (warn_about_parentheses): New function.
311 * c-common.h (warn_about_parentheses): Declare.
312 * doc/invoke.texi (Warning Options): Update -Wparentheses
315 2006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial)
318 * config/i386/driver-i386.c (bit_SSSE3): New.
320 2006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260)
322 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2
325 2006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973)
327 * doc/invoke.texi (core2): Add item.
329 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
331 (TARGET_CPU_CPP_BUILTINS): Add code for core2.
332 (TARGET_CPU_DEFAULT_generic): Change value.
333 (TARGET_CPU_DEFAULT_NAMES): Add core2.
334 (processor_type): Add new constant PROCESSOR_CORE2.
336 * config/i386/i386.md (cpu): Add core2.
338 * config/i386/i386.c (core2_cost): New initialized variable.
339 (m_CORE2): New macro.
340 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
341 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop,
342 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
343 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
344 x86_partial_reg_dependency, x86_memory_mismatch_stall,
345 x86_accumulate_outgoing_args, x86_prologue_using_move,
346 x86_epilogue_using_move, x86_arch_always_fancy_math_387,
347 x86_sse_partial_reg_dependency, x86_rep_movl_optimal,
348 x86_use_incdec, x86_four_jump_limit, x86_schedule,
349 x86_pad_returns): Add m_CORE2.
350 (override_options): Add entries for Core2.
351 (ix86_issue_rate): Add case for Core2.
353 2006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090)
355 * config/i386/i386.h (TARGET_GEODE):
356 (TARGET_CPU_CPP_BUILTINS): Add code for geode.
357 (TARGET_CPU_DEFAULT_geode): New macro.
358 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2,
359 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon,
360 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8,
361 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott,
362 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase
364 (TARGET_CPU_DEFAULT_NAMES): Add geode.
365 (processor_type): Add PROCESSOR_GEODE.
367 * config/i386/i386.md: Include geode.md.
370 * config/i386/i386.c (geode_cost): New initialized global
372 (m_GEODE, m_K6_GEODE): New macros.
373 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf,
374 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4,
375 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants,
376 x86_schedule): Use m_K6_GEODE instead of m_K6.
377 (x86_movx, x86_cmove): Set up m_GEODE.
378 (x86_integer_DFmode_moves): Clear m_GEODE.
379 (processor_target_table): Add entry for geode.
380 (processor_alias_table): Ditto.
382 * config/i386/geode.md: New file.
384 * doc/invoke.texi: Add entry about geode processor.
386 2006-10-24 Richard Guenther <rguenther@suse.de> (r118001)
389 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES
390 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS
391 for deciding optimizations in consistency with fold-const.c
392 (fold_builtin_unordered_cmp): Likewise.
394 2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958)
396 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
397 (x86_64-*-*): Likewise.
399 * config/i386/i386.c (pta_flags): Add PTA_SSSE3.
400 (override_options): Check SSSE3.
401 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
402 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
403 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
404 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
405 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
406 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
407 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
408 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
409 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
410 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
411 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
412 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
413 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
414 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
415 IX86_BUILTIN_PABSD128.
416 (bdesc_2arg): Add SSSE3.
417 (bdesc_1arg): Likewise.
418 (ix86_init_mmx_sse_builtins): Support SSSE3.
419 (ix86_expand_builtin): Likewise.
420 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.
422 * config/i386/i386.md (UNSPEC_PSHUFB): New.
423 (UNSPEC_PSIGN): Likewise.
424 (UNSPEC_PALIGNR): Likewise.
425 Include mmx.md before sse.md.
427 * config/i386/i386.opt: Add -mssse3.
429 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3.
430 (ssse3_phaddwv4hi3): Likewise.
431 (ssse3_phadddv4si3): Likewise.
432 (ssse3_phadddv2si3): Likewise.
433 (ssse3_phaddswv8hi3): Likewise.
434 (ssse3_phaddswv4hi3): Likewise.
435 (ssse3_phsubwv8hi3): Likewise.
436 (ssse3_phsubwv4hi3): Likewise.
437 (ssse3_phsubdv4si3): Likewise.
438 (ssse3_phsubdv2si3): Likewise.
439 (ssse3_phsubswv8hi3): Likewise.
440 (ssse3_phsubswv4hi3): Likewise.
441 (ssse3_pmaddubswv8hi3): Likewise.
442 (ssse3_pmaddubswv4hi3): Likewise.
443 (ssse3_pmulhrswv8hi3): Likewise.
444 (ssse3_pmulhrswv4hi3): Likewise.
445 (ssse3_pshufbv16qi3): Likewise.
446 (ssse3_pshufbv8qi3): Likewise.
447 (ssse3_psign<mode>3): Likewise.
448 (ssse3_psign<mode>3): Likewise.
449 (ssse3_palignrti): Likewise.
450 (ssse3_palignrdi): Likewise.
451 (abs<mode>2): Likewise.
452 (abs<mode>2): Likewise.
454 * config/i386/tmmintrin.h: New file.
456 * doc/extend.texi: Document SSSE3 built-in functions.
458 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
460 2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959)
462 * config/i386/tmmintrin.h: Remove the duplicated content.
464 2006-10-21 Richard Guenther <rguenther@suse.de> (r117932)
466 PR tree-optimization/3511
467 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that
468 got new invariant arguments during PHI translation.
470 2006-10-21 Richard Guenther <rguenther@suse.de> (r117929)
472 * builtins.c (fold_builtin_classify): Fix typo.