1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
427 /* We'd like to catch as many invalid transformations here as
428 possible. Unfortunately, there are way too many mode changes
429 that are perfectly valid, so we'd waste too much effort for
430 little gain doing the checks here. Focus on catching invalid
431 transformations involving integer constants. */
432 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
433 && GET_CODE (newval) == CONST_INT)
435 /* Sanity check that we're replacing oldval with a CONST_INT
436 that is a valid sign-extension for the original mode. */
437 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
441 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
442 CONST_INT is not valid, because after the replacement, the
443 original mode would be gone. Unfortunately, we can't tell
444 when do_SUBST is called to replace the operand thereof, so we
445 perform this test on oldval instead, checking whether an
446 invalid replacement took place before we got here. */
447 if ((GET_CODE (oldval) == SUBREG
448 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
449 || (GET_CODE (oldval) == ZERO_EXTEND
450 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
455 buf = undobuf.frees, undobuf.frees = buf->next;
457 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->old_contents.r = oldval;
464 buf->next = undobuf.undos, undobuf.undos = buf;
467 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
469 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
470 for the value of a HOST_WIDE_INT value (including CONST_INT) is
474 do_SUBST_INT (into, newval)
475 unsigned int *into, newval;
478 unsigned int oldval = *into;
480 if (oldval == newval)
484 buf = undobuf.frees, undobuf.frees = buf->next;
486 buf = (struct undo *) xmalloc (sizeof (struct undo));
490 buf->old_contents.i = oldval;
493 buf->next = undobuf.undos, undobuf.undos = buf;
496 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
498 /* Main entry point for combiner. F is the first insn of the function.
499 NREGS is the first unused pseudo-reg number.
501 Return non-zero if the combiner has turned an indirect jump
502 instruction into a direct jump. */
504 combine_instructions (f, nregs)
513 rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
537 reg_last_set_nonzero_bits
538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies
540 = (char *) xmalloc (nregs * sizeof (char));
542 init_reg_last_arrays ();
544 init_recog_no_volatile ();
546 /* Compute maximum uid value so uid_cuid can be allocated. */
548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
549 if (INSN_UID (insn) > i)
552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
557 /* Don't use reg_nonzero_bits when computing it. This can cause problems
558 when, for example, we have j <<= 1 in a loop. */
560 nonzero_sign_valid = 0;
562 /* Compute the mapping from uids to cuids.
563 Cuids are numbers assigned to insns, like uids,
564 except that cuids increase monotonically through the code.
566 Scan all SETs and see if we can deduce anything about what
567 bits are known to be zero for some registers and how many copies
568 of the sign bit are known to exist for those registers.
570 Also set any known values so that we can use it while searching
571 for what bits are known to be set. */
575 /* We need to initialize it here, because record_dead_and_set_regs may call
577 subst_prev_insn = NULL_RTX;
579 setup_incoming_promotions ();
581 refresh_blocks = sbitmap_alloc (n_basic_blocks);
582 sbitmap_zero (refresh_blocks);
585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
587 uid_cuid[INSN_UID (insn)] = ++i;
593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
595 record_dead_and_set_regs (insn);
598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
599 if (REG_NOTE_KIND (links) == REG_INC)
600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
605 if (GET_CODE (insn) == CODE_LABEL)
609 nonzero_sign_valid = 1;
611 /* Now scan all the insns in forward order. */
613 this_basic_block = -1;
617 init_reg_last_arrays ();
618 setup_incoming_promotions ();
620 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
624 /* If INSN starts a new basic block, update our basic block number. */
625 if (this_basic_block + 1 < n_basic_blocks
626 && BLOCK_HEAD (this_basic_block + 1) == insn)
629 if (GET_CODE (insn) == CODE_LABEL)
632 else if (INSN_P (insn))
634 /* See if we know about function return values before this
635 insn based upon SUBREG flags. */
636 check_promoted_subreg (insn, PATTERN (insn));
638 /* Try this insn with each insn it links back to. */
640 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 if ((next = try_combine (insn, XEXP (links, 0),
642 NULL_RTX, &new_direct_jump_p)) != 0)
645 /* Try each sequence of three linked insns ending with this one. */
647 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
649 rtx link = XEXP (links, 0);
651 /* If the linked insn has been replaced by a note, then there
652 is no point in pursuing this chain any further. */
653 if (GET_CODE (link) == NOTE)
656 for (nextlinks = LOG_LINKS (link);
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, link,
661 &new_direct_jump_p)) != 0)
666 /* Try to combine a jump insn that uses CC0
667 with a preceding insn that sets CC0, and maybe with its
668 logical predecessor as well.
669 This is how we make decrement-and-branch insns.
670 We need this special code because data flow connections
671 via CC0 do not get entered in LOG_LINKS. */
673 if (GET_CODE (insn) == JUMP_INSN
674 && (prev = prev_nonnote_insn (insn)) != 0
675 && GET_CODE (prev) == INSN
676 && sets_cc0_p (PATTERN (prev)))
678 if ((next = try_combine (insn, prev,
679 NULL_RTX, &new_direct_jump_p)) != 0)
682 for (nextlinks = LOG_LINKS (prev); nextlinks;
683 nextlinks = XEXP (nextlinks, 1))
684 if ((next = try_combine (insn, prev,
686 &new_direct_jump_p)) != 0)
690 /* Do the same for an insn that explicitly references CC0. */
691 if (GET_CODE (insn) == INSN
692 && (prev = prev_nonnote_insn (insn)) != 0
693 && GET_CODE (prev) == INSN
694 && sets_cc0_p (PATTERN (prev))
695 && GET_CODE (PATTERN (insn)) == SET
696 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
698 if ((next = try_combine (insn, prev,
699 NULL_RTX, &new_direct_jump_p)) != 0)
702 for (nextlinks = LOG_LINKS (prev); nextlinks;
703 nextlinks = XEXP (nextlinks, 1))
704 if ((next = try_combine (insn, prev,
706 &new_direct_jump_p)) != 0)
710 /* Finally, see if any of the insns that this insn links to
711 explicitly references CC0. If so, try this insn, that insn,
712 and its predecessor if it sets CC0. */
713 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
714 if (GET_CODE (XEXP (links, 0)) == INSN
715 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
716 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
717 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
718 && GET_CODE (prev) == INSN
719 && sets_cc0_p (PATTERN (prev))
720 && (next = try_combine (insn, XEXP (links, 0),
721 prev, &new_direct_jump_p)) != 0)
725 /* Try combining an insn with two different insns whose results it
727 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
728 for (nextlinks = XEXP (links, 1); nextlinks;
729 nextlinks = XEXP (nextlinks, 1))
730 if ((next = try_combine (insn, XEXP (links, 0),
732 &new_direct_jump_p)) != 0)
735 if (GET_CODE (insn) != NOTE)
736 record_dead_and_set_regs (insn);
743 delete_noop_moves (f);
747 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
752 sbitmap_free (refresh_blocks);
753 free (reg_nonzero_bits);
754 free (reg_sign_bit_copies);
755 free (reg_last_death);
757 free (reg_last_set_value);
758 free (reg_last_set_table_tick);
759 free (reg_last_set_label);
760 free (reg_last_set_invalid);
761 free (reg_last_set_mode);
762 free (reg_last_set_nonzero_bits);
763 free (reg_last_set_sign_bit_copies);
767 struct undo *undo, *next;
768 for (undo = undobuf.frees; undo; undo = next)
776 total_attempts += combine_attempts;
777 total_merges += combine_merges;
778 total_extras += combine_extras;
779 total_successes += combine_successes;
781 nonzero_sign_valid = 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs = combine_max_regno;
796 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
797 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
798 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
800 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
801 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
802 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
803 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
804 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode;
817 rtx first = get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
827 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
830 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode, const0_rtx)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x, set, data)
853 void *data ATTRIBUTE_UNUSED;
857 if (GET_CODE (x) == REG
858 && REGNO (x) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
864 if (set == 0 || GET_CODE (set) == CLOBBER)
866 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
867 reg_sign_bit_copies[REGNO (x)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set = expand_field_assignment (set);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set) == x
879 || (GET_CODE (SET_DEST (set)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
882 && SUBREG_REG (SET_DEST (set)) == x))
884 rtx src = SET_SRC (set);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
897 && GET_CODE (src) == CONST_INT
899 && 0 != (INTVAL (src)
901 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
902 src = GEN_INT (INTVAL (src)
903 | ((HOST_WIDE_INT) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x))));
907 /* Don't call nonzero_bits if it cannot change anything. */
908 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
909 reg_nonzero_bits[REGNO (x)]
910 |= nonzero_bits (src, nonzero_bits_mode);
911 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
912 if (reg_sign_bit_copies[REGNO (x)] == 0
913 || reg_sign_bit_copies[REGNO (x)] > num)
914 reg_sign_bit_copies[REGNO (x)] = num;
918 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
919 reg_sign_bit_copies[REGNO (x)] = 1;
924 /* See if INSN can be combined into I3. PRED and SUCC are optionally
925 insns that were previously combined into I3 or that will be combined
926 into the merger of INSN and I3.
928 Return 0 if the combination is not allowed for any reason.
930 If the combination is allowed, *PDEST will be set to the single
931 destination of INSN and *PSRC to the single source, and this function
935 can_combine_p (insn, i3, pred, succ, pdest, psrc)
938 rtx pred ATTRIBUTE_UNUSED;
943 rtx set = 0, src, dest;
948 int all_adjacent = (succ ? (next_active_insn (insn) == succ
949 && next_active_insn (succ) == i3)
950 : next_active_insn (insn) == i3);
952 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
953 or a PARALLEL consisting of such a SET and CLOBBERs.
955 If INSN has CLOBBER parallel parts, ignore them for our processing.
956 By definition, these happen during the execution of the insn. When it
957 is merged with another insn, all bets are off. If they are, in fact,
958 needed and aren't also supplied in I3, they may be added by
959 recog_for_combine. Otherwise, it won't match.
961 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
964 Get the source and destination of INSN. If more than one, can't
967 if (GET_CODE (PATTERN (insn)) == SET)
968 set = PATTERN (insn);
969 else if (GET_CODE (PATTERN (insn)) == PARALLEL
970 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
972 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
974 rtx elt = XVECEXP (PATTERN (insn), 0, i);
976 switch (GET_CODE (elt))
978 /* This is important to combine floating point insns
981 /* Combining an isolated USE doesn't make sense.
982 We depend here on combinable_i3pat to reject them. */
983 /* The code below this loop only verifies that the inputs of
984 the SET in INSN do not change. We call reg_set_between_p
985 to verify that the REG in the USE does not change between
987 If the USE in INSN was for a pseudo register, the matching
988 insn pattern will likely match any register; combining this
989 with any other USE would only be safe if we knew that the
990 used registers have identical values, or if there was
991 something to tell them apart, e.g. different modes. For
992 now, we forgo such complicated tests and simply disallow
993 combining of USES of pseudo registers with any other USE. */
994 if (GET_CODE (XEXP (elt, 0)) == REG
995 && GET_CODE (PATTERN (i3)) == PARALLEL)
997 rtx i3pat = PATTERN (i3);
998 int i = XVECLEN (i3pat, 0) - 1;
999 unsigned int regno = REGNO (XEXP (elt, 0));
1003 rtx i3elt = XVECEXP (i3pat, 0, i);
1005 if (GET_CODE (i3elt) == USE
1006 && GET_CODE (XEXP (i3elt, 0)) == REG
1007 && (REGNO (XEXP (i3elt, 0)) == regno
1008 ? reg_set_between_p (XEXP (elt, 0),
1009 PREV_INSN (insn), i3)
1010 : regno >= FIRST_PSEUDO_REGISTER))
1017 /* We can ignore CLOBBERs. */
1022 /* Ignore SETs whose result isn't used but not those that
1023 have side-effects. */
1024 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1025 && ! side_effects_p (elt))
1028 /* If we have already found a SET, this is a second one and
1029 so we cannot combine with this insn. */
1037 /* Anything else means we can't combine. */
1043 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1044 so don't do anything with it. */
1045 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1054 set = expand_field_assignment (set);
1055 src = SET_SRC (set), dest = SET_DEST (set);
1057 /* Don't eliminate a store in the stack pointer. */
1058 if (dest == stack_pointer_rtx
1059 /* If we couldn't eliminate a field assignment, we can't combine. */
1060 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1061 /* Don't combine with an insn that sets a register to itself if it has
1062 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1063 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1064 /* Can't merge an ASM_OPERANDS. */
1065 || GET_CODE (src) == ASM_OPERANDS
1066 /* Can't merge a function call. */
1067 || GET_CODE (src) == CALL
1068 /* Don't eliminate a function call argument. */
1069 || (GET_CODE (i3) == CALL_INSN
1070 && (find_reg_fusage (i3, USE, dest)
1071 || (GET_CODE (dest) == REG
1072 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1073 && global_regs[REGNO (dest)])))
1074 /* Don't substitute into an incremented register. */
1075 || FIND_REG_INC_NOTE (i3, dest)
1076 || (succ && FIND_REG_INC_NOTE (succ, dest))
1078 /* Don't combine the end of a libcall into anything. */
1079 /* ??? This gives worse code, and appears to be unnecessary, since no
1080 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1081 use REG_RETVAL notes for noconflict blocks, but other code here
1082 makes sure that those insns don't disappear. */
1083 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1085 /* Make sure that DEST is not used after SUCC but before I3. */
1086 || (succ && ! all_adjacent
1087 && reg_used_between_p (dest, succ, i3))
1088 /* Make sure that the value that is to be substituted for the register
1089 does not use any registers whose values alter in between. However,
1090 If the insns are adjacent, a use can't cross a set even though we
1091 think it might (this can happen for a sequence of insns each setting
1092 the same destination; reg_last_set of that register might point to
1093 a NOTE). If INSN has a REG_EQUIV note, the register is always
1094 equivalent to the memory so the substitution is valid even if there
1095 are intervening stores. Also, don't move a volatile asm or
1096 UNSPEC_VOLATILE across any other insns. */
1098 && (((GET_CODE (src) != MEM
1099 || ! find_reg_note (insn, REG_EQUIV, src))
1100 && use_crosses_set_p (src, INSN_CUID (insn)))
1101 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1102 || GET_CODE (src) == UNSPEC_VOLATILE))
1103 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1104 better register allocation by not doing the combine. */
1105 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1106 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1107 /* Don't combine across a CALL_INSN, because that would possibly
1108 change whether the life span of some REGs crosses calls or not,
1109 and it is a pain to update that information.
1110 Exception: if source is a constant, moving it later can't hurt.
1111 Accept that special case, because it helps -fforce-addr a lot. */
1112 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1115 /* DEST must either be a REG or CC0. */
1116 if (GET_CODE (dest) == REG)
1118 /* If register alignment is being enforced for multi-word items in all
1119 cases except for parameters, it is possible to have a register copy
1120 insn referencing a hard register that is not allowed to contain the
1121 mode being copied and which would not be valid as an operand of most
1122 insns. Eliminate this problem by not combining with such an insn.
1124 Also, on some machines we don't want to extend the life of a hard
1127 if (GET_CODE (src) == REG
1128 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1138 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1141 else if (GET_CODE (dest) != CC0)
1144 /* Don't substitute for a register intended as a clobberable operand.
1145 Similarly, don't substitute an expression containing a register that
1146 will be clobbered in I3. */
1147 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1148 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1149 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1150 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1152 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1155 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1156 or not), reject, unless nothing volatile comes between it and I3 */
1158 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1160 /* Make sure succ doesn't contain a volatile reference. */
1161 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1164 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1165 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1169 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1170 to be an explicit register variable, and was chosen for a reason. */
1172 if (GET_CODE (src) == ASM_OPERANDS
1173 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1176 /* If there are any volatile insns between INSN and I3, reject, because
1177 they might affect machine state. */
1179 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1180 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1183 /* If INSN or I2 contains an autoincrement or autodecrement,
1184 make sure that register is not used between there and I3,
1185 and not already used in I3 either.
1186 Also insist that I3 not be a jump; if it were one
1187 and the incremented register were spilled, we would lose. */
1190 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1191 if (REG_NOTE_KIND (link) == REG_INC
1192 && (GET_CODE (i3) == JUMP_INSN
1193 || reg_used_between_p (XEXP (link, 0), insn, i3)
1194 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1199 /* Don't combine an insn that follows a CC0-setting insn.
1200 An insn that uses CC0 must not be separated from the one that sets it.
1201 We do, however, allow I2 to follow a CC0-setting insn if that insn
1202 is passed as I1; in that case it will be deleted also.
1203 We also allow combining in this case if all the insns are adjacent
1204 because that would leave the two CC0 insns adjacent as well.
1205 It would be more logical to test whether CC0 occurs inside I1 or I2,
1206 but that would be much slower, and this ought to be equivalent. */
1208 p = prev_nonnote_insn (insn);
1209 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1214 /* If we get here, we have passed all the tests and the combination is
1223 /* Check if PAT is an insn - or a part of it - used to set up an
1224 argument for a function in a hard register. */
1227 sets_function_arg_p (pat)
1233 switch (GET_CODE (pat))
1236 return sets_function_arg_p (PATTERN (pat));
1239 for (i = XVECLEN (pat, 0); --i >= 0;)
1240 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1246 inner_dest = SET_DEST (pat);
1247 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1248 || GET_CODE (inner_dest) == SUBREG
1249 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1250 inner_dest = XEXP (inner_dest, 0);
1252 return (GET_CODE (inner_dest) == REG
1253 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1254 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1263 /* LOC is the location within I3 that contains its pattern or the component
1264 of a PARALLEL of the pattern. We validate that it is valid for combining.
1266 One problem is if I3 modifies its output, as opposed to replacing it
1267 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1268 so would produce an insn that is not equivalent to the original insns.
1272 (set (reg:DI 101) (reg:DI 100))
1273 (set (subreg:SI (reg:DI 101) 0) <foo>)
1275 This is NOT equivalent to:
1277 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1278 (set (reg:DI 101) (reg:DI 100))])
1280 Not only does this modify 100 (in which case it might still be valid
1281 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1283 We can also run into a problem if I2 sets a register that I1
1284 uses and I1 gets directly substituted into I3 (not via I2). In that
1285 case, we would be getting the wrong value of I2DEST into I3, so we
1286 must reject the combination. This case occurs when I2 and I1 both
1287 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1288 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1289 of a SET must prevent combination from occurring.
1291 Before doing the above check, we first try to expand a field assignment
1292 into a set of logical operations.
1294 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1295 we place a register that is both set and used within I3. If more than one
1296 such register is detected, we fail.
1298 Return 1 if the combination is valid, zero otherwise. */
1301 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1307 rtx *pi3dest_killed;
1311 if (GET_CODE (x) == SET)
1313 rtx set = expand_field_assignment (x);
1314 rtx dest = SET_DEST (set);
1315 rtx src = SET_SRC (set);
1316 rtx inner_dest = dest;
1319 rtx inner_src = src;
1324 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1325 || GET_CODE (inner_dest) == SUBREG
1326 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1327 inner_dest = XEXP (inner_dest, 0);
1329 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1332 while (GET_CODE (inner_src) == STRICT_LOW_PART
1333 || GET_CODE (inner_src) == SUBREG
1334 || GET_CODE (inner_src) == ZERO_EXTRACT)
1335 inner_src = XEXP (inner_src, 0);
1337 /* If it is better that two different modes keep two different pseudos,
1338 avoid combining them. This avoids producing the following pattern
1340 (set (subreg:SI (reg/v:QI 21) 0)
1341 (lshiftrt:SI (reg/v:SI 20)
1343 If that were made, reload could not handle the pair of
1344 reg 20/21, since it would try to get any GENERAL_REGS
1345 but some of them don't handle QImode. */
1347 if (rtx_equal_p (inner_src, i2dest)
1348 && GET_CODE (inner_dest) == REG
1349 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1353 /* Check for the case where I3 modifies its output, as
1355 if ((inner_dest != dest
1356 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1357 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1359 /* This is the same test done in can_combine_p except we can't test
1360 all_adjacent; we don't have to, since this instruction will stay
1361 in place, thus we are not considering increasing the lifetime of
1364 Also, if this insn sets a function argument, combining it with
1365 something that might need a spill could clobber a previous
1366 function argument; the all_adjacent test in can_combine_p also
1367 checks this; here, we do a more specific test for this case. */
1369 || (GET_CODE (inner_dest) == REG
1370 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1371 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1372 GET_MODE (inner_dest))))
1373 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1376 /* If DEST is used in I3, it is being killed in this insn,
1377 so record that for later.
1378 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1379 STACK_POINTER_REGNUM, since these are always considered to be
1380 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1381 if (pi3dest_killed && GET_CODE (dest) == REG
1382 && reg_referenced_p (dest, PATTERN (i3))
1383 && REGNO (dest) != FRAME_POINTER_REGNUM
1384 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1385 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1387 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1388 && (REGNO (dest) != ARG_POINTER_REGNUM
1389 || ! fixed_regs [REGNO (dest)])
1391 && REGNO (dest) != STACK_POINTER_REGNUM)
1393 if (*pi3dest_killed)
1396 *pi3dest_killed = dest;
1400 else if (GET_CODE (x) == PARALLEL)
1404 for (i = 0; i < XVECLEN (x, 0); i++)
1405 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1406 i1_not_in_src, pi3dest_killed))
1413 /* Return 1 if X is an arithmetic expression that contains a multiplication
1414 and division. We don't count multiplications by powers of two here. */
1420 switch (GET_CODE (x))
1422 case MOD: case DIV: case UMOD: case UDIV:
1426 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1427 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1429 switch (GET_RTX_CLASS (GET_CODE (x)))
1431 case 'c': case '<': case '2':
1432 return contains_muldiv (XEXP (x, 0))
1433 || contains_muldiv (XEXP (x, 1));
1436 return contains_muldiv (XEXP (x, 0));
1444 /* Determine whether INSN can be used in a combination. Return nonzero if
1445 not. This is used in try_combine to detect early some cases where we
1446 can't perform combinations. */
1449 cant_combine_insn_p (insn)
1455 /* If this isn't really an insn, we can't do anything.
1456 This can occur when flow deletes an insn that it has merged into an
1457 auto-increment address. */
1458 if (! INSN_P (insn))
1461 /* Never combine loads and stores involving hard regs. The register
1462 allocator can usually handle such reg-reg moves by tying. If we allow
1463 the combiner to make substitutions of hard regs, we risk aborting in
1464 reload on machines that have SMALL_REGISTER_CLASSES.
1465 As an exception, we allow combinations involving fixed regs; these are
1466 not available to the register allocator so there's no risk involved. */
1468 set = single_set (insn);
1471 src = SET_SRC (set);
1472 dest = SET_DEST (set);
1473 if (GET_CODE (src) == SUBREG)
1474 src = SUBREG_REG (src);
1475 if (GET_CODE (dest) == SUBREG)
1476 dest = SUBREG_REG (dest);
1477 if (REG_P (src) && REG_P (dest)
1478 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1479 && ! fixed_regs[REGNO (src)])
1480 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs[REGNO (dest)])))
1487 /* Try to combine the insns I1 and I2 into I3.
1488 Here I1 and I2 appear earlier than I3.
1489 I1 can be zero; then we combine just I2 into I3.
1491 If we are combining three insns and the resulting insn is not recognized,
1492 try splitting it into two insns. If that happens, I2 and I3 are retained
1493 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1496 Return 0 if the combination does not work. Then nothing is changed.
1497 If we did the combination, return the insn at which combine should
1500 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1501 new direct jump instruction. */
1504 try_combine (i3, i2, i1, new_direct_jump_p)
1506 int *new_direct_jump_p;
1508 /* New patterns for I3 and I2, respectively. */
1509 rtx newpat, newi2pat = 0;
1510 int substed_i2 = 0, substed_i1 = 0;
1511 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1512 int added_sets_1, added_sets_2;
1513 /* Total number of SETs to put into I3. */
1515 /* Nonzero is I2's body now appears in I3. */
1517 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1518 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1519 /* Contains I3 if the destination of I3 is used in its source, which means
1520 that the old life of I3 is being killed. If that usage is placed into
1521 I2 and not in I3, a REG_DEAD note must be made. */
1522 rtx i3dest_killed = 0;
1523 /* SET_DEST and SET_SRC of I2 and I1. */
1524 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1525 /* PATTERN (I2), or a copy of it in certain cases. */
1527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1528 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1529 int i1_feeds_i3 = 0;
1530 /* Notes that must be added to REG_NOTES in I3 and I2. */
1531 rtx new_i3_notes, new_i2_notes;
1532 /* Notes that we substituted I3 into I2 instead of the normal case. */
1533 int i3_subst_into_i2 = 0;
1534 /* Notes that I1, I2 or I3 is a MULT operation. */
1542 /* Exit early if one of the insns involved can't be used for
1544 if (cant_combine_insn_p (i3)
1545 || cant_combine_insn_p (i2)
1546 || (i1 && cant_combine_insn_p (i1))
1547 /* We also can't do anything if I3 has a
1548 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1551 /* ??? This gives worse code, and appears to be unnecessary, since no
1552 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1553 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1559 undobuf.other_insn = 0;
1561 /* Reset the hard register usage information. */
1562 CLEAR_HARD_REG_SET (newpat_used_regs);
1564 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1565 code below, set I1 to be the earlier of the two insns. */
1566 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1567 temp = i1, i1 = i2, i2 = temp;
1569 added_links_insn = 0;
1571 /* First check for one important special-case that the code below will
1572 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1573 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1574 we may be able to replace that destination with the destination of I3.
1575 This occurs in the common code where we compute both a quotient and
1576 remainder into a structure, in which case we want to do the computation
1577 directly into the structure to avoid register-register copies.
1579 Note that this case handles both multiple sets in I2 and also
1580 cases where I2 has a number of CLOBBER or PARALLELs.
1582 We make very conservative checks below and only try to handle the
1583 most common cases of this. For example, we only handle the case
1584 where I2 and I3 are adjacent to avoid making difficult register
1587 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1588 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1589 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1590 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1591 && GET_CODE (PATTERN (i2)) == PARALLEL
1592 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1593 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1594 below would need to check what is inside (and reg_overlap_mentioned_p
1595 doesn't support those codes anyway). Don't allow those destinations;
1596 the resulting insn isn't likely to be recognized anyway. */
1597 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1598 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1599 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1600 SET_DEST (PATTERN (i3)))
1601 && next_real_insn (i2) == i3)
1603 rtx p2 = PATTERN (i2);
1605 /* Make sure that the destination of I3,
1606 which we are going to substitute into one output of I2,
1607 is not used within another output of I2. We must avoid making this:
1608 (parallel [(set (mem (reg 69)) ...)
1609 (set (reg 69) ...)])
1610 which is not well-defined as to order of actions.
1611 (Besides, reload can't handle output reloads for this.)
1613 The problem can also happen if the dest of I3 is a memory ref,
1614 if another dest in I2 is an indirect memory ref. */
1615 for (i = 0; i < XVECLEN (p2, 0); i++)
1616 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1617 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1618 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1619 SET_DEST (XVECEXP (p2, 0, i))))
1622 if (i == XVECLEN (p2, 0))
1623 for (i = 0; i < XVECLEN (p2, 0); i++)
1624 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1625 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1626 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1631 subst_low_cuid = INSN_CUID (i2);
1633 added_sets_2 = added_sets_1 = 0;
1634 i2dest = SET_SRC (PATTERN (i3));
1636 /* Replace the dest in I2 with our dest and make the resulting
1637 insn the new pattern for I3. Then skip to where we
1638 validate the pattern. Everything was set up above. */
1639 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1640 SET_DEST (PATTERN (i3)));
1643 i3_subst_into_i2 = 1;
1644 goto validate_replacement;
1648 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1649 one of those words to another constant, merge them by making a new
1652 && (temp = single_set (i2)) != 0
1653 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1654 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1655 && GET_CODE (SET_DEST (temp)) == REG
1656 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1657 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1658 && GET_CODE (PATTERN (i3)) == SET
1659 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1660 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1661 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1662 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1663 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1665 HOST_WIDE_INT lo, hi;
1667 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1668 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1671 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1672 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1675 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1677 /* We don't handle the case of the target word being wider
1678 than a host wide int. */
1679 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1682 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1683 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1684 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1686 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1687 hi = INTVAL (SET_SRC (PATTERN (i3)));
1688 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1690 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1691 >> (HOST_BITS_PER_WIDE_INT - 1));
1693 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1694 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1695 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (INTVAL (SET_SRC (PATTERN (i3)))));
1698 hi = lo < 0 ? -1 : 0;
1701 /* We don't handle the case of the higher word not fitting
1702 entirely in either hi or lo. */
1707 subst_low_cuid = INSN_CUID (i2);
1708 added_sets_2 = added_sets_1 = 0;
1709 i2dest = SET_DEST (temp);
1711 SUBST (SET_SRC (temp),
1712 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1714 newpat = PATTERN (i2);
1715 goto validate_replacement;
1719 /* If we have no I1 and I2 looks like:
1720 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1722 make up a dummy I1 that is
1725 (set (reg:CC X) (compare:CC Y (const_int 0)))
1727 (We can ignore any trailing CLOBBERs.)
1729 This undoes a previous combination and allows us to match a branch-and-
1732 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1733 && XVECLEN (PATTERN (i2), 0) >= 2
1734 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1735 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1737 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1738 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1739 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1740 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1741 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1742 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1744 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1745 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1750 /* We make I1 with the same INSN_UID as I2. This gives it
1751 the same INSN_CUID for value tracking. Our fake I1 will
1752 never appear in the insn stream so giving it the same INSN_UID
1753 as I2 will not cause a problem. */
1755 subst_prev_insn = i1
1756 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1757 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1760 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1761 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1762 SET_DEST (PATTERN (i1)));
1767 /* Verify that I2 and I1 are valid for combining. */
1768 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1769 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1775 /* Record whether I2DEST is used in I2SRC and similarly for the other
1776 cases. Knowing this will help in register status updating below. */
1777 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1778 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1779 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1781 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1783 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1785 /* Ensure that I3's pattern can be the destination of combines. */
1786 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1787 i1 && i2dest_in_i1src && i1_feeds_i3,
1794 /* See if any of the insns is a MULT operation. Unless one is, we will
1795 reject a combination that is, since it must be slower. Be conservative
1797 if (GET_CODE (i2src) == MULT
1798 || (i1 != 0 && GET_CODE (i1src) == MULT)
1799 || (GET_CODE (PATTERN (i3)) == SET
1800 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1803 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1804 We used to do this EXCEPT in one case: I3 has a post-inc in an
1805 output operand. However, that exception can give rise to insns like
1807 which is a famous insn on the PDP-11 where the value of r3 used as the
1808 source was model-dependent. Avoid this sort of thing. */
1811 if (!(GET_CODE (PATTERN (i3)) == SET
1812 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1813 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1814 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1815 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1816 /* It's not the exception. */
1819 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1820 if (REG_NOTE_KIND (link) == REG_INC
1821 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1823 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1830 /* See if the SETs in I1 or I2 need to be kept around in the merged
1831 instruction: whenever the value set there is still needed past I3.
1832 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1834 For the SET in I1, we have two cases: If I1 and I2 independently
1835 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1836 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1837 in I1 needs to be kept around unless I1DEST dies or is set in either
1838 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1839 I1DEST. If so, we know I1 feeds into I2. */
1841 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1844 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1845 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1847 /* If the set in I2 needs to be kept around, we must make a copy of
1848 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1849 PATTERN (I2), we are only substituting for the original I1DEST, not into
1850 an already-substituted copy. This also prevents making self-referential
1851 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1854 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1855 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1859 i2pat = copy_rtx (i2pat);
1863 /* Substitute in the latest insn for the regs set by the earlier ones. */
1865 maxreg = max_reg_num ();
1869 /* It is possible that the source of I2 or I1 may be performing an
1870 unneeded operation, such as a ZERO_EXTEND of something that is known
1871 to have the high part zero. Handle that case by letting subst look at
1872 the innermost one of them.
1874 Another way to do this would be to have a function that tries to
1875 simplify a single insn instead of merging two or more insns. We don't
1876 do this because of the potential of infinite loops and because
1877 of the potential extra memory required. However, doing it the way
1878 we are is a bit of a kludge and doesn't catch all cases.
1880 But only do this if -fexpensive-optimizations since it slows things down
1881 and doesn't usually win. */
1883 if (flag_expensive_optimizations)
1885 /* Pass pc_rtx so no substitutions are done, just simplifications.
1886 The cases that we are interested in here do not involve the few
1887 cases were is_replaced is checked. */
1890 subst_low_cuid = INSN_CUID (i1);
1891 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1895 subst_low_cuid = INSN_CUID (i2);
1896 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1901 /* Many machines that don't use CC0 have insns that can both perform an
1902 arithmetic operation and set the condition code. These operations will
1903 be represented as a PARALLEL with the first element of the vector
1904 being a COMPARE of an arithmetic operation with the constant zero.
1905 The second element of the vector will set some pseudo to the result
1906 of the same arithmetic operation. If we simplify the COMPARE, we won't
1907 match such a pattern and so will generate an extra insn. Here we test
1908 for this case, where both the comparison and the operation result are
1909 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1910 I2SRC. Later we will make the PARALLEL that contains I2. */
1912 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1913 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1914 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1915 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1917 #ifdef EXTRA_CC_MODES
1919 enum machine_mode compare_mode;
1922 newpat = PATTERN (i3);
1923 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1927 #ifdef EXTRA_CC_MODES
1928 /* See if a COMPARE with the operand we substituted in should be done
1929 with the mode that is currently being used. If not, do the same
1930 processing we do in `subst' for a SET; namely, if the destination
1931 is used only once, try to replace it with a register of the proper
1932 mode and also replace the COMPARE. */
1933 if (undobuf.other_insn == 0
1934 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1935 &undobuf.other_insn))
1936 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1938 != GET_MODE (SET_DEST (newpat))))
1940 unsigned int regno = REGNO (SET_DEST (newpat));
1941 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1943 if (regno < FIRST_PSEUDO_REGISTER
1944 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1945 && ! REG_USERVAR_P (SET_DEST (newpat))))
1947 if (regno >= FIRST_PSEUDO_REGISTER)
1948 SUBST (regno_reg_rtx[regno], new_dest);
1950 SUBST (SET_DEST (newpat), new_dest);
1951 SUBST (XEXP (*cc_use, 0), new_dest);
1952 SUBST (SET_SRC (newpat),
1953 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1956 undobuf.other_insn = 0;
1963 n_occurrences = 0; /* `subst' counts here */
1965 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1966 need to make a unique copy of I2SRC each time we substitute it
1967 to avoid self-referential rtl. */
1969 subst_low_cuid = INSN_CUID (i2);
1970 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1971 ! i1_feeds_i3 && i1dest_in_i1src);
1974 /* Record whether i2's body now appears within i3's body. */
1975 i2_is_used = n_occurrences;
1978 /* If we already got a failure, don't try to do more. Otherwise,
1979 try to substitute in I1 if we have it. */
1981 if (i1 && GET_CODE (newpat) != CLOBBER)
1983 /* Before we can do this substitution, we must redo the test done
1984 above (see detailed comments there) that ensures that I1DEST
1985 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1987 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1995 subst_low_cuid = INSN_CUID (i1);
1996 newpat = subst (newpat, i1dest, i1src, 0, 0);
2000 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2001 to count all the ways that I2SRC and I1SRC can be used. */
2002 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2003 && i2_is_used + added_sets_2 > 1)
2004 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2005 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2007 /* Fail if we tried to make a new register (we used to abort, but there's
2008 really no reason to). */
2009 || max_reg_num () != maxreg
2010 /* Fail if we couldn't do something and have a CLOBBER. */
2011 || GET_CODE (newpat) == CLOBBER
2012 /* Fail if this new pattern is a MULT and we didn't have one before
2013 at the outer level. */
2014 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2021 /* If the actions of the earlier insns must be kept
2022 in addition to substituting them into the latest one,
2023 we must make a new PARALLEL for the latest insn
2024 to hold additional the SETs. */
2026 if (added_sets_1 || added_sets_2)
2030 if (GET_CODE (newpat) == PARALLEL)
2032 rtvec old = XVEC (newpat, 0);
2033 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2034 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2035 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2036 sizeof (old->elem[0]) * old->num_elem);
2041 total_sets = 1 + added_sets_1 + added_sets_2;
2042 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2043 XVECEXP (newpat, 0, 0) = old;
2047 XVECEXP (newpat, 0, --total_sets)
2048 = (GET_CODE (PATTERN (i1)) == PARALLEL
2049 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2053 /* If there is no I1, use I2's body as is. We used to also not do
2054 the subst call below if I2 was substituted into I3,
2055 but that could lose a simplification. */
2057 XVECEXP (newpat, 0, --total_sets) = i2pat;
2059 /* See comment where i2pat is assigned. */
2060 XVECEXP (newpat, 0, --total_sets)
2061 = subst (i2pat, i1dest, i1src, 0, 0);
2065 /* We come here when we are replacing a destination in I2 with the
2066 destination of I3. */
2067 validate_replacement:
2069 /* Note which hard regs this insn has as inputs. */
2070 mark_used_regs_combine (newpat);
2072 /* Is the result of combination a valid instruction? */
2073 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2075 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2076 the second SET's destination is a register that is unused. In that case,
2077 we just need the first SET. This can occur when simplifying a divmod
2078 insn. We *must* test for this case here because the code below that
2079 splits two independent SETs doesn't handle this case correctly when it
2080 updates the register status. Also check the case where the first
2081 SET's destination is unused. That would not cause incorrect code, but
2082 does cause an unneeded insn to remain. */
2084 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2085 && XVECLEN (newpat, 0) == 2
2086 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2087 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2088 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2089 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2090 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2091 && asm_noperands (newpat) < 0)
2093 newpat = XVECEXP (newpat, 0, 0);
2094 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2097 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2098 && XVECLEN (newpat, 0) == 2
2099 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2100 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2101 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2102 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2103 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2104 && asm_noperands (newpat) < 0)
2106 newpat = XVECEXP (newpat, 0, 1);
2107 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2110 /* If we were combining three insns and the result is a simple SET
2111 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2112 insns. There are two ways to do this. It can be split using a
2113 machine-specific method (like when you have an addition of a large
2114 constant) or by combine in the function find_split_point. */
2116 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2117 && asm_noperands (newpat) < 0)
2119 rtx m_split, *split;
2120 rtx ni2dest = i2dest;
2122 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2123 use I2DEST as a scratch register will help. In the latter case,
2124 convert I2DEST to the mode of the source of NEWPAT if we can. */
2126 m_split = split_insns (newpat, i3);
2128 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2129 inputs of NEWPAT. */
2131 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2132 possible to try that as a scratch reg. This would require adding
2133 more code to make it work though. */
2135 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2137 /* If I2DEST is a hard register or the only use of a pseudo,
2138 we can change its mode. */
2139 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2140 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2141 && GET_CODE (i2dest) == REG
2142 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2143 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2144 && ! REG_USERVAR_P (i2dest))))
2145 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2148 m_split = split_insns (gen_rtx_PARALLEL
2150 gen_rtvec (2, newpat,
2151 gen_rtx_CLOBBER (VOIDmode,
2154 /* If the split with the mode-changed register didn't work, try
2155 the original register. */
2156 if (! m_split && ni2dest != i2dest)
2159 m_split = split_insns (gen_rtx_PARALLEL
2161 gen_rtvec (2, newpat,
2162 gen_rtx_CLOBBER (VOIDmode,
2168 /* If we've split a jump pattern, we'll wind up with a sequence even
2169 with one instruction. We can handle that below, so extract it. */
2170 if (m_split && GET_CODE (m_split) == SEQUENCE
2171 && XVECLEN (m_split, 0) == 1)
2172 m_split = PATTERN (XVECEXP (m_split, 0, 0));
2174 if (m_split && GET_CODE (m_split) != SEQUENCE)
2176 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2177 if (insn_code_number >= 0)
2180 else if (m_split && GET_CODE (m_split) == SEQUENCE
2181 && XVECLEN (m_split, 0) == 2
2182 && (next_real_insn (i2) == i3
2183 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2187 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2188 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2190 i3set = single_set (XVECEXP (m_split, 0, 1));
2191 i2set = single_set (XVECEXP (m_split, 0, 0));
2193 /* In case we changed the mode of I2DEST, replace it in the
2194 pseudo-register table here. We can't do it above in case this
2195 code doesn't get executed and we do a split the other way. */
2197 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2198 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2200 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2202 /* If I2 or I3 has multiple SETs, we won't know how to track
2203 register status, so don't use these insns. If I2's destination
2204 is used between I2 and I3, we also can't use these insns. */
2206 if (i2_code_number >= 0 && i2set && i3set
2207 && (next_real_insn (i2) == i3
2208 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2209 insn_code_number = recog_for_combine (&newi3pat, i3,
2211 if (insn_code_number >= 0)
2214 /* It is possible that both insns now set the destination of I3.
2215 If so, we must show an extra use of it. */
2217 if (insn_code_number >= 0)
2219 rtx new_i3_dest = SET_DEST (i3set);
2220 rtx new_i2_dest = SET_DEST (i2set);
2222 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2223 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2224 || GET_CODE (new_i3_dest) == SUBREG)
2225 new_i3_dest = XEXP (new_i3_dest, 0);
2227 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2228 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2229 || GET_CODE (new_i2_dest) == SUBREG)
2230 new_i2_dest = XEXP (new_i2_dest, 0);
2232 if (GET_CODE (new_i3_dest) == REG
2233 && GET_CODE (new_i2_dest) == REG
2234 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2235 REG_N_SETS (REGNO (new_i2_dest))++;
2239 /* If we can split it and use I2DEST, go ahead and see if that
2240 helps things be recognized. Verify that none of the registers
2241 are set between I2 and I3. */
2242 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2244 && GET_CODE (i2dest) == REG
2246 /* We need I2DEST in the proper mode. If it is a hard register
2247 or the only use of a pseudo, we can change its mode. */
2248 && (GET_MODE (*split) == GET_MODE (i2dest)
2249 || GET_MODE (*split) == VOIDmode
2250 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2251 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2252 && ! REG_USERVAR_P (i2dest)))
2253 && (next_real_insn (i2) == i3
2254 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2255 /* We can't overwrite I2DEST if its value is still used by
2257 && ! reg_referenced_p (i2dest, newpat))
2259 rtx newdest = i2dest;
2260 enum rtx_code split_code = GET_CODE (*split);
2261 enum machine_mode split_mode = GET_MODE (*split);
2263 /* Get NEWDEST as a register in the proper mode. We have already
2264 validated that we can do this. */
2265 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2267 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2269 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2270 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2273 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2274 an ASHIFT. This can occur if it was inside a PLUS and hence
2275 appeared to be a memory address. This is a kludge. */
2276 if (split_code == MULT
2277 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2278 && INTVAL (XEXP (*split, 1)) > 0
2279 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2281 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2282 XEXP (*split, 0), GEN_INT (i)));
2283 /* Update split_code because we may not have a multiply
2285 split_code = GET_CODE (*split);
2288 #ifdef INSN_SCHEDULING
2289 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2290 be written as a ZERO_EXTEND. */
2291 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2292 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2293 SUBREG_REG (*split)));
2296 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2297 SUBST (*split, newdest);
2298 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2300 /* If the split point was a MULT and we didn't have one before,
2301 don't use one now. */
2302 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2303 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2307 /* Check for a case where we loaded from memory in a narrow mode and
2308 then sign extended it, but we need both registers. In that case,
2309 we have a PARALLEL with both loads from the same memory location.
2310 We can split this into a load from memory followed by a register-register
2311 copy. This saves at least one insn, more if register allocation can
2314 We cannot do this if the destination of the second assignment is
2315 a register that we have already assumed is zero-extended. Similarly
2316 for a SUBREG of such a register. */
2318 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2319 && GET_CODE (newpat) == PARALLEL
2320 && XVECLEN (newpat, 0) == 2
2321 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2322 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2323 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2324 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2325 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2326 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2328 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2329 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2330 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2331 (GET_CODE (temp) == REG
2332 && reg_nonzero_bits[REGNO (temp)] != 0
2333 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2334 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2335 && (reg_nonzero_bits[REGNO (temp)]
2336 != GET_MODE_MASK (word_mode))))
2337 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2338 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2339 (GET_CODE (temp) == REG
2340 && reg_nonzero_bits[REGNO (temp)] != 0
2341 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2342 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2343 && (reg_nonzero_bits[REGNO (temp)]
2344 != GET_MODE_MASK (word_mode)))))
2345 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2346 SET_SRC (XVECEXP (newpat, 0, 1)))
2347 && ! find_reg_note (i3, REG_UNUSED,
2348 SET_DEST (XVECEXP (newpat, 0, 0))))
2352 newi2pat = XVECEXP (newpat, 0, 0);
2353 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2354 newpat = XVECEXP (newpat, 0, 1);
2355 SUBST (SET_SRC (newpat),
2356 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2357 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2359 if (i2_code_number >= 0)
2360 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2362 if (insn_code_number >= 0)
2367 /* If we will be able to accept this, we have made a change to the
2368 destination of I3. This can invalidate a LOG_LINKS pointing
2369 to I3. No other part of combine.c makes such a transformation.
2371 The new I3 will have a destination that was previously the
2372 destination of I1 or I2 and which was used in i2 or I3. Call
2373 distribute_links to make a LOG_LINK from the next use of
2374 that destination. */
2376 PATTERN (i3) = newpat;
2377 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2379 /* I3 now uses what used to be its destination and which is
2380 now I2's destination. That means we need a LOG_LINK from
2381 I3 to I2. But we used to have one, so we still will.
2383 However, some later insn might be using I2's dest and have
2384 a LOG_LINK pointing at I3. We must remove this link.
2385 The simplest way to remove the link is to point it at I1,
2386 which we know will be a NOTE. */
2388 for (insn = NEXT_INSN (i3);
2389 insn && (this_basic_block == n_basic_blocks - 1
2390 || insn != BLOCK_HEAD (this_basic_block + 1));
2391 insn = NEXT_INSN (insn))
2393 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2395 for (link = LOG_LINKS (insn); link;
2396 link = XEXP (link, 1))
2397 if (XEXP (link, 0) == i3)
2398 XEXP (link, 0) = i1;
2406 /* Similarly, check for a case where we have a PARALLEL of two independent
2407 SETs but we started with three insns. In this case, we can do the sets
2408 as two separate insns. This case occurs when some SET allows two
2409 other insns to combine, but the destination of that SET is still live. */
2411 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2412 && GET_CODE (newpat) == PARALLEL
2413 && XVECLEN (newpat, 0) == 2
2414 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2415 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2416 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2417 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2418 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2419 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2420 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2422 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2423 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2424 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2425 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2426 XVECEXP (newpat, 0, 0))
2427 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2428 XVECEXP (newpat, 0, 1))
2429 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2430 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2432 /* Normally, it doesn't matter which of the two is done first,
2433 but it does if one references cc0. In that case, it has to
2436 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2438 newi2pat = XVECEXP (newpat, 0, 0);
2439 newpat = XVECEXP (newpat, 0, 1);
2444 newi2pat = XVECEXP (newpat, 0, 1);
2445 newpat = XVECEXP (newpat, 0, 0);
2448 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2450 if (i2_code_number >= 0)
2451 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2454 /* If it still isn't recognized, fail and change things back the way they
2456 if ((insn_code_number < 0
2457 /* Is the result a reasonable ASM_OPERANDS? */
2458 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2464 /* If we had to change another insn, make sure it is valid also. */
2465 if (undobuf.other_insn)
2467 rtx other_pat = PATTERN (undobuf.other_insn);
2468 rtx new_other_notes;
2471 CLEAR_HARD_REG_SET (newpat_used_regs);
2473 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2476 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2482 PATTERN (undobuf.other_insn) = other_pat;
2484 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2485 are still valid. Then add any non-duplicate notes added by
2486 recog_for_combine. */
2487 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2489 next = XEXP (note, 1);
2491 if (REG_NOTE_KIND (note) == REG_UNUSED
2492 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2494 if (GET_CODE (XEXP (note, 0)) == REG)
2495 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2497 remove_note (undobuf.other_insn, note);
2501 for (note = new_other_notes; note; note = XEXP (note, 1))
2502 if (GET_CODE (XEXP (note, 0)) == REG)
2503 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2505 distribute_notes (new_other_notes, undobuf.other_insn,
2506 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2509 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2510 they are adjacent to each other or not. */
2512 rtx p = prev_nonnote_insn (i3);
2513 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2514 && sets_cc0_p (newi2pat))
2522 /* We now know that we can do this combination. Merge the insns and
2523 update the status of registers and LOG_LINKS. */
2526 rtx i3notes, i2notes, i1notes = 0;
2527 rtx i3links, i2links, i1links = 0;
2530 /* Compute which registers we expect to eliminate. newi2pat may be setting
2531 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2532 same as i3dest, in which case newi2pat may be setting i1dest. */
2533 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2534 || i2dest_in_i2src || i2dest_in_i1src
2536 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2537 || (newi2pat && reg_set_p (i1dest, newi2pat))
2540 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2542 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2543 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2545 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2547 /* Ensure that we do not have something that should not be shared but
2548 occurs multiple times in the new insns. Check this by first
2549 resetting all the `used' flags and then copying anything is shared. */
2551 reset_used_flags (i3notes);
2552 reset_used_flags (i2notes);
2553 reset_used_flags (i1notes);
2554 reset_used_flags (newpat);
2555 reset_used_flags (newi2pat);
2556 if (undobuf.other_insn)
2557 reset_used_flags (PATTERN (undobuf.other_insn));
2559 i3notes = copy_rtx_if_shared (i3notes);
2560 i2notes = copy_rtx_if_shared (i2notes);
2561 i1notes = copy_rtx_if_shared (i1notes);
2562 newpat = copy_rtx_if_shared (newpat);
2563 newi2pat = copy_rtx_if_shared (newi2pat);
2564 if (undobuf.other_insn)
2565 reset_used_flags (PATTERN (undobuf.other_insn));
2567 INSN_CODE (i3) = insn_code_number;
2568 PATTERN (i3) = newpat;
2570 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2572 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2574 reset_used_flags (call_usage);
2575 call_usage = copy_rtx (call_usage);
2578 replace_rtx (call_usage, i2dest, i2src);
2581 replace_rtx (call_usage, i1dest, i1src);
2583 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2586 if (undobuf.other_insn)
2587 INSN_CODE (undobuf.other_insn) = other_code_number;
2589 /* We had one special case above where I2 had more than one set and
2590 we replaced a destination of one of those sets with the destination
2591 of I3. In that case, we have to update LOG_LINKS of insns later
2592 in this basic block. Note that this (expensive) case is rare.
2594 Also, in this case, we must pretend that all REG_NOTEs for I2
2595 actually came from I3, so that REG_UNUSED notes from I2 will be
2596 properly handled. */
2598 if (i3_subst_into_i2)
2600 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2601 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2602 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2603 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2604 && ! find_reg_note (i2, REG_UNUSED,
2605 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2606 for (temp = NEXT_INSN (i2);
2607 temp && (this_basic_block == n_basic_blocks - 1
2608 || BLOCK_HEAD (this_basic_block) != temp);
2609 temp = NEXT_INSN (temp))
2610 if (temp != i3 && INSN_P (temp))
2611 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2612 if (XEXP (link, 0) == i2)
2613 XEXP (link, 0) = i3;
2618 while (XEXP (link, 1))
2619 link = XEXP (link, 1);
2620 XEXP (link, 1) = i2notes;
2634 INSN_CODE (i2) = i2_code_number;
2635 PATTERN (i2) = newi2pat;
2639 PUT_CODE (i2, NOTE);
2640 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2641 NOTE_SOURCE_FILE (i2) = 0;
2648 PUT_CODE (i1, NOTE);
2649 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2650 NOTE_SOURCE_FILE (i1) = 0;
2653 /* Get death notes for everything that is now used in either I3 or
2654 I2 and used to die in a previous insn. If we built two new
2655 patterns, move from I1 to I2 then I2 to I3 so that we get the
2656 proper movement on registers that I2 modifies. */
2660 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2661 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2664 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2667 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2669 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2672 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2675 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2678 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2681 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2682 know these are REG_UNUSED and want them to go to the desired insn,
2683 so we always pass it as i3. We have not counted the notes in
2684 reg_n_deaths yet, so we need to do so now. */
2686 if (newi2pat && new_i2_notes)
2688 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2689 if (GET_CODE (XEXP (temp, 0)) == REG)
2690 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2692 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2697 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2698 if (GET_CODE (XEXP (temp, 0)) == REG)
2699 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2701 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2704 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2705 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2706 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2707 in that case, it might delete I2. Similarly for I2 and I1.
2708 Show an additional death due to the REG_DEAD note we make here. If
2709 we discard it in distribute_notes, we will decrement it again. */
2713 if (GET_CODE (i3dest_killed) == REG)
2714 REG_N_DEATHS (REGNO (i3dest_killed))++;
2716 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2717 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2719 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2721 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2723 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2727 if (i2dest_in_i2src)
2729 if (GET_CODE (i2dest) == REG)
2730 REG_N_DEATHS (REGNO (i2dest))++;
2732 if (newi2pat && reg_set_p (i2dest, newi2pat))
2733 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2734 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2736 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2737 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2738 NULL_RTX, NULL_RTX);
2741 if (i1dest_in_i1src)
2743 if (GET_CODE (i1dest) == REG)
2744 REG_N_DEATHS (REGNO (i1dest))++;
2746 if (newi2pat && reg_set_p (i1dest, newi2pat))
2747 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2748 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2750 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2751 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2752 NULL_RTX, NULL_RTX);
2755 distribute_links (i3links);
2756 distribute_links (i2links);
2757 distribute_links (i1links);
2759 if (GET_CODE (i2dest) == REG)
2762 rtx i2_insn = 0, i2_val = 0, set;
2764 /* The insn that used to set this register doesn't exist, and
2765 this life of the register may not exist either. See if one of
2766 I3's links points to an insn that sets I2DEST. If it does,
2767 that is now the last known value for I2DEST. If we don't update
2768 this and I2 set the register to a value that depended on its old
2769 contents, we will get confused. If this insn is used, thing
2770 will be set correctly in combine_instructions. */
2772 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2773 if ((set = single_set (XEXP (link, 0))) != 0
2774 && rtx_equal_p (i2dest, SET_DEST (set)))
2775 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2777 record_value_for_reg (i2dest, i2_insn, i2_val);
2779 /* If the reg formerly set in I2 died only once and that was in I3,
2780 zero its use count so it won't make `reload' do any work. */
2782 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2783 && ! i2dest_in_i2src)
2785 regno = REGNO (i2dest);
2786 REG_N_SETS (regno)--;
2790 if (i1 && GET_CODE (i1dest) == REG)
2793 rtx i1_insn = 0, i1_val = 0, set;
2795 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2796 if ((set = single_set (XEXP (link, 0))) != 0
2797 && rtx_equal_p (i1dest, SET_DEST (set)))
2798 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2800 record_value_for_reg (i1dest, i1_insn, i1_val);
2802 regno = REGNO (i1dest);
2803 if (! added_sets_1 && ! i1dest_in_i1src)
2804 REG_N_SETS (regno)--;
2807 /* Update reg_nonzero_bits et al for any changes that may have been made
2808 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2809 important. Because newi2pat can affect nonzero_bits of newpat */
2811 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2812 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2814 /* Set new_direct_jump_p if a new return or simple jump instruction
2817 If I3 is now an unconditional jump, ensure that it has a
2818 BARRIER following it since it may have initially been a
2819 conditional jump. It may also be the last nonnote insn. */
2821 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2823 *new_direct_jump_p = 1;
2825 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2826 || GET_CODE (temp) != BARRIER)
2827 emit_barrier_after (i3);
2829 /* An NOOP jump does not need barrier, but it does need cleaning up
2831 if (GET_CODE (newpat) == SET
2832 && SET_SRC (newpat) == pc_rtx
2833 && SET_DEST (newpat) == pc_rtx)
2834 *new_direct_jump_p = 1;
2837 combine_successes++;
2840 /* Clear this here, so that subsequent get_last_value calls are not
2842 subst_prev_insn = NULL_RTX;
2844 if (added_links_insn
2845 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2846 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2847 return added_links_insn;
2849 return newi2pat ? i2 : i3;
2852 /* Undo all the modifications recorded in undobuf. */
2857 struct undo *undo, *next;
2859 for (undo = undobuf.undos; undo; undo = next)
2863 *undo->where.i = undo->old_contents.i;
2865 *undo->where.r = undo->old_contents.r;
2867 undo->next = undobuf.frees;
2868 undobuf.frees = undo;
2873 /* Clear this here, so that subsequent get_last_value calls are not
2875 subst_prev_insn = NULL_RTX;
2878 /* We've committed to accepting the changes we made. Move all
2879 of the undos to the free list. */
2884 struct undo *undo, *next;
2886 for (undo = undobuf.undos; undo; undo = next)
2889 undo->next = undobuf.frees;
2890 undobuf.frees = undo;
2896 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2897 where we have an arithmetic expression and return that point. LOC will
2900 try_combine will call this function to see if an insn can be split into
2904 find_split_point (loc, insn)
2909 enum rtx_code code = GET_CODE (x);
2911 unsigned HOST_WIDE_INT len = 0;
2912 HOST_WIDE_INT pos = 0;
2914 rtx inner = NULL_RTX;
2916 /* First special-case some codes. */
2920 #ifdef INSN_SCHEDULING
2921 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2923 if (GET_CODE (SUBREG_REG (x)) == MEM)
2926 return find_split_point (&SUBREG_REG (x), insn);
2930 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2931 using LO_SUM and HIGH. */
2932 if (GET_CODE (XEXP (x, 0)) == CONST
2933 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2936 gen_rtx_LO_SUM (Pmode,
2937 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2939 return &XEXP (XEXP (x, 0), 0);
2943 /* If we have a PLUS whose second operand is a constant and the
2944 address is not valid, perhaps will can split it up using
2945 the machine-specific way to split large constants. We use
2946 the first pseudo-reg (one of the virtual regs) as a placeholder;
2947 it will not remain in the result. */
2948 if (GET_CODE (XEXP (x, 0)) == PLUS
2949 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2950 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2952 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2953 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2956 /* This should have produced two insns, each of which sets our
2957 placeholder. If the source of the second is a valid address,
2958 we can make put both sources together and make a split point
2961 if (seq && XVECLEN (seq, 0) == 2
2962 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2963 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2964 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2965 && ! reg_mentioned_p (reg,
2966 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2967 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2968 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2969 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2970 && memory_address_p (GET_MODE (x),
2971 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2973 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2974 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2976 /* Replace the placeholder in SRC2 with SRC1. If we can
2977 find where in SRC2 it was placed, that can become our
2978 split point and we can replace this address with SRC2.
2979 Just try two obvious places. */
2981 src2 = replace_rtx (src2, reg, src1);
2983 if (XEXP (src2, 0) == src1)
2984 split = &XEXP (src2, 0);
2985 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2986 && XEXP (XEXP (src2, 0), 0) == src1)
2987 split = &XEXP (XEXP (src2, 0), 0);
2991 SUBST (XEXP (x, 0), src2);
2996 /* If that didn't work, perhaps the first operand is complex and
2997 needs to be computed separately, so make a split point there.
2998 This will occur on machines that just support REG + CONST
2999 and have a constant moved through some previous computation. */
3001 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3002 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3003 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3005 return &XEXP (XEXP (x, 0), 0);
3011 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3012 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3013 we need to put the operand into a register. So split at that
3016 if (SET_DEST (x) == cc0_rtx
3017 && GET_CODE (SET_SRC (x)) != COMPARE
3018 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3019 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3020 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3021 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3022 return &SET_SRC (x);
3025 /* See if we can split SET_SRC as it stands. */
3026 split = find_split_point (&SET_SRC (x), insn);
3027 if (split && split != &SET_SRC (x))
3030 /* See if we can split SET_DEST as it stands. */
3031 split = find_split_point (&SET_DEST (x), insn);
3032 if (split && split != &SET_DEST (x))
3035 /* See if this is a bitfield assignment with everything constant. If
3036 so, this is an IOR of an AND, so split it into that. */
3037 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3038 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3039 <= HOST_BITS_PER_WIDE_INT)
3040 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3041 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3042 && GET_CODE (SET_SRC (x)) == CONST_INT
3043 && ((INTVAL (XEXP (SET_DEST (x), 1))
3044 + INTVAL (XEXP (SET_DEST (x), 2)))
3045 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3046 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3048 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3049 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3050 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3051 rtx dest = XEXP (SET_DEST (x), 0);
3052 enum machine_mode mode = GET_MODE (dest);
3053 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3055 if (BITS_BIG_ENDIAN)
3056 pos = GET_MODE_BITSIZE (mode) - len - pos;
3060 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3063 gen_binary (IOR, mode,
3064 gen_binary (AND, mode, dest,
3069 & GET_MODE_MASK (mode), mode))),
3070 GEN_INT (src << pos)));
3072 SUBST (SET_DEST (x), dest);
3074 split = find_split_point (&SET_SRC (x), insn);
3075 if (split && split != &SET_SRC (x))
3079 /* Otherwise, see if this is an operation that we can split into two.
3080 If so, try to split that. */
3081 code = GET_CODE (SET_SRC (x));
3086 /* If we are AND'ing with a large constant that is only a single
3087 bit and the result is only being used in a context where we
3088 need to know if it is zero or non-zero, replace it with a bit
3089 extraction. This will avoid the large constant, which might
3090 have taken more than one insn to make. If the constant were
3091 not a valid argument to the AND but took only one insn to make,
3092 this is no worse, but if it took more than one insn, it will
3095 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3096 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3097 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3098 && GET_CODE (SET_DEST (x)) == REG
3099 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3100 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3101 && XEXP (*split, 0) == SET_DEST (x)
3102 && XEXP (*split, 1) == const0_rtx)
3104 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3105 XEXP (SET_SRC (x), 0),
3106 pos, NULL_RTX, 1, 1, 0, 0);
3107 if (extraction != 0)
3109 SUBST (SET_SRC (x), extraction);
3110 return find_split_point (loc, insn);
3116 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3117 is known to be on, this can be converted into a NEG of a shift. */
3118 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3119 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3120 && 1 <= (pos = exact_log2
3121 (nonzero_bits (XEXP (SET_SRC (x), 0),
3122 GET_MODE (XEXP (SET_SRC (x), 0))))))
3124 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3128 gen_rtx_LSHIFTRT (mode,
3129 XEXP (SET_SRC (x), 0),
3132 split = find_split_point (&SET_SRC (x), insn);
3133 if (split && split != &SET_SRC (x))
3139 inner = XEXP (SET_SRC (x), 0);
3141 /* We can't optimize if either mode is a partial integer
3142 mode as we don't know how many bits are significant
3144 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3145 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3149 len = GET_MODE_BITSIZE (GET_MODE (inner));
3155 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3156 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3158 inner = XEXP (SET_SRC (x), 0);
3159 len = INTVAL (XEXP (SET_SRC (x), 1));
3160 pos = INTVAL (XEXP (SET_SRC (x), 2));
3162 if (BITS_BIG_ENDIAN)
3163 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3164 unsignedp = (code == ZERO_EXTRACT);
3172 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3174 enum machine_mode mode = GET_MODE (SET_SRC (x));
3176 /* For unsigned, we have a choice of a shift followed by an
3177 AND or two shifts. Use two shifts for field sizes where the
3178 constant might be too large. We assume here that we can
3179 always at least get 8-bit constants in an AND insn, which is
3180 true for every current RISC. */
3182 if (unsignedp && len <= 8)
3187 (mode, gen_lowpart_for_combine (mode, inner),
3189 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3191 split = find_split_point (&SET_SRC (x), insn);
3192 if (split && split != &SET_SRC (x))
3199 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3200 gen_rtx_ASHIFT (mode,
3201 gen_lowpart_for_combine (mode, inner),
3202 GEN_INT (GET_MODE_BITSIZE (mode)
3204 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3206 split = find_split_point (&SET_SRC (x), insn);
3207 if (split && split != &SET_SRC (x))
3212 /* See if this is a simple operation with a constant as the second
3213 operand. It might be that this constant is out of range and hence
3214 could be used as a split point. */
3215 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3216 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3217 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3218 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3219 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3220 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3221 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3223 return &XEXP (SET_SRC (x), 1);
3225 /* Finally, see if this is a simple operation with its first operand
3226 not in a register. The operation might require this operand in a
3227 register, so return it as a split point. We can always do this
3228 because if the first operand were another operation, we would have
3229 already found it as a split point. */
3230 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3231 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3232 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3233 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3234 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3235 return &XEXP (SET_SRC (x), 0);
3241 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3242 it is better to write this as (not (ior A B)) so we can split it.
3243 Similarly for IOR. */
3244 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3247 gen_rtx_NOT (GET_MODE (x),
3248 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3250 XEXP (XEXP (x, 0), 0),
3251 XEXP (XEXP (x, 1), 0))));
3252 return find_split_point (loc, insn);
3255 /* Many RISC machines have a large set of logical insns. If the
3256 second operand is a NOT, put it first so we will try to split the
3257 other operand first. */
3258 if (GET_CODE (XEXP (x, 1)) == NOT)
3260 rtx tem = XEXP (x, 0);
3261 SUBST (XEXP (x, 0), XEXP (x, 1));
3262 SUBST (XEXP (x, 1), tem);
3270 /* Otherwise, select our actions depending on our rtx class. */
3271 switch (GET_RTX_CLASS (code))
3273 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3275 split = find_split_point (&XEXP (x, 2), insn);
3278 /* ... fall through ... */
3282 split = find_split_point (&XEXP (x, 1), insn);
3285 /* ... fall through ... */
3287 /* Some machines have (and (shift ...) ...) insns. If X is not
3288 an AND, but XEXP (X, 0) is, use it as our split point. */
3289 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3290 return &XEXP (x, 0);
3292 split = find_split_point (&XEXP (x, 0), insn);
3298 /* Otherwise, we don't have a split point. */
3302 /* Throughout X, replace FROM with TO, and return the result.
3303 The result is TO if X is FROM;
3304 otherwise the result is X, but its contents may have been modified.
3305 If they were modified, a record was made in undobuf so that
3306 undo_all will (among other things) return X to its original state.
3308 If the number of changes necessary is too much to record to undo,
3309 the excess changes are not made, so the result is invalid.
3310 The changes already made can still be undone.
3311 undobuf.num_undo is incremented for such changes, so by testing that
3312 the caller can tell whether the result is valid.
3314 `n_occurrences' is incremented each time FROM is replaced.
3316 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3318 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3319 by copying if `n_occurrences' is non-zero. */
3322 subst (x, from, to, in_dest, unique_copy)
3327 enum rtx_code code = GET_CODE (x);
3328 enum machine_mode op0_mode = VOIDmode;
3333 /* Two expressions are equal if they are identical copies of a shared
3334 RTX or if they are both registers with the same register number
3337 #define COMBINE_RTX_EQUAL_P(X,Y) \
3339 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3340 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3342 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3345 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3348 /* If X and FROM are the same register but different modes, they will
3349 not have been seen as equal above. However, flow.c will make a
3350 LOG_LINKS entry for that case. If we do nothing, we will try to
3351 rerecognize our original insn and, when it succeeds, we will
3352 delete the feeding insn, which is incorrect.
3354 So force this insn not to match in this (rare) case. */
3355 if (! in_dest && code == REG && GET_CODE (from) == REG
3356 && REGNO (x) == REGNO (from))
3357 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3359 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3360 of which may contain things that can be combined. */
3361 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3364 /* It is possible to have a subexpression appear twice in the insn.
3365 Suppose that FROM is a register that appears within TO.
3366 Then, after that subexpression has been scanned once by `subst',
3367 the second time it is scanned, TO may be found. If we were
3368 to scan TO here, we would find FROM within it and create a
3369 self-referent rtl structure which is completely wrong. */
3370 if (COMBINE_RTX_EQUAL_P (x, to))
3373 /* Parallel asm_operands need special attention because all of the
3374 inputs are shared across the arms. Furthermore, unsharing the
3375 rtl results in recognition failures. Failure to handle this case
3376 specially can result in circular rtl.
3378 Solve this by doing a normal pass across the first entry of the
3379 parallel, and only processing the SET_DESTs of the subsequent
3382 if (code == PARALLEL
3383 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3384 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3386 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3388 /* If this substitution failed, this whole thing fails. */
3389 if (GET_CODE (new) == CLOBBER
3390 && XEXP (new, 0) == const0_rtx)
3393 SUBST (XVECEXP (x, 0, 0), new);
3395 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3397 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3399 if (GET_CODE (dest) != REG
3400 && GET_CODE (dest) != CC0
3401 && GET_CODE (dest) != PC)
3403 new = subst (dest, from, to, 0, unique_copy);
3405 /* If this substitution failed, this whole thing fails. */
3406 if (GET_CODE (new) == CLOBBER
3407 && XEXP (new, 0) == const0_rtx)
3410 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3416 len = GET_RTX_LENGTH (code);
3417 fmt = GET_RTX_FORMAT (code);
3419 /* We don't need to process a SET_DEST that is a register, CC0,
3420 or PC, so set up to skip this common case. All other cases
3421 where we want to suppress replacing something inside a
3422 SET_SRC are handled via the IN_DEST operand. */
3424 && (GET_CODE (SET_DEST (x)) == REG
3425 || GET_CODE (SET_DEST (x)) == CC0
3426 || GET_CODE (SET_DEST (x)) == PC))
3429 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3432 op0_mode = GET_MODE (XEXP (x, 0));
3434 for (i = 0; i < len; i++)
3439 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3441 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3443 new = (unique_copy && n_occurrences
3444 ? copy_rtx (to) : to);
3449 new = subst (XVECEXP (x, i, j), from, to, 0,
3452 /* If this substitution failed, this whole thing
3454 if (GET_CODE (new) == CLOBBER
3455 && XEXP (new, 0) == const0_rtx)
3459 SUBST (XVECEXP (x, i, j), new);
3462 else if (fmt[i] == 'e')
3464 /* If this is a register being set, ignore it. */
3467 && (code == SUBREG || code == STRICT_LOW_PART
3468 || code == ZERO_EXTRACT)
3470 && GET_CODE (new) == REG)
3473 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3475 /* In general, don't install a subreg involving two
3476 modes not tieable. It can worsen register
3477 allocation, and can even make invalid reload
3478 insns, since the reg inside may need to be copied
3479 from in the outside mode, and that may be invalid
3480 if it is an fp reg copied in integer mode.
3482 We allow two exceptions to this: It is valid if
3483 it is inside another SUBREG and the mode of that
3484 SUBREG and the mode of the inside of TO is
3485 tieable and it is valid if X is a SET that copies
3488 if (GET_CODE (to) == SUBREG
3489 && ! MODES_TIEABLE_P (GET_MODE (to),
3490 GET_MODE (SUBREG_REG (to)))
3491 && ! (code == SUBREG
3492 && MODES_TIEABLE_P (GET_MODE (x),
3493 GET_MODE (SUBREG_REG (to))))
3495 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3498 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3500 #ifdef CLASS_CANNOT_CHANGE_MODE
3502 && GET_CODE (to) == REG
3503 && REGNO (to) < FIRST_PSEUDO_REGISTER
3504 && (TEST_HARD_REG_BIT
3505 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3507 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3509 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3512 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3516 /* If we are in a SET_DEST, suppress most cases unless we
3517 have gone inside a MEM, in which case we want to
3518 simplify the address. We assume here that things that
3519 are actually part of the destination have their inner
3520 parts in the first expression. This is true for SUBREG,
3521 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3522 things aside from REG and MEM that should appear in a
3524 new = subst (XEXP (x, i), from, to,
3526 && (code == SUBREG || code == STRICT_LOW_PART
3527 || code == ZERO_EXTRACT))
3529 && i == 0), unique_copy);
3531 /* If we found that we will have to reject this combination,
3532 indicate that by returning the CLOBBER ourselves, rather than
3533 an expression containing it. This will speed things up as
3534 well as prevent accidents where two CLOBBERs are considered
3535 to be equal, thus producing an incorrect simplification. */
3537 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3540 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3542 x = simplify_subreg (GET_MODE (x), new,
3543 GET_MODE (SUBREG_REG (x)),
3548 else if (GET_CODE (new) == CONST_INT
3549 && GET_CODE (x) == ZERO_EXTEND)
3551 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3552 new, GET_MODE (XEXP (x, 0)));
3557 SUBST (XEXP (x, i), new);
3562 /* Try to simplify X. If the simplification changed the code, it is likely
3563 that further simplification will help, so loop, but limit the number
3564 of repetitions that will be performed. */
3566 for (i = 0; i < 4; i++)
3568 /* If X is sufficiently simple, don't bother trying to do anything
3570 if (code != CONST_INT && code != REG && code != CLOBBER)
3571 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3573 if (GET_CODE (x) == code)
3576 code = GET_CODE (x);
3578 /* We no longer know the original mode of operand 0 since we
3579 have changed the form of X) */
3580 op0_mode = VOIDmode;
3586 /* Simplify X, a piece of RTL. We just operate on the expression at the
3587 outer level; call `subst' to simplify recursively. Return the new
3590 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3591 will be the iteration even if an expression with a code different from
3592 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3595 combine_simplify_rtx (x, op0_mode, last, in_dest)
3597 enum machine_mode op0_mode;
3601 enum rtx_code code = GET_CODE (x);
3602 enum machine_mode mode = GET_MODE (x);
3607 /* If this is a commutative operation, put a constant last and a complex
3608 expression first. We don't need to do this for comparisons here. */
3609 if (GET_RTX_CLASS (code) == 'c'
3610 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3613 SUBST (XEXP (x, 0), XEXP (x, 1));
3614 SUBST (XEXP (x, 1), temp);
3617 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3618 sign extension of a PLUS with a constant, reverse the order of the sign
3619 extension and the addition. Note that this not the same as the original
3620 code, but overflow is undefined for signed values. Also note that the
3621 PLUS will have been partially moved "inside" the sign-extension, so that
3622 the first operand of X will really look like:
3623 (ashiftrt (plus (ashift A C4) C5) C4).
3625 (plus (ashiftrt (ashift A C4) C2) C4)
3626 and replace the first operand of X with that expression. Later parts
3627 of this function may simplify the expression further.
3629 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3630 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3631 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3633 We do this to simplify address expressions. */
3635 if ((code == PLUS || code == MINUS || code == MULT)
3636 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3637 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3638 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3639 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3640 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3641 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3642 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3643 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3644 XEXP (XEXP (XEXP (x, 0), 0), 1),
3645 XEXP (XEXP (x, 0), 1))) != 0)
3648 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3649 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3650 INTVAL (XEXP (XEXP (x, 0), 1)));
3652 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3653 INTVAL (XEXP (XEXP (x, 0), 1)));
3655 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3658 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3659 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3660 things. Check for cases where both arms are testing the same
3663 Don't do anything if all operands are very simple. */
3665 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3666 || GET_RTX_CLASS (code) == '<')
3667 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3668 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3669 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3671 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3672 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3673 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3675 || (GET_RTX_CLASS (code) == '1'
3676 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3677 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3678 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3681 rtx cond, true_rtx, false_rtx;
3683 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3685 /* If everything is a comparison, what we have is highly unlikely
3686 to be simpler, so don't use it. */
3687 && ! (GET_RTX_CLASS (code) == '<'
3688 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3689 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3691 rtx cop1 = const0_rtx;
3692 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3694 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3697 /* Simplify the alternative arms; this may collapse the true and
3698 false arms to store-flag values. */
3699 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3700 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3702 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3703 is unlikely to be simpler. */
3704 if (general_operand (true_rtx, VOIDmode)
3705 && general_operand (false_rtx, VOIDmode))
3707 /* Restarting if we generate a store-flag expression will cause
3708 us to loop. Just drop through in this case. */
3710 /* If the result values are STORE_FLAG_VALUE and zero, we can
3711 just make the comparison operation. */
3712 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3713 x = gen_binary (cond_code, mode, cond, cop1);
3714 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3715 && reverse_condition (cond_code) != UNKNOWN)
3716 x = gen_binary (reverse_condition (cond_code),
3719 /* Likewise, we can make the negate of a comparison operation
3720 if the result values are - STORE_FLAG_VALUE and zero. */
3721 else if (GET_CODE (true_rtx) == CONST_INT
3722 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3723 && false_rtx == const0_rtx)
3724 x = simplify_gen_unary (NEG, mode,
3725 gen_binary (cond_code, mode, cond,
3728 else if (GET_CODE (false_rtx) == CONST_INT
3729 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3730 && true_rtx == const0_rtx)
3731 x = simplify_gen_unary (NEG, mode,
3732 gen_binary (reverse_condition
3737 return gen_rtx_IF_THEN_ELSE (mode,
3738 gen_binary (cond_code, VOIDmode,
3740 true_rtx, false_rtx);
3742 code = GET_CODE (x);
3743 op0_mode = VOIDmode;
3748 /* Try to fold this expression in case we have constants that weren't
3751 switch (GET_RTX_CLASS (code))
3754 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3758 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3759 if (cmp_mode == VOIDmode)
3761 cmp_mode = GET_MODE (XEXP (x, 1));
3762 if (cmp_mode == VOIDmode)
3763 cmp_mode = op0_mode;
3765 temp = simplify_relational_operation (code, cmp_mode,
3766 XEXP (x, 0), XEXP (x, 1));
3768 #ifdef FLOAT_STORE_FLAG_VALUE
3769 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3771 if (temp == const0_rtx)
3772 temp = CONST0_RTX (mode);
3774 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3780 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3784 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3785 XEXP (x, 1), XEXP (x, 2));
3792 code = GET_CODE (temp);
3793 op0_mode = VOIDmode;
3794 mode = GET_MODE (temp);
3797 /* First see if we can apply the inverse distributive law. */
3798 if (code == PLUS || code == MINUS
3799 || code == AND || code == IOR || code == XOR)
3801 x = apply_distributive_law (x);
3802 code = GET_CODE (x);
3803 op0_mode = VOIDmode;
3806 /* If CODE is an associative operation not otherwise handled, see if we
3807 can associate some operands. This can win if they are constants or
3808 if they are logically related (i.e. (a & b) & a). */
3809 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3810 || code == AND || code == IOR || code == XOR
3811 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3812 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3813 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3815 if (GET_CODE (XEXP (x, 0)) == code)
3817 rtx other = XEXP (XEXP (x, 0), 0);
3818 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3819 rtx inner_op1 = XEXP (x, 1);
3822 /* Make sure we pass the constant operand if any as the second
3823 one if this is a commutative operation. */
3824 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3826 rtx tem = inner_op0;
3827 inner_op0 = inner_op1;
3830 inner = simplify_binary_operation (code == MINUS ? PLUS
3831 : code == DIV ? MULT
3833 mode, inner_op0, inner_op1);
3835 /* For commutative operations, try the other pair if that one
3837 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3839 other = XEXP (XEXP (x, 0), 1);
3840 inner = simplify_binary_operation (code, mode,
3841 XEXP (XEXP (x, 0), 0),
3846 return gen_binary (code, mode, other, inner);
3850 /* A little bit of algebraic simplification here. */
3854 /* Ensure that our address has any ASHIFTs converted to MULT in case
3855 address-recognizing predicates are called later. */
3856 temp = make_compound_operation (XEXP (x, 0), MEM);
3857 SUBST (XEXP (x, 0), temp);
3861 if (op0_mode == VOIDmode)
3862 op0_mode = GET_MODE (SUBREG_REG (x));
3864 /* simplify_subreg can't use gen_lowpart_for_combine. */
3865 if (CONSTANT_P (SUBREG_REG (x))
3866 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
3867 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3869 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3873 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3879 /* Don't change the mode of the MEM if that would change the meaning
3881 if (GET_CODE (SUBREG_REG (x)) == MEM
3882 && (MEM_VOLATILE_P (SUBREG_REG (x))
3883 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3884 return gen_rtx_CLOBBER (mode, const0_rtx);
3886 /* Note that we cannot do any narrowing for non-constants since
3887 we might have been counting on using the fact that some bits were
3888 zero. We now do this in the SET. */
3893 /* (not (plus X -1)) can become (neg X). */
3894 if (GET_CODE (XEXP (x, 0)) == PLUS
3895 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3896 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3898 /* Similarly, (not (neg X)) is (plus X -1). */
3899 if (GET_CODE (XEXP (x, 0)) == NEG)
3900 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3902 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3903 if (GET_CODE (XEXP (x, 0)) == XOR
3904 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3905 && (temp = simplify_unary_operation (NOT, mode,
3906 XEXP (XEXP (x, 0), 1),
3908 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3910 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3911 other than 1, but that is not valid. We could do a similar
3912 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3913 but this doesn't seem common enough to bother with. */
3914 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3915 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3916 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3918 XEXP (XEXP (x, 0), 1));
3920 if (GET_CODE (XEXP (x, 0)) == SUBREG
3921 && subreg_lowpart_p (XEXP (x, 0))
3922 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3923 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3924 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3925 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3927 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3929 x = gen_rtx_ROTATE (inner_mode,
3930 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3932 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3933 return gen_lowpart_for_combine (mode, x);
3936 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3937 reversing the comparison code if valid. */
3938 if (STORE_FLAG_VALUE == -1
3939 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3940 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3941 XEXP (XEXP (x, 0), 1))))
3944 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3945 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3946 perform the above simplification. */
3948 if (STORE_FLAG_VALUE == -1
3949 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3950 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3951 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3952 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3954 /* Apply De Morgan's laws to reduce number of patterns for machines
3955 with negating logical insns (and-not, nand, etc.). If result has
3956 only one NOT, put it first, since that is how the patterns are
3959 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3961 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3962 enum machine_mode op_mode;
3964 op_mode = GET_MODE (in1);
3965 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3967 op_mode = GET_MODE (in2);
3968 if (op_mode == VOIDmode)
3970 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3972 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3975 in2 = in1; in1 = tem;
3978 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3984 /* (neg (plus X 1)) can become (not X). */
3985 if (GET_CODE (XEXP (x, 0)) == PLUS
3986 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3987 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3989 /* Similarly, (neg (not X)) is (plus X 1). */
3990 if (GET_CODE (XEXP (x, 0)) == NOT)
3991 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3993 /* (neg (minus X Y)) can become (minus Y X). */
3994 if (GET_CODE (XEXP (x, 0)) == MINUS
3995 && (! FLOAT_MODE_P (mode)
3996 /* x-y != -(y-x) with IEEE floating point. */
3997 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3998 || flag_unsafe_math_optimizations))
3999 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4000 XEXP (XEXP (x, 0), 0));
4002 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4003 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4004 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4005 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4007 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4008 if we can then eliminate the NEG (e.g.,
4009 if the operand is a constant). */
4011 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4013 temp = simplify_unary_operation (NEG, mode,
4014 XEXP (XEXP (x, 0), 0), mode);
4016 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4019 temp = expand_compound_operation (XEXP (x, 0));
4021 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4022 replaced by (lshiftrt X C). This will convert
4023 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4025 if (GET_CODE (temp) == ASHIFTRT
4026 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4027 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4028 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4029 INTVAL (XEXP (temp, 1)));
4031 /* If X has only a single bit that might be nonzero, say, bit I, convert
4032 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4033 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4034 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4035 or a SUBREG of one since we'd be making the expression more
4036 complex if it was just a register. */
4038 if (GET_CODE (temp) != REG
4039 && ! (GET_CODE (temp) == SUBREG
4040 && GET_CODE (SUBREG_REG (temp)) == REG)
4041 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4043 rtx temp1 = simplify_shift_const
4044 (NULL_RTX, ASHIFTRT, mode,
4045 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4046 GET_MODE_BITSIZE (mode) - 1 - i),
4047 GET_MODE_BITSIZE (mode) - 1 - i);
4049 /* If all we did was surround TEMP with the two shifts, we
4050 haven't improved anything, so don't use it. Otherwise,
4051 we are better off with TEMP1. */
4052 if (GET_CODE (temp1) != ASHIFTRT
4053 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4054 || XEXP (XEXP (temp1, 0), 0) != temp)
4060 /* We can't handle truncation to a partial integer mode here
4061 because we don't know the real bitsize of the partial
4063 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4066 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4067 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4068 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4070 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4071 GET_MODE_MASK (mode), NULL_RTX, 0));
4073 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4074 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4075 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4076 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4077 return XEXP (XEXP (x, 0), 0);
4079 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4080 (OP:SI foo:SI) if OP is NEG or ABS. */
4081 if ((GET_CODE (XEXP (x, 0)) == ABS
4082 || GET_CODE (XEXP (x, 0)) == NEG)
4083 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4084 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4085 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4086 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4087 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4089 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4091 if (GET_CODE (XEXP (x, 0)) == SUBREG
4092 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4093 && subreg_lowpart_p (XEXP (x, 0)))
4094 return SUBREG_REG (XEXP (x, 0));
4096 /* If we know that the value is already truncated, we can
4097 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4098 is nonzero for the corresponding modes. But don't do this
4099 for an (LSHIFTRT (MULT ...)) since this will cause problems
4100 with the umulXi3_highpart patterns. */
4101 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4102 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4103 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4104 >= GET_MODE_BITSIZE (mode) + 1
4105 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4106 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4107 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4109 /* A truncate of a comparison can be replaced with a subreg if
4110 STORE_FLAG_VALUE permits. This is like the previous test,
4111 but it works even if the comparison is done in a mode larger
4112 than HOST_BITS_PER_WIDE_INT. */
4113 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4114 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4115 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4116 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4118 /* Similarly, a truncate of a register whose value is a
4119 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4121 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4122 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4123 && (temp = get_last_value (XEXP (x, 0)))
4124 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4125 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4129 case FLOAT_TRUNCATE:
4130 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4131 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4132 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4133 return XEXP (XEXP (x, 0), 0);
4135 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4136 (OP:SF foo:SF) if OP is NEG or ABS. */
4137 if ((GET_CODE (XEXP (x, 0)) == ABS
4138 || GET_CODE (XEXP (x, 0)) == NEG)
4139 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4140 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4141 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4142 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4144 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4145 is (float_truncate:SF x). */
4146 if (GET_CODE (XEXP (x, 0)) == SUBREG
4147 && subreg_lowpart_p (XEXP (x, 0))
4148 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4149 return SUBREG_REG (XEXP (x, 0));
4154 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4155 using cc0, in which case we want to leave it as a COMPARE
4156 so we can distinguish it from a register-register-copy. */
4157 if (XEXP (x, 1) == const0_rtx)
4160 /* In IEEE floating point, x-0 is not the same as x. */
4161 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4162 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4163 || flag_unsafe_math_optimizations)
4164 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4170 /* (const (const X)) can become (const X). Do it this way rather than
4171 returning the inner CONST since CONST can be shared with a
4173 if (GET_CODE (XEXP (x, 0)) == CONST)
4174 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4179 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4180 can add in an offset. find_split_point will split this address up
4181 again if it doesn't match. */
4182 if (GET_CODE (XEXP (x, 0)) == HIGH
4183 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4189 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4190 outermost. That's because that's the way indexed addresses are
4191 supposed to appear. This code used to check many more cases, but
4192 they are now checked elsewhere. */
4193 if (GET_CODE (XEXP (x, 0)) == PLUS
4194 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4195 return gen_binary (PLUS, mode,
4196 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4198 XEXP (XEXP (x, 0), 1));
4200 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4201 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4202 bit-field and can be replaced by either a sign_extend or a
4203 sign_extract. The `and' may be a zero_extend and the two
4204 <c>, -<c> constants may be reversed. */
4205 if (GET_CODE (XEXP (x, 0)) == XOR
4206 && GET_CODE (XEXP (x, 1)) == CONST_INT
4207 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4208 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4209 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4210 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4211 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4212 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4213 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4214 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4215 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4216 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4217 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4218 == (unsigned int) i + 1))))
4219 return simplify_shift_const
4220 (NULL_RTX, ASHIFTRT, mode,
4221 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4222 XEXP (XEXP (XEXP (x, 0), 0), 0),
4223 GET_MODE_BITSIZE (mode) - (i + 1)),
4224 GET_MODE_BITSIZE (mode) - (i + 1));
4226 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4227 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4228 is 1. This produces better code than the alternative immediately
4230 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4231 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4232 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4233 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4234 XEXP (XEXP (x, 0), 0),
4235 XEXP (XEXP (x, 0), 1))))
4237 simplify_gen_unary (NEG, mode, reversed, mode);
4239 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4240 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4241 the bitsize of the mode - 1. This allows simplification of
4242 "a = (b & 8) == 0;" */
4243 if (XEXP (x, 1) == constm1_rtx
4244 && GET_CODE (XEXP (x, 0)) != REG
4245 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4246 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4247 && nonzero_bits (XEXP (x, 0), mode) == 1)
4248 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4249 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4250 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4251 GET_MODE_BITSIZE (mode) - 1),
4252 GET_MODE_BITSIZE (mode) - 1);
4254 /* If we are adding two things that have no bits in common, convert
4255 the addition into an IOR. This will often be further simplified,
4256 for example in cases like ((a & 1) + (a & 2)), which can
4259 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4260 && (nonzero_bits (XEXP (x, 0), mode)
4261 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4263 /* Try to simplify the expression further. */
4264 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4265 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4267 /* If we could, great. If not, do not go ahead with the IOR
4268 replacement, since PLUS appears in many special purpose
4269 address arithmetic instructions. */
4270 if (GET_CODE (temp) != CLOBBER && temp != tor)
4276 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4277 by reversing the comparison code if valid. */
4278 if (STORE_FLAG_VALUE == 1
4279 && XEXP (x, 0) == const1_rtx
4280 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4281 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4282 XEXP (XEXP (x, 1), 0),
4283 XEXP (XEXP (x, 1), 1))))
4286 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4287 (and <foo> (const_int pow2-1)) */
4288 if (GET_CODE (XEXP (x, 1)) == AND
4289 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4290 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4291 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4292 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4293 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4295 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4297 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4298 return gen_binary (MINUS, mode,
4299 gen_binary (MINUS, mode, XEXP (x, 0),
4300 XEXP (XEXP (x, 1), 0)),
4301 XEXP (XEXP (x, 1), 1));
4305 /* If we have (mult (plus A B) C), apply the distributive law and then
4306 the inverse distributive law to see if things simplify. This
4307 occurs mostly in addresses, often when unrolling loops. */
4309 if (GET_CODE (XEXP (x, 0)) == PLUS)
4311 x = apply_distributive_law
4312 (gen_binary (PLUS, mode,
4313 gen_binary (MULT, mode,
4314 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4315 gen_binary (MULT, mode,
4316 XEXP (XEXP (x, 0), 1),
4317 copy_rtx (XEXP (x, 1)))));
4319 if (GET_CODE (x) != MULT)
4322 /* Try simplify a*(b/c) as (a*b)/c. */
4323 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4324 && GET_CODE (XEXP (x, 0)) == DIV)
4326 rtx tem = simplify_binary_operation (MULT, mode,
4327 XEXP (XEXP (x, 0), 0),
4330 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4335 /* If this is a divide by a power of two, treat it as a shift if
4336 its first operand is a shift. */
4337 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4338 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4339 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4340 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4341 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4342 || GET_CODE (XEXP (x, 0)) == ROTATE
4343 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4344 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4348 case GT: case GTU: case GE: case GEU:
4349 case LT: case LTU: case LE: case LEU:
4350 case UNEQ: case LTGT:
4351 case UNGT: case UNGE:
4352 case UNLT: case UNLE:
4353 case UNORDERED: case ORDERED:
4354 /* If the first operand is a condition code, we can't do anything
4356 if (GET_CODE (XEXP (x, 0)) == COMPARE
4357 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4359 && XEXP (x, 0) != cc0_rtx
4363 rtx op0 = XEXP (x, 0);
4364 rtx op1 = XEXP (x, 1);
4365 enum rtx_code new_code;
4367 if (GET_CODE (op0) == COMPARE)
4368 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4370 /* Simplify our comparison, if possible. */
4371 new_code = simplify_comparison (code, &op0, &op1);
4373 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4374 if only the low-order bit is possibly nonzero in X (such as when
4375 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4376 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4377 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4380 Remove any ZERO_EXTRACT we made when thinking this was a
4381 comparison. It may now be simpler to use, e.g., an AND. If a
4382 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4383 the call to make_compound_operation in the SET case. */
4385 if (STORE_FLAG_VALUE == 1
4386 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4387 && op1 == const0_rtx
4388 && mode == GET_MODE (op0)
4389 && nonzero_bits (op0, mode) == 1)
4390 return gen_lowpart_for_combine (mode,
4391 expand_compound_operation (op0));
4393 else if (STORE_FLAG_VALUE == 1
4394 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4395 && op1 == const0_rtx
4396 && mode == GET_MODE (op0)
4397 && (num_sign_bit_copies (op0, mode)
4398 == GET_MODE_BITSIZE (mode)))
4400 op0 = expand_compound_operation (op0);
4401 return simplify_gen_unary (NEG, mode,
4402 gen_lowpart_for_combine (mode, op0),
4406 else if (STORE_FLAG_VALUE == 1
4407 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4408 && op1 == const0_rtx
4409 && mode == GET_MODE (op0)
4410 && nonzero_bits (op0, mode) == 1)
4412 op0 = expand_compound_operation (op0);
4413 return gen_binary (XOR, mode,
4414 gen_lowpart_for_combine (mode, op0),
4418 else if (STORE_FLAG_VALUE == 1
4419 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4420 && op1 == const0_rtx
4421 && mode == GET_MODE (op0)
4422 && (num_sign_bit_copies (op0, mode)
4423 == GET_MODE_BITSIZE (mode)))
4425 op0 = expand_compound_operation (op0);
4426 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4429 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4431 if (STORE_FLAG_VALUE == -1
4432 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4433 && op1 == const0_rtx
4434 && (num_sign_bit_copies (op0, mode)
4435 == GET_MODE_BITSIZE (mode)))
4436 return gen_lowpart_for_combine (mode,
4437 expand_compound_operation (op0));
4439 else if (STORE_FLAG_VALUE == -1
4440 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4441 && op1 == const0_rtx
4442 && mode == GET_MODE (op0)
4443 && nonzero_bits (op0, mode) == 1)
4445 op0 = expand_compound_operation (op0);
4446 return simplify_gen_unary (NEG, mode,
4447 gen_lowpart_for_combine (mode, op0),
4451 else if (STORE_FLAG_VALUE == -1
4452 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4453 && op1 == const0_rtx
4454 && mode == GET_MODE (op0)
4455 && (num_sign_bit_copies (op0, mode)
4456 == GET_MODE_BITSIZE (mode)))
4458 op0 = expand_compound_operation (op0);
4459 return simplify_gen_unary (NOT, mode,
4460 gen_lowpart_for_combine (mode, op0),
4464 /* If X is 0/1, (eq X 0) is X-1. */
4465 else if (STORE_FLAG_VALUE == -1
4466 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4467 && op1 == const0_rtx
4468 && mode == GET_MODE (op0)
4469 && nonzero_bits (op0, mode) == 1)
4471 op0 = expand_compound_operation (op0);
4472 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4475 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4476 one bit that might be nonzero, we can convert (ne x 0) to
4477 (ashift x c) where C puts the bit in the sign bit. Remove any
4478 AND with STORE_FLAG_VALUE when we are done, since we are only
4479 going to test the sign bit. */
4480 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4481 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4482 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4483 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4484 && op1 == const0_rtx
4485 && mode == GET_MODE (op0)
4486 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4488 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4489 expand_compound_operation (op0),
4490 GET_MODE_BITSIZE (mode) - 1 - i);
4491 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4497 /* If the code changed, return a whole new comparison. */
4498 if (new_code != code)
4499 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4501 /* Otherwise, keep this operation, but maybe change its operands.
4502 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4503 SUBST (XEXP (x, 0), op0);
4504 SUBST (XEXP (x, 1), op1);
4509 return simplify_if_then_else (x);
4515 /* If we are processing SET_DEST, we are done. */
4519 return expand_compound_operation (x);
4522 return simplify_set (x);
4527 return simplify_logical (x, last);
4530 /* (abs (neg <foo>)) -> (abs <foo>) */
4531 if (GET_CODE (XEXP (x, 0)) == NEG)
4532 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4534 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4536 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4539 /* If operand is something known to be positive, ignore the ABS. */
4540 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4541 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4542 <= HOST_BITS_PER_WIDE_INT)
4543 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4544 & ((HOST_WIDE_INT) 1
4545 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4549 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4550 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4551 return gen_rtx_NEG (mode, XEXP (x, 0));
4556 /* (ffs (*_extend <X>)) = (ffs <X>) */
4557 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4558 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4559 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4563 /* (float (sign_extend <X>)) = (float <X>). */
4564 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4565 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4573 /* If this is a shift by a constant amount, simplify it. */
4574 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4575 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4576 INTVAL (XEXP (x, 1)));
4578 #ifdef SHIFT_COUNT_TRUNCATED
4579 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4581 force_to_mode (XEXP (x, 1), GET_MODE (x),
4583 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4592 rtx op0 = XEXP (x, 0);
4593 rtx op1 = XEXP (x, 1);
4596 if (GET_CODE (op1) != PARALLEL)
4598 len = XVECLEN (op1, 0);
4600 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4601 && GET_CODE (op0) == VEC_CONCAT)
4603 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4605 /* Try to find the element in the VEC_CONCAT. */
4608 if (GET_MODE (op0) == GET_MODE (x))
4610 if (GET_CODE (op0) == VEC_CONCAT)
4612 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4613 if (op0_size < offset)
4614 op0 = XEXP (op0, 0);
4618 op0 = XEXP (op0, 1);
4636 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4639 simplify_if_then_else (x)
4642 enum machine_mode mode = GET_MODE (x);
4643 rtx cond = XEXP (x, 0);
4644 rtx true_rtx = XEXP (x, 1);
4645 rtx false_rtx = XEXP (x, 2);
4646 enum rtx_code true_code = GET_CODE (cond);
4647 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4650 enum rtx_code false_code;
4653 /* Simplify storing of the truth value. */
4654 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4655 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4657 /* Also when the truth value has to be reversed. */
4659 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4660 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4664 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4665 in it is being compared against certain values. Get the true and false
4666 comparisons and see if that says anything about the value of each arm. */
4669 && ((false_code = combine_reversed_comparison_code (cond))
4671 && GET_CODE (XEXP (cond, 0)) == REG)
4674 rtx from = XEXP (cond, 0);
4675 rtx true_val = XEXP (cond, 1);
4676 rtx false_val = true_val;
4679 /* If FALSE_CODE is EQ, swap the codes and arms. */
4681 if (false_code == EQ)
4683 swapped = 1, true_code = EQ, false_code = NE;
4684 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4687 /* If we are comparing against zero and the expression being tested has
4688 only a single bit that might be nonzero, that is its value when it is
4689 not equal to zero. Similarly if it is known to be -1 or 0. */
4691 if (true_code == EQ && true_val == const0_rtx
4692 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4693 false_code = EQ, false_val = GEN_INT (nzb);
4694 else if (true_code == EQ && true_val == const0_rtx
4695 && (num_sign_bit_copies (from, GET_MODE (from))
4696 == GET_MODE_BITSIZE (GET_MODE (from))))
4697 false_code = EQ, false_val = constm1_rtx;
4699 /* Now simplify an arm if we know the value of the register in the
4700 branch and it is used in the arm. Be careful due to the potential
4701 of locally-shared RTL. */
4703 if (reg_mentioned_p (from, true_rtx))
4704 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4706 pc_rtx, pc_rtx, 0, 0);
4707 if (reg_mentioned_p (from, false_rtx))
4708 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4710 pc_rtx, pc_rtx, 0, 0);
4712 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4713 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4715 true_rtx = XEXP (x, 1);
4716 false_rtx = XEXP (x, 2);
4717 true_code = GET_CODE (cond);
4720 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4721 reversed, do so to avoid needing two sets of patterns for
4722 subtract-and-branch insns. Similarly if we have a constant in the true
4723 arm, the false arm is the same as the first operand of the comparison, or
4724 the false arm is more complicated than the true arm. */
4727 && combine_reversed_comparison_code (cond) != UNKNOWN
4728 && (true_rtx == pc_rtx
4729 || (CONSTANT_P (true_rtx)
4730 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4731 || true_rtx == const0_rtx
4732 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4733 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4734 || (GET_CODE (true_rtx) == SUBREG
4735 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4736 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4737 || reg_mentioned_p (true_rtx, false_rtx)
4738 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4740 true_code = reversed_comparison_code (cond, NULL);
4742 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4745 SUBST (XEXP (x, 1), false_rtx);
4746 SUBST (XEXP (x, 2), true_rtx);
4748 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4751 /* It is possible that the conditional has been simplified out. */
4752 true_code = GET_CODE (cond);
4753 comparison_p = GET_RTX_CLASS (true_code) == '<';
4756 /* If the two arms are identical, we don't need the comparison. */
4758 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4761 /* Convert a == b ? b : a to "a". */
4762 if (true_code == EQ && ! side_effects_p (cond)
4763 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4764 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4765 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4767 else if (true_code == NE && ! side_effects_p (cond)
4768 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4769 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4770 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4773 /* Look for cases where we have (abs x) or (neg (abs X)). */
4775 if (GET_MODE_CLASS (mode) == MODE_INT
4776 && GET_CODE (false_rtx) == NEG
4777 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4779 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4780 && ! side_effects_p (true_rtx))
4785 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4789 simplify_gen_unary (NEG, mode,
4790 simplify_gen_unary (ABS, mode, true_rtx, mode),
4796 /* Look for MIN or MAX. */
4798 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4800 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4801 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4802 && ! side_effects_p (cond))
4807 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4810 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4813 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4816 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4821 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4822 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4823 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4824 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4825 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4826 neither 1 or -1, but it isn't worth checking for. */
4828 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4829 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4831 rtx t = make_compound_operation (true_rtx, SET);
4832 rtx f = make_compound_operation (false_rtx, SET);
4833 rtx cond_op0 = XEXP (cond, 0);
4834 rtx cond_op1 = XEXP (cond, 1);
4835 enum rtx_code op = NIL, extend_op = NIL;
4836 enum machine_mode m = mode;
4837 rtx z = 0, c1 = NULL_RTX;
4839 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4840 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4841 || GET_CODE (t) == ASHIFT
4842 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4843 && rtx_equal_p (XEXP (t, 0), f))
4844 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4846 /* If an identity-zero op is commutative, check whether there
4847 would be a match if we swapped the operands. */
4848 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4849 || GET_CODE (t) == XOR)
4850 && rtx_equal_p (XEXP (t, 1), f))
4851 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4852 else if (GET_CODE (t) == SIGN_EXTEND
4853 && (GET_CODE (XEXP (t, 0)) == PLUS
4854 || GET_CODE (XEXP (t, 0)) == MINUS
4855 || GET_CODE (XEXP (t, 0)) == IOR
4856 || GET_CODE (XEXP (t, 0)) == XOR
4857 || GET_CODE (XEXP (t, 0)) == ASHIFT
4858 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4859 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4860 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4861 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4862 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4863 && (num_sign_bit_copies (f, GET_MODE (f))
4864 > (GET_MODE_BITSIZE (mode)
4865 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4867 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4868 extend_op = SIGN_EXTEND;
4869 m = GET_MODE (XEXP (t, 0));
4871 else if (GET_CODE (t) == SIGN_EXTEND
4872 && (GET_CODE (XEXP (t, 0)) == PLUS
4873 || GET_CODE (XEXP (t, 0)) == IOR
4874 || GET_CODE (XEXP (t, 0)) == XOR)
4875 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4876 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4877 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4878 && (num_sign_bit_copies (f, GET_MODE (f))
4879 > (GET_MODE_BITSIZE (mode)
4880 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4882 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4883 extend_op = SIGN_EXTEND;
4884 m = GET_MODE (XEXP (t, 0));
4886 else if (GET_CODE (t) == ZERO_EXTEND
4887 && (GET_CODE (XEXP (t, 0)) == PLUS
4888 || GET_CODE (XEXP (t, 0)) == MINUS
4889 || GET_CODE (XEXP (t, 0)) == IOR
4890 || GET_CODE (XEXP (t, 0)) == XOR
4891 || GET_CODE (XEXP (t, 0)) == ASHIFT
4892 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4893 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4894 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4895 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4896 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4897 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4898 && ((nonzero_bits (f, GET_MODE (f))
4899 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4902 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4903 extend_op = ZERO_EXTEND;
4904 m = GET_MODE (XEXP (t, 0));
4906 else if (GET_CODE (t) == ZERO_EXTEND
4907 && (GET_CODE (XEXP (t, 0)) == PLUS
4908 || GET_CODE (XEXP (t, 0)) == IOR
4909 || GET_CODE (XEXP (t, 0)) == XOR)
4910 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4911 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4912 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4913 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4914 && ((nonzero_bits (f, GET_MODE (f))
4915 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4918 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4919 extend_op = ZERO_EXTEND;
4920 m = GET_MODE (XEXP (t, 0));
4925 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4926 pc_rtx, pc_rtx, 0, 0);
4927 temp = gen_binary (MULT, m, temp,
4928 gen_binary (MULT, m, c1, const_true_rtx));
4929 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4930 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4932 if (extend_op != NIL)
4933 temp = simplify_gen_unary (extend_op, mode, temp, m);
4939 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4940 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4941 negation of a single bit, we can convert this operation to a shift. We
4942 can actually do this more generally, but it doesn't seem worth it. */
4944 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4945 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4946 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4947 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4948 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4949 == GET_MODE_BITSIZE (mode))
4950 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4952 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4953 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4958 /* Simplify X, a SET expression. Return the new expression. */
4964 rtx src = SET_SRC (x);
4965 rtx dest = SET_DEST (x);
4966 enum machine_mode mode
4967 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4971 /* (set (pc) (return)) gets written as (return). */
4972 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4975 /* Now that we know for sure which bits of SRC we are using, see if we can
4976 simplify the expression for the object knowing that we only need the
4979 if (GET_MODE_CLASS (mode) == MODE_INT)
4981 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4982 SUBST (SET_SRC (x), src);
4985 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4986 the comparison result and try to simplify it unless we already have used
4987 undobuf.other_insn. */
4988 if ((GET_CODE (src) == COMPARE
4993 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4994 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4995 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4996 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4998 enum rtx_code old_code = GET_CODE (*cc_use);
4999 enum rtx_code new_code;
5001 int other_changed = 0;
5002 enum machine_mode compare_mode = GET_MODE (dest);
5004 if (GET_CODE (src) == COMPARE)
5005 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5007 op0 = src, op1 = const0_rtx;
5009 /* Simplify our comparison, if possible. */
5010 new_code = simplify_comparison (old_code, &op0, &op1);
5012 #ifdef EXTRA_CC_MODES
5013 /* If this machine has CC modes other than CCmode, check to see if we
5014 need to use a different CC mode here. */
5015 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5016 #endif /* EXTRA_CC_MODES */
5018 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5019 /* If the mode changed, we have to change SET_DEST, the mode in the
5020 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5021 a hard register, just build new versions with the proper mode. If it
5022 is a pseudo, we lose unless it is only time we set the pseudo, in
5023 which case we can safely change its mode. */
5024 if (compare_mode != GET_MODE (dest))
5026 unsigned int regno = REGNO (dest);
5027 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5029 if (regno < FIRST_PSEUDO_REGISTER
5030 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5032 if (regno >= FIRST_PSEUDO_REGISTER)
5033 SUBST (regno_reg_rtx[regno], new_dest);
5035 SUBST (SET_DEST (x), new_dest);
5036 SUBST (XEXP (*cc_use, 0), new_dest);
5044 /* If the code changed, we have to build a new comparison in
5045 undobuf.other_insn. */
5046 if (new_code != old_code)
5048 unsigned HOST_WIDE_INT mask;
5050 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5053 /* If the only change we made was to change an EQ into an NE or
5054 vice versa, OP0 has only one bit that might be nonzero, and OP1
5055 is zero, check if changing the user of the condition code will
5056 produce a valid insn. If it won't, we can keep the original code
5057 in that insn by surrounding our operation with an XOR. */
5059 if (((old_code == NE && new_code == EQ)
5060 || (old_code == EQ && new_code == NE))
5061 && ! other_changed && op1 == const0_rtx
5062 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5063 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5065 rtx pat = PATTERN (other_insn), note = 0;
5067 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5068 && ! check_asm_operands (pat)))
5070 PUT_CODE (*cc_use, old_code);
5073 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5081 undobuf.other_insn = other_insn;
5084 /* If we are now comparing against zero, change our source if
5085 needed. If we do not use cc0, we always have a COMPARE. */
5086 if (op1 == const0_rtx && dest == cc0_rtx)
5088 SUBST (SET_SRC (x), op0);
5094 /* Otherwise, if we didn't previously have a COMPARE in the
5095 correct mode, we need one. */
5096 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5098 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5103 /* Otherwise, update the COMPARE if needed. */
5104 SUBST (XEXP (src, 0), op0);
5105 SUBST (XEXP (src, 1), op1);
5110 /* Get SET_SRC in a form where we have placed back any
5111 compound expressions. Then do the checks below. */
5112 src = make_compound_operation (src, SET);
5113 SUBST (SET_SRC (x), src);
5116 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5117 and X being a REG or (subreg (reg)), we may be able to convert this to
5118 (set (subreg:m2 x) (op)).
5120 We can always do this if M1 is narrower than M2 because that means that
5121 we only care about the low bits of the result.
5123 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5124 perform a narrower operation than requested since the high-order bits will
5125 be undefined. On machine where it is defined, this transformation is safe
5126 as long as M1 and M2 have the same number of words. */
5128 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5129 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5130 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5132 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5133 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5134 #ifndef WORD_REGISTER_OPERATIONS
5135 && (GET_MODE_SIZE (GET_MODE (src))
5136 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5138 #ifdef CLASS_CANNOT_CHANGE_MODE
5139 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5140 && (TEST_HARD_REG_BIT
5141 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5143 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5144 GET_MODE (SUBREG_REG (src))))
5146 && (GET_CODE (dest) == REG
5147 || (GET_CODE (dest) == SUBREG
5148 && GET_CODE (SUBREG_REG (dest)) == REG)))
5150 SUBST (SET_DEST (x),
5151 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5153 SUBST (SET_SRC (x), SUBREG_REG (src));
5155 src = SET_SRC (x), dest = SET_DEST (x);
5158 #ifdef LOAD_EXTEND_OP
5159 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5160 would require a paradoxical subreg. Replace the subreg with a
5161 zero_extend to avoid the reload that would otherwise be required. */
5163 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5164 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5165 && SUBREG_BYTE (src) == 0
5166 && (GET_MODE_SIZE (GET_MODE (src))
5167 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5168 && GET_CODE (SUBREG_REG (src)) == MEM)
5171 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5172 GET_MODE (src), SUBREG_REG (src)));
5178 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5179 are comparing an item known to be 0 or -1 against 0, use a logical
5180 operation instead. Check for one of the arms being an IOR of the other
5181 arm with some value. We compute three terms to be IOR'ed together. In
5182 practice, at most two will be nonzero. Then we do the IOR's. */
5184 if (GET_CODE (dest) != PC
5185 && GET_CODE (src) == IF_THEN_ELSE
5186 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5187 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5188 && XEXP (XEXP (src, 0), 1) == const0_rtx
5189 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5190 #ifdef HAVE_conditional_move
5191 && ! can_conditionally_move_p (GET_MODE (src))
5193 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5194 GET_MODE (XEXP (XEXP (src, 0), 0)))
5195 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5196 && ! side_effects_p (src))
5198 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5199 ? XEXP (src, 1) : XEXP (src, 2));
5200 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5201 ? XEXP (src, 2) : XEXP (src, 1));
5202 rtx term1 = const0_rtx, term2, term3;
5204 if (GET_CODE (true_rtx) == IOR
5205 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5206 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5207 else if (GET_CODE (true_rtx) == IOR
5208 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5209 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5210 else if (GET_CODE (false_rtx) == IOR
5211 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5212 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5213 else if (GET_CODE (false_rtx) == IOR
5214 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5215 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5217 term2 = gen_binary (AND, GET_MODE (src),
5218 XEXP (XEXP (src, 0), 0), true_rtx);
5219 term3 = gen_binary (AND, GET_MODE (src),
5220 simplify_gen_unary (NOT, GET_MODE (src),
5221 XEXP (XEXP (src, 0), 0),
5226 gen_binary (IOR, GET_MODE (src),
5227 gen_binary (IOR, GET_MODE (src), term1, term2),
5233 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5234 whole thing fail. */
5235 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5237 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5240 /* Convert this into a field assignment operation, if possible. */
5241 return make_field_assignment (x);
5244 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5245 result. LAST is nonzero if this is the last retry. */
5248 simplify_logical (x, last)
5252 enum machine_mode mode = GET_MODE (x);
5253 rtx op0 = XEXP (x, 0);
5254 rtx op1 = XEXP (x, 1);
5257 switch (GET_CODE (x))
5260 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5261 insn (and may simplify more). */
5262 if (GET_CODE (op0) == XOR
5263 && rtx_equal_p (XEXP (op0, 0), op1)
5264 && ! side_effects_p (op1))
5265 x = gen_binary (AND, mode,
5266 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5269 if (GET_CODE (op0) == XOR
5270 && rtx_equal_p (XEXP (op0, 1), op1)
5271 && ! side_effects_p (op1))
5272 x = gen_binary (AND, mode,
5273 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5276 /* Similarly for (~(A ^ B)) & A. */
5277 if (GET_CODE (op0) == NOT
5278 && GET_CODE (XEXP (op0, 0)) == XOR
5279 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5280 && ! side_effects_p (op1))
5281 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5283 if (GET_CODE (op0) == NOT
5284 && GET_CODE (XEXP (op0, 0)) == XOR
5285 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5286 && ! side_effects_p (op1))
5287 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5289 /* We can call simplify_and_const_int only if we don't lose
5290 any (sign) bits when converting INTVAL (op1) to
5291 "unsigned HOST_WIDE_INT". */
5292 if (GET_CODE (op1) == CONST_INT
5293 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5294 || INTVAL (op1) > 0))
5296 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5298 /* If we have (ior (and (X C1) C2)) and the next restart would be
5299 the last, simplify this by making C1 as small as possible
5302 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5303 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5304 && GET_CODE (op1) == CONST_INT)
5305 return gen_binary (IOR, mode,
5306 gen_binary (AND, mode, XEXP (op0, 0),
5307 GEN_INT (INTVAL (XEXP (op0, 1))
5308 & ~INTVAL (op1))), op1);
5310 if (GET_CODE (x) != AND)
5313 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5314 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5315 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5318 /* Convert (A | B) & A to A. */
5319 if (GET_CODE (op0) == IOR
5320 && (rtx_equal_p (XEXP (op0, 0), op1)
5321 || rtx_equal_p (XEXP (op0, 1), op1))
5322 && ! side_effects_p (XEXP (op0, 0))
5323 && ! side_effects_p (XEXP (op0, 1)))
5326 /* In the following group of tests (and those in case IOR below),
5327 we start with some combination of logical operations and apply
5328 the distributive law followed by the inverse distributive law.
5329 Most of the time, this results in no change. However, if some of
5330 the operands are the same or inverses of each other, simplifications
5333 For example, (and (ior A B) (not B)) can occur as the result of
5334 expanding a bit field assignment. When we apply the distributive
5335 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5336 which then simplifies to (and (A (not B))).
5338 If we have (and (ior A B) C), apply the distributive law and then
5339 the inverse distributive law to see if things simplify. */
5341 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5343 x = apply_distributive_law
5344 (gen_binary (GET_CODE (op0), mode,
5345 gen_binary (AND, mode, XEXP (op0, 0), op1),
5346 gen_binary (AND, mode, XEXP (op0, 1),
5348 if (GET_CODE (x) != AND)
5352 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5353 return apply_distributive_law
5354 (gen_binary (GET_CODE (op1), mode,
5355 gen_binary (AND, mode, XEXP (op1, 0), op0),
5356 gen_binary (AND, mode, XEXP (op1, 1),
5359 /* Similarly, taking advantage of the fact that
5360 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5362 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5363 return apply_distributive_law
5364 (gen_binary (XOR, mode,
5365 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5366 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5369 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5370 return apply_distributive_law
5371 (gen_binary (XOR, mode,
5372 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5373 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5377 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5378 if (GET_CODE (op1) == CONST_INT
5379 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5380 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5383 /* Convert (A & B) | A to A. */
5384 if (GET_CODE (op0) == AND
5385 && (rtx_equal_p (XEXP (op0, 0), op1)
5386 || rtx_equal_p (XEXP (op0, 1), op1))
5387 && ! side_effects_p (XEXP (op0, 0))
5388 && ! side_effects_p (XEXP (op0, 1)))
5391 /* If we have (ior (and A B) C), apply the distributive law and then
5392 the inverse distributive law to see if things simplify. */
5394 if (GET_CODE (op0) == AND)
5396 x = apply_distributive_law
5397 (gen_binary (AND, mode,
5398 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5399 gen_binary (IOR, mode, XEXP (op0, 1),
5402 if (GET_CODE (x) != IOR)
5406 if (GET_CODE (op1) == AND)
5408 x = apply_distributive_law
5409 (gen_binary (AND, mode,
5410 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5411 gen_binary (IOR, mode, XEXP (op1, 1),
5414 if (GET_CODE (x) != IOR)
5418 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5419 mode size to (rotate A CX). */
5421 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5422 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5423 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5424 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5425 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5426 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5427 == GET_MODE_BITSIZE (mode)))
5428 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5429 (GET_CODE (op0) == ASHIFT
5430 ? XEXP (op0, 1) : XEXP (op1, 1)));
5432 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5433 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5434 does not affect any of the bits in OP1, it can really be done
5435 as a PLUS and we can associate. We do this by seeing if OP1
5436 can be safely shifted left C bits. */
5437 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5438 && GET_CODE (XEXP (op0, 0)) == PLUS
5439 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5440 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5441 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5443 int count = INTVAL (XEXP (op0, 1));
5444 HOST_WIDE_INT mask = INTVAL (op1) << count;
5446 if (mask >> count == INTVAL (op1)
5447 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5449 SUBST (XEXP (XEXP (op0, 0), 1),
5450 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5457 /* If we are XORing two things that have no bits in common,
5458 convert them into an IOR. This helps to detect rotation encoded
5459 using those methods and possibly other simplifications. */
5461 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5462 && (nonzero_bits (op0, mode)
5463 & nonzero_bits (op1, mode)) == 0)
5464 return (gen_binary (IOR, mode, op0, op1));
5466 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5467 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5470 int num_negated = 0;
5472 if (GET_CODE (op0) == NOT)
5473 num_negated++, op0 = XEXP (op0, 0);
5474 if (GET_CODE (op1) == NOT)
5475 num_negated++, op1 = XEXP (op1, 0);
5477 if (num_negated == 2)
5479 SUBST (XEXP (x, 0), op0);
5480 SUBST (XEXP (x, 1), op1);
5482 else if (num_negated == 1)
5484 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5488 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5489 correspond to a machine insn or result in further simplifications
5490 if B is a constant. */
5492 if (GET_CODE (op0) == AND
5493 && rtx_equal_p (XEXP (op0, 1), op1)
5494 && ! side_effects_p (op1))
5495 return gen_binary (AND, mode,
5496 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5499 else if (GET_CODE (op0) == AND
5500 && rtx_equal_p (XEXP (op0, 0), op1)
5501 && ! side_effects_p (op1))
5502 return gen_binary (AND, mode,
5503 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5506 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5507 comparison if STORE_FLAG_VALUE is 1. */
5508 if (STORE_FLAG_VALUE == 1
5509 && op1 == const1_rtx
5510 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5511 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5515 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5516 is (lt foo (const_int 0)), so we can perform the above
5517 simplification if STORE_FLAG_VALUE is 1. */
5519 if (STORE_FLAG_VALUE == 1
5520 && op1 == const1_rtx
5521 && GET_CODE (op0) == LSHIFTRT
5522 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5523 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5524 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5526 /* (xor (comparison foo bar) (const_int sign-bit))
5527 when STORE_FLAG_VALUE is the sign bit. */
5528 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5529 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5530 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5531 && op1 == const_true_rtx
5532 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5533 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5546 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5547 operations" because they can be replaced with two more basic operations.
5548 ZERO_EXTEND is also considered "compound" because it can be replaced with
5549 an AND operation, which is simpler, though only one operation.
5551 The function expand_compound_operation is called with an rtx expression
5552 and will convert it to the appropriate shifts and AND operations,
5553 simplifying at each stage.
5555 The function make_compound_operation is called to convert an expression
5556 consisting of shifts and ANDs into the equivalent compound expression.
5557 It is the inverse of this function, loosely speaking. */
5560 expand_compound_operation (x)
5563 unsigned HOST_WIDE_INT pos = 0, len;
5565 unsigned int modewidth;
5568 switch (GET_CODE (x))
5573 /* We can't necessarily use a const_int for a multiword mode;
5574 it depends on implicitly extending the value.
5575 Since we don't know the right way to extend it,
5576 we can't tell whether the implicit way is right.
5578 Even for a mode that is no wider than a const_int,
5579 we can't win, because we need to sign extend one of its bits through
5580 the rest of it, and we don't know which bit. */
5581 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5584 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5585 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5586 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5587 reloaded. If not for that, MEM's would very rarely be safe.
5589 Reject MODEs bigger than a word, because we might not be able
5590 to reference a two-register group starting with an arbitrary register
5591 (and currently gen_lowpart might crash for a SUBREG). */
5593 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5596 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5597 /* If the inner object has VOIDmode (the only way this can happen
5598 is if it is a ASM_OPERANDS), we can't do anything since we don't
5599 know how much masking to do. */
5608 /* If the operand is a CLOBBER, just return it. */
5609 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5612 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5613 || GET_CODE (XEXP (x, 2)) != CONST_INT
5614 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5617 len = INTVAL (XEXP (x, 1));
5618 pos = INTVAL (XEXP (x, 2));
5620 /* If this goes outside the object being extracted, replace the object
5621 with a (use (mem ...)) construct that only combine understands
5622 and is used only for this purpose. */
5623 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5624 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5626 if (BITS_BIG_ENDIAN)
5627 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5634 /* Convert sign extension to zero extension, if we know that the high
5635 bit is not set, as this is easier to optimize. It will be converted
5636 back to cheaper alternative in make_extraction. */
5637 if (GET_CODE (x) == SIGN_EXTEND
5638 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5639 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5640 & ~(((unsigned HOST_WIDE_INT)
5641 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5645 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5646 return expand_compound_operation (temp);
5649 /* We can optimize some special cases of ZERO_EXTEND. */
5650 if (GET_CODE (x) == ZERO_EXTEND)
5652 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5653 know that the last value didn't have any inappropriate bits
5655 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5656 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5657 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5658 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5659 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5660 return XEXP (XEXP (x, 0), 0);
5662 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5663 if (GET_CODE (XEXP (x, 0)) == SUBREG
5664 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5665 && subreg_lowpart_p (XEXP (x, 0))
5666 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5667 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5668 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5669 return SUBREG_REG (XEXP (x, 0));
5671 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5672 is a comparison and STORE_FLAG_VALUE permits. This is like
5673 the first case, but it works even when GET_MODE (x) is larger
5674 than HOST_WIDE_INT. */
5675 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5676 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5677 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5678 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5679 <= HOST_BITS_PER_WIDE_INT)
5680 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5681 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5682 return XEXP (XEXP (x, 0), 0);
5684 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5685 if (GET_CODE (XEXP (x, 0)) == SUBREG
5686 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5687 && subreg_lowpart_p (XEXP (x, 0))
5688 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5689 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5690 <= HOST_BITS_PER_WIDE_INT)
5691 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5692 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5693 return SUBREG_REG (XEXP (x, 0));
5697 /* If we reach here, we want to return a pair of shifts. The inner
5698 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5699 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5700 logical depending on the value of UNSIGNEDP.
5702 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5703 converted into an AND of a shift.
5705 We must check for the case where the left shift would have a negative
5706 count. This can happen in a case like (x >> 31) & 255 on machines
5707 that can't shift by a constant. On those machines, we would first
5708 combine the shift with the AND to produce a variable-position
5709 extraction. Then the constant of 31 would be substituted in to produce
5710 a such a position. */
5712 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5713 if (modewidth + len >= pos)
5714 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5716 simplify_shift_const (NULL_RTX, ASHIFT,
5719 modewidth - pos - len),
5722 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5723 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5724 simplify_shift_const (NULL_RTX, LSHIFTRT,
5727 ((HOST_WIDE_INT) 1 << len) - 1);
5729 /* Any other cases we can't handle. */
5732 /* If we couldn't do this for some reason, return the original
5734 if (GET_CODE (tem) == CLOBBER)
5740 /* X is a SET which contains an assignment of one object into
5741 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5742 or certain SUBREGS). If possible, convert it into a series of
5745 We half-heartedly support variable positions, but do not at all
5746 support variable lengths. */
5749 expand_field_assignment (x)
5753 rtx pos; /* Always counts from low bit. */
5756 enum machine_mode compute_mode;
5758 /* Loop until we find something we can't simplify. */
5761 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5762 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5764 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5765 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5766 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5768 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5769 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5771 inner = XEXP (SET_DEST (x), 0);
5772 len = INTVAL (XEXP (SET_DEST (x), 1));
5773 pos = XEXP (SET_DEST (x), 2);
5775 /* If the position is constant and spans the width of INNER,
5776 surround INNER with a USE to indicate this. */
5777 if (GET_CODE (pos) == CONST_INT
5778 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5779 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5781 if (BITS_BIG_ENDIAN)
5783 if (GET_CODE (pos) == CONST_INT)
5784 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5786 else if (GET_CODE (pos) == MINUS
5787 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5788 && (INTVAL (XEXP (pos, 1))
5789 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5790 /* If position is ADJUST - X, new position is X. */
5791 pos = XEXP (pos, 0);
5793 pos = gen_binary (MINUS, GET_MODE (pos),
5794 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5800 /* A SUBREG between two modes that occupy the same numbers of words
5801 can be done by moving the SUBREG to the source. */
5802 else if (GET_CODE (SET_DEST (x)) == SUBREG
5803 /* We need SUBREGs to compute nonzero_bits properly. */
5804 && nonzero_sign_valid
5805 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5806 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5807 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5808 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5810 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5811 gen_lowpart_for_combine
5812 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5819 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5820 inner = SUBREG_REG (inner);
5822 compute_mode = GET_MODE (inner);
5824 /* Don't attempt bitwise arithmetic on non-integral modes. */
5825 if (! INTEGRAL_MODE_P (compute_mode))
5827 enum machine_mode imode;
5829 /* Something is probably seriously wrong if this matches. */
5830 if (! FLOAT_MODE_P (compute_mode))
5833 /* Try to find an integral mode to pun with. */
5834 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5835 if (imode == BLKmode)
5838 compute_mode = imode;
5839 inner = gen_lowpart_for_combine (imode, inner);
5842 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5843 if (len < HOST_BITS_PER_WIDE_INT)
5844 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5848 /* Now compute the equivalent expression. Make a copy of INNER
5849 for the SET_DEST in case it is a MEM into which we will substitute;
5850 we don't want shared RTL in that case. */
5852 (VOIDmode, copy_rtx (inner),
5853 gen_binary (IOR, compute_mode,
5854 gen_binary (AND, compute_mode,
5855 simplify_gen_unary (NOT, compute_mode,
5861 gen_binary (ASHIFT, compute_mode,
5862 gen_binary (AND, compute_mode,
5863 gen_lowpart_for_combine
5864 (compute_mode, SET_SRC (x)),
5872 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5873 it is an RTX that represents a variable starting position; otherwise,
5874 POS is the (constant) starting bit position (counted from the LSB).
5876 INNER may be a USE. This will occur when we started with a bitfield
5877 that went outside the boundary of the object in memory, which is
5878 allowed on most machines. To isolate this case, we produce a USE
5879 whose mode is wide enough and surround the MEM with it. The only
5880 code that understands the USE is this routine. If it is not removed,
5881 it will cause the resulting insn not to match.
5883 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5886 IN_DEST is non-zero if this is a reference in the destination of a
5887 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5888 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5891 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5892 ZERO_EXTRACT should be built even for bits starting at bit 0.
5894 MODE is the desired mode of the result (if IN_DEST == 0).
5896 The result is an RTX for the extraction or NULL_RTX if the target
5900 make_extraction (mode, inner, pos, pos_rtx, len,
5901 unsignedp, in_dest, in_compare)
5902 enum machine_mode mode;
5906 unsigned HOST_WIDE_INT len;
5908 int in_dest, in_compare;
5910 /* This mode describes the size of the storage area
5911 to fetch the overall value from. Within that, we
5912 ignore the POS lowest bits, etc. */
5913 enum machine_mode is_mode = GET_MODE (inner);
5914 enum machine_mode inner_mode;
5915 enum machine_mode wanted_inner_mode = byte_mode;
5916 enum machine_mode wanted_inner_reg_mode = word_mode;
5917 enum machine_mode pos_mode = word_mode;
5918 enum machine_mode extraction_mode = word_mode;
5919 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5922 rtx orig_pos_rtx = pos_rtx;
5923 HOST_WIDE_INT orig_pos;
5925 /* Get some information about INNER and get the innermost object. */
5926 if (GET_CODE (inner) == USE)
5927 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5928 /* We don't need to adjust the position because we set up the USE
5929 to pretend that it was a full-word object. */
5930 spans_byte = 1, inner = XEXP (inner, 0);
5931 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5933 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5934 consider just the QI as the memory to extract from.
5935 The subreg adds or removes high bits; its mode is
5936 irrelevant to the meaning of this extraction,
5937 since POS and LEN count from the lsb. */
5938 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5939 is_mode = GET_MODE (SUBREG_REG (inner));
5940 inner = SUBREG_REG (inner);
5943 inner_mode = GET_MODE (inner);
5945 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5946 pos = INTVAL (pos_rtx), pos_rtx = 0;
5948 /* See if this can be done without an extraction. We never can if the
5949 width of the field is not the same as that of some integer mode. For
5950 registers, we can only avoid the extraction if the position is at the
5951 low-order bit and this is either not in the destination or we have the
5952 appropriate STRICT_LOW_PART operation available.
5954 For MEM, we can avoid an extract if the field starts on an appropriate
5955 boundary and we can change the mode of the memory reference. However,
5956 we cannot directly access the MEM if we have a USE and the underlying
5957 MEM is not TMODE. This combination means that MEM was being used in a
5958 context where bits outside its mode were being referenced; that is only
5959 valid in bit-field insns. */
5961 if (tmode != BLKmode
5962 && ! (spans_byte && inner_mode != tmode)
5963 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5964 && GET_CODE (inner) != MEM
5966 || (GET_CODE (inner) == REG
5967 && have_insn_for (STRICT_LOW_PART, tmode))))
5968 || (GET_CODE (inner) == MEM && pos_rtx == 0
5970 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5971 : BITS_PER_UNIT)) == 0
5972 /* We can't do this if we are widening INNER_MODE (it
5973 may not be aligned, for one thing). */
5974 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5975 && (inner_mode == tmode
5976 || (! mode_dependent_address_p (XEXP (inner, 0))
5977 && ! MEM_VOLATILE_P (inner))))))
5979 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5980 field. If the original and current mode are the same, we need not
5981 adjust the offset. Otherwise, we do if bytes big endian.
5983 If INNER is not a MEM, get a piece consisting of just the field
5984 of interest (in this case POS % BITS_PER_WORD must be 0). */
5986 if (GET_CODE (inner) == MEM)
5988 HOST_WIDE_INT offset;
5990 /* POS counts from lsb, but make OFFSET count in memory order. */
5991 if (BYTES_BIG_ENDIAN)
5992 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5994 offset = pos / BITS_PER_UNIT;
5996 new = adjust_address_nv (inner, tmode, offset);
5998 else if (GET_CODE (inner) == REG)
6000 /* We can't call gen_lowpart_for_combine here since we always want
6001 a SUBREG and it would sometimes return a new hard register. */
6002 if (tmode != inner_mode)
6004 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6006 if (WORDS_BIG_ENDIAN
6007 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6008 final_word = ((GET_MODE_SIZE (inner_mode)
6009 - GET_MODE_SIZE (tmode))
6010 / UNITS_PER_WORD) - final_word;
6012 final_word *= UNITS_PER_WORD;
6013 if (BYTES_BIG_ENDIAN &&
6014 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6015 final_word += (GET_MODE_SIZE (inner_mode)
6016 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6018 new = gen_rtx_SUBREG (tmode, inner, final_word);
6024 new = force_to_mode (inner, tmode,
6025 len >= HOST_BITS_PER_WIDE_INT
6026 ? ~(unsigned HOST_WIDE_INT) 0
6027 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6030 /* If this extraction is going into the destination of a SET,
6031 make a STRICT_LOW_PART unless we made a MEM. */
6034 return (GET_CODE (new) == MEM ? new
6035 : (GET_CODE (new) != SUBREG
6036 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6037 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6042 if (GET_CODE (new) == CONST_INT)
6043 return GEN_INT (trunc_int_for_mode (INTVAL (new), mode));
6045 /* If we know that no extraneous bits are set, and that the high
6046 bit is not set, convert the extraction to the cheaper of
6047 sign and zero extension, that are equivalent in these cases. */
6048 if (flag_expensive_optimizations
6049 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6050 && ((nonzero_bits (new, tmode)
6051 & ~(((unsigned HOST_WIDE_INT)
6052 GET_MODE_MASK (tmode))
6056 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6057 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6059 /* Prefer ZERO_EXTENSION, since it gives more information to
6061 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6066 /* Otherwise, sign- or zero-extend unless we already are in the
6069 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6073 /* Unless this is a COMPARE or we have a funny memory reference,
6074 don't do anything with zero-extending field extracts starting at
6075 the low-order bit since they are simple AND operations. */
6076 if (pos_rtx == 0 && pos == 0 && ! in_dest
6077 && ! in_compare && ! spans_byte && unsignedp)
6080 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6081 we would be spanning bytes or if the position is not a constant and the
6082 length is not 1. In all other cases, we would only be going outside
6083 our object in cases when an original shift would have been
6085 if (! spans_byte && GET_CODE (inner) == MEM
6086 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6087 || (pos_rtx != 0 && len != 1)))
6090 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6091 and the mode for the result. */
6092 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6094 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6095 pos_mode = mode_for_extraction (EP_insv, 2);
6096 extraction_mode = mode_for_extraction (EP_insv, 3);
6099 if (! in_dest && unsignedp
6100 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6102 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6103 pos_mode = mode_for_extraction (EP_extzv, 3);
6104 extraction_mode = mode_for_extraction (EP_extzv, 0);
6107 if (! in_dest && ! unsignedp
6108 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6110 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6111 pos_mode = mode_for_extraction (EP_extv, 3);
6112 extraction_mode = mode_for_extraction (EP_extv, 0);
6115 /* Never narrow an object, since that might not be safe. */
6117 if (mode != VOIDmode
6118 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6119 extraction_mode = mode;
6121 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6122 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6123 pos_mode = GET_MODE (pos_rtx);
6125 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6126 if we have to change the mode of memory and cannot, the desired mode is
6128 if (GET_CODE (inner) != MEM)
6129 wanted_inner_mode = wanted_inner_reg_mode;
6130 else if (inner_mode != wanted_inner_mode
6131 && (mode_dependent_address_p (XEXP (inner, 0))
6132 || MEM_VOLATILE_P (inner)))
6133 wanted_inner_mode = extraction_mode;
6137 if (BITS_BIG_ENDIAN)
6139 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6140 BITS_BIG_ENDIAN style. If position is constant, compute new
6141 position. Otherwise, build subtraction.
6142 Note that POS is relative to the mode of the original argument.
6143 If it's a MEM we need to recompute POS relative to that.
6144 However, if we're extracting from (or inserting into) a register,
6145 we want to recompute POS relative to wanted_inner_mode. */
6146 int width = (GET_CODE (inner) == MEM
6147 ? GET_MODE_BITSIZE (is_mode)
6148 : GET_MODE_BITSIZE (wanted_inner_mode));
6151 pos = width - len - pos;
6154 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6155 /* POS may be less than 0 now, but we check for that below.
6156 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6159 /* If INNER has a wider mode, make it smaller. If this is a constant
6160 extract, try to adjust the byte to point to the byte containing
6162 if (wanted_inner_mode != VOIDmode
6163 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6164 && ((GET_CODE (inner) == MEM
6165 && (inner_mode == wanted_inner_mode
6166 || (! mode_dependent_address_p (XEXP (inner, 0))
6167 && ! MEM_VOLATILE_P (inner))))))
6171 /* The computations below will be correct if the machine is big
6172 endian in both bits and bytes or little endian in bits and bytes.
6173 If it is mixed, we must adjust. */
6175 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6176 adjust OFFSET to compensate. */
6177 if (BYTES_BIG_ENDIAN
6179 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6180 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6182 /* If this is a constant position, we can move to the desired byte. */
6185 offset += pos / BITS_PER_UNIT;
6186 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6189 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6191 && is_mode != wanted_inner_mode)
6192 offset = (GET_MODE_SIZE (is_mode)
6193 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6195 if (offset != 0 || inner_mode != wanted_inner_mode)
6196 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6199 /* If INNER is not memory, we can always get it into the proper mode. If we
6200 are changing its mode, POS must be a constant and smaller than the size
6202 else if (GET_CODE (inner) != MEM)
6204 if (GET_MODE (inner) != wanted_inner_mode
6206 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6209 inner = force_to_mode (inner, wanted_inner_mode,
6211 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6212 ? ~(unsigned HOST_WIDE_INT) 0
6213 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6218 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6219 have to zero extend. Otherwise, we can just use a SUBREG. */
6221 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6223 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6225 /* If we know that no extraneous bits are set, and that the high
6226 bit is not set, convert extraction to cheaper one - either
6227 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6229 if (flag_expensive_optimizations
6230 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6231 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6232 & ~(((unsigned HOST_WIDE_INT)
6233 GET_MODE_MASK (GET_MODE (pos_rtx)))
6237 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6239 /* Prefer ZERO_EXTENSION, since it gives more information to
6241 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6246 else if (pos_rtx != 0
6247 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6248 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6250 /* Make POS_RTX unless we already have it and it is correct. If we don't
6251 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6253 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6254 pos_rtx = orig_pos_rtx;
6256 else if (pos_rtx == 0)
6257 pos_rtx = GEN_INT (pos);
6259 /* Make the required operation. See if we can use existing rtx. */
6260 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6261 extraction_mode, inner, GEN_INT (len), pos_rtx);
6263 new = gen_lowpart_for_combine (mode, new);
6268 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6269 with any other operations in X. Return X without that shift if so. */
6272 extract_left_shift (x, count)
6276 enum rtx_code code = GET_CODE (x);
6277 enum machine_mode mode = GET_MODE (x);
6283 /* This is the shift itself. If it is wide enough, we will return
6284 either the value being shifted if the shift count is equal to
6285 COUNT or a shift for the difference. */
6286 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6287 && INTVAL (XEXP (x, 1)) >= count)
6288 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6289 INTVAL (XEXP (x, 1)) - count);
6293 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6294 return simplify_gen_unary (code, mode, tem, mode);
6298 case PLUS: case IOR: case XOR: case AND:
6299 /* If we can safely shift this constant and we find the inner shift,
6300 make a new operation. */
6301 if (GET_CODE (XEXP (x,1)) == CONST_INT
6302 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6303 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6304 return gen_binary (code, mode, tem,
6305 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6316 /* Look at the expression rooted at X. Look for expressions
6317 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6318 Form these expressions.
6320 Return the new rtx, usually just X.
6322 Also, for machines like the VAX that don't have logical shift insns,
6323 try to convert logical to arithmetic shift operations in cases where
6324 they are equivalent. This undoes the canonicalizations to logical
6325 shifts done elsewhere.
6327 We try, as much as possible, to re-use rtl expressions to save memory.
6329 IN_CODE says what kind of expression we are processing. Normally, it is
6330 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6331 being kludges), it is MEM. When processing the arguments of a comparison
6332 or a COMPARE against zero, it is COMPARE. */
6335 make_compound_operation (x, in_code)
6337 enum rtx_code in_code;
6339 enum rtx_code code = GET_CODE (x);
6340 enum machine_mode mode = GET_MODE (x);
6341 int mode_width = GET_MODE_BITSIZE (mode);
6343 enum rtx_code next_code;
6349 /* Select the code to be used in recursive calls. Once we are inside an
6350 address, we stay there. If we have a comparison, set to COMPARE,
6351 but once inside, go back to our default of SET. */
6353 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6354 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6355 && XEXP (x, 1) == const0_rtx) ? COMPARE
6356 : in_code == COMPARE ? SET : in_code);
6358 /* Process depending on the code of this operation. If NEW is set
6359 non-zero, it will be returned. */
6364 /* Convert shifts by constants into multiplications if inside
6366 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6367 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6368 && INTVAL (XEXP (x, 1)) >= 0)
6370 new = make_compound_operation (XEXP (x, 0), next_code);
6371 new = gen_rtx_MULT (mode, new,
6372 GEN_INT ((HOST_WIDE_INT) 1
6373 << INTVAL (XEXP (x, 1))));
6378 /* If the second operand is not a constant, we can't do anything
6380 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6383 /* If the constant is a power of two minus one and the first operand
6384 is a logical right shift, make an extraction. */
6385 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6386 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6388 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6389 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6390 0, in_code == COMPARE);
6393 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6394 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6395 && subreg_lowpart_p (XEXP (x, 0))
6396 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6397 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6399 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6401 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6402 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6403 0, in_code == COMPARE);
6405 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6406 else if ((GET_CODE (XEXP (x, 0)) == XOR
6407 || GET_CODE (XEXP (x, 0)) == IOR)
6408 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6409 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6410 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6412 /* Apply the distributive law, and then try to make extractions. */
6413 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6414 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6416 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6418 new = make_compound_operation (new, in_code);
6421 /* If we are have (and (rotate X C) M) and C is larger than the number
6422 of bits in M, this is an extraction. */
6424 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6425 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6426 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6427 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6429 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6430 new = make_extraction (mode, new,
6431 (GET_MODE_BITSIZE (mode)
6432 - INTVAL (XEXP (XEXP (x, 0), 1))),
6433 NULL_RTX, i, 1, 0, in_code == COMPARE);
6436 /* On machines without logical shifts, if the operand of the AND is
6437 a logical shift and our mask turns off all the propagated sign
6438 bits, we can replace the logical shift with an arithmetic shift. */
6439 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6440 && !have_insn_for (LSHIFTRT, mode)
6441 && have_insn_for (ASHIFTRT, mode)
6442 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6443 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6444 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6445 && mode_width <= HOST_BITS_PER_WIDE_INT)
6447 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6449 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6450 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6452 gen_rtx_ASHIFTRT (mode,
6453 make_compound_operation
6454 (XEXP (XEXP (x, 0), 0), next_code),
6455 XEXP (XEXP (x, 0), 1)));
6458 /* If the constant is one less than a power of two, this might be
6459 representable by an extraction even if no shift is present.
6460 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6461 we are in a COMPARE. */
6462 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6463 new = make_extraction (mode,
6464 make_compound_operation (XEXP (x, 0),
6466 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6468 /* If we are in a comparison and this is an AND with a power of two,
6469 convert this into the appropriate bit extract. */
6470 else if (in_code == COMPARE
6471 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6472 new = make_extraction (mode,
6473 make_compound_operation (XEXP (x, 0),
6475 i, NULL_RTX, 1, 1, 0, 1);
6480 /* If the sign bit is known to be zero, replace this with an
6481 arithmetic shift. */
6482 if (have_insn_for (ASHIFTRT, mode)
6483 && ! have_insn_for (LSHIFTRT, mode)
6484 && mode_width <= HOST_BITS_PER_WIDE_INT
6485 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6487 new = gen_rtx_ASHIFTRT (mode,
6488 make_compound_operation (XEXP (x, 0),
6494 /* ... fall through ... */
6500 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6501 this is a SIGN_EXTRACT. */
6502 if (GET_CODE (rhs) == CONST_INT
6503 && GET_CODE (lhs) == ASHIFT
6504 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6505 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6507 new = make_compound_operation (XEXP (lhs, 0), next_code);
6508 new = make_extraction (mode, new,
6509 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6510 NULL_RTX, mode_width - INTVAL (rhs),
6511 code == LSHIFTRT, 0, in_code == COMPARE);
6515 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6516 If so, try to merge the shifts into a SIGN_EXTEND. We could
6517 also do this for some cases of SIGN_EXTRACT, but it doesn't
6518 seem worth the effort; the case checked for occurs on Alpha. */
6520 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6521 && ! (GET_CODE (lhs) == SUBREG
6522 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6523 && GET_CODE (rhs) == CONST_INT
6524 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6525 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6526 new = make_extraction (mode, make_compound_operation (new, next_code),
6527 0, NULL_RTX, mode_width - INTVAL (rhs),
6528 code == LSHIFTRT, 0, in_code == COMPARE);
6533 /* Call ourselves recursively on the inner expression. If we are
6534 narrowing the object and it has a different RTL code from
6535 what it originally did, do this SUBREG as a force_to_mode. */
6537 tem = make_compound_operation (SUBREG_REG (x), in_code);
6538 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6539 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6540 && subreg_lowpart_p (x))
6542 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6545 /* If we have something other than a SUBREG, we might have
6546 done an expansion, so rerun ourselves. */
6547 if (GET_CODE (newer) != SUBREG)
6548 newer = make_compound_operation (newer, in_code);
6553 /* If this is a paradoxical subreg, and the new code is a sign or
6554 zero extension, omit the subreg and widen the extension. If it
6555 is a regular subreg, we can still get rid of the subreg by not
6556 widening so much, or in fact removing the extension entirely. */
6557 if ((GET_CODE (tem) == SIGN_EXTEND
6558 || GET_CODE (tem) == ZERO_EXTEND)
6559 && subreg_lowpart_p (x))
6561 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6562 || (GET_MODE_SIZE (mode) >
6563 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6564 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6566 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6577 x = gen_lowpart_for_combine (mode, new);
6578 code = GET_CODE (x);
6581 /* Now recursively process each operand of this operation. */
6582 fmt = GET_RTX_FORMAT (code);
6583 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6586 new = make_compound_operation (XEXP (x, i), next_code);
6587 SUBST (XEXP (x, i), new);
6593 /* Given M see if it is a value that would select a field of bits
6594 within an item, but not the entire word. Return -1 if not.
6595 Otherwise, return the starting position of the field, where 0 is the
6598 *PLEN is set to the length of the field. */
6601 get_pos_from_mask (m, plen)
6602 unsigned HOST_WIDE_INT m;
6603 unsigned HOST_WIDE_INT *plen;
6605 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6606 int pos = exact_log2 (m & -m);
6612 /* Now shift off the low-order zero bits and see if we have a power of
6614 len = exact_log2 ((m >> pos) + 1);
6623 /* See if X can be simplified knowing that we will only refer to it in
6624 MODE and will only refer to those bits that are nonzero in MASK.
6625 If other bits are being computed or if masking operations are done
6626 that select a superset of the bits in MASK, they can sometimes be
6629 Return a possibly simplified expression, but always convert X to
6630 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6632 Also, if REG is non-zero and X is a register equal in value to REG,
6635 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6636 are all off in X. This is used when X will be complemented, by either
6637 NOT, NEG, or XOR. */
6640 force_to_mode (x, mode, mask, reg, just_select)
6642 enum machine_mode mode;
6643 unsigned HOST_WIDE_INT mask;
6647 enum rtx_code code = GET_CODE (x);
6648 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6649 enum machine_mode op_mode;
6650 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6653 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6654 code below will do the wrong thing since the mode of such an
6655 expression is VOIDmode.
6657 Also do nothing if X is a CLOBBER; this can happen if X was
6658 the return value from a call to gen_lowpart_for_combine. */
6659 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6662 /* We want to perform the operation is its present mode unless we know
6663 that the operation is valid in MODE, in which case we do the operation
6665 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6666 && have_insn_for (code, mode))
6667 ? mode : GET_MODE (x));
6669 /* It is not valid to do a right-shift in a narrower mode
6670 than the one it came in with. */
6671 if ((code == LSHIFTRT || code == ASHIFTRT)
6672 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6673 op_mode = GET_MODE (x);
6675 /* Truncate MASK to fit OP_MODE. */
6677 mask &= GET_MODE_MASK (op_mode);
6679 /* When we have an arithmetic operation, or a shift whose count we
6680 do not know, we need to assume that all bit the up to the highest-order
6681 bit in MASK will be needed. This is how we form such a mask. */
6683 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6684 ? GET_MODE_MASK (op_mode)
6685 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6688 fuller_mask = ~(HOST_WIDE_INT) 0;
6690 /* Determine what bits of X are guaranteed to be (non)zero. */
6691 nonzero = nonzero_bits (x, mode);
6693 /* If none of the bits in X are needed, return a zero. */
6694 if (! just_select && (nonzero & mask) == 0)
6697 /* If X is a CONST_INT, return a new one. Do this here since the
6698 test below will fail. */
6699 if (GET_CODE (x) == CONST_INT)
6701 HOST_WIDE_INT cval = INTVAL (x) & mask;
6702 int width = GET_MODE_BITSIZE (mode);
6704 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6705 number, sign extend it. */
6706 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6707 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6708 cval |= (HOST_WIDE_INT) -1 << width;
6710 return GEN_INT (cval);
6713 /* If X is narrower than MODE and we want all the bits in X's mode, just
6714 get X in the proper mode. */
6715 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6716 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6717 return gen_lowpart_for_combine (mode, x);
6719 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6720 MASK are already known to be zero in X, we need not do anything. */
6721 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6727 /* If X is a (clobber (const_int)), return it since we know we are
6728 generating something that won't match. */
6732 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6733 spanned the boundary of the MEM. If we are now masking so it is
6734 within that boundary, we don't need the USE any more. */
6735 if (! BITS_BIG_ENDIAN
6736 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6737 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6744 x = expand_compound_operation (x);
6745 if (GET_CODE (x) != code)
6746 return force_to_mode (x, mode, mask, reg, next_select);
6750 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6751 || rtx_equal_p (reg, get_last_value (x))))
6756 if (subreg_lowpart_p (x)
6757 /* We can ignore the effect of this SUBREG if it narrows the mode or
6758 if the constant masks to zero all the bits the mode doesn't
6760 && ((GET_MODE_SIZE (GET_MODE (x))
6761 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6763 & GET_MODE_MASK (GET_MODE (x))
6764 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6765 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6769 /* If this is an AND with a constant, convert it into an AND
6770 whose constant is the AND of that constant with MASK. If it
6771 remains an AND of MASK, delete it since it is redundant. */
6773 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6775 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6776 mask & INTVAL (XEXP (x, 1)));
6778 /* If X is still an AND, see if it is an AND with a mask that
6779 is just some low-order bits. If so, and it is MASK, we don't
6782 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6783 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6784 == (HOST_WIDE_INT) mask))
6787 /* If it remains an AND, try making another AND with the bits
6788 in the mode mask that aren't in MASK turned on. If the
6789 constant in the AND is wide enough, this might make a
6790 cheaper constant. */
6792 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6793 && GET_MODE_MASK (GET_MODE (x)) != mask
6794 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6796 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6797 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6798 int width = GET_MODE_BITSIZE (GET_MODE (x));
6801 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6802 number, sign extend it. */
6803 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6804 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6805 cval |= (HOST_WIDE_INT) -1 << width;
6807 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6808 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6818 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6819 low-order bits (as in an alignment operation) and FOO is already
6820 aligned to that boundary, mask C1 to that boundary as well.
6821 This may eliminate that PLUS and, later, the AND. */
6824 unsigned int width = GET_MODE_BITSIZE (mode);
6825 unsigned HOST_WIDE_INT smask = mask;
6827 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6828 number, sign extend it. */
6830 if (width < HOST_BITS_PER_WIDE_INT
6831 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6832 smask |= (HOST_WIDE_INT) -1 << width;
6834 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6835 && exact_log2 (- smask) >= 0
6836 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6837 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6838 return force_to_mode (plus_constant (XEXP (x, 0),
6839 (INTVAL (XEXP (x, 1)) & smask)),
6840 mode, smask, reg, next_select);
6843 /* ... fall through ... */
6846 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6847 most significant bit in MASK since carries from those bits will
6848 affect the bits we are interested in. */
6853 /* If X is (minus C Y) where C's least set bit is larger than any bit
6854 in the mask, then we may replace with (neg Y). */
6855 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6856 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6857 & -INTVAL (XEXP (x, 0))))
6860 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6862 return force_to_mode (x, mode, mask, reg, next_select);
6865 /* Similarly, if C contains every bit in the mask, then we may
6866 replace with (not Y). */
6867 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6868 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6869 == INTVAL (XEXP (x, 0))))
6871 x = simplify_gen_unary (NOT, GET_MODE (x),
6872 XEXP (x, 1), GET_MODE (x));
6873 return force_to_mode (x, mode, mask, reg, next_select);
6881 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6882 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6883 operation which may be a bitfield extraction. Ensure that the
6884 constant we form is not wider than the mode of X. */
6886 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6887 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6888 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6889 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6890 && GET_CODE (XEXP (x, 1)) == CONST_INT
6891 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6892 + floor_log2 (INTVAL (XEXP (x, 1))))
6893 < GET_MODE_BITSIZE (GET_MODE (x)))
6894 && (INTVAL (XEXP (x, 1))
6895 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6897 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6898 << INTVAL (XEXP (XEXP (x, 0), 1)));
6899 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6900 XEXP (XEXP (x, 0), 0), temp);
6901 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6902 XEXP (XEXP (x, 0), 1));
6903 return force_to_mode (x, mode, mask, reg, next_select);
6907 /* For most binary operations, just propagate into the operation and
6908 change the mode if we have an operation of that mode. */
6910 op0 = gen_lowpart_for_combine (op_mode,
6911 force_to_mode (XEXP (x, 0), mode, mask,
6913 op1 = gen_lowpart_for_combine (op_mode,
6914 force_to_mode (XEXP (x, 1), mode, mask,
6917 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6918 MASK since OP1 might have been sign-extended but we never want
6919 to turn on extra bits, since combine might have previously relied
6920 on them being off. */
6921 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6922 && (INTVAL (op1) & mask) != 0)
6923 op1 = GEN_INT (INTVAL (op1) & mask);
6925 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6926 x = gen_binary (code, op_mode, op0, op1);
6930 /* For left shifts, do the same, but just for the first operand.
6931 However, we cannot do anything with shifts where we cannot
6932 guarantee that the counts are smaller than the size of the mode
6933 because such a count will have a different meaning in a
6936 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6937 && INTVAL (XEXP (x, 1)) >= 0
6938 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6939 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6940 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6941 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6944 /* If the shift count is a constant and we can do arithmetic in
6945 the mode of the shift, refine which bits we need. Otherwise, use the
6946 conservative form of the mask. */
6947 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6948 && INTVAL (XEXP (x, 1)) >= 0
6949 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6950 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6951 mask >>= INTVAL (XEXP (x, 1));
6955 op0 = gen_lowpart_for_combine (op_mode,
6956 force_to_mode (XEXP (x, 0), op_mode,
6957 mask, reg, next_select));
6959 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6960 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6964 /* Here we can only do something if the shift count is a constant,
6965 this shift constant is valid for the host, and we can do arithmetic
6968 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6969 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6970 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6972 rtx inner = XEXP (x, 0);
6973 unsigned HOST_WIDE_INT inner_mask;
6975 /* Select the mask of the bits we need for the shift operand. */
6976 inner_mask = mask << INTVAL (XEXP (x, 1));
6978 /* We can only change the mode of the shift if we can do arithmetic
6979 in the mode of the shift and INNER_MASK is no wider than the
6980 width of OP_MODE. */
6981 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6982 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6983 op_mode = GET_MODE (x);
6985 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6987 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6988 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6991 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6992 shift and AND produces only copies of the sign bit (C2 is one less
6993 than a power of two), we can do this with just a shift. */
6995 if (GET_CODE (x) == LSHIFTRT
6996 && GET_CODE (XEXP (x, 1)) == CONST_INT
6997 /* The shift puts one of the sign bit copies in the least significant
6999 && ((INTVAL (XEXP (x, 1))
7000 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7001 >= GET_MODE_BITSIZE (GET_MODE (x)))
7002 && exact_log2 (mask + 1) >= 0
7003 /* Number of bits left after the shift must be more than the mask
7005 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7006 <= GET_MODE_BITSIZE (GET_MODE (x)))
7007 /* Must be more sign bit copies than the mask needs. */
7008 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7009 >= exact_log2 (mask + 1)))
7010 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7011 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7012 - exact_log2 (mask + 1)));
7017 /* If we are just looking for the sign bit, we don't need this shift at
7018 all, even if it has a variable count. */
7019 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7020 && (mask == ((unsigned HOST_WIDE_INT) 1
7021 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7022 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7024 /* If this is a shift by a constant, get a mask that contains those bits
7025 that are not copies of the sign bit. We then have two cases: If
7026 MASK only includes those bits, this can be a logical shift, which may
7027 allow simplifications. If MASK is a single-bit field not within
7028 those bits, we are requesting a copy of the sign bit and hence can
7029 shift the sign bit to the appropriate location. */
7031 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7032 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7036 /* If the considered data is wider than HOST_WIDE_INT, we can't
7037 represent a mask for all its bits in a single scalar.
7038 But we only care about the lower bits, so calculate these. */
7040 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7042 nonzero = ~(HOST_WIDE_INT) 0;
7044 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7045 is the number of bits a full-width mask would have set.
7046 We need only shift if these are fewer than nonzero can
7047 hold. If not, we must keep all bits set in nonzero. */
7049 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7050 < HOST_BITS_PER_WIDE_INT)
7051 nonzero >>= INTVAL (XEXP (x, 1))
7052 + HOST_BITS_PER_WIDE_INT
7053 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7057 nonzero = GET_MODE_MASK (GET_MODE (x));
7058 nonzero >>= INTVAL (XEXP (x, 1));
7061 if ((mask & ~nonzero) == 0
7062 || (i = exact_log2 (mask)) >= 0)
7064 x = simplify_shift_const
7065 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7066 i < 0 ? INTVAL (XEXP (x, 1))
7067 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7069 if (GET_CODE (x) != ASHIFTRT)
7070 return force_to_mode (x, mode, mask, reg, next_select);
7074 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7075 even if the shift count isn't a constant. */
7077 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7081 /* If this is a zero- or sign-extension operation that just affects bits
7082 we don't care about, remove it. Be sure the call above returned
7083 something that is still a shift. */
7085 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7086 && GET_CODE (XEXP (x, 1)) == CONST_INT
7087 && INTVAL (XEXP (x, 1)) >= 0
7088 && (INTVAL (XEXP (x, 1))
7089 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7090 && GET_CODE (XEXP (x, 0)) == ASHIFT
7091 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7092 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7093 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7100 /* If the shift count is constant and we can do computations
7101 in the mode of X, compute where the bits we care about are.
7102 Otherwise, we can't do anything. Don't change the mode of
7103 the shift or propagate MODE into the shift, though. */
7104 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7105 && INTVAL (XEXP (x, 1)) >= 0)
7107 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7108 GET_MODE (x), GEN_INT (mask),
7110 if (temp && GET_CODE(temp) == CONST_INT)
7112 force_to_mode (XEXP (x, 0), GET_MODE (x),
7113 INTVAL (temp), reg, next_select));
7118 /* If we just want the low-order bit, the NEG isn't needed since it
7119 won't change the low-order bit. */
7121 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7123 /* We need any bits less significant than the most significant bit in
7124 MASK since carries from those bits will affect the bits we are
7130 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7131 same as the XOR case above. Ensure that the constant we form is not
7132 wider than the mode of X. */
7134 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7135 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7136 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7137 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7138 < GET_MODE_BITSIZE (GET_MODE (x)))
7139 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7141 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7142 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7143 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7145 return force_to_mode (x, mode, mask, reg, next_select);
7148 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7149 use the full mask inside the NOT. */
7153 op0 = gen_lowpart_for_combine (op_mode,
7154 force_to_mode (XEXP (x, 0), mode, mask,
7156 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7157 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7161 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7162 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7163 which is equal to STORE_FLAG_VALUE. */
7164 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7165 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7166 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7167 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7172 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7173 written in a narrower mode. We play it safe and do not do so. */
7176 gen_lowpart_for_combine (GET_MODE (x),
7177 force_to_mode (XEXP (x, 1), mode,
7178 mask, reg, next_select)));
7180 gen_lowpart_for_combine (GET_MODE (x),
7181 force_to_mode (XEXP (x, 2), mode,
7182 mask, reg,next_select)));
7189 /* Ensure we return a value of the proper mode. */
7190 return gen_lowpart_for_combine (mode, x);
7193 /* Return nonzero if X is an expression that has one of two values depending on
7194 whether some other value is zero or nonzero. In that case, we return the
7195 value that is being tested, *PTRUE is set to the value if the rtx being
7196 returned has a nonzero value, and *PFALSE is set to the other alternative.
7198 If we return zero, we set *PTRUE and *PFALSE to X. */
7201 if_then_else_cond (x, ptrue, pfalse)
7203 rtx *ptrue, *pfalse;
7205 enum machine_mode mode = GET_MODE (x);
7206 enum rtx_code code = GET_CODE (x);
7207 rtx cond0, cond1, true0, true1, false0, false1;
7208 unsigned HOST_WIDE_INT nz;
7210 /* If we are comparing a value against zero, we are done. */
7211 if ((code == NE || code == EQ)
7212 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7214 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7215 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7219 /* If this is a unary operation whose operand has one of two values, apply
7220 our opcode to compute those values. */
7221 else if (GET_RTX_CLASS (code) == '1'
7222 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7224 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7225 *pfalse = simplify_gen_unary (code, mode, false0,
7226 GET_MODE (XEXP (x, 0)));
7230 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7231 make can't possibly match and would suppress other optimizations. */
7232 else if (code == COMPARE)
7235 /* If this is a binary operation, see if either side has only one of two
7236 values. If either one does or if both do and they are conditional on
7237 the same value, compute the new true and false values. */
7238 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7239 || GET_RTX_CLASS (code) == '<')
7241 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7242 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7244 if ((cond0 != 0 || cond1 != 0)
7245 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7247 /* If if_then_else_cond returned zero, then true/false are the
7248 same rtl. We must copy one of them to prevent invalid rtl
7251 true0 = copy_rtx (true0);
7252 else if (cond1 == 0)
7253 true1 = copy_rtx (true1);
7255 *ptrue = gen_binary (code, mode, true0, true1);
7256 *pfalse = gen_binary (code, mode, false0, false1);
7257 return cond0 ? cond0 : cond1;
7260 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7261 operands is zero when the other is non-zero, and vice-versa,
7262 and STORE_FLAG_VALUE is 1 or -1. */
7264 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7265 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7267 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7269 rtx op0 = XEXP (XEXP (x, 0), 1);
7270 rtx op1 = XEXP (XEXP (x, 1), 1);
7272 cond0 = XEXP (XEXP (x, 0), 0);
7273 cond1 = XEXP (XEXP (x, 1), 0);
7275 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7276 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7277 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7278 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7279 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7280 || ((swap_condition (GET_CODE (cond0))
7281 == combine_reversed_comparison_code (cond1))
7282 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7283 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7284 && ! side_effects_p (x))
7286 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7287 *pfalse = gen_binary (MULT, mode,
7289 ? simplify_gen_unary (NEG, mode, op1,
7297 /* Similarly for MULT, AND and UMIN, except that for these the result
7299 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7300 && (code == MULT || code == AND || code == UMIN)
7301 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7303 cond0 = XEXP (XEXP (x, 0), 0);
7304 cond1 = XEXP (XEXP (x, 1), 0);
7306 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7307 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7308 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7309 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7310 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7311 || ((swap_condition (GET_CODE (cond0))
7312 == combine_reversed_comparison_code (cond1))
7313 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7314 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7315 && ! side_effects_p (x))
7317 *ptrue = *pfalse = const0_rtx;
7323 else if (code == IF_THEN_ELSE)
7325 /* If we have IF_THEN_ELSE already, extract the condition and
7326 canonicalize it if it is NE or EQ. */
7327 cond0 = XEXP (x, 0);
7328 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7329 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7330 return XEXP (cond0, 0);
7331 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7333 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7334 return XEXP (cond0, 0);
7340 /* If X is a SUBREG, we can narrow both the true and false values
7341 if the inner expression, if there is a condition. */
7342 else if (code == SUBREG
7343 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7346 *ptrue = simplify_gen_subreg (mode, true0,
7347 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7348 *pfalse = simplify_gen_subreg (mode, false0,
7349 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7354 /* If X is a constant, this isn't special and will cause confusions
7355 if we treat it as such. Likewise if it is equivalent to a constant. */
7356 else if (CONSTANT_P (x)
7357 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7360 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7361 will be least confusing to the rest of the compiler. */
7362 else if (mode == BImode)
7364 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7368 /* If X is known to be either 0 or -1, those are the true and
7369 false values when testing X. */
7370 else if (x == constm1_rtx || x == const0_rtx
7371 || (mode != VOIDmode
7372 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7374 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7378 /* Likewise for 0 or a single bit. */
7379 else if (mode != VOIDmode
7380 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7381 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7383 *ptrue = GEN_INT (trunc_int_for_mode (nz, mode)), *pfalse = const0_rtx;
7387 /* Otherwise fail; show no condition with true and false values the same. */
7388 *ptrue = *pfalse = x;
7392 /* Return the value of expression X given the fact that condition COND
7393 is known to be true when applied to REG as its first operand and VAL
7394 as its second. X is known to not be shared and so can be modified in
7397 We only handle the simplest cases, and specifically those cases that
7398 arise with IF_THEN_ELSE expressions. */
7401 known_cond (x, cond, reg, val)
7406 enum rtx_code code = GET_CODE (x);
7411 if (side_effects_p (x))
7414 /* If either operand of the condition is a floating point value,
7415 then we have to avoid collapsing an EQ comparison. */
7417 && rtx_equal_p (x, reg)
7418 && ! FLOAT_MODE_P (GET_MODE (x))
7419 && ! FLOAT_MODE_P (GET_MODE (val)))
7422 if (cond == UNEQ && rtx_equal_p (x, reg))
7425 /* If X is (abs REG) and we know something about REG's relationship
7426 with zero, we may be able to simplify this. */
7428 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7431 case GE: case GT: case EQ:
7434 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7436 GET_MODE (XEXP (x, 0)));
7441 /* The only other cases we handle are MIN, MAX, and comparisons if the
7442 operands are the same as REG and VAL. */
7444 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7446 if (rtx_equal_p (XEXP (x, 0), val))
7447 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7449 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7451 if (GET_RTX_CLASS (code) == '<')
7453 if (comparison_dominates_p (cond, code))
7454 return const_true_rtx;
7456 code = combine_reversed_comparison_code (x);
7458 && comparison_dominates_p (cond, code))
7463 else if (code == SMAX || code == SMIN
7464 || code == UMIN || code == UMAX)
7466 int unsignedp = (code == UMIN || code == UMAX);
7468 /* Do not reverse the condition when it is NE or EQ.
7469 This is because we cannot conclude anything about
7470 the value of 'SMAX (x, y)' when x is not equal to y,
7471 but we can when x equals y. */
7472 if ((code == SMAX || code == UMAX)
7473 && ! (cond == EQ || cond == NE))
7474 cond = reverse_condition (cond);
7479 return unsignedp ? x : XEXP (x, 1);
7481 return unsignedp ? x : XEXP (x, 0);
7483 return unsignedp ? XEXP (x, 1) : x;
7485 return unsignedp ? XEXP (x, 0) : x;
7492 else if (code == SUBREG)
7494 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7495 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7497 if (SUBREG_REG (x) != r)
7499 /* We must simplify subreg here, before we lose track of the
7500 original inner_mode. */
7501 new = simplify_subreg (GET_MODE (x), r,
7502 inner_mode, SUBREG_BYTE (x));
7506 SUBST (SUBREG_REG (x), r);
7511 /* We don't have to handle SIGN_EXTEND here, because even in the
7512 case of replacing something with a modeless CONST_INT, a
7513 CONST_INT is already (supposed to be) a valid sign extension for
7514 its narrower mode, which implies it's already properly
7515 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7516 story is different. */
7517 else if (code == ZERO_EXTEND)
7519 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7520 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7522 if (XEXP (x, 0) != r)
7524 /* We must simplify the zero_extend here, before we lose
7525 track of the original inner_mode. */
7526 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7531 SUBST (XEXP (x, 0), r);
7537 fmt = GET_RTX_FORMAT (code);
7538 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7541 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7542 else if (fmt[i] == 'E')
7543 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7544 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7551 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7552 assignment as a field assignment. */
7555 rtx_equal_for_field_assignment_p (x, y)
7559 if (x == y || rtx_equal_p (x, y))
7562 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7565 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7566 Note that all SUBREGs of MEM are paradoxical; otherwise they
7567 would have been rewritten. */
7568 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7569 && GET_CODE (SUBREG_REG (y)) == MEM
7570 && rtx_equal_p (SUBREG_REG (y),
7571 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7574 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7575 && GET_CODE (SUBREG_REG (x)) == MEM
7576 && rtx_equal_p (SUBREG_REG (x),
7577 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7580 /* We used to see if get_last_value of X and Y were the same but that's
7581 not correct. In one direction, we'll cause the assignment to have
7582 the wrong destination and in the case, we'll import a register into this
7583 insn that might have already have been dead. So fail if none of the
7584 above cases are true. */
7588 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7589 Return that assignment if so.
7591 We only handle the most common cases. */
7594 make_field_assignment (x)
7597 rtx dest = SET_DEST (x);
7598 rtx src = SET_SRC (x);
7603 unsigned HOST_WIDE_INT len;
7605 enum machine_mode mode;
7607 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7608 a clear of a one-bit field. We will have changed it to
7609 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7612 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7613 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7614 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7615 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7617 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7620 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7624 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7625 && subreg_lowpart_p (XEXP (src, 0))
7626 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7627 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7628 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7629 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7630 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7632 assign = make_extraction (VOIDmode, dest, 0,
7633 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7636 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7640 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7642 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7643 && XEXP (XEXP (src, 0), 0) == const1_rtx
7644 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7646 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7649 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7653 /* The other case we handle is assignments into a constant-position
7654 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7655 a mask that has all one bits except for a group of zero bits and
7656 OTHER is known to have zeros where C1 has ones, this is such an
7657 assignment. Compute the position and length from C1. Shift OTHER
7658 to the appropriate position, force it to the required mode, and
7659 make the extraction. Check for the AND in both operands. */
7661 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7664 rhs = expand_compound_operation (XEXP (src, 0));
7665 lhs = expand_compound_operation (XEXP (src, 1));
7667 if (GET_CODE (rhs) == AND
7668 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7669 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7670 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7671 else if (GET_CODE (lhs) == AND
7672 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7673 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7674 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7678 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7679 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7680 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7681 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7684 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7688 /* The mode to use for the source is the mode of the assignment, or of
7689 what is inside a possible STRICT_LOW_PART. */
7690 mode = (GET_CODE (assign) == STRICT_LOW_PART
7691 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7693 /* Shift OTHER right POS places and make it the source, restricting it
7694 to the proper length and mode. */
7696 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7697 GET_MODE (src), other, pos),
7699 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7700 ? ~(unsigned HOST_WIDE_INT) 0
7701 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7704 return gen_rtx_SET (VOIDmode, assign, src);
7707 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7711 apply_distributive_law (x)
7714 enum rtx_code code = GET_CODE (x);
7715 rtx lhs, rhs, other;
7717 enum rtx_code inner_code;
7719 /* Distributivity is not true for floating point.
7720 It can change the value. So don't do it.
7721 -- rms and moshier@world.std.com. */
7722 if (FLOAT_MODE_P (GET_MODE (x)))
7725 /* The outer operation can only be one of the following: */
7726 if (code != IOR && code != AND && code != XOR
7727 && code != PLUS && code != MINUS)
7730 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7732 /* If either operand is a primitive we can't do anything, so get out
7734 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7735 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7738 lhs = expand_compound_operation (lhs);
7739 rhs = expand_compound_operation (rhs);
7740 inner_code = GET_CODE (lhs);
7741 if (inner_code != GET_CODE (rhs))
7744 /* See if the inner and outer operations distribute. */
7751 /* These all distribute except over PLUS. */
7752 if (code == PLUS || code == MINUS)
7757 if (code != PLUS && code != MINUS)
7762 /* This is also a multiply, so it distributes over everything. */
7766 /* Non-paradoxical SUBREGs distributes over all operations, provided
7767 the inner modes and byte offsets are the same, this is an extraction
7768 of a low-order part, we don't convert an fp operation to int or
7769 vice versa, and we would not be converting a single-word
7770 operation into a multi-word operation. The latter test is not
7771 required, but it prevents generating unneeded multi-word operations.
7772 Some of the previous tests are redundant given the latter test, but
7773 are retained because they are required for correctness.
7775 We produce the result slightly differently in this case. */
7777 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7778 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7779 || ! subreg_lowpart_p (lhs)
7780 || (GET_MODE_CLASS (GET_MODE (lhs))
7781 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7782 || (GET_MODE_SIZE (GET_MODE (lhs))
7783 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7784 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7787 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7788 SUBREG_REG (lhs), SUBREG_REG (rhs));
7789 return gen_lowpart_for_combine (GET_MODE (x), tem);
7795 /* Set LHS and RHS to the inner operands (A and B in the example
7796 above) and set OTHER to the common operand (C in the example).
7797 These is only one way to do this unless the inner operation is
7799 if (GET_RTX_CLASS (inner_code) == 'c'
7800 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7801 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7802 else if (GET_RTX_CLASS (inner_code) == 'c'
7803 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7804 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7805 else if (GET_RTX_CLASS (inner_code) == 'c'
7806 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7807 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7808 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7809 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7813 /* Form the new inner operation, seeing if it simplifies first. */
7814 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7816 /* There is one exception to the general way of distributing:
7817 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7818 if (code == XOR && inner_code == IOR)
7821 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7824 /* We may be able to continuing distributing the result, so call
7825 ourselves recursively on the inner operation before forming the
7826 outer operation, which we return. */
7827 return gen_binary (inner_code, GET_MODE (x),
7828 apply_distributive_law (tem), other);
7831 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7834 Return an equivalent form, if different from X. Otherwise, return X. If
7835 X is zero, we are to always construct the equivalent form. */
7838 simplify_and_const_int (x, mode, varop, constop)
7840 enum machine_mode mode;
7842 unsigned HOST_WIDE_INT constop;
7844 unsigned HOST_WIDE_INT nonzero;
7847 /* Simplify VAROP knowing that we will be only looking at some of the
7850 Note by passing in CONSTOP, we guarantee that the bits not set in
7851 CONSTOP are not significant and will never be examined. We must
7852 ensure that is the case by explicitly masking out those bits
7853 before returning. */
7854 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7856 /* If VAROP is a CLOBBER, we will fail so return it. */
7857 if (GET_CODE (varop) == CLOBBER)
7860 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7861 to VAROP and return the new constant. */
7862 if (GET_CODE (varop) == CONST_INT)
7863 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7865 /* See what bits may be nonzero in VAROP. Unlike the general case of
7866 a call to nonzero_bits, here we don't care about bits outside
7869 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7871 /* Turn off all bits in the constant that are known to already be zero.
7872 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7873 which is tested below. */
7877 /* If we don't have any bits left, return zero. */
7881 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7882 a power of two, we can replace this with a ASHIFT. */
7883 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7884 && (i = exact_log2 (constop)) >= 0)
7885 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7887 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7888 or XOR, then try to apply the distributive law. This may eliminate
7889 operations if either branch can be simplified because of the AND.
7890 It may also make some cases more complex, but those cases probably
7891 won't match a pattern either with or without this. */
7893 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7895 gen_lowpart_for_combine
7897 apply_distributive_law
7898 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7899 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7900 XEXP (varop, 0), constop),
7901 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7902 XEXP (varop, 1), constop))));
7904 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7905 the AND and see if one of the operands simplifies to zero. If so, we
7906 may eliminate it. */
7908 if (GET_CODE (varop) == PLUS
7909 && exact_log2 (constop + 1) >= 0)
7913 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7914 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7915 if (o0 == const0_rtx)
7917 if (o1 == const0_rtx)
7921 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7922 if we already had one (just check for the simplest cases). */
7923 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7924 && GET_MODE (XEXP (x, 0)) == mode
7925 && SUBREG_REG (XEXP (x, 0)) == varop)
7926 varop = XEXP (x, 0);
7928 varop = gen_lowpart_for_combine (mode, varop);
7930 /* If we can't make the SUBREG, try to return what we were given. */
7931 if (GET_CODE (varop) == CLOBBER)
7932 return x ? x : varop;
7934 /* If we are only masking insignificant bits, return VAROP. */
7935 if (constop == nonzero)
7939 /* Otherwise, return an AND. */
7940 constop = trunc_int_for_mode (constop, mode);
7941 /* See how much, if any, of X we can use. */
7942 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7943 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7947 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7948 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7949 SUBST (XEXP (x, 1), GEN_INT (constop));
7951 SUBST (XEXP (x, 0), varop);
7958 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7959 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7960 is less useful. We can't allow both, because that results in exponential
7961 run time recursion. There is a nullstone testcase that triggered
7962 this. This macro avoids accidental uses of num_sign_bit_copies. */
7963 #define num_sign_bit_copies()
7965 /* Given an expression, X, compute which bits in X can be non-zero.
7966 We don't care about bits outside of those defined in MODE.
7968 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7969 a shift, AND, or zero_extract, we can do better. */
7971 static unsigned HOST_WIDE_INT
7972 nonzero_bits (x, mode)
7974 enum machine_mode mode;
7976 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7977 unsigned HOST_WIDE_INT inner_nz;
7979 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7982 /* For floating-point values, assume all bits are needed. */
7983 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7986 /* If X is wider than MODE, use its mode instead. */
7987 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7989 mode = GET_MODE (x);
7990 nonzero = GET_MODE_MASK (mode);
7991 mode_width = GET_MODE_BITSIZE (mode);
7994 if (mode_width > HOST_BITS_PER_WIDE_INT)
7995 /* Our only callers in this case look for single bit values. So
7996 just return the mode mask. Those tests will then be false. */
7999 #ifndef WORD_REGISTER_OPERATIONS
8000 /* If MODE is wider than X, but both are a single word for both the host
8001 and target machines, we can compute this from which bits of the
8002 object might be nonzero in its own mode, taking into account the fact
8003 that on many CISC machines, accessing an object in a wider mode
8004 causes the high-order bits to become undefined. So they are
8005 not known to be zero. */
8007 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8008 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8009 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8010 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8012 nonzero &= nonzero_bits (x, GET_MODE (x));
8013 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8018 code = GET_CODE (x);
8022 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8023 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8024 all the bits above ptr_mode are known to be zero. */
8025 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8027 nonzero &= GET_MODE_MASK (ptr_mode);
8030 /* Include declared information about alignment of pointers. */
8031 /* ??? We don't properly preserve REG_POINTER changes across
8032 pointer-to-integer casts, so we can't trust it except for
8033 things that we know must be pointers. See execute/960116-1.c. */
8034 if ((x == stack_pointer_rtx
8035 || x == frame_pointer_rtx
8036 || x == arg_pointer_rtx)
8037 && REGNO_POINTER_ALIGN (REGNO (x)))
8039 unsigned HOST_WIDE_INT alignment
8040 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8042 #ifdef PUSH_ROUNDING
8043 /* If PUSH_ROUNDING is defined, it is possible for the
8044 stack to be momentarily aligned only to that amount,
8045 so we pick the least alignment. */
8046 if (x == stack_pointer_rtx && PUSH_ARGS)
8047 alignment = MIN (PUSH_ROUNDING (1), alignment);
8050 nonzero &= ~(alignment - 1);
8053 /* If X is a register whose nonzero bits value is current, use it.
8054 Otherwise, if X is a register whose value we can find, use that
8055 value. Otherwise, use the previously-computed global nonzero bits
8056 for this register. */
8058 if (reg_last_set_value[REGNO (x)] != 0
8059 && (reg_last_set_mode[REGNO (x)] == mode
8060 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8061 && GET_MODE_CLASS (mode) == MODE_INT))
8062 && (reg_last_set_label[REGNO (x)] == label_tick
8063 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8064 && REG_N_SETS (REGNO (x)) == 1
8065 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8067 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8068 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8070 tem = get_last_value (x);
8074 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8075 /* If X is narrower than MODE and TEM is a non-negative
8076 constant that would appear negative in the mode of X,
8077 sign-extend it for use in reg_nonzero_bits because some
8078 machines (maybe most) will actually do the sign-extension
8079 and this is the conservative approach.
8081 ??? For 2.5, try to tighten up the MD files in this regard
8082 instead of this kludge. */
8084 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8085 && GET_CODE (tem) == CONST_INT
8087 && 0 != (INTVAL (tem)
8088 & ((HOST_WIDE_INT) 1
8089 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8090 tem = GEN_INT (INTVAL (tem)
8091 | ((HOST_WIDE_INT) (-1)
8092 << GET_MODE_BITSIZE (GET_MODE (x))));
8094 return nonzero_bits (tem, mode) & nonzero;
8096 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8098 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8100 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8101 /* We don't know anything about the upper bits. */
8102 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8103 return nonzero & mask;
8109 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8110 /* If X is negative in MODE, sign-extend the value. */
8111 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8112 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8113 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8119 #ifdef LOAD_EXTEND_OP
8120 /* In many, if not most, RISC machines, reading a byte from memory
8121 zeros the rest of the register. Noticing that fact saves a lot
8122 of extra zero-extends. */
8123 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8124 nonzero &= GET_MODE_MASK (GET_MODE (x));
8129 case UNEQ: case LTGT:
8130 case GT: case GTU: case UNGT:
8131 case LT: case LTU: case UNLT:
8132 case GE: case GEU: case UNGE:
8133 case LE: case LEU: case UNLE:
8134 case UNORDERED: case ORDERED:
8136 /* If this produces an integer result, we know which bits are set.
8137 Code here used to clear bits outside the mode of X, but that is
8140 if (GET_MODE_CLASS (mode) == MODE_INT
8141 && mode_width <= HOST_BITS_PER_WIDE_INT)
8142 nonzero = STORE_FLAG_VALUE;
8147 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8148 and num_sign_bit_copies. */
8149 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8150 == GET_MODE_BITSIZE (GET_MODE (x)))
8154 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8155 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8160 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8161 and num_sign_bit_copies. */
8162 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8163 == GET_MODE_BITSIZE (GET_MODE (x)))
8169 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8173 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8174 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8175 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8179 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8180 Otherwise, show all the bits in the outer mode but not the inner
8182 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8183 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8185 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8187 & (((HOST_WIDE_INT) 1
8188 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8189 inner_nz |= (GET_MODE_MASK (mode)
8190 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8193 nonzero &= inner_nz;
8197 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8198 & nonzero_bits (XEXP (x, 1), mode));
8202 case UMIN: case UMAX: case SMIN: case SMAX:
8204 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
8206 /* Don't call nonzero_bits for the second time if it cannot change
8208 if ((nonzero & nonzero0) != nonzero)
8209 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
8213 case PLUS: case MINUS:
8215 case DIV: case UDIV:
8216 case MOD: case UMOD:
8217 /* We can apply the rules of arithmetic to compute the number of
8218 high- and low-order zero bits of these operations. We start by
8219 computing the width (position of the highest-order non-zero bit)
8220 and the number of low-order zero bits for each value. */
8222 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8223 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8224 int width0 = floor_log2 (nz0) + 1;
8225 int width1 = floor_log2 (nz1) + 1;
8226 int low0 = floor_log2 (nz0 & -nz0);
8227 int low1 = floor_log2 (nz1 & -nz1);
8228 HOST_WIDE_INT op0_maybe_minusp
8229 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8230 HOST_WIDE_INT op1_maybe_minusp
8231 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8232 unsigned int result_width = mode_width;
8238 result_width = MAX (width0, width1) + 1;
8239 result_low = MIN (low0, low1);
8242 result_low = MIN (low0, low1);
8245 result_width = width0 + width1;
8246 result_low = low0 + low1;
8251 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8252 result_width = width0;
8257 result_width = width0;
8262 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8263 result_width = MIN (width0, width1);
8264 result_low = MIN (low0, low1);
8269 result_width = MIN (width0, width1);
8270 result_low = MIN (low0, low1);
8276 if (result_width < mode_width)
8277 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8280 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8282 #ifdef POINTERS_EXTEND_UNSIGNED
8283 /* If pointers extend unsigned and this is an addition or subtraction
8284 to a pointer in Pmode, all the bits above ptr_mode are known to be
8286 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8287 && (code == PLUS || code == MINUS)
8288 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8289 nonzero &= GET_MODE_MASK (ptr_mode);
8295 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8296 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8297 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8301 /* If this is a SUBREG formed for a promoted variable that has
8302 been zero-extended, we know that at least the high-order bits
8303 are zero, though others might be too. */
8305 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8306 nonzero = (GET_MODE_MASK (GET_MODE (x))
8307 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8309 /* If the inner mode is a single word for both the host and target
8310 machines, we can compute this from which bits of the inner
8311 object might be nonzero. */
8312 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8313 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8314 <= HOST_BITS_PER_WIDE_INT))
8316 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8318 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8319 /* If this is a typical RISC machine, we only have to worry
8320 about the way loads are extended. */
8321 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8323 & (((unsigned HOST_WIDE_INT) 1
8324 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8326 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8329 /* On many CISC machines, accessing an object in a wider mode
8330 causes the high-order bits to become undefined. So they are
8331 not known to be zero. */
8332 if (GET_MODE_SIZE (GET_MODE (x))
8333 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8334 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8335 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8344 /* The nonzero bits are in two classes: any bits within MODE
8345 that aren't in GET_MODE (x) are always significant. The rest of the
8346 nonzero bits are those that are significant in the operand of
8347 the shift when shifted the appropriate number of bits. This
8348 shows that high-order bits are cleared by the right shift and
8349 low-order bits by left shifts. */
8350 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8351 && INTVAL (XEXP (x, 1)) >= 0
8352 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8354 enum machine_mode inner_mode = GET_MODE (x);
8355 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8356 int count = INTVAL (XEXP (x, 1));
8357 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8358 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8359 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8360 unsigned HOST_WIDE_INT outer = 0;
8362 if (mode_width > width)
8363 outer = (op_nonzero & nonzero & ~mode_mask);
8365 if (code == LSHIFTRT)
8367 else if (code == ASHIFTRT)
8371 /* If the sign bit may have been nonzero before the shift, we
8372 need to mark all the places it could have been copied to
8373 by the shift as possibly nonzero. */
8374 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8375 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8377 else if (code == ASHIFT)
8380 inner = ((inner << (count % width)
8381 | (inner >> (width - (count % width)))) & mode_mask);
8383 nonzero &= (outer | inner);
8388 /* This is at most the number of bits in the mode. */
8389 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8393 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8394 | nonzero_bits (XEXP (x, 2), mode));
8404 /* See the macro definition above. */
8405 #undef num_sign_bit_copies
8407 /* Return the number of bits at the high-order end of X that are known to
8408 be equal to the sign bit. X will be used in mode MODE; if MODE is
8409 VOIDmode, X will be used in its own mode. The returned value will always
8410 be between 1 and the number of bits in MODE. */
8413 num_sign_bit_copies (x, mode)
8415 enum machine_mode mode;
8417 enum rtx_code code = GET_CODE (x);
8418 unsigned int bitwidth;
8419 int num0, num1, result;
8420 unsigned HOST_WIDE_INT nonzero;
8423 /* If we weren't given a mode, use the mode of X. If the mode is still
8424 VOIDmode, we don't know anything. Likewise if one of the modes is
8427 if (mode == VOIDmode)
8428 mode = GET_MODE (x);
8430 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8433 bitwidth = GET_MODE_BITSIZE (mode);
8435 /* For a smaller object, just ignore the high bits. */
8436 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8438 num0 = num_sign_bit_copies (x, GET_MODE (x));
8440 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8443 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8445 #ifndef WORD_REGISTER_OPERATIONS
8446 /* If this machine does not do all register operations on the entire
8447 register and MODE is wider than the mode of X, we can say nothing
8448 at all about the high-order bits. */
8451 /* Likewise on machines that do, if the mode of the object is smaller
8452 than a word and loads of that size don't sign extend, we can say
8453 nothing about the high order bits. */
8454 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8455 #ifdef LOAD_EXTEND_OP
8456 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8467 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8468 /* If pointers extend signed and this is a pointer in Pmode, say that
8469 all the bits above ptr_mode are known to be sign bit copies. */
8470 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8472 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8475 if (reg_last_set_value[REGNO (x)] != 0
8476 && reg_last_set_mode[REGNO (x)] == mode
8477 && (reg_last_set_label[REGNO (x)] == label_tick
8478 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8479 && REG_N_SETS (REGNO (x)) == 1
8480 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8482 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8483 return reg_last_set_sign_bit_copies[REGNO (x)];
8485 tem = get_last_value (x);
8487 return num_sign_bit_copies (tem, mode);
8489 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8490 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8491 return reg_sign_bit_copies[REGNO (x)];
8495 #ifdef LOAD_EXTEND_OP
8496 /* Some RISC machines sign-extend all loads of smaller than a word. */
8497 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8498 return MAX (1, ((int) bitwidth
8499 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8504 /* If the constant is negative, take its 1's complement and remask.
8505 Then see how many zero bits we have. */
8506 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8507 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8508 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8509 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8511 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8514 /* If this is a SUBREG for a promoted object that is sign-extended
8515 and we are looking at it in a wider mode, we know that at least the
8516 high-order bits are known to be sign bit copies. */
8518 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8520 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8521 return MAX ((int) bitwidth
8522 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8526 /* For a smaller object, just ignore the high bits. */
8527 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8529 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8530 return MAX (1, (num0
8531 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8535 #ifdef WORD_REGISTER_OPERATIONS
8536 #ifdef LOAD_EXTEND_OP
8537 /* For paradoxical SUBREGs on machines where all register operations
8538 affect the entire register, just look inside. Note that we are
8539 passing MODE to the recursive call, so the number of sign bit copies
8540 will remain relative to that mode, not the inner mode. */
8542 /* This works only if loads sign extend. Otherwise, if we get a
8543 reload for the inner part, it may be loaded from the stack, and
8544 then we lose all sign bit copies that existed before the store
8547 if ((GET_MODE_SIZE (GET_MODE (x))
8548 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8549 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8550 return num_sign_bit_copies (SUBREG_REG (x), mode);
8556 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8557 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8561 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8562 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8565 /* For a smaller object, just ignore the high bits. */
8566 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8567 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8571 return num_sign_bit_copies (XEXP (x, 0), mode);
8573 case ROTATE: case ROTATERT:
8574 /* If we are rotating left by a number of bits less than the number
8575 of sign bit copies, we can just subtract that amount from the
8577 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8578 && INTVAL (XEXP (x, 1)) >= 0
8579 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8581 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8582 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8583 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8588 /* In general, this subtracts one sign bit copy. But if the value
8589 is known to be positive, the number of sign bit copies is the
8590 same as that of the input. Finally, if the input has just one bit
8591 that might be nonzero, all the bits are copies of the sign bit. */
8592 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8593 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8594 return num0 > 1 ? num0 - 1 : 1;
8596 nonzero = nonzero_bits (XEXP (x, 0), mode);
8601 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8606 case IOR: case AND: case XOR:
8607 case SMIN: case SMAX: case UMIN: case UMAX:
8608 /* Logical operations will preserve the number of sign-bit copies.
8609 MIN and MAX operations always return one of the operands. */
8610 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8611 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8612 return MIN (num0, num1);
8614 case PLUS: case MINUS:
8615 /* For addition and subtraction, we can have a 1-bit carry. However,
8616 if we are subtracting 1 from a positive number, there will not
8617 be such a carry. Furthermore, if the positive number is known to
8618 be 0 or 1, we know the result is either -1 or 0. */
8620 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8621 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8623 nonzero = nonzero_bits (XEXP (x, 0), mode);
8624 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8625 return (nonzero == 1 || nonzero == 0 ? bitwidth
8626 : bitwidth - floor_log2 (nonzero) - 1);
8629 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8630 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8631 result = MAX (1, MIN (num0, num1) - 1);
8633 #ifdef POINTERS_EXTEND_UNSIGNED
8634 /* If pointers extend signed and this is an addition or subtraction
8635 to a pointer in Pmode, all the bits above ptr_mode are known to be
8637 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8638 && (code == PLUS || code == MINUS)
8639 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8640 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8641 - GET_MODE_BITSIZE (ptr_mode) + 1),
8647 /* The number of bits of the product is the sum of the number of
8648 bits of both terms. However, unless one of the terms if known
8649 to be positive, we must allow for an additional bit since negating
8650 a negative number can remove one sign bit copy. */
8652 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8653 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8655 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8657 && (bitwidth > HOST_BITS_PER_WIDE_INT
8658 || (((nonzero_bits (XEXP (x, 0), mode)
8659 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8660 && ((nonzero_bits (XEXP (x, 1), mode)
8661 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8664 return MAX (1, result);
8667 /* The result must be <= the first operand. If the first operand
8668 has the high bit set, we know nothing about the number of sign
8670 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8672 else if ((nonzero_bits (XEXP (x, 0), mode)
8673 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8676 return num_sign_bit_copies (XEXP (x, 0), mode);
8679 /* The result must be <= the second operand. */
8680 return num_sign_bit_copies (XEXP (x, 1), mode);
8683 /* Similar to unsigned division, except that we have to worry about
8684 the case where the divisor is negative, in which case we have
8686 result = num_sign_bit_copies (XEXP (x, 0), mode);
8688 && (bitwidth > HOST_BITS_PER_WIDE_INT
8689 || (nonzero_bits (XEXP (x, 1), mode)
8690 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8696 result = num_sign_bit_copies (XEXP (x, 1), mode);
8698 && (bitwidth > HOST_BITS_PER_WIDE_INT
8699 || (nonzero_bits (XEXP (x, 1), mode)
8700 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8706 /* Shifts by a constant add to the number of bits equal to the
8708 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8709 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8710 && INTVAL (XEXP (x, 1)) > 0)
8711 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8716 /* Left shifts destroy copies. */
8717 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8718 || INTVAL (XEXP (x, 1)) < 0
8719 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8722 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8723 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8726 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8727 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8728 return MIN (num0, num1);
8730 case EQ: case NE: case GE: case GT: case LE: case LT:
8731 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8732 case GEU: case GTU: case LEU: case LTU:
8733 case UNORDERED: case ORDERED:
8734 /* If the constant is negative, take its 1's complement and remask.
8735 Then see how many zero bits we have. */
8736 nonzero = STORE_FLAG_VALUE;
8737 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8738 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8739 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8741 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8748 /* If we haven't been able to figure it out by one of the above rules,
8749 see if some of the high-order bits are known to be zero. If so,
8750 count those bits and return one less than that amount. If we can't
8751 safely compute the mask for this mode, always return BITWIDTH. */
8753 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8756 nonzero = nonzero_bits (x, mode);
8757 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8758 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8761 /* Return the number of "extended" bits there are in X, when interpreted
8762 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8763 unsigned quantities, this is the number of high-order zero bits.
8764 For signed quantities, this is the number of copies of the sign bit
8765 minus 1. In both case, this function returns the number of "spare"
8766 bits. For example, if two quantities for which this function returns
8767 at least 1 are added, the addition is known not to overflow.
8769 This function will always return 0 unless called during combine, which
8770 implies that it must be called from a define_split. */
8773 extended_count (x, mode, unsignedp)
8775 enum machine_mode mode;
8778 if (nonzero_sign_valid == 0)
8782 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8783 ? (GET_MODE_BITSIZE (mode) - 1
8784 - floor_log2 (nonzero_bits (x, mode)))
8786 : num_sign_bit_copies (x, mode) - 1);
8789 /* This function is called from `simplify_shift_const' to merge two
8790 outer operations. Specifically, we have already found that we need
8791 to perform operation *POP0 with constant *PCONST0 at the outermost
8792 position. We would now like to also perform OP1 with constant CONST1
8793 (with *POP0 being done last).
8795 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8796 the resulting operation. *PCOMP_P is set to 1 if we would need to
8797 complement the innermost operand, otherwise it is unchanged.
8799 MODE is the mode in which the operation will be done. No bits outside
8800 the width of this mode matter. It is assumed that the width of this mode
8801 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8803 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8804 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8805 result is simply *PCONST0.
8807 If the resulting operation cannot be expressed as one operation, we
8808 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8811 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8812 enum rtx_code *pop0;
8813 HOST_WIDE_INT *pconst0;
8815 HOST_WIDE_INT const1;
8816 enum machine_mode mode;
8819 enum rtx_code op0 = *pop0;
8820 HOST_WIDE_INT const0 = *pconst0;
8822 const0 &= GET_MODE_MASK (mode);
8823 const1 &= GET_MODE_MASK (mode);
8825 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8829 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8832 if (op1 == NIL || op0 == SET)
8835 else if (op0 == NIL)
8836 op0 = op1, const0 = const1;
8838 else if (op0 == op1)
8862 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8863 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8866 /* If the two constants aren't the same, we can't do anything. The
8867 remaining six cases can all be done. */
8868 else if (const0 != const1)
8876 /* (a & b) | b == b */
8878 else /* op1 == XOR */
8879 /* (a ^ b) | b == a | b */
8885 /* (a & b) ^ b == (~a) & b */
8886 op0 = AND, *pcomp_p = 1;
8887 else /* op1 == IOR */
8888 /* (a | b) ^ b == a & ~b */
8889 op0 = AND, *pconst0 = ~const0;
8894 /* (a | b) & b == b */
8896 else /* op1 == XOR */
8897 /* (a ^ b) & b) == (~a) & b */
8904 /* Check for NO-OP cases. */
8905 const0 &= GET_MODE_MASK (mode);
8907 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8909 else if (const0 == 0 && op0 == AND)
8911 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8915 /* ??? Slightly redundant with the above mask, but not entirely.
8916 Moving this above means we'd have to sign-extend the mode mask
8917 for the final test. */
8918 const0 = trunc_int_for_mode (const0, mode);
8926 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8927 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8928 that we started with.
8930 The shift is normally computed in the widest mode we find in VAROP, as
8931 long as it isn't a different number of words than RESULT_MODE. Exceptions
8932 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8935 simplify_shift_const (x, code, result_mode, varop, orig_count)
8938 enum machine_mode result_mode;
8942 enum rtx_code orig_code = code;
8945 enum machine_mode mode = result_mode;
8946 enum machine_mode shift_mode, tmode;
8947 unsigned int mode_words
8948 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8949 /* We form (outer_op (code varop count) (outer_const)). */
8950 enum rtx_code outer_op = NIL;
8951 HOST_WIDE_INT outer_const = 0;
8953 int complement_p = 0;
8956 /* Make sure and truncate the "natural" shift on the way in. We don't
8957 want to do this inside the loop as it makes it more difficult to
8959 #ifdef SHIFT_COUNT_TRUNCATED
8960 if (SHIFT_COUNT_TRUNCATED)
8961 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8964 /* If we were given an invalid count, don't do anything except exactly
8965 what was requested. */
8967 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8972 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8977 /* Unless one of the branches of the `if' in this loop does a `continue',
8978 we will `break' the loop after the `if'. */
8982 /* If we have an operand of (clobber (const_int 0)), just return that
8984 if (GET_CODE (varop) == CLOBBER)
8987 /* If we discovered we had to complement VAROP, leave. Making a NOT
8988 here would cause an infinite loop. */
8992 /* Convert ROTATERT to ROTATE. */
8993 if (code == ROTATERT)
8994 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8996 /* We need to determine what mode we will do the shift in. If the
8997 shift is a right shift or a ROTATE, we must always do it in the mode
8998 it was originally done in. Otherwise, we can do it in MODE, the
8999 widest mode encountered. */
9001 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9002 ? result_mode : mode);
9004 /* Handle cases where the count is greater than the size of the mode
9005 minus 1. For ASHIFT, use the size minus one as the count (this can
9006 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9007 take the count modulo the size. For other shifts, the result is
9010 Since these shifts are being produced by the compiler by combining
9011 multiple operations, each of which are defined, we know what the
9012 result is supposed to be. */
9014 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
9016 if (code == ASHIFTRT)
9017 count = GET_MODE_BITSIZE (shift_mode) - 1;
9018 else if (code == ROTATE || code == ROTATERT)
9019 count %= GET_MODE_BITSIZE (shift_mode);
9022 /* We can't simply return zero because there may be an
9030 /* An arithmetic right shift of a quantity known to be -1 or 0
9032 if (code == ASHIFTRT
9033 && (num_sign_bit_copies (varop, shift_mode)
9034 == GET_MODE_BITSIZE (shift_mode)))
9040 /* If we are doing an arithmetic right shift and discarding all but
9041 the sign bit copies, this is equivalent to doing a shift by the
9042 bitsize minus one. Convert it into that shift because it will often
9043 allow other simplifications. */
9045 if (code == ASHIFTRT
9046 && (count + num_sign_bit_copies (varop, shift_mode)
9047 >= GET_MODE_BITSIZE (shift_mode)))
9048 count = GET_MODE_BITSIZE (shift_mode) - 1;
9050 /* We simplify the tests below and elsewhere by converting
9051 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9052 `make_compound_operation' will convert it to a ASHIFTRT for
9053 those machines (such as VAX) that don't have a LSHIFTRT. */
9054 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9056 && ((nonzero_bits (varop, shift_mode)
9057 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9061 switch (GET_CODE (varop))
9067 new = expand_compound_operation (varop);
9076 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9077 minus the width of a smaller mode, we can do this with a
9078 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9079 if ((code == ASHIFTRT || code == LSHIFTRT)
9080 && ! mode_dependent_address_p (XEXP (varop, 0))
9081 && ! MEM_VOLATILE_P (varop)
9082 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9083 MODE_INT, 1)) != BLKmode)
9085 new = adjust_address_nv (varop, tmode,
9086 BYTES_BIG_ENDIAN ? 0
9087 : count / BITS_PER_UNIT);
9089 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9090 : ZERO_EXTEND, mode, new);
9097 /* Similar to the case above, except that we can only do this if
9098 the resulting mode is the same as that of the underlying
9099 MEM and adjust the address depending on the *bits* endianness
9100 because of the way that bit-field extract insns are defined. */
9101 if ((code == ASHIFTRT || code == LSHIFTRT)
9102 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9103 MODE_INT, 1)) != BLKmode
9104 && tmode == GET_MODE (XEXP (varop, 0)))
9106 if (BITS_BIG_ENDIAN)
9107 new = XEXP (varop, 0);
9110 new = copy_rtx (XEXP (varop, 0));
9111 SUBST (XEXP (new, 0),
9112 plus_constant (XEXP (new, 0),
9113 count / BITS_PER_UNIT));
9116 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9117 : ZERO_EXTEND, mode, new);
9124 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9125 the same number of words as what we've seen so far. Then store
9126 the widest mode in MODE. */
9127 if (subreg_lowpart_p (varop)
9128 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9129 > GET_MODE_SIZE (GET_MODE (varop)))
9130 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9131 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9134 varop = SUBREG_REG (varop);
9135 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9136 mode = GET_MODE (varop);
9142 /* Some machines use MULT instead of ASHIFT because MULT
9143 is cheaper. But it is still better on those machines to
9144 merge two shifts into one. */
9145 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9146 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9149 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9150 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9156 /* Similar, for when divides are cheaper. */
9157 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9158 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9161 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9162 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9168 /* If we are extracting just the sign bit of an arithmetic
9169 right shift, that shift is not needed. However, the sign
9170 bit of a wider mode may be different from what would be
9171 interpreted as the sign bit in a narrower mode, so, if
9172 the result is narrower, don't discard the shift. */
9173 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9174 && (GET_MODE_BITSIZE (result_mode)
9175 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9177 varop = XEXP (varop, 0);
9181 /* ... fall through ... */
9186 /* Here we have two nested shifts. The result is usually the
9187 AND of a new shift with a mask. We compute the result below. */
9188 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9189 && INTVAL (XEXP (varop, 1)) >= 0
9190 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9191 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9192 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9194 enum rtx_code first_code = GET_CODE (varop);
9195 unsigned int first_count = INTVAL (XEXP (varop, 1));
9196 unsigned HOST_WIDE_INT mask;
9199 /* We have one common special case. We can't do any merging if
9200 the inner code is an ASHIFTRT of a smaller mode. However, if
9201 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9202 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9203 we can convert it to
9204 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9205 This simplifies certain SIGN_EXTEND operations. */
9206 if (code == ASHIFT && first_code == ASHIFTRT
9207 && (GET_MODE_BITSIZE (result_mode)
9208 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9210 /* C3 has the low-order C1 bits zero. */
9212 mask = (GET_MODE_MASK (mode)
9213 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9215 varop = simplify_and_const_int (NULL_RTX, result_mode,
9216 XEXP (varop, 0), mask);
9217 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9219 count = first_count;
9224 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9225 than C1 high-order bits equal to the sign bit, we can convert
9226 this to either an ASHIFT or a ASHIFTRT depending on the
9229 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9231 if (code == ASHIFTRT && first_code == ASHIFT
9232 && GET_MODE (varop) == shift_mode
9233 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9236 varop = XEXP (varop, 0);
9238 signed_count = count - first_count;
9239 if (signed_count < 0)
9240 count = -signed_count, code = ASHIFT;
9242 count = signed_count;
9247 /* There are some cases we can't do. If CODE is ASHIFTRT,
9248 we can only do this if FIRST_CODE is also ASHIFTRT.
9250 We can't do the case when CODE is ROTATE and FIRST_CODE is
9253 If the mode of this shift is not the mode of the outer shift,
9254 we can't do this if either shift is a right shift or ROTATE.
9256 Finally, we can't do any of these if the mode is too wide
9257 unless the codes are the same.
9259 Handle the case where the shift codes are the same
9262 if (code == first_code)
9264 if (GET_MODE (varop) != result_mode
9265 && (code == ASHIFTRT || code == LSHIFTRT
9269 count += first_count;
9270 varop = XEXP (varop, 0);
9274 if (code == ASHIFTRT
9275 || (code == ROTATE && first_code == ASHIFTRT)
9276 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9277 || (GET_MODE (varop) != result_mode
9278 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9279 || first_code == ROTATE
9280 || code == ROTATE)))
9283 /* To compute the mask to apply after the shift, shift the
9284 nonzero bits of the inner shift the same way the
9285 outer shift will. */
9287 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9290 = simplify_binary_operation (code, result_mode, mask_rtx,
9293 /* Give up if we can't compute an outer operation to use. */
9295 || GET_CODE (mask_rtx) != CONST_INT
9296 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9298 result_mode, &complement_p))
9301 /* If the shifts are in the same direction, we add the
9302 counts. Otherwise, we subtract them. */
9303 signed_count = count;
9304 if ((code == ASHIFTRT || code == LSHIFTRT)
9305 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9306 signed_count += first_count;
9308 signed_count -= first_count;
9310 /* If COUNT is positive, the new shift is usually CODE,
9311 except for the two exceptions below, in which case it is
9312 FIRST_CODE. If the count is negative, FIRST_CODE should
9314 if (signed_count > 0
9315 && ((first_code == ROTATE && code == ASHIFT)
9316 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9317 code = first_code, count = signed_count;
9318 else if (signed_count < 0)
9319 code = first_code, count = -signed_count;
9321 count = signed_count;
9323 varop = XEXP (varop, 0);
9327 /* If we have (A << B << C) for any shift, we can convert this to
9328 (A << C << B). This wins if A is a constant. Only try this if
9329 B is not a constant. */
9331 else if (GET_CODE (varop) == code
9332 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9334 = simplify_binary_operation (code, mode,
9338 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9345 /* Make this fit the case below. */
9346 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9347 GEN_INT (GET_MODE_MASK (mode)));
9353 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9354 with C the size of VAROP - 1 and the shift is logical if
9355 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9356 we have an (le X 0) operation. If we have an arithmetic shift
9357 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9358 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9360 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9361 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9362 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9363 && (code == LSHIFTRT || code == ASHIFTRT)
9364 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9365 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9368 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9371 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9372 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9377 /* If we have (shift (logical)), move the logical to the outside
9378 to allow it to possibly combine with another logical and the
9379 shift to combine with another shift. This also canonicalizes to
9380 what a ZERO_EXTRACT looks like. Also, some machines have
9381 (and (shift)) insns. */
9383 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9384 && (new = simplify_binary_operation (code, result_mode,
9386 GEN_INT (count))) != 0
9387 && GET_CODE (new) == CONST_INT
9388 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9389 INTVAL (new), result_mode, &complement_p))
9391 varop = XEXP (varop, 0);
9395 /* If we can't do that, try to simplify the shift in each arm of the
9396 logical expression, make a new logical expression, and apply
9397 the inverse distributive law. */
9399 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9400 XEXP (varop, 0), count);
9401 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9402 XEXP (varop, 1), count);
9404 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9405 varop = apply_distributive_law (varop);
9412 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9413 says that the sign bit can be tested, FOO has mode MODE, C is
9414 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9415 that may be nonzero. */
9416 if (code == LSHIFTRT
9417 && XEXP (varop, 1) == const0_rtx
9418 && GET_MODE (XEXP (varop, 0)) == result_mode
9419 && count == GET_MODE_BITSIZE (result_mode) - 1
9420 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9421 && ((STORE_FLAG_VALUE
9422 & ((HOST_WIDE_INT) 1
9423 < (GET_MODE_BITSIZE (result_mode) - 1))))
9424 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9425 && merge_outer_ops (&outer_op, &outer_const, XOR,
9426 (HOST_WIDE_INT) 1, result_mode,
9429 varop = XEXP (varop, 0);
9436 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9437 than the number of bits in the mode is equivalent to A. */
9438 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9439 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9441 varop = XEXP (varop, 0);
9446 /* NEG commutes with ASHIFT since it is multiplication. Move the
9447 NEG outside to allow shifts to combine. */
9449 && merge_outer_ops (&outer_op, &outer_const, NEG,
9450 (HOST_WIDE_INT) 0, result_mode,
9453 varop = XEXP (varop, 0);
9459 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9460 is one less than the number of bits in the mode is
9461 equivalent to (xor A 1). */
9462 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9463 && XEXP (varop, 1) == constm1_rtx
9464 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9465 && merge_outer_ops (&outer_op, &outer_const, XOR,
9466 (HOST_WIDE_INT) 1, result_mode,
9470 varop = XEXP (varop, 0);
9474 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9475 that might be nonzero in BAR are those being shifted out and those
9476 bits are known zero in FOO, we can replace the PLUS with FOO.
9477 Similarly in the other operand order. This code occurs when
9478 we are computing the size of a variable-size array. */
9480 if ((code == ASHIFTRT || code == LSHIFTRT)
9481 && count < HOST_BITS_PER_WIDE_INT
9482 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9483 && (nonzero_bits (XEXP (varop, 1), result_mode)
9484 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9486 varop = XEXP (varop, 0);
9489 else if ((code == ASHIFTRT || code == LSHIFTRT)
9490 && count < HOST_BITS_PER_WIDE_INT
9491 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9492 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9494 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9495 & nonzero_bits (XEXP (varop, 1),
9498 varop = XEXP (varop, 1);
9502 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9504 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9505 && (new = simplify_binary_operation (ASHIFT, result_mode,
9507 GEN_INT (count))) != 0
9508 && GET_CODE (new) == CONST_INT
9509 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9510 INTVAL (new), result_mode, &complement_p))
9512 varop = XEXP (varop, 0);
9518 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9519 with C the size of VAROP - 1 and the shift is logical if
9520 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9521 we have a (gt X 0) operation. If the shift is arithmetic with
9522 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9523 we have a (neg (gt X 0)) operation. */
9525 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9526 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9527 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9528 && (code == LSHIFTRT || code == ASHIFTRT)
9529 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9530 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9531 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9534 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9537 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9538 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9545 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9546 if the truncate does not affect the value. */
9547 if (code == LSHIFTRT
9548 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9549 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9550 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9551 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9552 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9554 rtx varop_inner = XEXP (varop, 0);
9557 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9558 XEXP (varop_inner, 0),
9560 (count + INTVAL (XEXP (varop_inner, 1))));
9561 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9574 /* We need to determine what mode to do the shift in. If the shift is
9575 a right shift or ROTATE, we must always do it in the mode it was
9576 originally done in. Otherwise, we can do it in MODE, the widest mode
9577 encountered. The code we care about is that of the shift that will
9578 actually be done, not the shift that was originally requested. */
9580 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9581 ? result_mode : mode);
9583 /* We have now finished analyzing the shift. The result should be
9584 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9585 OUTER_OP is non-NIL, it is an operation that needs to be applied
9586 to the result of the shift. OUTER_CONST is the relevant constant,
9587 but we must turn off all bits turned off in the shift.
9589 If we were passed a value for X, see if we can use any pieces of
9590 it. If not, make new rtx. */
9592 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9593 && GET_CODE (XEXP (x, 1)) == CONST_INT
9594 && INTVAL (XEXP (x, 1)) == count)
9595 const_rtx = XEXP (x, 1);
9597 const_rtx = GEN_INT (count);
9599 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9600 && GET_MODE (XEXP (x, 0)) == shift_mode
9601 && SUBREG_REG (XEXP (x, 0)) == varop)
9602 varop = XEXP (x, 0);
9603 else if (GET_MODE (varop) != shift_mode)
9604 varop = gen_lowpart_for_combine (shift_mode, varop);
9606 /* If we can't make the SUBREG, try to return what we were given. */
9607 if (GET_CODE (varop) == CLOBBER)
9608 return x ? x : varop;
9610 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9614 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9616 /* If we have an outer operation and we just made a shift, it is
9617 possible that we could have simplified the shift were it not
9618 for the outer operation. So try to do the simplification
9621 if (outer_op != NIL && GET_CODE (x) == code
9622 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9623 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9624 INTVAL (XEXP (x, 1)));
9626 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9627 turn off all the bits that the shift would have turned off. */
9628 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9629 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9630 GET_MODE_MASK (result_mode) >> orig_count);
9632 /* Do the remainder of the processing in RESULT_MODE. */
9633 x = gen_lowpart_for_combine (result_mode, x);
9635 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9638 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9640 if (outer_op != NIL)
9642 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9643 outer_const = trunc_int_for_mode (outer_const, result_mode);
9645 if (outer_op == AND)
9646 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9647 else if (outer_op == SET)
9648 /* This means that we have determined that the result is
9649 equivalent to a constant. This should be rare. */
9650 x = GEN_INT (outer_const);
9651 else if (GET_RTX_CLASS (outer_op) == '1')
9652 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9654 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9660 /* Like recog, but we receive the address of a pointer to a new pattern.
9661 We try to match the rtx that the pointer points to.
9662 If that fails, we may try to modify or replace the pattern,
9663 storing the replacement into the same pointer object.
9665 Modifications include deletion or addition of CLOBBERs.
9667 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9668 the CLOBBERs are placed.
9670 The value is the final insn code from the pattern ultimately matched,
9674 recog_for_combine (pnewpat, insn, pnotes)
9680 int insn_code_number;
9681 int num_clobbers_to_add = 0;
9686 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9687 we use to indicate that something didn't match. If we find such a
9688 thing, force rejection. */
9689 if (GET_CODE (pat) == PARALLEL)
9690 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9691 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9692 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9695 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9696 instruction for pattern recognition. */
9697 dummy_insn = shallow_copy_rtx (insn);
9698 PATTERN (dummy_insn) = pat;
9699 REG_NOTES (dummy_insn) = 0;
9701 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9703 /* If it isn't, there is the possibility that we previously had an insn
9704 that clobbered some register as a side effect, but the combined
9705 insn doesn't need to do that. So try once more without the clobbers
9706 unless this represents an ASM insn. */
9708 if (insn_code_number < 0 && ! check_asm_operands (pat)
9709 && GET_CODE (pat) == PARALLEL)
9713 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9714 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9717 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9721 SUBST_INT (XVECLEN (pat, 0), pos);
9724 pat = XVECEXP (pat, 0, 0);
9726 PATTERN (dummy_insn) = pat;
9727 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9730 /* Recognize all noop sets, these will be killed by followup pass. */
9731 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9732 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9734 /* If we had any clobbers to add, make a new pattern than contains
9735 them. Then check to make sure that all of them are dead. */
9736 if (num_clobbers_to_add)
9738 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9739 rtvec_alloc (GET_CODE (pat) == PARALLEL
9741 + num_clobbers_to_add)
9742 : num_clobbers_to_add + 1));
9744 if (GET_CODE (pat) == PARALLEL)
9745 for (i = 0; i < XVECLEN (pat, 0); i++)
9746 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9748 XVECEXP (newpat, 0, 0) = pat;
9750 add_clobbers (newpat, insn_code_number);
9752 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9753 i < XVECLEN (newpat, 0); i++)
9755 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9756 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9758 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9759 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9767 return insn_code_number;
9770 /* Like gen_lowpart but for use by combine. In combine it is not possible
9771 to create any new pseudoregs. However, it is safe to create
9772 invalid memory addresses, because combine will try to recognize
9773 them and all they will do is make the combine attempt fail.
9775 If for some reason this cannot do its job, an rtx
9776 (clobber (const_int 0)) is returned.
9777 An insn containing that will not be recognized. */
9782 gen_lowpart_for_combine (mode, x)
9783 enum machine_mode mode;
9788 if (GET_MODE (x) == mode)
9791 /* We can only support MODE being wider than a word if X is a
9792 constant integer or has a mode the same size. */
9794 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9795 && ! ((GET_MODE (x) == VOIDmode
9796 && (GET_CODE (x) == CONST_INT
9797 || GET_CODE (x) == CONST_DOUBLE))
9798 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9799 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9801 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9802 won't know what to do. So we will strip off the SUBREG here and
9803 process normally. */
9804 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9807 if (GET_MODE (x) == mode)
9811 result = gen_lowpart_common (mode, x);
9812 #ifdef CLASS_CANNOT_CHANGE_MODE
9814 && GET_CODE (result) == SUBREG
9815 && GET_CODE (SUBREG_REG (result)) == REG
9816 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9817 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9818 GET_MODE (SUBREG_REG (result))))
9819 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9825 if (GET_CODE (x) == MEM)
9829 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9831 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9832 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9834 /* If we want to refer to something bigger than the original memref,
9835 generate a perverse subreg instead. That will force a reload
9836 of the original memref X. */
9837 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9838 return gen_rtx_SUBREG (mode, x, 0);
9840 if (WORDS_BIG_ENDIAN)
9841 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9842 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9844 if (BYTES_BIG_ENDIAN)
9846 /* Adjust the address so that the address-after-the-data is
9848 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9849 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9852 return adjust_address_nv (x, mode, offset);
9855 /* If X is a comparison operator, rewrite it in a new mode. This
9856 probably won't match, but may allow further simplifications. */
9857 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9858 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9860 /* If we couldn't simplify X any other way, just enclose it in a
9861 SUBREG. Normally, this SUBREG won't match, but some patterns may
9862 include an explicit SUBREG or we may simplify it further in combine. */
9868 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9869 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9872 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9876 /* These routines make binary and unary operations by first seeing if they
9877 fold; if not, a new expression is allocated. */
9880 gen_binary (code, mode, op0, op1)
9882 enum machine_mode mode;
9888 if (GET_RTX_CLASS (code) == 'c'
9889 && swap_commutative_operands_p (op0, op1))
9890 tem = op0, op0 = op1, op1 = tem;
9892 if (GET_RTX_CLASS (code) == '<')
9894 enum machine_mode op_mode = GET_MODE (op0);
9896 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9897 just (REL_OP X Y). */
9898 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9900 op1 = XEXP (op0, 1);
9901 op0 = XEXP (op0, 0);
9902 op_mode = GET_MODE (op0);
9905 if (op_mode == VOIDmode)
9906 op_mode = GET_MODE (op1);
9907 result = simplify_relational_operation (code, op_mode, op0, op1);
9910 result = simplify_binary_operation (code, mode, op0, op1);
9915 /* Put complex operands first and constants second. */
9916 if (GET_RTX_CLASS (code) == 'c'
9917 && swap_commutative_operands_p (op0, op1))
9918 return gen_rtx_fmt_ee (code, mode, op1, op0);
9920 /* If we are turning off bits already known off in OP0, we need not do
9922 else if (code == AND && GET_CODE (op1) == CONST_INT
9923 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9924 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9927 return gen_rtx_fmt_ee (code, mode, op0, op1);
9930 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9931 comparison code that will be tested.
9933 The result is a possibly different comparison code to use. *POP0 and
9934 *POP1 may be updated.
9936 It is possible that we might detect that a comparison is either always
9937 true or always false. However, we do not perform general constant
9938 folding in combine, so this knowledge isn't useful. Such tautologies
9939 should have been detected earlier. Hence we ignore all such cases. */
9941 static enum rtx_code
9942 simplify_comparison (code, pop0, pop1)
9951 enum machine_mode mode, tmode;
9953 /* Try a few ways of applying the same transformation to both operands. */
9956 #ifndef WORD_REGISTER_OPERATIONS
9957 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9958 so check specially. */
9959 if (code != GTU && code != GEU && code != LTU && code != LEU
9960 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9961 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9962 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9963 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9964 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9965 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9966 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9967 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9968 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9969 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9970 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9971 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9972 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9973 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9974 && (INTVAL (XEXP (op0, 1))
9975 == (GET_MODE_BITSIZE (GET_MODE (op0))
9977 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9979 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9980 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9984 /* If both operands are the same constant shift, see if we can ignore the
9985 shift. We can if the shift is a rotate or if the bits shifted out of
9986 this shift are known to be zero for both inputs and if the type of
9987 comparison is compatible with the shift. */
9988 if (GET_CODE (op0) == GET_CODE (op1)
9989 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9990 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9991 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9992 && (code != GT && code != LT && code != GE && code != LE))
9993 || (GET_CODE (op0) == ASHIFTRT
9994 && (code != GTU && code != LTU
9995 && code != GEU && code != LEU)))
9996 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9997 && INTVAL (XEXP (op0, 1)) >= 0
9998 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9999 && XEXP (op0, 1) == XEXP (op1, 1))
10001 enum machine_mode mode = GET_MODE (op0);
10002 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10003 int shift_count = INTVAL (XEXP (op0, 1));
10005 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10006 mask &= (mask >> shift_count) << shift_count;
10007 else if (GET_CODE (op0) == ASHIFT)
10008 mask = (mask & (mask << shift_count)) >> shift_count;
10010 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10011 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10012 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10017 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10018 SUBREGs are of the same mode, and, in both cases, the AND would
10019 be redundant if the comparison was done in the narrower mode,
10020 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10021 and the operand's possibly nonzero bits are 0xffffff01; in that case
10022 if we only care about QImode, we don't need the AND). This case
10023 occurs if the output mode of an scc insn is not SImode and
10024 STORE_FLAG_VALUE == 1 (e.g., the 386).
10026 Similarly, check for a case where the AND's are ZERO_EXTEND
10027 operations from some narrower mode even though a SUBREG is not
10030 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10031 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10032 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10034 rtx inner_op0 = XEXP (op0, 0);
10035 rtx inner_op1 = XEXP (op1, 0);
10036 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10037 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10040 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10041 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10042 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10043 && (GET_MODE (SUBREG_REG (inner_op0))
10044 == GET_MODE (SUBREG_REG (inner_op1)))
10045 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10046 <= HOST_BITS_PER_WIDE_INT)
10047 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10048 GET_MODE (SUBREG_REG (inner_op0)))))
10049 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10050 GET_MODE (SUBREG_REG (inner_op1))))))
10052 op0 = SUBREG_REG (inner_op0);
10053 op1 = SUBREG_REG (inner_op1);
10055 /* The resulting comparison is always unsigned since we masked
10056 off the original sign bit. */
10057 code = unsigned_condition (code);
10063 for (tmode = GET_CLASS_NARROWEST_MODE
10064 (GET_MODE_CLASS (GET_MODE (op0)));
10065 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10066 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10068 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10069 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10070 code = unsigned_condition (code);
10079 /* If both operands are NOT, we can strip off the outer operation
10080 and adjust the comparison code for swapped operands; similarly for
10081 NEG, except that this must be an equality comparison. */
10082 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10083 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10084 && (code == EQ || code == NE)))
10085 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10091 /* If the first operand is a constant, swap the operands and adjust the
10092 comparison code appropriately, but don't do this if the second operand
10093 is already a constant integer. */
10094 if (swap_commutative_operands_p (op0, op1))
10096 tem = op0, op0 = op1, op1 = tem;
10097 code = swap_condition (code);
10100 /* We now enter a loop during which we will try to simplify the comparison.
10101 For the most part, we only are concerned with comparisons with zero,
10102 but some things may really be comparisons with zero but not start
10103 out looking that way. */
10105 while (GET_CODE (op1) == CONST_INT)
10107 enum machine_mode mode = GET_MODE (op0);
10108 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10109 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10110 int equality_comparison_p;
10111 int sign_bit_comparison_p;
10112 int unsigned_comparison_p;
10113 HOST_WIDE_INT const_op;
10115 /* We only want to handle integral modes. This catches VOIDmode,
10116 CCmode, and the floating-point modes. An exception is that we
10117 can handle VOIDmode if OP0 is a COMPARE or a comparison
10120 if (GET_MODE_CLASS (mode) != MODE_INT
10121 && ! (mode == VOIDmode
10122 && (GET_CODE (op0) == COMPARE
10123 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10126 /* Get the constant we are comparing against and turn off all bits
10127 not on in our mode. */
10128 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10129 op1 = GEN_INT (const_op);
10131 /* If we are comparing against a constant power of two and the value
10132 being compared can only have that single bit nonzero (e.g., it was
10133 `and'ed with that bit), we can replace this with a comparison
10136 && (code == EQ || code == NE || code == GE || code == GEU
10137 || code == LT || code == LTU)
10138 && mode_width <= HOST_BITS_PER_WIDE_INT
10139 && exact_log2 (const_op) >= 0
10140 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10142 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10143 op1 = const0_rtx, const_op = 0;
10146 /* Similarly, if we are comparing a value known to be either -1 or
10147 0 with -1, change it to the opposite comparison against zero. */
10150 && (code == EQ || code == NE || code == GT || code == LE
10151 || code == GEU || code == LTU)
10152 && num_sign_bit_copies (op0, mode) == mode_width)
10154 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10155 op1 = const0_rtx, const_op = 0;
10158 /* Do some canonicalizations based on the comparison code. We prefer
10159 comparisons against zero and then prefer equality comparisons.
10160 If we can reduce the size of a constant, we will do that too. */
10165 /* < C is equivalent to <= (C - 1) */
10169 op1 = GEN_INT (const_op);
10171 /* ... fall through to LE case below. */
10177 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10181 op1 = GEN_INT (const_op);
10185 /* If we are doing a <= 0 comparison on a value known to have
10186 a zero sign bit, we can replace this with == 0. */
10187 else if (const_op == 0
10188 && mode_width <= HOST_BITS_PER_WIDE_INT
10189 && (nonzero_bits (op0, mode)
10190 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10195 /* >= C is equivalent to > (C - 1). */
10199 op1 = GEN_INT (const_op);
10201 /* ... fall through to GT below. */
10207 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10211 op1 = GEN_INT (const_op);
10215 /* If we are doing a > 0 comparison on a value known to have
10216 a zero sign bit, we can replace this with != 0. */
10217 else if (const_op == 0
10218 && mode_width <= HOST_BITS_PER_WIDE_INT
10219 && (nonzero_bits (op0, mode)
10220 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10225 /* < C is equivalent to <= (C - 1). */
10229 op1 = GEN_INT (const_op);
10231 /* ... fall through ... */
10234 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10235 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10236 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10238 const_op = 0, op1 = const0_rtx;
10246 /* unsigned <= 0 is equivalent to == 0 */
10250 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10251 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10252 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10254 const_op = 0, op1 = const0_rtx;
10260 /* >= C is equivalent to < (C - 1). */
10264 op1 = GEN_INT (const_op);
10266 /* ... fall through ... */
10269 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10270 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10271 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10273 const_op = 0, op1 = const0_rtx;
10281 /* unsigned > 0 is equivalent to != 0 */
10285 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10286 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10287 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10289 const_op = 0, op1 = const0_rtx;
10298 /* Compute some predicates to simplify code below. */
10300 equality_comparison_p = (code == EQ || code == NE);
10301 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10302 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10305 /* If this is a sign bit comparison and we can do arithmetic in
10306 MODE, say that we will only be needing the sign bit of OP0. */
10307 if (sign_bit_comparison_p
10308 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10309 op0 = force_to_mode (op0, mode,
10311 << (GET_MODE_BITSIZE (mode) - 1)),
10314 /* Now try cases based on the opcode of OP0. If none of the cases
10315 does a "continue", we exit this loop immediately after the
10318 switch (GET_CODE (op0))
10321 /* If we are extracting a single bit from a variable position in
10322 a constant that has only a single bit set and are comparing it
10323 with zero, we can convert this into an equality comparison
10324 between the position and the location of the single bit. */
10326 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10327 && XEXP (op0, 1) == const1_rtx
10328 && equality_comparison_p && const_op == 0
10329 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10331 if (BITS_BIG_ENDIAN)
10333 enum machine_mode new_mode
10334 = mode_for_extraction (EP_extzv, 1);
10335 if (new_mode == MAX_MACHINE_MODE)
10336 i = BITS_PER_WORD - 1 - i;
10340 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10344 op0 = XEXP (op0, 2);
10348 /* Result is nonzero iff shift count is equal to I. */
10349 code = reverse_condition (code);
10353 /* ... fall through ... */
10356 tem = expand_compound_operation (op0);
10365 /* If testing for equality, we can take the NOT of the constant. */
10366 if (equality_comparison_p
10367 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10369 op0 = XEXP (op0, 0);
10374 /* If just looking at the sign bit, reverse the sense of the
10376 if (sign_bit_comparison_p)
10378 op0 = XEXP (op0, 0);
10379 code = (code == GE ? LT : GE);
10385 /* If testing for equality, we can take the NEG of the constant. */
10386 if (equality_comparison_p
10387 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10389 op0 = XEXP (op0, 0);
10394 /* The remaining cases only apply to comparisons with zero. */
10398 /* When X is ABS or is known positive,
10399 (neg X) is < 0 if and only if X != 0. */
10401 if (sign_bit_comparison_p
10402 && (GET_CODE (XEXP (op0, 0)) == ABS
10403 || (mode_width <= HOST_BITS_PER_WIDE_INT
10404 && (nonzero_bits (XEXP (op0, 0), mode)
10405 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10407 op0 = XEXP (op0, 0);
10408 code = (code == LT ? NE : EQ);
10412 /* If we have NEG of something whose two high-order bits are the
10413 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10414 if (num_sign_bit_copies (op0, mode) >= 2)
10416 op0 = XEXP (op0, 0);
10417 code = swap_condition (code);
10423 /* If we are testing equality and our count is a constant, we
10424 can perform the inverse operation on our RHS. */
10425 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10426 && (tem = simplify_binary_operation (ROTATERT, mode,
10427 op1, XEXP (op0, 1))) != 0)
10429 op0 = XEXP (op0, 0);
10434 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10435 a particular bit. Convert it to an AND of a constant of that
10436 bit. This will be converted into a ZERO_EXTRACT. */
10437 if (const_op == 0 && sign_bit_comparison_p
10438 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10439 && mode_width <= HOST_BITS_PER_WIDE_INT)
10441 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10444 - INTVAL (XEXP (op0, 1)))));
10445 code = (code == LT ? NE : EQ);
10449 /* Fall through. */
10452 /* ABS is ignorable inside an equality comparison with zero. */
10453 if (const_op == 0 && equality_comparison_p)
10455 op0 = XEXP (op0, 0);
10461 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10462 to (compare FOO CONST) if CONST fits in FOO's mode and we
10463 are either testing inequality or have an unsigned comparison
10464 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10465 if (! unsigned_comparison_p
10466 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10467 <= HOST_BITS_PER_WIDE_INT)
10468 && ((unsigned HOST_WIDE_INT) const_op
10469 < (((unsigned HOST_WIDE_INT) 1
10470 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10472 op0 = XEXP (op0, 0);
10478 /* Check for the case where we are comparing A - C1 with C2,
10479 both constants are smaller than 1/2 the maximum positive
10480 value in MODE, and the comparison is equality or unsigned.
10481 In that case, if A is either zero-extended to MODE or has
10482 sufficient sign bits so that the high-order bit in MODE
10483 is a copy of the sign in the inner mode, we can prove that it is
10484 safe to do the operation in the wider mode. This simplifies
10485 many range checks. */
10487 if (mode_width <= HOST_BITS_PER_WIDE_INT
10488 && subreg_lowpart_p (op0)
10489 && GET_CODE (SUBREG_REG (op0)) == PLUS
10490 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10491 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10492 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10493 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10494 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10495 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10496 GET_MODE (SUBREG_REG (op0)))
10497 & ~GET_MODE_MASK (mode))
10498 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10499 GET_MODE (SUBREG_REG (op0)))
10500 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10501 - GET_MODE_BITSIZE (mode)))))
10503 op0 = SUBREG_REG (op0);
10507 /* If the inner mode is narrower and we are extracting the low part,
10508 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10509 if (subreg_lowpart_p (op0)
10510 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10511 /* Fall through */ ;
10515 /* ... fall through ... */
10518 if ((unsigned_comparison_p || equality_comparison_p)
10519 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10520 <= HOST_BITS_PER_WIDE_INT)
10521 && ((unsigned HOST_WIDE_INT) const_op
10522 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10524 op0 = XEXP (op0, 0);
10530 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10531 this for equality comparisons due to pathological cases involving
10533 if (equality_comparison_p
10534 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10535 op1, XEXP (op0, 1))))
10537 op0 = XEXP (op0, 0);
10542 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10543 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10544 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10546 op0 = XEXP (XEXP (op0, 0), 0);
10547 code = (code == LT ? EQ : NE);
10553 /* We used to optimize signed comparisons against zero, but that
10554 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10555 arrive here as equality comparisons, or (GEU, LTU) are
10556 optimized away. No need to special-case them. */
10558 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10559 (eq B (minus A C)), whichever simplifies. We can only do
10560 this for equality comparisons due to pathological cases involving
10562 if (equality_comparison_p
10563 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10564 XEXP (op0, 1), op1)))
10566 op0 = XEXP (op0, 0);
10571 if (equality_comparison_p
10572 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10573 XEXP (op0, 0), op1)))
10575 op0 = XEXP (op0, 1);
10580 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10581 of bits in X minus 1, is one iff X > 0. */
10582 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10583 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10584 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10585 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10587 op0 = XEXP (op0, 1);
10588 code = (code == GE ? LE : GT);
10594 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10595 if C is zero or B is a constant. */
10596 if (equality_comparison_p
10597 && 0 != (tem = simplify_binary_operation (XOR, mode,
10598 XEXP (op0, 1), op1)))
10600 op0 = XEXP (op0, 0);
10607 case UNEQ: case LTGT:
10608 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10609 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10610 case UNORDERED: case ORDERED:
10611 /* We can't do anything if OP0 is a condition code value, rather
10612 than an actual data value. */
10615 || XEXP (op0, 0) == cc0_rtx
10617 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10620 /* Get the two operands being compared. */
10621 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10622 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10624 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10626 /* Check for the cases where we simply want the result of the
10627 earlier test or the opposite of that result. */
10628 if (code == NE || code == EQ
10629 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10630 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10631 && (STORE_FLAG_VALUE
10632 & (((HOST_WIDE_INT) 1
10633 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10634 && (code == LT || code == GE)))
10636 enum rtx_code new_code;
10637 if (code == LT || code == NE)
10638 new_code = GET_CODE (op0);
10640 new_code = combine_reversed_comparison_code (op0);
10642 if (new_code != UNKNOWN)
10653 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10655 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10656 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10657 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10659 op0 = XEXP (op0, 1);
10660 code = (code == GE ? GT : LE);
10666 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10667 will be converted to a ZERO_EXTRACT later. */
10668 if (const_op == 0 && equality_comparison_p
10669 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10670 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10672 op0 = simplify_and_const_int
10673 (op0, mode, gen_rtx_LSHIFTRT (mode,
10675 XEXP (XEXP (op0, 0), 1)),
10676 (HOST_WIDE_INT) 1);
10680 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10681 zero and X is a comparison and C1 and C2 describe only bits set
10682 in STORE_FLAG_VALUE, we can compare with X. */
10683 if (const_op == 0 && equality_comparison_p
10684 && mode_width <= HOST_BITS_PER_WIDE_INT
10685 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10686 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10687 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10688 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10689 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10691 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10692 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10693 if ((~STORE_FLAG_VALUE & mask) == 0
10694 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10695 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10696 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10698 op0 = XEXP (XEXP (op0, 0), 0);
10703 /* If we are doing an equality comparison of an AND of a bit equal
10704 to the sign bit, replace this with a LT or GE comparison of
10705 the underlying value. */
10706 if (equality_comparison_p
10708 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10709 && mode_width <= HOST_BITS_PER_WIDE_INT
10710 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10711 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10713 op0 = XEXP (op0, 0);
10714 code = (code == EQ ? GE : LT);
10718 /* If this AND operation is really a ZERO_EXTEND from a narrower
10719 mode, the constant fits within that mode, and this is either an
10720 equality or unsigned comparison, try to do this comparison in
10721 the narrower mode. */
10722 if ((equality_comparison_p || unsigned_comparison_p)
10723 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10724 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10725 & GET_MODE_MASK (mode))
10727 && const_op >> i == 0
10728 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10730 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10734 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10735 in both M1 and M2 and the SUBREG is either paradoxical or
10736 represents the low part, permute the SUBREG and the AND and
10738 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10740 #ifdef WORD_REGISTER_OPERATIONS
10742 > (GET_MODE_BITSIZE
10743 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10744 && mode_width <= BITS_PER_WORD)
10747 <= (GET_MODE_BITSIZE
10748 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10749 && subreg_lowpart_p (XEXP (op0, 0))))
10750 #ifndef WORD_REGISTER_OPERATIONS
10751 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10752 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10753 As originally written the upper bits have a defined value
10754 due to the AND operation. However, if we commute the AND
10755 inside the SUBREG then they no longer have defined values
10756 and the meaning of the code has been changed. */
10757 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10758 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10760 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10761 && mode_width <= HOST_BITS_PER_WIDE_INT
10762 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10763 <= HOST_BITS_PER_WIDE_INT)
10764 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10765 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10766 & INTVAL (XEXP (op0, 1)))
10767 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10768 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10769 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10773 = gen_lowpart_for_combine
10775 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10776 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10780 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10781 (eq (and (lshiftrt X) 1) 0). */
10782 if (const_op == 0 && equality_comparison_p
10783 && XEXP (op0, 1) == const1_rtx
10784 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10785 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10787 op0 = simplify_and_const_int
10789 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10790 XEXP (XEXP (op0, 0), 1)),
10791 (HOST_WIDE_INT) 1);
10792 code = (code == NE ? EQ : NE);
10798 /* If we have (compare (ashift FOO N) (const_int C)) and
10799 the high order N bits of FOO (N+1 if an inequality comparison)
10800 are known to be zero, we can do this by comparing FOO with C
10801 shifted right N bits so long as the low-order N bits of C are
10803 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10804 && INTVAL (XEXP (op0, 1)) >= 0
10805 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10806 < HOST_BITS_PER_WIDE_INT)
10808 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10809 && mode_width <= HOST_BITS_PER_WIDE_INT
10810 && (nonzero_bits (XEXP (op0, 0), mode)
10811 & ~(mask >> (INTVAL (XEXP (op0, 1))
10812 + ! equality_comparison_p))) == 0)
10814 /* We must perform a logical shift, not an arithmetic one,
10815 as we want the top N bits of C to be zero. */
10816 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10818 temp >>= INTVAL (XEXP (op0, 1));
10819 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10820 op0 = XEXP (op0, 0);
10824 /* If we are doing a sign bit comparison, it means we are testing
10825 a particular bit. Convert it to the appropriate AND. */
10826 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10827 && mode_width <= HOST_BITS_PER_WIDE_INT)
10829 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10832 - INTVAL (XEXP (op0, 1)))));
10833 code = (code == LT ? NE : EQ);
10837 /* If this an equality comparison with zero and we are shifting
10838 the low bit to the sign bit, we can convert this to an AND of the
10840 if (const_op == 0 && equality_comparison_p
10841 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10842 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10844 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10845 (HOST_WIDE_INT) 1);
10851 /* If this is an equality comparison with zero, we can do this
10852 as a logical shift, which might be much simpler. */
10853 if (equality_comparison_p && const_op == 0
10854 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10856 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10858 INTVAL (XEXP (op0, 1)));
10862 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10863 do the comparison in a narrower mode. */
10864 if (! unsigned_comparison_p
10865 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10866 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10867 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10868 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10869 MODE_INT, 1)) != BLKmode
10870 && (((unsigned HOST_WIDE_INT) const_op
10871 + (GET_MODE_MASK (tmode) >> 1) + 1)
10872 <= GET_MODE_MASK (tmode)))
10874 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10878 /* Likewise if OP0 is a PLUS of a sign extension with a
10879 constant, which is usually represented with the PLUS
10880 between the shifts. */
10881 if (! unsigned_comparison_p
10882 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10883 && GET_CODE (XEXP (op0, 0)) == PLUS
10884 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10885 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10886 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10887 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10888 MODE_INT, 1)) != BLKmode
10889 && (((unsigned HOST_WIDE_INT) const_op
10890 + (GET_MODE_MASK (tmode) >> 1) + 1)
10891 <= GET_MODE_MASK (tmode)))
10893 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10894 rtx add_const = XEXP (XEXP (op0, 0), 1);
10895 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10898 op0 = gen_binary (PLUS, tmode,
10899 gen_lowpart_for_combine (tmode, inner),
10904 /* ... fall through ... */
10906 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10907 the low order N bits of FOO are known to be zero, we can do this
10908 by comparing FOO with C shifted left N bits so long as no
10909 overflow occurs. */
10910 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10911 && INTVAL (XEXP (op0, 1)) >= 0
10912 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10913 && mode_width <= HOST_BITS_PER_WIDE_INT
10914 && (nonzero_bits (XEXP (op0, 0), mode)
10915 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10916 && (((unsigned HOST_WIDE_INT) const_op
10917 + (GET_CODE (op0) != LSHIFTRT
10918 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10921 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10923 /* If the shift was logical, then we must make the condition
10925 if (GET_CODE (op0) == LSHIFTRT)
10926 code = unsigned_condition (code);
10928 const_op <<= INTVAL (XEXP (op0, 1));
10929 op1 = GEN_INT (const_op);
10930 op0 = XEXP (op0, 0);
10934 /* If we are using this shift to extract just the sign bit, we
10935 can replace this with an LT or GE comparison. */
10937 && (equality_comparison_p || sign_bit_comparison_p)
10938 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10939 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10941 op0 = XEXP (op0, 0);
10942 code = (code == NE || code == GT ? LT : GE);
10954 /* Now make any compound operations involved in this comparison. Then,
10955 check for an outmost SUBREG on OP0 that is not doing anything or is
10956 paradoxical. The latter transformation must only be performed when
10957 it is known that the "extra" bits will be the same in op0 and op1 or
10958 that they don't matter. There are three cases to consider:
10960 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10961 care bits and we can assume they have any convenient value. So
10962 making the transformation is safe.
10964 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10965 In this case the upper bits of op0 are undefined. We should not make
10966 the simplification in that case as we do not know the contents of
10969 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10970 NIL. In that case we know those bits are zeros or ones. We must
10971 also be sure that they are the same as the upper bits of op1.
10973 We can never remove a SUBREG for a non-equality comparison because
10974 the sign bit is in a different place in the underlying object. */
10976 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10977 op1 = make_compound_operation (op1, SET);
10979 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10980 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
10982 && GET_CODE (SUBREG_REG (op0)) == REG
10983 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10984 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10985 && (code == NE || code == EQ))
10987 if (GET_MODE_SIZE (GET_MODE (op0))
10988 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10990 op0 = SUBREG_REG (op0);
10991 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10993 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10994 <= HOST_BITS_PER_WIDE_INT)
10995 && (nonzero_bits (SUBREG_REG (op0),
10996 GET_MODE (SUBREG_REG (op0)))
10997 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10999 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11001 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11002 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11003 op0 = SUBREG_REG (op0), op1 = tem;
11007 /* We now do the opposite procedure: Some machines don't have compare
11008 insns in all modes. If OP0's mode is an integer mode smaller than a
11009 word and we can't do a compare in that mode, see if there is a larger
11010 mode for which we can do the compare. There are a number of cases in
11011 which we can use the wider mode. */
11013 mode = GET_MODE (op0);
11014 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11015 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11016 && ! have_insn_for (COMPARE, mode))
11017 for (tmode = GET_MODE_WIDER_MODE (mode);
11019 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11020 tmode = GET_MODE_WIDER_MODE (tmode))
11021 if (have_insn_for (COMPARE, tmode))
11025 /* If the only nonzero bits in OP0 and OP1 are those in the
11026 narrower mode and this is an equality or unsigned comparison,
11027 we can use the wider mode. Similarly for sign-extended
11028 values, in which case it is true for all comparisons. */
11029 zero_extended = ((code == EQ || code == NE
11030 || code == GEU || code == GTU
11031 || code == LEU || code == LTU)
11032 && (nonzero_bits (op0, tmode)
11033 & ~GET_MODE_MASK (mode)) == 0
11034 && ((GET_CODE (op1) == CONST_INT
11035 || (nonzero_bits (op1, tmode)
11036 & ~GET_MODE_MASK (mode)) == 0)));
11039 || ((num_sign_bit_copies (op0, tmode)
11040 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
11041 && (num_sign_bit_copies (op1, tmode)
11042 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
11044 /* If OP0 is an AND and we don't have an AND in MODE either,
11045 make a new AND in the proper mode. */
11046 if (GET_CODE (op0) == AND
11047 && !have_insn_for (AND, mode))
11048 op0 = gen_binary (AND, tmode,
11049 gen_lowpart_for_combine (tmode,
11051 gen_lowpart_for_combine (tmode,
11054 op0 = gen_lowpart_for_combine (tmode, op0);
11055 if (zero_extended && GET_CODE (op1) == CONST_INT)
11056 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11057 op1 = gen_lowpart_for_combine (tmode, op1);
11061 /* If this is a test for negative, we can make an explicit
11062 test of the sign bit. */
11064 if (op1 == const0_rtx && (code == LT || code == GE)
11065 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11067 op0 = gen_binary (AND, tmode,
11068 gen_lowpart_for_combine (tmode, op0),
11069 GEN_INT ((HOST_WIDE_INT) 1
11070 << (GET_MODE_BITSIZE (mode) - 1)));
11071 code = (code == LT) ? NE : EQ;
11076 #ifdef CANONICALIZE_COMPARISON
11077 /* If this machine only supports a subset of valid comparisons, see if we
11078 can convert an unsupported one into a supported one. */
11079 CANONICALIZE_COMPARISON (code, op0, op1);
11088 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11089 searching backward. */
11090 static enum rtx_code
11091 combine_reversed_comparison_code (exp)
11094 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11097 if (code1 != UNKNOWN
11098 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11100 /* Otherwise try and find where the condition codes were last set and
11102 x = get_last_value (XEXP (exp, 0));
11103 if (!x || GET_CODE (x) != COMPARE)
11105 return reversed_comparison_code_parts (GET_CODE (exp),
11106 XEXP (x, 0), XEXP (x, 1), NULL);
11108 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11109 Return NULL_RTX in case we fail to do the reversal. */
11111 reversed_comparison (exp, mode, op0, op1)
11113 enum machine_mode mode;
11115 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11116 if (reversed_code == UNKNOWN)
11119 return gen_binary (reversed_code, mode, op0, op1);
11122 /* Utility function for following routine. Called when X is part of a value
11123 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11124 for each register mentioned. Similar to mention_regs in cse.c */
11127 update_table_tick (x)
11130 enum rtx_code code = GET_CODE (x);
11131 const char *fmt = GET_RTX_FORMAT (code);
11136 unsigned int regno = REGNO (x);
11137 unsigned int endregno
11138 = regno + (regno < FIRST_PSEUDO_REGISTER
11139 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11142 for (r = regno; r < endregno; r++)
11143 reg_last_set_table_tick[r] = label_tick;
11148 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11149 /* Note that we can't have an "E" in values stored; see
11150 get_last_value_validate. */
11152 update_table_tick (XEXP (x, i));
11155 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11156 are saying that the register is clobbered and we no longer know its
11157 value. If INSN is zero, don't update reg_last_set; this is only permitted
11158 with VALUE also zero and is used to invalidate the register. */
11161 record_value_for_reg (reg, insn, value)
11166 unsigned int regno = REGNO (reg);
11167 unsigned int endregno
11168 = regno + (regno < FIRST_PSEUDO_REGISTER
11169 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11172 /* If VALUE contains REG and we have a previous value for REG, substitute
11173 the previous value. */
11174 if (value && insn && reg_overlap_mentioned_p (reg, value))
11178 /* Set things up so get_last_value is allowed to see anything set up to
11180 subst_low_cuid = INSN_CUID (insn);
11181 tem = get_last_value (reg);
11183 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11184 it isn't going to be useful and will take a lot of time to process,
11185 so just use the CLOBBER. */
11189 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11190 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11191 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11192 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11193 tem = XEXP (tem, 0);
11195 value = replace_rtx (copy_rtx (value), reg, tem);
11199 /* For each register modified, show we don't know its value, that
11200 we don't know about its bitwise content, that its value has been
11201 updated, and that we don't know the location of the death of the
11203 for (i = regno; i < endregno; i++)
11206 reg_last_set[i] = insn;
11208 reg_last_set_value[i] = 0;
11209 reg_last_set_mode[i] = 0;
11210 reg_last_set_nonzero_bits[i] = 0;
11211 reg_last_set_sign_bit_copies[i] = 0;
11212 reg_last_death[i] = 0;
11215 /* Mark registers that are being referenced in this value. */
11217 update_table_tick (value);
11219 /* Now update the status of each register being set.
11220 If someone is using this register in this block, set this register
11221 to invalid since we will get confused between the two lives in this
11222 basic block. This makes using this register always invalid. In cse, we
11223 scan the table to invalidate all entries using this register, but this
11224 is too much work for us. */
11226 for (i = regno; i < endregno; i++)
11228 reg_last_set_label[i] = label_tick;
11229 if (value && reg_last_set_table_tick[i] == label_tick)
11230 reg_last_set_invalid[i] = 1;
11232 reg_last_set_invalid[i] = 0;
11235 /* The value being assigned might refer to X (like in "x++;"). In that
11236 case, we must replace it with (clobber (const_int 0)) to prevent
11238 if (value && ! get_last_value_validate (&value, insn,
11239 reg_last_set_label[regno], 0))
11241 value = copy_rtx (value);
11242 if (! get_last_value_validate (&value, insn,
11243 reg_last_set_label[regno], 1))
11247 /* For the main register being modified, update the value, the mode, the
11248 nonzero bits, and the number of sign bit copies. */
11250 reg_last_set_value[regno] = value;
11254 enum machine_mode mode = GET_MODE (reg);
11255 subst_low_cuid = INSN_CUID (insn);
11256 reg_last_set_mode[regno] = mode;
11257 if (GET_MODE_CLASS (mode) == MODE_INT
11258 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11259 mode = nonzero_bits_mode;
11260 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11261 reg_last_set_sign_bit_copies[regno]
11262 = num_sign_bit_copies (value, GET_MODE (reg));
11266 /* Called via note_stores from record_dead_and_set_regs to handle one
11267 SET or CLOBBER in an insn. DATA is the instruction in which the
11268 set is occurring. */
11271 record_dead_and_set_regs_1 (dest, setter, data)
11275 rtx record_dead_insn = (rtx) data;
11277 if (GET_CODE (dest) == SUBREG)
11278 dest = SUBREG_REG (dest);
11280 if (GET_CODE (dest) == REG)
11282 /* If we are setting the whole register, we know its value. Otherwise
11283 show that we don't know the value. We can handle SUBREG in
11285 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11286 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11287 else if (GET_CODE (setter) == SET
11288 && GET_CODE (SET_DEST (setter)) == SUBREG
11289 && SUBREG_REG (SET_DEST (setter)) == dest
11290 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11291 && subreg_lowpart_p (SET_DEST (setter)))
11292 record_value_for_reg (dest, record_dead_insn,
11293 gen_lowpart_for_combine (GET_MODE (dest),
11294 SET_SRC (setter)));
11296 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11298 else if (GET_CODE (dest) == MEM
11299 /* Ignore pushes, they clobber nothing. */
11300 && ! push_operand (dest, GET_MODE (dest)))
11301 mem_last_set = INSN_CUID (record_dead_insn);
11304 /* Update the records of when each REG was most recently set or killed
11305 for the things done by INSN. This is the last thing done in processing
11306 INSN in the combiner loop.
11308 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11309 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11310 and also the similar information mem_last_set (which insn most recently
11311 modified memory) and last_call_cuid (which insn was the most recent
11312 subroutine call). */
11315 record_dead_and_set_regs (insn)
11321 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11323 if (REG_NOTE_KIND (link) == REG_DEAD
11324 && GET_CODE (XEXP (link, 0)) == REG)
11326 unsigned int regno = REGNO (XEXP (link, 0));
11327 unsigned int endregno
11328 = regno + (regno < FIRST_PSEUDO_REGISTER
11329 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11332 for (i = regno; i < endregno; i++)
11333 reg_last_death[i] = insn;
11335 else if (REG_NOTE_KIND (link) == REG_INC)
11336 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11339 if (GET_CODE (insn) == CALL_INSN)
11341 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11342 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11344 reg_last_set_value[i] = 0;
11345 reg_last_set_mode[i] = 0;
11346 reg_last_set_nonzero_bits[i] = 0;
11347 reg_last_set_sign_bit_copies[i] = 0;
11348 reg_last_death[i] = 0;
11351 last_call_cuid = mem_last_set = INSN_CUID (insn);
11353 /* Don't bother recording what this insn does. It might set the
11354 return value register, but we can't combine into a call
11355 pattern anyway, so there's no point trying (and it may cause
11356 a crash, if e.g. we wind up asking for last_set_value of a
11357 SUBREG of the return value register). */
11361 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11364 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11365 register present in the SUBREG, so for each such SUBREG go back and
11366 adjust nonzero and sign bit information of the registers that are
11367 known to have some zero/sign bits set.
11369 This is needed because when combine blows the SUBREGs away, the
11370 information on zero/sign bits is lost and further combines can be
11371 missed because of that. */
11374 record_promoted_value (insn, subreg)
11379 unsigned int regno = REGNO (SUBREG_REG (subreg));
11380 enum machine_mode mode = GET_MODE (subreg);
11382 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11385 for (links = LOG_LINKS (insn); links;)
11387 insn = XEXP (links, 0);
11388 set = single_set (insn);
11390 if (! set || GET_CODE (SET_DEST (set)) != REG
11391 || REGNO (SET_DEST (set)) != regno
11392 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11394 links = XEXP (links, 1);
11398 if (reg_last_set[regno] == insn)
11400 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11401 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11404 if (GET_CODE (SET_SRC (set)) == REG)
11406 regno = REGNO (SET_SRC (set));
11407 links = LOG_LINKS (insn);
11414 /* Scan X for promoted SUBREGs. For each one found,
11415 note what it implies to the registers used in it. */
11418 check_promoted_subreg (insn, x)
11422 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11423 && GET_CODE (SUBREG_REG (x)) == REG)
11424 record_promoted_value (insn, x);
11427 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11430 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11434 check_promoted_subreg (insn, XEXP (x, i));
11438 if (XVEC (x, i) != 0)
11439 for (j = 0; j < XVECLEN (x, i); j++)
11440 check_promoted_subreg (insn, XVECEXP (x, i, j));
11446 /* Utility routine for the following function. Verify that all the registers
11447 mentioned in *LOC are valid when *LOC was part of a value set when
11448 label_tick == TICK. Return 0 if some are not.
11450 If REPLACE is non-zero, replace the invalid reference with
11451 (clobber (const_int 0)) and return 1. This replacement is useful because
11452 we often can get useful information about the form of a value (e.g., if
11453 it was produced by a shift that always produces -1 or 0) even though
11454 we don't know exactly what registers it was produced from. */
11457 get_last_value_validate (loc, insn, tick, replace)
11464 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11465 int len = GET_RTX_LENGTH (GET_CODE (x));
11468 if (GET_CODE (x) == REG)
11470 unsigned int regno = REGNO (x);
11471 unsigned int endregno
11472 = regno + (regno < FIRST_PSEUDO_REGISTER
11473 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11476 for (j = regno; j < endregno; j++)
11477 if (reg_last_set_invalid[j]
11478 /* If this is a pseudo-register that was only set once and not
11479 live at the beginning of the function, it is always valid. */
11480 || (! (regno >= FIRST_PSEUDO_REGISTER
11481 && REG_N_SETS (regno) == 1
11482 && (! REGNO_REG_SET_P
11483 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11484 && reg_last_set_label[j] > tick))
11487 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11493 /* If this is a memory reference, make sure that there were
11494 no stores after it that might have clobbered the value. We don't
11495 have alias info, so we assume any store invalidates it. */
11496 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11497 && INSN_CUID (insn) <= mem_last_set)
11500 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11504 for (i = 0; i < len; i++)
11506 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11507 /* Don't bother with these. They shouldn't occur anyway. */
11511 /* If we haven't found a reason for it to be invalid, it is valid. */
11515 /* Get the last value assigned to X, if known. Some registers
11516 in the value may be replaced with (clobber (const_int 0)) if their value
11517 is known longer known reliably. */
11523 unsigned int regno;
11526 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11527 then convert it to the desired mode. If this is a paradoxical SUBREG,
11528 we cannot predict what values the "extra" bits might have. */
11529 if (GET_CODE (x) == SUBREG
11530 && subreg_lowpart_p (x)
11531 && (GET_MODE_SIZE (GET_MODE (x))
11532 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11533 && (value = get_last_value (SUBREG_REG (x))) != 0)
11534 return gen_lowpart_for_combine (GET_MODE (x), value);
11536 if (GET_CODE (x) != REG)
11540 value = reg_last_set_value[regno];
11542 /* If we don't have a value, or if it isn't for this basic block and
11543 it's either a hard register, set more than once, or it's a live
11544 at the beginning of the function, return 0.
11546 Because if it's not live at the beginning of the function then the reg
11547 is always set before being used (is never used without being set).
11548 And, if it's set only once, and it's always set before use, then all
11549 uses must have the same last value, even if it's not from this basic
11553 || (reg_last_set_label[regno] != label_tick
11554 && (regno < FIRST_PSEUDO_REGISTER
11555 || REG_N_SETS (regno) != 1
11556 || (REGNO_REG_SET_P
11557 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11560 /* If the value was set in a later insn than the ones we are processing,
11561 we can't use it even if the register was only set once. */
11562 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11565 /* If the value has all its registers valid, return it. */
11566 if (get_last_value_validate (&value, reg_last_set[regno],
11567 reg_last_set_label[regno], 0))
11570 /* Otherwise, make a copy and replace any invalid register with
11571 (clobber (const_int 0)). If that fails for some reason, return 0. */
11573 value = copy_rtx (value);
11574 if (get_last_value_validate (&value, reg_last_set[regno],
11575 reg_last_set_label[regno], 1))
11581 /* Return nonzero if expression X refers to a REG or to memory
11582 that is set in an instruction more recent than FROM_CUID. */
11585 use_crosses_set_p (x, from_cuid)
11591 enum rtx_code code = GET_CODE (x);
11595 unsigned int regno = REGNO (x);
11596 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11597 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11599 #ifdef PUSH_ROUNDING
11600 /* Don't allow uses of the stack pointer to be moved,
11601 because we don't know whether the move crosses a push insn. */
11602 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11605 for (; regno < endreg; regno++)
11606 if (reg_last_set[regno]
11607 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11612 if (code == MEM && mem_last_set > from_cuid)
11615 fmt = GET_RTX_FORMAT (code);
11617 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11622 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11623 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11626 else if (fmt[i] == 'e'
11627 && use_crosses_set_p (XEXP (x, i), from_cuid))
11633 /* Define three variables used for communication between the following
11636 static unsigned int reg_dead_regno, reg_dead_endregno;
11637 static int reg_dead_flag;
11639 /* Function called via note_stores from reg_dead_at_p.
11641 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11642 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11645 reg_dead_at_p_1 (dest, x, data)
11648 void *data ATTRIBUTE_UNUSED;
11650 unsigned int regno, endregno;
11652 if (GET_CODE (dest) != REG)
11655 regno = REGNO (dest);
11656 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11657 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11659 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11660 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11663 /* Return non-zero if REG is known to be dead at INSN.
11665 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11666 referencing REG, it is dead. If we hit a SET referencing REG, it is
11667 live. Otherwise, see if it is live or dead at the start of the basic
11668 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11669 must be assumed to be always live. */
11672 reg_dead_at_p (reg, insn)
11679 /* Set variables for reg_dead_at_p_1. */
11680 reg_dead_regno = REGNO (reg);
11681 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11682 ? HARD_REGNO_NREGS (reg_dead_regno,
11688 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11689 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11691 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11692 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11696 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11697 beginning of function. */
11698 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11699 insn = prev_nonnote_insn (insn))
11701 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11703 return reg_dead_flag == 1 ? 1 : 0;
11705 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11709 /* Get the basic block number that we were in. */
11714 for (block = 0; block < n_basic_blocks; block++)
11715 if (insn == BLOCK_HEAD (block))
11718 if (block == n_basic_blocks)
11722 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11723 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11729 /* Note hard registers in X that are used. This code is similar to
11730 that in flow.c, but much simpler since we don't care about pseudos. */
11733 mark_used_regs_combine (x)
11736 RTX_CODE code = GET_CODE (x);
11737 unsigned int regno;
11750 case ADDR_DIFF_VEC:
11753 /* CC0 must die in the insn after it is set, so we don't need to take
11754 special note of it here. */
11760 /* If we are clobbering a MEM, mark any hard registers inside the
11761 address as used. */
11762 if (GET_CODE (XEXP (x, 0)) == MEM)
11763 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11768 /* A hard reg in a wide mode may really be multiple registers.
11769 If so, mark all of them just like the first. */
11770 if (regno < FIRST_PSEUDO_REGISTER)
11772 unsigned int endregno, r;
11774 /* None of this applies to the stack, frame or arg pointers */
11775 if (regno == STACK_POINTER_REGNUM
11776 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11777 || regno == HARD_FRAME_POINTER_REGNUM
11779 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11780 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11782 || regno == FRAME_POINTER_REGNUM)
11785 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11786 for (r = regno; r < endregno; r++)
11787 SET_HARD_REG_BIT (newpat_used_regs, r);
11793 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11795 rtx testreg = SET_DEST (x);
11797 while (GET_CODE (testreg) == SUBREG
11798 || GET_CODE (testreg) == ZERO_EXTRACT
11799 || GET_CODE (testreg) == SIGN_EXTRACT
11800 || GET_CODE (testreg) == STRICT_LOW_PART)
11801 testreg = XEXP (testreg, 0);
11803 if (GET_CODE (testreg) == MEM)
11804 mark_used_regs_combine (XEXP (testreg, 0));
11806 mark_used_regs_combine (SET_SRC (x));
11814 /* Recursively scan the operands of this expression. */
11817 const char *fmt = GET_RTX_FORMAT (code);
11819 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11822 mark_used_regs_combine (XEXP (x, i));
11823 else if (fmt[i] == 'E')
11827 for (j = 0; j < XVECLEN (x, i); j++)
11828 mark_used_regs_combine (XVECEXP (x, i, j));
11834 /* Remove register number REGNO from the dead registers list of INSN.
11836 Return the note used to record the death, if there was one. */
11839 remove_death (regno, insn)
11840 unsigned int regno;
11843 rtx note = find_regno_note (insn, REG_DEAD, regno);
11847 REG_N_DEATHS (regno)--;
11848 remove_note (insn, note);
11854 /* For each register (hardware or pseudo) used within expression X, if its
11855 death is in an instruction with cuid between FROM_CUID (inclusive) and
11856 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11857 list headed by PNOTES.
11859 That said, don't move registers killed by maybe_kill_insn.
11861 This is done when X is being merged by combination into TO_INSN. These
11862 notes will then be distributed as needed. */
11865 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11867 rtx maybe_kill_insn;
11874 enum rtx_code code = GET_CODE (x);
11878 unsigned int regno = REGNO (x);
11879 rtx where_dead = reg_last_death[regno];
11880 rtx before_dead, after_dead;
11882 /* Don't move the register if it gets killed in between from and to */
11883 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11884 && ! reg_referenced_p (x, maybe_kill_insn))
11887 /* WHERE_DEAD could be a USE insn made by combine, so first we
11888 make sure that we have insns with valid INSN_CUID values. */
11889 before_dead = where_dead;
11890 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11891 before_dead = PREV_INSN (before_dead);
11893 after_dead = where_dead;
11894 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11895 after_dead = NEXT_INSN (after_dead);
11897 if (before_dead && after_dead
11898 && INSN_CUID (before_dead) >= from_cuid
11899 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11900 || (where_dead != after_dead
11901 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11903 rtx note = remove_death (regno, where_dead);
11905 /* It is possible for the call above to return 0. This can occur
11906 when reg_last_death points to I2 or I1 that we combined with.
11907 In that case make a new note.
11909 We must also check for the case where X is a hard register
11910 and NOTE is a death note for a range of hard registers
11911 including X. In that case, we must put REG_DEAD notes for
11912 the remaining registers in place of NOTE. */
11914 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11915 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11916 > GET_MODE_SIZE (GET_MODE (x))))
11918 unsigned int deadregno = REGNO (XEXP (note, 0));
11919 unsigned int deadend
11920 = (deadregno + HARD_REGNO_NREGS (deadregno,
11921 GET_MODE (XEXP (note, 0))));
11922 unsigned int ourend
11923 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11926 for (i = deadregno; i < deadend; i++)
11927 if (i < regno || i >= ourend)
11928 REG_NOTES (where_dead)
11929 = gen_rtx_EXPR_LIST (REG_DEAD,
11930 gen_rtx_REG (reg_raw_mode[i], i),
11931 REG_NOTES (where_dead));
11934 /* If we didn't find any note, or if we found a REG_DEAD note that
11935 covers only part of the given reg, and we have a multi-reg hard
11936 register, then to be safe we must check for REG_DEAD notes
11937 for each register other than the first. They could have
11938 their own REG_DEAD notes lying around. */
11939 else if ((note == 0
11941 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11942 < GET_MODE_SIZE (GET_MODE (x)))))
11943 && regno < FIRST_PSEUDO_REGISTER
11944 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11946 unsigned int ourend
11947 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11948 unsigned int i, offset;
11952 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11956 for (i = regno + offset; i < ourend; i++)
11957 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11958 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11961 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11963 XEXP (note, 1) = *pnotes;
11967 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11969 REG_N_DEATHS (regno)++;
11975 else if (GET_CODE (x) == SET)
11977 rtx dest = SET_DEST (x);
11979 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11981 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11982 that accesses one word of a multi-word item, some
11983 piece of everything register in the expression is used by
11984 this insn, so remove any old death. */
11985 /* ??? So why do we test for equality of the sizes? */
11987 if (GET_CODE (dest) == ZERO_EXTRACT
11988 || GET_CODE (dest) == STRICT_LOW_PART
11989 || (GET_CODE (dest) == SUBREG
11990 && (((GET_MODE_SIZE (GET_MODE (dest))
11991 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11992 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11993 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11995 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11999 /* If this is some other SUBREG, we know it replaces the entire
12000 value, so use that as the destination. */
12001 if (GET_CODE (dest) == SUBREG)
12002 dest = SUBREG_REG (dest);
12004 /* If this is a MEM, adjust deaths of anything used in the address.
12005 For a REG (the only other possibility), the entire value is
12006 being replaced so the old value is not used in this insn. */
12008 if (GET_CODE (dest) == MEM)
12009 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12014 else if (GET_CODE (x) == CLOBBER)
12017 len = GET_RTX_LENGTH (code);
12018 fmt = GET_RTX_FORMAT (code);
12020 for (i = 0; i < len; i++)
12025 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12026 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12029 else if (fmt[i] == 'e')
12030 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12034 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12035 pattern of an insn. X must be a REG. */
12038 reg_bitfield_target_p (x, body)
12044 if (GET_CODE (body) == SET)
12046 rtx dest = SET_DEST (body);
12048 unsigned int regno, tregno, endregno, endtregno;
12050 if (GET_CODE (dest) == ZERO_EXTRACT)
12051 target = XEXP (dest, 0);
12052 else if (GET_CODE (dest) == STRICT_LOW_PART)
12053 target = SUBREG_REG (XEXP (dest, 0));
12057 if (GET_CODE (target) == SUBREG)
12058 target = SUBREG_REG (target);
12060 if (GET_CODE (target) != REG)
12063 tregno = REGNO (target), regno = REGNO (x);
12064 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12065 return target == x;
12067 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12068 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12070 return endregno > tregno && regno < endtregno;
12073 else if (GET_CODE (body) == PARALLEL)
12074 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12075 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12081 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12082 as appropriate. I3 and I2 are the insns resulting from the combination
12083 insns including FROM (I2 may be zero).
12085 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12086 not need REG_DEAD notes because they are being substituted for. This
12087 saves searching in the most common cases.
12089 Each note in the list is either ignored or placed on some insns, depending
12090 on the type of note. */
12093 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12097 rtx elim_i2, elim_i1;
12099 rtx note, next_note;
12102 for (note = notes; note; note = next_note)
12104 rtx place = 0, place2 = 0;
12106 /* If this NOTE references a pseudo register, ensure it references
12107 the latest copy of that register. */
12108 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12109 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12110 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12112 next_note = XEXP (note, 1);
12113 switch (REG_NOTE_KIND (note))
12117 case REG_EXEC_COUNT:
12118 /* Doesn't matter much where we put this, as long as it's somewhere.
12119 It is preferable to keep these notes on branches, which is most
12120 likely to be i3. */
12124 case REG_VTABLE_REF:
12125 /* ??? Should remain with *a particular* memory load. Given the
12126 nature of vtable data, the last insn seems relatively safe. */
12130 case REG_NON_LOCAL_GOTO:
12131 if (GET_CODE (i3) == JUMP_INSN)
12133 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12139 case REG_EH_REGION:
12140 /* These notes must remain with the call or trapping instruction. */
12141 if (GET_CODE (i3) == CALL_INSN)
12143 else if (i2 && GET_CODE (i2) == CALL_INSN)
12145 else if (flag_non_call_exceptions)
12147 if (may_trap_p (i3))
12149 else if (i2 && may_trap_p (i2))
12151 /* ??? Otherwise assume we've combined things such that we
12152 can now prove that the instructions can't trap. Drop the
12153 note in this case. */
12161 /* These notes must remain with the call. It should not be
12162 possible for both I2 and I3 to be a call. */
12163 if (GET_CODE (i3) == CALL_INSN)
12165 else if (i2 && GET_CODE (i2) == CALL_INSN)
12172 /* Any clobbers for i3 may still exist, and so we must process
12173 REG_UNUSED notes from that insn.
12175 Any clobbers from i2 or i1 can only exist if they were added by
12176 recog_for_combine. In that case, recog_for_combine created the
12177 necessary REG_UNUSED notes. Trying to keep any original
12178 REG_UNUSED notes from these insns can cause incorrect output
12179 if it is for the same register as the original i3 dest.
12180 In that case, we will notice that the register is set in i3,
12181 and then add a REG_UNUSED note for the destination of i3, which
12182 is wrong. However, it is possible to have REG_UNUSED notes from
12183 i2 or i1 for register which were both used and clobbered, so
12184 we keep notes from i2 or i1 if they will turn into REG_DEAD
12187 /* If this register is set or clobbered in I3, put the note there
12188 unless there is one already. */
12189 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12191 if (from_insn != i3)
12194 if (! (GET_CODE (XEXP (note, 0)) == REG
12195 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12196 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12199 /* Otherwise, if this register is used by I3, then this register
12200 now dies here, so we must put a REG_DEAD note here unless there
12202 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12203 && ! (GET_CODE (XEXP (note, 0)) == REG
12204 ? find_regno_note (i3, REG_DEAD,
12205 REGNO (XEXP (note, 0)))
12206 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12208 PUT_REG_NOTE_KIND (note, REG_DEAD);
12216 /* These notes say something about results of an insn. We can
12217 only support them if they used to be on I3 in which case they
12218 remain on I3. Otherwise they are ignored.
12220 If the note refers to an expression that is not a constant, we
12221 must also ignore the note since we cannot tell whether the
12222 equivalence is still true. It might be possible to do
12223 slightly better than this (we only have a problem if I2DEST
12224 or I1DEST is present in the expression), but it doesn't
12225 seem worth the trouble. */
12227 if (from_insn == i3
12228 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12233 case REG_NO_CONFLICT:
12234 /* These notes say something about how a register is used. They must
12235 be present on any use of the register in I2 or I3. */
12236 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12239 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12249 /* This can show up in several ways -- either directly in the
12250 pattern, or hidden off in the constant pool with (or without?)
12251 a REG_EQUAL note. */
12252 /* ??? Ignore the without-reg_equal-note problem for now. */
12253 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12254 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12255 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12256 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12260 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12261 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12262 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12263 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12271 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12272 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12273 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12275 if (JUMP_LABEL (place) != XEXP (note, 0))
12277 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12278 LABEL_NUSES (JUMP_LABEL (place))--;
12281 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12283 if (JUMP_LABEL (place2) != XEXP (note, 0))
12285 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12286 LABEL_NUSES (JUMP_LABEL (place2))--;
12293 /* These notes say something about the value of a register prior
12294 to the execution of an insn. It is too much trouble to see
12295 if the note is still correct in all situations. It is better
12296 to simply delete it. */
12300 /* If the insn previously containing this note still exists,
12301 put it back where it was. Otherwise move it to the previous
12302 insn. Adjust the corresponding REG_LIBCALL note. */
12303 if (GET_CODE (from_insn) != NOTE)
12307 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12308 place = prev_real_insn (from_insn);
12310 XEXP (tem, 0) = place;
12311 /* If we're deleting the last remaining instruction of a
12312 libcall sequence, don't add the notes. */
12313 else if (XEXP (note, 0) == from_insn)
12319 /* This is handled similarly to REG_RETVAL. */
12320 if (GET_CODE (from_insn) != NOTE)
12324 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12325 place = next_real_insn (from_insn);
12327 XEXP (tem, 0) = place;
12328 /* If we're deleting the last remaining instruction of a
12329 libcall sequence, don't add the notes. */
12330 else if (XEXP (note, 0) == from_insn)
12336 /* If the register is used as an input in I3, it dies there.
12337 Similarly for I2, if it is non-zero and adjacent to I3.
12339 If the register is not used as an input in either I3 or I2
12340 and it is not one of the registers we were supposed to eliminate,
12341 there are two possibilities. We might have a non-adjacent I2
12342 or we might have somehow eliminated an additional register
12343 from a computation. For example, we might have had A & B where
12344 we discover that B will always be zero. In this case we will
12345 eliminate the reference to A.
12347 In both cases, we must search to see if we can find a previous
12348 use of A and put the death note there. */
12351 && GET_CODE (from_insn) == CALL_INSN
12352 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12354 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12356 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12357 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12360 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12361 || rtx_equal_p (XEXP (note, 0), elim_i1))
12366 basic_block bb = BASIC_BLOCK (this_basic_block);
12368 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12370 if (! INSN_P (tem))
12372 if (tem == bb->head)
12377 /* If the register is being set at TEM, see if that is all
12378 TEM is doing. If so, delete TEM. Otherwise, make this
12379 into a REG_UNUSED note instead. */
12380 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12382 rtx set = single_set (tem);
12383 rtx inner_dest = 0;
12385 rtx cc0_setter = NULL_RTX;
12389 for (inner_dest = SET_DEST (set);
12390 (GET_CODE (inner_dest) == STRICT_LOW_PART
12391 || GET_CODE (inner_dest) == SUBREG
12392 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12393 inner_dest = XEXP (inner_dest, 0))
12396 /* Verify that it was the set, and not a clobber that
12397 modified the register.
12399 CC0 targets must be careful to maintain setter/user
12400 pairs. If we cannot delete the setter due to side
12401 effects, mark the user with an UNUSED note instead
12404 if (set != 0 && ! side_effects_p (SET_SRC (set))
12405 && rtx_equal_p (XEXP (note, 0), inner_dest)
12407 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12408 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12409 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12413 /* Move the notes and links of TEM elsewhere.
12414 This might delete other dead insns recursively.
12415 First set the pattern to something that won't use
12418 PATTERN (tem) = pc_rtx;
12420 distribute_notes (REG_NOTES (tem), tem, tem,
12421 NULL_RTX, NULL_RTX, NULL_RTX);
12422 distribute_links (LOG_LINKS (tem));
12424 PUT_CODE (tem, NOTE);
12425 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12426 NOTE_SOURCE_FILE (tem) = 0;
12429 /* Delete the setter too. */
12432 PATTERN (cc0_setter) = pc_rtx;
12434 distribute_notes (REG_NOTES (cc0_setter),
12435 cc0_setter, cc0_setter,
12436 NULL_RTX, NULL_RTX, NULL_RTX);
12437 distribute_links (LOG_LINKS (cc0_setter));
12439 PUT_CODE (cc0_setter, NOTE);
12440 NOTE_LINE_NUMBER (cc0_setter)
12441 = NOTE_INSN_DELETED;
12442 NOTE_SOURCE_FILE (cc0_setter) = 0;
12446 /* If the register is both set and used here, put the
12447 REG_DEAD note here, but place a REG_UNUSED note
12448 here too unless there already is one. */
12449 else if (reg_referenced_p (XEXP (note, 0),
12454 if (! find_regno_note (tem, REG_UNUSED,
12455 REGNO (XEXP (note, 0))))
12457 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12462 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12464 /* If there isn't already a REG_UNUSED note, put one
12466 if (! find_regno_note (tem, REG_UNUSED,
12467 REGNO (XEXP (note, 0))))
12472 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12473 || (GET_CODE (tem) == CALL_INSN
12474 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12478 /* If we are doing a 3->2 combination, and we have a
12479 register which formerly died in i3 and was not used
12480 by i2, which now no longer dies in i3 and is used in
12481 i2 but does not die in i2, and place is between i2
12482 and i3, then we may need to move a link from place to
12484 if (i2 && INSN_UID (place) <= max_uid_cuid
12485 && INSN_CUID (place) > INSN_CUID (i2)
12487 && INSN_CUID (from_insn) > INSN_CUID (i2)
12488 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12490 rtx links = LOG_LINKS (place);
12491 LOG_LINKS (place) = 0;
12492 distribute_links (links);
12497 if (tem == bb->head)
12501 /* We haven't found an insn for the death note and it
12502 is still a REG_DEAD note, but we have hit the beginning
12503 of the block. If the existing life info says the reg
12504 was dead, there's nothing left to do. Otherwise, we'll
12505 need to do a global life update after combine. */
12506 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12507 && REGNO_REG_SET_P (bb->global_live_at_start,
12508 REGNO (XEXP (note, 0))))
12510 SET_BIT (refresh_blocks, this_basic_block);
12515 /* If the register is set or already dead at PLACE, we needn't do
12516 anything with this note if it is still a REG_DEAD note.
12517 We can here if it is set at all, not if is it totally replace,
12518 which is what `dead_or_set_p' checks, so also check for it being
12521 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12523 unsigned int regno = REGNO (XEXP (note, 0));
12525 /* Similarly, if the instruction on which we want to place
12526 the note is a noop, we'll need do a global live update
12527 after we remove them in delete_noop_moves. */
12528 if (noop_move_p (place))
12530 SET_BIT (refresh_blocks, this_basic_block);
12534 if (dead_or_set_p (place, XEXP (note, 0))
12535 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12537 /* Unless the register previously died in PLACE, clear
12538 reg_last_death. [I no longer understand why this is
12540 if (reg_last_death[regno] != place)
12541 reg_last_death[regno] = 0;
12545 reg_last_death[regno] = place;
12547 /* If this is a death note for a hard reg that is occupying
12548 multiple registers, ensure that we are still using all
12549 parts of the object. If we find a piece of the object
12550 that is unused, we must arrange for an appropriate REG_DEAD
12551 note to be added for it. However, we can't just emit a USE
12552 and tag the note to it, since the register might actually
12553 be dead; so we recourse, and the recursive call then finds
12554 the previous insn that used this register. */
12556 if (place && regno < FIRST_PSEUDO_REGISTER
12557 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12559 unsigned int endregno
12560 = regno + HARD_REGNO_NREGS (regno,
12561 GET_MODE (XEXP (note, 0)));
12565 for (i = regno; i < endregno; i++)
12566 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12567 && ! find_regno_fusage (place, USE, i))
12568 || dead_or_set_regno_p (place, i))
12573 /* Put only REG_DEAD notes for pieces that are
12574 not already dead or set. */
12576 for (i = regno; i < endregno;
12577 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12579 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12580 basic_block bb = BASIC_BLOCK (this_basic_block);
12582 if (! dead_or_set_p (place, piece)
12583 && ! reg_bitfield_target_p (piece,
12587 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12589 distribute_notes (new_note, place, place,
12590 NULL_RTX, NULL_RTX, NULL_RTX);
12592 else if (! refers_to_regno_p (i, i + 1,
12593 PATTERN (place), 0)
12594 && ! find_regno_fusage (place, USE, i))
12595 for (tem = PREV_INSN (place); ;
12596 tem = PREV_INSN (tem))
12598 if (! INSN_P (tem))
12600 if (tem == bb->head)
12602 SET_BIT (refresh_blocks,
12609 if (dead_or_set_p (tem, piece)
12610 || reg_bitfield_target_p (piece,
12614 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12629 /* Any other notes should not be present at this point in the
12636 XEXP (note, 1) = REG_NOTES (place);
12637 REG_NOTES (place) = note;
12639 else if ((REG_NOTE_KIND (note) == REG_DEAD
12640 || REG_NOTE_KIND (note) == REG_UNUSED)
12641 && GET_CODE (XEXP (note, 0)) == REG)
12642 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12646 if ((REG_NOTE_KIND (note) == REG_DEAD
12647 || REG_NOTE_KIND (note) == REG_UNUSED)
12648 && GET_CODE (XEXP (note, 0)) == REG)
12649 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12651 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12652 REG_NOTE_KIND (note),
12654 REG_NOTES (place2));
12659 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12660 I3, I2, and I1 to new locations. This is also called in one case to
12661 add a link pointing at I3 when I3's destination is changed. */
12664 distribute_links (links)
12667 rtx link, next_link;
12669 for (link = links; link; link = next_link)
12675 next_link = XEXP (link, 1);
12677 /* If the insn that this link points to is a NOTE or isn't a single
12678 set, ignore it. In the latter case, it isn't clear what we
12679 can do other than ignore the link, since we can't tell which
12680 register it was for. Such links wouldn't be used by combine
12683 It is not possible for the destination of the target of the link to
12684 have been changed by combine. The only potential of this is if we
12685 replace I3, I2, and I1 by I3 and I2. But in that case the
12686 destination of I2 also remains unchanged. */
12688 if (GET_CODE (XEXP (link, 0)) == NOTE
12689 || (set = single_set (XEXP (link, 0))) == 0)
12692 reg = SET_DEST (set);
12693 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12694 || GET_CODE (reg) == SIGN_EXTRACT
12695 || GET_CODE (reg) == STRICT_LOW_PART)
12696 reg = XEXP (reg, 0);
12698 /* A LOG_LINK is defined as being placed on the first insn that uses
12699 a register and points to the insn that sets the register. Start
12700 searching at the next insn after the target of the link and stop
12701 when we reach a set of the register or the end of the basic block.
12703 Note that this correctly handles the link that used to point from
12704 I3 to I2. Also note that not much searching is typically done here
12705 since most links don't point very far away. */
12707 for (insn = NEXT_INSN (XEXP (link, 0));
12708 (insn && (this_basic_block == n_basic_blocks - 1
12709 || BLOCK_HEAD (this_basic_block + 1) != insn));
12710 insn = NEXT_INSN (insn))
12711 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12713 if (reg_referenced_p (reg, PATTERN (insn)))
12717 else if (GET_CODE (insn) == CALL_INSN
12718 && find_reg_fusage (insn, USE, reg))
12724 /* If we found a place to put the link, place it there unless there
12725 is already a link to the same insn as LINK at that point. */
12731 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12732 if (XEXP (link2, 0) == XEXP (link, 0))
12737 XEXP (link, 1) = LOG_LINKS (place);
12738 LOG_LINKS (place) = link;
12740 /* Set added_links_insn to the earliest insn we added a
12742 if (added_links_insn == 0
12743 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12744 added_links_insn = place;
12750 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12756 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12757 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12758 insn = NEXT_INSN (insn);
12760 if (INSN_UID (insn) > max_uid_cuid)
12763 return INSN_CUID (insn);
12767 dump_combine_stats (file)
12772 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12773 combine_attempts, combine_merges, combine_extras, combine_successes);
12777 dump_combine_total_stats (file)
12782 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12783 total_attempts, total_merges, total_extras, total_successes);