1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is an insn that belongs before subst_insn, but is not currently
177 on the insn chain. */
179 static rtx subst_prev_insn;
181 /* This is the lowest CUID that `subst' is currently dealing with.
182 get_last_value will not return a value if the register was set at or
183 after this CUID. If not for this mechanism, we could get confused if
184 I2 or I1 in try_combine were an insn that used the old value of a register
185 to obtain a new value. In that case, we might erroneously get the
186 new value of the register when we wanted the old one. */
188 static int subst_low_cuid;
190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
191 must consider all these registers to be always live. */
193 static HARD_REG_SET newpat_used_regs;
195 /* This is an insn to which a LOG_LINKS entry has been added. If this
196 insn is the earlier than I2 or I3, combine should rescan starting at
199 static rtx added_links_insn;
201 /* Basic block in which we are performing combines. */
202 static basic_block this_basic_block;
204 /* A bitmap indicating which blocks had registers go dead at entry.
205 After combine, we'll need to re-do global life analysis with
206 those blocks as starting points. */
207 static sbitmap refresh_blocks;
208 static int need_refresh;
210 /* The next group of arrays allows the recording of the last value assigned
211 to (hard or pseudo) register n. We use this information to see if an
212 operation being processed is redundant given a prior operation performed
213 on the register. For example, an `and' with a constant is redundant if
214 all the zero bits are already known to be turned off.
216 We use an approach similar to that used by cse, but change it in the
219 (1) We do not want to reinitialize at each label.
220 (2) It is useful, but not critical, to know the actual value assigned
221 to a register. Often just its form is helpful.
223 Therefore, we maintain the following arrays:
225 reg_last_set_value the last value assigned
226 reg_last_set_label records the value of label_tick when the
227 register was assigned
228 reg_last_set_table_tick records the value of label_tick when a
229 value using the register is assigned
230 reg_last_set_invalid set to nonzero when it is not valid
231 to use the value of this register in some
234 To understand the usage of these tables, it is important to understand
235 the distinction between the value in reg_last_set_value being valid
236 and the register being validly contained in some other expression in the
239 Entry I in reg_last_set_value is valid if it is nonzero, and either
240 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
242 Register I may validly appear in any expression returned for the value
243 of another register if reg_n_sets[i] is 1. It may also appear in the
244 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
245 reg_last_set_invalid[j] is zero.
247 If an expression is found in the table containing a register which may
248 not validly appear in an expression, the register is replaced by
249 something that won't match, (clobber (const_int 0)).
251 reg_last_set_invalid[i] is set nonzero when register I is being assigned
252 to and reg_last_set_table_tick[i] == label_tick. */
254 /* Record last value assigned to (hard or pseudo) register n. */
256 static rtx *reg_last_set_value;
258 /* Record the value of label_tick when the value for register n is placed in
259 reg_last_set_value[n]. */
261 static int *reg_last_set_label;
263 /* Record the value of label_tick when an expression involving register n
264 is placed in reg_last_set_value. */
266 static int *reg_last_set_table_tick;
268 /* Set nonzero if references to register n in expressions should not be
271 static char *reg_last_set_invalid;
273 /* Incremented for each label. */
275 static int label_tick;
277 /* Some registers that are set more than once and used in more than one
278 basic block are nevertheless always set in similar ways. For example,
279 a QImode register may be loaded from memory in two places on a machine
280 where byte loads zero extend.
282 We record in the following array what we know about the nonzero
283 bits of a register, specifically which bits are known to be zero.
285 If an entry is zero, it means that we don't know anything special. */
287 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
289 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
290 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
292 static enum machine_mode nonzero_bits_mode;
294 /* Nonzero if we know that a register has some leading bits that are always
295 equal to the sign bit. */
297 static unsigned char *reg_sign_bit_copies;
299 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
300 It is zero while computing them and after combine has completed. This
301 former test prevents propagating values based on previously set values,
302 which can be incorrect if a variable is modified in a loop. */
304 static int nonzero_sign_valid;
306 /* These arrays are maintained in parallel with reg_last_set_value
307 and are used to store the mode in which the register was last set,
308 the bits that were known to be zero when it was last set, and the
309 number of sign bits copies it was known to have when it was last set. */
311 static enum machine_mode *reg_last_set_mode;
312 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
313 static char *reg_last_set_sign_bit_copies;
315 /* Record one modification to rtl structure
316 to be undone by storing old_contents into *where.
317 is_int is 1 if the contents are an int. */
323 union {rtx r; int i;} old_contents;
324 union {rtx *r; int *i;} where;
327 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
328 num_undo says how many are currently recorded.
330 other_insn is nonzero if we have modified some other insn in the process
331 of working on subst_insn. It must be verified too. */
340 static struct undobuf undobuf;
342 /* Number of times the pseudo being substituted for
343 was found and replaced. */
345 static int n_occurrences;
347 static void do_SUBST PARAMS ((rtx *, rtx));
348 static void do_SUBST_INT PARAMS ((int *, int));
349 static void init_reg_last_arrays PARAMS ((void));
350 static void setup_incoming_promotions PARAMS ((void));
351 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
352 static int cant_combine_insn_p PARAMS ((rtx));
353 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
354 static int sets_function_arg_p PARAMS ((rtx));
355 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
356 static int contains_muldiv PARAMS ((rtx));
357 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
358 static void undo_all PARAMS ((void));
359 static void undo_commit PARAMS ((void));
360 static rtx *find_split_point PARAMS ((rtx *, rtx));
361 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
362 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
363 static rtx simplify_if_then_else PARAMS ((rtx));
364 static rtx simplify_set PARAMS ((rtx));
365 static rtx simplify_logical PARAMS ((rtx, int));
366 static rtx expand_compound_operation PARAMS ((rtx));
367 static rtx expand_field_assignment PARAMS ((rtx));
368 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
369 rtx, unsigned HOST_WIDE_INT, int,
371 static rtx extract_left_shift PARAMS ((rtx, int));
372 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
373 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
374 unsigned HOST_WIDE_INT *));
375 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
376 unsigned HOST_WIDE_INT, rtx, int));
377 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
378 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
379 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
380 static rtx make_field_assignment PARAMS ((rtx));
381 static rtx apply_distributive_law PARAMS ((rtx));
382 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
383 unsigned HOST_WIDE_INT));
384 static unsigned HOST_WIDE_INT cached_nonzero_bits
385 PARAMS ((rtx, enum machine_mode, rtx,
387 unsigned HOST_WIDE_INT));
388 static unsigned HOST_WIDE_INT nonzero_bits1
389 PARAMS ((rtx, enum machine_mode, rtx,
391 unsigned HOST_WIDE_INT));
392 static unsigned int cached_num_sign_bit_copies
393 PARAMS ((rtx, enum machine_mode, rtx,
394 enum machine_mode, unsigned int));
395 static unsigned int num_sign_bit_copies1
396 PARAMS ((rtx, enum machine_mode, rtx,
397 enum machine_mode, unsigned int));
398 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
399 enum rtx_code, HOST_WIDE_INT,
400 enum machine_mode, int *));
401 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
403 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
404 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
405 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
407 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
408 static void update_table_tick PARAMS ((rtx));
409 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
410 static void check_promoted_subreg PARAMS ((rtx, rtx));
411 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
412 static void record_dead_and_set_regs PARAMS ((rtx));
413 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
414 static rtx get_last_value PARAMS ((rtx));
415 static int use_crosses_set_p PARAMS ((rtx, int));
416 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
417 static int reg_dead_at_p PARAMS ((rtx, rtx));
418 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
419 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
420 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
421 static void distribute_links PARAMS ((rtx));
422 static void mark_used_regs_combine PARAMS ((rtx));
423 static int insn_cuid PARAMS ((rtx));
424 static void record_promoted_value PARAMS ((rtx, rtx));
425 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
426 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
427 static void adjust_for_new_dest PARAMS ((rtx));
429 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
430 insn. The substitution can be undone by undo_all. If INTO is already
431 set to NEWVAL, do not record this change. Because computing NEWVAL might
432 also call SUBST, we have to compute it before we put anything into
436 do_SUBST (into, newval)
442 if (oldval == newval)
445 /* We'd like to catch as many invalid transformations here as
446 possible. Unfortunately, there are way too many mode changes
447 that are perfectly valid, so we'd waste too much effort for
448 little gain doing the checks here. Focus on catching invalid
449 transformations involving integer constants. */
450 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
451 && GET_CODE (newval) == CONST_INT)
453 /* Sanity check that we're replacing oldval with a CONST_INT
454 that is a valid sign-extension for the original mode. */
455 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
459 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
460 CONST_INT is not valid, because after the replacement, the
461 original mode would be gone. Unfortunately, we can't tell
462 when do_SUBST is called to replace the operand thereof, so we
463 perform this test on oldval instead, checking whether an
464 invalid replacement took place before we got here. */
465 if ((GET_CODE (oldval) == SUBREG
466 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
467 || (GET_CODE (oldval) == ZERO_EXTEND
468 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
473 buf = undobuf.frees, undobuf.frees = buf->next;
475 buf = (struct undo *) xmalloc (sizeof (struct undo));
479 buf->old_contents.r = oldval;
482 buf->next = undobuf.undos, undobuf.undos = buf;
485 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
487 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
488 for the value of a HOST_WIDE_INT value (including CONST_INT) is
492 do_SUBST_INT (into, newval)
498 if (oldval == newval)
502 buf = undobuf.frees, undobuf.frees = buf->next;
504 buf = (struct undo *) xmalloc (sizeof (struct undo));
508 buf->old_contents.i = oldval;
511 buf->next = undobuf.undos, undobuf.undos = buf;
514 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
516 /* Main entry point for combiner. F is the first insn of the function.
517 NREGS is the first unused pseudo-reg number.
519 Return nonzero if the combiner has turned an indirect jump
520 instruction into a direct jump. */
522 combine_instructions (f, nregs)
531 rtx links, nextlinks;
533 int new_direct_jump_p = 0;
535 combine_attempts = 0;
538 combine_successes = 0;
540 combine_max_regno = nregs;
542 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
543 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
545 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
547 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
548 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
549 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
550 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
551 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
552 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
554 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
555 reg_last_set_nonzero_bits
556 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
557 reg_last_set_sign_bit_copies
558 = (char *) xmalloc (nregs * sizeof (char));
560 init_reg_last_arrays ();
562 init_recog_no_volatile ();
564 /* Compute maximum uid value so uid_cuid can be allocated. */
566 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
567 if (INSN_UID (insn) > i)
570 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
573 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
575 /* Don't use reg_nonzero_bits when computing it. This can cause problems
576 when, for example, we have j <<= 1 in a loop. */
578 nonzero_sign_valid = 0;
580 /* Compute the mapping from uids to cuids.
581 Cuids are numbers assigned to insns, like uids,
582 except that cuids increase monotonically through the code.
584 Scan all SETs and see if we can deduce anything about what
585 bits are known to be zero for some registers and how many copies
586 of the sign bit are known to exist for those registers.
588 Also set any known values so that we can use it while searching
589 for what bits are known to be set. */
593 /* We need to initialize it here, because record_dead_and_set_regs may call
595 subst_prev_insn = NULL_RTX;
597 setup_incoming_promotions ();
599 refresh_blocks = sbitmap_alloc (last_basic_block);
600 sbitmap_zero (refresh_blocks);
603 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
605 uid_cuid[INSN_UID (insn)] = ++i;
611 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
613 record_dead_and_set_regs (insn);
616 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
617 if (REG_NOTE_KIND (links) == REG_INC)
618 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
623 if (GET_CODE (insn) == CODE_LABEL)
627 nonzero_sign_valid = 1;
629 /* Now scan all the insns in forward order. */
634 init_reg_last_arrays ();
635 setup_incoming_promotions ();
637 FOR_EACH_BB (this_basic_block)
639 for (insn = this_basic_block->head;
640 insn != NEXT_INSN (this_basic_block->end);
641 insn = next ? next : NEXT_INSN (insn))
645 if (GET_CODE (insn) == CODE_LABEL)
648 else if (INSN_P (insn))
650 /* See if we know about function return values before this
651 insn based upon SUBREG flags. */
652 check_promoted_subreg (insn, PATTERN (insn));
654 /* Try this insn with each insn it links back to. */
656 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
657 if ((next = try_combine (insn, XEXP (links, 0),
658 NULL_RTX, &new_direct_jump_p)) != 0)
661 /* Try each sequence of three linked insns ending with this one. */
663 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
665 rtx link = XEXP (links, 0);
667 /* If the linked insn has been replaced by a note, then there
668 is no point in pursuing this chain any further. */
669 if (GET_CODE (link) == NOTE)
672 for (nextlinks = LOG_LINKS (link);
674 nextlinks = XEXP (nextlinks, 1))
675 if ((next = try_combine (insn, link,
677 &new_direct_jump_p)) != 0)
682 /* Try to combine a jump insn that uses CC0
683 with a preceding insn that sets CC0, and maybe with its
684 logical predecessor as well.
685 This is how we make decrement-and-branch insns.
686 We need this special code because data flow connections
687 via CC0 do not get entered in LOG_LINKS. */
689 if (GET_CODE (insn) == JUMP_INSN
690 && (prev = prev_nonnote_insn (insn)) != 0
691 && GET_CODE (prev) == INSN
692 && sets_cc0_p (PATTERN (prev)))
694 if ((next = try_combine (insn, prev,
695 NULL_RTX, &new_direct_jump_p)) != 0)
698 for (nextlinks = LOG_LINKS (prev); nextlinks;
699 nextlinks = XEXP (nextlinks, 1))
700 if ((next = try_combine (insn, prev,
702 &new_direct_jump_p)) != 0)
706 /* Do the same for an insn that explicitly references CC0. */
707 if (GET_CODE (insn) == INSN
708 && (prev = prev_nonnote_insn (insn)) != 0
709 && GET_CODE (prev) == INSN
710 && sets_cc0_p (PATTERN (prev))
711 && GET_CODE (PATTERN (insn)) == SET
712 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
714 if ((next = try_combine (insn, prev,
715 NULL_RTX, &new_direct_jump_p)) != 0)
718 for (nextlinks = LOG_LINKS (prev); nextlinks;
719 nextlinks = XEXP (nextlinks, 1))
720 if ((next = try_combine (insn, prev,
722 &new_direct_jump_p)) != 0)
726 /* Finally, see if any of the insns that this insn links to
727 explicitly references CC0. If so, try this insn, that insn,
728 and its predecessor if it sets CC0. */
729 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
730 if (GET_CODE (XEXP (links, 0)) == INSN
731 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
732 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
733 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
734 && GET_CODE (prev) == INSN
735 && sets_cc0_p (PATTERN (prev))
736 && (next = try_combine (insn, XEXP (links, 0),
737 prev, &new_direct_jump_p)) != 0)
741 /* Try combining an insn with two different insns whose results it
743 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
744 for (nextlinks = XEXP (links, 1); nextlinks;
745 nextlinks = XEXP (nextlinks, 1))
746 if ((next = try_combine (insn, XEXP (links, 0),
748 &new_direct_jump_p)) != 0)
751 if (GET_CODE (insn) != NOTE)
752 record_dead_and_set_regs (insn);
761 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
762 BASIC_BLOCK (i)->flags |= BB_DIRTY);
763 new_direct_jump_p |= purge_all_dead_edges (0);
764 delete_noop_moves (f);
766 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
767 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
768 | PROP_KILL_DEAD_CODE);
771 sbitmap_free (refresh_blocks);
772 free (reg_nonzero_bits);
773 free (reg_sign_bit_copies);
774 free (reg_last_death);
776 free (reg_last_set_value);
777 free (reg_last_set_table_tick);
778 free (reg_last_set_label);
779 free (reg_last_set_invalid);
780 free (reg_last_set_mode);
781 free (reg_last_set_nonzero_bits);
782 free (reg_last_set_sign_bit_copies);
786 struct undo *undo, *next;
787 for (undo = undobuf.frees; undo; undo = next)
795 total_attempts += combine_attempts;
796 total_merges += combine_merges;
797 total_extras += combine_extras;
798 total_successes += combine_successes;
800 nonzero_sign_valid = 0;
802 /* Make recognizer allow volatile MEMs again. */
805 return new_direct_jump_p;
808 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
811 init_reg_last_arrays ()
813 unsigned int nregs = combine_max_regno;
815 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
816 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
817 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
818 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
819 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
820 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
821 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
822 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
823 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
826 /* Set up any promoted values for incoming argument registers. */
829 setup_incoming_promotions ()
831 #ifdef PROMOTE_FUNCTION_ARGS
834 enum machine_mode mode;
836 rtx first = get_insns ();
838 #ifndef OUTGOING_REGNO
839 #define OUTGOING_REGNO(N) N
841 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
842 /* Check whether this register can hold an incoming pointer
843 argument. FUNCTION_ARG_REGNO_P tests outgoing register
844 numbers, so translate if necessary due to register windows. */
845 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
846 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
849 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
852 gen_rtx_CLOBBER (mode, const0_rtx)));
857 /* Called via note_stores. If X is a pseudo that is narrower than
858 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
860 If we are setting only a portion of X and we can't figure out what
861 portion, assume all bits will be used since we don't know what will
864 Similarly, set how many bits of X are known to be copies of the sign bit
865 at all locations in the function. This is the smallest number implied
869 set_nonzero_bits_and_sign_copies (x, set, data)
872 void *data ATTRIBUTE_UNUSED;
876 if (GET_CODE (x) == REG
877 && REGNO (x) >= FIRST_PSEUDO_REGISTER
878 /* If this register is undefined at the start of the file, we can't
879 say what its contents were. */
880 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
881 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
883 if (set == 0 || GET_CODE (set) == CLOBBER)
885 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
886 reg_sign_bit_copies[REGNO (x)] = 1;
890 /* If this is a complex assignment, see if we can convert it into a
891 simple assignment. */
892 set = expand_field_assignment (set);
894 /* If this is a simple assignment, or we have a paradoxical SUBREG,
895 set what we know about X. */
897 if (SET_DEST (set) == x
898 || (GET_CODE (SET_DEST (set)) == SUBREG
899 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
900 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
901 && SUBREG_REG (SET_DEST (set)) == x))
903 rtx src = SET_SRC (set);
905 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
906 /* If X is narrower than a word and SRC is a non-negative
907 constant that would appear negative in the mode of X,
908 sign-extend it for use in reg_nonzero_bits because some
909 machines (maybe most) will actually do the sign-extension
910 and this is the conservative approach.
912 ??? For 2.5, try to tighten up the MD files in this regard
913 instead of this kludge. */
915 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
916 && GET_CODE (src) == CONST_INT
918 && 0 != (INTVAL (src)
920 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
921 src = GEN_INT (INTVAL (src)
922 | ((HOST_WIDE_INT) (-1)
923 << GET_MODE_BITSIZE (GET_MODE (x))));
926 /* Don't call nonzero_bits if it cannot change anything. */
927 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
928 reg_nonzero_bits[REGNO (x)]
929 |= nonzero_bits (src, nonzero_bits_mode);
930 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
931 if (reg_sign_bit_copies[REGNO (x)] == 0
932 || reg_sign_bit_copies[REGNO (x)] > num)
933 reg_sign_bit_copies[REGNO (x)] = num;
937 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
938 reg_sign_bit_copies[REGNO (x)] = 1;
943 /* See if INSN can be combined into I3. PRED and SUCC are optionally
944 insns that were previously combined into I3 or that will be combined
945 into the merger of INSN and I3.
947 Return 0 if the combination is not allowed for any reason.
949 If the combination is allowed, *PDEST will be set to the single
950 destination of INSN and *PSRC to the single source, and this function
954 can_combine_p (insn, i3, pred, succ, pdest, psrc)
957 rtx pred ATTRIBUTE_UNUSED;
962 rtx set = 0, src, dest;
967 int all_adjacent = (succ ? (next_active_insn (insn) == succ
968 && next_active_insn (succ) == i3)
969 : next_active_insn (insn) == i3);
971 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
972 or a PARALLEL consisting of such a SET and CLOBBERs.
974 If INSN has CLOBBER parallel parts, ignore them for our processing.
975 By definition, these happen during the execution of the insn. When it
976 is merged with another insn, all bets are off. If they are, in fact,
977 needed and aren't also supplied in I3, they may be added by
978 recog_for_combine. Otherwise, it won't match.
980 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
983 Get the source and destination of INSN. If more than one, can't
986 if (GET_CODE (PATTERN (insn)) == SET)
987 set = PATTERN (insn);
988 else if (GET_CODE (PATTERN (insn)) == PARALLEL
989 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
991 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
993 rtx elt = XVECEXP (PATTERN (insn), 0, i);
995 switch (GET_CODE (elt))
997 /* This is important to combine floating point insns
1000 /* Combining an isolated USE doesn't make sense.
1001 We depend here on combinable_i3pat to reject them. */
1002 /* The code below this loop only verifies that the inputs of
1003 the SET in INSN do not change. We call reg_set_between_p
1004 to verify that the REG in the USE does not change between
1006 If the USE in INSN was for a pseudo register, the matching
1007 insn pattern will likely match any register; combining this
1008 with any other USE would only be safe if we knew that the
1009 used registers have identical values, or if there was
1010 something to tell them apart, e.g. different modes. For
1011 now, we forgo such complicated tests and simply disallow
1012 combining of USES of pseudo registers with any other USE. */
1013 if (GET_CODE (XEXP (elt, 0)) == REG
1014 && GET_CODE (PATTERN (i3)) == PARALLEL)
1016 rtx i3pat = PATTERN (i3);
1017 int i = XVECLEN (i3pat, 0) - 1;
1018 unsigned int regno = REGNO (XEXP (elt, 0));
1022 rtx i3elt = XVECEXP (i3pat, 0, i);
1024 if (GET_CODE (i3elt) == USE
1025 && GET_CODE (XEXP (i3elt, 0)) == REG
1026 && (REGNO (XEXP (i3elt, 0)) == regno
1027 ? reg_set_between_p (XEXP (elt, 0),
1028 PREV_INSN (insn), i3)
1029 : regno >= FIRST_PSEUDO_REGISTER))
1036 /* We can ignore CLOBBERs. */
1041 /* Ignore SETs whose result isn't used but not those that
1042 have side-effects. */
1043 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1044 && ! side_effects_p (elt))
1047 /* If we have already found a SET, this is a second one and
1048 so we cannot combine with this insn. */
1056 /* Anything else means we can't combine. */
1062 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1063 so don't do anything with it. */
1064 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1073 set = expand_field_assignment (set);
1074 src = SET_SRC (set), dest = SET_DEST (set);
1076 /* Don't eliminate a store in the stack pointer. */
1077 if (dest == stack_pointer_rtx
1078 /* If we couldn't eliminate a field assignment, we can't combine. */
1079 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1080 /* Don't combine with an insn that sets a register to itself if it has
1081 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1082 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1083 /* Can't merge an ASM_OPERANDS. */
1084 || GET_CODE (src) == ASM_OPERANDS
1085 /* Can't merge a function call. */
1086 || GET_CODE (src) == CALL
1087 /* Don't eliminate a function call argument. */
1088 || (GET_CODE (i3) == CALL_INSN
1089 && (find_reg_fusage (i3, USE, dest)
1090 || (GET_CODE (dest) == REG
1091 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1092 && global_regs[REGNO (dest)])))
1093 /* Don't substitute into an incremented register. */
1094 || FIND_REG_INC_NOTE (i3, dest)
1095 || (succ && FIND_REG_INC_NOTE (succ, dest))
1097 /* Don't combine the end of a libcall into anything. */
1098 /* ??? This gives worse code, and appears to be unnecessary, since no
1099 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1100 use REG_RETVAL notes for noconflict blocks, but other code here
1101 makes sure that those insns don't disappear. */
1102 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1104 /* Make sure that DEST is not used after SUCC but before I3. */
1105 || (succ && ! all_adjacent
1106 && reg_used_between_p (dest, succ, i3))
1107 /* Make sure that the value that is to be substituted for the register
1108 does not use any registers whose values alter in between. However,
1109 If the insns are adjacent, a use can't cross a set even though we
1110 think it might (this can happen for a sequence of insns each setting
1111 the same destination; reg_last_set of that register might point to
1112 a NOTE). If INSN has a REG_EQUIV note, the register is always
1113 equivalent to the memory so the substitution is valid even if there
1114 are intervening stores. Also, don't move a volatile asm or
1115 UNSPEC_VOLATILE across any other insns. */
1117 && (((GET_CODE (src) != MEM
1118 || ! find_reg_note (insn, REG_EQUIV, src))
1119 && use_crosses_set_p (src, INSN_CUID (insn)))
1120 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1121 || GET_CODE (src) == UNSPEC_VOLATILE))
1122 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1123 better register allocation by not doing the combine. */
1124 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1125 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1126 /* Don't combine across a CALL_INSN, because that would possibly
1127 change whether the life span of some REGs crosses calls or not,
1128 and it is a pain to update that information.
1129 Exception: if source is a constant, moving it later can't hurt.
1130 Accept that special case, because it helps -fforce-addr a lot. */
1131 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1134 /* DEST must either be a REG or CC0. */
1135 if (GET_CODE (dest) == REG)
1137 /* If register alignment is being enforced for multi-word items in all
1138 cases except for parameters, it is possible to have a register copy
1139 insn referencing a hard register that is not allowed to contain the
1140 mode being copied and which would not be valid as an operand of most
1141 insns. Eliminate this problem by not combining with such an insn.
1143 Also, on some machines we don't want to extend the life of a hard
1146 if (GET_CODE (src) == REG
1147 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1148 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1149 /* Don't extend the life of a hard register unless it is
1150 user variable (if we have few registers) or it can't
1151 fit into the desired register (meaning something special
1153 Also avoid substituting a return register into I3, because
1154 reload can't handle a conflict with constraints of other
1156 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1157 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1160 else if (GET_CODE (dest) != CC0)
1163 /* Don't substitute for a register intended as a clobberable operand.
1164 Similarly, don't substitute an expression containing a register that
1165 will be clobbered in I3. */
1166 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1167 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1168 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1169 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1171 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1174 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1175 or not), reject, unless nothing volatile comes between it and I3 */
1177 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1179 /* Make sure succ doesn't contain a volatile reference. */
1180 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1183 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1184 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1188 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1189 to be an explicit register variable, and was chosen for a reason. */
1191 if (GET_CODE (src) == ASM_OPERANDS
1192 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1195 /* If there are any volatile insns between INSN and I3, reject, because
1196 they might affect machine state. */
1198 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1199 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1202 /* If INSN or I2 contains an autoincrement or autodecrement,
1203 make sure that register is not used between there and I3,
1204 and not already used in I3 either.
1205 Also insist that I3 not be a jump; if it were one
1206 and the incremented register were spilled, we would lose. */
1209 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1210 if (REG_NOTE_KIND (link) == REG_INC
1211 && (GET_CODE (i3) == JUMP_INSN
1212 || reg_used_between_p (XEXP (link, 0), insn, i3)
1213 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1218 /* Don't combine an insn that follows a CC0-setting insn.
1219 An insn that uses CC0 must not be separated from the one that sets it.
1220 We do, however, allow I2 to follow a CC0-setting insn if that insn
1221 is passed as I1; in that case it will be deleted also.
1222 We also allow combining in this case if all the insns are adjacent
1223 because that would leave the two CC0 insns adjacent as well.
1224 It would be more logical to test whether CC0 occurs inside I1 or I2,
1225 but that would be much slower, and this ought to be equivalent. */
1227 p = prev_nonnote_insn (insn);
1228 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1233 /* If we get here, we have passed all the tests and the combination is
1242 /* Check if PAT is an insn - or a part of it - used to set up an
1243 argument for a function in a hard register. */
1246 sets_function_arg_p (pat)
1252 switch (GET_CODE (pat))
1255 return sets_function_arg_p (PATTERN (pat));
1258 for (i = XVECLEN (pat, 0); --i >= 0;)
1259 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1265 inner_dest = SET_DEST (pat);
1266 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1267 || GET_CODE (inner_dest) == SUBREG
1268 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1269 inner_dest = XEXP (inner_dest, 0);
1271 return (GET_CODE (inner_dest) == REG
1272 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1273 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1282 /* LOC is the location within I3 that contains its pattern or the component
1283 of a PARALLEL of the pattern. We validate that it is valid for combining.
1285 One problem is if I3 modifies its output, as opposed to replacing it
1286 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1287 so would produce an insn that is not equivalent to the original insns.
1291 (set (reg:DI 101) (reg:DI 100))
1292 (set (subreg:SI (reg:DI 101) 0) <foo>)
1294 This is NOT equivalent to:
1296 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1297 (set (reg:DI 101) (reg:DI 100))])
1299 Not only does this modify 100 (in which case it might still be valid
1300 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1302 We can also run into a problem if I2 sets a register that I1
1303 uses and I1 gets directly substituted into I3 (not via I2). In that
1304 case, we would be getting the wrong value of I2DEST into I3, so we
1305 must reject the combination. This case occurs when I2 and I1 both
1306 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1307 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1308 of a SET must prevent combination from occurring.
1310 Before doing the above check, we first try to expand a field assignment
1311 into a set of logical operations.
1313 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1314 we place a register that is both set and used within I3. If more than one
1315 such register is detected, we fail.
1317 Return 1 if the combination is valid, zero otherwise. */
1320 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1326 rtx *pi3dest_killed;
1330 if (GET_CODE (x) == SET)
1332 rtx set = expand_field_assignment (x);
1333 rtx dest = SET_DEST (set);
1334 rtx src = SET_SRC (set);
1335 rtx inner_dest = dest;
1338 rtx inner_src = src;
1343 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1344 || GET_CODE (inner_dest) == SUBREG
1345 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1346 inner_dest = XEXP (inner_dest, 0);
1348 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1351 while (GET_CODE (inner_src) == STRICT_LOW_PART
1352 || GET_CODE (inner_src) == SUBREG
1353 || GET_CODE (inner_src) == ZERO_EXTRACT)
1354 inner_src = XEXP (inner_src, 0);
1356 /* If it is better that two different modes keep two different pseudos,
1357 avoid combining them. This avoids producing the following pattern
1359 (set (subreg:SI (reg/v:QI 21) 0)
1360 (lshiftrt:SI (reg/v:SI 20)
1362 If that were made, reload could not handle the pair of
1363 reg 20/21, since it would try to get any GENERAL_REGS
1364 but some of them don't handle QImode. */
1366 if (rtx_equal_p (inner_src, i2dest)
1367 && GET_CODE (inner_dest) == REG
1368 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1372 /* Check for the case where I3 modifies its output, as
1374 if ((inner_dest != dest
1375 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1376 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1378 /* This is the same test done in can_combine_p except we can't test
1379 all_adjacent; we don't have to, since this instruction will stay
1380 in place, thus we are not considering increasing the lifetime of
1383 Also, if this insn sets a function argument, combining it with
1384 something that might need a spill could clobber a previous
1385 function argument; the all_adjacent test in can_combine_p also
1386 checks this; here, we do a more specific test for this case. */
1388 || (GET_CODE (inner_dest) == REG
1389 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1390 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1391 GET_MODE (inner_dest))))
1392 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1395 /* If DEST is used in I3, it is being killed in this insn,
1396 so record that for later.
1397 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1398 STACK_POINTER_REGNUM, since these are always considered to be
1399 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1400 if (pi3dest_killed && GET_CODE (dest) == REG
1401 && reg_referenced_p (dest, PATTERN (i3))
1402 && REGNO (dest) != FRAME_POINTER_REGNUM
1403 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1404 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1406 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1407 && (REGNO (dest) != ARG_POINTER_REGNUM
1408 || ! fixed_regs [REGNO (dest)])
1410 && REGNO (dest) != STACK_POINTER_REGNUM)
1412 if (*pi3dest_killed)
1415 *pi3dest_killed = dest;
1419 else if (GET_CODE (x) == PARALLEL)
1423 for (i = 0; i < XVECLEN (x, 0); i++)
1424 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1425 i1_not_in_src, pi3dest_killed))
1432 /* Return 1 if X is an arithmetic expression that contains a multiplication
1433 and division. We don't count multiplications by powers of two here. */
1439 switch (GET_CODE (x))
1441 case MOD: case DIV: case UMOD: case UDIV:
1445 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1446 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1448 switch (GET_RTX_CLASS (GET_CODE (x)))
1450 case 'c': case '<': case '2':
1451 return contains_muldiv (XEXP (x, 0))
1452 || contains_muldiv (XEXP (x, 1));
1455 return contains_muldiv (XEXP (x, 0));
1463 /* Determine whether INSN can be used in a combination. Return nonzero if
1464 not. This is used in try_combine to detect early some cases where we
1465 can't perform combinations. */
1468 cant_combine_insn_p (insn)
1474 /* If this isn't really an insn, we can't do anything.
1475 This can occur when flow deletes an insn that it has merged into an
1476 auto-increment address. */
1477 if (! INSN_P (insn))
1480 /* Never combine loads and stores involving hard regs. The register
1481 allocator can usually handle such reg-reg moves by tying. If we allow
1482 the combiner to make substitutions of hard regs, we risk aborting in
1483 reload on machines that have SMALL_REGISTER_CLASSES.
1484 As an exception, we allow combinations involving fixed regs; these are
1485 not available to the register allocator so there's no risk involved. */
1487 set = single_set (insn);
1490 src = SET_SRC (set);
1491 dest = SET_DEST (set);
1492 if (GET_CODE (src) == SUBREG)
1493 src = SUBREG_REG (src);
1494 if (GET_CODE (dest) == SUBREG)
1495 dest = SUBREG_REG (dest);
1496 if (REG_P (src) && REG_P (dest)
1497 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1498 && ! fixed_regs[REGNO (src)])
1499 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1500 && ! fixed_regs[REGNO (dest)])))
1506 /* Adjust INSN after we made a change to its destination.
1508 Changing the destination can invalidate notes that say something about
1509 the results of the insn and a LOG_LINK pointing to the insn. */
1512 adjust_for_new_dest (insn)
1517 /* For notes, be conservative and simply remove them. */
1518 loc = ®_NOTES (insn);
1521 enum reg_note kind = REG_NOTE_KIND (*loc);
1522 if (kind == REG_EQUAL || kind == REG_EQUIV)
1523 *loc = XEXP (*loc, 1);
1525 loc = &XEXP (*loc, 1);
1528 /* The new insn will have a destination that was previously the destination
1529 of an insn just above it. Call distribute_links to make a LOG_LINK from
1530 the next use of that destination. */
1531 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1534 /* Try to combine the insns I1 and I2 into I3.
1535 Here I1 and I2 appear earlier than I3.
1536 I1 can be zero; then we combine just I2 into I3.
1538 If we are combining three insns and the resulting insn is not recognized,
1539 try splitting it into two insns. If that happens, I2 and I3 are retained
1540 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1543 Return 0 if the combination does not work. Then nothing is changed.
1544 If we did the combination, return the insn at which combine should
1547 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1548 new direct jump instruction. */
1551 try_combine (i3, i2, i1, new_direct_jump_p)
1553 int *new_direct_jump_p;
1555 /* New patterns for I3 and I2, respectively. */
1556 rtx newpat, newi2pat = 0;
1557 int substed_i2 = 0, substed_i1 = 0;
1558 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1559 int added_sets_1, added_sets_2;
1560 /* Total number of SETs to put into I3. */
1562 /* Nonzero is I2's body now appears in I3. */
1564 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1565 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1566 /* Contains I3 if the destination of I3 is used in its source, which means
1567 that the old life of I3 is being killed. If that usage is placed into
1568 I2 and not in I3, a REG_DEAD note must be made. */
1569 rtx i3dest_killed = 0;
1570 /* SET_DEST and SET_SRC of I2 and I1. */
1571 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1572 /* PATTERN (I2), or a copy of it in certain cases. */
1574 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1575 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1576 int i1_feeds_i3 = 0;
1577 /* Notes that must be added to REG_NOTES in I3 and I2. */
1578 rtx new_i3_notes, new_i2_notes;
1579 /* Notes that we substituted I3 into I2 instead of the normal case. */
1580 int i3_subst_into_i2 = 0;
1581 /* Notes that I1, I2 or I3 is a MULT operation. */
1589 /* Exit early if one of the insns involved can't be used for
1591 if (cant_combine_insn_p (i3)
1592 || cant_combine_insn_p (i2)
1593 || (i1 && cant_combine_insn_p (i1))
1594 /* We also can't do anything if I3 has a
1595 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1598 /* ??? This gives worse code, and appears to be unnecessary, since no
1599 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1600 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1606 undobuf.other_insn = 0;
1608 /* Reset the hard register usage information. */
1609 CLEAR_HARD_REG_SET (newpat_used_regs);
1611 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1612 code below, set I1 to be the earlier of the two insns. */
1613 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1614 temp = i1, i1 = i2, i2 = temp;
1616 added_links_insn = 0;
1618 /* First check for one important special-case that the code below will
1619 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1620 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1621 we may be able to replace that destination with the destination of I3.
1622 This occurs in the common code where we compute both a quotient and
1623 remainder into a structure, in which case we want to do the computation
1624 directly into the structure to avoid register-register copies.
1626 Note that this case handles both multiple sets in I2 and also
1627 cases where I2 has a number of CLOBBER or PARALLELs.
1629 We make very conservative checks below and only try to handle the
1630 most common cases of this. For example, we only handle the case
1631 where I2 and I3 are adjacent to avoid making difficult register
1634 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1635 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1636 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1637 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1638 && GET_CODE (PATTERN (i2)) == PARALLEL
1639 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1640 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1641 below would need to check what is inside (and reg_overlap_mentioned_p
1642 doesn't support those codes anyway). Don't allow those destinations;
1643 the resulting insn isn't likely to be recognized anyway. */
1644 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1645 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1646 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1647 SET_DEST (PATTERN (i3)))
1648 && next_real_insn (i2) == i3)
1650 rtx p2 = PATTERN (i2);
1652 /* Make sure that the destination of I3,
1653 which we are going to substitute into one output of I2,
1654 is not used within another output of I2. We must avoid making this:
1655 (parallel [(set (mem (reg 69)) ...)
1656 (set (reg 69) ...)])
1657 which is not well-defined as to order of actions.
1658 (Besides, reload can't handle output reloads for this.)
1660 The problem can also happen if the dest of I3 is a memory ref,
1661 if another dest in I2 is an indirect memory ref. */
1662 for (i = 0; i < XVECLEN (p2, 0); i++)
1663 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1664 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1665 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1666 SET_DEST (XVECEXP (p2, 0, i))))
1669 if (i == XVECLEN (p2, 0))
1670 for (i = 0; i < XVECLEN (p2, 0); i++)
1671 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1672 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1673 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1678 subst_low_cuid = INSN_CUID (i2);
1680 added_sets_2 = added_sets_1 = 0;
1681 i2dest = SET_SRC (PATTERN (i3));
1683 /* Replace the dest in I2 with our dest and make the resulting
1684 insn the new pattern for I3. Then skip to where we
1685 validate the pattern. Everything was set up above. */
1686 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1687 SET_DEST (PATTERN (i3)));
1690 i3_subst_into_i2 = 1;
1691 goto validate_replacement;
1695 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1696 one of those words to another constant, merge them by making a new
1699 && (temp = single_set (i2)) != 0
1700 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1701 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1702 && GET_CODE (SET_DEST (temp)) == REG
1703 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1704 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1705 && GET_CODE (PATTERN (i3)) == SET
1706 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1707 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1708 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1709 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1710 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1712 HOST_WIDE_INT lo, hi;
1714 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1715 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1718 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1719 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1722 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1724 /* We don't handle the case of the target word being wider
1725 than a host wide int. */
1726 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1729 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1730 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1731 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1733 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1734 hi = INTVAL (SET_SRC (PATTERN (i3)));
1735 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1737 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1738 >> (HOST_BITS_PER_WIDE_INT - 1));
1740 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1741 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1742 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1743 (INTVAL (SET_SRC (PATTERN (i3)))));
1745 hi = lo < 0 ? -1 : 0;
1748 /* We don't handle the case of the higher word not fitting
1749 entirely in either hi or lo. */
1754 subst_low_cuid = INSN_CUID (i2);
1755 added_sets_2 = added_sets_1 = 0;
1756 i2dest = SET_DEST (temp);
1758 SUBST (SET_SRC (temp),
1759 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1761 newpat = PATTERN (i2);
1762 goto validate_replacement;
1766 /* If we have no I1 and I2 looks like:
1767 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1769 make up a dummy I1 that is
1772 (set (reg:CC X) (compare:CC Y (const_int 0)))
1774 (We can ignore any trailing CLOBBERs.)
1776 This undoes a previous combination and allows us to match a branch-and-
1779 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1780 && XVECLEN (PATTERN (i2), 0) >= 2
1781 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1782 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1784 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1785 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1786 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1787 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1788 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1789 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1791 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1792 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1797 /* We make I1 with the same INSN_UID as I2. This gives it
1798 the same INSN_CUID for value tracking. Our fake I1 will
1799 never appear in the insn stream so giving it the same INSN_UID
1800 as I2 will not cause a problem. */
1802 subst_prev_insn = i1
1803 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1804 BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
1805 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1808 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1809 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1810 SET_DEST (PATTERN (i1)));
1815 /* Verify that I2 and I1 are valid for combining. */
1816 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1817 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1823 /* Record whether I2DEST is used in I2SRC and similarly for the other
1824 cases. Knowing this will help in register status updating below. */
1825 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1826 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1827 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1829 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1831 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1833 /* Ensure that I3's pattern can be the destination of combines. */
1834 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1835 i1 && i2dest_in_i1src && i1_feeds_i3,
1842 /* See if any of the insns is a MULT operation. Unless one is, we will
1843 reject a combination that is, since it must be slower. Be conservative
1845 if (GET_CODE (i2src) == MULT
1846 || (i1 != 0 && GET_CODE (i1src) == MULT)
1847 || (GET_CODE (PATTERN (i3)) == SET
1848 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1851 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1852 We used to do this EXCEPT in one case: I3 has a post-inc in an
1853 output operand. However, that exception can give rise to insns like
1855 which is a famous insn on the PDP-11 where the value of r3 used as the
1856 source was model-dependent. Avoid this sort of thing. */
1859 if (!(GET_CODE (PATTERN (i3)) == SET
1860 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1861 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1862 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1863 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1864 /* It's not the exception. */
1867 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1868 if (REG_NOTE_KIND (link) == REG_INC
1869 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1871 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1878 /* See if the SETs in I1 or I2 need to be kept around in the merged
1879 instruction: whenever the value set there is still needed past I3.
1880 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1882 For the SET in I1, we have two cases: If I1 and I2 independently
1883 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1884 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1885 in I1 needs to be kept around unless I1DEST dies or is set in either
1886 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1887 I1DEST. If so, we know I1 feeds into I2. */
1889 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1892 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1893 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1895 /* If the set in I2 needs to be kept around, we must make a copy of
1896 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1897 PATTERN (I2), we are only substituting for the original I1DEST, not into
1898 an already-substituted copy. This also prevents making self-referential
1899 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1902 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1903 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1907 i2pat = copy_rtx (i2pat);
1911 /* Substitute in the latest insn for the regs set by the earlier ones. */
1913 maxreg = max_reg_num ();
1917 /* It is possible that the source of I2 or I1 may be performing an
1918 unneeded operation, such as a ZERO_EXTEND of something that is known
1919 to have the high part zero. Handle that case by letting subst look at
1920 the innermost one of them.
1922 Another way to do this would be to have a function that tries to
1923 simplify a single insn instead of merging two or more insns. We don't
1924 do this because of the potential of infinite loops and because
1925 of the potential extra memory required. However, doing it the way
1926 we are is a bit of a kludge and doesn't catch all cases.
1928 But only do this if -fexpensive-optimizations since it slows things down
1929 and doesn't usually win. */
1931 if (flag_expensive_optimizations)
1933 /* Pass pc_rtx so no substitutions are done, just simplifications.
1934 The cases that we are interested in here do not involve the few
1935 cases were is_replaced is checked. */
1938 subst_low_cuid = INSN_CUID (i1);
1939 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1943 subst_low_cuid = INSN_CUID (i2);
1944 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1949 /* Many machines that don't use CC0 have insns that can both perform an
1950 arithmetic operation and set the condition code. These operations will
1951 be represented as a PARALLEL with the first element of the vector
1952 being a COMPARE of an arithmetic operation with the constant zero.
1953 The second element of the vector will set some pseudo to the result
1954 of the same arithmetic operation. If we simplify the COMPARE, we won't
1955 match such a pattern and so will generate an extra insn. Here we test
1956 for this case, where both the comparison and the operation result are
1957 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1958 I2SRC. Later we will make the PARALLEL that contains I2. */
1960 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1961 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1962 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1963 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1965 #ifdef EXTRA_CC_MODES
1967 enum machine_mode compare_mode;
1970 newpat = PATTERN (i3);
1971 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1975 #ifdef EXTRA_CC_MODES
1976 /* See if a COMPARE with the operand we substituted in should be done
1977 with the mode that is currently being used. If not, do the same
1978 processing we do in `subst' for a SET; namely, if the destination
1979 is used only once, try to replace it with a register of the proper
1980 mode and also replace the COMPARE. */
1981 if (undobuf.other_insn == 0
1982 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1983 &undobuf.other_insn))
1984 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1986 != GET_MODE (SET_DEST (newpat))))
1988 unsigned int regno = REGNO (SET_DEST (newpat));
1989 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1991 if (regno < FIRST_PSEUDO_REGISTER
1992 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1993 && ! REG_USERVAR_P (SET_DEST (newpat))))
1995 if (regno >= FIRST_PSEUDO_REGISTER)
1996 SUBST (regno_reg_rtx[regno], new_dest);
1998 SUBST (SET_DEST (newpat), new_dest);
1999 SUBST (XEXP (*cc_use, 0), new_dest);
2000 SUBST (SET_SRC (newpat),
2001 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2004 undobuf.other_insn = 0;
2011 n_occurrences = 0; /* `subst' counts here */
2013 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2014 need to make a unique copy of I2SRC each time we substitute it
2015 to avoid self-referential rtl. */
2017 subst_low_cuid = INSN_CUID (i2);
2018 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2019 ! i1_feeds_i3 && i1dest_in_i1src);
2022 /* Record whether i2's body now appears within i3's body. */
2023 i2_is_used = n_occurrences;
2026 /* If we already got a failure, don't try to do more. Otherwise,
2027 try to substitute in I1 if we have it. */
2029 if (i1 && GET_CODE (newpat) != CLOBBER)
2031 /* Before we can do this substitution, we must redo the test done
2032 above (see detailed comments there) that ensures that I1DEST
2033 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2035 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2043 subst_low_cuid = INSN_CUID (i1);
2044 newpat = subst (newpat, i1dest, i1src, 0, 0);
2048 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2049 to count all the ways that I2SRC and I1SRC can be used. */
2050 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2051 && i2_is_used + added_sets_2 > 1)
2052 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2053 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2055 /* Fail if we tried to make a new register (we used to abort, but there's
2056 really no reason to). */
2057 || max_reg_num () != maxreg
2058 /* Fail if we couldn't do something and have a CLOBBER. */
2059 || GET_CODE (newpat) == CLOBBER
2060 /* Fail if this new pattern is a MULT and we didn't have one before
2061 at the outer level. */
2062 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2069 /* If the actions of the earlier insns must be kept
2070 in addition to substituting them into the latest one,
2071 we must make a new PARALLEL for the latest insn
2072 to hold additional the SETs. */
2074 if (added_sets_1 || added_sets_2)
2078 if (GET_CODE (newpat) == PARALLEL)
2080 rtvec old = XVEC (newpat, 0);
2081 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2082 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2083 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2084 sizeof (old->elem[0]) * old->num_elem);
2089 total_sets = 1 + added_sets_1 + added_sets_2;
2090 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2091 XVECEXP (newpat, 0, 0) = old;
2095 XVECEXP (newpat, 0, --total_sets)
2096 = (GET_CODE (PATTERN (i1)) == PARALLEL
2097 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2101 /* If there is no I1, use I2's body as is. We used to also not do
2102 the subst call below if I2 was substituted into I3,
2103 but that could lose a simplification. */
2105 XVECEXP (newpat, 0, --total_sets) = i2pat;
2107 /* See comment where i2pat is assigned. */
2108 XVECEXP (newpat, 0, --total_sets)
2109 = subst (i2pat, i1dest, i1src, 0, 0);
2113 /* We come here when we are replacing a destination in I2 with the
2114 destination of I3. */
2115 validate_replacement:
2117 /* Note which hard regs this insn has as inputs. */
2118 mark_used_regs_combine (newpat);
2120 /* Is the result of combination a valid instruction? */
2121 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2123 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2124 the second SET's destination is a register that is unused. In that case,
2125 we just need the first SET. This can occur when simplifying a divmod
2126 insn. We *must* test for this case here because the code below that
2127 splits two independent SETs doesn't handle this case correctly when it
2128 updates the register status. Also check the case where the first
2129 SET's destination is unused. That would not cause incorrect code, but
2130 does cause an unneeded insn to remain. */
2132 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2133 && XVECLEN (newpat, 0) == 2
2134 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2135 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2136 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2137 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2138 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2139 && asm_noperands (newpat) < 0)
2141 newpat = XVECEXP (newpat, 0, 0);
2142 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2145 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2146 && XVECLEN (newpat, 0) == 2
2147 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2148 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2149 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2150 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2151 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2152 && asm_noperands (newpat) < 0)
2154 newpat = XVECEXP (newpat, 0, 1);
2155 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2157 if (insn_code_number >= 0)
2159 /* If we will be able to accept this, we have made a change to the
2160 destination of I3. This requires us to do a few adjustments. */
2161 PATTERN (i3) = newpat;
2162 adjust_for_new_dest (i3);
2166 /* If we were combining three insns and the result is a simple SET
2167 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2168 insns. There are two ways to do this. It can be split using a
2169 machine-specific method (like when you have an addition of a large
2170 constant) or by combine in the function find_split_point. */
2172 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2173 && asm_noperands (newpat) < 0)
2175 rtx m_split, *split;
2176 rtx ni2dest = i2dest;
2178 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2179 use I2DEST as a scratch register will help. In the latter case,
2180 convert I2DEST to the mode of the source of NEWPAT if we can. */
2182 m_split = split_insns (newpat, i3);
2184 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2185 inputs of NEWPAT. */
2187 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2188 possible to try that as a scratch reg. This would require adding
2189 more code to make it work though. */
2191 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2193 /* If I2DEST is a hard register or the only use of a pseudo,
2194 we can change its mode. */
2195 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2196 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2197 && GET_CODE (i2dest) == REG
2198 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2199 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2200 && ! REG_USERVAR_P (i2dest))))
2201 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2204 m_split = split_insns (gen_rtx_PARALLEL
2206 gen_rtvec (2, newpat,
2207 gen_rtx_CLOBBER (VOIDmode,
2210 /* If the split with the mode-changed register didn't work, try
2211 the original register. */
2212 if (! m_split && ni2dest != i2dest)
2215 m_split = split_insns (gen_rtx_PARALLEL
2217 gen_rtvec (2, newpat,
2218 gen_rtx_CLOBBER (VOIDmode,
2224 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2226 m_split = PATTERN (m_split);
2227 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2228 if (insn_code_number >= 0)
2231 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2232 && (next_real_insn (i2) == i3
2233 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2236 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2237 newi2pat = PATTERN (m_split);
2239 i3set = single_set (NEXT_INSN (m_split));
2240 i2set = single_set (m_split);
2242 /* In case we changed the mode of I2DEST, replace it in the
2243 pseudo-register table here. We can't do it above in case this
2244 code doesn't get executed and we do a split the other way. */
2246 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2247 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2249 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2251 /* If I2 or I3 has multiple SETs, we won't know how to track
2252 register status, so don't use these insns. If I2's destination
2253 is used between I2 and I3, we also can't use these insns. */
2255 if (i2_code_number >= 0 && i2set && i3set
2256 && (next_real_insn (i2) == i3
2257 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2258 insn_code_number = recog_for_combine (&newi3pat, i3,
2260 if (insn_code_number >= 0)
2263 /* It is possible that both insns now set the destination of I3.
2264 If so, we must show an extra use of it. */
2266 if (insn_code_number >= 0)
2268 rtx new_i3_dest = SET_DEST (i3set);
2269 rtx new_i2_dest = SET_DEST (i2set);
2271 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2272 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2273 || GET_CODE (new_i3_dest) == SUBREG)
2274 new_i3_dest = XEXP (new_i3_dest, 0);
2276 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2277 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2278 || GET_CODE (new_i2_dest) == SUBREG)
2279 new_i2_dest = XEXP (new_i2_dest, 0);
2281 if (GET_CODE (new_i3_dest) == REG
2282 && GET_CODE (new_i2_dest) == REG
2283 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2284 REG_N_SETS (REGNO (new_i2_dest))++;
2288 /* If we can split it and use I2DEST, go ahead and see if that
2289 helps things be recognized. Verify that none of the registers
2290 are set between I2 and I3. */
2291 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2293 && GET_CODE (i2dest) == REG
2295 /* We need I2DEST in the proper mode. If it is a hard register
2296 or the only use of a pseudo, we can change its mode. */
2297 && (GET_MODE (*split) == GET_MODE (i2dest)
2298 || GET_MODE (*split) == VOIDmode
2299 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2300 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2301 && ! REG_USERVAR_P (i2dest)))
2302 && (next_real_insn (i2) == i3
2303 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2304 /* We can't overwrite I2DEST if its value is still used by
2306 && ! reg_referenced_p (i2dest, newpat))
2308 rtx newdest = i2dest;
2309 enum rtx_code split_code = GET_CODE (*split);
2310 enum machine_mode split_mode = GET_MODE (*split);
2312 /* Get NEWDEST as a register in the proper mode. We have already
2313 validated that we can do this. */
2314 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2316 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2318 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2319 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2322 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2323 an ASHIFT. This can occur if it was inside a PLUS and hence
2324 appeared to be a memory address. This is a kludge. */
2325 if (split_code == MULT
2326 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2327 && INTVAL (XEXP (*split, 1)) > 0
2328 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2330 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2331 XEXP (*split, 0), GEN_INT (i)));
2332 /* Update split_code because we may not have a multiply
2334 split_code = GET_CODE (*split);
2337 #ifdef INSN_SCHEDULING
2338 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2339 be written as a ZERO_EXTEND. */
2340 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2342 #ifdef LOAD_EXTEND_OP
2343 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2344 what it really is. */
2345 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2347 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2348 SUBREG_REG (*split)));
2351 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2352 SUBREG_REG (*split)));
2356 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2357 SUBST (*split, newdest);
2358 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2360 /* If the split point was a MULT and we didn't have one before,
2361 don't use one now. */
2362 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2363 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2367 /* Check for a case where we loaded from memory in a narrow mode and
2368 then sign extended it, but we need both registers. In that case,
2369 we have a PARALLEL with both loads from the same memory location.
2370 We can split this into a load from memory followed by a register-register
2371 copy. This saves at least one insn, more if register allocation can
2374 We cannot do this if the destination of the first assignment is a
2375 condition code register or cc0. We eliminate this case by making sure
2376 the SET_DEST and SET_SRC have the same mode.
2378 We cannot do this if the destination of the second assignment is
2379 a register that we have already assumed is zero-extended. Similarly
2380 for a SUBREG of such a register. */
2382 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2383 && GET_CODE (newpat) == PARALLEL
2384 && XVECLEN (newpat, 0) == 2
2385 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2386 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2387 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2388 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2389 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2390 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2391 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2392 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2394 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2395 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2396 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2397 (GET_CODE (temp) == REG
2398 && reg_nonzero_bits[REGNO (temp)] != 0
2399 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2400 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2401 && (reg_nonzero_bits[REGNO (temp)]
2402 != GET_MODE_MASK (word_mode))))
2403 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2404 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2405 (GET_CODE (temp) == REG
2406 && reg_nonzero_bits[REGNO (temp)] != 0
2407 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2408 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2409 && (reg_nonzero_bits[REGNO (temp)]
2410 != GET_MODE_MASK (word_mode)))))
2411 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2412 SET_SRC (XVECEXP (newpat, 0, 1)))
2413 && ! find_reg_note (i3, REG_UNUSED,
2414 SET_DEST (XVECEXP (newpat, 0, 0))))
2418 newi2pat = XVECEXP (newpat, 0, 0);
2419 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2420 newpat = XVECEXP (newpat, 0, 1);
2421 SUBST (SET_SRC (newpat),
2422 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2423 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2425 if (i2_code_number >= 0)
2426 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2428 if (insn_code_number >= 0)
2433 /* If we will be able to accept this, we have made a change to the
2434 destination of I3. This requires us to do a few adjustments. */
2435 PATTERN (i3) = newpat;
2436 adjust_for_new_dest (i3);
2438 /* I3 now uses what used to be its destination and which is
2439 now I2's destination. That means we need a LOG_LINK from
2440 I3 to I2. But we used to have one, so we still will.
2442 However, some later insn might be using I2's dest and have
2443 a LOG_LINK pointing at I3. We must remove this link.
2444 The simplest way to remove the link is to point it at I1,
2445 which we know will be a NOTE. */
2447 for (insn = NEXT_INSN (i3);
2448 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2449 || insn != this_basic_block->next_bb->head);
2450 insn = NEXT_INSN (insn))
2452 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2454 for (link = LOG_LINKS (insn); link;
2455 link = XEXP (link, 1))
2456 if (XEXP (link, 0) == i3)
2457 XEXP (link, 0) = i1;
2465 /* Similarly, check for a case where we have a PARALLEL of two independent
2466 SETs but we started with three insns. In this case, we can do the sets
2467 as two separate insns. This case occurs when some SET allows two
2468 other insns to combine, but the destination of that SET is still live. */
2470 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2471 && GET_CODE (newpat) == PARALLEL
2472 && XVECLEN (newpat, 0) == 2
2473 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2474 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2475 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2476 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2477 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2478 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2479 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2481 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2482 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2483 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2484 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2485 XVECEXP (newpat, 0, 0))
2486 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2487 XVECEXP (newpat, 0, 1))
2488 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2489 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2491 /* Normally, it doesn't matter which of the two is done first,
2492 but it does if one references cc0. In that case, it has to
2495 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2497 newi2pat = XVECEXP (newpat, 0, 0);
2498 newpat = XVECEXP (newpat, 0, 1);
2503 newi2pat = XVECEXP (newpat, 0, 1);
2504 newpat = XVECEXP (newpat, 0, 0);
2507 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2509 if (i2_code_number >= 0)
2510 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2513 /* If it still isn't recognized, fail and change things back the way they
2515 if ((insn_code_number < 0
2516 /* Is the result a reasonable ASM_OPERANDS? */
2517 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2523 /* If we had to change another insn, make sure it is valid also. */
2524 if (undobuf.other_insn)
2526 rtx other_pat = PATTERN (undobuf.other_insn);
2527 rtx new_other_notes;
2530 CLEAR_HARD_REG_SET (newpat_used_regs);
2532 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2535 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2541 PATTERN (undobuf.other_insn) = other_pat;
2543 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2544 are still valid. Then add any non-duplicate notes added by
2545 recog_for_combine. */
2546 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2548 next = XEXP (note, 1);
2550 if (REG_NOTE_KIND (note) == REG_UNUSED
2551 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2553 if (GET_CODE (XEXP (note, 0)) == REG)
2554 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2556 remove_note (undobuf.other_insn, note);
2560 for (note = new_other_notes; note; note = XEXP (note, 1))
2561 if (GET_CODE (XEXP (note, 0)) == REG)
2562 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2564 distribute_notes (new_other_notes, undobuf.other_insn,
2565 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2568 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2569 they are adjacent to each other or not. */
2571 rtx p = prev_nonnote_insn (i3);
2572 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2573 && sets_cc0_p (newi2pat))
2581 /* We now know that we can do this combination. Merge the insns and
2582 update the status of registers and LOG_LINKS. */
2585 rtx i3notes, i2notes, i1notes = 0;
2586 rtx i3links, i2links, i1links = 0;
2589 /* Compute which registers we expect to eliminate. newi2pat may be setting
2590 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2591 same as i3dest, in which case newi2pat may be setting i1dest. */
2592 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2593 || i2dest_in_i2src || i2dest_in_i1src
2595 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2596 || (newi2pat && reg_set_p (i1dest, newi2pat))
2599 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2601 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2602 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2604 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2606 /* Ensure that we do not have something that should not be shared but
2607 occurs multiple times in the new insns. Check this by first
2608 resetting all the `used' flags and then copying anything is shared. */
2610 reset_used_flags (i3notes);
2611 reset_used_flags (i2notes);
2612 reset_used_flags (i1notes);
2613 reset_used_flags (newpat);
2614 reset_used_flags (newi2pat);
2615 if (undobuf.other_insn)
2616 reset_used_flags (PATTERN (undobuf.other_insn));
2618 i3notes = copy_rtx_if_shared (i3notes);
2619 i2notes = copy_rtx_if_shared (i2notes);
2620 i1notes = copy_rtx_if_shared (i1notes);
2621 newpat = copy_rtx_if_shared (newpat);
2622 newi2pat = copy_rtx_if_shared (newi2pat);
2623 if (undobuf.other_insn)
2624 reset_used_flags (PATTERN (undobuf.other_insn));
2626 INSN_CODE (i3) = insn_code_number;
2627 PATTERN (i3) = newpat;
2629 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2631 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2633 reset_used_flags (call_usage);
2634 call_usage = copy_rtx (call_usage);
2637 replace_rtx (call_usage, i2dest, i2src);
2640 replace_rtx (call_usage, i1dest, i1src);
2642 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2645 if (undobuf.other_insn)
2646 INSN_CODE (undobuf.other_insn) = other_code_number;
2648 /* We had one special case above where I2 had more than one set and
2649 we replaced a destination of one of those sets with the destination
2650 of I3. In that case, we have to update LOG_LINKS of insns later
2651 in this basic block. Note that this (expensive) case is rare.
2653 Also, in this case, we must pretend that all REG_NOTEs for I2
2654 actually came from I3, so that REG_UNUSED notes from I2 will be
2655 properly handled. */
2657 if (i3_subst_into_i2)
2659 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2660 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2661 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2662 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2663 && ! find_reg_note (i2, REG_UNUSED,
2664 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2665 for (temp = NEXT_INSN (i2);
2666 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2667 || this_basic_block->head != temp);
2668 temp = NEXT_INSN (temp))
2669 if (temp != i3 && INSN_P (temp))
2670 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2671 if (XEXP (link, 0) == i2)
2672 XEXP (link, 0) = i3;
2677 while (XEXP (link, 1))
2678 link = XEXP (link, 1);
2679 XEXP (link, 1) = i2notes;
2693 INSN_CODE (i2) = i2_code_number;
2694 PATTERN (i2) = newi2pat;
2698 PUT_CODE (i2, NOTE);
2699 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2700 NOTE_SOURCE_FILE (i2) = 0;
2707 PUT_CODE (i1, NOTE);
2708 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2709 NOTE_SOURCE_FILE (i1) = 0;
2712 /* Get death notes for everything that is now used in either I3 or
2713 I2 and used to die in a previous insn. If we built two new
2714 patterns, move from I1 to I2 then I2 to I3 so that we get the
2715 proper movement on registers that I2 modifies. */
2719 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2720 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2723 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2726 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2728 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2731 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2734 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2737 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2740 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2741 know these are REG_UNUSED and want them to go to the desired insn,
2742 so we always pass it as i3. We have not counted the notes in
2743 reg_n_deaths yet, so we need to do so now. */
2745 if (newi2pat && new_i2_notes)
2747 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2748 if (GET_CODE (XEXP (temp, 0)) == REG)
2749 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2751 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2756 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2757 if (GET_CODE (XEXP (temp, 0)) == REG)
2758 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2760 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2763 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2764 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2765 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2766 in that case, it might delete I2. Similarly for I2 and I1.
2767 Show an additional death due to the REG_DEAD note we make here. If
2768 we discard it in distribute_notes, we will decrement it again. */
2772 if (GET_CODE (i3dest_killed) == REG)
2773 REG_N_DEATHS (REGNO (i3dest_killed))++;
2775 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2776 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2778 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2780 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2782 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2786 if (i2dest_in_i2src)
2788 if (GET_CODE (i2dest) == REG)
2789 REG_N_DEATHS (REGNO (i2dest))++;
2791 if (newi2pat && reg_set_p (i2dest, newi2pat))
2792 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2793 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2795 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2796 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2797 NULL_RTX, NULL_RTX);
2800 if (i1dest_in_i1src)
2802 if (GET_CODE (i1dest) == REG)
2803 REG_N_DEATHS (REGNO (i1dest))++;
2805 if (newi2pat && reg_set_p (i1dest, newi2pat))
2806 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2807 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2809 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2810 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2811 NULL_RTX, NULL_RTX);
2814 distribute_links (i3links);
2815 distribute_links (i2links);
2816 distribute_links (i1links);
2818 if (GET_CODE (i2dest) == REG)
2821 rtx i2_insn = 0, i2_val = 0, set;
2823 /* The insn that used to set this register doesn't exist, and
2824 this life of the register may not exist either. See if one of
2825 I3's links points to an insn that sets I2DEST. If it does,
2826 that is now the last known value for I2DEST. If we don't update
2827 this and I2 set the register to a value that depended on its old
2828 contents, we will get confused. If this insn is used, thing
2829 will be set correctly in combine_instructions. */
2831 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2832 if ((set = single_set (XEXP (link, 0))) != 0
2833 && rtx_equal_p (i2dest, SET_DEST (set)))
2834 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2836 record_value_for_reg (i2dest, i2_insn, i2_val);
2838 /* If the reg formerly set in I2 died only once and that was in I3,
2839 zero its use count so it won't make `reload' do any work. */
2841 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2842 && ! i2dest_in_i2src)
2844 regno = REGNO (i2dest);
2845 REG_N_SETS (regno)--;
2849 if (i1 && GET_CODE (i1dest) == REG)
2852 rtx i1_insn = 0, i1_val = 0, set;
2854 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2855 if ((set = single_set (XEXP (link, 0))) != 0
2856 && rtx_equal_p (i1dest, SET_DEST (set)))
2857 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2859 record_value_for_reg (i1dest, i1_insn, i1_val);
2861 regno = REGNO (i1dest);
2862 if (! added_sets_1 && ! i1dest_in_i1src)
2863 REG_N_SETS (regno)--;
2866 /* Update reg_nonzero_bits et al for any changes that may have been made
2867 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2868 important. Because newi2pat can affect nonzero_bits of newpat */
2870 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2871 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2873 /* Set new_direct_jump_p if a new return or simple jump instruction
2876 If I3 is now an unconditional jump, ensure that it has a
2877 BARRIER following it since it may have initially been a
2878 conditional jump. It may also be the last nonnote insn. */
2880 if (returnjump_p (i3) || any_uncondjump_p (i3))
2882 *new_direct_jump_p = 1;
2884 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2885 || GET_CODE (temp) != BARRIER)
2886 emit_barrier_after (i3);
2889 if (undobuf.other_insn != NULL_RTX
2890 && (returnjump_p (undobuf.other_insn)
2891 || any_uncondjump_p (undobuf.other_insn)))
2893 *new_direct_jump_p = 1;
2895 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2896 || GET_CODE (temp) != BARRIER)
2897 emit_barrier_after (undobuf.other_insn);
2900 /* An NOOP jump does not need barrier, but it does need cleaning up
2902 if (GET_CODE (newpat) == SET
2903 && SET_SRC (newpat) == pc_rtx
2904 && SET_DEST (newpat) == pc_rtx)
2905 *new_direct_jump_p = 1;
2908 combine_successes++;
2911 /* Clear this here, so that subsequent get_last_value calls are not
2913 subst_prev_insn = NULL_RTX;
2915 if (added_links_insn
2916 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2917 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2918 return added_links_insn;
2920 return newi2pat ? i2 : i3;
2923 /* Undo all the modifications recorded in undobuf. */
2928 struct undo *undo, *next;
2930 for (undo = undobuf.undos; undo; undo = next)
2934 *undo->where.i = undo->old_contents.i;
2936 *undo->where.r = undo->old_contents.r;
2938 undo->next = undobuf.frees;
2939 undobuf.frees = undo;
2944 /* Clear this here, so that subsequent get_last_value calls are not
2946 subst_prev_insn = NULL_RTX;
2949 /* We've committed to accepting the changes we made. Move all
2950 of the undos to the free list. */
2955 struct undo *undo, *next;
2957 for (undo = undobuf.undos; undo; undo = next)
2960 undo->next = undobuf.frees;
2961 undobuf.frees = undo;
2967 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2968 where we have an arithmetic expression and return that point. LOC will
2971 try_combine will call this function to see if an insn can be split into
2975 find_split_point (loc, insn)
2980 enum rtx_code code = GET_CODE (x);
2982 unsigned HOST_WIDE_INT len = 0;
2983 HOST_WIDE_INT pos = 0;
2985 rtx inner = NULL_RTX;
2987 /* First special-case some codes. */
2991 #ifdef INSN_SCHEDULING
2992 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2994 if (GET_CODE (SUBREG_REG (x)) == MEM)
2997 return find_split_point (&SUBREG_REG (x), insn);
3001 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3002 using LO_SUM and HIGH. */
3003 if (GET_CODE (XEXP (x, 0)) == CONST
3004 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3007 gen_rtx_LO_SUM (Pmode,
3008 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3010 return &XEXP (XEXP (x, 0), 0);
3014 /* If we have a PLUS whose second operand is a constant and the
3015 address is not valid, perhaps will can split it up using
3016 the machine-specific way to split large constants. We use
3017 the first pseudo-reg (one of the virtual regs) as a placeholder;
3018 it will not remain in the result. */
3019 if (GET_CODE (XEXP (x, 0)) == PLUS
3020 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3021 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3023 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3024 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3027 /* This should have produced two insns, each of which sets our
3028 placeholder. If the source of the second is a valid address,
3029 we can make put both sources together and make a split point
3033 && NEXT_INSN (seq) != NULL_RTX
3034 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3035 && GET_CODE (seq) == INSN
3036 && GET_CODE (PATTERN (seq)) == SET
3037 && SET_DEST (PATTERN (seq)) == reg
3038 && ! reg_mentioned_p (reg,
3039 SET_SRC (PATTERN (seq)))
3040 && GET_CODE (NEXT_INSN (seq)) == INSN
3041 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3042 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3043 && memory_address_p (GET_MODE (x),
3044 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3046 rtx src1 = SET_SRC (PATTERN (seq));
3047 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3049 /* Replace the placeholder in SRC2 with SRC1. If we can
3050 find where in SRC2 it was placed, that can become our
3051 split point and we can replace this address with SRC2.
3052 Just try two obvious places. */
3054 src2 = replace_rtx (src2, reg, src1);
3056 if (XEXP (src2, 0) == src1)
3057 split = &XEXP (src2, 0);
3058 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3059 && XEXP (XEXP (src2, 0), 0) == src1)
3060 split = &XEXP (XEXP (src2, 0), 0);
3064 SUBST (XEXP (x, 0), src2);
3069 /* If that didn't work, perhaps the first operand is complex and
3070 needs to be computed separately, so make a split point there.
3071 This will occur on machines that just support REG + CONST
3072 and have a constant moved through some previous computation. */
3074 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3075 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3076 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3078 return &XEXP (XEXP (x, 0), 0);
3084 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3085 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3086 we need to put the operand into a register. So split at that
3089 if (SET_DEST (x) == cc0_rtx
3090 && GET_CODE (SET_SRC (x)) != COMPARE
3091 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3092 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3093 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3094 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3095 return &SET_SRC (x);
3098 /* See if we can split SET_SRC as it stands. */
3099 split = find_split_point (&SET_SRC (x), insn);
3100 if (split && split != &SET_SRC (x))
3103 /* See if we can split SET_DEST as it stands. */
3104 split = find_split_point (&SET_DEST (x), insn);
3105 if (split && split != &SET_DEST (x))
3108 /* See if this is a bitfield assignment with everything constant. If
3109 so, this is an IOR of an AND, so split it into that. */
3110 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3111 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3112 <= HOST_BITS_PER_WIDE_INT)
3113 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3114 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3115 && GET_CODE (SET_SRC (x)) == CONST_INT
3116 && ((INTVAL (XEXP (SET_DEST (x), 1))
3117 + INTVAL (XEXP (SET_DEST (x), 2)))
3118 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3119 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3121 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3122 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3123 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3124 rtx dest = XEXP (SET_DEST (x), 0);
3125 enum machine_mode mode = GET_MODE (dest);
3126 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3128 if (BITS_BIG_ENDIAN)
3129 pos = GET_MODE_BITSIZE (mode) - len - pos;
3133 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3136 gen_binary (IOR, mode,
3137 gen_binary (AND, mode, dest,
3138 gen_int_mode (~(mask << pos),
3140 GEN_INT (src << pos)));
3142 SUBST (SET_DEST (x), dest);
3144 split = find_split_point (&SET_SRC (x), insn);
3145 if (split && split != &SET_SRC (x))
3149 /* Otherwise, see if this is an operation that we can split into two.
3150 If so, try to split that. */
3151 code = GET_CODE (SET_SRC (x));
3156 /* If we are AND'ing with a large constant that is only a single
3157 bit and the result is only being used in a context where we
3158 need to know if it is zero or nonzero, replace it with a bit
3159 extraction. This will avoid the large constant, which might
3160 have taken more than one insn to make. If the constant were
3161 not a valid argument to the AND but took only one insn to make,
3162 this is no worse, but if it took more than one insn, it will
3165 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3166 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3167 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3168 && GET_CODE (SET_DEST (x)) == REG
3169 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3170 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3171 && XEXP (*split, 0) == SET_DEST (x)
3172 && XEXP (*split, 1) == const0_rtx)
3174 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3175 XEXP (SET_SRC (x), 0),
3176 pos, NULL_RTX, 1, 1, 0, 0);
3177 if (extraction != 0)
3179 SUBST (SET_SRC (x), extraction);
3180 return find_split_point (loc, insn);
3186 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3187 is known to be on, this can be converted into a NEG of a shift. */
3188 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3189 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3190 && 1 <= (pos = exact_log2
3191 (nonzero_bits (XEXP (SET_SRC (x), 0),
3192 GET_MODE (XEXP (SET_SRC (x), 0))))))
3194 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3198 gen_rtx_LSHIFTRT (mode,
3199 XEXP (SET_SRC (x), 0),
3202 split = find_split_point (&SET_SRC (x), insn);
3203 if (split && split != &SET_SRC (x))
3209 inner = XEXP (SET_SRC (x), 0);
3211 /* We can't optimize if either mode is a partial integer
3212 mode as we don't know how many bits are significant
3214 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3215 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3219 len = GET_MODE_BITSIZE (GET_MODE (inner));
3225 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3226 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3228 inner = XEXP (SET_SRC (x), 0);
3229 len = INTVAL (XEXP (SET_SRC (x), 1));
3230 pos = INTVAL (XEXP (SET_SRC (x), 2));
3232 if (BITS_BIG_ENDIAN)
3233 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3234 unsignedp = (code == ZERO_EXTRACT);
3242 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3244 enum machine_mode mode = GET_MODE (SET_SRC (x));
3246 /* For unsigned, we have a choice of a shift followed by an
3247 AND or two shifts. Use two shifts for field sizes where the
3248 constant might be too large. We assume here that we can
3249 always at least get 8-bit constants in an AND insn, which is
3250 true for every current RISC. */
3252 if (unsignedp && len <= 8)
3257 (mode, gen_lowpart_for_combine (mode, inner),
3259 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3261 split = find_split_point (&SET_SRC (x), insn);
3262 if (split && split != &SET_SRC (x))
3269 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3270 gen_rtx_ASHIFT (mode,
3271 gen_lowpart_for_combine (mode, inner),
3272 GEN_INT (GET_MODE_BITSIZE (mode)
3274 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3276 split = find_split_point (&SET_SRC (x), insn);
3277 if (split && split != &SET_SRC (x))
3282 /* See if this is a simple operation with a constant as the second
3283 operand. It might be that this constant is out of range and hence
3284 could be used as a split point. */
3285 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3286 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3287 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3288 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3289 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3290 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3291 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3293 return &XEXP (SET_SRC (x), 1);
3295 /* Finally, see if this is a simple operation with its first operand
3296 not in a register. The operation might require this operand in a
3297 register, so return it as a split point. We can always do this
3298 because if the first operand were another operation, we would have
3299 already found it as a split point. */
3300 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3301 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3302 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3303 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3304 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3305 return &XEXP (SET_SRC (x), 0);
3311 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3312 it is better to write this as (not (ior A B)) so we can split it.
3313 Similarly for IOR. */
3314 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3317 gen_rtx_NOT (GET_MODE (x),
3318 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3320 XEXP (XEXP (x, 0), 0),
3321 XEXP (XEXP (x, 1), 0))));
3322 return find_split_point (loc, insn);
3325 /* Many RISC machines have a large set of logical insns. If the
3326 second operand is a NOT, put it first so we will try to split the
3327 other operand first. */
3328 if (GET_CODE (XEXP (x, 1)) == NOT)
3330 rtx tem = XEXP (x, 0);
3331 SUBST (XEXP (x, 0), XEXP (x, 1));
3332 SUBST (XEXP (x, 1), tem);
3340 /* Otherwise, select our actions depending on our rtx class. */
3341 switch (GET_RTX_CLASS (code))
3343 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3345 split = find_split_point (&XEXP (x, 2), insn);
3348 /* ... fall through ... */
3352 split = find_split_point (&XEXP (x, 1), insn);
3355 /* ... fall through ... */
3357 /* Some machines have (and (shift ...) ...) insns. If X is not
3358 an AND, but XEXP (X, 0) is, use it as our split point. */
3359 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3360 return &XEXP (x, 0);
3362 split = find_split_point (&XEXP (x, 0), insn);
3368 /* Otherwise, we don't have a split point. */
3372 /* Throughout X, replace FROM with TO, and return the result.
3373 The result is TO if X is FROM;
3374 otherwise the result is X, but its contents may have been modified.
3375 If they were modified, a record was made in undobuf so that
3376 undo_all will (among other things) return X to its original state.
3378 If the number of changes necessary is too much to record to undo,
3379 the excess changes are not made, so the result is invalid.
3380 The changes already made can still be undone.
3381 undobuf.num_undo is incremented for such changes, so by testing that
3382 the caller can tell whether the result is valid.
3384 `n_occurrences' is incremented each time FROM is replaced.
3386 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3388 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3389 by copying if `n_occurrences' is nonzero. */
3392 subst (x, from, to, in_dest, unique_copy)
3397 enum rtx_code code = GET_CODE (x);
3398 enum machine_mode op0_mode = VOIDmode;
3403 /* Two expressions are equal if they are identical copies of a shared
3404 RTX or if they are both registers with the same register number
3407 #define COMBINE_RTX_EQUAL_P(X,Y) \
3409 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3410 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3412 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3415 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3418 /* If X and FROM are the same register but different modes, they will
3419 not have been seen as equal above. However, flow.c will make a
3420 LOG_LINKS entry for that case. If we do nothing, we will try to
3421 rerecognize our original insn and, when it succeeds, we will
3422 delete the feeding insn, which is incorrect.
3424 So force this insn not to match in this (rare) case. */
3425 if (! in_dest && code == REG && GET_CODE (from) == REG
3426 && REGNO (x) == REGNO (from))
3427 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3429 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3430 of which may contain things that can be combined. */
3431 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3434 /* It is possible to have a subexpression appear twice in the insn.
3435 Suppose that FROM is a register that appears within TO.
3436 Then, after that subexpression has been scanned once by `subst',
3437 the second time it is scanned, TO may be found. If we were
3438 to scan TO here, we would find FROM within it and create a
3439 self-referent rtl structure which is completely wrong. */
3440 if (COMBINE_RTX_EQUAL_P (x, to))
3443 /* Parallel asm_operands need special attention because all of the
3444 inputs are shared across the arms. Furthermore, unsharing the
3445 rtl results in recognition failures. Failure to handle this case
3446 specially can result in circular rtl.
3448 Solve this by doing a normal pass across the first entry of the
3449 parallel, and only processing the SET_DESTs of the subsequent
3452 if (code == PARALLEL
3453 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3454 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3456 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3458 /* If this substitution failed, this whole thing fails. */
3459 if (GET_CODE (new) == CLOBBER
3460 && XEXP (new, 0) == const0_rtx)
3463 SUBST (XVECEXP (x, 0, 0), new);
3465 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3467 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3469 if (GET_CODE (dest) != REG
3470 && GET_CODE (dest) != CC0
3471 && GET_CODE (dest) != PC)
3473 new = subst (dest, from, to, 0, unique_copy);
3475 /* If this substitution failed, this whole thing fails. */
3476 if (GET_CODE (new) == CLOBBER
3477 && XEXP (new, 0) == const0_rtx)
3480 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3486 len = GET_RTX_LENGTH (code);
3487 fmt = GET_RTX_FORMAT (code);
3489 /* We don't need to process a SET_DEST that is a register, CC0,
3490 or PC, so set up to skip this common case. All other cases
3491 where we want to suppress replacing something inside a
3492 SET_SRC are handled via the IN_DEST operand. */
3494 && (GET_CODE (SET_DEST (x)) == REG
3495 || GET_CODE (SET_DEST (x)) == CC0
3496 || GET_CODE (SET_DEST (x)) == PC))
3499 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3502 op0_mode = GET_MODE (XEXP (x, 0));
3504 for (i = 0; i < len; i++)
3509 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3511 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3513 new = (unique_copy && n_occurrences
3514 ? copy_rtx (to) : to);
3519 new = subst (XVECEXP (x, i, j), from, to, 0,
3522 /* If this substitution failed, this whole thing
3524 if (GET_CODE (new) == CLOBBER
3525 && XEXP (new, 0) == const0_rtx)
3529 SUBST (XVECEXP (x, i, j), new);
3532 else if (fmt[i] == 'e')
3534 /* If this is a register being set, ignore it. */
3537 && (code == SUBREG || code == STRICT_LOW_PART
3538 || code == ZERO_EXTRACT)
3540 && GET_CODE (new) == REG)
3543 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3545 /* In general, don't install a subreg involving two
3546 modes not tieable. It can worsen register
3547 allocation, and can even make invalid reload
3548 insns, since the reg inside may need to be copied
3549 from in the outside mode, and that may be invalid
3550 if it is an fp reg copied in integer mode.
3552 We allow two exceptions to this: It is valid if
3553 it is inside another SUBREG and the mode of that
3554 SUBREG and the mode of the inside of TO is
3555 tieable and it is valid if X is a SET that copies
3558 if (GET_CODE (to) == SUBREG
3559 && ! MODES_TIEABLE_P (GET_MODE (to),
3560 GET_MODE (SUBREG_REG (to)))
3561 && ! (code == SUBREG
3562 && MODES_TIEABLE_P (GET_MODE (x),
3563 GET_MODE (SUBREG_REG (to))))
3565 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3568 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3570 #ifdef CANNOT_CHANGE_MODE_CLASS
3572 && GET_CODE (to) == REG
3573 && REGNO (to) < FIRST_PSEUDO_REGISTER
3574 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3577 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3580 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3584 /* If we are in a SET_DEST, suppress most cases unless we
3585 have gone inside a MEM, in which case we want to
3586 simplify the address. We assume here that things that
3587 are actually part of the destination have their inner
3588 parts in the first expression. This is true for SUBREG,
3589 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3590 things aside from REG and MEM that should appear in a
3592 new = subst (XEXP (x, i), from, to,
3594 && (code == SUBREG || code == STRICT_LOW_PART
3595 || code == ZERO_EXTRACT))
3597 && i == 0), unique_copy);
3599 /* If we found that we will have to reject this combination,
3600 indicate that by returning the CLOBBER ourselves, rather than
3601 an expression containing it. This will speed things up as
3602 well as prevent accidents where two CLOBBERs are considered
3603 to be equal, thus producing an incorrect simplification. */
3605 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3608 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3610 enum machine_mode mode = GET_MODE (x);
3612 x = simplify_subreg (GET_MODE (x), new,
3613 GET_MODE (SUBREG_REG (x)),
3616 x = gen_rtx_CLOBBER (mode, const0_rtx);
3618 else if (GET_CODE (new) == CONST_INT
3619 && GET_CODE (x) == ZERO_EXTEND)
3621 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3622 new, GET_MODE (XEXP (x, 0)));
3627 SUBST (XEXP (x, i), new);
3632 /* Try to simplify X. If the simplification changed the code, it is likely
3633 that further simplification will help, so loop, but limit the number
3634 of repetitions that will be performed. */
3636 for (i = 0; i < 4; i++)
3638 /* If X is sufficiently simple, don't bother trying to do anything
3640 if (code != CONST_INT && code != REG && code != CLOBBER)
3641 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3643 if (GET_CODE (x) == code)
3646 code = GET_CODE (x);
3648 /* We no longer know the original mode of operand 0 since we
3649 have changed the form of X) */
3650 op0_mode = VOIDmode;
3656 /* Simplify X, a piece of RTL. We just operate on the expression at the
3657 outer level; call `subst' to simplify recursively. Return the new
3660 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3661 will be the iteration even if an expression with a code different from
3662 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3665 combine_simplify_rtx (x, op0_mode, last, in_dest)
3667 enum machine_mode op0_mode;
3671 enum rtx_code code = GET_CODE (x);
3672 enum machine_mode mode = GET_MODE (x);
3677 /* If this is a commutative operation, put a constant last and a complex
3678 expression first. We don't need to do this for comparisons here. */
3679 if (GET_RTX_CLASS (code) == 'c'
3680 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3683 SUBST (XEXP (x, 0), XEXP (x, 1));
3684 SUBST (XEXP (x, 1), temp);
3687 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3688 sign extension of a PLUS with a constant, reverse the order of the sign
3689 extension and the addition. Note that this not the same as the original
3690 code, but overflow is undefined for signed values. Also note that the
3691 PLUS will have been partially moved "inside" the sign-extension, so that
3692 the first operand of X will really look like:
3693 (ashiftrt (plus (ashift A C4) C5) C4).
3695 (plus (ashiftrt (ashift A C4) C2) C4)
3696 and replace the first operand of X with that expression. Later parts
3697 of this function may simplify the expression further.
3699 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3700 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3701 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3703 We do this to simplify address expressions. */
3705 if ((code == PLUS || code == MINUS || code == MULT)
3706 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3707 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3708 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3709 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3710 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3711 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3712 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3713 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3714 XEXP (XEXP (XEXP (x, 0), 0), 1),
3715 XEXP (XEXP (x, 0), 1))) != 0)
3718 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3719 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3720 INTVAL (XEXP (XEXP (x, 0), 1)));
3722 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3723 INTVAL (XEXP (XEXP (x, 0), 1)));
3725 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3728 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3729 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3730 things. Check for cases where both arms are testing the same
3733 Don't do anything if all operands are very simple. */
3735 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3736 || GET_RTX_CLASS (code) == '<')
3737 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3738 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3739 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3741 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3742 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3743 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3745 || (GET_RTX_CLASS (code) == '1'
3746 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3747 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3748 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3751 rtx cond, true_rtx, false_rtx;
3753 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3755 /* If everything is a comparison, what we have is highly unlikely
3756 to be simpler, so don't use it. */
3757 && ! (GET_RTX_CLASS (code) == '<'
3758 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3759 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3761 rtx cop1 = const0_rtx;
3762 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3764 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3767 /* Simplify the alternative arms; this may collapse the true and
3768 false arms to store-flag values. */
3769 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3770 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3772 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3773 is unlikely to be simpler. */
3774 if (general_operand (true_rtx, VOIDmode)
3775 && general_operand (false_rtx, VOIDmode))
3777 /* Restarting if we generate a store-flag expression will cause
3778 us to loop. Just drop through in this case. */
3780 /* If the result values are STORE_FLAG_VALUE and zero, we can
3781 just make the comparison operation. */
3782 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3783 x = gen_binary (cond_code, mode, cond, cop1);
3784 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3785 && reverse_condition (cond_code) != UNKNOWN)
3786 x = gen_binary (reverse_condition (cond_code),
3789 /* Likewise, we can make the negate of a comparison operation
3790 if the result values are - STORE_FLAG_VALUE and zero. */
3791 else if (GET_CODE (true_rtx) == CONST_INT
3792 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3793 && false_rtx == const0_rtx)
3794 x = simplify_gen_unary (NEG, mode,
3795 gen_binary (cond_code, mode, cond,
3798 else if (GET_CODE (false_rtx) == CONST_INT
3799 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3800 && true_rtx == const0_rtx)
3801 x = simplify_gen_unary (NEG, mode,
3802 gen_binary (reverse_condition
3807 return gen_rtx_IF_THEN_ELSE (mode,
3808 gen_binary (cond_code, VOIDmode,
3810 true_rtx, false_rtx);
3812 code = GET_CODE (x);
3813 op0_mode = VOIDmode;
3818 /* Try to fold this expression in case we have constants that weren't
3821 switch (GET_RTX_CLASS (code))
3824 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3828 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3829 if (cmp_mode == VOIDmode)
3831 cmp_mode = GET_MODE (XEXP (x, 1));
3832 if (cmp_mode == VOIDmode)
3833 cmp_mode = op0_mode;
3835 temp = simplify_relational_operation (code, cmp_mode,
3836 XEXP (x, 0), XEXP (x, 1));
3838 #ifdef FLOAT_STORE_FLAG_VALUE
3839 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3841 if (temp == const0_rtx)
3842 temp = CONST0_RTX (mode);
3844 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3851 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3855 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3856 XEXP (x, 1), XEXP (x, 2));
3863 code = GET_CODE (temp);
3864 op0_mode = VOIDmode;
3865 mode = GET_MODE (temp);
3868 /* First see if we can apply the inverse distributive law. */
3869 if (code == PLUS || code == MINUS
3870 || code == AND || code == IOR || code == XOR)
3872 x = apply_distributive_law (x);
3873 code = GET_CODE (x);
3874 op0_mode = VOIDmode;
3877 /* If CODE is an associative operation not otherwise handled, see if we
3878 can associate some operands. This can win if they are constants or
3879 if they are logically related (i.e. (a & b) & a). */
3880 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3881 || code == AND || code == IOR || code == XOR
3882 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3883 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3884 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3886 if (GET_CODE (XEXP (x, 0)) == code)
3888 rtx other = XEXP (XEXP (x, 0), 0);
3889 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3890 rtx inner_op1 = XEXP (x, 1);
3893 /* Make sure we pass the constant operand if any as the second
3894 one if this is a commutative operation. */
3895 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3897 rtx tem = inner_op0;
3898 inner_op0 = inner_op1;
3901 inner = simplify_binary_operation (code == MINUS ? PLUS
3902 : code == DIV ? MULT
3904 mode, inner_op0, inner_op1);
3906 /* For commutative operations, try the other pair if that one
3908 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3910 other = XEXP (XEXP (x, 0), 1);
3911 inner = simplify_binary_operation (code, mode,
3912 XEXP (XEXP (x, 0), 0),
3917 return gen_binary (code, mode, other, inner);
3921 /* A little bit of algebraic simplification here. */
3925 /* Ensure that our address has any ASHIFTs converted to MULT in case
3926 address-recognizing predicates are called later. */
3927 temp = make_compound_operation (XEXP (x, 0), MEM);
3928 SUBST (XEXP (x, 0), temp);
3932 if (op0_mode == VOIDmode)
3933 op0_mode = GET_MODE (SUBREG_REG (x));
3935 /* simplify_subreg can't use gen_lowpart_for_combine. */
3936 if (CONSTANT_P (SUBREG_REG (x))
3937 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3938 /* Don't call gen_lowpart_for_combine if the inner mode
3939 is VOIDmode and we cannot simplify it, as SUBREG without
3940 inner mode is invalid. */
3941 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3942 || gen_lowpart_common (mode, SUBREG_REG (x))))
3943 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3945 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3949 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3955 /* Don't change the mode of the MEM if that would change the meaning
3957 if (GET_CODE (SUBREG_REG (x)) == MEM
3958 && (MEM_VOLATILE_P (SUBREG_REG (x))
3959 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3960 return gen_rtx_CLOBBER (mode, const0_rtx);
3962 /* Note that we cannot do any narrowing for non-constants since
3963 we might have been counting on using the fact that some bits were
3964 zero. We now do this in the SET. */
3969 /* (not (plus X -1)) can become (neg X). */
3970 if (GET_CODE (XEXP (x, 0)) == PLUS
3971 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3972 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3974 /* Similarly, (not (neg X)) is (plus X -1). */
3975 if (GET_CODE (XEXP (x, 0)) == NEG)
3976 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3978 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3979 if (GET_CODE (XEXP (x, 0)) == XOR
3980 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3981 && (temp = simplify_unary_operation (NOT, mode,
3982 XEXP (XEXP (x, 0), 1),
3984 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3986 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3987 other than 1, but that is not valid. We could do a similar
3988 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3989 but this doesn't seem common enough to bother with. */
3990 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3991 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3992 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3994 XEXP (XEXP (x, 0), 1));
3996 if (GET_CODE (XEXP (x, 0)) == SUBREG
3997 && subreg_lowpart_p (XEXP (x, 0))
3998 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3999 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4000 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4001 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4003 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4005 x = gen_rtx_ROTATE (inner_mode,
4006 simplify_gen_unary (NOT, inner_mode, const1_rtx,
4008 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4009 return gen_lowpart_for_combine (mode, x);
4012 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
4013 reversing the comparison code if valid. */
4014 if (STORE_FLAG_VALUE == -1
4015 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4016 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
4017 XEXP (XEXP (x, 0), 1))))
4020 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
4021 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
4022 perform the above simplification. */
4024 if (STORE_FLAG_VALUE == -1
4025 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
4026 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4027 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
4028 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
4030 /* Apply De Morgan's laws to reduce number of patterns for machines
4031 with negating logical insns (and-not, nand, etc.). If result has
4032 only one NOT, put it first, since that is how the patterns are
4035 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4037 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4038 enum machine_mode op_mode;
4040 op_mode = GET_MODE (in1);
4041 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4043 op_mode = GET_MODE (in2);
4044 if (op_mode == VOIDmode)
4046 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4048 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4051 in2 = in1; in1 = tem;
4054 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4060 /* (neg (plus X 1)) can become (not X). */
4061 if (GET_CODE (XEXP (x, 0)) == PLUS
4062 && XEXP (XEXP (x, 0), 1) == const1_rtx)
4063 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
4065 /* Similarly, (neg (not X)) is (plus X 1). */
4066 if (GET_CODE (XEXP (x, 0)) == NOT)
4067 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
4069 /* (neg (minus X Y)) can become (minus Y X). This transformation
4070 isn't safe for modes with signed zeros, since if X and Y are
4071 both +0, (minus Y X) is the same as (minus X Y). If the rounding
4072 mode is towards +infinity (or -infinity) then the two expressions
4073 will be rounded differently. */
4074 if (GET_CODE (XEXP (x, 0)) == MINUS
4075 && !HONOR_SIGNED_ZEROS (mode)
4076 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4077 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4078 XEXP (XEXP (x, 0), 0));
4080 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
4081 if (GET_CODE (XEXP (x, 0)) == PLUS
4082 && !HONOR_SIGNED_ZEROS (mode)
4083 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4085 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4086 temp = combine_simplify_rtx (temp, mode, last, in_dest);
4087 return gen_binary (MINUS, mode, temp, XEXP (XEXP (x, 0), 1));
4090 /* (neg (mult A B)) becomes (mult (neg A) B).
4091 This works even for floating-point values. */
4092 if (GET_CODE (XEXP (x, 0)) == MULT)
4094 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4095 return gen_binary (MULT, mode, temp, XEXP (XEXP (x, 0), 1));
4098 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4099 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4100 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4101 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4103 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4104 if we can then eliminate the NEG (e.g.,
4105 if the operand is a constant). */
4107 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4109 temp = simplify_unary_operation (NEG, mode,
4110 XEXP (XEXP (x, 0), 0), mode);
4112 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4115 temp = expand_compound_operation (XEXP (x, 0));
4117 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4118 replaced by (lshiftrt X C). This will convert
4119 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4121 if (GET_CODE (temp) == ASHIFTRT
4122 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4123 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4124 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4125 INTVAL (XEXP (temp, 1)));
4127 /* If X has only a single bit that might be nonzero, say, bit I, convert
4128 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4129 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4130 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4131 or a SUBREG of one since we'd be making the expression more
4132 complex if it was just a register. */
4134 if (GET_CODE (temp) != REG
4135 && ! (GET_CODE (temp) == SUBREG
4136 && GET_CODE (SUBREG_REG (temp)) == REG)
4137 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4139 rtx temp1 = simplify_shift_const
4140 (NULL_RTX, ASHIFTRT, mode,
4141 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4142 GET_MODE_BITSIZE (mode) - 1 - i),
4143 GET_MODE_BITSIZE (mode) - 1 - i);
4145 /* If all we did was surround TEMP with the two shifts, we
4146 haven't improved anything, so don't use it. Otherwise,
4147 we are better off with TEMP1. */
4148 if (GET_CODE (temp1) != ASHIFTRT
4149 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4150 || XEXP (XEXP (temp1, 0), 0) != temp)
4156 /* We can't handle truncation to a partial integer mode here
4157 because we don't know the real bitsize of the partial
4159 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4162 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4163 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4164 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4166 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4167 GET_MODE_MASK (mode), NULL_RTX, 0));
4169 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4170 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4171 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4172 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4173 return XEXP (XEXP (x, 0), 0);
4175 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4176 (OP:SI foo:SI) if OP is NEG or ABS. */
4177 if ((GET_CODE (XEXP (x, 0)) == ABS
4178 || GET_CODE (XEXP (x, 0)) == NEG)
4179 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4180 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4181 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4182 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4183 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4185 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4187 if (GET_CODE (XEXP (x, 0)) == SUBREG
4188 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4189 && subreg_lowpart_p (XEXP (x, 0)))
4190 return SUBREG_REG (XEXP (x, 0));
4192 /* If we know that the value is already truncated, we can
4193 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4194 is nonzero for the corresponding modes. But don't do this
4195 for an (LSHIFTRT (MULT ...)) since this will cause problems
4196 with the umulXi3_highpart patterns. */
4197 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4198 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4199 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4200 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4201 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4202 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4203 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4205 /* A truncate of a comparison can be replaced with a subreg if
4206 STORE_FLAG_VALUE permits. This is like the previous test,
4207 but it works even if the comparison is done in a mode larger
4208 than HOST_BITS_PER_WIDE_INT. */
4209 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4210 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4211 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4212 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4214 /* Similarly, a truncate of a register whose value is a
4215 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4217 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4218 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4219 && (temp = get_last_value (XEXP (x, 0)))
4220 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4221 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4225 case FLOAT_TRUNCATE:
4226 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4227 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4228 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4229 return XEXP (XEXP (x, 0), 0);
4231 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4232 (OP:SF foo:SF) if OP is NEG or ABS. */
4233 if ((GET_CODE (XEXP (x, 0)) == ABS
4234 || GET_CODE (XEXP (x, 0)) == NEG)
4235 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4236 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4237 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4238 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4240 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4241 is (float_truncate:SF x). */
4242 if (GET_CODE (XEXP (x, 0)) == SUBREG
4243 && subreg_lowpart_p (XEXP (x, 0))
4244 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4245 return SUBREG_REG (XEXP (x, 0));
4250 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4251 using cc0, in which case we want to leave it as a COMPARE
4252 so we can distinguish it from a register-register-copy. */
4253 if (XEXP (x, 1) == const0_rtx)
4256 /* x - 0 is the same as x unless x's mode has signed zeros and
4257 allows rounding towards -infinity. Under those conditions,
4259 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4260 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4261 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4267 /* (const (const X)) can become (const X). Do it this way rather than
4268 returning the inner CONST since CONST can be shared with a
4270 if (GET_CODE (XEXP (x, 0)) == CONST)
4271 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4276 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4277 can add in an offset. find_split_point will split this address up
4278 again if it doesn't match. */
4279 if (GET_CODE (XEXP (x, 0)) == HIGH
4280 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4286 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4288 if (GET_CODE (XEXP (x, 0)) == MULT
4289 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4293 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4294 in2 = XEXP (XEXP (x, 0), 1);
4295 return gen_binary (MINUS, mode, XEXP (x, 1),
4296 gen_binary (MULT, mode, in1, in2));
4299 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4300 outermost. That's because that's the way indexed addresses are
4301 supposed to appear. This code used to check many more cases, but
4302 they are now checked elsewhere. */
4303 if (GET_CODE (XEXP (x, 0)) == PLUS
4304 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4305 return gen_binary (PLUS, mode,
4306 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4308 XEXP (XEXP (x, 0), 1));
4310 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4311 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4312 bit-field and can be replaced by either a sign_extend or a
4313 sign_extract. The `and' may be a zero_extend and the two
4314 <c>, -<c> constants may be reversed. */
4315 if (GET_CODE (XEXP (x, 0)) == XOR
4316 && GET_CODE (XEXP (x, 1)) == CONST_INT
4317 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4318 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4319 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4320 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4321 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4322 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4323 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4324 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4325 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4326 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4327 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4328 == (unsigned int) i + 1))))
4329 return simplify_shift_const
4330 (NULL_RTX, ASHIFTRT, mode,
4331 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4332 XEXP (XEXP (XEXP (x, 0), 0), 0),
4333 GET_MODE_BITSIZE (mode) - (i + 1)),
4334 GET_MODE_BITSIZE (mode) - (i + 1));
4336 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4337 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4338 is 1. This produces better code than the alternative immediately
4340 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4341 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4342 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4343 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4344 XEXP (XEXP (x, 0), 0),
4345 XEXP (XEXP (x, 0), 1))))
4347 simplify_gen_unary (NEG, mode, reversed, mode);
4349 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4350 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4351 the bitsize of the mode - 1. This allows simplification of
4352 "a = (b & 8) == 0;" */
4353 if (XEXP (x, 1) == constm1_rtx
4354 && GET_CODE (XEXP (x, 0)) != REG
4355 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4356 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4357 && nonzero_bits (XEXP (x, 0), mode) == 1)
4358 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4359 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4360 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4361 GET_MODE_BITSIZE (mode) - 1),
4362 GET_MODE_BITSIZE (mode) - 1);
4364 /* If we are adding two things that have no bits in common, convert
4365 the addition into an IOR. This will often be further simplified,
4366 for example in cases like ((a & 1) + (a & 2)), which can
4369 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4370 && (nonzero_bits (XEXP (x, 0), mode)
4371 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4373 /* Try to simplify the expression further. */
4374 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4375 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4377 /* If we could, great. If not, do not go ahead with the IOR
4378 replacement, since PLUS appears in many special purpose
4379 address arithmetic instructions. */
4380 if (GET_CODE (temp) != CLOBBER && temp != tor)
4386 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4387 by reversing the comparison code if valid. */
4388 if (STORE_FLAG_VALUE == 1
4389 && XEXP (x, 0) == const1_rtx
4390 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4391 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4392 XEXP (XEXP (x, 1), 0),
4393 XEXP (XEXP (x, 1), 1))))
4396 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4397 (and <foo> (const_int pow2-1)) */
4398 if (GET_CODE (XEXP (x, 1)) == AND
4399 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4400 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4401 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4402 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4403 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4405 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4407 if (GET_CODE (XEXP (x, 1)) == MULT
4408 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4412 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4413 in2 = XEXP (XEXP (x, 1), 1);
4414 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4418 /* Canonicalize (minus (neg A) (mult B C)) to
4419 (minus (mult (neg B) C) A). */
4420 if (GET_CODE (XEXP (x, 1)) == MULT
4421 && GET_CODE (XEXP (x, 0)) == NEG)
4425 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4426 in2 = XEXP (XEXP (x, 1), 1);
4427 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4428 XEXP (XEXP (x, 0), 0));
4431 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4433 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4434 return gen_binary (MINUS, mode,
4435 gen_binary (MINUS, mode, XEXP (x, 0),
4436 XEXP (XEXP (x, 1), 0)),
4437 XEXP (XEXP (x, 1), 1));
4441 /* If we have (mult (plus A B) C), apply the distributive law and then
4442 the inverse distributive law to see if things simplify. This
4443 occurs mostly in addresses, often when unrolling loops. */
4445 if (GET_CODE (XEXP (x, 0)) == PLUS)
4447 x = apply_distributive_law
4448 (gen_binary (PLUS, mode,
4449 gen_binary (MULT, mode,
4450 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4451 gen_binary (MULT, mode,
4452 XEXP (XEXP (x, 0), 1),
4453 copy_rtx (XEXP (x, 1)))));
4455 if (GET_CODE (x) != MULT)
4458 /* Try simplify a*(b/c) as (a*b)/c. */
4459 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4460 && GET_CODE (XEXP (x, 0)) == DIV)
4462 rtx tem = simplify_binary_operation (MULT, mode,
4463 XEXP (XEXP (x, 0), 0),
4466 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4471 /* If this is a divide by a power of two, treat it as a shift if
4472 its first operand is a shift. */
4473 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4474 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4475 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4476 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4477 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4478 || GET_CODE (XEXP (x, 0)) == ROTATE
4479 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4480 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4484 case GT: case GTU: case GE: case GEU:
4485 case LT: case LTU: case LE: case LEU:
4486 case UNEQ: case LTGT:
4487 case UNGT: case UNGE:
4488 case UNLT: case UNLE:
4489 case UNORDERED: case ORDERED:
4490 /* If the first operand is a condition code, we can't do anything
4492 if (GET_CODE (XEXP (x, 0)) == COMPARE
4493 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4495 && XEXP (x, 0) != cc0_rtx
4499 rtx op0 = XEXP (x, 0);
4500 rtx op1 = XEXP (x, 1);
4501 enum rtx_code new_code;
4503 if (GET_CODE (op0) == COMPARE)
4504 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4506 /* Simplify our comparison, if possible. */
4507 new_code = simplify_comparison (code, &op0, &op1);
4509 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4510 if only the low-order bit is possibly nonzero in X (such as when
4511 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4512 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4513 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4516 Remove any ZERO_EXTRACT we made when thinking this was a
4517 comparison. It may now be simpler to use, e.g., an AND. If a
4518 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4519 the call to make_compound_operation in the SET case. */
4521 if (STORE_FLAG_VALUE == 1
4522 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4523 && op1 == const0_rtx
4524 && mode == GET_MODE (op0)
4525 && nonzero_bits (op0, mode) == 1)
4526 return gen_lowpart_for_combine (mode,
4527 expand_compound_operation (op0));
4529 else if (STORE_FLAG_VALUE == 1
4530 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4531 && op1 == const0_rtx
4532 && mode == GET_MODE (op0)
4533 && (num_sign_bit_copies (op0, mode)
4534 == GET_MODE_BITSIZE (mode)))
4536 op0 = expand_compound_operation (op0);
4537 return simplify_gen_unary (NEG, mode,
4538 gen_lowpart_for_combine (mode, op0),
4542 else if (STORE_FLAG_VALUE == 1
4543 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4544 && op1 == const0_rtx
4545 && mode == GET_MODE (op0)
4546 && nonzero_bits (op0, mode) == 1)
4548 op0 = expand_compound_operation (op0);
4549 return gen_binary (XOR, mode,
4550 gen_lowpart_for_combine (mode, op0),
4554 else if (STORE_FLAG_VALUE == 1
4555 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4556 && op1 == const0_rtx
4557 && mode == GET_MODE (op0)
4558 && (num_sign_bit_copies (op0, mode)
4559 == GET_MODE_BITSIZE (mode)))
4561 op0 = expand_compound_operation (op0);
4562 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4565 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4567 if (STORE_FLAG_VALUE == -1
4568 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4569 && op1 == const0_rtx
4570 && (num_sign_bit_copies (op0, mode)
4571 == GET_MODE_BITSIZE (mode)))
4572 return gen_lowpart_for_combine (mode,
4573 expand_compound_operation (op0));
4575 else if (STORE_FLAG_VALUE == -1
4576 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4577 && op1 == const0_rtx
4578 && mode == GET_MODE (op0)
4579 && nonzero_bits (op0, mode) == 1)
4581 op0 = expand_compound_operation (op0);
4582 return simplify_gen_unary (NEG, mode,
4583 gen_lowpart_for_combine (mode, op0),
4587 else if (STORE_FLAG_VALUE == -1
4588 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4589 && op1 == const0_rtx
4590 && mode == GET_MODE (op0)
4591 && (num_sign_bit_copies (op0, mode)
4592 == GET_MODE_BITSIZE (mode)))
4594 op0 = expand_compound_operation (op0);
4595 return simplify_gen_unary (NOT, mode,
4596 gen_lowpart_for_combine (mode, op0),
4600 /* If X is 0/1, (eq X 0) is X-1. */
4601 else if (STORE_FLAG_VALUE == -1
4602 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4603 && op1 == const0_rtx
4604 && mode == GET_MODE (op0)
4605 && nonzero_bits (op0, mode) == 1)
4607 op0 = expand_compound_operation (op0);
4608 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4611 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4612 one bit that might be nonzero, we can convert (ne x 0) to
4613 (ashift x c) where C puts the bit in the sign bit. Remove any
4614 AND with STORE_FLAG_VALUE when we are done, since we are only
4615 going to test the sign bit. */
4616 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4617 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4618 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4619 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4620 && op1 == const0_rtx
4621 && mode == GET_MODE (op0)
4622 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4624 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4625 expand_compound_operation (op0),
4626 GET_MODE_BITSIZE (mode) - 1 - i);
4627 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4633 /* If the code changed, return a whole new comparison. */
4634 if (new_code != code)
4635 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4637 /* Otherwise, keep this operation, but maybe change its operands.
4638 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4639 SUBST (XEXP (x, 0), op0);
4640 SUBST (XEXP (x, 1), op1);
4645 return simplify_if_then_else (x);
4651 /* If we are processing SET_DEST, we are done. */
4655 return expand_compound_operation (x);
4658 return simplify_set (x);
4663 return simplify_logical (x, last);
4666 /* (abs (neg <foo>)) -> (abs <foo>) */
4667 if (GET_CODE (XEXP (x, 0)) == NEG)
4668 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4670 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4672 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4675 /* If operand is something known to be positive, ignore the ABS. */
4676 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4677 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4678 <= HOST_BITS_PER_WIDE_INT)
4679 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4680 & ((HOST_WIDE_INT) 1
4681 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4685 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4686 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4687 return gen_rtx_NEG (mode, XEXP (x, 0));
4692 /* (ffs (*_extend <X>)) = (ffs <X>) */
4693 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4694 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4695 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4699 /* (float (sign_extend <X>)) = (float <X>). */
4700 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4701 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4709 /* If this is a shift by a constant amount, simplify it. */
4710 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4711 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4712 INTVAL (XEXP (x, 1)));
4714 #ifdef SHIFT_COUNT_TRUNCATED
4715 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4717 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4719 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4728 rtx op0 = XEXP (x, 0);
4729 rtx op1 = XEXP (x, 1);
4732 if (GET_CODE (op1) != PARALLEL)
4734 len = XVECLEN (op1, 0);
4736 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4737 && GET_CODE (op0) == VEC_CONCAT)
4739 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4741 /* Try to find the element in the VEC_CONCAT. */
4744 if (GET_MODE (op0) == GET_MODE (x))
4746 if (GET_CODE (op0) == VEC_CONCAT)
4748 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4749 if (op0_size < offset)
4750 op0 = XEXP (op0, 0);
4754 op0 = XEXP (op0, 1);
4772 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4775 simplify_if_then_else (x)
4778 enum machine_mode mode = GET_MODE (x);
4779 rtx cond = XEXP (x, 0);
4780 rtx true_rtx = XEXP (x, 1);
4781 rtx false_rtx = XEXP (x, 2);
4782 enum rtx_code true_code = GET_CODE (cond);
4783 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4786 enum rtx_code false_code;
4789 /* Simplify storing of the truth value. */
4790 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4791 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4793 /* Also when the truth value has to be reversed. */
4795 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4796 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4800 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4801 in it is being compared against certain values. Get the true and false
4802 comparisons and see if that says anything about the value of each arm. */
4805 && ((false_code = combine_reversed_comparison_code (cond))
4807 && GET_CODE (XEXP (cond, 0)) == REG)
4810 rtx from = XEXP (cond, 0);
4811 rtx true_val = XEXP (cond, 1);
4812 rtx false_val = true_val;
4815 /* If FALSE_CODE is EQ, swap the codes and arms. */
4817 if (false_code == EQ)
4819 swapped = 1, true_code = EQ, false_code = NE;
4820 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4823 /* If we are comparing against zero and the expression being tested has
4824 only a single bit that might be nonzero, that is its value when it is
4825 not equal to zero. Similarly if it is known to be -1 or 0. */
4827 if (true_code == EQ && true_val == const0_rtx
4828 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4829 false_code = EQ, false_val = GEN_INT (nzb);
4830 else if (true_code == EQ && true_val == const0_rtx
4831 && (num_sign_bit_copies (from, GET_MODE (from))
4832 == GET_MODE_BITSIZE (GET_MODE (from))))
4833 false_code = EQ, false_val = constm1_rtx;
4835 /* Now simplify an arm if we know the value of the register in the
4836 branch and it is used in the arm. Be careful due to the potential
4837 of locally-shared RTL. */
4839 if (reg_mentioned_p (from, true_rtx))
4840 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4842 pc_rtx, pc_rtx, 0, 0);
4843 if (reg_mentioned_p (from, false_rtx))
4844 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4846 pc_rtx, pc_rtx, 0, 0);
4848 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4849 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4851 true_rtx = XEXP (x, 1);
4852 false_rtx = XEXP (x, 2);
4853 true_code = GET_CODE (cond);
4856 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4857 reversed, do so to avoid needing two sets of patterns for
4858 subtract-and-branch insns. Similarly if we have a constant in the true
4859 arm, the false arm is the same as the first operand of the comparison, or
4860 the false arm is more complicated than the true arm. */
4863 && combine_reversed_comparison_code (cond) != UNKNOWN
4864 && (true_rtx == pc_rtx
4865 || (CONSTANT_P (true_rtx)
4866 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4867 || true_rtx == const0_rtx
4868 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4869 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4870 || (GET_CODE (true_rtx) == SUBREG
4871 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4872 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4873 || reg_mentioned_p (true_rtx, false_rtx)
4874 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4876 true_code = reversed_comparison_code (cond, NULL);
4878 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4881 SUBST (XEXP (x, 1), false_rtx);
4882 SUBST (XEXP (x, 2), true_rtx);
4884 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4887 /* It is possible that the conditional has been simplified out. */
4888 true_code = GET_CODE (cond);
4889 comparison_p = GET_RTX_CLASS (true_code) == '<';
4892 /* If the two arms are identical, we don't need the comparison. */
4894 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4897 /* Convert a == b ? b : a to "a". */
4898 if (true_code == EQ && ! side_effects_p (cond)
4899 && !HONOR_NANS (mode)
4900 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4901 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4903 else if (true_code == NE && ! side_effects_p (cond)
4904 && !HONOR_NANS (mode)
4905 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4906 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4909 /* Look for cases where we have (abs x) or (neg (abs X)). */
4911 if (GET_MODE_CLASS (mode) == MODE_INT
4912 && GET_CODE (false_rtx) == NEG
4913 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4915 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4916 && ! side_effects_p (true_rtx))
4921 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4925 simplify_gen_unary (NEG, mode,
4926 simplify_gen_unary (ABS, mode, true_rtx, mode),
4932 /* Look for MIN or MAX. */
4934 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4936 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4937 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4938 && ! side_effects_p (cond))
4943 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4946 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4949 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4952 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4957 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4958 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4959 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4960 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4961 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4962 neither 1 or -1, but it isn't worth checking for. */
4964 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4966 && GET_MODE_CLASS (mode) == MODE_INT
4967 && ! side_effects_p (x))
4969 rtx t = make_compound_operation (true_rtx, SET);
4970 rtx f = make_compound_operation (false_rtx, SET);
4971 rtx cond_op0 = XEXP (cond, 0);
4972 rtx cond_op1 = XEXP (cond, 1);
4973 enum rtx_code op = NIL, extend_op = NIL;
4974 enum machine_mode m = mode;
4975 rtx z = 0, c1 = NULL_RTX;
4977 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4978 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4979 || GET_CODE (t) == ASHIFT
4980 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4981 && rtx_equal_p (XEXP (t, 0), f))
4982 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4984 /* If an identity-zero op is commutative, check whether there
4985 would be a match if we swapped the operands. */
4986 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4987 || GET_CODE (t) == XOR)
4988 && rtx_equal_p (XEXP (t, 1), f))
4989 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4990 else if (GET_CODE (t) == SIGN_EXTEND
4991 && (GET_CODE (XEXP (t, 0)) == PLUS
4992 || GET_CODE (XEXP (t, 0)) == MINUS
4993 || GET_CODE (XEXP (t, 0)) == IOR
4994 || GET_CODE (XEXP (t, 0)) == XOR
4995 || GET_CODE (XEXP (t, 0)) == ASHIFT
4996 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4997 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4998 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4999 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5000 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5001 && (num_sign_bit_copies (f, GET_MODE (f))
5003 (GET_MODE_BITSIZE (mode)
5004 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5006 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5007 extend_op = SIGN_EXTEND;
5008 m = GET_MODE (XEXP (t, 0));
5010 else if (GET_CODE (t) == SIGN_EXTEND
5011 && (GET_CODE (XEXP (t, 0)) == PLUS
5012 || GET_CODE (XEXP (t, 0)) == IOR
5013 || GET_CODE (XEXP (t, 0)) == XOR)
5014 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5015 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5016 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5017 && (num_sign_bit_copies (f, GET_MODE (f))
5019 (GET_MODE_BITSIZE (mode)
5020 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5022 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5023 extend_op = SIGN_EXTEND;
5024 m = GET_MODE (XEXP (t, 0));
5026 else if (GET_CODE (t) == ZERO_EXTEND
5027 && (GET_CODE (XEXP (t, 0)) == PLUS
5028 || GET_CODE (XEXP (t, 0)) == MINUS
5029 || GET_CODE (XEXP (t, 0)) == IOR
5030 || GET_CODE (XEXP (t, 0)) == XOR
5031 || GET_CODE (XEXP (t, 0)) == ASHIFT
5032 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5033 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5034 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5035 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5036 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5037 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5038 && ((nonzero_bits (f, GET_MODE (f))
5039 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5042 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5043 extend_op = ZERO_EXTEND;
5044 m = GET_MODE (XEXP (t, 0));
5046 else if (GET_CODE (t) == ZERO_EXTEND
5047 && (GET_CODE (XEXP (t, 0)) == PLUS
5048 || GET_CODE (XEXP (t, 0)) == IOR
5049 || GET_CODE (XEXP (t, 0)) == XOR)
5050 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5051 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5052 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5053 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5054 && ((nonzero_bits (f, GET_MODE (f))
5055 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5058 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5059 extend_op = ZERO_EXTEND;
5060 m = GET_MODE (XEXP (t, 0));
5065 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5066 pc_rtx, pc_rtx, 0, 0);
5067 temp = gen_binary (MULT, m, temp,
5068 gen_binary (MULT, m, c1, const_true_rtx));
5069 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5070 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
5072 if (extend_op != NIL)
5073 temp = simplify_gen_unary (extend_op, mode, temp, m);
5079 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5080 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5081 negation of a single bit, we can convert this operation to a shift. We
5082 can actually do this more generally, but it doesn't seem worth it. */
5084 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5085 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5086 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5087 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5088 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5089 == GET_MODE_BITSIZE (mode))
5090 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5092 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5093 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
5098 /* Simplify X, a SET expression. Return the new expression. */
5104 rtx src = SET_SRC (x);
5105 rtx dest = SET_DEST (x);
5106 enum machine_mode mode
5107 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5111 /* (set (pc) (return)) gets written as (return). */
5112 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5115 /* Now that we know for sure which bits of SRC we are using, see if we can
5116 simplify the expression for the object knowing that we only need the
5119 if (GET_MODE_CLASS (mode) == MODE_INT
5120 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5122 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5123 SUBST (SET_SRC (x), src);
5126 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5127 the comparison result and try to simplify it unless we already have used
5128 undobuf.other_insn. */
5129 if ((GET_MODE_CLASS (mode) == MODE_CC
5130 || GET_CODE (src) == COMPARE
5132 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5133 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5134 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5135 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5137 enum rtx_code old_code = GET_CODE (*cc_use);
5138 enum rtx_code new_code;
5140 int other_changed = 0;
5141 enum machine_mode compare_mode = GET_MODE (dest);
5142 enum machine_mode tmp_mode;
5144 if (GET_CODE (src) == COMPARE)
5145 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5147 op0 = src, op1 = const0_rtx;
5149 /* Check whether the comparison is known at compile time. */
5150 if (GET_MODE (op0) != VOIDmode)
5151 tmp_mode = GET_MODE (op0);
5152 else if (GET_MODE (op1) != VOIDmode)
5153 tmp_mode = GET_MODE (op1);
5155 tmp_mode = compare_mode;
5156 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5157 if (tmp != NULL_RTX)
5159 rtx pat = PATTERN (other_insn);
5160 undobuf.other_insn = other_insn;
5161 SUBST (*cc_use, tmp);
5163 /* Attempt to simplify CC user. */
5164 if (GET_CODE (pat) == SET)
5166 rtx new = simplify_rtx (SET_SRC (pat));
5167 if (new != NULL_RTX)
5168 SUBST (SET_SRC (pat), new);
5171 /* Convert X into a no-op move. */
5172 SUBST (SET_DEST (x), pc_rtx);
5173 SUBST (SET_SRC (x), pc_rtx);
5177 /* Simplify our comparison, if possible. */
5178 new_code = simplify_comparison (old_code, &op0, &op1);
5180 #ifdef EXTRA_CC_MODES
5181 /* If this machine has CC modes other than CCmode, check to see if we
5182 need to use a different CC mode here. */
5183 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5184 #endif /* EXTRA_CC_MODES */
5186 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5187 /* If the mode changed, we have to change SET_DEST, the mode in the
5188 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5189 a hard register, just build new versions with the proper mode. If it
5190 is a pseudo, we lose unless it is only time we set the pseudo, in
5191 which case we can safely change its mode. */
5192 if (compare_mode != GET_MODE (dest))
5194 unsigned int regno = REGNO (dest);
5195 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5197 if (regno < FIRST_PSEUDO_REGISTER
5198 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5200 if (regno >= FIRST_PSEUDO_REGISTER)
5201 SUBST (regno_reg_rtx[regno], new_dest);
5203 SUBST (SET_DEST (x), new_dest);
5204 SUBST (XEXP (*cc_use, 0), new_dest);
5212 /* If the code changed, we have to build a new comparison in
5213 undobuf.other_insn. */
5214 if (new_code != old_code)
5216 unsigned HOST_WIDE_INT mask;
5218 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5221 /* If the only change we made was to change an EQ into an NE or
5222 vice versa, OP0 has only one bit that might be nonzero, and OP1
5223 is zero, check if changing the user of the condition code will
5224 produce a valid insn. If it won't, we can keep the original code
5225 in that insn by surrounding our operation with an XOR. */
5227 if (((old_code == NE && new_code == EQ)
5228 || (old_code == EQ && new_code == NE))
5229 && ! other_changed && op1 == const0_rtx
5230 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5231 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5233 rtx pat = PATTERN (other_insn), note = 0;
5235 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5236 && ! check_asm_operands (pat)))
5238 PUT_CODE (*cc_use, old_code);
5241 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5249 undobuf.other_insn = other_insn;
5252 /* If we are now comparing against zero, change our source if
5253 needed. If we do not use cc0, we always have a COMPARE. */
5254 if (op1 == const0_rtx && dest == cc0_rtx)
5256 SUBST (SET_SRC (x), op0);
5262 /* Otherwise, if we didn't previously have a COMPARE in the
5263 correct mode, we need one. */
5264 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5266 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5271 /* Otherwise, update the COMPARE if needed. */
5272 SUBST (XEXP (src, 0), op0);
5273 SUBST (XEXP (src, 1), op1);
5278 /* Get SET_SRC in a form where we have placed back any
5279 compound expressions. Then do the checks below. */
5280 src = make_compound_operation (src, SET);
5281 SUBST (SET_SRC (x), src);
5284 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5285 and X being a REG or (subreg (reg)), we may be able to convert this to
5286 (set (subreg:m2 x) (op)).
5288 We can always do this if M1 is narrower than M2 because that means that
5289 we only care about the low bits of the result.
5291 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5292 perform a narrower operation than requested since the high-order bits will
5293 be undefined. On machine where it is defined, this transformation is safe
5294 as long as M1 and M2 have the same number of words. */
5296 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5297 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5298 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5300 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5301 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5302 #ifndef WORD_REGISTER_OPERATIONS
5303 && (GET_MODE_SIZE (GET_MODE (src))
5304 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5306 #ifdef CANNOT_CHANGE_MODE_CLASS
5307 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5308 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5309 GET_MODE (SUBREG_REG (src)),
5312 && (GET_CODE (dest) == REG
5313 || (GET_CODE (dest) == SUBREG
5314 && GET_CODE (SUBREG_REG (dest)) == REG)))
5316 SUBST (SET_DEST (x),
5317 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5319 SUBST (SET_SRC (x), SUBREG_REG (src));
5321 src = SET_SRC (x), dest = SET_DEST (x);
5325 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5328 && GET_CODE (src) == SUBREG
5329 && subreg_lowpart_p (src)
5330 && (GET_MODE_BITSIZE (GET_MODE (src))
5331 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5333 rtx inner = SUBREG_REG (src);
5334 enum machine_mode inner_mode = GET_MODE (inner);
5336 /* Here we make sure that we don't have a sign bit on. */
5337 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5338 && (nonzero_bits (inner, inner_mode)
5339 < ((unsigned HOST_WIDE_INT) 1
5340 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5342 SUBST (SET_SRC (x), inner);
5348 #ifdef LOAD_EXTEND_OP
5349 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5350 would require a paradoxical subreg. Replace the subreg with a
5351 zero_extend to avoid the reload that would otherwise be required. */
5353 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5354 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5355 && SUBREG_BYTE (src) == 0
5356 && (GET_MODE_SIZE (GET_MODE (src))
5357 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5358 && GET_CODE (SUBREG_REG (src)) == MEM)
5361 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5362 GET_MODE (src), SUBREG_REG (src)));
5368 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5369 are comparing an item known to be 0 or -1 against 0, use a logical
5370 operation instead. Check for one of the arms being an IOR of the other
5371 arm with some value. We compute three terms to be IOR'ed together. In
5372 practice, at most two will be nonzero. Then we do the IOR's. */
5374 if (GET_CODE (dest) != PC
5375 && GET_CODE (src) == IF_THEN_ELSE
5376 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5377 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5378 && XEXP (XEXP (src, 0), 1) == const0_rtx
5379 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5380 #ifdef HAVE_conditional_move
5381 && ! can_conditionally_move_p (GET_MODE (src))
5383 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5384 GET_MODE (XEXP (XEXP (src, 0), 0)))
5385 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5386 && ! side_effects_p (src))
5388 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5389 ? XEXP (src, 1) : XEXP (src, 2));
5390 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5391 ? XEXP (src, 2) : XEXP (src, 1));
5392 rtx term1 = const0_rtx, term2, term3;
5394 if (GET_CODE (true_rtx) == IOR
5395 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5396 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5397 else if (GET_CODE (true_rtx) == IOR
5398 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5399 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5400 else if (GET_CODE (false_rtx) == IOR
5401 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5402 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5403 else if (GET_CODE (false_rtx) == IOR
5404 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5405 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5407 term2 = gen_binary (AND, GET_MODE (src),
5408 XEXP (XEXP (src, 0), 0), true_rtx);
5409 term3 = gen_binary (AND, GET_MODE (src),
5410 simplify_gen_unary (NOT, GET_MODE (src),
5411 XEXP (XEXP (src, 0), 0),
5416 gen_binary (IOR, GET_MODE (src),
5417 gen_binary (IOR, GET_MODE (src), term1, term2),
5423 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5424 whole thing fail. */
5425 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5427 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5430 /* Convert this into a field assignment operation, if possible. */
5431 return make_field_assignment (x);
5434 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5435 result. LAST is nonzero if this is the last retry. */
5438 simplify_logical (x, last)
5442 enum machine_mode mode = GET_MODE (x);
5443 rtx op0 = XEXP (x, 0);
5444 rtx op1 = XEXP (x, 1);
5447 switch (GET_CODE (x))
5450 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5451 insn (and may simplify more). */
5452 if (GET_CODE (op0) == XOR
5453 && rtx_equal_p (XEXP (op0, 0), op1)
5454 && ! side_effects_p (op1))
5455 x = gen_binary (AND, mode,
5456 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5459 if (GET_CODE (op0) == XOR
5460 && rtx_equal_p (XEXP (op0, 1), op1)
5461 && ! side_effects_p (op1))
5462 x = gen_binary (AND, mode,
5463 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5466 /* Similarly for (~(A ^ B)) & A. */
5467 if (GET_CODE (op0) == NOT
5468 && GET_CODE (XEXP (op0, 0)) == XOR
5469 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5470 && ! side_effects_p (op1))
5471 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5473 if (GET_CODE (op0) == NOT
5474 && GET_CODE (XEXP (op0, 0)) == XOR
5475 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5476 && ! side_effects_p (op1))
5477 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5479 /* We can call simplify_and_const_int only if we don't lose
5480 any (sign) bits when converting INTVAL (op1) to
5481 "unsigned HOST_WIDE_INT". */
5482 if (GET_CODE (op1) == CONST_INT
5483 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5484 || INTVAL (op1) > 0))
5486 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5488 /* If we have (ior (and (X C1) C2)) and the next restart would be
5489 the last, simplify this by making C1 as small as possible
5492 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5493 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5494 && GET_CODE (op1) == CONST_INT)
5495 return gen_binary (IOR, mode,
5496 gen_binary (AND, mode, XEXP (op0, 0),
5497 GEN_INT (INTVAL (XEXP (op0, 1))
5498 & ~INTVAL (op1))), op1);
5500 if (GET_CODE (x) != AND)
5503 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5504 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5505 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5508 /* Convert (A | B) & A to A. */
5509 if (GET_CODE (op0) == IOR
5510 && (rtx_equal_p (XEXP (op0, 0), op1)
5511 || rtx_equal_p (XEXP (op0, 1), op1))
5512 && ! side_effects_p (XEXP (op0, 0))
5513 && ! side_effects_p (XEXP (op0, 1)))
5516 /* In the following group of tests (and those in case IOR below),
5517 we start with some combination of logical operations and apply
5518 the distributive law followed by the inverse distributive law.
5519 Most of the time, this results in no change. However, if some of
5520 the operands are the same or inverses of each other, simplifications
5523 For example, (and (ior A B) (not B)) can occur as the result of
5524 expanding a bit field assignment. When we apply the distributive
5525 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5526 which then simplifies to (and (A (not B))).
5528 If we have (and (ior A B) C), apply the distributive law and then
5529 the inverse distributive law to see if things simplify. */
5531 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5533 x = apply_distributive_law
5534 (gen_binary (GET_CODE (op0), mode,
5535 gen_binary (AND, mode, XEXP (op0, 0), op1),
5536 gen_binary (AND, mode, XEXP (op0, 1),
5538 if (GET_CODE (x) != AND)
5542 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5543 return apply_distributive_law
5544 (gen_binary (GET_CODE (op1), mode,
5545 gen_binary (AND, mode, XEXP (op1, 0), op0),
5546 gen_binary (AND, mode, XEXP (op1, 1),
5549 /* Similarly, taking advantage of the fact that
5550 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5552 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5553 return apply_distributive_law
5554 (gen_binary (XOR, mode,
5555 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5556 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5559 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5560 return apply_distributive_law
5561 (gen_binary (XOR, mode,
5562 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5563 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5567 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5568 if (GET_CODE (op1) == CONST_INT
5569 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5570 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5573 /* Convert (A & B) | A to A. */
5574 if (GET_CODE (op0) == AND
5575 && (rtx_equal_p (XEXP (op0, 0), op1)
5576 || rtx_equal_p (XEXP (op0, 1), op1))
5577 && ! side_effects_p (XEXP (op0, 0))
5578 && ! side_effects_p (XEXP (op0, 1)))
5581 /* If we have (ior (and A B) C), apply the distributive law and then
5582 the inverse distributive law to see if things simplify. */
5584 if (GET_CODE (op0) == AND)
5586 x = apply_distributive_law
5587 (gen_binary (AND, mode,
5588 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5589 gen_binary (IOR, mode, XEXP (op0, 1),
5592 if (GET_CODE (x) != IOR)
5596 if (GET_CODE (op1) == AND)
5598 x = apply_distributive_law
5599 (gen_binary (AND, mode,
5600 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5601 gen_binary (IOR, mode, XEXP (op1, 1),
5604 if (GET_CODE (x) != IOR)
5608 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5609 mode size to (rotate A CX). */
5611 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5612 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5613 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5614 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5615 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5616 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5617 == GET_MODE_BITSIZE (mode)))
5618 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5619 (GET_CODE (op0) == ASHIFT
5620 ? XEXP (op0, 1) : XEXP (op1, 1)));
5622 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5623 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5624 does not affect any of the bits in OP1, it can really be done
5625 as a PLUS and we can associate. We do this by seeing if OP1
5626 can be safely shifted left C bits. */
5627 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5628 && GET_CODE (XEXP (op0, 0)) == PLUS
5629 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5630 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5631 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5633 int count = INTVAL (XEXP (op0, 1));
5634 HOST_WIDE_INT mask = INTVAL (op1) << count;
5636 if (mask >> count == INTVAL (op1)
5637 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5639 SUBST (XEXP (XEXP (op0, 0), 1),
5640 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5647 /* If we are XORing two things that have no bits in common,
5648 convert them into an IOR. This helps to detect rotation encoded
5649 using those methods and possibly other simplifications. */
5651 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5652 && (nonzero_bits (op0, mode)
5653 & nonzero_bits (op1, mode)) == 0)
5654 return (gen_binary (IOR, mode, op0, op1));
5656 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5657 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5660 int num_negated = 0;
5662 if (GET_CODE (op0) == NOT)
5663 num_negated++, op0 = XEXP (op0, 0);
5664 if (GET_CODE (op1) == NOT)
5665 num_negated++, op1 = XEXP (op1, 0);
5667 if (num_negated == 2)
5669 SUBST (XEXP (x, 0), op0);
5670 SUBST (XEXP (x, 1), op1);
5672 else if (num_negated == 1)
5674 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5678 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5679 correspond to a machine insn or result in further simplifications
5680 if B is a constant. */
5682 if (GET_CODE (op0) == AND
5683 && rtx_equal_p (XEXP (op0, 1), op1)
5684 && ! side_effects_p (op1))
5685 return gen_binary (AND, mode,
5686 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5689 else if (GET_CODE (op0) == AND
5690 && rtx_equal_p (XEXP (op0, 0), op1)
5691 && ! side_effects_p (op1))
5692 return gen_binary (AND, mode,
5693 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5696 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5697 comparison if STORE_FLAG_VALUE is 1. */
5698 if (STORE_FLAG_VALUE == 1
5699 && op1 == const1_rtx
5700 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5701 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5705 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5706 is (lt foo (const_int 0)), so we can perform the above
5707 simplification if STORE_FLAG_VALUE is 1. */
5709 if (STORE_FLAG_VALUE == 1
5710 && op1 == const1_rtx
5711 && GET_CODE (op0) == LSHIFTRT
5712 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5713 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5714 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5716 /* (xor (comparison foo bar) (const_int sign-bit))
5717 when STORE_FLAG_VALUE is the sign bit. */
5718 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5719 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5720 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5721 && op1 == const_true_rtx
5722 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5723 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5736 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5737 operations" because they can be replaced with two more basic operations.
5738 ZERO_EXTEND is also considered "compound" because it can be replaced with
5739 an AND operation, which is simpler, though only one operation.
5741 The function expand_compound_operation is called with an rtx expression
5742 and will convert it to the appropriate shifts and AND operations,
5743 simplifying at each stage.
5745 The function make_compound_operation is called to convert an expression
5746 consisting of shifts and ANDs into the equivalent compound expression.
5747 It is the inverse of this function, loosely speaking. */
5750 expand_compound_operation (x)
5753 unsigned HOST_WIDE_INT pos = 0, len;
5755 unsigned int modewidth;
5758 switch (GET_CODE (x))
5763 /* We can't necessarily use a const_int for a multiword mode;
5764 it depends on implicitly extending the value.
5765 Since we don't know the right way to extend it,
5766 we can't tell whether the implicit way is right.
5768 Even for a mode that is no wider than a const_int,
5769 we can't win, because we need to sign extend one of its bits through
5770 the rest of it, and we don't know which bit. */
5771 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5774 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5775 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5776 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5777 reloaded. If not for that, MEM's would very rarely be safe.
5779 Reject MODEs bigger than a word, because we might not be able
5780 to reference a two-register group starting with an arbitrary register
5781 (and currently gen_lowpart might crash for a SUBREG). */
5783 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5786 /* Reject MODEs that aren't scalar integers because turning vector
5787 or complex modes into shifts causes problems. */
5789 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5792 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5793 /* If the inner object has VOIDmode (the only way this can happen
5794 is if it is an ASM_OPERANDS), we can't do anything since we don't
5795 know how much masking to do. */
5804 /* If the operand is a CLOBBER, just return it. */
5805 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5808 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5809 || GET_CODE (XEXP (x, 2)) != CONST_INT
5810 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5813 /* Reject MODEs that aren't scalar integers because turning vector
5814 or complex modes into shifts causes problems. */
5816 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5819 len = INTVAL (XEXP (x, 1));
5820 pos = INTVAL (XEXP (x, 2));
5822 /* If this goes outside the object being extracted, replace the object
5823 with a (use (mem ...)) construct that only combine understands
5824 and is used only for this purpose. */
5825 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5826 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5828 if (BITS_BIG_ENDIAN)
5829 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5836 /* Convert sign extension to zero extension, if we know that the high
5837 bit is not set, as this is easier to optimize. It will be converted
5838 back to cheaper alternative in make_extraction. */
5839 if (GET_CODE (x) == SIGN_EXTEND
5840 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5841 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5842 & ~(((unsigned HOST_WIDE_INT)
5843 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5847 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5848 return expand_compound_operation (temp);
5851 /* We can optimize some special cases of ZERO_EXTEND. */
5852 if (GET_CODE (x) == ZERO_EXTEND)
5854 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5855 know that the last value didn't have any inappropriate bits
5857 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5858 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5859 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5860 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5861 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5862 return XEXP (XEXP (x, 0), 0);
5864 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5865 if (GET_CODE (XEXP (x, 0)) == SUBREG
5866 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5867 && subreg_lowpart_p (XEXP (x, 0))
5868 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5869 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5870 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5871 return SUBREG_REG (XEXP (x, 0));
5873 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5874 is a comparison and STORE_FLAG_VALUE permits. This is like
5875 the first case, but it works even when GET_MODE (x) is larger
5876 than HOST_WIDE_INT. */
5877 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5878 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5879 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5880 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5881 <= HOST_BITS_PER_WIDE_INT)
5882 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5883 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5884 return XEXP (XEXP (x, 0), 0);
5886 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5887 if (GET_CODE (XEXP (x, 0)) == SUBREG
5888 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5889 && subreg_lowpart_p (XEXP (x, 0))
5890 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5891 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5892 <= HOST_BITS_PER_WIDE_INT)
5893 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5894 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5895 return SUBREG_REG (XEXP (x, 0));
5899 /* If we reach here, we want to return a pair of shifts. The inner
5900 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5901 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5902 logical depending on the value of UNSIGNEDP.
5904 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5905 converted into an AND of a shift.
5907 We must check for the case where the left shift would have a negative
5908 count. This can happen in a case like (x >> 31) & 255 on machines
5909 that can't shift by a constant. On those machines, we would first
5910 combine the shift with the AND to produce a variable-position
5911 extraction. Then the constant of 31 would be substituted in to produce
5912 a such a position. */
5914 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5915 if (modewidth + len >= pos)
5916 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5918 simplify_shift_const (NULL_RTX, ASHIFT,
5921 modewidth - pos - len),
5924 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5925 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5926 simplify_shift_const (NULL_RTX, LSHIFTRT,
5929 ((HOST_WIDE_INT) 1 << len) - 1);
5931 /* Any other cases we can't handle. */
5934 /* If we couldn't do this for some reason, return the original
5936 if (GET_CODE (tem) == CLOBBER)
5942 /* X is a SET which contains an assignment of one object into
5943 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5944 or certain SUBREGS). If possible, convert it into a series of
5947 We half-heartedly support variable positions, but do not at all
5948 support variable lengths. */
5951 expand_field_assignment (x)
5955 rtx pos; /* Always counts from low bit. */
5958 enum machine_mode compute_mode;
5960 /* Loop until we find something we can't simplify. */
5963 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5964 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5966 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5967 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5968 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5970 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5971 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5973 inner = XEXP (SET_DEST (x), 0);
5974 len = INTVAL (XEXP (SET_DEST (x), 1));
5975 pos = XEXP (SET_DEST (x), 2);
5977 /* If the position is constant and spans the width of INNER,
5978 surround INNER with a USE to indicate this. */
5979 if (GET_CODE (pos) == CONST_INT
5980 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5981 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5983 if (BITS_BIG_ENDIAN)
5985 if (GET_CODE (pos) == CONST_INT)
5986 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5988 else if (GET_CODE (pos) == MINUS
5989 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5990 && (INTVAL (XEXP (pos, 1))
5991 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5992 /* If position is ADJUST - X, new position is X. */
5993 pos = XEXP (pos, 0);
5995 pos = gen_binary (MINUS, GET_MODE (pos),
5996 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
6002 /* A SUBREG between two modes that occupy the same numbers of words
6003 can be done by moving the SUBREG to the source. */
6004 else if (GET_CODE (SET_DEST (x)) == SUBREG
6005 /* We need SUBREGs to compute nonzero_bits properly. */
6006 && nonzero_sign_valid
6007 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6008 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6009 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6010 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6012 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6013 gen_lowpart_for_combine
6014 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6021 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6022 inner = SUBREG_REG (inner);
6024 compute_mode = GET_MODE (inner);
6026 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6027 if (! SCALAR_INT_MODE_P (compute_mode))
6029 enum machine_mode imode;
6031 /* Don't do anything for vector or complex integral types. */
6032 if (! FLOAT_MODE_P (compute_mode))
6035 /* Try to find an integral mode to pun with. */
6036 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6037 if (imode == BLKmode)
6040 compute_mode = imode;
6041 inner = gen_lowpart_for_combine (imode, inner);
6044 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6045 if (len < HOST_BITS_PER_WIDE_INT)
6046 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6050 /* Now compute the equivalent expression. Make a copy of INNER
6051 for the SET_DEST in case it is a MEM into which we will substitute;
6052 we don't want shared RTL in that case. */
6054 (VOIDmode, copy_rtx (inner),
6055 gen_binary (IOR, compute_mode,
6056 gen_binary (AND, compute_mode,
6057 simplify_gen_unary (NOT, compute_mode,
6063 gen_binary (ASHIFT, compute_mode,
6064 gen_binary (AND, compute_mode,
6065 gen_lowpart_for_combine
6066 (compute_mode, SET_SRC (x)),
6074 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6075 it is an RTX that represents a variable starting position; otherwise,
6076 POS is the (constant) starting bit position (counted from the LSB).
6078 INNER may be a USE. This will occur when we started with a bitfield
6079 that went outside the boundary of the object in memory, which is
6080 allowed on most machines. To isolate this case, we produce a USE
6081 whose mode is wide enough and surround the MEM with it. The only
6082 code that understands the USE is this routine. If it is not removed,
6083 it will cause the resulting insn not to match.
6085 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6088 IN_DEST is nonzero if this is a reference in the destination of a
6089 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6090 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6093 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6094 ZERO_EXTRACT should be built even for bits starting at bit 0.
6096 MODE is the desired mode of the result (if IN_DEST == 0).
6098 The result is an RTX for the extraction or NULL_RTX if the target
6102 make_extraction (mode, inner, pos, pos_rtx, len,
6103 unsignedp, in_dest, in_compare)
6104 enum machine_mode mode;
6108 unsigned HOST_WIDE_INT len;
6110 int in_dest, in_compare;
6112 /* This mode describes the size of the storage area
6113 to fetch the overall value from. Within that, we
6114 ignore the POS lowest bits, etc. */
6115 enum machine_mode is_mode = GET_MODE (inner);
6116 enum machine_mode inner_mode;
6117 enum machine_mode wanted_inner_mode = byte_mode;
6118 enum machine_mode wanted_inner_reg_mode = word_mode;
6119 enum machine_mode pos_mode = word_mode;
6120 enum machine_mode extraction_mode = word_mode;
6121 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6124 rtx orig_pos_rtx = pos_rtx;
6125 HOST_WIDE_INT orig_pos;
6127 /* Get some information about INNER and get the innermost object. */
6128 if (GET_CODE (inner) == USE)
6129 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6130 /* We don't need to adjust the position because we set up the USE
6131 to pretend that it was a full-word object. */
6132 spans_byte = 1, inner = XEXP (inner, 0);
6133 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6135 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6136 consider just the QI as the memory to extract from.
6137 The subreg adds or removes high bits; its mode is
6138 irrelevant to the meaning of this extraction,
6139 since POS and LEN count from the lsb. */
6140 if (GET_CODE (SUBREG_REG (inner)) == MEM)
6141 is_mode = GET_MODE (SUBREG_REG (inner));
6142 inner = SUBREG_REG (inner);
6144 else if (GET_CODE (inner) == ASHIFT
6145 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6146 && pos_rtx == 0 && pos == 0
6147 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6149 /* We're extracting the least significant bits of an rtx
6150 (ashift X (const_int C)), where LEN > C. Extract the
6151 least significant (LEN - C) bits of X, giving an rtx
6152 whose mode is MODE, then shift it left C times. */
6153 new = make_extraction (mode, XEXP (inner, 0),
6154 0, 0, len - INTVAL (XEXP (inner, 1)),
6155 unsignedp, in_dest, in_compare);
6157 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6160 inner_mode = GET_MODE (inner);
6162 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6163 pos = INTVAL (pos_rtx), pos_rtx = 0;
6165 /* See if this can be done without an extraction. We never can if the
6166 width of the field is not the same as that of some integer mode. For
6167 registers, we can only avoid the extraction if the position is at the
6168 low-order bit and this is either not in the destination or we have the
6169 appropriate STRICT_LOW_PART operation available.
6171 For MEM, we can avoid an extract if the field starts on an appropriate
6172 boundary and we can change the mode of the memory reference. However,
6173 we cannot directly access the MEM if we have a USE and the underlying
6174 MEM is not TMODE. This combination means that MEM was being used in a
6175 context where bits outside its mode were being referenced; that is only
6176 valid in bit-field insns. */
6178 if (tmode != BLKmode
6179 && ! (spans_byte && inner_mode != tmode)
6180 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6181 && GET_CODE (inner) != MEM
6183 || (GET_CODE (inner) == REG
6184 && have_insn_for (STRICT_LOW_PART, tmode))))
6185 || (GET_CODE (inner) == MEM && pos_rtx == 0
6187 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6188 : BITS_PER_UNIT)) == 0
6189 /* We can't do this if we are widening INNER_MODE (it
6190 may not be aligned, for one thing). */
6191 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6192 && (inner_mode == tmode
6193 || (! mode_dependent_address_p (XEXP (inner, 0))
6194 && ! MEM_VOLATILE_P (inner))))))
6196 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6197 field. If the original and current mode are the same, we need not
6198 adjust the offset. Otherwise, we do if bytes big endian.
6200 If INNER is not a MEM, get a piece consisting of just the field
6201 of interest (in this case POS % BITS_PER_WORD must be 0). */
6203 if (GET_CODE (inner) == MEM)
6205 HOST_WIDE_INT offset;
6207 /* POS counts from lsb, but make OFFSET count in memory order. */
6208 if (BYTES_BIG_ENDIAN)
6209 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6211 offset = pos / BITS_PER_UNIT;
6213 new = adjust_address_nv (inner, tmode, offset);
6215 else if (GET_CODE (inner) == REG)
6217 /* We can't call gen_lowpart_for_combine here since we always want
6218 a SUBREG and it would sometimes return a new hard register. */
6219 if (tmode != inner_mode)
6221 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6223 if (WORDS_BIG_ENDIAN
6224 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6225 final_word = ((GET_MODE_SIZE (inner_mode)
6226 - GET_MODE_SIZE (tmode))
6227 / UNITS_PER_WORD) - final_word;
6229 final_word *= UNITS_PER_WORD;
6230 if (BYTES_BIG_ENDIAN &&
6231 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6232 final_word += (GET_MODE_SIZE (inner_mode)
6233 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6235 /* Avoid creating invalid subregs, for example when
6236 simplifying (x>>32)&255. */
6237 if (final_word >= GET_MODE_SIZE (inner_mode))
6240 new = gen_rtx_SUBREG (tmode, inner, final_word);
6246 new = force_to_mode (inner, tmode,
6247 len >= HOST_BITS_PER_WIDE_INT
6248 ? ~(unsigned HOST_WIDE_INT) 0
6249 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6252 /* If this extraction is going into the destination of a SET,
6253 make a STRICT_LOW_PART unless we made a MEM. */
6256 return (GET_CODE (new) == MEM ? new
6257 : (GET_CODE (new) != SUBREG
6258 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6259 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6264 if (GET_CODE (new) == CONST_INT)
6265 return gen_int_mode (INTVAL (new), mode);
6267 /* If we know that no extraneous bits are set, and that the high
6268 bit is not set, convert the extraction to the cheaper of
6269 sign and zero extension, that are equivalent in these cases. */
6270 if (flag_expensive_optimizations
6271 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6272 && ((nonzero_bits (new, tmode)
6273 & ~(((unsigned HOST_WIDE_INT)
6274 GET_MODE_MASK (tmode))
6278 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6279 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6281 /* Prefer ZERO_EXTENSION, since it gives more information to
6283 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6288 /* Otherwise, sign- or zero-extend unless we already are in the
6291 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6295 /* Unless this is a COMPARE or we have a funny memory reference,
6296 don't do anything with zero-extending field extracts starting at
6297 the low-order bit since they are simple AND operations. */
6298 if (pos_rtx == 0 && pos == 0 && ! in_dest
6299 && ! in_compare && ! spans_byte && unsignedp)
6302 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6303 we would be spanning bytes or if the position is not a constant and the
6304 length is not 1. In all other cases, we would only be going outside
6305 our object in cases when an original shift would have been
6307 if (! spans_byte && GET_CODE (inner) == MEM
6308 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6309 || (pos_rtx != 0 && len != 1)))
6312 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6313 and the mode for the result. */
6314 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6316 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6317 pos_mode = mode_for_extraction (EP_insv, 2);
6318 extraction_mode = mode_for_extraction (EP_insv, 3);
6321 if (! in_dest && unsignedp
6322 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6324 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6325 pos_mode = mode_for_extraction (EP_extzv, 3);
6326 extraction_mode = mode_for_extraction (EP_extzv, 0);
6329 if (! in_dest && ! unsignedp
6330 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6332 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6333 pos_mode = mode_for_extraction (EP_extv, 3);
6334 extraction_mode = mode_for_extraction (EP_extv, 0);
6337 /* Never narrow an object, since that might not be safe. */
6339 if (mode != VOIDmode
6340 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6341 extraction_mode = mode;
6343 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6344 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6345 pos_mode = GET_MODE (pos_rtx);
6347 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6348 if we have to change the mode of memory and cannot, the desired mode is
6350 if (GET_CODE (inner) != MEM)
6351 wanted_inner_mode = wanted_inner_reg_mode;
6352 else if (inner_mode != wanted_inner_mode
6353 && (mode_dependent_address_p (XEXP (inner, 0))
6354 || MEM_VOLATILE_P (inner)))
6355 wanted_inner_mode = extraction_mode;
6359 if (BITS_BIG_ENDIAN)
6361 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6362 BITS_BIG_ENDIAN style. If position is constant, compute new
6363 position. Otherwise, build subtraction.
6364 Note that POS is relative to the mode of the original argument.
6365 If it's a MEM we need to recompute POS relative to that.
6366 However, if we're extracting from (or inserting into) a register,
6367 we want to recompute POS relative to wanted_inner_mode. */
6368 int width = (GET_CODE (inner) == MEM
6369 ? GET_MODE_BITSIZE (is_mode)
6370 : GET_MODE_BITSIZE (wanted_inner_mode));
6373 pos = width - len - pos;
6376 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6377 /* POS may be less than 0 now, but we check for that below.
6378 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6381 /* If INNER has a wider mode, make it smaller. If this is a constant
6382 extract, try to adjust the byte to point to the byte containing
6384 if (wanted_inner_mode != VOIDmode
6385 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6386 && ((GET_CODE (inner) == MEM
6387 && (inner_mode == wanted_inner_mode
6388 || (! mode_dependent_address_p (XEXP (inner, 0))
6389 && ! MEM_VOLATILE_P (inner))))))
6393 /* The computations below will be correct if the machine is big
6394 endian in both bits and bytes or little endian in bits and bytes.
6395 If it is mixed, we must adjust. */
6397 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6398 adjust OFFSET to compensate. */
6399 if (BYTES_BIG_ENDIAN
6401 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6402 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6404 /* If this is a constant position, we can move to the desired byte. */
6407 offset += pos / BITS_PER_UNIT;
6408 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6411 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6413 && is_mode != wanted_inner_mode)
6414 offset = (GET_MODE_SIZE (is_mode)
6415 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6417 if (offset != 0 || inner_mode != wanted_inner_mode)
6418 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6421 /* If INNER is not memory, we can always get it into the proper mode. If we
6422 are changing its mode, POS must be a constant and smaller than the size
6424 else if (GET_CODE (inner) != MEM)
6426 if (GET_MODE (inner) != wanted_inner_mode
6428 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6431 inner = force_to_mode (inner, wanted_inner_mode,
6433 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6434 ? ~(unsigned HOST_WIDE_INT) 0
6435 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6440 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6441 have to zero extend. Otherwise, we can just use a SUBREG. */
6443 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6445 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6447 /* If we know that no extraneous bits are set, and that the high
6448 bit is not set, convert extraction to cheaper one - either
6449 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6451 if (flag_expensive_optimizations
6452 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6453 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6454 & ~(((unsigned HOST_WIDE_INT)
6455 GET_MODE_MASK (GET_MODE (pos_rtx)))
6459 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6461 /* Prefer ZERO_EXTENSION, since it gives more information to
6463 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6468 else if (pos_rtx != 0
6469 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6470 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6472 /* Make POS_RTX unless we already have it and it is correct. If we don't
6473 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6475 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6476 pos_rtx = orig_pos_rtx;
6478 else if (pos_rtx == 0)
6479 pos_rtx = GEN_INT (pos);
6481 /* Make the required operation. See if we can use existing rtx. */
6482 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6483 extraction_mode, inner, GEN_INT (len), pos_rtx);
6485 new = gen_lowpart_for_combine (mode, new);
6490 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6491 with any other operations in X. Return X without that shift if so. */
6494 extract_left_shift (x, count)
6498 enum rtx_code code = GET_CODE (x);
6499 enum machine_mode mode = GET_MODE (x);
6505 /* This is the shift itself. If it is wide enough, we will return
6506 either the value being shifted if the shift count is equal to
6507 COUNT or a shift for the difference. */
6508 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6509 && INTVAL (XEXP (x, 1)) >= count)
6510 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6511 INTVAL (XEXP (x, 1)) - count);
6515 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6516 return simplify_gen_unary (code, mode, tem, mode);
6520 case PLUS: case IOR: case XOR: case AND:
6521 /* If we can safely shift this constant and we find the inner shift,
6522 make a new operation. */
6523 if (GET_CODE (XEXP (x,1)) == CONST_INT
6524 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6525 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6526 return gen_binary (code, mode, tem,
6527 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6538 /* Look at the expression rooted at X. Look for expressions
6539 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6540 Form these expressions.
6542 Return the new rtx, usually just X.
6544 Also, for machines like the VAX that don't have logical shift insns,
6545 try to convert logical to arithmetic shift operations in cases where
6546 they are equivalent. This undoes the canonicalizations to logical
6547 shifts done elsewhere.
6549 We try, as much as possible, to re-use rtl expressions to save memory.
6551 IN_CODE says what kind of expression we are processing. Normally, it is
6552 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6553 being kludges), it is MEM. When processing the arguments of a comparison
6554 or a COMPARE against zero, it is COMPARE. */
6557 make_compound_operation (x, in_code)
6559 enum rtx_code in_code;
6561 enum rtx_code code = GET_CODE (x);
6562 enum machine_mode mode = GET_MODE (x);
6563 int mode_width = GET_MODE_BITSIZE (mode);
6565 enum rtx_code next_code;
6571 /* Select the code to be used in recursive calls. Once we are inside an
6572 address, we stay there. If we have a comparison, set to COMPARE,
6573 but once inside, go back to our default of SET. */
6575 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6576 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6577 && XEXP (x, 1) == const0_rtx) ? COMPARE
6578 : in_code == COMPARE ? SET : in_code);
6580 /* Process depending on the code of this operation. If NEW is set
6581 nonzero, it will be returned. */
6586 /* Convert shifts by constants into multiplications if inside
6588 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6589 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6590 && INTVAL (XEXP (x, 1)) >= 0)
6592 new = make_compound_operation (XEXP (x, 0), next_code);
6593 new = gen_rtx_MULT (mode, new,
6594 GEN_INT ((HOST_WIDE_INT) 1
6595 << INTVAL (XEXP (x, 1))));
6600 /* If the second operand is not a constant, we can't do anything
6602 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6605 /* If the constant is a power of two minus one and the first operand
6606 is a logical right shift, make an extraction. */
6607 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6608 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6610 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6611 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6612 0, in_code == COMPARE);
6615 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6616 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6617 && subreg_lowpart_p (XEXP (x, 0))
6618 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6619 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6621 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6623 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6624 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6625 0, in_code == COMPARE);
6627 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6628 else if ((GET_CODE (XEXP (x, 0)) == XOR
6629 || GET_CODE (XEXP (x, 0)) == IOR)
6630 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6631 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6632 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6634 /* Apply the distributive law, and then try to make extractions. */
6635 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6636 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6638 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6640 new = make_compound_operation (new, in_code);
6643 /* If we are have (and (rotate X C) M) and C is larger than the number
6644 of bits in M, this is an extraction. */
6646 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6647 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6648 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6649 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6651 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6652 new = make_extraction (mode, new,
6653 (GET_MODE_BITSIZE (mode)
6654 - INTVAL (XEXP (XEXP (x, 0), 1))),
6655 NULL_RTX, i, 1, 0, in_code == COMPARE);
6658 /* On machines without logical shifts, if the operand of the AND is
6659 a logical shift and our mask turns off all the propagated sign
6660 bits, we can replace the logical shift with an arithmetic shift. */
6661 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6662 && !have_insn_for (LSHIFTRT, mode)
6663 && have_insn_for (ASHIFTRT, mode)
6664 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6665 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6666 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6667 && mode_width <= HOST_BITS_PER_WIDE_INT)
6669 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6671 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6672 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6674 gen_rtx_ASHIFTRT (mode,
6675 make_compound_operation
6676 (XEXP (XEXP (x, 0), 0), next_code),
6677 XEXP (XEXP (x, 0), 1)));
6680 /* If the constant is one less than a power of two, this might be
6681 representable by an extraction even if no shift is present.
6682 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6683 we are in a COMPARE. */
6684 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6685 new = make_extraction (mode,
6686 make_compound_operation (XEXP (x, 0),
6688 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6690 /* If we are in a comparison and this is an AND with a power of two,
6691 convert this into the appropriate bit extract. */
6692 else if (in_code == COMPARE
6693 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6694 new = make_extraction (mode,
6695 make_compound_operation (XEXP (x, 0),
6697 i, NULL_RTX, 1, 1, 0, 1);
6702 /* If the sign bit is known to be zero, replace this with an
6703 arithmetic shift. */
6704 if (have_insn_for (ASHIFTRT, mode)
6705 && ! have_insn_for (LSHIFTRT, mode)
6706 && mode_width <= HOST_BITS_PER_WIDE_INT
6707 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6709 new = gen_rtx_ASHIFTRT (mode,
6710 make_compound_operation (XEXP (x, 0),
6716 /* ... fall through ... */
6722 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6723 this is a SIGN_EXTRACT. */
6724 if (GET_CODE (rhs) == CONST_INT
6725 && GET_CODE (lhs) == ASHIFT
6726 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6727 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6729 new = make_compound_operation (XEXP (lhs, 0), next_code);
6730 new = make_extraction (mode, new,
6731 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6732 NULL_RTX, mode_width - INTVAL (rhs),
6733 code == LSHIFTRT, 0, in_code == COMPARE);
6737 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6738 If so, try to merge the shifts into a SIGN_EXTEND. We could
6739 also do this for some cases of SIGN_EXTRACT, but it doesn't
6740 seem worth the effort; the case checked for occurs on Alpha. */
6742 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6743 && ! (GET_CODE (lhs) == SUBREG
6744 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6745 && GET_CODE (rhs) == CONST_INT
6746 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6747 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6748 new = make_extraction (mode, make_compound_operation (new, next_code),
6749 0, NULL_RTX, mode_width - INTVAL (rhs),
6750 code == LSHIFTRT, 0, in_code == COMPARE);
6755 /* Call ourselves recursively on the inner expression. If we are
6756 narrowing the object and it has a different RTL code from
6757 what it originally did, do this SUBREG as a force_to_mode. */
6759 tem = make_compound_operation (SUBREG_REG (x), in_code);
6760 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6761 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6762 && subreg_lowpart_p (x))
6764 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6767 /* If we have something other than a SUBREG, we might have
6768 done an expansion, so rerun ourselves. */
6769 if (GET_CODE (newer) != SUBREG)
6770 newer = make_compound_operation (newer, in_code);
6775 /* If this is a paradoxical subreg, and the new code is a sign or
6776 zero extension, omit the subreg and widen the extension. If it
6777 is a regular subreg, we can still get rid of the subreg by not
6778 widening so much, or in fact removing the extension entirely. */
6779 if ((GET_CODE (tem) == SIGN_EXTEND
6780 || GET_CODE (tem) == ZERO_EXTEND)
6781 && subreg_lowpart_p (x))
6783 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6784 || (GET_MODE_SIZE (mode) >
6785 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6787 if (! SCALAR_INT_MODE_P (mode))
6789 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6792 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6803 x = gen_lowpart_for_combine (mode, new);
6804 code = GET_CODE (x);
6807 /* Now recursively process each operand of this operation. */
6808 fmt = GET_RTX_FORMAT (code);
6809 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6812 new = make_compound_operation (XEXP (x, i), next_code);
6813 SUBST (XEXP (x, i), new);
6819 /* Given M see if it is a value that would select a field of bits
6820 within an item, but not the entire word. Return -1 if not.
6821 Otherwise, return the starting position of the field, where 0 is the
6824 *PLEN is set to the length of the field. */
6827 get_pos_from_mask (m, plen)
6828 unsigned HOST_WIDE_INT m;
6829 unsigned HOST_WIDE_INT *plen;
6831 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6832 int pos = exact_log2 (m & -m);
6838 /* Now shift off the low-order zero bits and see if we have a power of
6840 len = exact_log2 ((m >> pos) + 1);
6849 /* See if X can be simplified knowing that we will only refer to it in
6850 MODE and will only refer to those bits that are nonzero in MASK.
6851 If other bits are being computed or if masking operations are done
6852 that select a superset of the bits in MASK, they can sometimes be
6855 Return a possibly simplified expression, but always convert X to
6856 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6858 Also, if REG is nonzero and X is a register equal in value to REG,
6861 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6862 are all off in X. This is used when X will be complemented, by either
6863 NOT, NEG, or XOR. */
6866 force_to_mode (x, mode, mask, reg, just_select)
6868 enum machine_mode mode;
6869 unsigned HOST_WIDE_INT mask;
6873 enum rtx_code code = GET_CODE (x);
6874 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6875 enum machine_mode op_mode;
6876 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6879 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6880 code below will do the wrong thing since the mode of such an
6881 expression is VOIDmode.
6883 Also do nothing if X is a CLOBBER; this can happen if X was
6884 the return value from a call to gen_lowpart_for_combine. */
6885 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6888 /* We want to perform the operation is its present mode unless we know
6889 that the operation is valid in MODE, in which case we do the operation
6891 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6892 && have_insn_for (code, mode))
6893 ? mode : GET_MODE (x));
6895 /* It is not valid to do a right-shift in a narrower mode
6896 than the one it came in with. */
6897 if ((code == LSHIFTRT || code == ASHIFTRT)
6898 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6899 op_mode = GET_MODE (x);
6901 /* Truncate MASK to fit OP_MODE. */
6903 mask &= GET_MODE_MASK (op_mode);
6905 /* When we have an arithmetic operation, or a shift whose count we
6906 do not know, we need to assume that all bit the up to the highest-order
6907 bit in MASK will be needed. This is how we form such a mask. */
6909 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6910 ? GET_MODE_MASK (op_mode)
6911 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6914 fuller_mask = ~(HOST_WIDE_INT) 0;
6916 /* Determine what bits of X are guaranteed to be (non)zero. */
6917 nonzero = nonzero_bits (x, mode);
6919 /* If none of the bits in X are needed, return a zero. */
6920 if (! just_select && (nonzero & mask) == 0)
6923 /* If X is a CONST_INT, return a new one. Do this here since the
6924 test below will fail. */
6925 if (GET_CODE (x) == CONST_INT)
6927 if (SCALAR_INT_MODE_P (mode))
6928 return gen_int_mode (INTVAL (x) & mask, mode);
6931 x = GEN_INT (INTVAL (x) & mask);
6932 return gen_lowpart_common (mode, x);
6936 /* If X is narrower than MODE and we want all the bits in X's mode, just
6937 get X in the proper mode. */
6938 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6939 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6940 return gen_lowpart_for_combine (mode, x);
6942 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6943 MASK are already known to be zero in X, we need not do anything. */
6944 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6950 /* If X is a (clobber (const_int)), return it since we know we are
6951 generating something that won't match. */
6955 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6956 spanned the boundary of the MEM. If we are now masking so it is
6957 within that boundary, we don't need the USE any more. */
6958 if (! BITS_BIG_ENDIAN
6959 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6960 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6967 x = expand_compound_operation (x);
6968 if (GET_CODE (x) != code)
6969 return force_to_mode (x, mode, mask, reg, next_select);
6973 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6974 || rtx_equal_p (reg, get_last_value (x))))
6979 if (subreg_lowpart_p (x)
6980 /* We can ignore the effect of this SUBREG if it narrows the mode or
6981 if the constant masks to zero all the bits the mode doesn't
6983 && ((GET_MODE_SIZE (GET_MODE (x))
6984 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6986 & GET_MODE_MASK (GET_MODE (x))
6987 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6988 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6992 /* If this is an AND with a constant, convert it into an AND
6993 whose constant is the AND of that constant with MASK. If it
6994 remains an AND of MASK, delete it since it is redundant. */
6996 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6998 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6999 mask & INTVAL (XEXP (x, 1)));
7001 /* If X is still an AND, see if it is an AND with a mask that
7002 is just some low-order bits. If so, and it is MASK, we don't
7005 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7006 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7010 /* If it remains an AND, try making another AND with the bits
7011 in the mode mask that aren't in MASK turned on. If the
7012 constant in the AND is wide enough, this might make a
7013 cheaper constant. */
7015 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7016 && GET_MODE_MASK (GET_MODE (x)) != mask
7017 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7019 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7020 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7021 int width = GET_MODE_BITSIZE (GET_MODE (x));
7024 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
7025 number, sign extend it. */
7026 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7027 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7028 cval |= (HOST_WIDE_INT) -1 << width;
7030 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
7031 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7041 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7042 low-order bits (as in an alignment operation) and FOO is already
7043 aligned to that boundary, mask C1 to that boundary as well.
7044 This may eliminate that PLUS and, later, the AND. */
7047 unsigned int width = GET_MODE_BITSIZE (mode);
7048 unsigned HOST_WIDE_INT smask = mask;
7050 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7051 number, sign extend it. */
7053 if (width < HOST_BITS_PER_WIDE_INT
7054 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7055 smask |= (HOST_WIDE_INT) -1 << width;
7057 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7058 && exact_log2 (- smask) >= 0
7059 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7060 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7061 return force_to_mode (plus_constant (XEXP (x, 0),
7062 (INTVAL (XEXP (x, 1)) & smask)),
7063 mode, smask, reg, next_select);
7066 /* ... fall through ... */
7069 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7070 most significant bit in MASK since carries from those bits will
7071 affect the bits we are interested in. */
7076 /* If X is (minus C Y) where C's least set bit is larger than any bit
7077 in the mask, then we may replace with (neg Y). */
7078 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7079 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7080 & -INTVAL (XEXP (x, 0))))
7083 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7085 return force_to_mode (x, mode, mask, reg, next_select);
7088 /* Similarly, if C contains every bit in the fuller_mask, then we may
7089 replace with (not Y). */
7090 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7091 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7092 == INTVAL (XEXP (x, 0))))
7094 x = simplify_gen_unary (NOT, GET_MODE (x),
7095 XEXP (x, 1), GET_MODE (x));
7096 return force_to_mode (x, mode, mask, reg, next_select);
7104 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7105 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7106 operation which may be a bitfield extraction. Ensure that the
7107 constant we form is not wider than the mode of X. */
7109 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7110 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7111 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7112 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7113 && GET_CODE (XEXP (x, 1)) == CONST_INT
7114 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7115 + floor_log2 (INTVAL (XEXP (x, 1))))
7116 < GET_MODE_BITSIZE (GET_MODE (x)))
7117 && (INTVAL (XEXP (x, 1))
7118 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7120 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7121 << INTVAL (XEXP (XEXP (x, 0), 1)));
7122 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7123 XEXP (XEXP (x, 0), 0), temp);
7124 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7125 XEXP (XEXP (x, 0), 1));
7126 return force_to_mode (x, mode, mask, reg, next_select);
7130 /* For most binary operations, just propagate into the operation and
7131 change the mode if we have an operation of that mode. */
7133 op0 = gen_lowpart_for_combine (op_mode,
7134 force_to_mode (XEXP (x, 0), mode, mask,
7136 op1 = gen_lowpart_for_combine (op_mode,
7137 force_to_mode (XEXP (x, 1), mode, mask,
7140 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7141 x = gen_binary (code, op_mode, op0, op1);
7145 /* For left shifts, do the same, but just for the first operand.
7146 However, we cannot do anything with shifts where we cannot
7147 guarantee that the counts are smaller than the size of the mode
7148 because such a count will have a different meaning in a
7151 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7152 && INTVAL (XEXP (x, 1)) >= 0
7153 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7154 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7155 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7156 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7159 /* If the shift count is a constant and we can do arithmetic in
7160 the mode of the shift, refine which bits we need. Otherwise, use the
7161 conservative form of the mask. */
7162 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7163 && INTVAL (XEXP (x, 1)) >= 0
7164 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7165 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7166 mask >>= INTVAL (XEXP (x, 1));
7170 op0 = gen_lowpart_for_combine (op_mode,
7171 force_to_mode (XEXP (x, 0), op_mode,
7172 mask, reg, next_select));
7174 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7175 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7179 /* Here we can only do something if the shift count is a constant,
7180 this shift constant is valid for the host, and we can do arithmetic
7183 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7184 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7185 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7187 rtx inner = XEXP (x, 0);
7188 unsigned HOST_WIDE_INT inner_mask;
7190 /* Select the mask of the bits we need for the shift operand. */
7191 inner_mask = mask << INTVAL (XEXP (x, 1));
7193 /* We can only change the mode of the shift if we can do arithmetic
7194 in the mode of the shift and INNER_MASK is no wider than the
7195 width of OP_MODE. */
7196 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7197 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7198 op_mode = GET_MODE (x);
7200 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7202 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7203 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7206 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7207 shift and AND produces only copies of the sign bit (C2 is one less
7208 than a power of two), we can do this with just a shift. */
7210 if (GET_CODE (x) == LSHIFTRT
7211 && GET_CODE (XEXP (x, 1)) == CONST_INT
7212 /* The shift puts one of the sign bit copies in the least significant
7214 && ((INTVAL (XEXP (x, 1))
7215 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7216 >= GET_MODE_BITSIZE (GET_MODE (x)))
7217 && exact_log2 (mask + 1) >= 0
7218 /* Number of bits left after the shift must be more than the mask
7220 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7221 <= GET_MODE_BITSIZE (GET_MODE (x)))
7222 /* Must be more sign bit copies than the mask needs. */
7223 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7224 >= exact_log2 (mask + 1)))
7225 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7226 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7227 - exact_log2 (mask + 1)));
7232 /* If we are just looking for the sign bit, we don't need this shift at
7233 all, even if it has a variable count. */
7234 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7235 && (mask == ((unsigned HOST_WIDE_INT) 1
7236 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7237 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7239 /* If this is a shift by a constant, get a mask that contains those bits
7240 that are not copies of the sign bit. We then have two cases: If
7241 MASK only includes those bits, this can be a logical shift, which may
7242 allow simplifications. If MASK is a single-bit field not within
7243 those bits, we are requesting a copy of the sign bit and hence can
7244 shift the sign bit to the appropriate location. */
7246 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7247 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7251 /* If the considered data is wider than HOST_WIDE_INT, we can't
7252 represent a mask for all its bits in a single scalar.
7253 But we only care about the lower bits, so calculate these. */
7255 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7257 nonzero = ~(HOST_WIDE_INT) 0;
7259 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7260 is the number of bits a full-width mask would have set.
7261 We need only shift if these are fewer than nonzero can
7262 hold. If not, we must keep all bits set in nonzero. */
7264 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7265 < HOST_BITS_PER_WIDE_INT)
7266 nonzero >>= INTVAL (XEXP (x, 1))
7267 + HOST_BITS_PER_WIDE_INT
7268 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7272 nonzero = GET_MODE_MASK (GET_MODE (x));
7273 nonzero >>= INTVAL (XEXP (x, 1));
7276 if ((mask & ~nonzero) == 0
7277 || (i = exact_log2 (mask)) >= 0)
7279 x = simplify_shift_const
7280 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7281 i < 0 ? INTVAL (XEXP (x, 1))
7282 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7284 if (GET_CODE (x) != ASHIFTRT)
7285 return force_to_mode (x, mode, mask, reg, next_select);
7289 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7290 even if the shift count isn't a constant. */
7292 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7296 /* If this is a zero- or sign-extension operation that just affects bits
7297 we don't care about, remove it. Be sure the call above returned
7298 something that is still a shift. */
7300 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7301 && GET_CODE (XEXP (x, 1)) == CONST_INT
7302 && INTVAL (XEXP (x, 1)) >= 0
7303 && (INTVAL (XEXP (x, 1))
7304 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7305 && GET_CODE (XEXP (x, 0)) == ASHIFT
7306 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7307 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7308 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7315 /* If the shift count is constant and we can do computations
7316 in the mode of X, compute where the bits we care about are.
7317 Otherwise, we can't do anything. Don't change the mode of
7318 the shift or propagate MODE into the shift, though. */
7319 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7320 && INTVAL (XEXP (x, 1)) >= 0)
7322 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7323 GET_MODE (x), GEN_INT (mask),
7325 if (temp && GET_CODE(temp) == CONST_INT)
7327 force_to_mode (XEXP (x, 0), GET_MODE (x),
7328 INTVAL (temp), reg, next_select));
7333 /* If we just want the low-order bit, the NEG isn't needed since it
7334 won't change the low-order bit. */
7336 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7338 /* We need any bits less significant than the most significant bit in
7339 MASK since carries from those bits will affect the bits we are
7345 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7346 same as the XOR case above. Ensure that the constant we form is not
7347 wider than the mode of X. */
7349 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7350 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7351 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7352 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7353 < GET_MODE_BITSIZE (GET_MODE (x)))
7354 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7356 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7358 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7359 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7361 return force_to_mode (x, mode, mask, reg, next_select);
7364 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7365 use the full mask inside the NOT. */
7369 op0 = gen_lowpart_for_combine (op_mode,
7370 force_to_mode (XEXP (x, 0), mode, mask,
7372 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7373 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7377 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7378 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7379 which is equal to STORE_FLAG_VALUE. */
7380 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7381 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7382 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7383 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7388 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7389 written in a narrower mode. We play it safe and do not do so. */
7392 gen_lowpart_for_combine (GET_MODE (x),
7393 force_to_mode (XEXP (x, 1), mode,
7394 mask, reg, next_select)));
7396 gen_lowpart_for_combine (GET_MODE (x),
7397 force_to_mode (XEXP (x, 2), mode,
7398 mask, reg,next_select)));
7405 /* Ensure we return a value of the proper mode. */
7406 return gen_lowpart_for_combine (mode, x);
7409 /* Return nonzero if X is an expression that has one of two values depending on
7410 whether some other value is zero or nonzero. In that case, we return the
7411 value that is being tested, *PTRUE is set to the value if the rtx being
7412 returned has a nonzero value, and *PFALSE is set to the other alternative.
7414 If we return zero, we set *PTRUE and *PFALSE to X. */
7417 if_then_else_cond (x, ptrue, pfalse)
7419 rtx *ptrue, *pfalse;
7421 enum machine_mode mode = GET_MODE (x);
7422 enum rtx_code code = GET_CODE (x);
7423 rtx cond0, cond1, true0, true1, false0, false1;
7424 unsigned HOST_WIDE_INT nz;
7426 /* If we are comparing a value against zero, we are done. */
7427 if ((code == NE || code == EQ)
7428 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7430 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7431 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7435 /* If this is a unary operation whose operand has one of two values, apply
7436 our opcode to compute those values. */
7437 else if (GET_RTX_CLASS (code) == '1'
7438 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7440 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7441 *pfalse = simplify_gen_unary (code, mode, false0,
7442 GET_MODE (XEXP (x, 0)));
7446 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7447 make can't possibly match and would suppress other optimizations. */
7448 else if (code == COMPARE)
7451 /* If this is a binary operation, see if either side has only one of two
7452 values. If either one does or if both do and they are conditional on
7453 the same value, compute the new true and false values. */
7454 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7455 || GET_RTX_CLASS (code) == '<')
7457 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7458 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7460 if ((cond0 != 0 || cond1 != 0)
7461 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7463 /* If if_then_else_cond returned zero, then true/false are the
7464 same rtl. We must copy one of them to prevent invalid rtl
7467 true0 = copy_rtx (true0);
7468 else if (cond1 == 0)
7469 true1 = copy_rtx (true1);
7471 *ptrue = gen_binary (code, mode, true0, true1);
7472 *pfalse = gen_binary (code, mode, false0, false1);
7473 return cond0 ? cond0 : cond1;
7476 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7477 operands is zero when the other is nonzero, and vice-versa,
7478 and STORE_FLAG_VALUE is 1 or -1. */
7480 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7481 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7483 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7485 rtx op0 = XEXP (XEXP (x, 0), 1);
7486 rtx op1 = XEXP (XEXP (x, 1), 1);
7488 cond0 = XEXP (XEXP (x, 0), 0);
7489 cond1 = XEXP (XEXP (x, 1), 0);
7491 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7492 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7493 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7494 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7495 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7496 || ((swap_condition (GET_CODE (cond0))
7497 == combine_reversed_comparison_code (cond1))
7498 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7499 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7500 && ! side_effects_p (x))
7502 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7503 *pfalse = gen_binary (MULT, mode,
7505 ? simplify_gen_unary (NEG, mode, op1,
7513 /* Similarly for MULT, AND and UMIN, except that for these the result
7515 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7516 && (code == MULT || code == AND || code == UMIN)
7517 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7519 cond0 = XEXP (XEXP (x, 0), 0);
7520 cond1 = XEXP (XEXP (x, 1), 0);
7522 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7523 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7524 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7525 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7526 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7527 || ((swap_condition (GET_CODE (cond0))
7528 == combine_reversed_comparison_code (cond1))
7529 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7530 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7531 && ! side_effects_p (x))
7533 *ptrue = *pfalse = const0_rtx;
7539 else if (code == IF_THEN_ELSE)
7541 /* If we have IF_THEN_ELSE already, extract the condition and
7542 canonicalize it if it is NE or EQ. */
7543 cond0 = XEXP (x, 0);
7544 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7545 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7546 return XEXP (cond0, 0);
7547 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7549 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7550 return XEXP (cond0, 0);
7556 /* If X is a SUBREG, we can narrow both the true and false values
7557 if the inner expression, if there is a condition. */
7558 else if (code == SUBREG
7559 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7562 *ptrue = simplify_gen_subreg (mode, true0,
7563 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7564 *pfalse = simplify_gen_subreg (mode, false0,
7565 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7570 /* If X is a constant, this isn't special and will cause confusions
7571 if we treat it as such. Likewise if it is equivalent to a constant. */
7572 else if (CONSTANT_P (x)
7573 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7576 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7577 will be least confusing to the rest of the compiler. */
7578 else if (mode == BImode)
7580 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7584 /* If X is known to be either 0 or -1, those are the true and
7585 false values when testing X. */
7586 else if (x == constm1_rtx || x == const0_rtx
7587 || (mode != VOIDmode
7588 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7590 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7594 /* Likewise for 0 or a single bit. */
7595 else if (mode != VOIDmode
7596 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7597 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7599 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7603 /* Otherwise fail; show no condition with true and false values the same. */
7604 *ptrue = *pfalse = x;
7608 /* Return the value of expression X given the fact that condition COND
7609 is known to be true when applied to REG as its first operand and VAL
7610 as its second. X is known to not be shared and so can be modified in
7613 We only handle the simplest cases, and specifically those cases that
7614 arise with IF_THEN_ELSE expressions. */
7617 known_cond (x, cond, reg, val)
7622 enum rtx_code code = GET_CODE (x);
7627 if (side_effects_p (x))
7630 /* If either operand of the condition is a floating point value,
7631 then we have to avoid collapsing an EQ comparison. */
7633 && rtx_equal_p (x, reg)
7634 && ! FLOAT_MODE_P (GET_MODE (x))
7635 && ! FLOAT_MODE_P (GET_MODE (val)))
7638 if (cond == UNEQ && rtx_equal_p (x, reg))
7641 /* If X is (abs REG) and we know something about REG's relationship
7642 with zero, we may be able to simplify this. */
7644 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7647 case GE: case GT: case EQ:
7650 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7652 GET_MODE (XEXP (x, 0)));
7657 /* The only other cases we handle are MIN, MAX, and comparisons if the
7658 operands are the same as REG and VAL. */
7660 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7662 if (rtx_equal_p (XEXP (x, 0), val))
7663 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7665 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7667 if (GET_RTX_CLASS (code) == '<')
7669 if (comparison_dominates_p (cond, code))
7670 return const_true_rtx;
7672 code = combine_reversed_comparison_code (x);
7674 && comparison_dominates_p (cond, code))
7679 else if (code == SMAX || code == SMIN
7680 || code == UMIN || code == UMAX)
7682 int unsignedp = (code == UMIN || code == UMAX);
7684 /* Do not reverse the condition when it is NE or EQ.
7685 This is because we cannot conclude anything about
7686 the value of 'SMAX (x, y)' when x is not equal to y,
7687 but we can when x equals y. */
7688 if ((code == SMAX || code == UMAX)
7689 && ! (cond == EQ || cond == NE))
7690 cond = reverse_condition (cond);
7695 return unsignedp ? x : XEXP (x, 1);
7697 return unsignedp ? x : XEXP (x, 0);
7699 return unsignedp ? XEXP (x, 1) : x;
7701 return unsignedp ? XEXP (x, 0) : x;
7708 else if (code == SUBREG)
7710 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7711 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7713 if (SUBREG_REG (x) != r)
7715 /* We must simplify subreg here, before we lose track of the
7716 original inner_mode. */
7717 new = simplify_subreg (GET_MODE (x), r,
7718 inner_mode, SUBREG_BYTE (x));
7722 SUBST (SUBREG_REG (x), r);
7727 /* We don't have to handle SIGN_EXTEND here, because even in the
7728 case of replacing something with a modeless CONST_INT, a
7729 CONST_INT is already (supposed to be) a valid sign extension for
7730 its narrower mode, which implies it's already properly
7731 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7732 story is different. */
7733 else if (code == ZERO_EXTEND)
7735 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7736 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7738 if (XEXP (x, 0) != r)
7740 /* We must simplify the zero_extend here, before we lose
7741 track of the original inner_mode. */
7742 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7747 SUBST (XEXP (x, 0), r);
7753 fmt = GET_RTX_FORMAT (code);
7754 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7757 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7758 else if (fmt[i] == 'E')
7759 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7760 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7767 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7768 assignment as a field assignment. */
7771 rtx_equal_for_field_assignment_p (x, y)
7775 if (x == y || rtx_equal_p (x, y))
7778 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7781 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7782 Note that all SUBREGs of MEM are paradoxical; otherwise they
7783 would have been rewritten. */
7784 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7785 && GET_CODE (SUBREG_REG (y)) == MEM
7786 && rtx_equal_p (SUBREG_REG (y),
7787 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7790 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7791 && GET_CODE (SUBREG_REG (x)) == MEM
7792 && rtx_equal_p (SUBREG_REG (x),
7793 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7796 /* We used to see if get_last_value of X and Y were the same but that's
7797 not correct. In one direction, we'll cause the assignment to have
7798 the wrong destination and in the case, we'll import a register into this
7799 insn that might have already have been dead. So fail if none of the
7800 above cases are true. */
7804 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7805 Return that assignment if so.
7807 We only handle the most common cases. */
7810 make_field_assignment (x)
7813 rtx dest = SET_DEST (x);
7814 rtx src = SET_SRC (x);
7819 unsigned HOST_WIDE_INT len;
7821 enum machine_mode mode;
7823 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7824 a clear of a one-bit field. We will have changed it to
7825 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7828 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7829 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7830 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7831 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7833 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7836 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7840 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7841 && subreg_lowpart_p (XEXP (src, 0))
7842 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7843 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7844 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7845 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7846 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7847 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7849 assign = make_extraction (VOIDmode, dest, 0,
7850 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7853 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7857 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7859 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7860 && XEXP (XEXP (src, 0), 0) == const1_rtx
7861 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7863 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7866 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7870 /* The other case we handle is assignments into a constant-position
7871 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7872 a mask that has all one bits except for a group of zero bits and
7873 OTHER is known to have zeros where C1 has ones, this is such an
7874 assignment. Compute the position and length from C1. Shift OTHER
7875 to the appropriate position, force it to the required mode, and
7876 make the extraction. Check for the AND in both operands. */
7878 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7881 rhs = expand_compound_operation (XEXP (src, 0));
7882 lhs = expand_compound_operation (XEXP (src, 1));
7884 if (GET_CODE (rhs) == AND
7885 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7886 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7887 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7888 else if (GET_CODE (lhs) == AND
7889 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7890 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7891 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7895 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7896 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7897 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7898 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7901 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7905 /* The mode to use for the source is the mode of the assignment, or of
7906 what is inside a possible STRICT_LOW_PART. */
7907 mode = (GET_CODE (assign) == STRICT_LOW_PART
7908 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7910 /* Shift OTHER right POS places and make it the source, restricting it
7911 to the proper length and mode. */
7913 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7914 GET_MODE (src), other, pos),
7916 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7917 ? ~(unsigned HOST_WIDE_INT) 0
7918 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7921 return gen_rtx_SET (VOIDmode, assign, src);
7924 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7928 apply_distributive_law (x)
7931 enum rtx_code code = GET_CODE (x);
7932 rtx lhs, rhs, other;
7934 enum rtx_code inner_code;
7936 /* Distributivity is not true for floating point.
7937 It can change the value. So don't do it.
7938 -- rms and moshier@world.std.com. */
7939 if (FLOAT_MODE_P (GET_MODE (x)))
7942 /* The outer operation can only be one of the following: */
7943 if (code != IOR && code != AND && code != XOR
7944 && code != PLUS && code != MINUS)
7947 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7949 /* If either operand is a primitive we can't do anything, so get out
7951 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7952 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7955 lhs = expand_compound_operation (lhs);
7956 rhs = expand_compound_operation (rhs);
7957 inner_code = GET_CODE (lhs);
7958 if (inner_code != GET_CODE (rhs))
7961 /* See if the inner and outer operations distribute. */
7968 /* These all distribute except over PLUS. */
7969 if (code == PLUS || code == MINUS)
7974 if (code != PLUS && code != MINUS)
7979 /* This is also a multiply, so it distributes over everything. */
7983 /* Non-paradoxical SUBREGs distributes over all operations, provided
7984 the inner modes and byte offsets are the same, this is an extraction
7985 of a low-order part, we don't convert an fp operation to int or
7986 vice versa, and we would not be converting a single-word
7987 operation into a multi-word operation. The latter test is not
7988 required, but it prevents generating unneeded multi-word operations.
7989 Some of the previous tests are redundant given the latter test, but
7990 are retained because they are required for correctness.
7992 We produce the result slightly differently in this case. */
7994 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7995 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7996 || ! subreg_lowpart_p (lhs)
7997 || (GET_MODE_CLASS (GET_MODE (lhs))
7998 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7999 || (GET_MODE_SIZE (GET_MODE (lhs))
8000 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8001 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8004 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8005 SUBREG_REG (lhs), SUBREG_REG (rhs));
8006 return gen_lowpart_for_combine (GET_MODE (x), tem);
8012 /* Set LHS and RHS to the inner operands (A and B in the example
8013 above) and set OTHER to the common operand (C in the example).
8014 These is only one way to do this unless the inner operation is
8016 if (GET_RTX_CLASS (inner_code) == 'c'
8017 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8018 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8019 else if (GET_RTX_CLASS (inner_code) == 'c'
8020 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8021 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8022 else if (GET_RTX_CLASS (inner_code) == 'c'
8023 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8024 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8025 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8026 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8030 /* Form the new inner operation, seeing if it simplifies first. */
8031 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
8033 /* There is one exception to the general way of distributing:
8034 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
8035 if (code == XOR && inner_code == IOR)
8038 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8041 /* We may be able to continuing distributing the result, so call
8042 ourselves recursively on the inner operation before forming the
8043 outer operation, which we return. */
8044 return gen_binary (inner_code, GET_MODE (x),
8045 apply_distributive_law (tem), other);
8048 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8051 Return an equivalent form, if different from X. Otherwise, return X. If
8052 X is zero, we are to always construct the equivalent form. */
8055 simplify_and_const_int (x, mode, varop, constop)
8057 enum machine_mode mode;
8059 unsigned HOST_WIDE_INT constop;
8061 unsigned HOST_WIDE_INT nonzero;
8064 /* Simplify VAROP knowing that we will be only looking at some of the
8067 Note by passing in CONSTOP, we guarantee that the bits not set in
8068 CONSTOP are not significant and will never be examined. We must
8069 ensure that is the case by explicitly masking out those bits
8070 before returning. */
8071 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8073 /* If VAROP is a CLOBBER, we will fail so return it. */
8074 if (GET_CODE (varop) == CLOBBER)
8077 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8078 to VAROP and return the new constant. */
8079 if (GET_CODE (varop) == CONST_INT)
8080 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8082 /* See what bits may be nonzero in VAROP. Unlike the general case of
8083 a call to nonzero_bits, here we don't care about bits outside
8086 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8088 /* Turn off all bits in the constant that are known to already be zero.
8089 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8090 which is tested below. */
8094 /* If we don't have any bits left, return zero. */
8098 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8099 a power of two, we can replace this with an ASHIFT. */
8100 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8101 && (i = exact_log2 (constop)) >= 0)
8102 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8104 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8105 or XOR, then try to apply the distributive law. This may eliminate
8106 operations if either branch can be simplified because of the AND.
8107 It may also make some cases more complex, but those cases probably
8108 won't match a pattern either with or without this. */
8110 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8112 gen_lowpart_for_combine
8114 apply_distributive_law
8115 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8116 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8117 XEXP (varop, 0), constop),
8118 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8119 XEXP (varop, 1), constop))));
8121 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8122 the AND and see if one of the operands simplifies to zero. If so, we
8123 may eliminate it. */
8125 if (GET_CODE (varop) == PLUS
8126 && exact_log2 (constop + 1) >= 0)
8130 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8131 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8132 if (o0 == const0_rtx)
8134 if (o1 == const0_rtx)
8138 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8139 if we already had one (just check for the simplest cases). */
8140 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8141 && GET_MODE (XEXP (x, 0)) == mode
8142 && SUBREG_REG (XEXP (x, 0)) == varop)
8143 varop = XEXP (x, 0);
8145 varop = gen_lowpart_for_combine (mode, varop);
8147 /* If we can't make the SUBREG, try to return what we were given. */
8148 if (GET_CODE (varop) == CLOBBER)
8149 return x ? x : varop;
8151 /* If we are only masking insignificant bits, return VAROP. */
8152 if (constop == nonzero)
8156 /* Otherwise, return an AND. */
8157 constop = trunc_int_for_mode (constop, mode);
8158 /* See how much, if any, of X we can use. */
8159 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8160 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8164 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8165 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8166 SUBST (XEXP (x, 1), GEN_INT (constop));
8168 SUBST (XEXP (x, 0), varop);
8175 #define nonzero_bits_with_known(X, MODE) \
8176 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8178 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8179 It avoids exponential behavior in nonzero_bits1 when X has
8180 identical subexpressions on the first or the second level. */
8182 static unsigned HOST_WIDE_INT
8183 cached_nonzero_bits (x, mode, known_x, known_mode, known_ret)
8185 enum machine_mode mode;
8187 enum machine_mode known_mode;
8188 unsigned HOST_WIDE_INT known_ret;
8190 if (x == known_x && mode == known_mode)
8193 /* Try to find identical subexpressions. If found call
8194 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8195 precomputed value for the subexpression as KNOWN_RET. */
8197 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8198 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8200 rtx x0 = XEXP (x, 0);
8201 rtx x1 = XEXP (x, 1);
8203 /* Check the first level. */
8205 return nonzero_bits1 (x, mode, x0, mode,
8206 nonzero_bits_with_known (x0, mode));
8208 /* Check the second level. */
8209 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8210 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8211 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8212 return nonzero_bits1 (x, mode, x1, mode,
8213 nonzero_bits_with_known (x1, mode));
8215 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8216 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8217 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8218 return nonzero_bits1 (x, mode, x0, mode,
8219 nonzero_bits_with_known (x0, mode));
8222 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8225 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8226 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8227 is less useful. We can't allow both, because that results in exponential
8228 run time recursion. There is a nullstone testcase that triggered
8229 this. This macro avoids accidental uses of num_sign_bit_copies. */
8230 #define cached_num_sign_bit_copies()
8232 /* Given an expression, X, compute which bits in X can be nonzero.
8233 We don't care about bits outside of those defined in MODE.
8235 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8236 a shift, AND, or zero_extract, we can do better. */
8238 static unsigned HOST_WIDE_INT
8239 nonzero_bits1 (x, mode, known_x, known_mode, known_ret)
8241 enum machine_mode mode;
8243 enum machine_mode known_mode;
8244 unsigned HOST_WIDE_INT known_ret;
8246 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8247 unsigned HOST_WIDE_INT inner_nz;
8249 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8252 /* For floating-point values, assume all bits are needed. */
8253 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8256 /* If X is wider than MODE, use its mode instead. */
8257 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8259 mode = GET_MODE (x);
8260 nonzero = GET_MODE_MASK (mode);
8261 mode_width = GET_MODE_BITSIZE (mode);
8264 if (mode_width > HOST_BITS_PER_WIDE_INT)
8265 /* Our only callers in this case look for single bit values. So
8266 just return the mode mask. Those tests will then be false. */
8269 #ifndef WORD_REGISTER_OPERATIONS
8270 /* If MODE is wider than X, but both are a single word for both the host
8271 and target machines, we can compute this from which bits of the
8272 object might be nonzero in its own mode, taking into account the fact
8273 that on many CISC machines, accessing an object in a wider mode
8274 causes the high-order bits to become undefined. So they are
8275 not known to be zero. */
8277 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8278 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8279 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8280 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8282 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8283 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8288 code = GET_CODE (x);
8292 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8293 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8294 all the bits above ptr_mode are known to be zero. */
8295 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8297 nonzero &= GET_MODE_MASK (ptr_mode);
8300 /* Include declared information about alignment of pointers. */
8301 /* ??? We don't properly preserve REG_POINTER changes across
8302 pointer-to-integer casts, so we can't trust it except for
8303 things that we know must be pointers. See execute/960116-1.c. */
8304 if ((x == stack_pointer_rtx
8305 || x == frame_pointer_rtx
8306 || x == arg_pointer_rtx)
8307 && REGNO_POINTER_ALIGN (REGNO (x)))
8309 unsigned HOST_WIDE_INT alignment
8310 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8312 #ifdef PUSH_ROUNDING
8313 /* If PUSH_ROUNDING is defined, it is possible for the
8314 stack to be momentarily aligned only to that amount,
8315 so we pick the least alignment. */
8316 if (x == stack_pointer_rtx && PUSH_ARGS)
8317 alignment = MIN (PUSH_ROUNDING (1), alignment);
8320 nonzero &= ~(alignment - 1);
8323 /* If X is a register whose nonzero bits value is current, use it.
8324 Otherwise, if X is a register whose value we can find, use that
8325 value. Otherwise, use the previously-computed global nonzero bits
8326 for this register. */
8328 if (reg_last_set_value[REGNO (x)] != 0
8329 && (reg_last_set_mode[REGNO (x)] == mode
8330 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8331 && GET_MODE_CLASS (mode) == MODE_INT))
8332 && (reg_last_set_label[REGNO (x)] == label_tick
8333 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8334 && REG_N_SETS (REGNO (x)) == 1
8335 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8337 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8338 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8340 tem = get_last_value (x);
8344 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8345 /* If X is narrower than MODE and TEM is a non-negative
8346 constant that would appear negative in the mode of X,
8347 sign-extend it for use in reg_nonzero_bits because some
8348 machines (maybe most) will actually do the sign-extension
8349 and this is the conservative approach.
8351 ??? For 2.5, try to tighten up the MD files in this regard
8352 instead of this kludge. */
8354 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8355 && GET_CODE (tem) == CONST_INT
8357 && 0 != (INTVAL (tem)
8358 & ((HOST_WIDE_INT) 1
8359 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8360 tem = GEN_INT (INTVAL (tem)
8361 | ((HOST_WIDE_INT) (-1)
8362 << GET_MODE_BITSIZE (GET_MODE (x))));
8364 return nonzero_bits_with_known (tem, mode) & nonzero;
8366 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8368 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8370 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8371 /* We don't know anything about the upper bits. */
8372 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8373 return nonzero & mask;
8379 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8380 /* If X is negative in MODE, sign-extend the value. */
8381 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8382 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8383 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8389 #ifdef LOAD_EXTEND_OP
8390 /* In many, if not most, RISC machines, reading a byte from memory
8391 zeros the rest of the register. Noticing that fact saves a lot
8392 of extra zero-extends. */
8393 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8394 nonzero &= GET_MODE_MASK (GET_MODE (x));
8399 case UNEQ: case LTGT:
8400 case GT: case GTU: case UNGT:
8401 case LT: case LTU: case UNLT:
8402 case GE: case GEU: case UNGE:
8403 case LE: case LEU: case UNLE:
8404 case UNORDERED: case ORDERED:
8406 /* If this produces an integer result, we know which bits are set.
8407 Code here used to clear bits outside the mode of X, but that is
8410 if (GET_MODE_CLASS (mode) == MODE_INT
8411 && mode_width <= HOST_BITS_PER_WIDE_INT)
8412 nonzero = STORE_FLAG_VALUE;
8417 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8418 and num_sign_bit_copies. */
8419 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8420 == GET_MODE_BITSIZE (GET_MODE (x)))
8424 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8425 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8430 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8431 and num_sign_bit_copies. */
8432 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8433 == GET_MODE_BITSIZE (GET_MODE (x)))
8439 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8440 & GET_MODE_MASK (mode));
8444 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8445 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8446 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8450 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8451 Otherwise, show all the bits in the outer mode but not the inner
8453 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8454 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8456 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8458 & (((HOST_WIDE_INT) 1
8459 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8460 inner_nz |= (GET_MODE_MASK (mode)
8461 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8464 nonzero &= inner_nz;
8468 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8469 & nonzero_bits_with_known (XEXP (x, 1), mode));
8473 case UMIN: case UMAX: case SMIN: case SMAX:
8475 unsigned HOST_WIDE_INT nonzero0 =
8476 nonzero_bits_with_known (XEXP (x, 0), mode);
8478 /* Don't call nonzero_bits for the second time if it cannot change
8480 if ((nonzero & nonzero0) != nonzero)
8481 nonzero &= (nonzero0
8482 | nonzero_bits_with_known (XEXP (x, 1), mode));
8486 case PLUS: case MINUS:
8488 case DIV: case UDIV:
8489 case MOD: case UMOD:
8490 /* We can apply the rules of arithmetic to compute the number of
8491 high- and low-order zero bits of these operations. We start by
8492 computing the width (position of the highest-order nonzero bit)
8493 and the number of low-order zero bits for each value. */
8495 unsigned HOST_WIDE_INT nz0 =
8496 nonzero_bits_with_known (XEXP (x, 0), mode);
8497 unsigned HOST_WIDE_INT nz1 =
8498 nonzero_bits_with_known (XEXP (x, 1), mode);
8499 int width0 = floor_log2 (nz0) + 1;
8500 int width1 = floor_log2 (nz1) + 1;
8501 int low0 = floor_log2 (nz0 & -nz0);
8502 int low1 = floor_log2 (nz1 & -nz1);
8503 HOST_WIDE_INT op0_maybe_minusp
8504 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8505 HOST_WIDE_INT op1_maybe_minusp
8506 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8507 unsigned int result_width = mode_width;
8513 result_width = MAX (width0, width1) + 1;
8514 result_low = MIN (low0, low1);
8517 result_low = MIN (low0, low1);
8520 result_width = width0 + width1;
8521 result_low = low0 + low1;
8526 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8527 result_width = width0;
8532 result_width = width0;
8537 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8538 result_width = MIN (width0, width1);
8539 result_low = MIN (low0, low1);
8544 result_width = MIN (width0, width1);
8545 result_low = MIN (low0, low1);
8551 if (result_width < mode_width)
8552 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8555 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8557 #ifdef POINTERS_EXTEND_UNSIGNED
8558 /* If pointers extend unsigned and this is an addition or subtraction
8559 to a pointer in Pmode, all the bits above ptr_mode are known to be
8561 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8562 && (code == PLUS || code == MINUS)
8563 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8564 nonzero &= GET_MODE_MASK (ptr_mode);
8570 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8571 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8572 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8576 /* If this is a SUBREG formed for a promoted variable that has
8577 been zero-extended, we know that at least the high-order bits
8578 are zero, though others might be too. */
8580 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8581 nonzero = (GET_MODE_MASK (GET_MODE (x))
8582 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8584 /* If the inner mode is a single word for both the host and target
8585 machines, we can compute this from which bits of the inner
8586 object might be nonzero. */
8587 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8588 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8589 <= HOST_BITS_PER_WIDE_INT))
8591 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8593 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8594 /* If this is a typical RISC machine, we only have to worry
8595 about the way loads are extended. */
8596 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8598 & (((unsigned HOST_WIDE_INT) 1
8599 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8601 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8602 || GET_CODE (SUBREG_REG (x)) != MEM)
8605 /* On many CISC machines, accessing an object in a wider mode
8606 causes the high-order bits to become undefined. So they are
8607 not known to be zero. */
8608 if (GET_MODE_SIZE (GET_MODE (x))
8609 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8610 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8611 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8620 /* The nonzero bits are in two classes: any bits within MODE
8621 that aren't in GET_MODE (x) are always significant. The rest of the
8622 nonzero bits are those that are significant in the operand of
8623 the shift when shifted the appropriate number of bits. This
8624 shows that high-order bits are cleared by the right shift and
8625 low-order bits by left shifts. */
8626 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8627 && INTVAL (XEXP (x, 1)) >= 0
8628 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8630 enum machine_mode inner_mode = GET_MODE (x);
8631 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8632 int count = INTVAL (XEXP (x, 1));
8633 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8634 unsigned HOST_WIDE_INT op_nonzero =
8635 nonzero_bits_with_known (XEXP (x, 0), mode);
8636 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8637 unsigned HOST_WIDE_INT outer = 0;
8639 if (mode_width > width)
8640 outer = (op_nonzero & nonzero & ~mode_mask);
8642 if (code == LSHIFTRT)
8644 else if (code == ASHIFTRT)
8648 /* If the sign bit may have been nonzero before the shift, we
8649 need to mark all the places it could have been copied to
8650 by the shift as possibly nonzero. */
8651 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8652 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8654 else if (code == ASHIFT)
8657 inner = ((inner << (count % width)
8658 | (inner >> (width - (count % width)))) & mode_mask);
8660 nonzero &= (outer | inner);
8665 /* This is at most the number of bits in the mode. */
8666 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8670 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8671 | nonzero_bits_with_known (XEXP (x, 2), mode));
8681 /* See the macro definition above. */
8682 #undef cached_num_sign_bit_copies
8684 #define num_sign_bit_copies_with_known(X, M) \
8685 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8687 /* The function cached_num_sign_bit_copies is a wrapper around
8688 num_sign_bit_copies1. It avoids exponential behavior in
8689 num_sign_bit_copies1 when X has identical subexpressions on the
8690 first or the second level. */
8693 cached_num_sign_bit_copies (x, mode, known_x, known_mode, known_ret)
8695 enum machine_mode mode;
8697 enum machine_mode known_mode;
8698 unsigned int known_ret;
8700 if (x == known_x && mode == known_mode)
8703 /* Try to find identical subexpressions. If found call
8704 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8705 the precomputed value for the subexpression as KNOWN_RET. */
8707 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8708 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8710 rtx x0 = XEXP (x, 0);
8711 rtx x1 = XEXP (x, 1);
8713 /* Check the first level. */
8716 num_sign_bit_copies1 (x, mode, x0, mode,
8717 num_sign_bit_copies_with_known (x0, mode));
8719 /* Check the second level. */
8720 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8721 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8722 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8724 num_sign_bit_copies1 (x, mode, x1, mode,
8725 num_sign_bit_copies_with_known (x1, mode));
8727 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8728 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8729 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8731 num_sign_bit_copies1 (x, mode, x0, mode,
8732 num_sign_bit_copies_with_known (x0, mode));
8735 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8738 /* Return the number of bits at the high-order end of X that are known to
8739 be equal to the sign bit. X will be used in mode MODE; if MODE is
8740 VOIDmode, X will be used in its own mode. The returned value will always
8741 be between 1 and the number of bits in MODE. */
8744 num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret)
8746 enum machine_mode mode;
8748 enum machine_mode known_mode;
8749 unsigned int known_ret;
8751 enum rtx_code code = GET_CODE (x);
8752 unsigned int bitwidth;
8753 int num0, num1, result;
8754 unsigned HOST_WIDE_INT nonzero;
8757 /* If we weren't given a mode, use the mode of X. If the mode is still
8758 VOIDmode, we don't know anything. Likewise if one of the modes is
8761 if (mode == VOIDmode)
8762 mode = GET_MODE (x);
8764 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8767 bitwidth = GET_MODE_BITSIZE (mode);
8769 /* For a smaller object, just ignore the high bits. */
8770 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8772 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8774 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8777 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8779 #ifndef WORD_REGISTER_OPERATIONS
8780 /* If this machine does not do all register operations on the entire
8781 register and MODE is wider than the mode of X, we can say nothing
8782 at all about the high-order bits. */
8785 /* Likewise on machines that do, if the mode of the object is smaller
8786 than a word and loads of that size don't sign extend, we can say
8787 nothing about the high order bits. */
8788 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8789 #ifdef LOAD_EXTEND_OP
8790 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8801 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8802 /* If pointers extend signed and this is a pointer in Pmode, say that
8803 all the bits above ptr_mode are known to be sign bit copies. */
8804 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8806 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8809 if (reg_last_set_value[REGNO (x)] != 0
8810 && reg_last_set_mode[REGNO (x)] == mode
8811 && (reg_last_set_label[REGNO (x)] == label_tick
8812 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8813 && REG_N_SETS (REGNO (x)) == 1
8814 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8816 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8817 return reg_last_set_sign_bit_copies[REGNO (x)];
8819 tem = get_last_value (x);
8821 return num_sign_bit_copies_with_known (tem, mode);
8823 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8824 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8825 return reg_sign_bit_copies[REGNO (x)];
8829 #ifdef LOAD_EXTEND_OP
8830 /* Some RISC machines sign-extend all loads of smaller than a word. */
8831 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8832 return MAX (1, ((int) bitwidth
8833 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8838 /* If the constant is negative, take its 1's complement and remask.
8839 Then see how many zero bits we have. */
8840 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8841 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8842 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8843 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8845 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8848 /* If this is a SUBREG for a promoted object that is sign-extended
8849 and we are looking at it in a wider mode, we know that at least the
8850 high-order bits are known to be sign bit copies. */
8852 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8854 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8855 return MAX ((int) bitwidth
8856 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8860 /* For a smaller object, just ignore the high bits. */
8861 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8863 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8864 return MAX (1, (num0
8865 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8869 #ifdef WORD_REGISTER_OPERATIONS
8870 #ifdef LOAD_EXTEND_OP
8871 /* For paradoxical SUBREGs on machines where all register operations
8872 affect the entire register, just look inside. Note that we are
8873 passing MODE to the recursive call, so the number of sign bit copies
8874 will remain relative to that mode, not the inner mode. */
8876 /* This works only if loads sign extend. Otherwise, if we get a
8877 reload for the inner part, it may be loaded from the stack, and
8878 then we lose all sign bit copies that existed before the store
8881 if ((GET_MODE_SIZE (GET_MODE (x))
8882 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8883 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8884 && GET_CODE (SUBREG_REG (x)) == MEM)
8885 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8891 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8892 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8896 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8897 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8900 /* For a smaller object, just ignore the high bits. */
8901 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8902 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8906 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8908 case ROTATE: case ROTATERT:
8909 /* If we are rotating left by a number of bits less than the number
8910 of sign bit copies, we can just subtract that amount from the
8912 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8913 && INTVAL (XEXP (x, 1)) >= 0
8914 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8916 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8917 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8918 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8923 /* In general, this subtracts one sign bit copy. But if the value
8924 is known to be positive, the number of sign bit copies is the
8925 same as that of the input. Finally, if the input has just one bit
8926 that might be nonzero, all the bits are copies of the sign bit. */
8927 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8928 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8929 return num0 > 1 ? num0 - 1 : 1;
8931 nonzero = nonzero_bits (XEXP (x, 0), mode);
8936 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8941 case IOR: case AND: case XOR:
8942 case SMIN: case SMAX: case UMIN: case UMAX:
8943 /* Logical operations will preserve the number of sign-bit copies.
8944 MIN and MAX operations always return one of the operands. */
8945 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8946 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8947 return MIN (num0, num1);
8949 case PLUS: case MINUS:
8950 /* For addition and subtraction, we can have a 1-bit carry. However,
8951 if we are subtracting 1 from a positive number, there will not
8952 be such a carry. Furthermore, if the positive number is known to
8953 be 0 or 1, we know the result is either -1 or 0. */
8955 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8956 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8958 nonzero = nonzero_bits (XEXP (x, 0), mode);
8959 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8960 return (nonzero == 1 || nonzero == 0 ? bitwidth
8961 : bitwidth - floor_log2 (nonzero) - 1);
8964 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8965 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8966 result = MAX (1, MIN (num0, num1) - 1);
8968 #ifdef POINTERS_EXTEND_UNSIGNED
8969 /* If pointers extend signed and this is an addition or subtraction
8970 to a pointer in Pmode, all the bits above ptr_mode are known to be
8972 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8973 && (code == PLUS || code == MINUS)
8974 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8975 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8976 - GET_MODE_BITSIZE (ptr_mode) + 1),
8982 /* The number of bits of the product is the sum of the number of
8983 bits of both terms. However, unless one of the terms if known
8984 to be positive, we must allow for an additional bit since negating
8985 a negative number can remove one sign bit copy. */
8987 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8988 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8990 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8992 && (bitwidth > HOST_BITS_PER_WIDE_INT
8993 || (((nonzero_bits (XEXP (x, 0), mode)
8994 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8995 && ((nonzero_bits (XEXP (x, 1), mode)
8996 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8999 return MAX (1, result);
9002 /* The result must be <= the first operand. If the first operand
9003 has the high bit set, we know nothing about the number of sign
9005 if (bitwidth > HOST_BITS_PER_WIDE_INT)
9007 else if ((nonzero_bits (XEXP (x, 0), mode)
9008 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9011 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9014 /* The result must be <= the second operand. */
9015 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9018 /* Similar to unsigned division, except that we have to worry about
9019 the case where the divisor is negative, in which case we have
9021 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9023 && (bitwidth > HOST_BITS_PER_WIDE_INT
9024 || (nonzero_bits (XEXP (x, 1), mode)
9025 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
9031 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9033 && (bitwidth > HOST_BITS_PER_WIDE_INT
9034 || (nonzero_bits (XEXP (x, 1), mode)
9035 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
9041 /* Shifts by a constant add to the number of bits equal to the
9043 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9044 if (GET_CODE (XEXP (x, 1)) == CONST_INT
9045 && INTVAL (XEXP (x, 1)) > 0)
9046 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
9051 /* Left shifts destroy copies. */
9052 if (GET_CODE (XEXP (x, 1)) != CONST_INT
9053 || INTVAL (XEXP (x, 1)) < 0
9054 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
9057 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
9058 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
9061 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9062 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
9063 return MIN (num0, num1);
9065 case EQ: case NE: case GE: case GT: case LE: case LT:
9066 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
9067 case GEU: case GTU: case LEU: case LTU:
9068 case UNORDERED: case ORDERED:
9069 /* If the constant is negative, take its 1's complement and remask.
9070 Then see how many zero bits we have. */
9071 nonzero = STORE_FLAG_VALUE;
9072 if (bitwidth <= HOST_BITS_PER_WIDE_INT
9073 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9074 nonzero = (~nonzero) & GET_MODE_MASK (mode);
9076 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
9083 /* If we haven't been able to figure it out by one of the above rules,
9084 see if some of the high-order bits are known to be zero. If so,
9085 count those bits and return one less than that amount. If we can't
9086 safely compute the mask for this mode, always return BITWIDTH. */
9088 if (bitwidth > HOST_BITS_PER_WIDE_INT)
9091 nonzero = nonzero_bits (x, mode);
9092 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
9093 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
9096 /* Return the number of "extended" bits there are in X, when interpreted
9097 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9098 unsigned quantities, this is the number of high-order zero bits.
9099 For signed quantities, this is the number of copies of the sign bit
9100 minus 1. In both case, this function returns the number of "spare"
9101 bits. For example, if two quantities for which this function returns
9102 at least 1 are added, the addition is known not to overflow.
9104 This function will always return 0 unless called during combine, which
9105 implies that it must be called from a define_split. */
9108 extended_count (x, mode, unsignedp)
9110 enum machine_mode mode;
9113 if (nonzero_sign_valid == 0)
9117 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9118 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9119 - floor_log2 (nonzero_bits (x, mode)))
9121 : num_sign_bit_copies (x, mode) - 1);
9124 /* This function is called from `simplify_shift_const' to merge two
9125 outer operations. Specifically, we have already found that we need
9126 to perform operation *POP0 with constant *PCONST0 at the outermost
9127 position. We would now like to also perform OP1 with constant CONST1
9128 (with *POP0 being done last).
9130 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9131 the resulting operation. *PCOMP_P is set to 1 if we would need to
9132 complement the innermost operand, otherwise it is unchanged.
9134 MODE is the mode in which the operation will be done. No bits outside
9135 the width of this mode matter. It is assumed that the width of this mode
9136 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9138 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9139 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9140 result is simply *PCONST0.
9142 If the resulting operation cannot be expressed as one operation, we
9143 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9146 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
9147 enum rtx_code *pop0;
9148 HOST_WIDE_INT *pconst0;
9150 HOST_WIDE_INT const1;
9151 enum machine_mode mode;
9154 enum rtx_code op0 = *pop0;
9155 HOST_WIDE_INT const0 = *pconst0;
9157 const0 &= GET_MODE_MASK (mode);
9158 const1 &= GET_MODE_MASK (mode);
9160 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9164 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9167 if (op1 == NIL || op0 == SET)
9170 else if (op0 == NIL)
9171 op0 = op1, const0 = const1;
9173 else if (op0 == op1)
9197 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9198 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9201 /* If the two constants aren't the same, we can't do anything. The
9202 remaining six cases can all be done. */
9203 else if (const0 != const1)
9211 /* (a & b) | b == b */
9213 else /* op1 == XOR */
9214 /* (a ^ b) | b == a | b */
9220 /* (a & b) ^ b == (~a) & b */
9221 op0 = AND, *pcomp_p = 1;
9222 else /* op1 == IOR */
9223 /* (a | b) ^ b == a & ~b */
9224 op0 = AND, *pconst0 = ~const0;
9229 /* (a | b) & b == b */
9231 else /* op1 == XOR */
9232 /* (a ^ b) & b) == (~a) & b */
9239 /* Check for NO-OP cases. */
9240 const0 &= GET_MODE_MASK (mode);
9242 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9244 else if (const0 == 0 && op0 == AND)
9246 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9250 /* ??? Slightly redundant with the above mask, but not entirely.
9251 Moving this above means we'd have to sign-extend the mode mask
9252 for the final test. */
9253 const0 = trunc_int_for_mode (const0, mode);
9261 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9262 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9263 that we started with.
9265 The shift is normally computed in the widest mode we find in VAROP, as
9266 long as it isn't a different number of words than RESULT_MODE. Exceptions
9267 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9270 simplify_shift_const (x, code, result_mode, varop, orig_count)
9273 enum machine_mode result_mode;
9277 enum rtx_code orig_code = code;
9280 enum machine_mode mode = result_mode;
9281 enum machine_mode shift_mode, tmode;
9282 unsigned int mode_words
9283 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9284 /* We form (outer_op (code varop count) (outer_const)). */
9285 enum rtx_code outer_op = NIL;
9286 HOST_WIDE_INT outer_const = 0;
9288 int complement_p = 0;
9291 /* Make sure and truncate the "natural" shift on the way in. We don't
9292 want to do this inside the loop as it makes it more difficult to
9294 #ifdef SHIFT_COUNT_TRUNCATED
9295 if (SHIFT_COUNT_TRUNCATED)
9296 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9299 /* If we were given an invalid count, don't do anything except exactly
9300 what was requested. */
9302 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9307 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9312 /* Unless one of the branches of the `if' in this loop does a `continue',
9313 we will `break' the loop after the `if'. */
9317 /* If we have an operand of (clobber (const_int 0)), just return that
9319 if (GET_CODE (varop) == CLOBBER)
9322 /* If we discovered we had to complement VAROP, leave. Making a NOT
9323 here would cause an infinite loop. */
9327 /* Convert ROTATERT to ROTATE. */
9328 if (code == ROTATERT)
9330 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9332 if (VECTOR_MODE_P (result_mode))
9333 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9335 count = bitsize - count;
9338 /* We need to determine what mode we will do the shift in. If the
9339 shift is a right shift or a ROTATE, we must always do it in the mode
9340 it was originally done in. Otherwise, we can do it in MODE, the
9341 widest mode encountered. */
9343 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9344 ? result_mode : mode);
9346 /* Handle cases where the count is greater than the size of the mode
9347 minus 1. For ASHIFT, use the size minus one as the count (this can
9348 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9349 take the count modulo the size. For other shifts, the result is
9352 Since these shifts are being produced by the compiler by combining
9353 multiple operations, each of which are defined, we know what the
9354 result is supposed to be. */
9356 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9358 if (code == ASHIFTRT)
9359 count = GET_MODE_BITSIZE (shift_mode) - 1;
9360 else if (code == ROTATE || code == ROTATERT)
9361 count %= GET_MODE_BITSIZE (shift_mode);
9364 /* We can't simply return zero because there may be an
9372 /* An arithmetic right shift of a quantity known to be -1 or 0
9374 if (code == ASHIFTRT
9375 && (num_sign_bit_copies (varop, shift_mode)
9376 == GET_MODE_BITSIZE (shift_mode)))
9382 /* If we are doing an arithmetic right shift and discarding all but
9383 the sign bit copies, this is equivalent to doing a shift by the
9384 bitsize minus one. Convert it into that shift because it will often
9385 allow other simplifications. */
9387 if (code == ASHIFTRT
9388 && (count + num_sign_bit_copies (varop, shift_mode)
9389 >= GET_MODE_BITSIZE (shift_mode)))
9390 count = GET_MODE_BITSIZE (shift_mode) - 1;
9392 /* We simplify the tests below and elsewhere by converting
9393 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9394 `make_compound_operation' will convert it to an ASHIFTRT for
9395 those machines (such as VAX) that don't have an LSHIFTRT. */
9396 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9398 && ((nonzero_bits (varop, shift_mode)
9399 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9403 switch (GET_CODE (varop))
9409 new = expand_compound_operation (varop);
9418 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9419 minus the width of a smaller mode, we can do this with a
9420 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9421 if ((code == ASHIFTRT || code == LSHIFTRT)
9422 && ! mode_dependent_address_p (XEXP (varop, 0))
9423 && ! MEM_VOLATILE_P (varop)
9424 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9425 MODE_INT, 1)) != BLKmode)
9427 new = adjust_address_nv (varop, tmode,
9428 BYTES_BIG_ENDIAN ? 0
9429 : count / BITS_PER_UNIT);
9431 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9432 : ZERO_EXTEND, mode, new);
9439 /* Similar to the case above, except that we can only do this if
9440 the resulting mode is the same as that of the underlying
9441 MEM and adjust the address depending on the *bits* endianness
9442 because of the way that bit-field extract insns are defined. */
9443 if ((code == ASHIFTRT || code == LSHIFTRT)
9444 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9445 MODE_INT, 1)) != BLKmode
9446 && tmode == GET_MODE (XEXP (varop, 0)))
9448 if (BITS_BIG_ENDIAN)
9449 new = XEXP (varop, 0);
9452 new = copy_rtx (XEXP (varop, 0));
9453 SUBST (XEXP (new, 0),
9454 plus_constant (XEXP (new, 0),
9455 count / BITS_PER_UNIT));
9458 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9459 : ZERO_EXTEND, mode, new);
9466 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9467 the same number of words as what we've seen so far. Then store
9468 the widest mode in MODE. */
9469 if (subreg_lowpart_p (varop)
9470 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9471 > GET_MODE_SIZE (GET_MODE (varop)))
9472 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9473 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9476 varop = SUBREG_REG (varop);
9477 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9478 mode = GET_MODE (varop);
9484 /* Some machines use MULT instead of ASHIFT because MULT
9485 is cheaper. But it is still better on those machines to
9486 merge two shifts into one. */
9487 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9488 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9491 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9492 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9498 /* Similar, for when divides are cheaper. */
9499 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9500 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9503 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9504 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9510 /* If we are extracting just the sign bit of an arithmetic
9511 right shift, that shift is not needed. However, the sign
9512 bit of a wider mode may be different from what would be
9513 interpreted as the sign bit in a narrower mode, so, if
9514 the result is narrower, don't discard the shift. */
9515 if (code == LSHIFTRT
9516 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9517 && (GET_MODE_BITSIZE (result_mode)
9518 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9520 varop = XEXP (varop, 0);
9524 /* ... fall through ... */
9529 /* Here we have two nested shifts. The result is usually the
9530 AND of a new shift with a mask. We compute the result below. */
9531 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9532 && INTVAL (XEXP (varop, 1)) >= 0
9533 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9534 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9535 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9537 enum rtx_code first_code = GET_CODE (varop);
9538 unsigned int first_count = INTVAL (XEXP (varop, 1));
9539 unsigned HOST_WIDE_INT mask;
9542 /* We have one common special case. We can't do any merging if
9543 the inner code is an ASHIFTRT of a smaller mode. However, if
9544 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9545 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9546 we can convert it to
9547 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9548 This simplifies certain SIGN_EXTEND operations. */
9549 if (code == ASHIFT && first_code == ASHIFTRT
9550 && count == (unsigned int)
9551 (GET_MODE_BITSIZE (result_mode)
9552 - GET_MODE_BITSIZE (GET_MODE (varop))))
9554 /* C3 has the low-order C1 bits zero. */
9556 mask = (GET_MODE_MASK (mode)
9557 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9559 varop = simplify_and_const_int (NULL_RTX, result_mode,
9560 XEXP (varop, 0), mask);
9561 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9563 count = first_count;
9568 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9569 than C1 high-order bits equal to the sign bit, we can convert
9570 this to either an ASHIFT or an ASHIFTRT depending on the
9573 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9575 if (code == ASHIFTRT && first_code == ASHIFT
9576 && GET_MODE (varop) == shift_mode
9577 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9580 varop = XEXP (varop, 0);
9582 signed_count = count - first_count;
9583 if (signed_count < 0)
9584 count = -signed_count, code = ASHIFT;
9586 count = signed_count;
9591 /* There are some cases we can't do. If CODE is ASHIFTRT,
9592 we can only do this if FIRST_CODE is also ASHIFTRT.
9594 We can't do the case when CODE is ROTATE and FIRST_CODE is
9597 If the mode of this shift is not the mode of the outer shift,
9598 we can't do this if either shift is a right shift or ROTATE.
9600 Finally, we can't do any of these if the mode is too wide
9601 unless the codes are the same.
9603 Handle the case where the shift codes are the same
9606 if (code == first_code)
9608 if (GET_MODE (varop) != result_mode
9609 && (code == ASHIFTRT || code == LSHIFTRT
9613 count += first_count;
9614 varop = XEXP (varop, 0);
9618 if (code == ASHIFTRT
9619 || (code == ROTATE && first_code == ASHIFTRT)
9620 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9621 || (GET_MODE (varop) != result_mode
9622 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9623 || first_code == ROTATE
9624 || code == ROTATE)))
9627 /* To compute the mask to apply after the shift, shift the
9628 nonzero bits of the inner shift the same way the
9629 outer shift will. */
9631 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9634 = simplify_binary_operation (code, result_mode, mask_rtx,
9637 /* Give up if we can't compute an outer operation to use. */
9639 || GET_CODE (mask_rtx) != CONST_INT
9640 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9642 result_mode, &complement_p))
9645 /* If the shifts are in the same direction, we add the
9646 counts. Otherwise, we subtract them. */
9647 signed_count = count;
9648 if ((code == ASHIFTRT || code == LSHIFTRT)
9649 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9650 signed_count += first_count;
9652 signed_count -= first_count;
9654 /* If COUNT is positive, the new shift is usually CODE,
9655 except for the two exceptions below, in which case it is
9656 FIRST_CODE. If the count is negative, FIRST_CODE should
9658 if (signed_count > 0
9659 && ((first_code == ROTATE && code == ASHIFT)
9660 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9661 code = first_code, count = signed_count;
9662 else if (signed_count < 0)
9663 code = first_code, count = -signed_count;
9665 count = signed_count;
9667 varop = XEXP (varop, 0);
9671 /* If we have (A << B << C) for any shift, we can convert this to
9672 (A << C << B). This wins if A is a constant. Only try this if
9673 B is not a constant. */
9675 else if (GET_CODE (varop) == code
9676 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9678 = simplify_binary_operation (code, mode,
9682 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9689 /* Make this fit the case below. */
9690 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9691 GEN_INT (GET_MODE_MASK (mode)));
9697 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9698 with C the size of VAROP - 1 and the shift is logical if
9699 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9700 we have an (le X 0) operation. If we have an arithmetic shift
9701 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9702 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9704 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9705 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9706 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9707 && (code == LSHIFTRT || code == ASHIFTRT)
9708 && count == (unsigned int)
9709 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9710 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9713 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9716 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9717 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9722 /* If we have (shift (logical)), move the logical to the outside
9723 to allow it to possibly combine with another logical and the
9724 shift to combine with another shift. This also canonicalizes to
9725 what a ZERO_EXTRACT looks like. Also, some machines have
9726 (and (shift)) insns. */
9728 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9729 && (new = simplify_binary_operation (code, result_mode,
9731 GEN_INT (count))) != 0
9732 && GET_CODE (new) == CONST_INT
9733 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9734 INTVAL (new), result_mode, &complement_p))
9736 varop = XEXP (varop, 0);
9740 /* If we can't do that, try to simplify the shift in each arm of the
9741 logical expression, make a new logical expression, and apply
9742 the inverse distributive law. */
9744 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9745 XEXP (varop, 0), count);
9746 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9747 XEXP (varop, 1), count);
9749 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9750 varop = apply_distributive_law (varop);
9757 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9758 says that the sign bit can be tested, FOO has mode MODE, C is
9759 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9760 that may be nonzero. */
9761 if (code == LSHIFTRT
9762 && XEXP (varop, 1) == const0_rtx
9763 && GET_MODE (XEXP (varop, 0)) == result_mode
9764 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9765 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9766 && ((STORE_FLAG_VALUE
9767 & ((HOST_WIDE_INT) 1
9768 < (GET_MODE_BITSIZE (result_mode) - 1))))
9769 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9770 && merge_outer_ops (&outer_op, &outer_const, XOR,
9771 (HOST_WIDE_INT) 1, result_mode,
9774 varop = XEXP (varop, 0);
9781 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9782 than the number of bits in the mode is equivalent to A. */
9783 if (code == LSHIFTRT
9784 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9785 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9787 varop = XEXP (varop, 0);
9792 /* NEG commutes with ASHIFT since it is multiplication. Move the
9793 NEG outside to allow shifts to combine. */
9795 && merge_outer_ops (&outer_op, &outer_const, NEG,
9796 (HOST_WIDE_INT) 0, result_mode,
9799 varop = XEXP (varop, 0);
9805 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9806 is one less than the number of bits in the mode is
9807 equivalent to (xor A 1). */
9808 if (code == LSHIFTRT
9809 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9810 && XEXP (varop, 1) == constm1_rtx
9811 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9812 && merge_outer_ops (&outer_op, &outer_const, XOR,
9813 (HOST_WIDE_INT) 1, result_mode,
9817 varop = XEXP (varop, 0);
9821 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9822 that might be nonzero in BAR are those being shifted out and those
9823 bits are known zero in FOO, we can replace the PLUS with FOO.
9824 Similarly in the other operand order. This code occurs when
9825 we are computing the size of a variable-size array. */
9827 if ((code == ASHIFTRT || code == LSHIFTRT)
9828 && count < HOST_BITS_PER_WIDE_INT
9829 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9830 && (nonzero_bits (XEXP (varop, 1), result_mode)
9831 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9833 varop = XEXP (varop, 0);
9836 else if ((code == ASHIFTRT || code == LSHIFTRT)
9837 && count < HOST_BITS_PER_WIDE_INT
9838 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9839 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9841 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9842 & nonzero_bits (XEXP (varop, 1),
9845 varop = XEXP (varop, 1);
9849 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9851 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9852 && (new = simplify_binary_operation (ASHIFT, result_mode,
9854 GEN_INT (count))) != 0
9855 && GET_CODE (new) == CONST_INT
9856 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9857 INTVAL (new), result_mode, &complement_p))
9859 varop = XEXP (varop, 0);
9865 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9866 with C the size of VAROP - 1 and the shift is logical if
9867 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9868 we have a (gt X 0) operation. If the shift is arithmetic with
9869 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9870 we have a (neg (gt X 0)) operation. */
9872 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9873 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9874 && count == (unsigned int)
9875 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9876 && (code == LSHIFTRT || code == ASHIFTRT)
9877 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9878 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9880 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9883 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9886 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9887 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9894 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9895 if the truncate does not affect the value. */
9896 if (code == LSHIFTRT
9897 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9898 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9899 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9900 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9901 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9903 rtx varop_inner = XEXP (varop, 0);
9906 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9907 XEXP (varop_inner, 0),
9909 (count + INTVAL (XEXP (varop_inner, 1))));
9910 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9923 /* We need to determine what mode to do the shift in. If the shift is
9924 a right shift or ROTATE, we must always do it in the mode it was
9925 originally done in. Otherwise, we can do it in MODE, the widest mode
9926 encountered. The code we care about is that of the shift that will
9927 actually be done, not the shift that was originally requested. */
9929 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9930 ? result_mode : mode);
9932 /* We have now finished analyzing the shift. The result should be
9933 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9934 OUTER_OP is non-NIL, it is an operation that needs to be applied
9935 to the result of the shift. OUTER_CONST is the relevant constant,
9936 but we must turn off all bits turned off in the shift.
9938 If we were passed a value for X, see if we can use any pieces of
9939 it. If not, make new rtx. */
9941 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9942 && GET_CODE (XEXP (x, 1)) == CONST_INT
9943 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9944 const_rtx = XEXP (x, 1);
9946 const_rtx = GEN_INT (count);
9948 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9949 && GET_MODE (XEXP (x, 0)) == shift_mode
9950 && SUBREG_REG (XEXP (x, 0)) == varop)
9951 varop = XEXP (x, 0);
9952 else if (GET_MODE (varop) != shift_mode)
9953 varop = gen_lowpart_for_combine (shift_mode, varop);
9955 /* If we can't make the SUBREG, try to return what we were given. */
9956 if (GET_CODE (varop) == CLOBBER)
9957 return x ? x : varop;
9959 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9963 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9965 /* If we have an outer operation and we just made a shift, it is
9966 possible that we could have simplified the shift were it not
9967 for the outer operation. So try to do the simplification
9970 if (outer_op != NIL && GET_CODE (x) == code
9971 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9972 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9973 INTVAL (XEXP (x, 1)));
9975 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9976 turn off all the bits that the shift would have turned off. */
9977 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9978 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9979 GET_MODE_MASK (result_mode) >> orig_count);
9981 /* Do the remainder of the processing in RESULT_MODE. */
9982 x = gen_lowpart_for_combine (result_mode, x);
9984 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9987 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9989 if (outer_op != NIL)
9991 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9992 outer_const = trunc_int_for_mode (outer_const, result_mode);
9994 if (outer_op == AND)
9995 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9996 else if (outer_op == SET)
9997 /* This means that we have determined that the result is
9998 equivalent to a constant. This should be rare. */
9999 x = GEN_INT (outer_const);
10000 else if (GET_RTX_CLASS (outer_op) == '1')
10001 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10003 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
10009 /* Like recog, but we receive the address of a pointer to a new pattern.
10010 We try to match the rtx that the pointer points to.
10011 If that fails, we may try to modify or replace the pattern,
10012 storing the replacement into the same pointer object.
10014 Modifications include deletion or addition of CLOBBERs.
10016 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10017 the CLOBBERs are placed.
10019 The value is the final insn code from the pattern ultimately matched,
10023 recog_for_combine (pnewpat, insn, pnotes)
10028 rtx pat = *pnewpat;
10029 int insn_code_number;
10030 int num_clobbers_to_add = 0;
10035 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10036 we use to indicate that something didn't match. If we find such a
10037 thing, force rejection. */
10038 if (GET_CODE (pat) == PARALLEL)
10039 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10040 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10041 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10044 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
10045 instruction for pattern recognition. */
10046 dummy_insn = shallow_copy_rtx (insn);
10047 PATTERN (dummy_insn) = pat;
10048 REG_NOTES (dummy_insn) = 0;
10050 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
10052 /* If it isn't, there is the possibility that we previously had an insn
10053 that clobbered some register as a side effect, but the combined
10054 insn doesn't need to do that. So try once more without the clobbers
10055 unless this represents an ASM insn. */
10057 if (insn_code_number < 0 && ! check_asm_operands (pat)
10058 && GET_CODE (pat) == PARALLEL)
10062 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10063 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10066 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10070 SUBST_INT (XVECLEN (pat, 0), pos);
10073 pat = XVECEXP (pat, 0, 0);
10075 PATTERN (dummy_insn) = pat;
10076 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
10079 /* Recognize all noop sets, these will be killed by followup pass. */
10080 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10081 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10083 /* If we had any clobbers to add, make a new pattern than contains
10084 them. Then check to make sure that all of them are dead. */
10085 if (num_clobbers_to_add)
10087 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10088 rtvec_alloc (GET_CODE (pat) == PARALLEL
10089 ? (XVECLEN (pat, 0)
10090 + num_clobbers_to_add)
10091 : num_clobbers_to_add + 1));
10093 if (GET_CODE (pat) == PARALLEL)
10094 for (i = 0; i < XVECLEN (pat, 0); i++)
10095 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10097 XVECEXP (newpat, 0, 0) = pat;
10099 add_clobbers (newpat, insn_code_number);
10101 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10102 i < XVECLEN (newpat, 0); i++)
10104 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
10105 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10107 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
10108 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10116 return insn_code_number;
10119 /* Like gen_lowpart but for use by combine. In combine it is not possible
10120 to create any new pseudoregs. However, it is safe to create
10121 invalid memory addresses, because combine will try to recognize
10122 them and all they will do is make the combine attempt fail.
10124 If for some reason this cannot do its job, an rtx
10125 (clobber (const_int 0)) is returned.
10126 An insn containing that will not be recognized. */
10131 gen_lowpart_for_combine (mode, x)
10132 enum machine_mode mode;
10137 if (GET_MODE (x) == mode)
10140 /* We can only support MODE being wider than a word if X is a
10141 constant integer or has a mode the same size. */
10143 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
10144 && ! ((GET_MODE (x) == VOIDmode
10145 && (GET_CODE (x) == CONST_INT
10146 || GET_CODE (x) == CONST_DOUBLE))
10147 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
10148 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10150 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10151 won't know what to do. So we will strip off the SUBREG here and
10152 process normally. */
10153 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10155 x = SUBREG_REG (x);
10156 if (GET_MODE (x) == mode)
10160 result = gen_lowpart_common (mode, x);
10161 #ifdef CANNOT_CHANGE_MODE_CLASS
10163 && GET_CODE (result) == SUBREG
10164 && GET_CODE (SUBREG_REG (result)) == REG
10165 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10166 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
10168 + GET_MODE (result));
10174 if (GET_CODE (x) == MEM)
10178 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10180 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10181 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10183 /* If we want to refer to something bigger than the original memref,
10184 generate a perverse subreg instead. That will force a reload
10185 of the original memref X. */
10186 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10187 return gen_rtx_SUBREG (mode, x, 0);
10189 if (WORDS_BIG_ENDIAN)
10190 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10191 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10193 if (BYTES_BIG_ENDIAN)
10195 /* Adjust the address so that the address-after-the-data is
10197 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10198 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10201 return adjust_address_nv (x, mode, offset);
10204 /* If X is a comparison operator, rewrite it in a new mode. This
10205 probably won't match, but may allow further simplifications. */
10206 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10207 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10209 /* If we couldn't simplify X any other way, just enclose it in a
10210 SUBREG. Normally, this SUBREG won't match, but some patterns may
10211 include an explicit SUBREG or we may simplify it further in combine. */
10216 enum machine_mode sub_mode = GET_MODE (x);
10218 offset = subreg_lowpart_offset (mode, sub_mode);
10219 if (sub_mode == VOIDmode)
10221 sub_mode = int_mode_for_mode (mode);
10222 x = gen_lowpart_common (sub_mode, x);
10224 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10227 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10231 /* These routines make binary and unary operations by first seeing if they
10232 fold; if not, a new expression is allocated. */
10235 gen_binary (code, mode, op0, op1)
10236 enum rtx_code code;
10237 enum machine_mode mode;
10243 if (GET_CODE (op0) == CLOBBER)
10245 else if (GET_CODE (op1) == CLOBBER)
10248 if (GET_RTX_CLASS (code) == 'c'
10249 && swap_commutative_operands_p (op0, op1))
10250 tem = op0, op0 = op1, op1 = tem;
10252 if (GET_RTX_CLASS (code) == '<')
10254 enum machine_mode op_mode = GET_MODE (op0);
10256 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10257 just (REL_OP X Y). */
10258 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10260 op1 = XEXP (op0, 1);
10261 op0 = XEXP (op0, 0);
10262 op_mode = GET_MODE (op0);
10265 if (op_mode == VOIDmode)
10266 op_mode = GET_MODE (op1);
10267 result = simplify_relational_operation (code, op_mode, op0, op1);
10270 result = simplify_binary_operation (code, mode, op0, op1);
10275 /* Put complex operands first and constants second. */
10276 if (GET_RTX_CLASS (code) == 'c'
10277 && swap_commutative_operands_p (op0, op1))
10278 return gen_rtx_fmt_ee (code, mode, op1, op0);
10280 /* If we are turning off bits already known off in OP0, we need not do
10282 else if (code == AND && GET_CODE (op1) == CONST_INT
10283 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10284 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10287 return gen_rtx_fmt_ee (code, mode, op0, op1);
10290 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10291 comparison code that will be tested.
10293 The result is a possibly different comparison code to use. *POP0 and
10294 *POP1 may be updated.
10296 It is possible that we might detect that a comparison is either always
10297 true or always false. However, we do not perform general constant
10298 folding in combine, so this knowledge isn't useful. Such tautologies
10299 should have been detected earlier. Hence we ignore all such cases. */
10301 static enum rtx_code
10302 simplify_comparison (code, pop0, pop1)
10303 enum rtx_code code;
10311 enum machine_mode mode, tmode;
10313 /* Try a few ways of applying the same transformation to both operands. */
10316 #ifndef WORD_REGISTER_OPERATIONS
10317 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10318 so check specially. */
10319 if (code != GTU && code != GEU && code != LTU && code != LEU
10320 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10321 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10322 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10323 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10324 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10325 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10326 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10327 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10328 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10329 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10330 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10331 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10332 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10333 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10334 && (INTVAL (XEXP (op0, 1))
10335 == (GET_MODE_BITSIZE (GET_MODE (op0))
10336 - (GET_MODE_BITSIZE
10337 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10339 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10340 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10344 /* If both operands are the same constant shift, see if we can ignore the
10345 shift. We can if the shift is a rotate or if the bits shifted out of
10346 this shift are known to be zero for both inputs and if the type of
10347 comparison is compatible with the shift. */
10348 if (GET_CODE (op0) == GET_CODE (op1)
10349 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10350 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10351 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10352 && (code != GT && code != LT && code != GE && code != LE))
10353 || (GET_CODE (op0) == ASHIFTRT
10354 && (code != GTU && code != LTU
10355 && code != GEU && code != LEU)))
10356 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10357 && INTVAL (XEXP (op0, 1)) >= 0
10358 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10359 && XEXP (op0, 1) == XEXP (op1, 1))
10361 enum machine_mode mode = GET_MODE (op0);
10362 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10363 int shift_count = INTVAL (XEXP (op0, 1));
10365 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10366 mask &= (mask >> shift_count) << shift_count;
10367 else if (GET_CODE (op0) == ASHIFT)
10368 mask = (mask & (mask << shift_count)) >> shift_count;
10370 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10371 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10372 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10377 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10378 SUBREGs are of the same mode, and, in both cases, the AND would
10379 be redundant if the comparison was done in the narrower mode,
10380 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10381 and the operand's possibly nonzero bits are 0xffffff01; in that case
10382 if we only care about QImode, we don't need the AND). This case
10383 occurs if the output mode of an scc insn is not SImode and
10384 STORE_FLAG_VALUE == 1 (e.g., the 386).
10386 Similarly, check for a case where the AND's are ZERO_EXTEND
10387 operations from some narrower mode even though a SUBREG is not
10390 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10391 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10392 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10394 rtx inner_op0 = XEXP (op0, 0);
10395 rtx inner_op1 = XEXP (op1, 0);
10396 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10397 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10400 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10401 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10402 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10403 && (GET_MODE (SUBREG_REG (inner_op0))
10404 == GET_MODE (SUBREG_REG (inner_op1)))
10405 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10406 <= HOST_BITS_PER_WIDE_INT)
10407 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10408 GET_MODE (SUBREG_REG (inner_op0)))))
10409 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10410 GET_MODE (SUBREG_REG (inner_op1))))))
10412 op0 = SUBREG_REG (inner_op0);
10413 op1 = SUBREG_REG (inner_op1);
10415 /* The resulting comparison is always unsigned since we masked
10416 off the original sign bit. */
10417 code = unsigned_condition (code);
10423 for (tmode = GET_CLASS_NARROWEST_MODE
10424 (GET_MODE_CLASS (GET_MODE (op0)));
10425 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10426 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10428 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10429 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10430 code = unsigned_condition (code);
10439 /* If both operands are NOT, we can strip off the outer operation
10440 and adjust the comparison code for swapped operands; similarly for
10441 NEG, except that this must be an equality comparison. */
10442 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10443 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10444 && (code == EQ || code == NE)))
10445 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10451 /* If the first operand is a constant, swap the operands and adjust the
10452 comparison code appropriately, but don't do this if the second operand
10453 is already a constant integer. */
10454 if (swap_commutative_operands_p (op0, op1))
10456 tem = op0, op0 = op1, op1 = tem;
10457 code = swap_condition (code);
10460 /* We now enter a loop during which we will try to simplify the comparison.
10461 For the most part, we only are concerned with comparisons with zero,
10462 but some things may really be comparisons with zero but not start
10463 out looking that way. */
10465 while (GET_CODE (op1) == CONST_INT)
10467 enum machine_mode mode = GET_MODE (op0);
10468 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10469 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10470 int equality_comparison_p;
10471 int sign_bit_comparison_p;
10472 int unsigned_comparison_p;
10473 HOST_WIDE_INT const_op;
10475 /* We only want to handle integral modes. This catches VOIDmode,
10476 CCmode, and the floating-point modes. An exception is that we
10477 can handle VOIDmode if OP0 is a COMPARE or a comparison
10480 if (GET_MODE_CLASS (mode) != MODE_INT
10481 && ! (mode == VOIDmode
10482 && (GET_CODE (op0) == COMPARE
10483 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10486 /* Get the constant we are comparing against and turn off all bits
10487 not on in our mode. */
10488 const_op = INTVAL (op1);
10489 if (mode != VOIDmode)
10490 const_op = trunc_int_for_mode (const_op, mode);
10491 op1 = GEN_INT (const_op);
10493 /* If we are comparing against a constant power of two and the value
10494 being compared can only have that single bit nonzero (e.g., it was
10495 `and'ed with that bit), we can replace this with a comparison
10498 && (code == EQ || code == NE || code == GE || code == GEU
10499 || code == LT || code == LTU)
10500 && mode_width <= HOST_BITS_PER_WIDE_INT
10501 && exact_log2 (const_op) >= 0
10502 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10504 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10505 op1 = const0_rtx, const_op = 0;
10508 /* Similarly, if we are comparing a value known to be either -1 or
10509 0 with -1, change it to the opposite comparison against zero. */
10512 && (code == EQ || code == NE || code == GT || code == LE
10513 || code == GEU || code == LTU)
10514 && num_sign_bit_copies (op0, mode) == mode_width)
10516 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10517 op1 = const0_rtx, const_op = 0;
10520 /* Do some canonicalizations based on the comparison code. We prefer
10521 comparisons against zero and then prefer equality comparisons.
10522 If we can reduce the size of a constant, we will do that too. */
10527 /* < C is equivalent to <= (C - 1) */
10531 op1 = GEN_INT (const_op);
10533 /* ... fall through to LE case below. */
10539 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10543 op1 = GEN_INT (const_op);
10547 /* If we are doing a <= 0 comparison on a value known to have
10548 a zero sign bit, we can replace this with == 0. */
10549 else if (const_op == 0
10550 && mode_width <= HOST_BITS_PER_WIDE_INT
10551 && (nonzero_bits (op0, mode)
10552 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10557 /* >= C is equivalent to > (C - 1). */
10561 op1 = GEN_INT (const_op);
10563 /* ... fall through to GT below. */
10569 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10573 op1 = GEN_INT (const_op);
10577 /* If we are doing a > 0 comparison on a value known to have
10578 a zero sign bit, we can replace this with != 0. */
10579 else if (const_op == 0
10580 && mode_width <= HOST_BITS_PER_WIDE_INT
10581 && (nonzero_bits (op0, mode)
10582 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10587 /* < C is equivalent to <= (C - 1). */
10591 op1 = GEN_INT (const_op);
10593 /* ... fall through ... */
10596 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10597 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10598 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10600 const_op = 0, op1 = const0_rtx;
10608 /* unsigned <= 0 is equivalent to == 0 */
10612 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10613 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10614 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10616 const_op = 0, op1 = const0_rtx;
10622 /* >= C is equivalent to < (C - 1). */
10626 op1 = GEN_INT (const_op);
10628 /* ... fall through ... */
10631 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10632 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10633 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10635 const_op = 0, op1 = const0_rtx;
10643 /* unsigned > 0 is equivalent to != 0 */
10647 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10648 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10649 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10651 const_op = 0, op1 = const0_rtx;
10660 /* Compute some predicates to simplify code below. */
10662 equality_comparison_p = (code == EQ || code == NE);
10663 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10664 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10667 /* If this is a sign bit comparison and we can do arithmetic in
10668 MODE, say that we will only be needing the sign bit of OP0. */
10669 if (sign_bit_comparison_p
10670 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10671 op0 = force_to_mode (op0, mode,
10673 << (GET_MODE_BITSIZE (mode) - 1)),
10676 /* Now try cases based on the opcode of OP0. If none of the cases
10677 does a "continue", we exit this loop immediately after the
10680 switch (GET_CODE (op0))
10683 /* If we are extracting a single bit from a variable position in
10684 a constant that has only a single bit set and are comparing it
10685 with zero, we can convert this into an equality comparison
10686 between the position and the location of the single bit. */
10688 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10689 && XEXP (op0, 1) == const1_rtx
10690 && equality_comparison_p && const_op == 0
10691 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10693 if (BITS_BIG_ENDIAN)
10695 enum machine_mode new_mode
10696 = mode_for_extraction (EP_extzv, 1);
10697 if (new_mode == MAX_MACHINE_MODE)
10698 i = BITS_PER_WORD - 1 - i;
10702 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10706 op0 = XEXP (op0, 2);
10710 /* Result is nonzero iff shift count is equal to I. */
10711 code = reverse_condition (code);
10715 /* ... fall through ... */
10718 tem = expand_compound_operation (op0);
10727 /* If testing for equality, we can take the NOT of the constant. */
10728 if (equality_comparison_p
10729 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10731 op0 = XEXP (op0, 0);
10736 /* If just looking at the sign bit, reverse the sense of the
10738 if (sign_bit_comparison_p)
10740 op0 = XEXP (op0, 0);
10741 code = (code == GE ? LT : GE);
10747 /* If testing for equality, we can take the NEG of the constant. */
10748 if (equality_comparison_p
10749 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10751 op0 = XEXP (op0, 0);
10756 /* The remaining cases only apply to comparisons with zero. */
10760 /* When X is ABS or is known positive,
10761 (neg X) is < 0 if and only if X != 0. */
10763 if (sign_bit_comparison_p
10764 && (GET_CODE (XEXP (op0, 0)) == ABS
10765 || (mode_width <= HOST_BITS_PER_WIDE_INT
10766 && (nonzero_bits (XEXP (op0, 0), mode)
10767 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10769 op0 = XEXP (op0, 0);
10770 code = (code == LT ? NE : EQ);
10774 /* If we have NEG of something whose two high-order bits are the
10775 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10776 if (num_sign_bit_copies (op0, mode) >= 2)
10778 op0 = XEXP (op0, 0);
10779 code = swap_condition (code);
10785 /* If we are testing equality and our count is a constant, we
10786 can perform the inverse operation on our RHS. */
10787 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10788 && (tem = simplify_binary_operation (ROTATERT, mode,
10789 op1, XEXP (op0, 1))) != 0)
10791 op0 = XEXP (op0, 0);
10796 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10797 a particular bit. Convert it to an AND of a constant of that
10798 bit. This will be converted into a ZERO_EXTRACT. */
10799 if (const_op == 0 && sign_bit_comparison_p
10800 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10801 && mode_width <= HOST_BITS_PER_WIDE_INT)
10803 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10806 - INTVAL (XEXP (op0, 1)))));
10807 code = (code == LT ? NE : EQ);
10811 /* Fall through. */
10814 /* ABS is ignorable inside an equality comparison with zero. */
10815 if (const_op == 0 && equality_comparison_p)
10817 op0 = XEXP (op0, 0);
10823 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10824 to (compare FOO CONST) if CONST fits in FOO's mode and we
10825 are either testing inequality or have an unsigned comparison
10826 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10827 if (! unsigned_comparison_p
10828 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10829 <= HOST_BITS_PER_WIDE_INT)
10830 && ((unsigned HOST_WIDE_INT) const_op
10831 < (((unsigned HOST_WIDE_INT) 1
10832 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10834 op0 = XEXP (op0, 0);
10840 /* Check for the case where we are comparing A - C1 with C2,
10841 both constants are smaller than 1/2 the maximum positive
10842 value in MODE, and the comparison is equality or unsigned.
10843 In that case, if A is either zero-extended to MODE or has
10844 sufficient sign bits so that the high-order bit in MODE
10845 is a copy of the sign in the inner mode, we can prove that it is
10846 safe to do the operation in the wider mode. This simplifies
10847 many range checks. */
10849 if (mode_width <= HOST_BITS_PER_WIDE_INT
10850 && subreg_lowpart_p (op0)
10851 && GET_CODE (SUBREG_REG (op0)) == PLUS
10852 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10853 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10854 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10855 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10856 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10857 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10858 GET_MODE (SUBREG_REG (op0)))
10859 & ~GET_MODE_MASK (mode))
10860 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10861 GET_MODE (SUBREG_REG (op0)))
10863 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10864 - GET_MODE_BITSIZE (mode)))))
10866 op0 = SUBREG_REG (op0);
10870 /* If the inner mode is narrower and we are extracting the low part,
10871 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10872 if (subreg_lowpart_p (op0)
10873 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10874 /* Fall through */ ;
10878 /* ... fall through ... */
10881 if ((unsigned_comparison_p || equality_comparison_p)
10882 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10883 <= HOST_BITS_PER_WIDE_INT)
10884 && ((unsigned HOST_WIDE_INT) const_op
10885 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10887 op0 = XEXP (op0, 0);
10893 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10894 this for equality comparisons due to pathological cases involving
10896 if (equality_comparison_p
10897 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10898 op1, XEXP (op0, 1))))
10900 op0 = XEXP (op0, 0);
10905 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10906 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10907 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10909 op0 = XEXP (XEXP (op0, 0), 0);
10910 code = (code == LT ? EQ : NE);
10916 /* We used to optimize signed comparisons against zero, but that
10917 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10918 arrive here as equality comparisons, or (GEU, LTU) are
10919 optimized away. No need to special-case them. */
10921 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10922 (eq B (minus A C)), whichever simplifies. We can only do
10923 this for equality comparisons due to pathological cases involving
10925 if (equality_comparison_p
10926 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10927 XEXP (op0, 1), op1)))
10929 op0 = XEXP (op0, 0);
10934 if (equality_comparison_p
10935 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10936 XEXP (op0, 0), op1)))
10938 op0 = XEXP (op0, 1);
10943 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10944 of bits in X minus 1, is one iff X > 0. */
10945 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10946 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10947 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10949 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10951 op0 = XEXP (op0, 1);
10952 code = (code == GE ? LE : GT);
10958 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10959 if C is zero or B is a constant. */
10960 if (equality_comparison_p
10961 && 0 != (tem = simplify_binary_operation (XOR, mode,
10962 XEXP (op0, 1), op1)))
10964 op0 = XEXP (op0, 0);
10971 case UNEQ: case LTGT:
10972 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10973 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10974 case UNORDERED: case ORDERED:
10975 /* We can't do anything if OP0 is a condition code value, rather
10976 than an actual data value. */
10979 || XEXP (op0, 0) == cc0_rtx
10981 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10984 /* Get the two operands being compared. */
10985 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10986 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10988 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10990 /* Check for the cases where we simply want the result of the
10991 earlier test or the opposite of that result. */
10992 if (code == NE || code == EQ
10993 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10994 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10995 && (STORE_FLAG_VALUE
10996 & (((HOST_WIDE_INT) 1
10997 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10998 && (code == LT || code == GE)))
11000 enum rtx_code new_code;
11001 if (code == LT || code == NE)
11002 new_code = GET_CODE (op0);
11004 new_code = combine_reversed_comparison_code (op0);
11006 if (new_code != UNKNOWN)
11017 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11019 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11020 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11021 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11023 op0 = XEXP (op0, 1);
11024 code = (code == GE ? GT : LE);
11030 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11031 will be converted to a ZERO_EXTRACT later. */
11032 if (const_op == 0 && equality_comparison_p
11033 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11034 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11036 op0 = simplify_and_const_int
11037 (op0, mode, gen_rtx_LSHIFTRT (mode,
11039 XEXP (XEXP (op0, 0), 1)),
11040 (HOST_WIDE_INT) 1);
11044 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11045 zero and X is a comparison and C1 and C2 describe only bits set
11046 in STORE_FLAG_VALUE, we can compare with X. */
11047 if (const_op == 0 && equality_comparison_p
11048 && mode_width <= HOST_BITS_PER_WIDE_INT
11049 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11050 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11051 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11052 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11053 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11055 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11056 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11057 if ((~STORE_FLAG_VALUE & mask) == 0
11058 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
11059 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11060 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
11062 op0 = XEXP (XEXP (op0, 0), 0);
11067 /* If we are doing an equality comparison of an AND of a bit equal
11068 to the sign bit, replace this with a LT or GE comparison of
11069 the underlying value. */
11070 if (equality_comparison_p
11072 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11073 && mode_width <= HOST_BITS_PER_WIDE_INT
11074 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11075 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11077 op0 = XEXP (op0, 0);
11078 code = (code == EQ ? GE : LT);
11082 /* If this AND operation is really a ZERO_EXTEND from a narrower
11083 mode, the constant fits within that mode, and this is either an
11084 equality or unsigned comparison, try to do this comparison in
11085 the narrower mode. */
11086 if ((equality_comparison_p || unsigned_comparison_p)
11087 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11088 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11089 & GET_MODE_MASK (mode))
11091 && const_op >> i == 0
11092 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
11094 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
11098 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
11099 in both M1 and M2 and the SUBREG is either paradoxical or
11100 represents the low part, permute the SUBREG and the AND and
11102 if (GET_CODE (XEXP (op0, 0)) == SUBREG
11103 /* Require an integral mode, to avoid creating something like
11105 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
11107 #ifdef WORD_REGISTER_OPERATIONS
11109 > (GET_MODE_BITSIZE
11110 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
11111 && mode_width <= BITS_PER_WORD)
11114 <= (GET_MODE_BITSIZE
11115 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
11116 && subreg_lowpart_p (XEXP (op0, 0))))
11117 #ifndef WORD_REGISTER_OPERATIONS
11118 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
11119 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
11120 As originally written the upper bits have a defined value
11121 due to the AND operation. However, if we commute the AND
11122 inside the SUBREG then they no longer have defined values
11123 and the meaning of the code has been changed. */
11124 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
11125 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
11127 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11128 && mode_width <= HOST_BITS_PER_WIDE_INT
11129 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
11130 <= HOST_BITS_PER_WIDE_INT)
11131 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
11132 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
11133 & INTVAL (XEXP (op0, 1)))
11134 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
11135 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11136 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
11140 = gen_lowpart_for_combine
11142 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
11143 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
11147 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11148 (eq (and (lshiftrt X) 1) 0). */
11149 if (const_op == 0 && equality_comparison_p
11150 && XEXP (op0, 1) == const1_rtx
11151 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11152 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
11154 op0 = simplify_and_const_int
11156 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
11157 XEXP (XEXP (op0, 0), 1)),
11158 (HOST_WIDE_INT) 1);
11159 code = (code == NE ? EQ : NE);
11165 /* If we have (compare (ashift FOO N) (const_int C)) and
11166 the high order N bits of FOO (N+1 if an inequality comparison)
11167 are known to be zero, we can do this by comparing FOO with C
11168 shifted right N bits so long as the low-order N bits of C are
11170 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11171 && INTVAL (XEXP (op0, 1)) >= 0
11172 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11173 < HOST_BITS_PER_WIDE_INT)
11175 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11176 && mode_width <= HOST_BITS_PER_WIDE_INT
11177 && (nonzero_bits (XEXP (op0, 0), mode)
11178 & ~(mask >> (INTVAL (XEXP (op0, 1))
11179 + ! equality_comparison_p))) == 0)
11181 /* We must perform a logical shift, not an arithmetic one,
11182 as we want the top N bits of C to be zero. */
11183 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11185 temp >>= INTVAL (XEXP (op0, 1));
11186 op1 = gen_int_mode (temp, mode);
11187 op0 = XEXP (op0, 0);
11191 /* If we are doing a sign bit comparison, it means we are testing
11192 a particular bit. Convert it to the appropriate AND. */
11193 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11194 && mode_width <= HOST_BITS_PER_WIDE_INT)
11196 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11199 - INTVAL (XEXP (op0, 1)))));
11200 code = (code == LT ? NE : EQ);
11204 /* If this an equality comparison with zero and we are shifting
11205 the low bit to the sign bit, we can convert this to an AND of the
11207 if (const_op == 0 && equality_comparison_p
11208 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11209 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11212 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11213 (HOST_WIDE_INT) 1);
11219 /* If this is an equality comparison with zero, we can do this
11220 as a logical shift, which might be much simpler. */
11221 if (equality_comparison_p && const_op == 0
11222 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11224 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11226 INTVAL (XEXP (op0, 1)));
11230 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11231 do the comparison in a narrower mode. */
11232 if (! unsigned_comparison_p
11233 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11234 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11235 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11236 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11237 MODE_INT, 1)) != BLKmode
11238 && (((unsigned HOST_WIDE_INT) const_op
11239 + (GET_MODE_MASK (tmode) >> 1) + 1)
11240 <= GET_MODE_MASK (tmode)))
11242 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11246 /* Likewise if OP0 is a PLUS of a sign extension with a
11247 constant, which is usually represented with the PLUS
11248 between the shifts. */
11249 if (! unsigned_comparison_p
11250 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11251 && GET_CODE (XEXP (op0, 0)) == PLUS
11252 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11253 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11254 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11255 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11256 MODE_INT, 1)) != BLKmode
11257 && (((unsigned HOST_WIDE_INT) const_op
11258 + (GET_MODE_MASK (tmode) >> 1) + 1)
11259 <= GET_MODE_MASK (tmode)))
11261 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11262 rtx add_const = XEXP (XEXP (op0, 0), 1);
11263 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11266 op0 = gen_binary (PLUS, tmode,
11267 gen_lowpart_for_combine (tmode, inner),
11272 /* ... fall through ... */
11274 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11275 the low order N bits of FOO are known to be zero, we can do this
11276 by comparing FOO with C shifted left N bits so long as no
11277 overflow occurs. */
11278 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11279 && INTVAL (XEXP (op0, 1)) >= 0
11280 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11281 && mode_width <= HOST_BITS_PER_WIDE_INT
11282 && (nonzero_bits (XEXP (op0, 0), mode)
11283 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11284 && (((unsigned HOST_WIDE_INT) const_op
11285 + (GET_CODE (op0) != LSHIFTRT
11286 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11289 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11291 /* If the shift was logical, then we must make the condition
11293 if (GET_CODE (op0) == LSHIFTRT)
11294 code = unsigned_condition (code);
11296 const_op <<= INTVAL (XEXP (op0, 1));
11297 op1 = GEN_INT (const_op);
11298 op0 = XEXP (op0, 0);
11302 /* If we are using this shift to extract just the sign bit, we
11303 can replace this with an LT or GE comparison. */
11305 && (equality_comparison_p || sign_bit_comparison_p)
11306 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11307 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11310 op0 = XEXP (op0, 0);
11311 code = (code == NE || code == GT ? LT : GE);
11323 /* Now make any compound operations involved in this comparison. Then,
11324 check for an outmost SUBREG on OP0 that is not doing anything or is
11325 paradoxical. The latter transformation must only be performed when
11326 it is known that the "extra" bits will be the same in op0 and op1 or
11327 that they don't matter. There are three cases to consider:
11329 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11330 care bits and we can assume they have any convenient value. So
11331 making the transformation is safe.
11333 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11334 In this case the upper bits of op0 are undefined. We should not make
11335 the simplification in that case as we do not know the contents of
11338 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11339 NIL. In that case we know those bits are zeros or ones. We must
11340 also be sure that they are the same as the upper bits of op1.
11342 We can never remove a SUBREG for a non-equality comparison because
11343 the sign bit is in a different place in the underlying object. */
11345 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11346 op1 = make_compound_operation (op1, SET);
11348 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11349 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11351 && GET_CODE (SUBREG_REG (op0)) == REG
11352 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11353 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11354 && (code == NE || code == EQ))
11356 if (GET_MODE_SIZE (GET_MODE (op0))
11357 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11359 op0 = SUBREG_REG (op0);
11360 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11362 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11363 <= HOST_BITS_PER_WIDE_INT)
11364 && (nonzero_bits (SUBREG_REG (op0),
11365 GET_MODE (SUBREG_REG (op0)))
11366 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11368 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11370 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11371 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11372 op0 = SUBREG_REG (op0), op1 = tem;
11376 /* We now do the opposite procedure: Some machines don't have compare
11377 insns in all modes. If OP0's mode is an integer mode smaller than a
11378 word and we can't do a compare in that mode, see if there is a larger
11379 mode for which we can do the compare. There are a number of cases in
11380 which we can use the wider mode. */
11382 mode = GET_MODE (op0);
11383 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11384 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11385 && ! have_insn_for (COMPARE, mode))
11386 for (tmode = GET_MODE_WIDER_MODE (mode);
11388 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11389 tmode = GET_MODE_WIDER_MODE (tmode))
11390 if (have_insn_for (COMPARE, tmode))
11394 /* If the only nonzero bits in OP0 and OP1 are those in the
11395 narrower mode and this is an equality or unsigned comparison,
11396 we can use the wider mode. Similarly for sign-extended
11397 values, in which case it is true for all comparisons. */
11398 zero_extended = ((code == EQ || code == NE
11399 || code == GEU || code == GTU
11400 || code == LEU || code == LTU)
11401 && (nonzero_bits (op0, tmode)
11402 & ~GET_MODE_MASK (mode)) == 0
11403 && ((GET_CODE (op1) == CONST_INT
11404 || (nonzero_bits (op1, tmode)
11405 & ~GET_MODE_MASK (mode)) == 0)));
11408 || ((num_sign_bit_copies (op0, tmode)
11409 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11410 - GET_MODE_BITSIZE (mode)))
11411 && (num_sign_bit_copies (op1, tmode)
11412 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11413 - GET_MODE_BITSIZE (mode)))))
11415 /* If OP0 is an AND and we don't have an AND in MODE either,
11416 make a new AND in the proper mode. */
11417 if (GET_CODE (op0) == AND
11418 && !have_insn_for (AND, mode))
11419 op0 = gen_binary (AND, tmode,
11420 gen_lowpart_for_combine (tmode,
11422 gen_lowpart_for_combine (tmode,
11425 op0 = gen_lowpart_for_combine (tmode, op0);
11426 if (zero_extended && GET_CODE (op1) == CONST_INT)
11427 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11428 op1 = gen_lowpart_for_combine (tmode, op1);
11432 /* If this is a test for negative, we can make an explicit
11433 test of the sign bit. */
11435 if (op1 == const0_rtx && (code == LT || code == GE)
11436 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11438 op0 = gen_binary (AND, tmode,
11439 gen_lowpart_for_combine (tmode, op0),
11440 GEN_INT ((HOST_WIDE_INT) 1
11441 << (GET_MODE_BITSIZE (mode) - 1)));
11442 code = (code == LT) ? NE : EQ;
11447 #ifdef CANONICALIZE_COMPARISON
11448 /* If this machine only supports a subset of valid comparisons, see if we
11449 can convert an unsupported one into a supported one. */
11450 CANONICALIZE_COMPARISON (code, op0, op1);
11459 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11460 searching backward. */
11461 static enum rtx_code
11462 combine_reversed_comparison_code (exp)
11465 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11468 if (code1 != UNKNOWN
11469 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11471 /* Otherwise try and find where the condition codes were last set and
11473 x = get_last_value (XEXP (exp, 0));
11474 if (!x || GET_CODE (x) != COMPARE)
11476 return reversed_comparison_code_parts (GET_CODE (exp),
11477 XEXP (x, 0), XEXP (x, 1), NULL);
11479 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11480 Return NULL_RTX in case we fail to do the reversal. */
11482 reversed_comparison (exp, mode, op0, op1)
11484 enum machine_mode mode;
11486 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11487 if (reversed_code == UNKNOWN)
11490 return gen_binary (reversed_code, mode, op0, op1);
11493 /* Utility function for following routine. Called when X is part of a value
11494 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11495 for each register mentioned. Similar to mention_regs in cse.c */
11498 update_table_tick (x)
11501 enum rtx_code code = GET_CODE (x);
11502 const char *fmt = GET_RTX_FORMAT (code);
11507 unsigned int regno = REGNO (x);
11508 unsigned int endregno
11509 = regno + (regno < FIRST_PSEUDO_REGISTER
11510 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11513 for (r = regno; r < endregno; r++)
11514 reg_last_set_table_tick[r] = label_tick;
11519 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11520 /* Note that we can't have an "E" in values stored; see
11521 get_last_value_validate. */
11524 /* Check for identical subexpressions. If x contains
11525 identical subexpression we only have to traverse one of
11528 && (GET_RTX_CLASS (code) == '2'
11529 || GET_RTX_CLASS (code) == 'c'))
11531 /* Note that at this point x1 has already been
11533 rtx x0 = XEXP (x, 0);
11534 rtx x1 = XEXP (x, 1);
11536 /* If x0 and x1 are identical then there is no need to
11541 /* If x0 is identical to a subexpression of x1 then while
11542 processing x1, x0 has already been processed. Thus we
11543 are done with x. */
11544 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11545 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11546 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11549 /* If x1 is identical to a subexpression of x0 then we
11550 still have to process the rest of x0. */
11551 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11552 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11553 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11555 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11560 update_table_tick (XEXP (x, i));
11564 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11565 are saying that the register is clobbered and we no longer know its
11566 value. If INSN is zero, don't update reg_last_set; this is only permitted
11567 with VALUE also zero and is used to invalidate the register. */
11570 record_value_for_reg (reg, insn, value)
11575 unsigned int regno = REGNO (reg);
11576 unsigned int endregno
11577 = regno + (regno < FIRST_PSEUDO_REGISTER
11578 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11581 /* If VALUE contains REG and we have a previous value for REG, substitute
11582 the previous value. */
11583 if (value && insn && reg_overlap_mentioned_p (reg, value))
11587 /* Set things up so get_last_value is allowed to see anything set up to
11589 subst_low_cuid = INSN_CUID (insn);
11590 tem = get_last_value (reg);
11592 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11593 it isn't going to be useful and will take a lot of time to process,
11594 so just use the CLOBBER. */
11598 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11599 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11600 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11601 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11602 tem = XEXP (tem, 0);
11604 value = replace_rtx (copy_rtx (value), reg, tem);
11608 /* For each register modified, show we don't know its value, that
11609 we don't know about its bitwise content, that its value has been
11610 updated, and that we don't know the location of the death of the
11612 for (i = regno; i < endregno; i++)
11615 reg_last_set[i] = insn;
11617 reg_last_set_value[i] = 0;
11618 reg_last_set_mode[i] = 0;
11619 reg_last_set_nonzero_bits[i] = 0;
11620 reg_last_set_sign_bit_copies[i] = 0;
11621 reg_last_death[i] = 0;
11624 /* Mark registers that are being referenced in this value. */
11626 update_table_tick (value);
11628 /* Now update the status of each register being set.
11629 If someone is using this register in this block, set this register
11630 to invalid since we will get confused between the two lives in this
11631 basic block. This makes using this register always invalid. In cse, we
11632 scan the table to invalidate all entries using this register, but this
11633 is too much work for us. */
11635 for (i = regno; i < endregno; i++)
11637 reg_last_set_label[i] = label_tick;
11638 if (value && reg_last_set_table_tick[i] == label_tick)
11639 reg_last_set_invalid[i] = 1;
11641 reg_last_set_invalid[i] = 0;
11644 /* The value being assigned might refer to X (like in "x++;"). In that
11645 case, we must replace it with (clobber (const_int 0)) to prevent
11647 if (value && ! get_last_value_validate (&value, insn,
11648 reg_last_set_label[regno], 0))
11650 value = copy_rtx (value);
11651 if (! get_last_value_validate (&value, insn,
11652 reg_last_set_label[regno], 1))
11656 /* For the main register being modified, update the value, the mode, the
11657 nonzero bits, and the number of sign bit copies. */
11659 reg_last_set_value[regno] = value;
11663 enum machine_mode mode = GET_MODE (reg);
11664 subst_low_cuid = INSN_CUID (insn);
11665 reg_last_set_mode[regno] = mode;
11666 if (GET_MODE_CLASS (mode) == MODE_INT
11667 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11668 mode = nonzero_bits_mode;
11669 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11670 reg_last_set_sign_bit_copies[regno]
11671 = num_sign_bit_copies (value, GET_MODE (reg));
11675 /* Called via note_stores from record_dead_and_set_regs to handle one
11676 SET or CLOBBER in an insn. DATA is the instruction in which the
11677 set is occurring. */
11680 record_dead_and_set_regs_1 (dest, setter, data)
11684 rtx record_dead_insn = (rtx) data;
11686 if (GET_CODE (dest) == SUBREG)
11687 dest = SUBREG_REG (dest);
11689 if (GET_CODE (dest) == REG)
11691 /* If we are setting the whole register, we know its value. Otherwise
11692 show that we don't know the value. We can handle SUBREG in
11694 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11695 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11696 else if (GET_CODE (setter) == SET
11697 && GET_CODE (SET_DEST (setter)) == SUBREG
11698 && SUBREG_REG (SET_DEST (setter)) == dest
11699 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11700 && subreg_lowpart_p (SET_DEST (setter)))
11701 record_value_for_reg (dest, record_dead_insn,
11702 gen_lowpart_for_combine (GET_MODE (dest),
11703 SET_SRC (setter)));
11705 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11707 else if (GET_CODE (dest) == MEM
11708 /* Ignore pushes, they clobber nothing. */
11709 && ! push_operand (dest, GET_MODE (dest)))
11710 mem_last_set = INSN_CUID (record_dead_insn);
11713 /* Update the records of when each REG was most recently set or killed
11714 for the things done by INSN. This is the last thing done in processing
11715 INSN in the combiner loop.
11717 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11718 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11719 and also the similar information mem_last_set (which insn most recently
11720 modified memory) and last_call_cuid (which insn was the most recent
11721 subroutine call). */
11724 record_dead_and_set_regs (insn)
11730 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11732 if (REG_NOTE_KIND (link) == REG_DEAD
11733 && GET_CODE (XEXP (link, 0)) == REG)
11735 unsigned int regno = REGNO (XEXP (link, 0));
11736 unsigned int endregno
11737 = regno + (regno < FIRST_PSEUDO_REGISTER
11738 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11741 for (i = regno; i < endregno; i++)
11742 reg_last_death[i] = insn;
11744 else if (REG_NOTE_KIND (link) == REG_INC)
11745 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11748 if (GET_CODE (insn) == CALL_INSN)
11750 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11751 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11753 reg_last_set_value[i] = 0;
11754 reg_last_set_mode[i] = 0;
11755 reg_last_set_nonzero_bits[i] = 0;
11756 reg_last_set_sign_bit_copies[i] = 0;
11757 reg_last_death[i] = 0;
11760 last_call_cuid = mem_last_set = INSN_CUID (insn);
11762 /* Don't bother recording what this insn does. It might set the
11763 return value register, but we can't combine into a call
11764 pattern anyway, so there's no point trying (and it may cause
11765 a crash, if e.g. we wind up asking for last_set_value of a
11766 SUBREG of the return value register). */
11770 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11773 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11774 register present in the SUBREG, so for each such SUBREG go back and
11775 adjust nonzero and sign bit information of the registers that are
11776 known to have some zero/sign bits set.
11778 This is needed because when combine blows the SUBREGs away, the
11779 information on zero/sign bits is lost and further combines can be
11780 missed because of that. */
11783 record_promoted_value (insn, subreg)
11788 unsigned int regno = REGNO (SUBREG_REG (subreg));
11789 enum machine_mode mode = GET_MODE (subreg);
11791 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11794 for (links = LOG_LINKS (insn); links;)
11796 insn = XEXP (links, 0);
11797 set = single_set (insn);
11799 if (! set || GET_CODE (SET_DEST (set)) != REG
11800 || REGNO (SET_DEST (set)) != regno
11801 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11803 links = XEXP (links, 1);
11807 if (reg_last_set[regno] == insn)
11809 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11810 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11813 if (GET_CODE (SET_SRC (set)) == REG)
11815 regno = REGNO (SET_SRC (set));
11816 links = LOG_LINKS (insn);
11823 /* Scan X for promoted SUBREGs. For each one found,
11824 note what it implies to the registers used in it. */
11827 check_promoted_subreg (insn, x)
11831 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11832 && GET_CODE (SUBREG_REG (x)) == REG)
11833 record_promoted_value (insn, x);
11836 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11839 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11843 check_promoted_subreg (insn, XEXP (x, i));
11847 if (XVEC (x, i) != 0)
11848 for (j = 0; j < XVECLEN (x, i); j++)
11849 check_promoted_subreg (insn, XVECEXP (x, i, j));
11855 /* Utility routine for the following function. Verify that all the registers
11856 mentioned in *LOC are valid when *LOC was part of a value set when
11857 label_tick == TICK. Return 0 if some are not.
11859 If REPLACE is nonzero, replace the invalid reference with
11860 (clobber (const_int 0)) and return 1. This replacement is useful because
11861 we often can get useful information about the form of a value (e.g., if
11862 it was produced by a shift that always produces -1 or 0) even though
11863 we don't know exactly what registers it was produced from. */
11866 get_last_value_validate (loc, insn, tick, replace)
11873 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11874 int len = GET_RTX_LENGTH (GET_CODE (x));
11877 if (GET_CODE (x) == REG)
11879 unsigned int regno = REGNO (x);
11880 unsigned int endregno
11881 = regno + (regno < FIRST_PSEUDO_REGISTER
11882 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11885 for (j = regno; j < endregno; j++)
11886 if (reg_last_set_invalid[j]
11887 /* If this is a pseudo-register that was only set once and not
11888 live at the beginning of the function, it is always valid. */
11889 || (! (regno >= FIRST_PSEUDO_REGISTER
11890 && REG_N_SETS (regno) == 1
11891 && (! REGNO_REG_SET_P
11892 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11893 && reg_last_set_label[j] > tick))
11896 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11902 /* If this is a memory reference, make sure that there were
11903 no stores after it that might have clobbered the value. We don't
11904 have alias info, so we assume any store invalidates it. */
11905 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11906 && INSN_CUID (insn) <= mem_last_set)
11909 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11913 for (i = 0; i < len; i++)
11917 /* Check for identical subexpressions. If x contains
11918 identical subexpression we only have to traverse one of
11921 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11922 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11924 /* Note that at this point x0 has already been checked
11925 and found valid. */
11926 rtx x0 = XEXP (x, 0);
11927 rtx x1 = XEXP (x, 1);
11929 /* If x0 and x1 are identical then x is also valid. */
11933 /* If x1 is identical to a subexpression of x0 then
11934 while checking x0, x1 has already been checked. Thus
11935 it is valid and so as x. */
11936 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11937 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11938 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11941 /* If x0 is identical to a subexpression of x1 then x is
11942 valid iff the rest of x1 is valid. */
11943 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11944 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11945 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11947 get_last_value_validate (&XEXP (x1,
11948 x0 == XEXP (x1, 0) ? 1 : 0),
11949 insn, tick, replace);
11952 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11956 /* Don't bother with these. They shouldn't occur anyway. */
11957 else if (fmt[i] == 'E')
11961 /* If we haven't found a reason for it to be invalid, it is valid. */
11965 /* Get the last value assigned to X, if known. Some registers
11966 in the value may be replaced with (clobber (const_int 0)) if their value
11967 is known longer known reliably. */
11973 unsigned int regno;
11976 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11977 then convert it to the desired mode. If this is a paradoxical SUBREG,
11978 we cannot predict what values the "extra" bits might have. */
11979 if (GET_CODE (x) == SUBREG
11980 && subreg_lowpart_p (x)
11981 && (GET_MODE_SIZE (GET_MODE (x))
11982 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11983 && (value = get_last_value (SUBREG_REG (x))) != 0)
11984 return gen_lowpart_for_combine (GET_MODE (x), value);
11986 if (GET_CODE (x) != REG)
11990 value = reg_last_set_value[regno];
11992 /* If we don't have a value, or if it isn't for this basic block and
11993 it's either a hard register, set more than once, or it's a live
11994 at the beginning of the function, return 0.
11996 Because if it's not live at the beginning of the function then the reg
11997 is always set before being used (is never used without being set).
11998 And, if it's set only once, and it's always set before use, then all
11999 uses must have the same last value, even if it's not from this basic
12003 || (reg_last_set_label[regno] != label_tick
12004 && (regno < FIRST_PSEUDO_REGISTER
12005 || REG_N_SETS (regno) != 1
12006 || (REGNO_REG_SET_P
12007 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
12010 /* If the value was set in a later insn than the ones we are processing,
12011 we can't use it even if the register was only set once. */
12012 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
12015 /* If the value has all its registers valid, return it. */
12016 if (get_last_value_validate (&value, reg_last_set[regno],
12017 reg_last_set_label[regno], 0))
12020 /* Otherwise, make a copy and replace any invalid register with
12021 (clobber (const_int 0)). If that fails for some reason, return 0. */
12023 value = copy_rtx (value);
12024 if (get_last_value_validate (&value, reg_last_set[regno],
12025 reg_last_set_label[regno], 1))
12031 /* Return nonzero if expression X refers to a REG or to memory
12032 that is set in an instruction more recent than FROM_CUID. */
12035 use_crosses_set_p (x, from_cuid)
12041 enum rtx_code code = GET_CODE (x);
12045 unsigned int regno = REGNO (x);
12046 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
12047 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
12049 #ifdef PUSH_ROUNDING
12050 /* Don't allow uses of the stack pointer to be moved,
12051 because we don't know whether the move crosses a push insn. */
12052 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12055 for (; regno < endreg; regno++)
12056 if (reg_last_set[regno]
12057 && INSN_CUID (reg_last_set[regno]) > from_cuid)
12062 if (code == MEM && mem_last_set > from_cuid)
12065 fmt = GET_RTX_FORMAT (code);
12067 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12072 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12073 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
12076 else if (fmt[i] == 'e'
12077 && use_crosses_set_p (XEXP (x, i), from_cuid))
12083 /* Define three variables used for communication between the following
12086 static unsigned int reg_dead_regno, reg_dead_endregno;
12087 static int reg_dead_flag;
12089 /* Function called via note_stores from reg_dead_at_p.
12091 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12092 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12095 reg_dead_at_p_1 (dest, x, data)
12098 void *data ATTRIBUTE_UNUSED;
12100 unsigned int regno, endregno;
12102 if (GET_CODE (dest) != REG)
12105 regno = REGNO (dest);
12106 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
12107 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
12109 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12110 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12113 /* Return nonzero if REG is known to be dead at INSN.
12115 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12116 referencing REG, it is dead. If we hit a SET referencing REG, it is
12117 live. Otherwise, see if it is live or dead at the start of the basic
12118 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12119 must be assumed to be always live. */
12122 reg_dead_at_p (reg, insn)
12129 /* Set variables for reg_dead_at_p_1. */
12130 reg_dead_regno = REGNO (reg);
12131 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
12132 ? HARD_REGNO_NREGS (reg_dead_regno,
12138 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
12139 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12141 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12142 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
12146 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12147 beginning of function. */
12148 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
12149 insn = prev_nonnote_insn (insn))
12151 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12153 return reg_dead_flag == 1 ? 1 : 0;
12155 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12159 /* Get the basic block that we were in. */
12161 block = ENTRY_BLOCK_PTR->next_bb;
12164 FOR_EACH_BB (block)
12165 if (insn == block->head)
12168 if (block == EXIT_BLOCK_PTR)
12172 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12173 if (REGNO_REG_SET_P (block->global_live_at_start, i))
12179 /* Note hard registers in X that are used. This code is similar to
12180 that in flow.c, but much simpler since we don't care about pseudos. */
12183 mark_used_regs_combine (x)
12186 RTX_CODE code = GET_CODE (x);
12187 unsigned int regno;
12200 case ADDR_DIFF_VEC:
12203 /* CC0 must die in the insn after it is set, so we don't need to take
12204 special note of it here. */
12210 /* If we are clobbering a MEM, mark any hard registers inside the
12211 address as used. */
12212 if (GET_CODE (XEXP (x, 0)) == MEM)
12213 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12218 /* A hard reg in a wide mode may really be multiple registers.
12219 If so, mark all of them just like the first. */
12220 if (regno < FIRST_PSEUDO_REGISTER)
12222 unsigned int endregno, r;
12224 /* None of this applies to the stack, frame or arg pointers. */
12225 if (regno == STACK_POINTER_REGNUM
12226 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12227 || regno == HARD_FRAME_POINTER_REGNUM
12229 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12230 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12232 || regno == FRAME_POINTER_REGNUM)
12235 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12236 for (r = regno; r < endregno; r++)
12237 SET_HARD_REG_BIT (newpat_used_regs, r);
12243 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12245 rtx testreg = SET_DEST (x);
12247 while (GET_CODE (testreg) == SUBREG
12248 || GET_CODE (testreg) == ZERO_EXTRACT
12249 || GET_CODE (testreg) == SIGN_EXTRACT
12250 || GET_CODE (testreg) == STRICT_LOW_PART)
12251 testreg = XEXP (testreg, 0);
12253 if (GET_CODE (testreg) == MEM)
12254 mark_used_regs_combine (XEXP (testreg, 0));
12256 mark_used_regs_combine (SET_SRC (x));
12264 /* Recursively scan the operands of this expression. */
12267 const char *fmt = GET_RTX_FORMAT (code);
12269 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12272 mark_used_regs_combine (XEXP (x, i));
12273 else if (fmt[i] == 'E')
12277 for (j = 0; j < XVECLEN (x, i); j++)
12278 mark_used_regs_combine (XVECEXP (x, i, j));
12284 /* Remove register number REGNO from the dead registers list of INSN.
12286 Return the note used to record the death, if there was one. */
12289 remove_death (regno, insn)
12290 unsigned int regno;
12293 rtx note = find_regno_note (insn, REG_DEAD, regno);
12297 REG_N_DEATHS (regno)--;
12298 remove_note (insn, note);
12304 /* For each register (hardware or pseudo) used within expression X, if its
12305 death is in an instruction with cuid between FROM_CUID (inclusive) and
12306 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12307 list headed by PNOTES.
12309 That said, don't move registers killed by maybe_kill_insn.
12311 This is done when X is being merged by combination into TO_INSN. These
12312 notes will then be distributed as needed. */
12315 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
12317 rtx maybe_kill_insn;
12324 enum rtx_code code = GET_CODE (x);
12328 unsigned int regno = REGNO (x);
12329 rtx where_dead = reg_last_death[regno];
12330 rtx before_dead, after_dead;
12332 /* Don't move the register if it gets killed in between from and to. */
12333 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12334 && ! reg_referenced_p (x, maybe_kill_insn))
12337 /* WHERE_DEAD could be a USE insn made by combine, so first we
12338 make sure that we have insns with valid INSN_CUID values. */
12339 before_dead = where_dead;
12340 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12341 before_dead = PREV_INSN (before_dead);
12343 after_dead = where_dead;
12344 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12345 after_dead = NEXT_INSN (after_dead);
12347 if (before_dead && after_dead
12348 && INSN_CUID (before_dead) >= from_cuid
12349 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12350 || (where_dead != after_dead
12351 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12353 rtx note = remove_death (regno, where_dead);
12355 /* It is possible for the call above to return 0. This can occur
12356 when reg_last_death points to I2 or I1 that we combined with.
12357 In that case make a new note.
12359 We must also check for the case where X is a hard register
12360 and NOTE is a death note for a range of hard registers
12361 including X. In that case, we must put REG_DEAD notes for
12362 the remaining registers in place of NOTE. */
12364 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12365 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12366 > GET_MODE_SIZE (GET_MODE (x))))
12368 unsigned int deadregno = REGNO (XEXP (note, 0));
12369 unsigned int deadend
12370 = (deadregno + HARD_REGNO_NREGS (deadregno,
12371 GET_MODE (XEXP (note, 0))));
12372 unsigned int ourend
12373 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12376 for (i = deadregno; i < deadend; i++)
12377 if (i < regno || i >= ourend)
12378 REG_NOTES (where_dead)
12379 = gen_rtx_EXPR_LIST (REG_DEAD,
12381 REG_NOTES (where_dead));
12384 /* If we didn't find any note, or if we found a REG_DEAD note that
12385 covers only part of the given reg, and we have a multi-reg hard
12386 register, then to be safe we must check for REG_DEAD notes
12387 for each register other than the first. They could have
12388 their own REG_DEAD notes lying around. */
12389 else if ((note == 0
12391 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12392 < GET_MODE_SIZE (GET_MODE (x)))))
12393 && regno < FIRST_PSEUDO_REGISTER
12394 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12396 unsigned int ourend
12397 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12398 unsigned int i, offset;
12402 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12406 for (i = regno + offset; i < ourend; i++)
12407 move_deaths (regno_reg_rtx[i],
12408 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12411 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12413 XEXP (note, 1) = *pnotes;
12417 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12419 REG_N_DEATHS (regno)++;
12425 else if (GET_CODE (x) == SET)
12427 rtx dest = SET_DEST (x);
12429 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12431 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12432 that accesses one word of a multi-word item, some
12433 piece of everything register in the expression is used by
12434 this insn, so remove any old death. */
12435 /* ??? So why do we test for equality of the sizes? */
12437 if (GET_CODE (dest) == ZERO_EXTRACT
12438 || GET_CODE (dest) == STRICT_LOW_PART
12439 || (GET_CODE (dest) == SUBREG
12440 && (((GET_MODE_SIZE (GET_MODE (dest))
12441 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12442 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12443 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12445 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12449 /* If this is some other SUBREG, we know it replaces the entire
12450 value, so use that as the destination. */
12451 if (GET_CODE (dest) == SUBREG)
12452 dest = SUBREG_REG (dest);
12454 /* If this is a MEM, adjust deaths of anything used in the address.
12455 For a REG (the only other possibility), the entire value is
12456 being replaced so the old value is not used in this insn. */
12458 if (GET_CODE (dest) == MEM)
12459 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12464 else if (GET_CODE (x) == CLOBBER)
12467 len = GET_RTX_LENGTH (code);
12468 fmt = GET_RTX_FORMAT (code);
12470 for (i = 0; i < len; i++)
12475 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12476 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12479 else if (fmt[i] == 'e')
12480 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12484 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12485 pattern of an insn. X must be a REG. */
12488 reg_bitfield_target_p (x, body)
12494 if (GET_CODE (body) == SET)
12496 rtx dest = SET_DEST (body);
12498 unsigned int regno, tregno, endregno, endtregno;
12500 if (GET_CODE (dest) == ZERO_EXTRACT)
12501 target = XEXP (dest, 0);
12502 else if (GET_CODE (dest) == STRICT_LOW_PART)
12503 target = SUBREG_REG (XEXP (dest, 0));
12507 if (GET_CODE (target) == SUBREG)
12508 target = SUBREG_REG (target);
12510 if (GET_CODE (target) != REG)
12513 tregno = REGNO (target), regno = REGNO (x);
12514 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12515 return target == x;
12517 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12518 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12520 return endregno > tregno && regno < endtregno;
12523 else if (GET_CODE (body) == PARALLEL)
12524 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12525 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12531 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12532 as appropriate. I3 and I2 are the insns resulting from the combination
12533 insns including FROM (I2 may be zero).
12535 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12536 not need REG_DEAD notes because they are being substituted for. This
12537 saves searching in the most common cases.
12539 Each note in the list is either ignored or placed on some insns, depending
12540 on the type of note. */
12543 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12547 rtx elim_i2, elim_i1;
12549 rtx note, next_note;
12552 for (note = notes; note; note = next_note)
12554 rtx place = 0, place2 = 0;
12556 /* If this NOTE references a pseudo register, ensure it references
12557 the latest copy of that register. */
12558 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12559 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12560 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12562 next_note = XEXP (note, 1);
12563 switch (REG_NOTE_KIND (note))
12567 /* Doesn't matter much where we put this, as long as it's somewhere.
12568 It is preferable to keep these notes on branches, which is most
12569 likely to be i3. */
12573 case REG_VTABLE_REF:
12574 /* ??? Should remain with *a particular* memory load. Given the
12575 nature of vtable data, the last insn seems relatively safe. */
12579 case REG_NON_LOCAL_GOTO:
12580 if (GET_CODE (i3) == JUMP_INSN)
12582 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12588 case REG_EH_REGION:
12589 /* These notes must remain with the call or trapping instruction. */
12590 if (GET_CODE (i3) == CALL_INSN)
12592 else if (i2 && GET_CODE (i2) == CALL_INSN)
12594 else if (flag_non_call_exceptions)
12596 if (may_trap_p (i3))
12598 else if (i2 && may_trap_p (i2))
12600 /* ??? Otherwise assume we've combined things such that we
12601 can now prove that the instructions can't trap. Drop the
12602 note in this case. */
12608 case REG_ALWAYS_RETURN:
12611 /* These notes must remain with the call. It should not be
12612 possible for both I2 and I3 to be a call. */
12613 if (GET_CODE (i3) == CALL_INSN)
12615 else if (i2 && GET_CODE (i2) == CALL_INSN)
12622 /* Any clobbers for i3 may still exist, and so we must process
12623 REG_UNUSED notes from that insn.
12625 Any clobbers from i2 or i1 can only exist if they were added by
12626 recog_for_combine. In that case, recog_for_combine created the
12627 necessary REG_UNUSED notes. Trying to keep any original
12628 REG_UNUSED notes from these insns can cause incorrect output
12629 if it is for the same register as the original i3 dest.
12630 In that case, we will notice that the register is set in i3,
12631 and then add a REG_UNUSED note for the destination of i3, which
12632 is wrong. However, it is possible to have REG_UNUSED notes from
12633 i2 or i1 for register which were both used and clobbered, so
12634 we keep notes from i2 or i1 if they will turn into REG_DEAD
12637 /* If this register is set or clobbered in I3, put the note there
12638 unless there is one already. */
12639 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12641 if (from_insn != i3)
12644 if (! (GET_CODE (XEXP (note, 0)) == REG
12645 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12646 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12649 /* Otherwise, if this register is used by I3, then this register
12650 now dies here, so we must put a REG_DEAD note here unless there
12652 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12653 && ! (GET_CODE (XEXP (note, 0)) == REG
12654 ? find_regno_note (i3, REG_DEAD,
12655 REGNO (XEXP (note, 0)))
12656 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12658 PUT_REG_NOTE_KIND (note, REG_DEAD);
12666 /* These notes say something about results of an insn. We can
12667 only support them if they used to be on I3 in which case they
12668 remain on I3. Otherwise they are ignored.
12670 If the note refers to an expression that is not a constant, we
12671 must also ignore the note since we cannot tell whether the
12672 equivalence is still true. It might be possible to do
12673 slightly better than this (we only have a problem if I2DEST
12674 or I1DEST is present in the expression), but it doesn't
12675 seem worth the trouble. */
12677 if (from_insn == i3
12678 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12683 case REG_NO_CONFLICT:
12684 /* These notes say something about how a register is used. They must
12685 be present on any use of the register in I2 or I3. */
12686 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12689 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12699 /* This can show up in several ways -- either directly in the
12700 pattern, or hidden off in the constant pool with (or without?)
12701 a REG_EQUAL note. */
12702 /* ??? Ignore the without-reg_equal-note problem for now. */
12703 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12704 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12705 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12706 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12710 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12711 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12712 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12713 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12721 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12722 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12723 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12725 if (JUMP_LABEL (place) != XEXP (note, 0))
12727 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12728 LABEL_NUSES (JUMP_LABEL (place))--;
12731 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12733 if (JUMP_LABEL (place2) != XEXP (note, 0))
12735 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12736 LABEL_NUSES (JUMP_LABEL (place2))--;
12743 /* These notes say something about the value of a register prior
12744 to the execution of an insn. It is too much trouble to see
12745 if the note is still correct in all situations. It is better
12746 to simply delete it. */
12750 /* If the insn previously containing this note still exists,
12751 put it back where it was. Otherwise move it to the previous
12752 insn. Adjust the corresponding REG_LIBCALL note. */
12753 if (GET_CODE (from_insn) != NOTE)
12757 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12758 place = prev_real_insn (from_insn);
12760 XEXP (tem, 0) = place;
12761 /* If we're deleting the last remaining instruction of a
12762 libcall sequence, don't add the notes. */
12763 else if (XEXP (note, 0) == from_insn)
12769 /* This is handled similarly to REG_RETVAL. */
12770 if (GET_CODE (from_insn) != NOTE)
12774 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12775 place = next_real_insn (from_insn);
12777 XEXP (tem, 0) = place;
12778 /* If we're deleting the last remaining instruction of a
12779 libcall sequence, don't add the notes. */
12780 else if (XEXP (note, 0) == from_insn)
12786 /* If the register is used as an input in I3, it dies there.
12787 Similarly for I2, if it is nonzero and adjacent to I3.
12789 If the register is not used as an input in either I3 or I2
12790 and it is not one of the registers we were supposed to eliminate,
12791 there are two possibilities. We might have a non-adjacent I2
12792 or we might have somehow eliminated an additional register
12793 from a computation. For example, we might have had A & B where
12794 we discover that B will always be zero. In this case we will
12795 eliminate the reference to A.
12797 In both cases, we must search to see if we can find a previous
12798 use of A and put the death note there. */
12801 && GET_CODE (from_insn) == CALL_INSN
12802 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12804 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12806 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12807 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12810 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12811 || rtx_equal_p (XEXP (note, 0), elim_i1))
12816 basic_block bb = this_basic_block;
12818 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12820 if (! INSN_P (tem))
12822 if (tem == bb->head)
12827 /* If the register is being set at TEM, see if that is all
12828 TEM is doing. If so, delete TEM. Otherwise, make this
12829 into a REG_UNUSED note instead. */
12830 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12832 rtx set = single_set (tem);
12833 rtx inner_dest = 0;
12835 rtx cc0_setter = NULL_RTX;
12839 for (inner_dest = SET_DEST (set);
12840 (GET_CODE (inner_dest) == STRICT_LOW_PART
12841 || GET_CODE (inner_dest) == SUBREG
12842 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12843 inner_dest = XEXP (inner_dest, 0))
12846 /* Verify that it was the set, and not a clobber that
12847 modified the register.
12849 CC0 targets must be careful to maintain setter/user
12850 pairs. If we cannot delete the setter due to side
12851 effects, mark the user with an UNUSED note instead
12854 if (set != 0 && ! side_effects_p (SET_SRC (set))
12855 && rtx_equal_p (XEXP (note, 0), inner_dest)
12857 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12858 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12859 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12863 /* Move the notes and links of TEM elsewhere.
12864 This might delete other dead insns recursively.
12865 First set the pattern to something that won't use
12868 PATTERN (tem) = pc_rtx;
12870 distribute_notes (REG_NOTES (tem), tem, tem,
12871 NULL_RTX, NULL_RTX, NULL_RTX);
12872 distribute_links (LOG_LINKS (tem));
12874 PUT_CODE (tem, NOTE);
12875 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12876 NOTE_SOURCE_FILE (tem) = 0;
12879 /* Delete the setter too. */
12882 PATTERN (cc0_setter) = pc_rtx;
12884 distribute_notes (REG_NOTES (cc0_setter),
12885 cc0_setter, cc0_setter,
12886 NULL_RTX, NULL_RTX, NULL_RTX);
12887 distribute_links (LOG_LINKS (cc0_setter));
12889 PUT_CODE (cc0_setter, NOTE);
12890 NOTE_LINE_NUMBER (cc0_setter)
12891 = NOTE_INSN_DELETED;
12892 NOTE_SOURCE_FILE (cc0_setter) = 0;
12896 /* If the register is both set and used here, put the
12897 REG_DEAD note here, but place a REG_UNUSED note
12898 here too unless there already is one. */
12899 else if (reg_referenced_p (XEXP (note, 0),
12904 if (! find_regno_note (tem, REG_UNUSED,
12905 REGNO (XEXP (note, 0))))
12907 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12912 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12914 /* If there isn't already a REG_UNUSED note, put one
12916 if (! find_regno_note (tem, REG_UNUSED,
12917 REGNO (XEXP (note, 0))))
12922 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12923 || (GET_CODE (tem) == CALL_INSN
12924 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12928 /* If we are doing a 3->2 combination, and we have a
12929 register which formerly died in i3 and was not used
12930 by i2, which now no longer dies in i3 and is used in
12931 i2 but does not die in i2, and place is between i2
12932 and i3, then we may need to move a link from place to
12934 if (i2 && INSN_UID (place) <= max_uid_cuid
12935 && INSN_CUID (place) > INSN_CUID (i2)
12937 && INSN_CUID (from_insn) > INSN_CUID (i2)
12938 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12940 rtx links = LOG_LINKS (place);
12941 LOG_LINKS (place) = 0;
12942 distribute_links (links);
12947 if (tem == bb->head)
12951 /* We haven't found an insn for the death note and it
12952 is still a REG_DEAD note, but we have hit the beginning
12953 of the block. If the existing life info says the reg
12954 was dead, there's nothing left to do. Otherwise, we'll
12955 need to do a global life update after combine. */
12956 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12957 && REGNO_REG_SET_P (bb->global_live_at_start,
12958 REGNO (XEXP (note, 0))))
12960 SET_BIT (refresh_blocks, this_basic_block->index);
12965 /* If the register is set or already dead at PLACE, we needn't do
12966 anything with this note if it is still a REG_DEAD note.
12967 We can here if it is set at all, not if is it totally replace,
12968 which is what `dead_or_set_p' checks, so also check for it being
12971 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12973 unsigned int regno = REGNO (XEXP (note, 0));
12975 /* Similarly, if the instruction on which we want to place
12976 the note is a noop, we'll need do a global live update
12977 after we remove them in delete_noop_moves. */
12978 if (noop_move_p (place))
12980 SET_BIT (refresh_blocks, this_basic_block->index);
12984 if (dead_or_set_p (place, XEXP (note, 0))
12985 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12987 /* Unless the register previously died in PLACE, clear
12988 reg_last_death. [I no longer understand why this is
12990 if (reg_last_death[regno] != place)
12991 reg_last_death[regno] = 0;
12995 reg_last_death[regno] = place;
12997 /* If this is a death note for a hard reg that is occupying
12998 multiple registers, ensure that we are still using all
12999 parts of the object. If we find a piece of the object
13000 that is unused, we must arrange for an appropriate REG_DEAD
13001 note to be added for it. However, we can't just emit a USE
13002 and tag the note to it, since the register might actually
13003 be dead; so we recourse, and the recursive call then finds
13004 the previous insn that used this register. */
13006 if (place && regno < FIRST_PSEUDO_REGISTER
13007 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
13009 unsigned int endregno
13010 = regno + HARD_REGNO_NREGS (regno,
13011 GET_MODE (XEXP (note, 0)));
13015 for (i = regno; i < endregno; i++)
13016 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13017 && ! find_regno_fusage (place, USE, i))
13018 || dead_or_set_regno_p (place, i))
13023 /* Put only REG_DEAD notes for pieces that are
13024 not already dead or set. */
13026 for (i = regno; i < endregno;
13027 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
13029 rtx piece = regno_reg_rtx[i];
13030 basic_block bb = this_basic_block;
13032 if (! dead_or_set_p (place, piece)
13033 && ! reg_bitfield_target_p (piece,
13037 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
13039 distribute_notes (new_note, place, place,
13040 NULL_RTX, NULL_RTX, NULL_RTX);
13042 else if (! refers_to_regno_p (i, i + 1,
13043 PATTERN (place), 0)
13044 && ! find_regno_fusage (place, USE, i))
13045 for (tem = PREV_INSN (place); ;
13046 tem = PREV_INSN (tem))
13048 if (! INSN_P (tem))
13050 if (tem == bb->head)
13052 SET_BIT (refresh_blocks,
13053 this_basic_block->index);
13059 if (dead_or_set_p (tem, piece)
13060 || reg_bitfield_target_p (piece,
13064 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
13079 /* Any other notes should not be present at this point in the
13086 XEXP (note, 1) = REG_NOTES (place);
13087 REG_NOTES (place) = note;
13089 else if ((REG_NOTE_KIND (note) == REG_DEAD
13090 || REG_NOTE_KIND (note) == REG_UNUSED)
13091 && GET_CODE (XEXP (note, 0)) == REG)
13092 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
13096 if ((REG_NOTE_KIND (note) == REG_DEAD
13097 || REG_NOTE_KIND (note) == REG_UNUSED)
13098 && GET_CODE (XEXP (note, 0)) == REG)
13099 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
13101 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
13102 REG_NOTE_KIND (note),
13104 REG_NOTES (place2));
13109 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13110 I3, I2, and I1 to new locations. This is also called to add a link
13111 pointing at I3 when I3's destination is changed. */
13114 distribute_links (links)
13117 rtx link, next_link;
13119 for (link = links; link; link = next_link)
13125 next_link = XEXP (link, 1);
13127 /* If the insn that this link points to is a NOTE or isn't a single
13128 set, ignore it. In the latter case, it isn't clear what we
13129 can do other than ignore the link, since we can't tell which
13130 register it was for. Such links wouldn't be used by combine
13133 It is not possible for the destination of the target of the link to
13134 have been changed by combine. The only potential of this is if we
13135 replace I3, I2, and I1 by I3 and I2. But in that case the
13136 destination of I2 also remains unchanged. */
13138 if (GET_CODE (XEXP (link, 0)) == NOTE
13139 || (set = single_set (XEXP (link, 0))) == 0)
13142 reg = SET_DEST (set);
13143 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13144 || GET_CODE (reg) == SIGN_EXTRACT
13145 || GET_CODE (reg) == STRICT_LOW_PART)
13146 reg = XEXP (reg, 0);
13148 /* A LOG_LINK is defined as being placed on the first insn that uses
13149 a register and points to the insn that sets the register. Start
13150 searching at the next insn after the target of the link and stop
13151 when we reach a set of the register or the end of the basic block.
13153 Note that this correctly handles the link that used to point from
13154 I3 to I2. Also note that not much searching is typically done here
13155 since most links don't point very far away. */
13157 for (insn = NEXT_INSN (XEXP (link, 0));
13158 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13159 || this_basic_block->next_bb->head != insn));
13160 insn = NEXT_INSN (insn))
13161 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13163 if (reg_referenced_p (reg, PATTERN (insn)))
13167 else if (GET_CODE (insn) == CALL_INSN
13168 && find_reg_fusage (insn, USE, reg))
13174 /* If we found a place to put the link, place it there unless there
13175 is already a link to the same insn as LINK at that point. */
13181 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13182 if (XEXP (link2, 0) == XEXP (link, 0))
13187 XEXP (link, 1) = LOG_LINKS (place);
13188 LOG_LINKS (place) = link;
13190 /* Set added_links_insn to the earliest insn we added a
13192 if (added_links_insn == 0
13193 || INSN_CUID (added_links_insn) > INSN_CUID (place))
13194 added_links_insn = place;
13200 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13206 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
13207 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
13208 insn = NEXT_INSN (insn);
13210 if (INSN_UID (insn) > max_uid_cuid)
13213 return INSN_CUID (insn);
13217 dump_combine_stats (file)
13222 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13223 combine_attempts, combine_merges, combine_extras, combine_successes);
13227 dump_combine_total_stats (file)
13232 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13233 total_attempts, total_merges, total_extras, total_successes);