1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static void arm_add_gc_roots (void);
63 static int arm_gen_constant (enum rtx_code, enum machine_mode, HOST_WIDE_INT,
65 static unsigned bit_count (unsigned long);
66 static int arm_address_register_rtx_p (rtx, int);
67 static int arm_legitimate_index_p (enum machine_mode, rtx, int);
68 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
69 inline static int thumb_index_register_rtx_p (rtx, int);
70 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
71 static rtx emit_multi_reg_push (int);
72 static rtx emit_sfm (int, int);
74 static bool arm_assemble_integer (rtx, unsigned int, int);
76 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
77 static arm_cc get_arm_condition_code (rtx);
78 static void init_fpa_table (void);
79 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
80 static rtx is_jump_table (rtx);
81 static const char *output_multi_immediate (rtx *, const char *, const char *,
83 static void print_multi_reg (FILE *, const char *, int, int);
84 static const char *shift_op (rtx, HOST_WIDE_INT *);
85 static struct machine_function *arm_init_machine_status (void);
86 static int number_of_first_bit_set (int);
87 static void replace_symbols_in_block (tree, rtx, rtx);
88 static void thumb_exit (FILE *, int, rtx);
89 static void thumb_pushpop (FILE *, int, int, int *, int);
90 static rtx is_jump_table (rtx);
91 static HOST_WIDE_INT get_jump_table_size (rtx);
92 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
93 static Mnode *add_minipool_forward_ref (Mfix *);
94 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
95 static Mnode *add_minipool_backward_ref (Mfix *);
96 static void assign_minipool_offsets (Mfix *);
97 static void arm_print_value (FILE *, rtx);
98 static void dump_minipool (rtx);
99 static int arm_barrier_cost (rtx);
100 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
101 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
102 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
104 static void arm_reorg (void);
105 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
106 static int current_file_function_operand (rtx);
107 static unsigned long arm_compute_save_reg0_reg12_mask (void);
108 static unsigned long arm_compute_save_reg_mask (void);
109 static unsigned long arm_isr_value (tree);
110 static unsigned long arm_compute_func_type (void);
111 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
112 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
113 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
114 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
116 static int arm_comp_type_attributes (tree, tree);
117 static void arm_set_default_type_attributes (tree);
118 static int arm_adjust_cost (rtx, rtx, rtx, int);
119 static int arm_use_dfa_pipeline_interface (void);
120 static int count_insns_for_constant (HOST_WIDE_INT, int);
121 static int arm_get_strip_length (int);
122 static bool arm_function_ok_for_sibcall (tree, tree);
123 static void arm_internal_label (FILE *, const char *, unsigned long);
124 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
126 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
127 static bool arm_rtx_costs (rtx, int, int, int *);
128 static int arm_address_cost (rtx);
129 static bool arm_memory_load_p (rtx);
130 static bool arm_cirrus_insn_p (rtx);
131 static void cirrus_reorg (rtx);
132 static void arm_init_builtins (void);
133 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
134 static void arm_init_iwmmxt_builtins (void);
135 static rtx safe_vector_operand (rtx, enum machine_mode);
136 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
137 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
138 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
140 #ifdef OBJECT_FORMAT_ELF
141 static void arm_elf_asm_named_section (const char *, unsigned int);
144 static void arm_encode_section_info (tree, rtx, int);
147 static void aof_globalize_label (FILE *, const char *);
148 static void aof_dump_imports (FILE *);
149 static void aof_dump_pic_table (FILE *);
150 static void aof_file_start (void);
151 static void aof_file_end (void);
155 /* Initialize the GCC target structure. */
156 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
157 #undef TARGET_MERGE_DECL_ATTRIBUTES
158 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
161 #undef TARGET_ATTRIBUTE_TABLE
162 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
165 #undef TARGET_ASM_BYTE_OP
166 #define TARGET_ASM_BYTE_OP "\tDCB\t"
167 #undef TARGET_ASM_ALIGNED_HI_OP
168 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
169 #undef TARGET_ASM_ALIGNED_SI_OP
170 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
171 #undef TARGET_ASM_GLOBALIZE_LABEL
172 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
173 #undef TARGET_ASM_FILE_START
174 #define TARGET_ASM_FILE_START aof_file_start
175 #undef TARGET_ASM_FILE_END
176 #define TARGET_ASM_FILE_END aof_file_end
178 #undef TARGET_ASM_ALIGNED_SI_OP
179 #define TARGET_ASM_ALIGNED_SI_OP NULL
180 #undef TARGET_ASM_INTEGER
181 #define TARGET_ASM_INTEGER arm_assemble_integer
184 #undef TARGET_ASM_FUNCTION_PROLOGUE
185 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
187 #undef TARGET_ASM_FUNCTION_EPILOGUE
188 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
190 #undef TARGET_COMP_TYPE_ATTRIBUTES
191 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
193 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
194 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
196 #undef TARGET_SCHED_ADJUST_COST
197 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
199 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
200 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
202 #undef TARGET_ENCODE_SECTION_INFO
204 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
206 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
209 #undef TARGET_STRIP_NAME_ENCODING
210 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
212 #undef TARGET_ASM_INTERNAL_LABEL
213 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
215 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
216 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
218 #undef TARGET_ASM_OUTPUT_MI_THUNK
219 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
220 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
221 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
223 #undef TARGET_RTX_COSTS
224 #define TARGET_RTX_COSTS arm_rtx_costs
225 #undef TARGET_ADDRESS_COST
226 #define TARGET_ADDRESS_COST arm_address_cost
228 #undef TARGET_MACHINE_DEPENDENT_REORG
229 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
231 #undef TARGET_INIT_BUILTINS
232 #define TARGET_INIT_BUILTINS arm_init_builtins
233 #undef TARGET_EXPAND_BUILTIN
234 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
236 struct gcc_target targetm = TARGET_INITIALIZER;
238 /* Obstack for minipool constant handling. */
239 static struct obstack minipool_obstack;
240 static char * minipool_startobj;
242 /* The maximum number of insns skipped which
243 will be conditionalised if possible. */
244 static int max_insns_skipped = 5;
246 extern FILE * asm_out_file;
248 /* True if we are currently building a constant table. */
249 int making_const_table;
251 /* Define the information needed to generate branch insns. This is
252 stored from the compare operation. */
253 rtx arm_compare_op0, arm_compare_op1;
255 /* What type of floating point are we tuning for? */
256 enum fputype arm_fpu_tune;
258 /* What type of floating point instructions are available? */
259 enum fputype arm_fpu_arch;
261 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
262 enum prog_mode_type arm_prgmode;
264 /* Set by the -mfp=... option. */
265 const char * target_fp_name = NULL;
267 /* Used to parse -mstructure_size_boundary command line option. */
268 const char * structure_size_string = NULL;
269 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
271 /* Bit values used to identify processor capabilities. */
272 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
273 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
274 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
275 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
276 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
277 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
278 #define FL_THUMB (1 << 6) /* Thumb aware */
279 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
280 #define FL_STRONG (1 << 8) /* StrongARM */
281 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
282 #define FL_XSCALE (1 << 10) /* XScale */
283 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
284 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
285 #define FL_ARCH6J (1 << 12) /* Architecture rel 6. Adds
286 media instructions. */
287 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
289 /* The bits in this mask specify which
290 instructions we are allowed to generate. */
291 static unsigned long insn_flags = 0;
293 /* The bits in this mask specify which instruction scheduling options should
294 be used. Note - there is an overlap with the FL_FAST_MULT. For some
295 hardware we want to be able to generate the multiply instructions, but to
296 tune as if they were not present in the architecture. */
297 static unsigned long tune_flags = 0;
299 /* The following are used in the arm.md file as equivalents to bits
300 in the above two flag variables. */
302 /* Nonzero if this is an "M" variant of the processor. */
303 int arm_fast_multiply = 0;
305 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
308 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
311 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
314 /* Nonzero if this chip can benefit from load scheduling. */
315 int arm_ld_sched = 0;
317 /* Nonzero if this chip is a StrongARM. */
318 int arm_is_strong = 0;
320 /* Nonzero if this chip supports Intel Wireless MMX technology. */
321 int arm_arch_iwmmxt = 0;
323 /* Nonzero if this chip is an XScale. */
324 int arm_arch_xscale = 0;
326 /* Nonzero if tuning for XScale */
327 int arm_tune_xscale = 0;
329 /* Nonzero if this chip is an ARM6 or an ARM7. */
330 int arm_is_6_or_7 = 0;
332 /* Nonzero if this chip is a Cirrus/DSP. */
333 int arm_is_cirrus = 0;
335 /* Nonzero if generating Thumb instructions. */
338 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
339 must report the mode of the memory reference from PRINT_OPERAND to
340 PRINT_OPERAND_ADDRESS. */
341 enum machine_mode output_memory_reference_mode;
343 /* The register number to be used for the PIC offset register. */
344 const char * arm_pic_register_string = NULL;
345 int arm_pic_register = INVALID_REGNUM;
347 /* Set to 1 when a return insn is output, this means that the epilogue
349 int return_used_this_function;
351 /* Set to 1 after arm_reorg has started. Reset to start at the start of
352 the next function. */
353 static int after_arm_reorg = 0;
355 /* The maximum number of insns to be used when loading a constant. */
356 static int arm_constant_limit = 3;
358 /* For an explanation of these variables, see final_prescan_insn below. */
360 enum arm_cond_code arm_current_cc;
362 int arm_target_label;
364 /* The condition codes of the ARM, and the inverse function. */
365 static const char * const arm_condition_codes[] =
367 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
368 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
371 #define streq(string1, string2) (strcmp (string1, string2) == 0)
373 /* Initialization code. */
377 const char *const name;
378 const unsigned long flags;
381 /* Not all of these give usefully different compilation alternatives,
382 but there is no simple way of generalizing them. */
383 static const struct processors all_cores[] =
387 {"arm2", FL_CO_PROC | FL_MODE26 },
388 {"arm250", FL_CO_PROC | FL_MODE26 },
389 {"arm3", FL_CO_PROC | FL_MODE26 },
390 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
391 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
392 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
393 {"arm610", FL_MODE26 | FL_MODE32 },
394 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
395 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
396 /* arm7m doesn't exist on its own, but only with D, (and I), but
397 those don't alter the code, so arm7m is sometimes used. */
398 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
399 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
400 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
401 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
402 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
403 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
404 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
405 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
406 {"arm710", FL_MODE26 | FL_MODE32 },
407 {"arm720", FL_MODE26 | FL_MODE32 },
408 {"arm710c", FL_MODE26 | FL_MODE32 },
409 {"arm7100", FL_MODE26 | FL_MODE32 },
410 {"arm7500", FL_MODE26 | FL_MODE32 },
411 /* Doesn't have an external co-proc, but does have embedded fpa. */
412 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
413 /* V4 Architecture Processors */
414 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
415 {"arm710t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
416 {"arm720t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
417 {"arm740t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
418 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
419 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
420 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
421 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
422 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
423 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
424 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
425 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
426 {"ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
427 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
428 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
429 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
430 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
431 /* V5 Architecture Processors */
432 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
433 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
434 {"arm926ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
435 {"arm1026ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
436 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
437 {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
438 /* V6 Architecture Processors */
439 {"arm1136js", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J },
440 {"arm1136jfs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J | FL_VFPV2 },
444 static const struct processors all_architectures[] =
446 /* ARM Architectures */
448 { "armv2", FL_CO_PROC | FL_MODE26 },
449 { "armv2a", FL_CO_PROC | FL_MODE26 },
450 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
451 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
452 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
453 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
454 implementations that support it, so we will leave it out for now. */
455 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
456 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
457 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
458 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
459 { "armv6j", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J },
460 { "ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
461 {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
465 /* This is a magic structure. The 'string' field is magically filled in
466 with a pointer to the value specified by the user on the command line
467 assuming that the user has specified such a value. */
469 struct arm_cpu_select arm_select[] =
471 /* string name processors */
472 { NULL, "-mcpu=", all_cores },
473 { NULL, "-march=", all_architectures },
474 { NULL, "-mtune=", all_cores }
477 /* Return the number of bits set in VALUE. */
479 bit_count (unsigned long value)
481 unsigned long count = 0;
486 value &= value - 1; /* Clear the least-significant set bit. */
492 /* Fix up any incompatible options that the user has specified.
493 This has now turned into a maze. */
495 arm_override_options (void)
499 /* Set up the flags based on the cpu/architecture selected by the user. */
500 for (i = ARRAY_SIZE (arm_select); i--;)
502 struct arm_cpu_select * ptr = arm_select + i;
504 if (ptr->string != NULL && ptr->string[0] != '\0')
506 const struct processors * sel;
508 for (sel = ptr->processors; sel->name != NULL; sel++)
509 if (streq (ptr->string, sel->name))
512 tune_flags = sel->flags;
515 /* If we have been given an architecture and a processor
516 make sure that they are compatible. We only generate
517 a warning though, and we prefer the CPU over the
519 if (insn_flags != 0 && (insn_flags ^ sel->flags))
520 warning ("switch -mcpu=%s conflicts with -march= switch",
523 insn_flags = sel->flags;
529 if (sel->name == NULL)
530 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
534 /* If the user did not specify a processor, choose one for them. */
537 const struct processors * sel;
539 static const struct cpu_default
542 const char *const name;
546 { TARGET_CPU_arm2, "arm2" },
547 { TARGET_CPU_arm6, "arm6" },
548 { TARGET_CPU_arm610, "arm610" },
549 { TARGET_CPU_arm710, "arm710" },
550 { TARGET_CPU_arm7m, "arm7m" },
551 { TARGET_CPU_arm7500fe, "arm7500fe" },
552 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
553 { TARGET_CPU_arm8, "arm8" },
554 { TARGET_CPU_arm810, "arm810" },
555 { TARGET_CPU_arm9, "arm9" },
556 { TARGET_CPU_strongarm, "strongarm" },
557 { TARGET_CPU_xscale, "xscale" },
558 { TARGET_CPU_ep9312, "ep9312" },
559 { TARGET_CPU_iwmmxt, "iwmmxt" },
560 { TARGET_CPU_arm926ej_s, "arm926ej-s" },
561 { TARGET_CPU_arm1026ej_s, "arm1026ej-s" },
562 { TARGET_CPU_arm1136j_s, "arm1136j_s" },
563 { TARGET_CPU_arm1136jf_s, "arm1136jf_s" },
564 { TARGET_CPU_generic, "arm" },
567 const struct cpu_default * def;
569 /* Find the default. */
570 for (def = cpu_defaults; def->name; def++)
571 if (def->cpu == TARGET_CPU_DEFAULT)
574 /* Make sure we found the default CPU. */
575 if (def->name == NULL)
578 /* Find the default CPU's flags. */
579 for (sel = all_cores; sel->name != NULL; sel++)
580 if (streq (def->name, sel->name))
583 if (sel->name == NULL)
586 insn_flags = sel->flags;
588 /* Now check to see if the user has specified some command line
589 switch that require certain abilities from the cpu. */
592 if (TARGET_INTERWORK || TARGET_THUMB)
594 sought |= (FL_THUMB | FL_MODE32);
596 /* Force apcs-32 to be used for interworking. */
597 target_flags |= ARM_FLAG_APCS_32;
599 /* There are no ARM processors that support both APCS-26 and
600 interworking. Therefore we force FL_MODE26 to be removed
601 from insn_flags here (if it was set), so that the search
602 below will always be able to find a compatible processor. */
603 insn_flags &= ~FL_MODE26;
605 else if (!TARGET_APCS_32)
608 if (sought != 0 && ((sought & insn_flags) != sought))
610 /* Try to locate a CPU type that supports all of the abilities
611 of the default CPU, plus the extra abilities requested by
613 for (sel = all_cores; sel->name != NULL; sel++)
614 if ((sel->flags & sought) == (sought | insn_flags))
617 if (sel->name == NULL)
619 unsigned current_bit_count = 0;
620 const struct processors * best_fit = NULL;
622 /* Ideally we would like to issue an error message here
623 saying that it was not possible to find a CPU compatible
624 with the default CPU, but which also supports the command
625 line options specified by the programmer, and so they
626 ought to use the -mcpu=<name> command line option to
627 override the default CPU type.
629 Unfortunately this does not work with multilibing. We
630 need to be able to support multilibs for -mapcs-26 and for
631 -mthumb-interwork and there is no CPU that can support both
632 options. Instead if we cannot find a cpu that has both the
633 characteristics of the default cpu and the given command line
634 options we scan the array again looking for a best match. */
635 for (sel = all_cores; sel->name != NULL; sel++)
636 if ((sel->flags & sought) == sought)
640 count = bit_count (sel->flags & insn_flags);
642 if (count >= current_bit_count)
645 current_bit_count = count;
649 if (best_fit == NULL)
655 insn_flags = sel->flags;
659 /* If tuning has not been specified, tune for whichever processor or
660 architecture has been selected. */
662 tune_flags = insn_flags;
664 /* Make sure that the processor choice does not conflict with any of the
665 other command line choices. */
666 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
668 /* If APCS-32 was not the default then it must have been set by the
669 user, so issue a warning message. If the user has specified
670 "-mapcs-32 -mcpu=arm2" then we loose here. */
671 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
672 warning ("target CPU does not support APCS-32" );
673 target_flags &= ~ARM_FLAG_APCS_32;
675 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
677 warning ("target CPU does not support APCS-26" );
678 target_flags |= ARM_FLAG_APCS_32;
681 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
683 warning ("target CPU does not support interworking" );
684 target_flags &= ~ARM_FLAG_INTERWORK;
687 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
689 warning ("target CPU does not support THUMB instructions");
690 target_flags &= ~ARM_FLAG_THUMB;
694 inform ("future releases of GCC will not support -mapcs-26");
696 if (TARGET_APCS_FRAME && TARGET_THUMB)
698 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
699 target_flags &= ~ARM_FLAG_APCS_FRAME;
702 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
703 from here where no function is being compiled currently. */
704 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
706 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
708 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
709 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
711 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
712 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
714 /* If interworking is enabled then APCS-32 must be selected as well. */
715 if (TARGET_INTERWORK)
718 warning ("interworking forces APCS-32 to be used" );
719 target_flags |= ARM_FLAG_APCS_32;
722 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
724 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
725 target_flags |= ARM_FLAG_APCS_FRAME;
728 if (TARGET_POKE_FUNCTION_NAME)
729 target_flags |= ARM_FLAG_APCS_FRAME;
731 if (TARGET_APCS_REENT && flag_pic)
732 error ("-fpic and -mapcs-reent are incompatible");
734 if (TARGET_APCS_REENT)
735 warning ("APCS reentrant code not supported. Ignored");
737 /* If this target is normally configured to use APCS frames, warn if they
738 are turned off and debugging is turned on. */
740 && write_symbols != NO_DEBUG
741 && !TARGET_APCS_FRAME
742 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
743 warning ("-g with -mno-apcs-frame may not give sensible debugging");
745 /* If stack checking is disabled, we can use r10 as the PIC register,
746 which keeps r9 available. */
748 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
750 if (TARGET_APCS_FLOAT)
751 warning ("passing floating point arguments in fp regs not yet supported");
753 /* Initialize boolean versions of the flags, for use in the arm.md file. */
754 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
755 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
756 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
757 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
758 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
760 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
761 arm_is_strong = (tune_flags & FL_STRONG) != 0;
762 thumb_code = (TARGET_ARM == 0);
763 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
764 && !(tune_flags & FL_ARCH4))) != 0;
765 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
766 arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0;
767 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
769 if (TARGET_IWMMXT && (! TARGET_ATPCS))
770 target_flags |= ARM_FLAG_ATPCS;
774 arm_fpu_tune = FPUTYPE_MAVERICK;
776 /* Ignore -mhard-float if -mcpu=ep9312. */
777 if (TARGET_HARD_FLOAT)
778 target_flags ^= ARM_FLAG_SOFT_FLOAT;
781 /* Default value for floating point code... if no co-processor
782 bus, then schedule for emulated floating point. Otherwise,
783 assume the user has an FPA.
784 Note: this does not prevent use of floating point instructions,
785 -msoft-float does that. */
786 arm_fpu_tune = (tune_flags & FL_CO_PROC) ? FPUTYPE_FPA : FPUTYPE_FPA_EMU3;
790 if (streq (target_fp_name, "2"))
791 arm_fpu_arch = FPUTYPE_FPA_EMU2;
792 else if (streq (target_fp_name, "3"))
793 arm_fpu_arch = FPUTYPE_FPA_EMU3;
795 error ("invalid floating point emulation option: -mfpe-%s",
799 arm_fpu_arch = FPUTYPE_DEFAULT;
803 if (arm_fpu_tune == FPUTYPE_FPA_EMU3)
804 arm_fpu_tune = FPUTYPE_FPA_EMU2;
805 else if (arm_fpu_tune == FPUTYPE_MAVERICK)
806 warning ("-mfpe switch not supported by ep9312 target cpu - ignored.");
807 else if (arm_fpu_tune != FPUTYPE_FPA)
808 arm_fpu_tune = FPUTYPE_FPA_EMU2;
811 /* For arm2/3 there is no need to do any scheduling if there is only
812 a floating point emulator, or we are doing software floating-point. */
813 if ((TARGET_SOFT_FLOAT || arm_fpu_tune != FPUTYPE_FPA)
814 && (tune_flags & FL_MODE32) == 0)
815 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
817 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
819 if (structure_size_string != NULL)
821 int size = strtol (structure_size_string, NULL, 0);
823 if (size == 8 || size == 32)
824 arm_structure_size_boundary = size;
826 warning ("structure size boundary can only be set to 8 or 32");
829 if (arm_pic_register_string != NULL)
831 int pic_register = decode_reg_name (arm_pic_register_string);
834 warning ("-mpic-register= is useless without -fpic");
836 /* Prevent the user from choosing an obviously stupid PIC register. */
837 else if (pic_register < 0 || call_used_regs[pic_register]
838 || pic_register == HARD_FRAME_POINTER_REGNUM
839 || pic_register == STACK_POINTER_REGNUM
840 || pic_register >= PC_REGNUM)
841 error ("unable to use '%s' for PIC register", arm_pic_register_string);
843 arm_pic_register = pic_register;
846 if (TARGET_THUMB && flag_schedule_insns)
848 /* Don't warn since it's on by default in -O2. */
849 flag_schedule_insns = 0;
854 /* There's some dispute as to whether this should be 1 or 2. However,
855 experiments seem to show that in pathological cases a setting of
856 1 degrades less severely than a setting of 2. This could change if
857 other parts of the compiler change their behavior. */
858 arm_constant_limit = 1;
860 /* If optimizing for size, bump the number of instructions that we
861 are prepared to conditionally execute (even on a StrongARM). */
862 max_insns_skipped = 6;
866 /* For processors with load scheduling, it never costs more than
867 2 cycles to load a constant, and the load scheduler may well
869 if (tune_flags & FL_LDSCHED)
870 arm_constant_limit = 1;
872 /* On XScale the longer latency of a load makes it more difficult
873 to achieve a good schedule, so it's faster to synthesize
874 constants that can be done in two insns. */
876 arm_constant_limit = 2;
878 /* StrongARM has early execution of branches, so a sequence
879 that is worth skipping is shorter. */
881 max_insns_skipped = 3;
884 /* Register global variables with the garbage collector. */
889 arm_add_gc_roots (void)
891 gcc_obstack_init(&minipool_obstack);
892 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
895 /* A table of known ARM exception types.
896 For use with the interrupt function attribute. */
900 const char *const arg;
901 const unsigned long return_value;
905 static const isr_attribute_arg isr_attribute_args [] =
907 { "IRQ", ARM_FT_ISR },
908 { "irq", ARM_FT_ISR },
909 { "FIQ", ARM_FT_FIQ },
910 { "fiq", ARM_FT_FIQ },
911 { "ABORT", ARM_FT_ISR },
912 { "abort", ARM_FT_ISR },
913 { "ABORT", ARM_FT_ISR },
914 { "abort", ARM_FT_ISR },
915 { "UNDEF", ARM_FT_EXCEPTION },
916 { "undef", ARM_FT_EXCEPTION },
917 { "SWI", ARM_FT_EXCEPTION },
918 { "swi", ARM_FT_EXCEPTION },
919 { NULL, ARM_FT_NORMAL }
922 /* Returns the (interrupt) function type of the current
923 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
926 arm_isr_value (tree argument)
928 const isr_attribute_arg * ptr;
931 /* No argument - default to IRQ. */
932 if (argument == NULL_TREE)
935 /* Get the value of the argument. */
936 if (TREE_VALUE (argument) == NULL_TREE
937 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
938 return ARM_FT_UNKNOWN;
940 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
942 /* Check it against the list of known arguments. */
943 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
944 if (streq (arg, ptr->arg))
945 return ptr->return_value;
947 /* An unrecognized interrupt type. */
948 return ARM_FT_UNKNOWN;
951 /* Computes the type of the current function. */
954 arm_compute_func_type (void)
956 unsigned long type = ARM_FT_UNKNOWN;
960 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
963 /* Decide if the current function is volatile. Such functions
964 never return, and many memory cycles can be saved by not storing
965 register values that will never be needed again. This optimization
966 was added to speed up context switching in a kernel application. */
968 && current_function_nothrow
969 && TREE_THIS_VOLATILE (current_function_decl))
970 type |= ARM_FT_VOLATILE;
972 if (current_function_needs_context)
973 type |= ARM_FT_NESTED;
975 attr = DECL_ATTRIBUTES (current_function_decl);
977 a = lookup_attribute ("naked", attr);
979 type |= ARM_FT_NAKED;
981 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
982 type |= ARM_FT_EXCEPTION_HANDLER;
985 a = lookup_attribute ("isr", attr);
987 a = lookup_attribute ("interrupt", attr);
990 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
992 type |= arm_isr_value (TREE_VALUE (a));
998 /* Returns the type of the current function. */
1001 arm_current_func_type (void)
1003 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1004 cfun->machine->func_type = arm_compute_func_type ();
1006 return cfun->machine->func_type;
1009 /* Return 1 if it is possible to return using a single instruction.
1010 If SIBLING is non-null, this is a test for a return before a sibling
1011 call. SIBLING is the call insn, so we can examine its register usage. */
1014 use_return_insn (int iscond, rtx sibling)
1017 unsigned int func_type;
1018 unsigned long saved_int_regs;
1019 unsigned HOST_WIDE_INT stack_adjust;
1021 /* Never use a return instruction before reload has run. */
1022 if (!reload_completed)
1025 func_type = arm_current_func_type ();
1027 /* Naked functions and volatile functions need special
1029 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1032 /* So do interrupt functions that use the frame pointer. */
1033 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1036 stack_adjust = arm_get_frame_size () + current_function_outgoing_args_size;
1038 /* As do variadic functions. */
1039 if (current_function_pretend_args_size
1040 || cfun->machine->uses_anonymous_args
1041 /* Or if the function calls __builtin_eh_return () */
1042 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1043 /* Or if the function calls alloca */
1044 || current_function_calls_alloca
1045 /* Or if there is a stack adjustment. However, if the stack pointer
1046 is saved on the stack, we can use a pre-incrementing stack load. */
1047 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1050 saved_int_regs = arm_compute_save_reg_mask ();
1052 /* Unfortunately, the insn
1054 ldmib sp, {..., sp, ...}
1056 triggers a bug on most SA-110 based devices, such that the stack
1057 pointer won't be correctly restored if the instruction takes a
1058 page fault. We work around this problem by popping r3 along with
1059 the other registers, since that is never slower than executing
1060 another instruction.
1062 We test for !arm_arch5 here, because code for any architecture
1063 less than this could potentially be run on one of the buggy
1065 if (stack_adjust == 4 && !arm_arch5)
1067 /* Validate that r3 is a call-clobbered register (always true in
1068 the default abi) ... */
1069 if (!call_used_regs[3])
1072 /* ... that it isn't being used for a return value (always true
1073 until we implement return-in-regs), or for a tail-call
1077 if (GET_CODE (sibling) != CALL_INSN)
1080 if (find_regno_fusage (sibling, USE, 3))
1084 /* ... and that there are no call-saved registers in r0-r2
1085 (always true in the default ABI). */
1086 if (saved_int_regs & 0x7)
1090 /* Can't be done if interworking with Thumb, and any registers have been
1092 if (TARGET_INTERWORK && saved_int_regs != 0)
1095 /* On StrongARM, conditional returns are expensive if they aren't
1096 taken and multiple registers have been stacked. */
1097 if (iscond && arm_is_strong)
1099 /* Conditional return when just the LR is stored is a simple
1100 conditional-load instruction, that's not expensive. */
1101 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1104 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1108 /* If there are saved registers but the LR isn't saved, then we need
1109 two instructions for the return. */
1110 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1113 /* Can't be done if any of the FPA regs are pushed,
1114 since this also requires an insn. */
1115 if (TARGET_HARD_FLOAT)
1116 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
1117 if (regs_ever_live[regno] && !call_used_regs[regno])
1120 if (TARGET_REALLY_IWMMXT)
1121 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1122 if (regs_ever_live[regno] && ! call_used_regs [regno])
1128 /* Return TRUE if int I is a valid immediate ARM constant. */
1131 const_ok_for_arm (HOST_WIDE_INT i)
1133 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1135 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1136 be all zero, or all one. */
1137 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1138 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1139 != ((~(unsigned HOST_WIDE_INT) 0)
1140 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1143 /* Fast return for 0 and powers of 2 */
1144 if ((i & (i - 1)) == 0)
1149 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1152 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1153 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1155 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1160 /* Return true if I is a valid constant for the operation CODE. */
1162 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1164 if (const_ok_for_arm (i))
1170 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1172 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1178 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1185 /* Emit a sequence of insns to handle a large constant.
1186 CODE is the code of the operation required, it can be any of SET, PLUS,
1187 IOR, AND, XOR, MINUS;
1188 MODE is the mode in which the operation is being performed;
1189 VAL is the integer to operate on;
1190 SOURCE is the other operand (a register, or a null-pointer for SET);
1191 SUBTARGETS means it is safe to create scratch registers if that will
1192 either produce a simpler sequence, or we will want to cse the values.
1193 Return value is the number of insns emitted. */
1196 arm_split_constant (enum rtx_code code, enum machine_mode mode,
1197 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1199 if (subtargets || code == SET
1200 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1201 && REGNO (target) != REGNO (source)))
1203 /* After arm_reorg has been called, we can't fix up expensive
1204 constants by pushing them into memory so we must synthesize
1205 them in-line, regardless of the cost. This is only likely to
1206 be more costly on chips that have load delay slots and we are
1207 compiling without running the scheduler (so no splitting
1208 occurred before the final instruction emission).
1210 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1212 if (!after_arm_reorg
1213 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1214 > arm_constant_limit + (code != SET)))
1218 /* Currently SET is the only monadic value for CODE, all
1219 the rest are diadic. */
1220 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1225 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1227 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1228 /* For MINUS, the value is subtracted from, since we never
1229 have subtraction of a constant. */
1231 emit_insn (gen_rtx_SET (VOIDmode, target,
1232 gen_rtx_MINUS (mode, temp, source)));
1234 emit_insn (gen_rtx_SET (VOIDmode, target,
1235 gen_rtx (code, mode, source, temp)));
1241 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1245 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1247 HOST_WIDE_INT temp1;
1255 if (remainder & (3 << (i - 2)))
1260 temp1 = remainder & ((0x0ff << end)
1261 | ((i < end) ? (0xff >> (32 - end)) : 0));
1262 remainder &= ~temp1;
1267 } while (remainder);
1271 /* As above, but extra parameter GENERATE which, if clear, suppresses
1275 arm_gen_constant (enum rtx_code code, enum machine_mode mode,
1276 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1281 int can_negate_initial = 0;
1284 int num_bits_set = 0;
1285 int set_sign_bit_copies = 0;
1286 int clear_sign_bit_copies = 0;
1287 int clear_zero_bit_copies = 0;
1288 int set_zero_bit_copies = 0;
1290 unsigned HOST_WIDE_INT temp1, temp2;
1291 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1293 /* Find out which operations are safe for a given CODE. Also do a quick
1294 check for degenerate cases; these can occur when DImode operations
1306 can_negate_initial = 1;
1310 if (remainder == 0xffffffff)
1313 emit_insn (gen_rtx_SET (VOIDmode, target,
1314 GEN_INT (ARM_SIGN_EXTEND (val))));
1319 if (reload_completed && rtx_equal_p (target, source))
1322 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1331 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1334 if (remainder == 0xffffffff)
1336 if (reload_completed && rtx_equal_p (target, source))
1339 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1348 if (reload_completed && rtx_equal_p (target, source))
1351 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1354 if (remainder == 0xffffffff)
1357 emit_insn (gen_rtx_SET (VOIDmode, target,
1358 gen_rtx_NOT (mode, source)));
1362 /* We don't know how to handle this yet below. */
1366 /* We treat MINUS as (val - source), since (source - val) is always
1367 passed as (source + (-val)). */
1371 emit_insn (gen_rtx_SET (VOIDmode, target,
1372 gen_rtx_NEG (mode, source)));
1375 if (const_ok_for_arm (val))
1378 emit_insn (gen_rtx_SET (VOIDmode, target,
1379 gen_rtx_MINUS (mode, GEN_INT (val),
1391 /* If we can do it in one insn get out quickly. */
1392 if (const_ok_for_arm (val)
1393 || (can_negate_initial && const_ok_for_arm (-val))
1394 || (can_invert && const_ok_for_arm (~val)))
1397 emit_insn (gen_rtx_SET (VOIDmode, target,
1398 (source ? gen_rtx (code, mode, source,
1404 /* Calculate a few attributes that may be useful for specific
1406 for (i = 31; i >= 0; i--)
1408 if ((remainder & (1 << i)) == 0)
1409 clear_sign_bit_copies++;
1414 for (i = 31; i >= 0; i--)
1416 if ((remainder & (1 << i)) != 0)
1417 set_sign_bit_copies++;
1422 for (i = 0; i <= 31; i++)
1424 if ((remainder & (1 << i)) == 0)
1425 clear_zero_bit_copies++;
1430 for (i = 0; i <= 31; i++)
1432 if ((remainder & (1 << i)) != 0)
1433 set_zero_bit_copies++;
1441 /* See if we can do this by sign_extending a constant that is known
1442 to be negative. This is a good, way of doing it, since the shift
1443 may well merge into a subsequent insn. */
1444 if (set_sign_bit_copies > 1)
1446 if (const_ok_for_arm
1447 (temp1 = ARM_SIGN_EXTEND (remainder
1448 << (set_sign_bit_copies - 1))))
1452 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1453 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1455 emit_insn (gen_ashrsi3 (target, new_src,
1456 GEN_INT (set_sign_bit_copies - 1)));
1460 /* For an inverted constant, we will need to set the low bits,
1461 these will be shifted out of harm's way. */
1462 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1463 if (const_ok_for_arm (~temp1))
1467 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1468 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1470 emit_insn (gen_ashrsi3 (target, new_src,
1471 GEN_INT (set_sign_bit_copies - 1)));
1477 /* See if we can generate this by setting the bottom (or the top)
1478 16 bits, and then shifting these into the other half of the
1479 word. We only look for the simplest cases, to do more would cost
1480 too much. Be careful, however, not to generate this when the
1481 alternative would take fewer insns. */
1482 if (val & 0xffff0000)
1484 temp1 = remainder & 0xffff0000;
1485 temp2 = remainder & 0x0000ffff;
1487 /* Overlaps outside this range are best done using other methods. */
1488 for (i = 9; i < 24; i++)
1490 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1491 && !const_ok_for_arm (temp2))
1493 rtx new_src = (subtargets
1494 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1496 insns = arm_gen_constant (code, mode, temp2, new_src,
1497 source, subtargets, generate);
1500 emit_insn (gen_rtx_SET
1503 gen_rtx_ASHIFT (mode, source,
1510 /* Don't duplicate cases already considered. */
1511 for (i = 17; i < 24; i++)
1513 if (((temp1 | (temp1 >> i)) == remainder)
1514 && !const_ok_for_arm (temp1))
1516 rtx new_src = (subtargets
1517 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1519 insns = arm_gen_constant (code, mode, temp1, new_src,
1520 source, subtargets, generate);
1524 (gen_rtx_SET (VOIDmode, target,
1527 gen_rtx_LSHIFTRT (mode, source,
1538 /* If we have IOR or XOR, and the constant can be loaded in a
1539 single instruction, and we can find a temporary to put it in,
1540 then this can be done in two instructions instead of 3-4. */
1542 /* TARGET can't be NULL if SUBTARGETS is 0 */
1543 || (reload_completed && !reg_mentioned_p (target, source)))
1545 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1549 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1551 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1552 emit_insn (gen_rtx_SET (VOIDmode, target,
1553 gen_rtx (code, mode, source, sub)));
1562 if (set_sign_bit_copies > 8
1563 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1567 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1568 rtx shift = GEN_INT (set_sign_bit_copies);
1570 emit_insn (gen_rtx_SET (VOIDmode, sub,
1572 gen_rtx_ASHIFT (mode,
1575 emit_insn (gen_rtx_SET (VOIDmode, target,
1577 gen_rtx_LSHIFTRT (mode, sub,
1583 if (set_zero_bit_copies > 8
1584 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1588 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1589 rtx shift = GEN_INT (set_zero_bit_copies);
1591 emit_insn (gen_rtx_SET (VOIDmode, sub,
1593 gen_rtx_LSHIFTRT (mode,
1596 emit_insn (gen_rtx_SET (VOIDmode, target,
1598 gen_rtx_ASHIFT (mode, sub,
1604 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1608 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1609 emit_insn (gen_rtx_SET (VOIDmode, sub,
1610 gen_rtx_NOT (mode, source)));
1613 sub = gen_reg_rtx (mode);
1614 emit_insn (gen_rtx_SET (VOIDmode, sub,
1615 gen_rtx_AND (mode, source,
1617 emit_insn (gen_rtx_SET (VOIDmode, target,
1618 gen_rtx_NOT (mode, sub)));
1625 /* See if two shifts will do 2 or more insn's worth of work. */
1626 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1628 HOST_WIDE_INT shift_mask = ((0xffffffff
1629 << (32 - clear_sign_bit_copies))
1632 if ((remainder | shift_mask) != 0xffffffff)
1636 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1637 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1638 new_src, source, subtargets, 1);
1643 rtx targ = subtargets ? NULL_RTX : target;
1644 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1645 targ, source, subtargets, 0);
1651 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1652 rtx shift = GEN_INT (clear_sign_bit_copies);
1654 emit_insn (gen_ashlsi3 (new_src, source, shift));
1655 emit_insn (gen_lshrsi3 (target, new_src, shift));
1661 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1663 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1665 if ((remainder | shift_mask) != 0xffffffff)
1669 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1671 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1672 new_src, source, subtargets, 1);
1677 rtx targ = subtargets ? NULL_RTX : target;
1679 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1680 targ, source, subtargets, 0);
1686 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1687 rtx shift = GEN_INT (clear_zero_bit_copies);
1689 emit_insn (gen_lshrsi3 (new_src, source, shift));
1690 emit_insn (gen_ashlsi3 (target, new_src, shift));
1702 for (i = 0; i < 32; i++)
1703 if (remainder & (1 << i))
1706 if (code == AND || (can_invert && num_bits_set > 16))
1707 remainder = (~remainder) & 0xffffffff;
1708 else if (code == PLUS && num_bits_set > 16)
1709 remainder = (-remainder) & 0xffffffff;
1716 /* Now try and find a way of doing the job in either two or three
1718 We start by looking for the largest block of zeros that are aligned on
1719 a 2-bit boundary, we then fill up the temps, wrapping around to the
1720 top of the word when we drop off the bottom.
1721 In the worst case this code should produce no more than four insns. */
1724 int best_consecutive_zeros = 0;
1726 for (i = 0; i < 32; i += 2)
1728 int consecutive_zeros = 0;
1730 if (!(remainder & (3 << i)))
1732 while ((i < 32) && !(remainder & (3 << i)))
1734 consecutive_zeros += 2;
1737 if (consecutive_zeros > best_consecutive_zeros)
1739 best_consecutive_zeros = consecutive_zeros;
1740 best_start = i - consecutive_zeros;
1746 /* So long as it won't require any more insns to do so, it's
1747 desirable to emit a small constant (in bits 0...9) in the last
1748 insn. This way there is more chance that it can be combined with
1749 a later addressing insn to form a pre-indexed load or store
1750 operation. Consider:
1752 *((volatile int *)0xe0000100) = 1;
1753 *((volatile int *)0xe0000110) = 2;
1755 We want this to wind up as:
1759 str rB, [rA, #0x100]
1761 str rB, [rA, #0x110]
1763 rather than having to synthesize both large constants from scratch.
1765 Therefore, we calculate how many insns would be required to emit
1766 the constant starting from `best_start', and also starting from
1767 zero (ie with bit 31 first to be output). If `best_start' doesn't
1768 yield a shorter sequence, we may as well use zero. */
1770 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1771 && (count_insns_for_constant (remainder, 0) <=
1772 count_insns_for_constant (remainder, best_start)))
1775 /* Now start emitting the insns. */
1783 if (remainder & (3 << (i - 2)))
1788 temp1 = remainder & ((0x0ff << end)
1789 | ((i < end) ? (0xff >> (32 - end)) : 0));
1790 remainder &= ~temp1;
1794 rtx new_src, temp1_rtx;
1796 if (code == SET || code == MINUS)
1798 new_src = (subtargets ? gen_reg_rtx (mode) : target);
1799 if (can_invert && code != MINUS)
1804 if (remainder && subtargets)
1805 new_src = gen_reg_rtx (mode);
1810 else if (can_negate)
1814 temp1 = trunc_int_for_mode (temp1, mode);
1815 temp1_rtx = GEN_INT (temp1);
1819 else if (code == MINUS)
1820 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
1822 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
1824 emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx));
1833 else if (code == MINUS)
1847 /* Canonicalize a comparison so that we are more likely to recognize it.
1848 This can be done for a few constant compares, where we can make the
1849 immediate value easier to load. */
1852 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
1854 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1864 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1865 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1867 *op1 = GEN_INT (i + 1);
1868 return code == GT ? GE : LT;
1874 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1875 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1877 *op1 = GEN_INT (i - 1);
1878 return code == GE ? GT : LE;
1884 if (i != ~((unsigned HOST_WIDE_INT) 0)
1885 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1887 *op1 = GEN_INT (i + 1);
1888 return code == GTU ? GEU : LTU;
1895 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1897 *op1 = GEN_INT (i - 1);
1898 return code == GEU ? GTU : LEU;
1909 /* Decide whether a type should be returned in memory (true)
1910 or in a register (false). This is called by the macro
1911 RETURN_IN_MEMORY. */
1913 arm_return_in_memory (tree type)
1917 if (!AGGREGATE_TYPE_P (type))
1918 /* All simple types are returned in registers. */
1921 size = int_size_in_bytes (type);
1925 /* ATPCS returns aggregate types in memory only if they are
1926 larger than a word (or are variable size). */
1927 return (size < 0 || size > UNITS_PER_WORD);
1930 /* For the arm-wince targets we choose to be compatible with Microsoft's
1931 ARM and Thumb compilers, which always return aggregates in memory. */
1933 /* All structures/unions bigger than one word are returned in memory.
1934 Also catch the case where int_size_in_bytes returns -1. In this case
1935 the aggregate is either huge or of variable size, and in either case
1936 we will want to return it via memory and not in a register. */
1937 if (size < 0 || size > UNITS_PER_WORD)
1940 if (TREE_CODE (type) == RECORD_TYPE)
1944 /* For a struct the APCS says that we only return in a register
1945 if the type is 'integer like' and every addressable element
1946 has an offset of zero. For practical purposes this means
1947 that the structure can have at most one non bit-field element
1948 and that this element must be the first one in the structure. */
1950 /* Find the first field, ignoring non FIELD_DECL things which will
1951 have been created by C++. */
1952 for (field = TYPE_FIELDS (type);
1953 field && TREE_CODE (field) != FIELD_DECL;
1954 field = TREE_CHAIN (field))
1958 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1960 /* Check that the first field is valid for returning in a register. */
1962 /* ... Floats are not allowed */
1963 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1966 /* ... Aggregates that are not themselves valid for returning in
1967 a register are not allowed. */
1968 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1971 /* Now check the remaining fields, if any. Only bitfields are allowed,
1972 since they are not addressable. */
1973 for (field = TREE_CHAIN (field);
1975 field = TREE_CHAIN (field))
1977 if (TREE_CODE (field) != FIELD_DECL)
1980 if (!DECL_BIT_FIELD_TYPE (field))
1987 if (TREE_CODE (type) == UNION_TYPE)
1991 /* Unions can be returned in registers if every element is
1992 integral, or can be returned in an integer register. */
1993 for (field = TYPE_FIELDS (type);
1995 field = TREE_CHAIN (field))
1997 if (TREE_CODE (field) != FIELD_DECL)
2000 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2003 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2009 #endif /* not ARM_WINCE */
2011 /* Return all other types in memory. */
2015 /* Indicate whether or not words of a double are in big-endian order. */
2018 arm_float_words_big_endian (void)
2023 /* For FPA, float words are always big-endian. For VFP, floats words
2024 follow the memory system mode. */
2026 if (TARGET_HARD_FLOAT)
2028 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
2033 return (TARGET_BIG_END ? 1 : 0);
2038 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2039 for a call to a function whose data type is FNTYPE.
2040 For a library call, FNTYPE is NULL. */
2042 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2043 rtx libname ATTRIBUTE_UNUSED,
2044 tree fndecl ATTRIBUTE_UNUSED)
2046 /* On the ARM, the offset starts at 0. */
2047 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2048 pcum->iwmmxt_nregs = 0;
2050 pcum->call_cookie = CALL_NORMAL;
2052 if (TARGET_LONG_CALLS)
2053 pcum->call_cookie = CALL_LONG;
2055 /* Check for long call/short call attributes. The attributes
2056 override any command line option. */
2059 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2060 pcum->call_cookie = CALL_SHORT;
2061 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2062 pcum->call_cookie = CALL_LONG;
2065 /* Varargs vectors are treated the same as long long.
2066 named_count avoids having to change the way arm handles 'named' */
2067 pcum->named_count = 0;
2070 if (TARGET_REALLY_IWMMXT && fntype)
2074 for (fn_arg = TYPE_ARG_TYPES (fntype);
2076 fn_arg = TREE_CHAIN (fn_arg))
2077 pcum->named_count += 1;
2079 if (! pcum->named_count)
2080 pcum->named_count = INT_MAX;
2084 /* Determine where to put an argument to a function.
2085 Value is zero to push the argument on the stack,
2086 or a hard register in which to store the argument.
2088 MODE is the argument's machine mode.
2089 TYPE is the data type of the argument (as a tree).
2090 This is null for libcalls where that information may
2092 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2093 the preceding args and about the function being called.
2094 NAMED is nonzero if this argument is a named parameter
2095 (otherwise it is an extra parameter matching an ellipsis). */
2098 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2099 tree type ATTRIBUTE_UNUSED, int named)
2101 if (TARGET_REALLY_IWMMXT)
2103 if (VECTOR_MODE_SUPPORTED_P (mode))
2105 /* varargs vectors are treated the same as long long.
2106 named_count avoids having to change the way arm handles 'named' */
2107 if (pcum->named_count <= pcum->nargs + 1)
2109 if (pcum->nregs == 1)
2111 if (pcum->nregs <= 2)
2112 return gen_rtx_REG (mode, pcum->nregs);
2116 else if (pcum->iwmmxt_nregs <= 9)
2117 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2121 else if ((mode == DImode || mode == DFmode) && pcum->nregs & 1)
2125 if (mode == VOIDmode)
2126 /* Compute operand 2 of the call insn. */
2127 return GEN_INT (pcum->call_cookie);
2129 if (!named || pcum->nregs >= NUM_ARG_REGS)
2132 return gen_rtx_REG (mode, pcum->nregs);
2135 /* Variable sized types are passed by reference. This is a GCC
2136 extension to the ARM ABI. */
2139 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2140 enum machine_mode mode ATTRIBUTE_UNUSED,
2141 tree type, int named ATTRIBUTE_UNUSED)
2143 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2146 /* Implement va_arg. */
2149 arm_va_arg (tree valist, tree type)
2151 /* Variable sized types are passed by reference. */
2152 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2154 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2155 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2158 if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), NULL) == IWMMXT_ALIGNMENT)
2163 /* Maintain 64-bit alignment of the valist pointer by
2164 constructing: valist = ((valist + (8 - 1)) & -8). */
2165 minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1);
2166 t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0);
2167 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2168 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, minus_eight);
2169 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2170 TREE_SIDE_EFFECTS (t) = 1;
2171 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2173 /* This is to stop the combine pass optimizing
2174 away the alignment adjustment. */
2175 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2178 return std_expand_builtin_va_arg (valist, type);
2181 /* Encode the current state of the #pragma [no_]long_calls. */
2184 OFF, /* No #pramgma [no_]long_calls is in effect. */
2185 LONG, /* #pragma long_calls is in effect. */
2186 SHORT /* #pragma no_long_calls is in effect. */
2189 static arm_pragma_enum arm_pragma_long_calls = OFF;
2192 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2194 arm_pragma_long_calls = LONG;
2198 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2200 arm_pragma_long_calls = SHORT;
2204 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2206 arm_pragma_long_calls = OFF;
2209 /* Table of machine attributes. */
2210 const struct attribute_spec arm_attribute_table[] =
2212 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2213 /* Function calls made to this symbol must be done indirectly, because
2214 it may lie outside of the 26 bit addressing range of a normal function
2216 { "long_call", 0, 0, false, true, true, NULL },
2217 /* Whereas these functions are always known to reside within the 26 bit
2218 addressing range. */
2219 { "short_call", 0, 0, false, true, true, NULL },
2220 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2221 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2222 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2223 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2225 /* ARM/PE has three new attributes:
2227 dllexport - for exporting a function/variable that will live in a dll
2228 dllimport - for importing a function/variable from a dll
2230 Microsoft allows multiple declspecs in one __declspec, separating
2231 them with spaces. We do NOT support this. Instead, use __declspec
2234 { "dllimport", 0, 0, true, false, false, NULL },
2235 { "dllexport", 0, 0, true, false, false, NULL },
2236 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2238 { NULL, 0, 0, false, false, false, NULL }
2241 /* Handle an attribute requiring a FUNCTION_DECL;
2242 arguments as in struct attribute_spec.handler. */
2244 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2245 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2247 if (TREE_CODE (*node) != FUNCTION_DECL)
2249 warning ("`%s' attribute only applies to functions",
2250 IDENTIFIER_POINTER (name));
2251 *no_add_attrs = true;
2257 /* Handle an "interrupt" or "isr" attribute;
2258 arguments as in struct attribute_spec.handler. */
2260 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2265 if (TREE_CODE (*node) != FUNCTION_DECL)
2267 warning ("`%s' attribute only applies to functions",
2268 IDENTIFIER_POINTER (name));
2269 *no_add_attrs = true;
2271 /* FIXME: the argument if any is checked for type attributes;
2272 should it be checked for decl ones? */
2276 if (TREE_CODE (*node) == FUNCTION_TYPE
2277 || TREE_CODE (*node) == METHOD_TYPE)
2279 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2281 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2282 *no_add_attrs = true;
2285 else if (TREE_CODE (*node) == POINTER_TYPE
2286 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2287 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2288 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2290 *node = build_type_copy (*node);
2291 TREE_TYPE (*node) = build_type_attribute_variant
2293 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2294 *no_add_attrs = true;
2298 /* Possibly pass this attribute on from the type to a decl. */
2299 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2300 | (int) ATTR_FLAG_FUNCTION_NEXT
2301 | (int) ATTR_FLAG_ARRAY_NEXT))
2303 *no_add_attrs = true;
2304 return tree_cons (name, args, NULL_TREE);
2308 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2316 /* Return 0 if the attributes for two types are incompatible, 1 if they
2317 are compatible, and 2 if they are nearly compatible (which causes a
2318 warning to be generated). */
2320 arm_comp_type_attributes (tree type1, tree type2)
2324 /* Check for mismatch of non-default calling convention. */
2325 if (TREE_CODE (type1) != FUNCTION_TYPE)
2328 /* Check for mismatched call attributes. */
2329 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2330 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2331 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2332 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2334 /* Only bother to check if an attribute is defined. */
2335 if (l1 | l2 | s1 | s2)
2337 /* If one type has an attribute, the other must have the same attribute. */
2338 if ((l1 != l2) || (s1 != s2))
2341 /* Disallow mixed attributes. */
2342 if ((l1 & s2) || (l2 & s1))
2346 /* Check for mismatched ISR attribute. */
2347 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2349 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2350 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2352 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2359 /* Encode long_call or short_call attribute by prefixing
2360 symbol name in DECL with a special character FLAG. */
2362 arm_encode_call_attribute (tree decl, int flag)
2364 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2365 int len = strlen (str);
2368 /* Do not allow weak functions to be treated as short call. */
2369 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2372 newstr = alloca (len + 2);
2374 strcpy (newstr + 1, str);
2376 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2377 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2380 /* Assigns default attributes to newly defined type. This is used to
2381 set short_call/long_call attributes for function types of
2382 functions defined inside corresponding #pragma scopes. */
2384 arm_set_default_type_attributes (tree type)
2386 /* Add __attribute__ ((long_call)) to all functions, when
2387 inside #pragma long_calls or __attribute__ ((short_call)),
2388 when inside #pragma no_long_calls. */
2389 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2391 tree type_attr_list, attr_name;
2392 type_attr_list = TYPE_ATTRIBUTES (type);
2394 if (arm_pragma_long_calls == LONG)
2395 attr_name = get_identifier ("long_call");
2396 else if (arm_pragma_long_calls == SHORT)
2397 attr_name = get_identifier ("short_call");
2401 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2402 TYPE_ATTRIBUTES (type) = type_attr_list;
2406 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2407 defined within the current compilation unit. If this cannot be
2408 determined, then 0 is returned. */
2410 current_file_function_operand (rtx sym_ref)
2412 /* This is a bit of a fib. A function will have a short call flag
2413 applied to its name if it has the short call attribute, or it has
2414 already been defined within the current compilation unit. */
2415 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2418 /* The current function is always defined within the current compilation
2419 unit. if it s a weak definition however, then this may not be the real
2420 definition of the function, and so we have to say no. */
2421 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2422 && !DECL_WEAK (current_function_decl))
2425 /* We cannot make the determination - default to returning 0. */
2429 /* Return nonzero if a 32 bit "long_call" should be generated for
2430 this call. We generate a long_call if the function:
2432 a. has an __attribute__((long call))
2433 or b. is within the scope of a #pragma long_calls
2434 or c. the -mlong-calls command line switch has been specified
2436 However we do not generate a long call if the function:
2438 d. has an __attribute__ ((short_call))
2439 or e. is inside the scope of a #pragma no_long_calls
2440 or f. has an __attribute__ ((section))
2441 or g. is defined within the current compilation unit.
2443 This function will be called by C fragments contained in the machine
2444 description file. CALL_REF and CALL_COOKIE correspond to the matched
2445 rtl operands. CALL_SYMBOL is used to distinguish between
2446 two different callers of the function. It is set to 1 in the
2447 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2448 and "call_value" patterns. This is because of the difference in the
2449 SYM_REFs passed by these patterns. */
2451 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2455 if (GET_CODE (sym_ref) != MEM)
2458 sym_ref = XEXP (sym_ref, 0);
2461 if (GET_CODE (sym_ref) != SYMBOL_REF)
2464 if (call_cookie & CALL_SHORT)
2467 if (TARGET_LONG_CALLS && flag_function_sections)
2470 if (current_file_function_operand (sym_ref))
2473 return (call_cookie & CALL_LONG)
2474 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2475 || TARGET_LONG_CALLS;
2478 /* Return nonzero if it is ok to make a tail-call to DECL. */
2480 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2482 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2484 if (cfun->machine->sibcall_blocked)
2487 /* Never tailcall something for which we have no decl, or if we
2488 are in Thumb mode. */
2489 if (decl == NULL || TARGET_THUMB)
2492 /* Get the calling method. */
2493 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2494 call_type = CALL_SHORT;
2495 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2496 call_type = CALL_LONG;
2498 /* Cannot tail-call to long calls, since these are out of range of
2499 a branch instruction. However, if not compiling PIC, we know
2500 we can reach the symbol if it is in this compilation unit. */
2501 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2504 /* If we are interworking and the function is not declared static
2505 then we can't tail-call it unless we know that it exists in this
2506 compilation unit (since it might be a Thumb routine). */
2507 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2510 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2511 if (IS_INTERRUPT (arm_current_func_type ()))
2514 /* Everything else is ok. */
2519 /* Addressing mode support functions. */
2521 /* Return nonzero if X is a legitimate immediate operand when compiling
2524 legitimate_pic_operand_p (rtx x)
2528 && (GET_CODE (x) == SYMBOL_REF
2529 || (GET_CODE (x) == CONST
2530 && GET_CODE (XEXP (x, 0)) == PLUS
2531 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2538 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2540 if (GET_CODE (orig) == SYMBOL_REF
2541 || GET_CODE (orig) == LABEL_REF)
2543 #ifndef AOF_ASSEMBLER
2544 rtx pic_ref, address;
2554 reg = gen_reg_rtx (Pmode);
2559 #ifdef AOF_ASSEMBLER
2560 /* The AOF assembler can generate relocations for these directly, and
2561 understands that the PIC register has to be added into the offset. */
2562 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2565 address = gen_reg_rtx (Pmode);
2570 emit_insn (gen_pic_load_addr_arm (address, orig));
2572 emit_insn (gen_pic_load_addr_thumb (address, orig));
2574 if ((GET_CODE (orig) == LABEL_REF
2575 || (GET_CODE (orig) == SYMBOL_REF &&
2576 SYMBOL_REF_LOCAL_P (orig)))
2578 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2581 pic_ref = gen_rtx_MEM (Pmode,
2582 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2584 RTX_UNCHANGING_P (pic_ref) = 1;
2587 insn = emit_move_insn (reg, pic_ref);
2589 current_function_uses_pic_offset_table = 1;
2590 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2592 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2596 else if (GET_CODE (orig) == CONST)
2600 if (GET_CODE (XEXP (orig, 0)) == PLUS
2601 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2609 reg = gen_reg_rtx (Pmode);
2612 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2614 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2615 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2616 base == reg ? 0 : reg);
2621 if (GET_CODE (offset) == CONST_INT)
2623 /* The base register doesn't really matter, we only want to
2624 test the index for the appropriate mode. */
2625 if (!arm_legitimate_index_p (mode, offset, 0))
2627 if (!no_new_pseudos)
2628 offset = force_reg (Pmode, offset);
2633 if (GET_CODE (offset) == CONST_INT)
2634 return plus_constant (base, INTVAL (offset));
2637 if (GET_MODE_SIZE (mode) > 4
2638 && (GET_MODE_CLASS (mode) == MODE_INT
2639 || TARGET_SOFT_FLOAT))
2641 emit_insn (gen_addsi3 (reg, base, offset));
2645 return gen_rtx_PLUS (Pmode, base, offset);
2651 /* Generate code to load the PIC register. PROLOGUE is true if
2652 called from arm_expand_prologue (in which case we want the
2653 generated insns at the start of the function); false if called
2654 by an exception receiver that needs the PIC register reloaded
2655 (in which case the insns are just dumped at the current location). */
2657 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2659 #ifndef AOF_ASSEMBLER
2660 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2661 rtx global_offset_table;
2663 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2670 l1 = gen_label_rtx ();
2672 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2673 /* On the ARM the PC register contains 'dot + 8' at the time of the
2674 addition, on the Thumb it is 'dot + 4'. */
2675 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2677 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2678 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2680 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2682 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2686 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2687 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2691 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2692 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2698 emit_insn_after (seq, get_insns ());
2702 /* Need to emit this whether or not we obey regdecls,
2703 since setjmp/longjmp can cause life info to screw up. */
2704 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2705 #endif /* AOF_ASSEMBLER */
2708 /* Return nonzero if X is valid as an ARM state addressing register. */
2710 arm_address_register_rtx_p (rtx x, int strict_p)
2714 if (GET_CODE (x) != REG)
2720 return ARM_REGNO_OK_FOR_BASE_P (regno);
2722 return (regno <= LAST_ARM_REGNUM
2723 || regno >= FIRST_PSEUDO_REGISTER
2724 || regno == FRAME_POINTER_REGNUM
2725 || regno == ARG_POINTER_REGNUM);
2728 /* Return nonzero if X is a valid ARM state address operand. */
2730 arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
2732 if (arm_address_register_rtx_p (x, strict_p))
2735 else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
2736 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2738 else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY)
2739 && GET_MODE_SIZE (mode) <= 4
2740 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2741 && GET_CODE (XEXP (x, 1)) == PLUS
2742 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2743 return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p);
2745 /* After reload constants split into minipools will have addresses
2746 from a LABEL_REF. */
2747 else if (reload_completed
2748 && (GET_CODE (x) == LABEL_REF
2749 || (GET_CODE (x) == CONST
2750 && GET_CODE (XEXP (x, 0)) == PLUS
2751 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2752 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2755 else if (mode == TImode)
2758 else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
2760 if (GET_CODE (x) == PLUS
2761 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2762 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2764 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2766 if (val == 4 || val == -4 || val == -8)
2771 else if (GET_CODE (x) == PLUS)
2773 rtx xop0 = XEXP (x, 0);
2774 rtx xop1 = XEXP (x, 1);
2776 return ((arm_address_register_rtx_p (xop0, strict_p)
2777 && arm_legitimate_index_p (mode, xop1, strict_p))
2778 || (arm_address_register_rtx_p (xop1, strict_p)
2779 && arm_legitimate_index_p (mode, xop0, strict_p)));
2783 /* Reload currently can't handle MINUS, so disable this for now */
2784 else if (GET_CODE (x) == MINUS)
2786 rtx xop0 = XEXP (x, 0);
2787 rtx xop1 = XEXP (x, 1);
2789 return (arm_address_register_rtx_p (xop0, strict_p)
2790 && arm_legitimate_index_p (mode, xop1, strict_p));
2794 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2795 && GET_CODE (x) == SYMBOL_REF
2796 && CONSTANT_POOL_ADDRESS_P (x)
2798 && symbol_mentioned_p (get_pool_constant (x))))
2801 else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC)
2802 && (GET_MODE_SIZE (mode) <= 4)
2803 && arm_address_register_rtx_p (XEXP (x, 0), strict_p))
2809 /* Return nonzero if INDEX is valid for an address index operand in
2812 arm_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
2814 HOST_WIDE_INT range;
2815 enum rtx_code code = GET_CODE (index);
2817 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
2818 return (code == CONST_INT && INTVAL (index) < 1024
2819 && INTVAL (index) > -1024
2820 && (INTVAL (index) & 3) == 0);
2823 && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode))
2824 return (code == CONST_INT
2825 && INTVAL (index) < 255
2826 && INTVAL (index) > -255);
2828 if (arm_address_register_rtx_p (index, strict_p)
2829 && GET_MODE_SIZE (mode) <= 4)
2832 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
2833 return (code == CONST_INT
2834 && INTVAL (index) < 256
2835 && INTVAL (index) > -256);
2837 /* XXX What about ldrsb? */
2838 if (GET_MODE_SIZE (mode) <= 4 && code == MULT
2839 && (!arm_arch4 || (mode) != HImode))
2841 rtx xiop0 = XEXP (index, 0);
2842 rtx xiop1 = XEXP (index, 1);
2844 return ((arm_address_register_rtx_p (xiop0, strict_p)
2845 && power_of_two_operand (xiop1, SImode))
2846 || (arm_address_register_rtx_p (xiop1, strict_p)
2847 && power_of_two_operand (xiop0, SImode)));
2850 if (GET_MODE_SIZE (mode) <= 4
2851 && (code == LSHIFTRT || code == ASHIFTRT
2852 || code == ASHIFT || code == ROTATERT)
2853 && (!arm_arch4 || (mode) != HImode))
2855 rtx op = XEXP (index, 1);
2857 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
2858 && GET_CODE (op) == CONST_INT
2860 && INTVAL (op) <= 31);
2863 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2864 load, but that has a restricted addressing range and we are unable
2865 to tell here whether that is the case. To be safe we restrict all
2866 loads to that range. */
2868 range = (mode == HImode || mode == QImode) ? 256 : 4096;
2870 range = (mode == HImode) ? 4095 : 4096;
2872 return (code == CONST_INT
2873 && INTVAL (index) < range
2874 && INTVAL (index) > -range);
2877 /* Return nonzero if X is valid as a Thumb state base register. */
2879 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
2883 if (GET_CODE (x) != REG)
2889 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
2891 return (regno <= LAST_LO_REGNUM
2892 || regno > LAST_VIRTUAL_REGISTER
2893 || regno == FRAME_POINTER_REGNUM
2894 || (GET_MODE_SIZE (mode) >= 4
2895 && (regno == STACK_POINTER_REGNUM
2896 || regno >= FIRST_PSEUDO_REGISTER
2897 || x == hard_frame_pointer_rtx
2898 || x == arg_pointer_rtx)));
2901 /* Return nonzero if x is a legitimate index register. This is the case
2902 for any base register that can access a QImode object. */
2904 thumb_index_register_rtx_p (rtx x, int strict_p)
2906 return thumb_base_register_rtx_p (x, QImode, strict_p);
2909 /* Return nonzero if x is a legitimate Thumb-state address.
2911 The AP may be eliminated to either the SP or the FP, so we use the
2912 least common denominator, e.g. SImode, and offsets from 0 to 64.
2914 ??? Verify whether the above is the right approach.
2916 ??? Also, the FP may be eliminated to the SP, so perhaps that
2917 needs special handling also.
2919 ??? Look at how the mips16 port solves this problem. It probably uses
2920 better ways to solve some of these problems.
2922 Although it is not incorrect, we don't accept QImode and HImode
2923 addresses based on the frame pointer or arg pointer until the
2924 reload pass starts. This is so that eliminating such addresses
2925 into stack based ones won't produce impossible code. */
2927 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
2929 /* ??? Not clear if this is right. Experiment. */
2930 if (GET_MODE_SIZE (mode) < 4
2931 && !(reload_in_progress || reload_completed)
2932 && (reg_mentioned_p (frame_pointer_rtx, x)
2933 || reg_mentioned_p (arg_pointer_rtx, x)
2934 || reg_mentioned_p (virtual_incoming_args_rtx, x)
2935 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
2936 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
2937 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
2940 /* Accept any base register. SP only in SImode or larger. */
2941 else if (thumb_base_register_rtx_p (x, mode, strict_p))
2944 /* This is PC relative data before arm_reorg runs. */
2945 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
2946 && GET_CODE (x) == SYMBOL_REF
2947 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
2950 /* This is PC relative data after arm_reorg runs. */
2951 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
2952 && (GET_CODE (x) == LABEL_REF
2953 || (GET_CODE (x) == CONST
2954 && GET_CODE (XEXP (x, 0)) == PLUS
2955 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2956 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2959 /* Post-inc indexing only supported for SImode and larger. */
2960 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
2961 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
2964 else if (GET_CODE (x) == PLUS)
2966 /* REG+REG address can be any two index registers. */
2967 /* We disallow FRAME+REG addressing since we know that FRAME
2968 will be replaced with STACK, and SP relative addressing only
2969 permits SP+OFFSET. */
2970 if (GET_MODE_SIZE (mode) <= 4
2971 && XEXP (x, 0) != frame_pointer_rtx
2972 && XEXP (x, 1) != frame_pointer_rtx
2973 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2974 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
2977 /* REG+const has 5-7 bit offset for non-SP registers. */
2978 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2979 || XEXP (x, 0) == arg_pointer_rtx)
2980 && GET_CODE (XEXP (x, 1)) == CONST_INT
2981 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
2984 /* REG+const has 10 bit offset for SP, but only SImode and
2985 larger is supported. */
2986 /* ??? Should probably check for DI/DFmode overflow here
2987 just like GO_IF_LEGITIMATE_OFFSET does. */
2988 else if (GET_CODE (XEXP (x, 0)) == REG
2989 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
2990 && GET_MODE_SIZE (mode) >= 4
2991 && GET_CODE (XEXP (x, 1)) == CONST_INT
2992 && INTVAL (XEXP (x, 1)) >= 0
2993 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
2994 && (INTVAL (XEXP (x, 1)) & 3) == 0)
2997 else if (GET_CODE (XEXP (x, 0)) == REG
2998 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
2999 && GET_MODE_SIZE (mode) >= 4
3000 && GET_CODE (XEXP (x, 1)) == CONST_INT
3001 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3005 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3006 && GET_MODE_SIZE (mode) == 4
3007 && GET_CODE (x) == SYMBOL_REF
3008 && CONSTANT_POOL_ADDRESS_P (x)
3010 && symbol_mentioned_p (get_pool_constant (x))))
3016 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3017 instruction of mode MODE. */
3019 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3021 switch (GET_MODE_SIZE (mode))
3024 return val >= 0 && val < 32;
3027 return val >= 0 && val < 64 && (val & 1) == 0;
3031 && (val + GET_MODE_SIZE (mode)) <= 128
3036 /* Try machine-dependent ways of modifying an illegitimate address
3037 to be legitimate. If we find one, return the new, valid address. */
3039 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3041 if (GET_CODE (x) == PLUS)
3043 rtx xop0 = XEXP (x, 0);
3044 rtx xop1 = XEXP (x, 1);
3046 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3047 xop0 = force_reg (SImode, xop0);
3049 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3050 xop1 = force_reg (SImode, xop1);
3052 if (ARM_BASE_REGISTER_RTX_P (xop0)
3053 && GET_CODE (xop1) == CONST_INT)
3055 HOST_WIDE_INT n, low_n;
3059 if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
3071 low_n = ((mode) == TImode ? 0
3072 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3076 base_reg = gen_reg_rtx (SImode);
3077 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3078 GEN_INT (n)), NULL_RTX);
3079 emit_move_insn (base_reg, val);
3080 x = (low_n == 0 ? base_reg
3081 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3083 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3084 x = gen_rtx_PLUS (SImode, xop0, xop1);
3087 /* XXX We don't allow MINUS any more -- see comment in
3088 arm_legitimate_address_p (). */
3089 else if (GET_CODE (x) == MINUS)
3091 rtx xop0 = XEXP (x, 0);
3092 rtx xop1 = XEXP (x, 1);
3094 if (CONSTANT_P (xop0))
3095 xop0 = force_reg (SImode, xop0);
3097 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3098 xop1 = force_reg (SImode, xop1);
3100 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3101 x = gen_rtx_MINUS (SImode, xop0, xop1);
3106 /* We need to find and carefully transform any SYMBOL and LABEL
3107 references; so go back to the original address expression. */
3108 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3110 if (new_x != orig_x)
3119 #define REG_OR_SUBREG_REG(X) \
3120 (GET_CODE (X) == REG \
3121 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3123 #define REG_OR_SUBREG_RTX(X) \
3124 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3126 #ifndef COSTS_N_INSNS
3127 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3129 /* Worker routine for arm_rtx_costs. */
3131 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3133 enum machine_mode mode = GET_MODE (x);
3134 enum rtx_code subcode;
3150 return COSTS_N_INSNS (1);
3153 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3156 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3163 return COSTS_N_INSNS (2) + cycles;
3165 return COSTS_N_INSNS (1) + 16;
3168 return (COSTS_N_INSNS (1)
3169 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3170 + GET_CODE (SET_DEST (x)) == MEM));
3175 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3177 if (thumb_shiftable_const (INTVAL (x)))
3178 return COSTS_N_INSNS (2);
3179 return COSTS_N_INSNS (3);
3181 else if ((outer == PLUS || outer == COMPARE)
3182 && INTVAL (x) < 256 && INTVAL (x) > -256)
3184 else if (outer == AND
3185 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3186 return COSTS_N_INSNS (1);
3187 else if (outer == ASHIFT || outer == ASHIFTRT
3188 || outer == LSHIFTRT)
3190 return COSTS_N_INSNS (2);
3196 return COSTS_N_INSNS (3);
3215 /* XXX another guess. */
3216 /* Memory costs quite a lot for the first word, but subsequent words
3217 load at the equivalent of a single insn each. */
3218 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3219 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3224 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3229 /* XXX still guessing. */
3230 switch (GET_MODE (XEXP (x, 0)))
3233 return (1 + (mode == DImode ? 4 : 0)
3234 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3237 return (4 + (mode == DImode ? 4 : 0)
3238 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3241 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3255 /* Memory costs quite a lot for the first word, but subsequent words
3256 load at the equivalent of a single insn each. */
3257 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3258 + (GET_CODE (x) == SYMBOL_REF
3259 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3265 return optimize_size ? COSTS_N_INSNS (2) : 100;
3268 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3275 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3277 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3278 + ((GET_CODE (XEXP (x, 0)) == REG
3279 || (GET_CODE (XEXP (x, 0)) == SUBREG
3280 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3282 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3283 || (GET_CODE (XEXP (x, 0)) == SUBREG
3284 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3286 + ((GET_CODE (XEXP (x, 1)) == REG
3287 || (GET_CODE (XEXP (x, 1)) == SUBREG
3288 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3289 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3294 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3295 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3296 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3297 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3300 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3301 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3302 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3303 && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
3305 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3306 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3307 && const_double_rtx_ok_for_fpa (XEXP (x, 0))))
3310 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3311 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3312 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3313 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3314 || subcode == ASHIFTRT || subcode == LSHIFTRT
3315 || subcode == ROTATE || subcode == ROTATERT
3317 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3318 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3319 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3320 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3321 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3322 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3323 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3328 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3329 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3330 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3331 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3332 && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
3336 case AND: case XOR: case IOR:
3339 /* Normally the frame registers will be spilt into reg+const during
3340 reload, so it is a bad idea to combine them with other instructions,
3341 since then they might not be moved outside of loops. As a compromise
3342 we allow integration with ops that have a constant as their second
3344 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3345 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3346 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3347 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3348 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3352 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3353 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3354 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3355 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3358 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3359 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3360 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3361 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3362 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3365 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3366 return (1 + extra_cost
3367 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3368 || subcode == LSHIFTRT || subcode == ASHIFTRT
3369 || subcode == ROTATE || subcode == ROTATERT
3371 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3372 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3373 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3374 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3375 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3376 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3382 /* There is no point basing this on the tuning, since it is always the
3383 fast variant if it exists at all. */
3384 if (arm_fast_multiply && mode == DImode
3385 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3386 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3387 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3390 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3394 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3396 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3397 & (unsigned HOST_WIDE_INT) 0xffffffff);
3398 int cost, const_ok = const_ok_for_arm (i);
3399 int j, booth_unit_size;
3401 if (arm_tune_xscale)
3403 unsigned HOST_WIDE_INT masked_const;
3405 /* The cost will be related to two insns.
3406 First a load of the constant (MOV or LDR), then a multiply. */
3409 cost += 1; /* LDR is probably more expensive because
3410 of longer result latency. */
3411 masked_const = i & 0xffff8000;
3412 if (masked_const != 0 && masked_const != 0xffff8000)
3414 masked_const = i & 0xf8000000;
3415 if (masked_const == 0 || masked_const == 0xf8000000)
3423 /* Tune as appropriate. */
3424 cost = const_ok ? 4 : 8;
3425 booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
3426 for (j = 0; i && j < 32; j += booth_unit_size)
3428 i >>= booth_unit_size;
3435 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
3436 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3437 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
3440 if (arm_fast_multiply && mode == SImode
3441 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3442 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3443 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3444 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3445 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3446 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3451 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3452 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3456 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3458 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3461 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3469 return 4 + (mode == DImode ? 4 : 0);
3472 if (GET_MODE (XEXP (x, 0)) == QImode)
3473 return (4 + (mode == DImode ? 4 : 0)
3474 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3477 switch (GET_MODE (XEXP (x, 0)))
3480 return (1 + (mode == DImode ? 4 : 0)
3481 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3484 return (4 + (mode == DImode ? 4 : 0)
3485 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3488 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3503 if (const_ok_for_arm (INTVAL (x)))
3504 return outer == SET ? 2 : -1;
3505 else if (outer == AND
3506 && const_ok_for_arm (~INTVAL (x)))
3508 else if ((outer == COMPARE
3509 || outer == PLUS || outer == MINUS)
3510 && const_ok_for_arm (-INTVAL (x)))
3521 if (const_double_rtx_ok_for_fpa (x))
3522 return outer == SET ? 2 : -1;
3523 else if ((outer == COMPARE || outer == PLUS)
3524 && neg_const_double_rtx_ok_for_fpa (x))
3534 arm_rtx_costs (rtx x, int code, int outer_code, int *total)
3536 *total = arm_rtx_costs_1 (x, code, outer_code);
3540 /* All address computations that can be done are free, but rtx cost returns
3541 the same for practically all of them. So we weight the different types
3542 of address here in the order (most pref first):
3543 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3545 arm_arm_address_cost (rtx x)
3547 enum rtx_code c = GET_CODE (x);
3549 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
3551 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
3554 if (c == PLUS || c == MINUS)
3556 char cl0 = GET_RTX_CLASS (GET_CODE (XEXP (x, 0)));
3557 char cl1 = GET_RTX_CLASS (GET_CODE (XEXP (x, 1)));
3559 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
3562 if (cl0 == '2' || cl0 == 'c' || cl1 == '2' || cl1 == 'c')
3572 arm_thumb_address_cost (rtx x)
3574 enum rtx_code c = GET_CODE (x);
3579 && GET_CODE (XEXP (x, 0)) == REG
3580 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3587 arm_address_cost (rtx x)
3589 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
3593 arm_use_dfa_pipeline_interface (void)
3599 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
3603 /* Some true dependencies can have a higher cost depending
3604 on precisely how certain input operands are used. */
3606 && REG_NOTE_KIND (link) == 0
3607 && recog_memoized (insn) >= 0
3608 && recog_memoized (dep) >= 0)
3610 int shift_opnum = get_attr_shift (insn);
3611 enum attr_type attr_type = get_attr_type (dep);
3613 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3614 operand for INSN. If we have a shifted input operand and the
3615 instruction we depend on is another ALU instruction, then we may
3616 have to account for an additional stall. */
3617 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
3619 rtx shifted_operand;
3622 /* Get the shifted operand. */
3623 extract_insn (insn);
3624 shifted_operand = recog_data.operand[shift_opnum];
3626 /* Iterate over all the operands in DEP. If we write an operand
3627 that overlaps with SHIFTED_OPERAND, then we have increase the
3628 cost of this dependency. */
3630 preprocess_constraints ();
3631 for (opno = 0; opno < recog_data.n_operands; opno++)
3633 /* We can ignore strict inputs. */
3634 if (recog_data.operand_type[opno] == OP_IN)
3637 if (reg_overlap_mentioned_p (recog_data.operand[opno],
3644 /* XXX This is not strictly true for the FPA. */
3645 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
3646 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3649 /* Call insns don't incur a stall, even if they follow a load. */
3650 if (REG_NOTE_KIND (link) == 0
3651 && GET_CODE (insn) == CALL_INSN)
3654 if ((i_pat = single_set (insn)) != NULL
3655 && GET_CODE (SET_SRC (i_pat)) == MEM
3656 && (d_pat = single_set (dep)) != NULL
3657 && GET_CODE (SET_DEST (d_pat)) == MEM)
3659 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
3660 /* This is a load after a store, there is no conflict if the load reads
3661 from a cached area. Assume that loads from the stack, and from the
3662 constant pool are cached, and that others will miss. This is a
3665 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
3666 || reg_mentioned_p (stack_pointer_rtx, src_mem)
3667 || reg_mentioned_p (frame_pointer_rtx, src_mem)
3668 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
3675 static int fpa_consts_inited = 0;
3677 static const char * const strings_fpa[8] =
3680 "4", "5", "0.5", "10"
3683 static REAL_VALUE_TYPE values_fpa[8];
3686 init_fpa_table (void)
3691 for (i = 0; i < 8; i++)
3693 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
3697 fpa_consts_inited = 1;
3700 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3702 const_double_rtx_ok_for_fpa (rtx x)
3707 if (!fpa_consts_inited)
3710 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3711 if (REAL_VALUE_MINUS_ZERO (r))
3714 for (i = 0; i < 8; i++)
3715 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3721 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3723 neg_const_double_rtx_ok_for_fpa (rtx x)
3728 if (!fpa_consts_inited)
3731 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3732 r = REAL_VALUE_NEGATE (r);
3733 if (REAL_VALUE_MINUS_ZERO (r))
3736 for (i = 0; i < 8; i++)
3737 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3743 /* Predicates for `match_operand' and `match_operator'. */
3745 /* s_register_operand is the same as register_operand, but it doesn't accept
3748 This function exists because at the time it was put in it led to better
3749 code. SUBREG(MEM) always needs a reload in the places where
3750 s_register_operand is used, and this seemed to lead to excessive
3753 s_register_operand (rtx op, enum machine_mode mode)
3755 if (GET_MODE (op) != mode && mode != VOIDmode)
3758 if (GET_CODE (op) == SUBREG)
3759 op = SUBREG_REG (op);
3761 /* We don't consider registers whose class is NO_REGS
3762 to be a register operand. */
3763 /* XXX might have to check for lo regs only for thumb ??? */
3764 return (GET_CODE (op) == REG
3765 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3766 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3769 /* A hard register operand (even before reload. */
3771 arm_hard_register_operand (rtx op, enum machine_mode mode)
3773 if (GET_MODE (op) != mode && mode != VOIDmode)
3776 return (GET_CODE (op) == REG
3777 && REGNO (op) < FIRST_PSEUDO_REGISTER);
3780 /* Only accept reg, subreg(reg), const_int. */
3782 reg_or_int_operand (rtx op, enum machine_mode mode)
3784 if (GET_CODE (op) == CONST_INT)
3787 if (GET_MODE (op) != mode && mode != VOIDmode)
3790 if (GET_CODE (op) == SUBREG)
3791 op = SUBREG_REG (op);
3793 /* We don't consider registers whose class is NO_REGS
3794 to be a register operand. */
3795 return (GET_CODE (op) == REG
3796 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3797 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3800 /* Return 1 if OP is an item in memory, given that we are in reload. */
3802 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3804 int regno = true_regnum (op);
3806 return (!CONSTANT_P (op)
3808 || (GET_CODE (op) == REG
3809 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
3812 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3813 memory access (architecture V4).
3814 MODE is QImode if called when computing constraints, or VOIDmode when
3815 emitting patterns. In this latter case we cannot use memory_operand()
3816 because it will fail on badly formed MEMs, which is precisely what we are
3819 bad_signed_byte_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3821 if (GET_CODE (op) != MEM)
3826 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3827 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3828 && (!s_register_operand (XEXP (op, 0), VOIDmode)
3829 || (!s_register_operand (XEXP (op, 1), VOIDmode)
3830 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
3833 /* Big constants are also bad. */
3834 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
3835 && (INTVAL (XEXP (op, 1)) > 0xff
3836 || -INTVAL (XEXP (op, 1)) > 0xff))
3839 /* Everything else is good, or can will automatically be made so. */
3843 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3845 arm_rhs_operand (rtx op, enum machine_mode mode)
3847 return (s_register_operand (op, mode)
3848 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
3851 /* Return TRUE for valid operands for the
3852 rhs of an ARM instruction, or a load. */
3854 arm_rhsm_operand (rtx op, enum machine_mode mode)
3856 return (s_register_operand (op, mode)
3857 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
3858 || memory_operand (op, mode));
3861 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3862 constant that is valid when negated. */
3864 arm_add_operand (rtx op, enum machine_mode mode)
3867 return thumb_cmp_operand (op, mode);
3869 return (s_register_operand (op, mode)
3870 || (GET_CODE (op) == CONST_INT
3871 && (const_ok_for_arm (INTVAL (op))
3872 || const_ok_for_arm (-INTVAL (op)))));
3875 /* Return TRUE for valid ARM constants (or when valid if negated). */
3877 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3879 return (GET_CODE (op) == CONST_INT
3880 && (const_ok_for_arm (INTVAL (op))
3881 || const_ok_for_arm (-INTVAL (op))));
3885 arm_not_operand (rtx op, enum machine_mode mode)
3887 return (s_register_operand (op, mode)
3888 || (GET_CODE (op) == CONST_INT
3889 && (const_ok_for_arm (INTVAL (op))
3890 || const_ok_for_arm (~INTVAL (op)))));
3893 /* Return TRUE if the operand is a memory reference which contains an
3894 offsettable address. */
3896 offsettable_memory_operand (rtx op, enum machine_mode mode)
3898 if (mode == VOIDmode)
3899 mode = GET_MODE (op);
3901 return (mode == GET_MODE (op)
3902 && GET_CODE (op) == MEM
3903 && offsettable_address_p (reload_completed | reload_in_progress,
3904 mode, XEXP (op, 0)));
3907 /* Return TRUE if the operand is a memory reference which is, or can be
3908 made word aligned by adjusting the offset. */
3910 alignable_memory_operand (rtx op, enum machine_mode mode)
3914 if (mode == VOIDmode)
3915 mode = GET_MODE (op);
3917 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3922 return ((GET_CODE (reg = op) == REG
3923 || (GET_CODE (op) == SUBREG
3924 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3925 || (GET_CODE (op) == PLUS
3926 && GET_CODE (XEXP (op, 1)) == CONST_INT
3927 && (GET_CODE (reg = XEXP (op, 0)) == REG
3928 || (GET_CODE (XEXP (op, 0)) == SUBREG
3929 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3930 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3933 /* Similar to s_register_operand, but does not allow hard integer
3936 f_register_operand (rtx op, enum machine_mode mode)
3938 if (GET_MODE (op) != mode && mode != VOIDmode)
3941 if (GET_CODE (op) == SUBREG)
3942 op = SUBREG_REG (op);
3944 /* We don't consider registers whose class is NO_REGS
3945 to be a register operand. */
3946 return (GET_CODE (op) == REG
3947 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3948 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
3951 /* Return TRUE for valid operands for the rhs of an FPA instruction. */
3953 fpa_rhs_operand (rtx op, enum machine_mode mode)
3955 if (s_register_operand (op, mode))
3958 if (GET_MODE (op) != mode && mode != VOIDmode)
3961 if (GET_CODE (op) == CONST_DOUBLE)
3962 return const_double_rtx_ok_for_fpa (op);
3968 fpa_add_operand (rtx op, enum machine_mode mode)
3970 if (s_register_operand (op, mode))
3973 if (GET_MODE (op) != mode && mode != VOIDmode)
3976 if (GET_CODE (op) == CONST_DOUBLE)
3977 return (const_double_rtx_ok_for_fpa (op)
3978 || neg_const_double_rtx_ok_for_fpa (op));
3983 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
3985 cirrus_memory_offset (rtx op)
3987 /* Reject eliminable registers. */
3988 if (! (reload_in_progress || reload_completed)
3989 && ( reg_mentioned_p (frame_pointer_rtx, op)
3990 || reg_mentioned_p (arg_pointer_rtx, op)
3991 || reg_mentioned_p (virtual_incoming_args_rtx, op)
3992 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
3993 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
3994 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
3997 if (GET_CODE (op) == MEM)
4003 /* Match: (mem (reg)). */
4004 if (GET_CODE (ind) == REG)
4010 if (GET_CODE (ind) == PLUS
4011 && GET_CODE (XEXP (ind, 0)) == REG
4012 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4013 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4020 /* Return nonzero if OP is a Cirrus or general register. */
4022 cirrus_register_operand (rtx op, enum machine_mode mode)
4024 if (GET_MODE (op) != mode && mode != VOIDmode)
4027 if (GET_CODE (op) == SUBREG)
4028 op = SUBREG_REG (op);
4030 return (GET_CODE (op) == REG
4031 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4032 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4035 /* Return nonzero if OP is a cirrus FP register. */
4037 cirrus_fp_register (rtx op, enum machine_mode mode)
4039 if (GET_MODE (op) != mode && mode != VOIDmode)
4042 if (GET_CODE (op) == SUBREG)
4043 op = SUBREG_REG (op);
4045 return (GET_CODE (op) == REG
4046 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4047 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4050 /* Return nonzero if OP is a 6bit constant (0..63). */
4052 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4054 return (GET_CODE (op) == CONST_INT
4056 && INTVAL (op) < 64);
4059 /* Return true if X is a register that will be eliminated later on. */
4061 arm_eliminable_register (rtx x)
4063 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
4064 || REGNO (x) == ARG_POINTER_REGNUM
4065 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
4066 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
4069 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4070 Use by the Cirrus Maverick code which has to workaround
4071 a hardware bug triggered by such instructions. */
4073 arm_memory_load_p (rtx insn)
4075 rtx body, lhs, rhs;;
4077 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4080 body = PATTERN (insn);
4082 if (GET_CODE (body) != SET)
4085 lhs = XEXP (body, 0);
4086 rhs = XEXP (body, 1);
4088 lhs = REG_OR_SUBREG_RTX (lhs);
4090 /* If the destination is not a general purpose
4091 register we do not have to worry. */
4092 if (GET_CODE (lhs) != REG
4093 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4096 /* As well as loads from memory we also have to react
4097 to loads of invalid constants which will be turned
4098 into loads from the minipool. */
4099 return (GET_CODE (rhs) == MEM
4100 || GET_CODE (rhs) == SYMBOL_REF
4101 || note_invalid_constants (insn, -1, false));
4104 /* Return TRUE if INSN is a Cirrus instruction. */
4106 arm_cirrus_insn_p (rtx insn)
4108 enum attr_cirrus attr;
4110 /* get_attr aborts on USE and CLOBBER. */
4112 || GET_CODE (insn) != INSN
4113 || GET_CODE (PATTERN (insn)) == USE
4114 || GET_CODE (PATTERN (insn)) == CLOBBER)
4117 attr = get_attr_cirrus (insn);
4119 return attr != CIRRUS_NOT;
4122 /* Cirrus reorg for invalid instruction combinations. */
4124 cirrus_reorg (rtx first)
4126 enum attr_cirrus attr;
4127 rtx body = PATTERN (first);
4131 /* Any branch must be followed by 2 non Cirrus instructions. */
4132 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4135 t = next_nonnote_insn (first);
4137 if (arm_cirrus_insn_p (t))
4140 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4144 emit_insn_after (gen_nop (), first);
4149 /* (float (blah)) is in parallel with a clobber. */
4150 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4151 body = XVECEXP (body, 0, 0);
4153 if (GET_CODE (body) == SET)
4155 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4157 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4158 be followed by a non Cirrus insn. */
4159 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4161 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4162 emit_insn_after (gen_nop (), first);
4166 else if (arm_memory_load_p (first))
4168 unsigned int arm_regno;
4170 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4171 ldr/cfmv64hr combination where the Rd field is the same
4172 in both instructions must be split with a non Cirrus
4179 /* Get Arm register number for ldr insn. */
4180 if (GET_CODE (lhs) == REG)
4181 arm_regno = REGNO (lhs);
4182 else if (GET_CODE (rhs) == REG)
4183 arm_regno = REGNO (rhs);
4188 first = next_nonnote_insn (first);
4190 if (! arm_cirrus_insn_p (first))
4193 body = PATTERN (first);
4195 /* (float (blah)) is in parallel with a clobber. */
4196 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4197 body = XVECEXP (body, 0, 0);
4199 if (GET_CODE (body) == FLOAT)
4200 body = XEXP (body, 0);
4202 if (get_attr_cirrus (first) == CIRRUS_MOVE
4203 && GET_CODE (XEXP (body, 1)) == REG
4204 && arm_regno == REGNO (XEXP (body, 1)))
4205 emit_insn_after (gen_nop (), first);
4211 /* get_attr aborts on USE and CLOBBER. */
4213 || GET_CODE (first) != INSN
4214 || GET_CODE (PATTERN (first)) == USE
4215 || GET_CODE (PATTERN (first)) == CLOBBER)
4218 attr = get_attr_cirrus (first);
4220 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4221 must be followed by a non-coprocessor instruction. */
4222 if (attr == CIRRUS_COMPARE)
4226 t = next_nonnote_insn (first);
4228 if (arm_cirrus_insn_p (t))
4231 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4235 emit_insn_after (gen_nop (), first);
4241 /* Return nonzero if OP is a constant power of two. */
4243 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4245 if (GET_CODE (op) == CONST_INT)
4247 HOST_WIDE_INT value = INTVAL (op);
4249 return value != 0 && (value & (value - 1)) == 0;
4255 /* Return TRUE for a valid operand of a DImode operation.
4256 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4257 Note that this disallows MEM(REG+REG), but allows
4258 MEM(PRE/POST_INC/DEC(REG)). */
4260 di_operand (rtx op, enum machine_mode mode)
4262 if (s_register_operand (op, mode))
4265 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4268 if (GET_CODE (op) == SUBREG)
4269 op = SUBREG_REG (op);
4271 switch (GET_CODE (op))
4278 return memory_address_p (DImode, XEXP (op, 0));
4285 /* Like di_operand, but don't accept constants. */
4287 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4289 if (s_register_operand (op, mode))
4292 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4295 if (GET_CODE (op) == SUBREG)
4296 op = SUBREG_REG (op);
4298 if (GET_CODE (op) == MEM)
4299 return memory_address_p (DImode, XEXP (op, 0));
4304 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
4305 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4306 Note that this disallows MEM(REG+REG), but allows
4307 MEM(PRE/POST_INC/DEC(REG)). */
4309 soft_df_operand (rtx op, enum machine_mode mode)
4311 if (s_register_operand (op, mode))
4314 if (mode != VOIDmode && GET_MODE (op) != mode)
4317 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4320 if (GET_CODE (op) == SUBREG)
4321 op = SUBREG_REG (op);
4323 switch (GET_CODE (op))
4329 return memory_address_p (DFmode, XEXP (op, 0));
4336 /* Like soft_df_operand, but don't accept constants. */
4338 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4340 if (s_register_operand (op, mode))
4343 if (mode != VOIDmode && GET_MODE (op) != mode)
4346 if (GET_CODE (op) == SUBREG)
4347 op = SUBREG_REG (op);
4349 if (GET_CODE (op) == MEM)
4350 return memory_address_p (DFmode, XEXP (op, 0));
4354 /* Return TRUE for valid index operands. */
4356 index_operand (rtx op, enum machine_mode mode)
4358 return (s_register_operand (op, mode)
4359 || (immediate_operand (op, mode)
4360 && (GET_CODE (op) != CONST_INT
4361 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4364 /* Return TRUE for valid shifts by a constant. This also accepts any
4365 power of two on the (somewhat overly relaxed) assumption that the
4366 shift operator in this case was a mult. */
4368 const_shift_operand (rtx op, enum machine_mode mode)
4370 return (power_of_two_operand (op, mode)
4371 || (immediate_operand (op, mode)
4372 && (GET_CODE (op) != CONST_INT
4373 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
4376 /* Return TRUE for arithmetic operators which can be combined with a multiply
4379 shiftable_operator (rtx x, enum machine_mode mode)
4383 if (GET_MODE (x) != mode)
4386 code = GET_CODE (x);
4388 return (code == PLUS || code == MINUS
4389 || code == IOR || code == XOR || code == AND);
4392 /* Return TRUE for binary logical operators. */
4394 logical_binary_operator (rtx x, enum machine_mode mode)
4398 if (GET_MODE (x) != mode)
4401 code = GET_CODE (x);
4403 return (code == IOR || code == XOR || code == AND);
4406 /* Return TRUE for shift operators. */
4408 shift_operator (rtx x,enum machine_mode mode)
4412 if (GET_MODE (x) != mode)
4415 code = GET_CODE (x);
4418 return power_of_two_operand (XEXP (x, 1), mode);
4420 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
4421 || code == ROTATERT);
4424 /* Return TRUE if x is EQ or NE. */
4426 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
4428 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
4431 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4433 arm_comparison_operator (rtx x, enum machine_mode mode)
4435 return (comparison_operator (x, mode)
4436 && GET_CODE (x) != LTGT
4437 && GET_CODE (x) != UNEQ);
4440 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4442 minmax_operator (rtx x, enum machine_mode mode)
4444 enum rtx_code code = GET_CODE (x);
4446 if (GET_MODE (x) != mode)
4449 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
4452 /* Return TRUE if this is the condition code register, if we aren't given
4453 a mode, accept any class CCmode register. */
4455 cc_register (rtx x, enum machine_mode mode)
4457 if (mode == VOIDmode)
4459 mode = GET_MODE (x);
4461 if (GET_MODE_CLASS (mode) != MODE_CC)
4465 if ( GET_MODE (x) == mode
4466 && GET_CODE (x) == REG
4467 && REGNO (x) == CC_REGNUM)
4473 /* Return TRUE if this is the condition code register, if we aren't given
4474 a mode, accept any class CCmode register which indicates a dominance
4477 dominant_cc_register (rtx x, enum machine_mode mode)
4479 if (mode == VOIDmode)
4481 mode = GET_MODE (x);
4483 if (GET_MODE_CLASS (mode) != MODE_CC)
4487 if (mode != CC_DNEmode && mode != CC_DEQmode
4488 && mode != CC_DLEmode && mode != CC_DLTmode
4489 && mode != CC_DGEmode && mode != CC_DGTmode
4490 && mode != CC_DLEUmode && mode != CC_DLTUmode
4491 && mode != CC_DGEUmode && mode != CC_DGTUmode)
4494 return cc_register (x, mode);
4497 /* Return TRUE if X references a SYMBOL_REF. */
4499 symbol_mentioned_p (rtx x)
4504 if (GET_CODE (x) == SYMBOL_REF)
4507 fmt = GET_RTX_FORMAT (GET_CODE (x));
4509 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4515 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4516 if (symbol_mentioned_p (XVECEXP (x, i, j)))
4519 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
4526 /* Return TRUE if X references a LABEL_REF. */
4528 label_mentioned_p (rtx x)
4533 if (GET_CODE (x) == LABEL_REF)
4536 fmt = GET_RTX_FORMAT (GET_CODE (x));
4537 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4543 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4544 if (label_mentioned_p (XVECEXP (x, i, j)))
4547 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
4557 enum rtx_code code = GET_CODE (x);
4561 else if (code == SMIN)
4563 else if (code == UMIN)
4565 else if (code == UMAX)
4571 /* Return 1 if memory locations are adjacent. */
4573 adjacent_mem_locations (rtx a, rtx b)
4575 if ((GET_CODE (XEXP (a, 0)) == REG
4576 || (GET_CODE (XEXP (a, 0)) == PLUS
4577 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
4578 && (GET_CODE (XEXP (b, 0)) == REG
4579 || (GET_CODE (XEXP (b, 0)) == PLUS
4580 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
4582 HOST_WIDE_INT val0 = 0, val1 = 0;
4586 if (GET_CODE (XEXP (a, 0)) == PLUS)
4588 reg0 = XEXP (XEXP (a, 0), 0);
4589 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
4594 if (GET_CODE (XEXP (b, 0)) == PLUS)
4596 reg1 = XEXP (XEXP (b, 0), 0);
4597 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
4602 /* Don't accept any offset that will require multiple
4603 instructions to handle, since this would cause the
4604 arith_adjacentmem pattern to output an overlong sequence. */
4605 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
4608 /* Don't allow an eliminable register: register elimination can make
4609 the offset too large. */
4610 if (arm_eliminable_register (reg0))
4613 val_diff = val1 - val0;
4614 return ((REGNO (reg0) == REGNO (reg1))
4615 && (val_diff == 4 || val_diff == -4));
4621 /* Return 1 if OP is a load multiple operation. It is known to be
4622 parallel and the first section will be tested. */
4624 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4626 HOST_WIDE_INT count = XVECLEN (op, 0);
4629 HOST_WIDE_INT i = 1, base = 0;
4633 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4636 /* Check to see if this might be a write-back. */
4637 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4642 /* Now check it more carefully. */
4643 if (GET_CODE (SET_DEST (elt)) != REG
4644 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4645 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4646 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4650 /* Perform a quick check so we don't blow up below. */
4652 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4653 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
4654 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
4657 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
4658 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
4660 for (; i < count; i++)
4662 elt = XVECEXP (op, 0, i);
4664 if (GET_CODE (elt) != SET
4665 || GET_CODE (SET_DEST (elt)) != REG
4666 || GET_MODE (SET_DEST (elt)) != SImode
4667 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
4668 || GET_CODE (SET_SRC (elt)) != MEM
4669 || GET_MODE (SET_SRC (elt)) != SImode
4670 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
4671 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
4672 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
4673 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
4680 /* Return 1 if OP is a store multiple operation. It is known to be
4681 parallel and the first section will be tested. */
4683 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4685 HOST_WIDE_INT count = XVECLEN (op, 0);
4688 HOST_WIDE_INT i = 1, base = 0;
4692 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4695 /* Check to see if this might be a write-back. */
4696 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4701 /* Now check it more carefully. */
4702 if (GET_CODE (SET_DEST (elt)) != REG
4703 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4704 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4705 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4709 /* Perform a quick check so we don't blow up below. */
4711 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4712 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
4713 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
4716 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
4717 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
4719 for (; i < count; i++)
4721 elt = XVECEXP (op, 0, i);
4723 if (GET_CODE (elt) != SET
4724 || GET_CODE (SET_SRC (elt)) != REG
4725 || GET_MODE (SET_SRC (elt)) != SImode
4726 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
4727 || GET_CODE (SET_DEST (elt)) != MEM
4728 || GET_MODE (SET_DEST (elt)) != SImode
4729 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
4730 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
4731 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
4732 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
4740 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
4741 HOST_WIDE_INT *load_offset)
4743 int unsorted_regs[4];
4744 HOST_WIDE_INT unsorted_offsets[4];
4749 /* Can only handle 2, 3, or 4 insns at present,
4750 though could be easily extended if required. */
4751 if (nops < 2 || nops > 4)
4754 /* Loop over the operands and check that the memory references are
4755 suitable (ie immediate offsets from the same base register). At
4756 the same time, extract the target register, and the memory
4758 for (i = 0; i < nops; i++)
4763 /* Convert a subreg of a mem into the mem itself. */
4764 if (GET_CODE (operands[nops + i]) == SUBREG)
4765 operands[nops + i] = alter_subreg (operands + (nops + i));
4767 if (GET_CODE (operands[nops + i]) != MEM)
4770 /* Don't reorder volatile memory references; it doesn't seem worth
4771 looking for the case where the order is ok anyway. */
4772 if (MEM_VOLATILE_P (operands[nops + i]))
4775 offset = const0_rtx;
4777 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4778 || (GET_CODE (reg) == SUBREG
4779 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4780 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4781 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4783 || (GET_CODE (reg) == SUBREG
4784 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4785 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4790 base_reg = REGNO (reg);
4791 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4792 ? REGNO (operands[i])
4793 : REGNO (SUBREG_REG (operands[i])));
4798 if (base_reg != (int) REGNO (reg))
4799 /* Not addressed from the same base register. */
4802 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
4803 ? REGNO (operands[i])
4804 : REGNO (SUBREG_REG (operands[i])));
4805 if (unsorted_regs[i] < unsorted_regs[order[0]])
4809 /* If it isn't an integer register, or if it overwrites the
4810 base register but isn't the last insn in the list, then
4811 we can't do this. */
4812 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
4813 || (i != nops - 1 && unsorted_regs[i] == base_reg))
4816 unsorted_offsets[i] = INTVAL (offset);
4819 /* Not a suitable memory address. */
4823 /* All the useful information has now been extracted from the
4824 operands into unsorted_regs and unsorted_offsets; additionally,
4825 order[0] has been set to the lowest numbered register in the
4826 list. Sort the registers into order, and check that the memory
4827 offsets are ascending and adjacent. */
4829 for (i = 1; i < nops; i++)
4833 order[i] = order[i - 1];
4834 for (j = 0; j < nops; j++)
4835 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4836 && (order[i] == order[i - 1]
4837 || unsorted_regs[j] < unsorted_regs[order[i]]))
4840 /* Have we found a suitable register? if not, one must be used more
4842 if (order[i] == order[i - 1])
4845 /* Is the memory address adjacent and ascending? */
4846 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4854 for (i = 0; i < nops; i++)
4855 regs[i] = unsorted_regs[order[i]];
4857 *load_offset = unsorted_offsets[order[0]];
4860 if (unsorted_offsets[order[0]] == 0)
4861 return 1; /* ldmia */
4863 if (unsorted_offsets[order[0]] == 4)
4864 return 2; /* ldmib */
4866 if (unsorted_offsets[order[nops - 1]] == 0)
4867 return 3; /* ldmda */
4869 if (unsorted_offsets[order[nops - 1]] == -4)
4870 return 4; /* ldmdb */
4872 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4873 if the offset isn't small enough. The reason 2 ldrs are faster
4874 is because these ARMs are able to do more than one cache access
4875 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4876 whilst the ARM8 has a double bandwidth cache. This means that
4877 these cores can do both an instruction fetch and a data fetch in
4878 a single cycle, so the trick of calculating the address into a
4879 scratch register (one of the result regs) and then doing a load
4880 multiple actually becomes slower (and no smaller in code size).
4881 That is the transformation
4883 ldr rd1, [rbase + offset]
4884 ldr rd2, [rbase + offset + 4]
4888 add rd1, rbase, offset
4889 ldmia rd1, {rd1, rd2}
4891 produces worse code -- '3 cycles + any stalls on rd2' instead of
4892 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4893 access per cycle, the first sequence could never complete in less
4894 than 6 cycles, whereas the ldm sequence would only take 5 and
4895 would make better use of sequential accesses if not hitting the
4898 We cheat here and test 'arm_ld_sched' which we currently know to
4899 only be true for the ARM8, ARM9 and StrongARM. If this ever
4900 changes, then the test below needs to be reworked. */
4901 if (nops == 2 && arm_ld_sched)
4904 /* Can't do it without setting up the offset, only do this if it takes
4905 no more than one insn. */
4906 return (const_ok_for_arm (unsorted_offsets[order[0]])
4907 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
4911 emit_ldm_seq (rtx *operands, int nops)
4915 HOST_WIDE_INT offset;
4919 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4922 strcpy (buf, "ldm%?ia\t");
4926 strcpy (buf, "ldm%?ib\t");
4930 strcpy (buf, "ldm%?da\t");
4934 strcpy (buf, "ldm%?db\t");
4939 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4940 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4943 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4944 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4946 output_asm_insn (buf, operands);
4948 strcpy (buf, "ldm%?ia\t");
4955 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4956 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4958 for (i = 1; i < nops; i++)
4959 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4960 reg_names[regs[i]]);
4962 strcat (buf, "}\t%@ phole ldm");
4964 output_asm_insn (buf, operands);
4969 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
4970 HOST_WIDE_INT * load_offset)
4972 int unsorted_regs[4];
4973 HOST_WIDE_INT unsorted_offsets[4];
4978 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4979 extended if required. */
4980 if (nops < 2 || nops > 4)
4983 /* Loop over the operands and check that the memory references are
4984 suitable (ie immediate offsets from the same base register). At
4985 the same time, extract the target register, and the memory
4987 for (i = 0; i < nops; i++)
4992 /* Convert a subreg of a mem into the mem itself. */
4993 if (GET_CODE (operands[nops + i]) == SUBREG)
4994 operands[nops + i] = alter_subreg (operands + (nops + i));
4996 if (GET_CODE (operands[nops + i]) != MEM)
4999 /* Don't reorder volatile memory references; it doesn't seem worth
5000 looking for the case where the order is ok anyway. */
5001 if (MEM_VOLATILE_P (operands[nops + i]))
5004 offset = const0_rtx;
5006 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5007 || (GET_CODE (reg) == SUBREG
5008 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5009 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5010 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5012 || (GET_CODE (reg) == SUBREG
5013 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5014 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5019 base_reg = REGNO (reg);
5020 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5021 ? REGNO (operands[i])
5022 : REGNO (SUBREG_REG (operands[i])));
5027 if (base_reg != (int) REGNO (reg))
5028 /* Not addressed from the same base register. */
5031 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5032 ? REGNO (operands[i])
5033 : REGNO (SUBREG_REG (operands[i])));
5034 if (unsorted_regs[i] < unsorted_regs[order[0]])
5038 /* If it isn't an integer register, then we can't do this. */
5039 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5042 unsorted_offsets[i] = INTVAL (offset);
5045 /* Not a suitable memory address. */
5049 /* All the useful information has now been extracted from the
5050 operands into unsorted_regs and unsorted_offsets; additionally,
5051 order[0] has been set to the lowest numbered register in the
5052 list. Sort the registers into order, and check that the memory
5053 offsets are ascending and adjacent. */
5055 for (i = 1; i < nops; i++)
5059 order[i] = order[i - 1];
5060 for (j = 0; j < nops; j++)
5061 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5062 && (order[i] == order[i - 1]
5063 || unsorted_regs[j] < unsorted_regs[order[i]]))
5066 /* Have we found a suitable register? if not, one must be used more
5068 if (order[i] == order[i - 1])
5071 /* Is the memory address adjacent and ascending? */
5072 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5080 for (i = 0; i < nops; i++)
5081 regs[i] = unsorted_regs[order[i]];
5083 *load_offset = unsorted_offsets[order[0]];
5086 if (unsorted_offsets[order[0]] == 0)
5087 return 1; /* stmia */
5089 if (unsorted_offsets[order[0]] == 4)
5090 return 2; /* stmib */
5092 if (unsorted_offsets[order[nops - 1]] == 0)
5093 return 3; /* stmda */
5095 if (unsorted_offsets[order[nops - 1]] == -4)
5096 return 4; /* stmdb */
5102 emit_stm_seq (rtx *operands, int nops)
5106 HOST_WIDE_INT offset;
5110 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5113 strcpy (buf, "stm%?ia\t");
5117 strcpy (buf, "stm%?ib\t");
5121 strcpy (buf, "stm%?da\t");
5125 strcpy (buf, "stm%?db\t");
5132 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5133 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5135 for (i = 1; i < nops; i++)
5136 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5137 reg_names[regs[i]]);
5139 strcat (buf, "}\t%@ phole stm");
5141 output_asm_insn (buf, operands);
5146 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5148 if (GET_CODE (op) != PARALLEL
5149 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5150 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5151 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5157 /* Routines for use in generating RTL. */
5160 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5161 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5163 HOST_WIDE_INT offset = *offsetp;
5166 int sign = up ? 1 : -1;
5169 /* XScale has load-store double instructions, but they have stricter
5170 alignment requirements than load-store multiple, so we can not
5173 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5174 the pipeline until completion.
5182 An ldr instruction takes 1-3 cycles, but does not block the
5191 Best case ldr will always win. However, the more ldr instructions
5192 we issue, the less likely we are to be able to schedule them well.
5193 Using ldr instructions also increases code size.
5195 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5196 for counts of 3 or 4 regs. */
5197 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5203 for (i = 0; i < count; i++)
5205 addr = plus_constant (from, i * 4 * sign);
5206 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5207 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5213 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5223 result = gen_rtx_PARALLEL (VOIDmode,
5224 rtvec_alloc (count + (write_back ? 1 : 0)));
5227 XVECEXP (result, 0, 0)
5228 = gen_rtx_SET (GET_MODE (from), from,
5229 plus_constant (from, count * 4 * sign));
5234 for (j = 0; i < count; i++, j++)
5236 addr = plus_constant (from, j * 4 * sign);
5237 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5238 XVECEXP (result, 0, i)
5239 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5250 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5251 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
5253 HOST_WIDE_INT offset = *offsetp;
5256 int sign = up ? 1 : -1;
5259 /* See arm_gen_load_multiple for discussion of
5260 the pros/cons of ldm/stm usage for XScale. */
5261 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5267 for (i = 0; i < count; i++)
5269 addr = plus_constant (to, i * 4 * sign);
5270 mem = adjust_automodify_address (basemem, SImode, addr, offset);
5271 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5277 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5287 result = gen_rtx_PARALLEL (VOIDmode,
5288 rtvec_alloc (count + (write_back ? 1 : 0)));
5291 XVECEXP (result, 0, 0)
5292 = gen_rtx_SET (GET_MODE (to), to,
5293 plus_constant (to, count * 4 * sign));
5298 for (j = 0; i < count; i++, j++)
5300 addr = plus_constant (to, j * 4 * sign);
5301 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
5302 XVECEXP (result, 0, i)
5303 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5314 arm_gen_movstrqi (rtx *operands)
5316 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5317 HOST_WIDE_INT srcoffset, dstoffset;
5319 rtx src, dst, srcbase, dstbase;
5320 rtx part_bytes_reg = NULL;
5323 if (GET_CODE (operands[2]) != CONST_INT
5324 || GET_CODE (operands[3]) != CONST_INT
5325 || INTVAL (operands[2]) > 64
5326 || INTVAL (operands[3]) & 3)
5329 dstbase = operands[0];
5330 srcbase = operands[1];
5332 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
5333 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
5335 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5336 out_words_to_go = INTVAL (operands[2]) / 4;
5337 last_bytes = INTVAL (operands[2]) & 3;
5338 dstoffset = srcoffset = 0;
5340 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5341 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5343 for (i = 0; in_words_to_go >= 2; i+=4)
5345 if (in_words_to_go > 4)
5346 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5347 srcbase, &srcoffset));
5349 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5350 FALSE, srcbase, &srcoffset));
5352 if (out_words_to_go)
5354 if (out_words_to_go > 4)
5355 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5356 dstbase, &dstoffset));
5358 else if (out_words_to_go != 1)
5359 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5363 dstbase, &dstoffset));
5366 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
5367 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5368 if (last_bytes != 0)
5370 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5376 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5377 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5380 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5381 if (out_words_to_go)
5385 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
5386 sreg = copy_to_reg (mem);
5388 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
5389 emit_move_insn (mem, sreg);
5392 if (in_words_to_go) /* Sanity check */
5398 if (in_words_to_go < 0)
5401 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
5402 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5405 if (last_bytes && part_bytes_reg == NULL)
5408 if (BYTES_BIG_ENDIAN && last_bytes)
5410 rtx tmp = gen_reg_rtx (SImode);
5412 /* The bytes we want are in the top end of the word. */
5413 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
5414 GEN_INT (8 * (4 - last_bytes))));
5415 part_bytes_reg = tmp;
5419 mem = adjust_automodify_address (dstbase, QImode,
5420 plus_constant (dst, last_bytes - 1),
5421 dstoffset + last_bytes - 1);
5422 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5426 tmp = gen_reg_rtx (SImode);
5427 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
5428 part_bytes_reg = tmp;
5437 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
5438 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
5442 rtx tmp = gen_reg_rtx (SImode);
5444 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
5445 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
5446 part_bytes_reg = tmp;
5453 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
5454 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5461 /* Generate a memory reference for a half word, such that it will be loaded
5462 into the top 16 bits of the word. We can assume that the address is
5463 known to be alignable and of the form reg, or plus (reg, const). */
5466 arm_gen_rotated_half_load (rtx memref)
5468 HOST_WIDE_INT offset = 0;
5469 rtx base = XEXP (memref, 0);
5471 if (GET_CODE (base) == PLUS)
5473 offset = INTVAL (XEXP (base, 1));
5474 base = XEXP (base, 0);
5477 /* If we aren't allowed to generate unaligned addresses, then fail. */
5478 if (TARGET_MMU_TRAPS
5479 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
5482 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
5484 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
5487 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
5490 /* Select a dominance comparison mode if possible for a test of the general
5491 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5492 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5493 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5494 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5495 In all cases OP will be either EQ or NE, but we don't need to know which
5496 here. If we are unable to support a dominance comparison we return
5497 CC mode. This will then fail to match for the RTL expressions that
5498 generate this call. */
5500 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
5502 enum rtx_code cond1, cond2;
5505 /* Currently we will probably get the wrong result if the individual
5506 comparisons are not simple. This also ensures that it is safe to
5507 reverse a comparison if necessary. */
5508 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
5510 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
5514 /* The if_then_else variant of this tests the second condition if the
5515 first passes, but is true if the first fails. Reverse the first
5516 condition to get a true "inclusive-or" expression. */
5517 if (cond_or == DOM_CC_NX_OR_Y)
5518 cond1 = reverse_condition (cond1);
5520 /* If the comparisons are not equal, and one doesn't dominate the other,
5521 then we can't do this. */
5523 && !comparison_dominates_p (cond1, cond2)
5524 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
5529 enum rtx_code temp = cond1;
5537 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
5542 case LE: return CC_DLEmode;
5543 case LEU: return CC_DLEUmode;
5544 case GE: return CC_DGEmode;
5545 case GEU: return CC_DGEUmode;
5552 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
5561 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
5570 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
5579 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
5587 /* The remaining cases only occur when both comparisons are the
5612 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
5614 /* All floating point compares return CCFP if it is an equality
5615 comparison, and CCFPE otherwise. */
5616 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5645 /* A compare with a shifted operand. Because of canonicalization, the
5646 comparison will have to be swapped when we emit the assembler. */
5647 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
5648 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5649 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
5650 || GET_CODE (x) == ROTATERT))
5653 /* This is a special case that is used by combine to allow a
5654 comparison of a shifted byte load to be split into a zero-extend
5655 followed by a comparison of the shifted integer (only valid for
5656 equalities and unsigned inequalities). */
5657 if (GET_MODE (x) == SImode
5658 && GET_CODE (x) == ASHIFT
5659 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
5660 && GET_CODE (XEXP (x, 0)) == SUBREG
5661 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
5662 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
5663 && (op == EQ || op == NE
5664 || op == GEU || op == GTU || op == LTU || op == LEU)
5665 && GET_CODE (y) == CONST_INT)
5668 /* A construct for a conditional compare, if the false arm contains
5669 0, then both conditions must be true, otherwise either condition
5670 must be true. Not all conditions are possible, so CCmode is
5671 returned if it can't be done. */
5672 if (GET_CODE (x) == IF_THEN_ELSE
5673 && (XEXP (x, 2) == const0_rtx
5674 || XEXP (x, 2) == const1_rtx)
5675 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5676 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5677 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5678 INTVAL (XEXP (x, 2)));
5680 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5681 if (GET_CODE (x) == AND
5682 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5683 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5684 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5687 if (GET_CODE (x) == IOR
5688 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5689 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5690 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5693 /* An operation (on Thumb) where we want to test for a single bit.
5694 This is done by shifting that bit up into the top bit of a
5695 scratch register; we can then branch on the sign bit. */
5697 && GET_MODE (x) == SImode
5698 && (op == EQ || op == NE)
5699 && (GET_CODE (x) == ZERO_EXTRACT))
5702 /* An operation that sets the condition codes as a side-effect, the
5703 V flag is not set correctly, so we can only use comparisons where
5704 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5706 if (GET_MODE (x) == SImode
5708 && (op == EQ || op == NE || op == LT || op == GE)
5709 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
5710 || GET_CODE (x) == AND || GET_CODE (x) == IOR
5711 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
5712 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
5713 || GET_CODE (x) == LSHIFTRT
5714 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5715 || GET_CODE (x) == ROTATERT
5716 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
5719 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
5722 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
5723 && GET_CODE (x) == PLUS
5724 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
5730 /* X and Y are two things to compare using CODE. Emit the compare insn and
5731 return the rtx for register 0 in the proper mode. FP means this is a
5732 floating point compare: I don't think that it is needed on the arm. */
5734 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
5736 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
5737 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
5739 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5740 gen_rtx_COMPARE (mode, x, y)));
5745 /* Generate a sequence of insns that will generate the correct return
5746 address mask depending on the physical architecture that the program
5749 arm_gen_return_addr_mask (void)
5751 rtx reg = gen_reg_rtx (Pmode);
5753 emit_insn (gen_return_addr_mask (reg));
5758 arm_reload_in_hi (rtx *operands)
5760 rtx ref = operands[1];
5762 HOST_WIDE_INT offset = 0;
5764 if (GET_CODE (ref) == SUBREG)
5766 offset = SUBREG_BYTE (ref);
5767 ref = SUBREG_REG (ref);
5770 if (GET_CODE (ref) == REG)
5772 /* We have a pseudo which has been spilt onto the stack; there
5773 are two cases here: the first where there is a simple
5774 stack-slot replacement and a second where the stack-slot is
5775 out of range, or is used as a subreg. */
5776 if (reg_equiv_mem[REGNO (ref)])
5778 ref = reg_equiv_mem[REGNO (ref)];
5779 base = find_replacement (&XEXP (ref, 0));
5782 /* The slot is out of range, or was dressed up in a SUBREG. */
5783 base = reg_equiv_address[REGNO (ref)];
5786 base = find_replacement (&XEXP (ref, 0));
5788 /* Handle the case where the address is too complex to be offset by 1. */
5789 if (GET_CODE (base) == MINUS
5790 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5792 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5794 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5797 else if (GET_CODE (base) == PLUS)
5799 /* The addend must be CONST_INT, or we would have dealt with it above. */
5800 HOST_WIDE_INT hi, lo;
5802 offset += INTVAL (XEXP (base, 1));
5803 base = XEXP (base, 0);
5805 /* Rework the address into a legal sequence of insns. */
5806 /* Valid range for lo is -4095 -> 4095 */
5809 : -((-offset) & 0xfff));
5811 /* Corner case, if lo is the max offset then we would be out of range
5812 once we have added the additional 1 below, so bump the msb into the
5813 pre-loading insn(s). */
5817 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5818 ^ (HOST_WIDE_INT) 0x80000000)
5819 - (HOST_WIDE_INT) 0x80000000);
5821 if (hi + lo != offset)
5826 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5828 /* Get the base address; addsi3 knows how to handle constants
5829 that require more than one insn. */
5830 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5836 /* Operands[2] may overlap operands[0] (though it won't overlap
5837 operands[1]), that's why we asked for a DImode reg -- so we can
5838 use the bit that does not overlap. */
5839 if (REGNO (operands[2]) == REGNO (operands[0]))
5840 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5842 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5844 emit_insn (gen_zero_extendqisi2 (scratch,
5845 gen_rtx_MEM (QImode,
5846 plus_constant (base,
5848 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
5849 gen_rtx_MEM (QImode,
5850 plus_constant (base,
5852 if (!BYTES_BIG_ENDIAN)
5853 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5854 gen_rtx_IOR (SImode,
5857 gen_rtx_SUBREG (SImode, operands[0], 0),
5861 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5862 gen_rtx_IOR (SImode,
5863 gen_rtx_ASHIFT (SImode, scratch,
5865 gen_rtx_SUBREG (SImode, operands[0],
5869 /* Handle storing a half-word to memory during reload by synthesizing as two
5870 byte stores. Take care not to clobber the input values until after we
5871 have moved them somewhere safe. This code assumes that if the DImode
5872 scratch in operands[2] overlaps either the input value or output address
5873 in some way, then that value must die in this insn (we absolutely need
5874 two scratch registers for some corner cases). */
5876 arm_reload_out_hi (rtx *operands)
5878 rtx ref = operands[0];
5879 rtx outval = operands[1];
5881 HOST_WIDE_INT offset = 0;
5883 if (GET_CODE (ref) == SUBREG)
5885 offset = SUBREG_BYTE (ref);
5886 ref = SUBREG_REG (ref);
5889 if (GET_CODE (ref) == REG)
5891 /* We have a pseudo which has been spilt onto the stack; there
5892 are two cases here: the first where there is a simple
5893 stack-slot replacement and a second where the stack-slot is
5894 out of range, or is used as a subreg. */
5895 if (reg_equiv_mem[REGNO (ref)])
5897 ref = reg_equiv_mem[REGNO (ref)];
5898 base = find_replacement (&XEXP (ref, 0));
5901 /* The slot is out of range, or was dressed up in a SUBREG. */
5902 base = reg_equiv_address[REGNO (ref)];
5905 base = find_replacement (&XEXP (ref, 0));
5907 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5909 /* Handle the case where the address is too complex to be offset by 1. */
5910 if (GET_CODE (base) == MINUS
5911 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5913 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5915 /* Be careful not to destroy OUTVAL. */
5916 if (reg_overlap_mentioned_p (base_plus, outval))
5918 /* Updating base_plus might destroy outval, see if we can
5919 swap the scratch and base_plus. */
5920 if (!reg_overlap_mentioned_p (scratch, outval))
5923 scratch = base_plus;
5928 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5930 /* Be conservative and copy OUTVAL into the scratch now,
5931 this should only be necessary if outval is a subreg
5932 of something larger than a word. */
5933 /* XXX Might this clobber base? I can't see how it can,
5934 since scratch is known to overlap with OUTVAL, and
5935 must be wider than a word. */
5936 emit_insn (gen_movhi (scratch_hi, outval));
5937 outval = scratch_hi;
5941 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5944 else if (GET_CODE (base) == PLUS)
5946 /* The addend must be CONST_INT, or we would have dealt with it above. */
5947 HOST_WIDE_INT hi, lo;
5949 offset += INTVAL (XEXP (base, 1));
5950 base = XEXP (base, 0);
5952 /* Rework the address into a legal sequence of insns. */
5953 /* Valid range for lo is -4095 -> 4095 */
5956 : -((-offset) & 0xfff));
5958 /* Corner case, if lo is the max offset then we would be out of range
5959 once we have added the additional 1 below, so bump the msb into the
5960 pre-loading insn(s). */
5964 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5965 ^ (HOST_WIDE_INT) 0x80000000)
5966 - (HOST_WIDE_INT) 0x80000000);
5968 if (hi + lo != offset)
5973 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5975 /* Be careful not to destroy OUTVAL. */
5976 if (reg_overlap_mentioned_p (base_plus, outval))
5978 /* Updating base_plus might destroy outval, see if we
5979 can swap the scratch and base_plus. */
5980 if (!reg_overlap_mentioned_p (scratch, outval))
5983 scratch = base_plus;
5988 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5990 /* Be conservative and copy outval into scratch now,
5991 this should only be necessary if outval is a
5992 subreg of something larger than a word. */
5993 /* XXX Might this clobber base? I can't see how it
5994 can, since scratch is known to overlap with
5996 emit_insn (gen_movhi (scratch_hi, outval));
5997 outval = scratch_hi;
6001 /* Get the base address; addsi3 knows how to handle constants
6002 that require more than one insn. */
6003 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6009 if (BYTES_BIG_ENDIAN)
6011 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6012 plus_constant (base, offset + 1)),
6013 gen_lowpart (QImode, outval)));
6014 emit_insn (gen_lshrsi3 (scratch,
6015 gen_rtx_SUBREG (SImode, outval, 0),
6017 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6018 gen_lowpart (QImode, scratch)));
6022 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6023 gen_lowpart (QImode, outval)));
6024 emit_insn (gen_lshrsi3 (scratch,
6025 gen_rtx_SUBREG (SImode, outval, 0),
6027 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6028 plus_constant (base, offset + 1)),
6029 gen_lowpart (QImode, scratch)));
6033 /* Print a symbolic form of X to the debug file, F. */
6035 arm_print_value (FILE *f, rtx x)
6037 switch (GET_CODE (x))
6040 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6044 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6052 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6054 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6055 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6063 fprintf (f, "\"%s\"", XSTR (x, 0));
6067 fprintf (f, "`%s'", XSTR (x, 0));
6071 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6075 arm_print_value (f, XEXP (x, 0));
6079 arm_print_value (f, XEXP (x, 0));
6081 arm_print_value (f, XEXP (x, 1));
6089 fprintf (f, "????");
6094 /* Routines for manipulation of the constant pool. */
6096 /* Arm instructions cannot load a large constant directly into a
6097 register; they have to come from a pc relative load. The constant
6098 must therefore be placed in the addressable range of the pc
6099 relative load. Depending on the precise pc relative load
6100 instruction the range is somewhere between 256 bytes and 4k. This
6101 means that we often have to dump a constant inside a function, and
6102 generate code to branch around it.
6104 It is important to minimize this, since the branches will slow
6105 things down and make the code larger.
6107 Normally we can hide the table after an existing unconditional
6108 branch so that there is no interruption of the flow, but in the
6109 worst case the code looks like this:
6127 We fix this by performing a scan after scheduling, which notices
6128 which instructions need to have their operands fetched from the
6129 constant table and builds the table.
6131 The algorithm starts by building a table of all the constants that
6132 need fixing up and all the natural barriers in the function (places
6133 where a constant table can be dropped without breaking the flow).
6134 For each fixup we note how far the pc-relative replacement will be
6135 able to reach and the offset of the instruction into the function.
6137 Having built the table we then group the fixes together to form
6138 tables that are as large as possible (subject to addressing
6139 constraints) and emit each table of constants after the last
6140 barrier that is within range of all the instructions in the group.
6141 If a group does not contain a barrier, then we forcibly create one
6142 by inserting a jump instruction into the flow. Once the table has
6143 been inserted, the insns are then modified to reference the
6144 relevant entry in the pool.
6146 Possible enhancements to the algorithm (not implemented) are:
6148 1) For some processors and object formats, there may be benefit in
6149 aligning the pools to the start of cache lines; this alignment
6150 would need to be taken into account when calculating addressability
6153 /* These typedefs are located at the start of this file, so that
6154 they can be used in the prototypes there. This comment is to
6155 remind readers of that fact so that the following structures
6156 can be understood more easily.
6158 typedef struct minipool_node Mnode;
6159 typedef struct minipool_fixup Mfix; */
6161 struct minipool_node
6163 /* Doubly linked chain of entries. */
6166 /* The maximum offset into the code that this entry can be placed. While
6167 pushing fixes for forward references, all entries are sorted in order
6168 of increasing max_address. */
6169 HOST_WIDE_INT max_address;
6170 /* Similarly for an entry inserted for a backwards ref. */
6171 HOST_WIDE_INT min_address;
6172 /* The number of fixes referencing this entry. This can become zero
6173 if we "unpush" an entry. In this case we ignore the entry when we
6174 come to emit the code. */
6176 /* The offset from the start of the minipool. */
6177 HOST_WIDE_INT offset;
6178 /* The value in table. */
6180 /* The mode of value. */
6181 enum machine_mode mode;
6182 /* The size of the value. With iWMMXt enabled
6183 sizes > 4 also imply an alignment of 8-bytes. */
6187 struct minipool_fixup
6191 HOST_WIDE_INT address;
6193 enum machine_mode mode;
6197 HOST_WIDE_INT forwards;
6198 HOST_WIDE_INT backwards;
6201 /* Fixes less than a word need padding out to a word boundary. */
6202 #define MINIPOOL_FIX_SIZE(mode) \
6203 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6205 static Mnode * minipool_vector_head;
6206 static Mnode * minipool_vector_tail;
6207 static rtx minipool_vector_label;
6209 /* The linked list of all minipool fixes required for this function. */
6210 Mfix * minipool_fix_head;
6211 Mfix * minipool_fix_tail;
6212 /* The fix entry for the current minipool, once it has been placed. */
6213 Mfix * minipool_barrier;
6215 /* Determines if INSN is the start of a jump table. Returns the end
6216 of the TABLE or NULL_RTX. */
6218 is_jump_table (rtx insn)
6222 if (GET_CODE (insn) == JUMP_INSN
6223 && JUMP_LABEL (insn) != NULL
6224 && ((table = next_real_insn (JUMP_LABEL (insn)))
6225 == next_real_insn (insn))
6227 && GET_CODE (table) == JUMP_INSN
6228 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6229 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6235 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6236 #define JUMP_TABLES_IN_TEXT_SECTION 0
6239 static HOST_WIDE_INT
6240 get_jump_table_size (rtx insn)
6242 /* ADDR_VECs only take room if read-only data does into the text
6244 if (JUMP_TABLES_IN_TEXT_SECTION
6245 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6250 rtx body = PATTERN (insn);
6251 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6253 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6259 /* Move a minipool fix MP from its current location to before MAX_MP.
6260 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6261 constraints may need updating. */
6263 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6264 HOST_WIDE_INT max_address)
6266 /* This should never be true and the code below assumes these are
6273 if (max_address < mp->max_address)
6274 mp->max_address = max_address;
6278 if (max_address > max_mp->max_address - mp->fix_size)
6279 mp->max_address = max_mp->max_address - mp->fix_size;
6281 mp->max_address = max_address;
6283 /* Unlink MP from its current position. Since max_mp is non-null,
6284 mp->prev must be non-null. */
6285 mp->prev->next = mp->next;
6286 if (mp->next != NULL)
6287 mp->next->prev = mp->prev;
6289 minipool_vector_tail = mp->prev;
6291 /* Re-insert it before MAX_MP. */
6293 mp->prev = max_mp->prev;
6296 if (mp->prev != NULL)
6297 mp->prev->next = mp;
6299 minipool_vector_head = mp;
6302 /* Save the new entry. */
6305 /* Scan over the preceding entries and adjust their addresses as
6307 while (mp->prev != NULL
6308 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6310 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6317 /* Add a constant to the minipool for a forward reference. Returns the
6318 node added or NULL if the constant will not fit in this pool. */
6320 add_minipool_forward_ref (Mfix *fix)
6322 /* If set, max_mp is the first pool_entry that has a lower
6323 constraint than the one we are trying to add. */
6324 Mnode * max_mp = NULL;
6325 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6328 /* If this fix's address is greater than the address of the first
6329 entry, then we can't put the fix in this pool. We subtract the
6330 size of the current fix to ensure that if the table is fully
6331 packed we still have enough room to insert this value by suffling
6332 the other fixes forwards. */
6333 if (minipool_vector_head &&
6334 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6337 /* Scan the pool to see if a constant with the same value has
6338 already been added. While we are doing this, also note the
6339 location where we must insert the constant if it doesn't already
6341 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6343 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6344 && fix->mode == mp->mode
6345 && (GET_CODE (fix->value) != CODE_LABEL
6346 || (CODE_LABEL_NUMBER (fix->value)
6347 == CODE_LABEL_NUMBER (mp->value)))
6348 && rtx_equal_p (fix->value, mp->value))
6350 /* More than one fix references this entry. */
6352 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6355 /* Note the insertion point if necessary. */
6357 && mp->max_address > max_address)
6360 /* If we are inserting an 8-bytes aligned quantity and
6361 we have not already found an insertion point, then
6362 make sure that all such 8-byte aligned quantities are
6363 placed at the start of the pool. */
6364 if (TARGET_REALLY_IWMMXT
6366 && fix->fix_size == 8
6367 && mp->fix_size != 8)
6370 max_address = mp->max_address;
6374 /* The value is not currently in the minipool, so we need to create
6375 a new entry for it. If MAX_MP is NULL, the entry will be put on
6376 the end of the list since the placement is less constrained than
6377 any existing entry. Otherwise, we insert the new fix before
6378 MAX_MP and, if necessary, adjust the constraints on the other
6380 mp = xmalloc (sizeof (* mp));
6381 mp->fix_size = fix->fix_size;
6382 mp->mode = fix->mode;
6383 mp->value = fix->value;
6385 /* Not yet required for a backwards ref. */
6386 mp->min_address = -65536;
6390 mp->max_address = max_address;
6392 mp->prev = minipool_vector_tail;
6394 if (mp->prev == NULL)
6396 minipool_vector_head = mp;
6397 minipool_vector_label = gen_label_rtx ();
6400 mp->prev->next = mp;
6402 minipool_vector_tail = mp;
6406 if (max_address > max_mp->max_address - mp->fix_size)
6407 mp->max_address = max_mp->max_address - mp->fix_size;
6409 mp->max_address = max_address;
6412 mp->prev = max_mp->prev;
6414 if (mp->prev != NULL)
6415 mp->prev->next = mp;
6417 minipool_vector_head = mp;
6420 /* Save the new entry. */
6423 /* Scan over the preceding entries and adjust their addresses as
6425 while (mp->prev != NULL
6426 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6428 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6436 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
6437 HOST_WIDE_INT min_address)
6439 HOST_WIDE_INT offset;
6441 /* This should never be true, and the code below assumes these are
6448 if (min_address > mp->min_address)
6449 mp->min_address = min_address;
6453 /* We will adjust this below if it is too loose. */
6454 mp->min_address = min_address;
6456 /* Unlink MP from its current position. Since min_mp is non-null,
6457 mp->next must be non-null. */
6458 mp->next->prev = mp->prev;
6459 if (mp->prev != NULL)
6460 mp->prev->next = mp->next;
6462 minipool_vector_head = mp->next;
6464 /* Reinsert it after MIN_MP. */
6466 mp->next = min_mp->next;
6468 if (mp->next != NULL)
6469 mp->next->prev = mp;
6471 minipool_vector_tail = mp;
6477 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6479 mp->offset = offset;
6480 if (mp->refcount > 0)
6481 offset += mp->fix_size;
6483 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
6484 mp->next->min_address = mp->min_address + mp->fix_size;
6490 /* Add a constant to the minipool for a backward reference. Returns the
6491 node added or NULL if the constant will not fit in this pool.
6493 Note that the code for insertion for a backwards reference can be
6494 somewhat confusing because the calculated offsets for each fix do
6495 not take into account the size of the pool (which is still under
6498 add_minipool_backward_ref (Mfix *fix)
6500 /* If set, min_mp is the last pool_entry that has a lower constraint
6501 than the one we are trying to add. */
6502 Mnode *min_mp = NULL;
6503 /* This can be negative, since it is only a constraint. */
6504 HOST_WIDE_INT min_address = fix->address - fix->backwards;
6507 /* If we can't reach the current pool from this insn, or if we can't
6508 insert this entry at the end of the pool without pushing other
6509 fixes out of range, then we don't try. This ensures that we
6510 can't fail later on. */
6511 if (min_address >= minipool_barrier->address
6512 || (minipool_vector_tail->min_address + fix->fix_size
6513 >= minipool_barrier->address))
6516 /* Scan the pool to see if a constant with the same value has
6517 already been added. While we are doing this, also note the
6518 location where we must insert the constant if it doesn't already
6520 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
6522 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6523 && fix->mode == mp->mode
6524 && (GET_CODE (fix->value) != CODE_LABEL
6525 || (CODE_LABEL_NUMBER (fix->value)
6526 == CODE_LABEL_NUMBER (mp->value)))
6527 && rtx_equal_p (fix->value, mp->value)
6528 /* Check that there is enough slack to move this entry to the
6529 end of the table (this is conservative). */
6531 > (minipool_barrier->address
6532 + minipool_vector_tail->offset
6533 + minipool_vector_tail->fix_size)))
6536 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
6540 mp->min_address += fix->fix_size;
6543 /* Note the insertion point if necessary. */
6544 if (mp->min_address < min_address)
6546 /* For now, we do not allow the insertion of 8-byte alignment
6547 requiring nodes anywhere but at the start of the pool. */
6548 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8 && mp->fix_size != 8)
6553 else if (mp->max_address
6554 < minipool_barrier->address + mp->offset + fix->fix_size)
6556 /* Inserting before this entry would push the fix beyond
6557 its maximum address (which can happen if we have
6558 re-located a forwards fix); force the new fix to come
6561 min_address = mp->min_address + fix->fix_size;
6563 /* If we are inserting an 8-bytes aligned quantity and
6564 we have not already found an insertion point, then
6565 make sure that all such 8-byte aligned quantities are
6566 placed at the start of the pool. */
6567 else if (TARGET_REALLY_IWMMXT
6569 && fix->fix_size == 8
6570 && mp->fix_size < 8)
6573 min_address = mp->min_address + fix->fix_size;
6578 /* We need to create a new entry. */
6579 mp = xmalloc (sizeof (* mp));
6580 mp->fix_size = fix->fix_size;
6581 mp->mode = fix->mode;
6582 mp->value = fix->value;
6584 mp->max_address = minipool_barrier->address + 65536;
6586 mp->min_address = min_address;
6591 mp->next = minipool_vector_head;
6593 if (mp->next == NULL)
6595 minipool_vector_tail = mp;
6596 minipool_vector_label = gen_label_rtx ();
6599 mp->next->prev = mp;
6601 minipool_vector_head = mp;
6605 mp->next = min_mp->next;
6609 if (mp->next != NULL)
6610 mp->next->prev = mp;
6612 minipool_vector_tail = mp;
6615 /* Save the new entry. */
6623 /* Scan over the following entries and adjust their offsets. */
6624 while (mp->next != NULL)
6626 if (mp->next->min_address < mp->min_address + mp->fix_size)
6627 mp->next->min_address = mp->min_address + mp->fix_size;
6630 mp->next->offset = mp->offset + mp->fix_size;
6632 mp->next->offset = mp->offset;
6641 assign_minipool_offsets (Mfix *barrier)
6643 HOST_WIDE_INT offset = 0;
6646 minipool_barrier = barrier;
6648 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6650 mp->offset = offset;
6652 if (mp->refcount > 0)
6653 offset += mp->fix_size;
6657 /* Output the literal table */
6659 dump_minipool (rtx scan)
6665 if (TARGET_REALLY_IWMMXT)
6666 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6667 if (mp->refcount > 0 && mp->fix_size == 8)
6674 fprintf (rtl_dump_file,
6675 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
6676 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
6678 scan = emit_label_after (gen_label_rtx (), scan);
6679 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
6680 scan = emit_label_after (minipool_vector_label, scan);
6682 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
6684 if (mp->refcount > 0)
6688 fprintf (rtl_dump_file,
6689 ";; Offset %u, min %ld, max %ld ",
6690 (unsigned) mp->offset, (unsigned long) mp->min_address,
6691 (unsigned long) mp->max_address);
6692 arm_print_value (rtl_dump_file, mp->value);
6693 fputc ('\n', rtl_dump_file);
6696 switch (mp->fix_size)
6698 #ifdef HAVE_consttable_1
6700 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
6704 #ifdef HAVE_consttable_2
6706 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
6710 #ifdef HAVE_consttable_4
6712 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
6716 #ifdef HAVE_consttable_8
6718 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
6732 minipool_vector_head = minipool_vector_tail = NULL;
6733 scan = emit_insn_after (gen_consttable_end (), scan);
6734 scan = emit_barrier_after (scan);
6737 /* Return the cost of forcibly inserting a barrier after INSN. */
6739 arm_barrier_cost (rtx insn)
6741 /* Basing the location of the pool on the loop depth is preferable,
6742 but at the moment, the basic block information seems to be
6743 corrupt by this stage of the compilation. */
6745 rtx next = next_nonnote_insn (insn);
6747 if (next != NULL && GET_CODE (next) == CODE_LABEL)
6750 switch (GET_CODE (insn))
6753 /* It will always be better to place the table before the label, rather
6762 return base_cost - 10;
6765 return base_cost + 10;
6769 /* Find the best place in the insn stream in the range
6770 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6771 Create the barrier by inserting a jump and add a new fix entry for
6774 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
6776 HOST_WIDE_INT count = 0;
6778 rtx from = fix->insn;
6779 rtx selected = from;
6781 HOST_WIDE_INT selected_address;
6783 HOST_WIDE_INT max_count = max_address - fix->address;
6784 rtx label = gen_label_rtx ();
6786 selected_cost = arm_barrier_cost (from);
6787 selected_address = fix->address;
6789 while (from && count < max_count)
6794 /* This code shouldn't have been called if there was a natural barrier
6796 if (GET_CODE (from) == BARRIER)
6799 /* Count the length of this insn. */
6800 count += get_attr_length (from);
6802 /* If there is a jump table, add its length. */
6803 tmp = is_jump_table (from);
6806 count += get_jump_table_size (tmp);
6808 /* Jump tables aren't in a basic block, so base the cost on
6809 the dispatch insn. If we select this location, we will
6810 still put the pool after the table. */
6811 new_cost = arm_barrier_cost (from);
6813 if (count < max_count && new_cost <= selected_cost)
6816 selected_cost = new_cost;
6817 selected_address = fix->address + count;
6820 /* Continue after the dispatch table. */
6821 from = NEXT_INSN (tmp);
6825 new_cost = arm_barrier_cost (from);
6827 if (count < max_count && new_cost <= selected_cost)
6830 selected_cost = new_cost;
6831 selected_address = fix->address + count;
6834 from = NEXT_INSN (from);
6837 /* Create a new JUMP_INSN that branches around a barrier. */
6838 from = emit_jump_insn_after (gen_jump (label), selected);
6839 JUMP_LABEL (from) = label;
6840 barrier = emit_barrier_after (from);
6841 emit_label_after (label, barrier);
6843 /* Create a minipool barrier entry for the new barrier. */
6844 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
6845 new_fix->insn = barrier;
6846 new_fix->address = selected_address;
6847 new_fix->next = fix->next;
6848 fix->next = new_fix;
6853 /* Record that there is a natural barrier in the insn stream at
6856 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
6858 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6861 fix->address = address;
6864 if (minipool_fix_head != NULL)
6865 minipool_fix_tail->next = fix;
6867 minipool_fix_head = fix;
6869 minipool_fix_tail = fix;
6872 /* Record INSN, which will need fixing up to load a value from the
6873 minipool. ADDRESS is the offset of the insn since the start of the
6874 function; LOC is a pointer to the part of the insn which requires
6875 fixing; VALUE is the constant that must be loaded, which is of type
6878 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
6879 enum machine_mode mode, rtx value)
6881 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6883 #ifdef AOF_ASSEMBLER
6884 /* PIC symbol references need to be converted into offsets into the
6886 /* XXX This shouldn't be done here. */
6887 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
6888 value = aof_pic_entry (value);
6889 #endif /* AOF_ASSEMBLER */
6892 fix->address = address;
6895 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
6897 fix->forwards = get_attr_pool_range (insn);
6898 fix->backwards = get_attr_neg_pool_range (insn);
6899 fix->minipool = NULL;
6901 /* If an insn doesn't have a range defined for it, then it isn't
6902 expecting to be reworked by this code. Better to abort now than
6903 to generate duff assembly code. */
6904 if (fix->forwards == 0 && fix->backwards == 0)
6907 /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary.
6908 So there might be an empty word before the start of the pool.
6909 Hence we reduce the forward range by 4 to allow for this
6911 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8)
6916 fprintf (rtl_dump_file,
6917 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6918 GET_MODE_NAME (mode),
6919 INSN_UID (insn), (unsigned long) address,
6920 -1 * (long)fix->backwards, (long)fix->forwards);
6921 arm_print_value (rtl_dump_file, fix->value);
6922 fprintf (rtl_dump_file, "\n");
6925 /* Add it to the chain of fixes. */
6928 if (minipool_fix_head != NULL)
6929 minipool_fix_tail->next = fix;
6931 minipool_fix_head = fix;
6933 minipool_fix_tail = fix;
6936 /* Scan INSN and note any of its operands that need fixing.
6937 If DO_PUSHES is false we do not actually push any of the fixups
6938 needed. The function returns TRUE is any fixups were needed/pushed.
6939 This is used by arm_memory_load_p() which needs to know about loads
6940 of constants that will be converted into minipool loads. */
6942 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
6944 bool result = false;
6947 extract_insn (insn);
6949 if (!constrain_operands (1))
6950 fatal_insn_not_found (insn);
6952 if (recog_data.n_alternatives == 0)
6955 /* Fill in recog_op_alt with information about the constraints of this insn. */
6956 preprocess_constraints ();
6958 for (opno = 0; opno < recog_data.n_operands; opno++)
6960 /* Things we need to fix can only occur in inputs. */
6961 if (recog_data.operand_type[opno] != OP_IN)
6964 /* If this alternative is a memory reference, then any mention
6965 of constants in this alternative is really to fool reload
6966 into allowing us to accept one there. We need to fix them up
6967 now so that we output the right code. */
6968 if (recog_op_alt[opno][which_alternative].memory_ok)
6970 rtx op = recog_data.operand[opno];
6972 if (CONSTANT_P (op))
6975 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6976 recog_data.operand_mode[opno], op);
6979 else if (GET_CODE (op) == MEM
6980 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
6981 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
6985 rtx cop = avoid_constant_pool_reference (op);
6987 /* Casting the address of something to a mode narrower
6988 than a word can cause avoid_constant_pool_reference()
6989 to return the pool reference itself. That's no good to
6990 us here. Lets just hope that we can use the
6991 constant pool value directly. */
6993 cop = get_pool_constant (XEXP (op, 0));
6995 push_minipool_fix (insn, address,
6996 recog_data.operand_loc[opno],
6997 recog_data.operand_mode[opno], cop);
7008 /* Gcc puts the pool in the wrong place for ARM, since we can only
7009 load addresses a limited distance around the pc. We do some
7010 special munging to move the constant pool values to the correct
7011 point in the code. */
7016 HOST_WIDE_INT address = 0;
7019 minipool_fix_head = minipool_fix_tail = NULL;
7021 /* The first insn must always be a note, or the code below won't
7022 scan it properly. */
7023 insn = get_insns ();
7024 if (GET_CODE (insn) != NOTE)
7027 /* Scan all the insns and record the operands that will need fixing. */
7028 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7030 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7031 && (arm_cirrus_insn_p (insn)
7032 || GET_CODE (insn) == JUMP_INSN
7033 || arm_memory_load_p (insn)))
7034 cirrus_reorg (insn);
7036 if (GET_CODE (insn) == BARRIER)
7037 push_minipool_barrier (insn, address);
7038 else if (INSN_P (insn))
7042 note_invalid_constants (insn, address, true);
7043 address += get_attr_length (insn);
7045 /* If the insn is a vector jump, add the size of the table
7046 and skip the table. */
7047 if ((table = is_jump_table (insn)) != NULL)
7049 address += get_jump_table_size (table);
7055 fix = minipool_fix_head;
7057 /* Now scan the fixups and perform the required changes. */
7062 Mfix * last_added_fix;
7063 Mfix * last_barrier = NULL;
7066 /* Skip any further barriers before the next fix. */
7067 while (fix && GET_CODE (fix->insn) == BARRIER)
7070 /* No more fixes. */
7074 last_added_fix = NULL;
7076 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7078 if (GET_CODE (ftmp->insn) == BARRIER)
7080 if (ftmp->address >= minipool_vector_head->max_address)
7083 last_barrier = ftmp;
7085 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7088 last_added_fix = ftmp; /* Keep track of the last fix added. */
7091 /* If we found a barrier, drop back to that; any fixes that we
7092 could have reached but come after the barrier will now go in
7093 the next mini-pool. */
7094 if (last_barrier != NULL)
7096 /* Reduce the refcount for those fixes that won't go into this
7098 for (fdel = last_barrier->next;
7099 fdel && fdel != ftmp;
7102 fdel->minipool->refcount--;
7103 fdel->minipool = NULL;
7106 ftmp = last_barrier;
7110 /* ftmp is first fix that we can't fit into this pool and
7111 there no natural barriers that we could use. Insert a
7112 new barrier in the code somewhere between the previous
7113 fix and this one, and arrange to jump around it. */
7114 HOST_WIDE_INT max_address;
7116 /* The last item on the list of fixes must be a barrier, so
7117 we can never run off the end of the list of fixes without
7118 last_barrier being set. */
7122 max_address = minipool_vector_head->max_address;
7123 /* Check that there isn't another fix that is in range that
7124 we couldn't fit into this pool because the pool was
7125 already too large: we need to put the pool before such an
7127 if (ftmp->address < max_address)
7128 max_address = ftmp->address;
7130 last_barrier = create_fix_barrier (last_added_fix, max_address);
7133 assign_minipool_offsets (last_barrier);
7137 if (GET_CODE (ftmp->insn) != BARRIER
7138 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7145 /* Scan over the fixes we have identified for this pool, fixing them
7146 up and adding the constants to the pool itself. */
7147 for (this_fix = fix; this_fix && ftmp != this_fix;
7148 this_fix = this_fix->next)
7149 if (GET_CODE (this_fix->insn) != BARRIER)
7152 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7153 minipool_vector_label),
7154 this_fix->minipool->offset);
7155 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7158 dump_minipool (last_barrier->insn);
7162 /* From now on we must synthesize any constants that we can't handle
7163 directly. This can happen if the RTL gets split during final
7164 instruction generation. */
7165 after_arm_reorg = 1;
7167 /* Free the minipool memory. */
7168 obstack_free (&minipool_obstack, minipool_startobj);
7171 /* Routines to output assembly language. */
7173 /* If the rtx is the correct value then return the string of the number.
7174 In this way we can ensure that valid double constants are generated even
7175 when cross compiling. */
7177 fp_immediate_constant (rtx x)
7182 if (!fpa_consts_inited)
7185 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7186 for (i = 0; i < 8; i++)
7187 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
7188 return strings_fpa[i];
7193 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7195 fp_const_from_val (REAL_VALUE_TYPE *r)
7199 if (!fpa_consts_inited)
7202 for (i = 0; i < 8; i++)
7203 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
7204 return strings_fpa[i];
7209 /* Output the operands of a LDM/STM instruction to STREAM.
7210 MASK is the ARM register set mask of which only bits 0-15 are important.
7211 REG is the base register, either the frame pointer or the stack pointer,
7212 INSTR is the possibly suffixed load or store instruction. */
7214 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7217 int not_first = FALSE;
7219 fputc ('\t', stream);
7220 asm_fprintf (stream, instr, reg);
7221 fputs (", {", stream);
7223 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7224 if (mask & (1 << i))
7227 fprintf (stream, ", ");
7229 asm_fprintf (stream, "%r", i);
7233 fprintf (stream, "}");
7235 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7236 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7237 Strictly speaking the instruction would be unpredicatble only if
7238 we were writing back the base register as well, but since we never
7239 want to generate an LDM type 2 instruction (register bank switching)
7240 which is what you get if the PC is not being loaded, we do not need
7241 to check for writeback. */
7242 if (! TARGET_APCS_32
7243 && ((mask & (1 << PC_REGNUM)) != 0))
7244 fprintf (stream, "^");
7246 fprintf (stream, "\n");
7249 /* Output a 'call' insn. */
7251 output_call (rtx *operands)
7253 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7255 if (REGNO (operands[0]) == LR_REGNUM)
7257 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
7258 output_asm_insn ("mov%?\t%0, %|lr", operands);
7261 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7263 if (TARGET_INTERWORK)
7264 output_asm_insn ("bx%?\t%0", operands);
7266 output_asm_insn ("mov%?\t%|pc, %0", operands);
7271 /* Output a 'call' insn that is a reference in memory. */
7273 output_call_mem (rtx *operands)
7275 if (TARGET_INTERWORK)
7277 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7278 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7279 output_asm_insn ("bx%?\t%|ip", operands);
7281 else if (regno_use_in (LR_REGNUM, operands[0]))
7283 /* LR is used in the memory address. We load the address in the
7284 first instruction. It's safe to use IP as the target of the
7285 load since the call will kill it anyway. */
7286 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7287 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7288 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
7292 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7293 output_asm_insn ("ldr%?\t%|pc, %0", operands);
7299 /* Output a move from arm registers to an fpa registers.
7300 OPERANDS[0] is an fpa register.
7301 OPERANDS[1] is the first registers of an arm register pair. */
7303 output_mov_long_double_fpa_from_arm (rtx *operands)
7305 int arm_reg0 = REGNO (operands[1]);
7308 if (arm_reg0 == IP_REGNUM)
7311 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7312 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7313 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7315 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
7316 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
7321 /* Output a move from an fpa register to arm registers.
7322 OPERANDS[0] is the first registers of an arm register pair.
7323 OPERANDS[1] is an fpa register. */
7325 output_mov_long_double_arm_from_fpa (rtx *operands)
7327 int arm_reg0 = REGNO (operands[0]);
7330 if (arm_reg0 == IP_REGNUM)
7333 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7334 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7335 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7337 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
7338 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
7342 /* Output a move from arm registers to arm registers of a long double
7343 OPERANDS[0] is the destination.
7344 OPERANDS[1] is the source. */
7346 output_mov_long_double_arm_from_arm (rtx *operands)
7348 /* We have to be careful here because the two might overlap. */
7349 int dest_start = REGNO (operands[0]);
7350 int src_start = REGNO (operands[1]);
7354 if (dest_start < src_start)
7356 for (i = 0; i < 3; i++)
7358 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7359 ops[1] = gen_rtx_REG (SImode, src_start + i);
7360 output_asm_insn ("mov%?\t%0, %1", ops);
7365 for (i = 2; i >= 0; i--)
7367 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7368 ops[1] = gen_rtx_REG (SImode, src_start + i);
7369 output_asm_insn ("mov%?\t%0, %1", ops);
7377 /* Output a move from arm registers to an fpa registers.
7378 OPERANDS[0] is an fpa register.
7379 OPERANDS[1] is the first registers of an arm register pair. */
7381 output_mov_double_fpa_from_arm (rtx *operands)
7383 int arm_reg0 = REGNO (operands[1]);
7386 if (arm_reg0 == IP_REGNUM)
7389 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7390 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7391 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
7392 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
7396 /* Output a move from an fpa register to arm registers.
7397 OPERANDS[0] is the first registers of an arm register pair.
7398 OPERANDS[1] is an fpa register. */
7400 output_mov_double_arm_from_fpa (rtx *operands)
7402 int arm_reg0 = REGNO (operands[0]);
7405 if (arm_reg0 == IP_REGNUM)
7408 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7409 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7410 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
7411 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
7415 /* Output a move between double words.
7416 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7417 or MEM<-REG and all MEMs must be offsettable addresses. */
7419 output_move_double (rtx *operands)
7421 enum rtx_code code0 = GET_CODE (operands[0]);
7422 enum rtx_code code1 = GET_CODE (operands[1]);
7427 int reg0 = REGNO (operands[0]);
7429 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
7433 int reg1 = REGNO (operands[1]);
7434 if (reg1 == IP_REGNUM)
7437 /* Ensure the second source is not overwritten. */
7438 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
7439 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
7441 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
7443 else if (code1 == CONST_VECTOR)
7445 HOST_WIDE_INT hint = 0;
7447 switch (GET_MODE (operands[1]))
7450 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
7451 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
7455 if (BYTES_BIG_ENDIAN)
7457 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7459 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7463 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7465 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7468 otherops[1] = GEN_INT (hint);
7471 if (BYTES_BIG_ENDIAN)
7473 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7475 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7479 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7481 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7484 operands[1] = GEN_INT (hint);
7488 if (BYTES_BIG_ENDIAN)
7490 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7492 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7494 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7496 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7500 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7502 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7504 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7506 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7509 otherops[1] = GEN_INT (hint);
7512 if (BYTES_BIG_ENDIAN)
7514 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7516 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7518 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7520 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7524 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7526 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7528 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7530 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7533 operands[1] = GEN_INT (hint);
7539 output_mov_immediate (operands);
7540 output_mov_immediate (otherops);
7542 else if (code1 == CONST_DOUBLE)
7544 if (GET_MODE (operands[1]) == DFmode)
7549 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
7550 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
7551 otherops[1] = GEN_INT (l[1]);
7552 operands[1] = GEN_INT (l[0]);
7554 else if (GET_MODE (operands[1]) != VOIDmode)
7556 else if (WORDS_BIG_ENDIAN)
7558 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7559 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7563 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7564 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7567 output_mov_immediate (operands);
7568 output_mov_immediate (otherops);
7570 else if (code1 == CONST_INT)
7572 #if HOST_BITS_PER_WIDE_INT > 32
7573 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7574 what the upper word is. */
7575 if (WORDS_BIG_ENDIAN)
7577 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7578 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7582 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7583 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7586 /* Sign extend the intval into the high-order word. */
7587 if (WORDS_BIG_ENDIAN)
7589 otherops[1] = operands[1];
7590 operands[1] = (INTVAL (operands[1]) < 0
7591 ? constm1_rtx : const0_rtx);
7594 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
7596 output_mov_immediate (otherops);
7597 output_mov_immediate (operands);
7599 else if (code1 == MEM)
7601 switch (GET_CODE (XEXP (operands[1], 0)))
7604 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
7608 abort (); /* Should never happen now. */
7612 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
7616 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
7620 abort (); /* Should never happen now. */
7625 output_asm_insn ("adr%?\t%0, %1", operands);
7626 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
7630 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
7631 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
7633 otherops[0] = operands[0];
7634 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
7635 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
7637 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
7639 if (GET_CODE (otherops[2]) == CONST_INT)
7641 switch ((int) INTVAL (otherops[2]))
7644 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
7647 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
7650 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
7654 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
7655 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
7657 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7660 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7663 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
7665 return "ldm%?ia\t%0, %M0";
7669 otherops[1] = adjust_address (operands[1], SImode, 4);
7670 /* Take care of overlapping base/data reg. */
7671 if (reg_mentioned_p (operands[0], operands[1]))
7673 output_asm_insn ("ldr%?\t%0, %1", otherops);
7674 output_asm_insn ("ldr%?\t%0, %1", operands);
7678 output_asm_insn ("ldr%?\t%0, %1", operands);
7679 output_asm_insn ("ldr%?\t%0, %1", otherops);
7685 abort (); /* Constraints should prevent this. */
7687 else if (code0 == MEM && code1 == REG)
7689 if (REGNO (operands[1]) == IP_REGNUM)
7692 switch (GET_CODE (XEXP (operands[0], 0)))
7695 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
7699 abort (); /* Should never happen now. */
7703 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
7707 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
7711 abort (); /* Should never happen now. */
7715 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
7717 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
7720 output_asm_insn ("stm%?db\t%m0, %M1", operands);
7724 output_asm_insn ("stm%?da\t%m0, %M1", operands);
7728 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
7735 otherops[0] = adjust_address (operands[0], SImode, 4);
7736 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
7737 output_asm_insn ("str%?\t%1, %0", operands);
7738 output_asm_insn ("str%?\t%1, %0", otherops);
7742 /* Constraints should prevent this. */
7749 /* Output an arbitrary MOV reg, #n.
7750 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
7752 output_mov_immediate (rtx *operands)
7754 HOST_WIDE_INT n = INTVAL (operands[1]);
7756 /* Try to use one MOV. */
7757 if (const_ok_for_arm (n))
7758 output_asm_insn ("mov%?\t%0, %1", operands);
7760 /* Try to use one MVN. */
7761 else if (const_ok_for_arm (~n))
7763 operands[1] = GEN_INT (~n);
7764 output_asm_insn ("mvn%?\t%0, %1", operands);
7771 /* If all else fails, make it out of ORRs or BICs as appropriate. */
7772 for (i = 0; i < 32; i++)
7776 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
7777 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
7779 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
7785 /* Output an ADD r, s, #n where n may be too big for one instruction.
7786 If adding zero to one register, output nothing. */
7788 output_add_immediate (rtx *operands)
7790 HOST_WIDE_INT n = INTVAL (operands[2]);
7792 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
7795 output_multi_immediate (operands,
7796 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
7799 output_multi_immediate (operands,
7800 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
7807 /* Output a multiple immediate operation.
7808 OPERANDS is the vector of operands referred to in the output patterns.
7809 INSTR1 is the output pattern to use for the first constant.
7810 INSTR2 is the output pattern to use for subsequent constants.
7811 IMMED_OP is the index of the constant slot in OPERANDS.
7812 N is the constant value. */
7814 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
7815 int immed_op, HOST_WIDE_INT n)
7817 #if HOST_BITS_PER_WIDE_INT > 32
7823 /* Quick and easy output. */
7824 operands[immed_op] = const0_rtx;
7825 output_asm_insn (instr1, operands);
7830 const char * instr = instr1;
7832 /* Note that n is never zero here (which would give no output). */
7833 for (i = 0; i < 32; i += 2)
7837 operands[immed_op] = GEN_INT (n & (255 << i));
7838 output_asm_insn (instr, operands);
7848 /* Return the appropriate ARM instruction for the operation code.
7849 The returned result should not be overwritten. OP is the rtx of the
7850 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
7853 arithmetic_instr (rtx op, int shift_first_arg)
7855 switch (GET_CODE (op))
7861 return shift_first_arg ? "rsb" : "sub";
7877 /* Ensure valid constant shifts and return the appropriate shift mnemonic
7878 for the operation code. The returned result should not be overwritten.
7879 OP is the rtx code of the shift.
7880 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
7883 shift_op (rtx op, HOST_WIDE_INT *amountp)
7886 enum rtx_code code = GET_CODE (op);
7888 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
7890 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
7891 *amountp = INTVAL (XEXP (op, 1));
7914 /* We never have to worry about the amount being other than a
7915 power of 2, since this case can never be reloaded from a reg. */
7917 *amountp = int_log2 (*amountp);
7928 /* This is not 100% correct, but follows from the desire to merge
7929 multiplication by a power of 2 with the recognizer for a
7930 shift. >=32 is not a valid shift for "asl", so we must try and
7931 output a shift that produces the correct arithmetical result.
7932 Using lsr #32 is identical except for the fact that the carry bit
7933 is not set correctly if we set the flags; but we never use the
7934 carry bit from such an operation, so we can ignore that. */
7935 if (code == ROTATERT)
7936 /* Rotate is just modulo 32. */
7938 else if (*amountp != (*amountp & 31))
7945 /* Shifts of 0 are no-ops. */
7953 /* Obtain the shift from the POWER of two. */
7955 static HOST_WIDE_INT
7956 int_log2 (HOST_WIDE_INT power)
7958 HOST_WIDE_INT shift = 0;
7960 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
7970 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7971 /bin/as is horribly restrictive. */
7972 #define MAX_ASCII_LEN 51
7975 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
7980 fputs ("\t.ascii\t\"", stream);
7982 for (i = 0; i < len; i++)
7986 if (len_so_far >= MAX_ASCII_LEN)
7988 fputs ("\"\n\t.ascii\t\"", stream);
7995 fputs ("\\t", stream);
8000 fputs ("\\f", stream);
8005 fputs ("\\b", stream);
8010 fputs ("\\r", stream);
8014 case TARGET_NEWLINE:
8015 fputs ("\\n", stream);
8017 if ((c >= ' ' && c <= '~')
8019 /* This is a good place for a line break. */
8020 len_so_far = MAX_ASCII_LEN;
8027 putc ('\\', stream);
8032 if (c >= ' ' && c <= '~')
8039 fprintf (stream, "\\%03o", c);
8046 fputs ("\"\n", stream);
8049 /* Compute the register sabe mask for registers 0 through 12
8050 inclusive. This code is used by both arm_compute_save_reg_mask
8051 and arm_compute_initial_elimination_offset. */
8052 static unsigned long
8053 arm_compute_save_reg0_reg12_mask (void)
8055 unsigned long func_type = arm_current_func_type ();
8056 unsigned int save_reg_mask = 0;
8059 if (IS_INTERRUPT (func_type))
8061 unsigned int max_reg;
8062 /* Interrupt functions must not corrupt any registers,
8063 even call clobbered ones. If this is a leaf function
8064 we can just examine the registers used by the RTL, but
8065 otherwise we have to assume that whatever function is
8066 called might clobber anything, and so we have to save
8067 all the call-clobbered registers as well. */
8068 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8069 /* FIQ handlers have registers r8 - r12 banked, so
8070 we only need to check r0 - r7, Normal ISRs only
8071 bank r14 and r15, so we must check up to r12.
8072 r13 is the stack pointer which is always preserved,
8073 so we do not need to consider it here. */
8078 for (reg = 0; reg <= max_reg; reg++)
8079 if (regs_ever_live[reg]
8080 || (! current_function_is_leaf && call_used_regs [reg]))
8081 save_reg_mask |= (1 << reg);
8085 /* In the normal case we only need to save those registers
8086 which are call saved and which are used by this function. */
8087 for (reg = 0; reg <= 10; reg++)
8088 if (regs_ever_live[reg] && ! call_used_regs [reg])
8089 save_reg_mask |= (1 << reg);
8091 /* Handle the frame pointer as a special case. */
8092 if (! TARGET_APCS_FRAME
8093 && ! frame_pointer_needed
8094 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8095 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8096 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8098 /* If we aren't loading the PIC register,
8099 don't stack it even though it may be live. */
8101 && ! TARGET_SINGLE_PIC_BASE
8102 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8103 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8106 return save_reg_mask;
8109 /* Compute a bit mask of which registers need to be
8110 saved on the stack for the current function. */
8112 static unsigned long
8113 arm_compute_save_reg_mask (void)
8115 unsigned int save_reg_mask = 0;
8116 unsigned long func_type = arm_current_func_type ();
8118 if (IS_NAKED (func_type))
8119 /* This should never really happen. */
8122 /* If we are creating a stack frame, then we must save the frame pointer,
8123 IP (which will hold the old stack pointer), LR and the PC. */
8124 if (frame_pointer_needed)
8126 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8131 /* Volatile functions do not return, so there
8132 is no need to save any other registers. */
8133 if (IS_VOLATILE (func_type))
8134 return save_reg_mask;
8136 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8138 /* Decide if we need to save the link register.
8139 Interrupt routines have their own banked link register,
8140 so they never need to save it.
8141 Otherwise if we do not use the link register we do not need to save
8142 it. If we are pushing other registers onto the stack however, we
8143 can save an instruction in the epilogue by pushing the link register
8144 now and then popping it back into the PC. This incurs extra memory
8145 accesses though, so we only do it when optimizing for size, and only
8146 if we know that we will not need a fancy return sequence. */
8147 if (regs_ever_live [LR_REGNUM]
8150 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8151 save_reg_mask |= 1 << LR_REGNUM;
8153 if (cfun->machine->lr_save_eliminated)
8154 save_reg_mask &= ~ (1 << LR_REGNUM);
8156 if (TARGET_REALLY_IWMMXT
8157 && ((bit_count (save_reg_mask)
8158 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8162 /* The total number of registers that are going to be pushed
8163 onto the stack is odd. We need to ensure that the stack
8164 is 64-bit aligned before we start to save iWMMXt registers,
8165 and also before we start to create locals. (A local variable
8166 might be a double or long long which we will load/store using
8167 an iWMMXt instruction). Therefore we need to push another
8168 ARM register, so that the stack will be 64-bit aligned. We
8169 try to avoid using the arg registers (r0 -r3) as they might be
8170 used to pass values in a tail call. */
8171 for (reg = 4; reg <= 12; reg++)
8172 if ((save_reg_mask & (1 << reg)) == 0)
8176 save_reg_mask |= (1 << reg);
8179 cfun->machine->sibcall_blocked = 1;
8180 save_reg_mask |= (1 << 3);
8184 return save_reg_mask;
8187 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
8188 everything bar the final return instruction. */
8190 output_return_instruction (rtx operand, int really_return, int reverse)
8192 char conditional[10];
8195 unsigned long live_regs_mask;
8196 unsigned long func_type;
8198 func_type = arm_current_func_type ();
8200 if (IS_NAKED (func_type))
8203 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8205 /* If this function was declared non-returning, and we have
8206 found a tail call, then we have to trust that the called
8207 function won't return. */
8212 /* Otherwise, trap an attempted return by aborting. */
8214 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
8216 assemble_external_libcall (ops[1]);
8217 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
8223 if (current_function_calls_alloca && !really_return)
8226 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
8228 return_used_this_function = 1;
8230 live_regs_mask = arm_compute_save_reg_mask ();
8234 const char * return_reg;
8236 /* If we do not have any special requirements for function exit
8237 (eg interworking, or ISR) then we can load the return address
8238 directly into the PC. Otherwise we must load it into LR. */
8240 && ! TARGET_INTERWORK)
8241 return_reg = reg_names[PC_REGNUM];
8243 return_reg = reg_names[LR_REGNUM];
8245 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
8247 /* There are three possible reasons for the IP register
8248 being saved. 1) a stack frame was created, in which case
8249 IP contains the old stack pointer, or 2) an ISR routine
8250 corrupted it, or 3) it was saved to align the stack on
8251 iWMMXt. In case 1, restore IP into SP, otherwise just
8253 if (frame_pointer_needed)
8255 live_regs_mask &= ~ (1 << IP_REGNUM);
8256 live_regs_mask |= (1 << SP_REGNUM);
8260 if (! IS_INTERRUPT (func_type)
8261 && ! TARGET_REALLY_IWMMXT)
8266 /* On some ARM architectures it is faster to use LDR rather than
8267 LDM to load a single register. On other architectures, the
8268 cost is the same. In 26 bit mode, or for exception handlers,
8269 we have to use LDM to load the PC so that the CPSR is also
8271 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8273 if (live_regs_mask == (unsigned int)(1 << reg))
8276 if (reg <= LAST_ARM_REGNUM
8277 && (reg != LR_REGNUM
8279 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
8281 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
8282 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
8289 /* Generate the load multiple instruction to restore the
8290 registers. Note we can get here, even if
8291 frame_pointer_needed is true, but only if sp already
8292 points to the base of the saved core registers. */
8293 if (live_regs_mask & (1 << SP_REGNUM))
8295 unsigned HOST_WIDE_INT stack_adjust =
8296 arm_get_frame_size () + current_function_outgoing_args_size;
8298 if (stack_adjust != 0 && stack_adjust != 4)
8301 if (stack_adjust && arm_arch5)
8302 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
8305 /* If we can't use ldmib (SA110 bug), then try to pop r3
8308 live_regs_mask |= 1 << 3;
8309 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
8313 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
8315 p = instr + strlen (instr);
8317 for (reg = 0; reg <= SP_REGNUM; reg++)
8318 if (live_regs_mask & (1 << reg))
8320 int l = strlen (reg_names[reg]);
8326 memcpy (p, ", ", 2);
8330 memcpy (p, "%|", 2);
8331 memcpy (p + 2, reg_names[reg], l);
8335 if (live_regs_mask & (1 << LR_REGNUM))
8337 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
8338 /* Decide if we need to add the ^ symbol to the end of the
8339 register list. This causes the saved condition codes
8340 register to be copied into the current condition codes
8341 register. We do the copy if we are conforming to the 32-bit
8342 ABI and this is an interrupt function, or if we are
8343 conforming to the 26-bit ABI. There is a special case for
8344 the 26-bit ABI however, which is if we are writing back the
8345 stack pointer but not loading the PC. In this case adding
8346 the ^ symbol would create a type 2 LDM instruction, where
8347 writeback is UNPREDICTABLE. We are safe in leaving the ^
8348 character off in this case however, since the actual return
8349 instruction will be a MOVS which will restore the CPSR. */
8350 if ((TARGET_APCS_32 && IS_INTERRUPT (func_type))
8351 || (! TARGET_APCS_32 && really_return))
8358 output_asm_insn (instr, & operand);
8360 /* See if we need to generate an extra instruction to
8361 perform the actual function return. */
8363 && func_type != ARM_FT_INTERWORKED
8364 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
8366 /* The return has already been handled
8367 by loading the LR into the PC. */
8374 switch ((int) ARM_FUNC_TYPE (func_type))
8378 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
8381 case ARM_FT_INTERWORKED:
8382 sprintf (instr, "bx%s\t%%|lr", conditional);
8385 case ARM_FT_EXCEPTION:
8386 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
8390 /* ARMv5 implementations always provide BX, so interworking
8391 is the default unless APCS-26 is in use. */
8392 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
8393 sprintf (instr, "bx%s\t%%|lr", conditional);
8395 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
8396 conditional, TARGET_APCS_32 ? "" : "s");
8400 output_asm_insn (instr, & operand);
8406 /* Write the function name into the code section, directly preceding
8407 the function prologue.
8409 Code will be output similar to this:
8411 .ascii "arm_poke_function_name", 0
8414 .word 0xff000000 + (t1 - t0)
8415 arm_poke_function_name
8417 stmfd sp!, {fp, ip, lr, pc}
8420 When performing a stack backtrace, code can inspect the value
8421 of 'pc' stored at 'fp' + 0. If the trace function then looks
8422 at location pc - 12 and the top 8 bits are set, then we know
8423 that there is a function name embedded immediately preceding this
8424 location and has length ((pc[-3]) & 0xff000000).
8426 We assume that pc is declared as a pointer to an unsigned long.
8428 It is of no benefit to output the function name if we are assembling
8429 a leaf function. These function types will not contain a stack
8430 backtrace structure, therefore it is not possible to determine the
8433 arm_poke_function_name (FILE *stream, const char *name)
8435 unsigned long alignlength;
8436 unsigned long length;
8439 length = strlen (name) + 1;
8440 alignlength = ROUND_UP_WORD (length);
8442 ASM_OUTPUT_ASCII (stream, name, length);
8443 ASM_OUTPUT_ALIGN (stream, 2);
8444 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
8445 assemble_aligned_integer (UNITS_PER_WORD, x);
8448 /* Place some comments into the assembler stream
8449 describing the current function. */
8451 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
8453 unsigned long func_type;
8457 thumb_output_function_prologue (f, frame_size);
8462 if (arm_ccfsm_state || arm_target_insn)
8465 func_type = arm_current_func_type ();
8467 switch ((int) ARM_FUNC_TYPE (func_type))
8472 case ARM_FT_INTERWORKED:
8473 asm_fprintf (f, "\t%@ Function supports interworking.\n");
8475 case ARM_FT_EXCEPTION_HANDLER:
8476 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
8479 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
8482 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
8484 case ARM_FT_EXCEPTION:
8485 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
8489 if (IS_NAKED (func_type))
8490 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
8492 if (IS_VOLATILE (func_type))
8493 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
8495 if (IS_NESTED (func_type))
8496 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
8498 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
8499 current_function_args_size,
8500 current_function_pretend_args_size, frame_size);
8502 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
8503 frame_pointer_needed,
8504 cfun->machine->uses_anonymous_args);
8506 if (cfun->machine->lr_save_eliminated)
8507 asm_fprintf (f, "\t%@ link register save eliminated.\n");
8509 #ifdef AOF_ASSEMBLER
8511 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
8514 return_used_this_function = 0;
8518 arm_output_epilogue (rtx sibling)
8521 unsigned long saved_regs_mask;
8522 unsigned long func_type;
8523 /* Floats_offset is the offset from the "virtual" frame. In an APCS
8524 frame that is $fp + 4 for a non-variadic function. */
8525 int floats_offset = 0;
8527 int frame_size = arm_get_frame_size ();
8528 FILE * f = asm_out_file;
8529 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
8530 unsigned int lrm_count = 0;
8531 int really_return = (sibling == NULL);
8533 /* If we have already generated the return instruction
8534 then it is futile to generate anything else. */
8535 if (use_return_insn (FALSE, sibling) && return_used_this_function)
8538 func_type = arm_current_func_type ();
8540 if (IS_NAKED (func_type))
8541 /* Naked functions don't have epilogues. */
8544 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8548 /* A volatile function should never return. Call abort. */
8549 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
8550 assemble_external_libcall (op);
8551 output_asm_insn ("bl\t%a0", &op);
8556 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
8558 /* If we are throwing an exception, then we really must
8559 be doing a return, so we can't tail-call. */
8562 saved_regs_mask = arm_compute_save_reg_mask ();
8565 lrm_count = bit_count (saved_regs_mask);
8567 /* XXX We should adjust floats_offset for any anonymous args, and then
8568 re-adjust vfp_offset below to compensate. */
8570 /* Compute how far away the floats will be. */
8571 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8572 if (saved_regs_mask & (1 << reg))
8575 if (frame_pointer_needed)
8579 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8581 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8582 if (regs_ever_live[reg] && !call_used_regs[reg])
8584 floats_offset += 12;
8585 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
8586 reg, FP_REGNUM, floats_offset - vfp_offset);
8591 int start_reg = LAST_ARM_FP_REGNUM;
8593 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8595 if (regs_ever_live[reg] && !call_used_regs[reg])
8597 floats_offset += 12;
8599 /* We can't unstack more than four registers at once. */
8600 if (start_reg - reg == 3)
8602 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
8603 reg, FP_REGNUM, floats_offset - vfp_offset);
8604 start_reg = reg - 1;
8609 if (reg != start_reg)
8610 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8611 reg + 1, start_reg - reg,
8612 FP_REGNUM, floats_offset - vfp_offset);
8613 start_reg = reg - 1;
8617 /* Just in case the last register checked also needs unstacking. */
8618 if (reg != start_reg)
8619 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8620 reg + 1, start_reg - reg,
8621 FP_REGNUM, floats_offset - vfp_offset);
8626 /* The frame pointer is guaranteed to be non-double-word aligned.
8627 This is because it is set to (old_stack_pointer - 4) and the
8628 old_stack_pointer was double word aligned. Thus the offset to
8629 the iWMMXt registers to be loaded must also be non-double-word
8630 sized, so that the resultant address *is* double-word aligned.
8631 We can ignore floats_offset since that was already included in
8632 the live_regs_mask. */
8633 lrm_count += (lrm_count % 2 ? 2 : 1);
8635 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
8636 if (regs_ever_live[reg] && !call_used_regs[reg])
8638 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
8639 reg, FP_REGNUM, lrm_count * 4);
8644 /* saved_regs_mask should contain the IP, which at the time of stack
8645 frame generation actually contains the old stack pointer. So a
8646 quick way to unwind the stack is just pop the IP register directly
8647 into the stack pointer. */
8648 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
8650 saved_regs_mask &= ~ (1 << IP_REGNUM);
8651 saved_regs_mask |= (1 << SP_REGNUM);
8653 /* There are two registers left in saved_regs_mask - LR and PC. We
8654 only need to restore the LR register (the return address), but to
8655 save time we can load it directly into the PC, unless we need a
8656 special function exit sequence, or we are not really returning. */
8657 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
8658 /* Delete the LR from the register mask, so that the LR on
8659 the stack is loaded into the PC in the register mask. */
8660 saved_regs_mask &= ~ (1 << LR_REGNUM);
8662 saved_regs_mask &= ~ (1 << PC_REGNUM);
8664 /* We must use SP as the base register, because SP is one of the
8665 registers being restored. If an interrupt or page fault
8666 happens in the ldm instruction, the SP might or might not
8667 have been restored. That would be bad, as then SP will no
8668 longer indicate the safe area of stack, and we can get stack
8669 corruption. Using SP as the base register means that it will
8670 be reset correctly to the original value, should an interrupt
8671 occur. If the stack pointer already points at the right
8672 place, then omit the subtraction. */
8673 if (((frame_size + current_function_outgoing_args_size + floats_offset)
8674 != 4 * (1 + (int) bit_count (saved_regs_mask)))
8675 || current_function_calls_alloca)
8676 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
8677 4 * bit_count (saved_regs_mask));
8678 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
8680 if (IS_INTERRUPT (func_type))
8681 /* Interrupt handlers will have pushed the
8682 IP onto the stack, so restore it now. */
8683 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
8687 /* Restore stack pointer if necessary. */
8688 if (frame_size + current_function_outgoing_args_size != 0)
8690 operands[0] = operands[1] = stack_pointer_rtx;
8691 operands[2] = GEN_INT (frame_size
8692 + current_function_outgoing_args_size);
8693 output_add_immediate (operands);
8696 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8698 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8699 if (regs_ever_live[reg] && !call_used_regs[reg])
8700 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
8705 int start_reg = FIRST_ARM_FP_REGNUM;
8707 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8709 if (regs_ever_live[reg] && !call_used_regs[reg])
8711 if (reg - start_reg == 3)
8713 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
8714 start_reg, SP_REGNUM);
8715 start_reg = reg + 1;
8720 if (reg != start_reg)
8721 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8722 start_reg, reg - start_reg,
8725 start_reg = reg + 1;
8729 /* Just in case the last register checked also needs unstacking. */
8730 if (reg != start_reg)
8731 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8732 start_reg, reg - start_reg, SP_REGNUM);
8736 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
8737 if (regs_ever_live[reg] && !call_used_regs[reg])
8738 asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM);
8740 /* If we can, restore the LR into the PC. */
8741 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8743 && current_function_pretend_args_size == 0
8744 && saved_regs_mask & (1 << LR_REGNUM))
8746 saved_regs_mask &= ~ (1 << LR_REGNUM);
8747 saved_regs_mask |= (1 << PC_REGNUM);
8750 /* Load the registers off the stack. If we only have one register
8751 to load use the LDR instruction - it is faster. */
8752 if (saved_regs_mask == (1 << LR_REGNUM))
8754 /* The exception handler ignores the LR, so we do
8755 not really need to load it off the stack. */
8757 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
8759 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
8761 else if (saved_regs_mask)
8763 if (saved_regs_mask & (1 << SP_REGNUM))
8764 /* Note - write back to the stack register is not enabled
8765 (ie "ldmfd sp!..."). We know that the stack pointer is
8766 in the list of registers and if we add writeback the
8767 instruction becomes UNPREDICTABLE. */
8768 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
8770 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
8773 if (current_function_pretend_args_size)
8775 /* Unwind the pre-pushed regs. */
8776 operands[0] = operands[1] = stack_pointer_rtx;
8777 operands[2] = GEN_INT (current_function_pretend_args_size);
8778 output_add_immediate (operands);
8783 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8784 && current_function_pretend_args_size == 0
8785 && saved_regs_mask & (1 << PC_REGNUM)))
8788 /* Generate the return instruction. */
8789 switch ((int) ARM_FUNC_TYPE (func_type))
8791 case ARM_FT_EXCEPTION_HANDLER:
8792 /* Even in 26-bit mode we do a mov (rather than a movs)
8793 because we don't have the PSR bits set in the address. */
8794 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
8799 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
8802 case ARM_FT_EXCEPTION:
8803 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8806 case ARM_FT_INTERWORKED:
8807 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
8811 if (frame_pointer_needed)
8812 /* If we used the frame pointer then the return address
8813 will have been loaded off the stack directly into the
8814 PC, so there is no need to issue a MOV instruction
8817 else if (current_function_pretend_args_size == 0
8818 && (saved_regs_mask & (1 << LR_REGNUM)))
8819 /* Similarly we may have been able to load LR into the PC
8820 even if we did not create a stack frame. */
8822 else if (TARGET_APCS_32)
8823 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8825 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8833 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8834 HOST_WIDE_INT frame_size)
8838 /* ??? Probably not safe to set this here, since it assumes that a
8839 function will be emitted as assembly immediately after we generate
8840 RTL for it. This does not happen for inline functions. */
8841 return_used_this_function = 0;
8845 /* We need to take into account any stack-frame rounding. */
8846 frame_size = arm_get_frame_size ();
8848 if (use_return_insn (FALSE, NULL)
8849 && return_used_this_function
8850 && (frame_size + current_function_outgoing_args_size) != 0
8851 && !frame_pointer_needed)
8854 /* Reset the ARM-specific per-function variables. */
8855 after_arm_reorg = 0;
8859 /* Generate and emit an insn that we will recognize as a push_multi.
8860 Unfortunately, since this insn does not reflect very well the actual
8861 semantics of the operation, we need to annotate the insn for the benefit
8862 of DWARF2 frame unwind information. */
8864 emit_multi_reg_push (int mask)
8871 int dwarf_par_index;
8874 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8875 if (mask & (1 << i))
8878 if (num_regs == 0 || num_regs > 16)
8881 /* We don't record the PC in the dwarf frame information. */
8882 num_dwarf_regs = num_regs;
8883 if (mask & (1 << PC_REGNUM))
8886 /* For the body of the insn we are going to generate an UNSPEC in
8887 parallel with several USEs. This allows the insn to be recognized
8888 by the push_multi pattern in the arm.md file. The insn looks
8889 something like this:
8892 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
8893 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
8894 (use (reg:SI 11 fp))
8895 (use (reg:SI 12 ip))
8896 (use (reg:SI 14 lr))
8897 (use (reg:SI 15 pc))
8900 For the frame note however, we try to be more explicit and actually
8901 show each register being stored into the stack frame, plus a (single)
8902 decrement of the stack pointer. We do it this way in order to be
8903 friendly to the stack unwinding code, which only wants to see a single
8904 stack decrement per instruction. The RTL we generate for the note looks
8905 something like this:
8908 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
8909 (set (mem:SI (reg:SI sp)) (reg:SI r4))
8910 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
8911 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
8912 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
8915 This sequence is used both by the code to support stack unwinding for
8916 exceptions handlers and the code to generate dwarf2 frame debugging. */
8918 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
8919 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
8920 dwarf_par_index = 1;
8922 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8924 if (mask & (1 << i))
8926 reg = gen_rtx_REG (SImode, i);
8929 = gen_rtx_SET (VOIDmode,
8930 gen_rtx_MEM (BLKmode,
8931 gen_rtx_PRE_DEC (BLKmode,
8932 stack_pointer_rtx)),
8933 gen_rtx_UNSPEC (BLKmode,
8939 tmp = gen_rtx_SET (VOIDmode,
8940 gen_rtx_MEM (SImode, stack_pointer_rtx),
8942 RTX_FRAME_RELATED_P (tmp) = 1;
8943 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
8951 for (j = 1, i++; j < num_regs; i++)
8953 if (mask & (1 << i))
8955 reg = gen_rtx_REG (SImode, i);
8957 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
8961 tmp = gen_rtx_SET (VOIDmode,
8962 gen_rtx_MEM (SImode,
8963 plus_constant (stack_pointer_rtx,
8966 RTX_FRAME_RELATED_P (tmp) = 1;
8967 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
8974 par = emit_insn (par);
8976 tmp = gen_rtx_SET (SImode,
8978 gen_rtx_PLUS (SImode,
8980 GEN_INT (-4 * num_regs)));
8981 RTX_FRAME_RELATED_P (tmp) = 1;
8982 XVECEXP (dwarf, 0, 0) = tmp;
8984 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8990 emit_sfm (int base_reg, int count)
8997 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8998 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9000 reg = gen_rtx_REG (XFmode, base_reg++);
9003 = gen_rtx_SET (VOIDmode,
9004 gen_rtx_MEM (BLKmode,
9005 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9006 gen_rtx_UNSPEC (BLKmode,
9010 = gen_rtx_SET (VOIDmode,
9011 gen_rtx_MEM (XFmode,
9012 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9014 RTX_FRAME_RELATED_P (tmp) = 1;
9015 XVECEXP (dwarf, 0, count - 1) = tmp;
9017 for (i = 1; i < count; i++)
9019 reg = gen_rtx_REG (XFmode, base_reg++);
9020 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9022 tmp = gen_rtx_SET (VOIDmode,
9023 gen_rtx_MEM (XFmode,
9024 gen_rtx_PRE_DEC (BLKmode,
9025 stack_pointer_rtx)),
9027 RTX_FRAME_RELATED_P (tmp) = 1;
9028 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9031 par = emit_insn (par);
9032 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9037 /* Compute the distance from register FROM to register TO.
9038 These can be the arg pointer (26), the soft frame pointer (25),
9039 the stack pointer (13) or the hard frame pointer (11).
9040 Typical stack layout looks like this:
9042 old stack pointer -> | |
9045 | | saved arguments for
9046 | | vararg functions
9049 hard FP & arg pointer -> | | \
9057 soft frame pointer -> | | /
9067 current stack pointer -> | | /
9070 For a given function some or all of these stack components
9071 may not be needed, giving rise to the possibility of
9072 eliminating some of the registers.
9074 The values returned by this function must reflect the behavior
9075 of arm_expand_prologue() and arm_compute_save_reg_mask().
9077 The sign of the number returned reflects the direction of stack
9078 growth, so the values are positive for all eliminations except
9079 from the soft frame pointer to the hard frame pointer. */
9081 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
9083 unsigned int local_vars = arm_get_frame_size ();
9084 unsigned int outgoing_args = current_function_outgoing_args_size;
9085 unsigned int stack_frame;
9086 unsigned int call_saved_registers;
9087 unsigned long func_type;
9089 func_type = arm_current_func_type ();
9091 /* Volatile functions never return, so there is
9092 no need to save call saved registers. */
9093 call_saved_registers = 0;
9094 if (! IS_VOLATILE (func_type))
9096 unsigned int reg_mask;
9099 /* Make sure that we compute which registers will be saved
9100 on the stack using the same algorithm that is used by
9101 the prologue creation code. */
9102 reg_mask = arm_compute_save_reg_mask ();
9104 /* Now count the number of bits set in save_reg_mask.
9105 If we have already counted the registers in the stack
9106 frame, do not count them again. Non call-saved registers
9107 might be saved in the call-save area of the stack, if
9108 doing so will preserve the stack's alignment. Hence we
9109 must count them here. For each set bit we need 4 bytes
9111 if (frame_pointer_needed)
9113 call_saved_registers += 4 * bit_count (reg_mask);
9115 /* If the hard floating point registers are going to be
9116 used then they must be saved on the stack as well.
9117 Each register occupies 12 bytes of stack space. */
9118 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
9119 if (regs_ever_live[reg] && ! call_used_regs[reg])
9120 call_saved_registers += 12;
9122 if (TARGET_REALLY_IWMMXT)
9123 /* Check for the call-saved iWMMXt registers. */
9124 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9125 if (regs_ever_live[reg] && ! call_used_regs [reg])
9126 call_saved_registers += 8;
9129 /* The stack frame contains 4 registers - the old frame pointer,
9130 the old stack pointer, the return address and PC of the start
9132 stack_frame = frame_pointer_needed ? 16 : 0;
9134 /* OK, now we have enough information to compute the distances.
9135 There must be an entry in these switch tables for each pair
9136 of registers in ELIMINABLE_REGS, even if some of the entries
9137 seem to be redundant or useless. */
9140 case ARG_POINTER_REGNUM:
9143 case THUMB_HARD_FRAME_POINTER_REGNUM:
9146 case FRAME_POINTER_REGNUM:
9147 /* This is the reverse of the soft frame pointer
9148 to hard frame pointer elimination below. */
9149 if (call_saved_registers == 0 && stack_frame == 0)
9151 return (call_saved_registers + stack_frame - 4);
9153 case ARM_HARD_FRAME_POINTER_REGNUM:
9154 /* If there is no stack frame then the hard
9155 frame pointer and the arg pointer coincide. */
9156 if (stack_frame == 0 && call_saved_registers != 0)
9158 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9159 return (frame_pointer_needed
9160 && current_function_needs_context
9161 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
9163 case STACK_POINTER_REGNUM:
9164 /* If nothing has been pushed on the stack at all
9165 then this will return -4. This *is* correct! */
9166 return call_saved_registers + stack_frame + local_vars + outgoing_args - 4;
9173 case FRAME_POINTER_REGNUM:
9176 case THUMB_HARD_FRAME_POINTER_REGNUM:
9179 case ARM_HARD_FRAME_POINTER_REGNUM:
9180 /* The hard frame pointer points to the top entry in the
9181 stack frame. The soft frame pointer to the bottom entry
9182 in the stack frame. If there is no stack frame at all,
9183 then they are identical. */
9184 if (call_saved_registers == 0 && stack_frame == 0)
9186 return - (call_saved_registers + stack_frame - 4);
9188 case STACK_POINTER_REGNUM:
9189 return local_vars + outgoing_args;
9197 /* You cannot eliminate from the stack pointer.
9198 In theory you could eliminate from the hard frame
9199 pointer to the stack pointer, but this will never
9200 happen, since if a stack frame is not needed the
9201 hard frame pointer will never be used. */
9206 /* Calculate the size of the stack frame, taking into account any
9207 padding that is required to ensure stack-alignment. */
9209 arm_get_frame_size (void)
9213 int base_size = ROUND_UP_WORD (get_frame_size ());
9215 unsigned long func_type = arm_current_func_type ();
9224 /* We need to know if we are a leaf function. Unfortunately, it
9225 is possible to be called after start_sequence has been called,
9226 which causes get_insns to return the insns for the sequence,
9227 not the function, which will cause leaf_function_p to return
9228 the incorrect result.
9230 To work around this, we cache the computed frame size. This
9231 works because we will only be calling RTL expanders that need
9232 to know about leaf functions once reload has completed, and the
9233 frame size cannot be changed after that time, so we can safely
9234 use the cached value. */
9236 if (reload_completed)
9237 return cfun->machine->frame_size;
9239 leaf = leaf_function_p ();
9241 /* A leaf function does not need any stack alignment if it has nothing
9243 if (leaf && base_size == 0)
9245 cfun->machine->frame_size = 0;
9249 /* We know that SP will be word aligned on entry, and we must
9250 preserve that condition at any subroutine call. But those are
9251 the only constraints. */
9253 /* Space for variadic functions. */
9254 if (current_function_pretend_args_size)
9255 entry_size += current_function_pretend_args_size;
9257 /* Space for saved registers. */
9258 entry_size += bit_count (arm_compute_save_reg_mask ()) * 4;
9260 /* Space for saved FPA registers. */
9261 if (! IS_VOLATILE (func_type))
9263 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
9264 if (regs_ever_live[regno] && ! call_used_regs[regno])
9268 if (TARGET_REALLY_IWMMXT)
9270 /* Check for the call-saved iWMMXt registers. */
9271 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
9272 if (regs_ever_live [regno] && ! call_used_regs [regno])
9276 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9278 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9281 cfun->machine->frame_size = base_size;
9286 /* Generate the prologue instructions for entry into an ARM function. */
9288 arm_expand_prologue (void)
9294 unsigned long live_regs_mask;
9295 unsigned long func_type;
9297 int saved_pretend_args = 0;
9298 unsigned int args_to_push;
9300 func_type = arm_current_func_type ();
9302 /* Naked functions don't have prologues. */
9303 if (IS_NAKED (func_type))
9306 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9307 args_to_push = current_function_pretend_args_size;
9309 /* Compute which register we will have to save onto the stack. */
9310 live_regs_mask = arm_compute_save_reg_mask ();
9312 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
9314 if (frame_pointer_needed)
9316 if (IS_INTERRUPT (func_type))
9318 /* Interrupt functions must not corrupt any registers.
9319 Creating a frame pointer however, corrupts the IP
9320 register, so we must push it first. */
9321 insn = emit_multi_reg_push (1 << IP_REGNUM);
9323 /* Do not set RTX_FRAME_RELATED_P on this insn.
9324 The dwarf stack unwinding code only wants to see one
9325 stack decrement per function, and this is not it. If
9326 this instruction is labeled as being part of the frame
9327 creation sequence then dwarf2out_frame_debug_expr will
9328 abort when it encounters the assignment of IP to FP
9329 later on, since the use of SP here establishes SP as
9330 the CFA register and not IP.
9332 Anyway this instruction is not really part of the stack
9333 frame creation although it is part of the prologue. */
9335 else if (IS_NESTED (func_type))
9337 /* The Static chain register is the same as the IP register
9338 used as a scratch register during stack frame creation.
9339 To get around this need to find somewhere to store IP
9340 whilst the frame is being created. We try the following
9343 1. The last argument register.
9344 2. A slot on the stack above the frame. (This only
9345 works if the function is not a varargs function).
9346 3. Register r3, after pushing the argument registers
9349 Note - we only need to tell the dwarf2 backend about the SP
9350 adjustment in the second variant; the static chain register
9351 doesn't need to be unwound, as it doesn't contain a value
9352 inherited from the caller. */
9354 if (regs_ever_live[3] == 0)
9356 insn = gen_rtx_REG (SImode, 3);
9357 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9358 insn = emit_insn (insn);
9360 else if (args_to_push == 0)
9363 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
9364 insn = gen_rtx_MEM (SImode, insn);
9365 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
9366 insn = emit_insn (insn);
9370 /* Just tell the dwarf backend that we adjusted SP. */
9371 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9372 gen_rtx_PLUS (SImode, stack_pointer_rtx,
9373 GEN_INT (-fp_offset)));
9374 RTX_FRAME_RELATED_P (insn) = 1;
9375 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9376 dwarf, REG_NOTES (insn));
9380 /* Store the args on the stack. */
9381 if (cfun->machine->uses_anonymous_args)
9382 insn = emit_multi_reg_push
9383 ((0xf0 >> (args_to_push / 4)) & 0xf);
9386 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9387 GEN_INT (- args_to_push)));
9389 RTX_FRAME_RELATED_P (insn) = 1;
9391 saved_pretend_args = 1;
9392 fp_offset = args_to_push;
9395 /* Now reuse r3 to preserve IP. */
9396 insn = gen_rtx_REG (SImode, 3);
9397 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9398 (void) emit_insn (insn);
9404 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
9405 insn = gen_rtx_SET (SImode, ip_rtx, insn);
9408 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
9410 insn = emit_insn (insn);
9411 RTX_FRAME_RELATED_P (insn) = 1;
9416 /* Push the argument registers, or reserve space for them. */
9417 if (cfun->machine->uses_anonymous_args)
9418 insn = emit_multi_reg_push
9419 ((0xf0 >> (args_to_push / 4)) & 0xf);
9422 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9423 GEN_INT (- args_to_push)));
9424 RTX_FRAME_RELATED_P (insn) = 1;
9427 /* If this is an interrupt service routine, and the link register
9428 is going to be pushed, and we are not creating a stack frame,
9429 (which would involve an extra push of IP and a pop in the epilogue)
9430 subtracting four from LR now will mean that the function return
9431 can be done with a single instruction. */
9432 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
9433 && (live_regs_mask & (1 << LR_REGNUM)) != 0
9434 && ! frame_pointer_needed)
9435 emit_insn (gen_rtx_SET (SImode,
9436 gen_rtx_REG (SImode, LR_REGNUM),
9437 gen_rtx_PLUS (SImode,
9438 gen_rtx_REG (SImode, LR_REGNUM),
9443 insn = emit_multi_reg_push (live_regs_mask);
9444 RTX_FRAME_RELATED_P (insn) = 1;
9448 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9449 if (regs_ever_live[reg] && ! call_used_regs [reg])
9451 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
9452 insn = gen_rtx_MEM (V2SImode, insn);
9453 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
9454 gen_rtx_REG (V2SImode, reg)));
9455 RTX_FRAME_RELATED_P (insn) = 1;
9458 if (! IS_VOLATILE (func_type))
9460 /* Save any floating point call-saved registers used by this
9462 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9464 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
9465 if (regs_ever_live[reg] && !call_used_regs[reg])
9467 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
9468 insn = gen_rtx_MEM (XFmode, insn);
9469 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
9470 gen_rtx_REG (XFmode, reg)));
9471 RTX_FRAME_RELATED_P (insn) = 1;
9476 int start_reg = LAST_ARM_FP_REGNUM;
9478 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
9480 if (regs_ever_live[reg] && !call_used_regs[reg])
9482 if (start_reg - reg == 3)
9484 insn = emit_sfm (reg, 4);
9485 RTX_FRAME_RELATED_P (insn) = 1;
9486 start_reg = reg - 1;
9491 if (start_reg != reg)
9493 insn = emit_sfm (reg + 1, start_reg - reg);
9494 RTX_FRAME_RELATED_P (insn) = 1;
9496 start_reg = reg - 1;
9500 if (start_reg != reg)
9502 insn = emit_sfm (reg + 1, start_reg - reg);
9503 RTX_FRAME_RELATED_P (insn) = 1;
9508 if (frame_pointer_needed)
9510 /* Create the new frame pointer. */
9511 insn = GEN_INT (-(4 + args_to_push + fp_offset));
9512 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
9513 RTX_FRAME_RELATED_P (insn) = 1;
9515 if (IS_NESTED (func_type))
9517 /* Recover the static chain register. */
9518 if (regs_ever_live [3] == 0
9519 || saved_pretend_args)
9520 insn = gen_rtx_REG (SImode, 3);
9521 else /* if (current_function_pretend_args_size == 0) */
9523 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
9525 insn = gen_rtx_MEM (SImode, insn);
9528 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
9529 /* Add a USE to stop propagate_one_insn() from barfing. */
9530 emit_insn (gen_prologue_use (ip_rtx));
9534 amount = GEN_INT (-(arm_get_frame_size ()
9535 + current_function_outgoing_args_size));
9537 if (amount != const0_rtx)
9539 /* This add can produce multiple insns for a large constant, so we
9540 need to get tricky. */
9541 rtx last = get_last_insn ();
9542 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9546 last = last ? NEXT_INSN (last) : get_insns ();
9547 RTX_FRAME_RELATED_P (last) = 1;
9549 while (last != insn);
9551 /* If the frame pointer is needed, emit a special barrier that
9552 will prevent the scheduler from moving stores to the frame
9553 before the stack adjustment. */
9554 if (frame_pointer_needed)
9555 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
9556 hard_frame_pointer_rtx));
9559 /* If we are profiling, make sure no instructions are scheduled before
9560 the call to mcount. Similarly if the user has requested no
9561 scheduling in the prolog. */
9562 if (current_function_profile || TARGET_NO_SCHED_PRO)
9563 emit_insn (gen_blockage ());
9565 /* If the link register is being kept alive, with the return address in it,
9566 then make sure that it does not get reused by the ce2 pass. */
9567 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
9569 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
9570 cfun->machine->lr_save_eliminated = 1;
9574 /* If CODE is 'd', then the X is a condition operand and the instruction
9575 should only be executed if the condition is true.
9576 if CODE is 'D', then the X is a condition operand and the instruction
9577 should only be executed if the condition is false: however, if the mode
9578 of the comparison is CCFPEmode, then always execute the instruction -- we
9579 do this because in these circumstances !GE does not necessarily imply LT;
9580 in these cases the instruction pattern will take care to make sure that
9581 an instruction containing %d will follow, thereby undoing the effects of
9582 doing this instruction unconditionally.
9583 If CODE is 'N' then X is a floating point operand that must be negated
9585 If CODE is 'B' then output a bitwise inverted value of X (a const int).
9586 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9588 arm_print_operand (FILE *stream, rtx x, int code)
9593 fputs (ASM_COMMENT_START, stream);
9597 fputs (user_label_prefix, stream);
9601 fputs (REGISTER_PREFIX, stream);
9605 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
9607 if (TARGET_THUMB || current_insn_predicate != NULL)
9610 fputs (arm_condition_codes[arm_current_cc], stream);
9612 else if (current_insn_predicate)
9614 enum arm_cond_code code;
9619 code = get_arm_condition_code (current_insn_predicate);
9620 fputs (arm_condition_codes[code], stream);
9627 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9628 r = REAL_VALUE_NEGATE (r);
9629 fprintf (stream, "%s", fp_const_from_val (&r));
9634 if (GET_CODE (x) == CONST_INT)
9637 val = ARM_SIGN_EXTEND (~INTVAL (x));
9638 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
9643 output_addr_const (stream, x);
9648 fprintf (stream, "%s", arithmetic_instr (x, 1));
9651 /* Truncate Cirrus shift counts. */
9653 if (GET_CODE (x) == CONST_INT)
9655 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
9658 arm_print_operand (stream, x, 0);
9662 fprintf (stream, "%s", arithmetic_instr (x, 0));
9668 const char * shift = shift_op (x, &val);
9672 fprintf (stream, ", %s ", shift_op (x, &val));
9674 arm_print_operand (stream, XEXP (x, 1), 0);
9676 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
9681 /* An explanation of the 'Q', 'R' and 'H' register operands:
9683 In a pair of registers containing a DI or DF value the 'Q'
9684 operand returns the register number of the register containing
9685 the least significant part of the value. The 'R' operand returns
9686 the register number of the register containing the most
9687 significant part of the value.
9689 The 'H' operand returns the higher of the two register numbers.
9690 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
9691 same as the 'Q' operand, since the most significant part of the
9692 value is held in the lower number register. The reverse is true
9693 on systems where WORDS_BIG_ENDIAN is false.
9695 The purpose of these operands is to distinguish between cases
9696 where the endian-ness of the values is important (for example
9697 when they are added together), and cases where the endian-ness
9698 is irrelevant, but the order of register operations is important.
9699 For example when loading a value from memory into a register
9700 pair, the endian-ness does not matter. Provided that the value
9701 from the lower memory address is put into the lower numbered
9702 register, and the value from the higher address is put into the
9703 higher numbered register, the load will work regardless of whether
9704 the value being loaded is big-wordian or little-wordian. The
9705 order of the two register loads can matter however, if the address
9706 of the memory location is actually held in one of the registers
9707 being overwritten by the load. */
9709 if (REGNO (x) > LAST_ARM_REGNUM)
9711 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
9715 if (REGNO (x) > LAST_ARM_REGNUM)
9717 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
9721 if (REGNO (x) > LAST_ARM_REGNUM)
9723 asm_fprintf (stream, "%r", REGNO (x) + 1);
9727 asm_fprintf (stream, "%r",
9728 GET_CODE (XEXP (x, 0)) == REG
9729 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
9733 asm_fprintf (stream, "{%r-%r}",
9735 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
9739 /* CONST_TRUE_RTX means always -- that's the default. */
9740 if (x == const_true_rtx)
9743 fputs (arm_condition_codes[get_arm_condition_code (x)],
9748 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
9750 if (x == const_true_rtx)
9753 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
9754 (get_arm_condition_code (x))],
9758 /* Cirrus registers can be accessed in a variety of ways:
9759 single floating point (f)
9760 double floating point (d)
9762 64bit integer (dx). */
9763 case 'W': /* Cirrus register in F mode. */
9764 case 'X': /* Cirrus register in D mode. */
9765 case 'Y': /* Cirrus register in FX mode. */
9766 case 'Z': /* Cirrus register in DX mode. */
9767 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9770 fprintf (stream, "mv%s%s",
9773 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
9777 /* Print cirrus register in the mode specified by the register's mode. */
9780 int mode = GET_MODE (x);
9782 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9785 fprintf (stream, "mv%s%s",
9786 mode == DFmode ? "d"
9787 : mode == SImode ? "fx"
9788 : mode == DImode ? "dx"
9789 : "f", reg_names[REGNO (x)] + 2);
9795 if (GET_CODE (x) != REG
9796 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
9797 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
9798 /* Bad value for wCG register number. */
9801 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
9804 /* Print an iWMMXt control register name. */
9806 if (GET_CODE (x) != CONST_INT
9808 || INTVAL (x) >= 16)
9809 /* Bad value for wC register number. */
9813 static const char * wc_reg_names [16] =
9815 "wCID", "wCon", "wCSSF", "wCASF",
9816 "wC4", "wC5", "wC6", "wC7",
9817 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
9818 "wC12", "wC13", "wC14", "wC15"
9821 fprintf (stream, wc_reg_names [INTVAL (x)]);
9829 if (GET_CODE (x) == REG)
9830 asm_fprintf (stream, "%r", REGNO (x));
9831 else if (GET_CODE (x) == MEM)
9833 output_memory_reference_mode = GET_MODE (x);
9834 output_address (XEXP (x, 0));
9836 else if (GET_CODE (x) == CONST_DOUBLE)
9837 fprintf (stream, "#%s", fp_immediate_constant (x));
9838 else if (GET_CODE (x) == NEG)
9839 abort (); /* This should never happen now. */
9842 fputc ('#', stream);
9843 output_addr_const (stream, x);
9848 #ifndef AOF_ASSEMBLER
9849 /* Target hook for assembling integer objects. The ARM version needs to
9850 handle word-sized values specially. */
9852 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
9854 if (size == UNITS_PER_WORD && aligned_p)
9856 fputs ("\t.word\t", asm_out_file);
9857 output_addr_const (asm_out_file, x);
9859 /* Mark symbols as position independent. We only do this in the
9860 .text segment, not in the .data segment. */
9861 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
9862 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
9864 if (GET_CODE (x) == SYMBOL_REF
9865 && (CONSTANT_POOL_ADDRESS_P (x)
9866 || SYMBOL_REF_LOCAL_P (x)))
9867 fputs ("(GOTOFF)", asm_out_file);
9868 else if (GET_CODE (x) == LABEL_REF)
9869 fputs ("(GOTOFF)", asm_out_file);
9871 fputs ("(GOT)", asm_out_file);
9873 fputc ('\n', asm_out_file);
9877 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
9881 if (GET_CODE (x) != CONST_VECTOR)
9884 units = CONST_VECTOR_NUNITS (x);
9886 switch (GET_MODE (x))
9888 case V2SImode: size = 4; break;
9889 case V4HImode: size = 2; break;
9890 case V8QImode: size = 1; break;
9895 for (i = 0; i < units; i++)
9899 elt = CONST_VECTOR_ELT (x, i);
9901 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
9907 return default_assemble_integer (x, size, aligned_p);
9911 /* A finite state machine takes care of noticing whether or not instructions
9912 can be conditionally executed, and thus decrease execution time and code
9913 size by deleting branch instructions. The fsm is controlled by
9914 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
9916 /* The state of the fsm controlling condition codes are:
9917 0: normal, do nothing special
9918 1: make ASM_OUTPUT_OPCODE not output this instruction
9919 2: make ASM_OUTPUT_OPCODE not output this instruction
9920 3: make instructions conditional
9921 4: make instructions conditional
9923 State transitions (state->state by whom under condition):
9924 0 -> 1 final_prescan_insn if the `target' is a label
9925 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
9926 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
9927 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
9928 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
9929 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
9930 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
9931 (the target insn is arm_target_insn).
9933 If the jump clobbers the conditions then we use states 2 and 4.
9935 A similar thing can be done with conditional return insns.
9937 XXX In case the `target' is an unconditional branch, this conditionalising
9938 of the instructions always reduces code size, but not always execution
9939 time. But then, I want to reduce the code size to somewhere near what
9940 /bin/cc produces. */
9942 /* Returns the index of the ARM condition code string in
9943 `arm_condition_codes'. COMPARISON should be an rtx like
9944 `(eq (...) (...))'. */
9945 static enum arm_cond_code
9946 get_arm_condition_code (rtx comparison)
9948 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
9950 enum rtx_code comp_code = GET_CODE (comparison);
9952 if (GET_MODE_CLASS (mode) != MODE_CC)
9953 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
9954 XEXP (comparison, 1));
9958 case CC_DNEmode: code = ARM_NE; goto dominance;
9959 case CC_DEQmode: code = ARM_EQ; goto dominance;
9960 case CC_DGEmode: code = ARM_GE; goto dominance;
9961 case CC_DGTmode: code = ARM_GT; goto dominance;
9962 case CC_DLEmode: code = ARM_LE; goto dominance;
9963 case CC_DLTmode: code = ARM_LT; goto dominance;
9964 case CC_DGEUmode: code = ARM_CS; goto dominance;
9965 case CC_DGTUmode: code = ARM_HI; goto dominance;
9966 case CC_DLEUmode: code = ARM_LS; goto dominance;
9967 case CC_DLTUmode: code = ARM_CC;
9970 if (comp_code != EQ && comp_code != NE)
9973 if (comp_code == EQ)
9974 return ARM_INVERSE_CONDITION_CODE (code);
9980 case NE: return ARM_NE;
9981 case EQ: return ARM_EQ;
9982 case GE: return ARM_PL;
9983 case LT: return ARM_MI;
9990 case NE: return ARM_NE;
9991 case EQ: return ARM_EQ;
9998 case NE: return ARM_MI;
9999 case EQ: return ARM_PL;
10005 /* These encodings assume that AC=1 in the FPA system control
10006 byte. This allows us to handle all cases except UNEQ and
10010 case GE: return ARM_GE;
10011 case GT: return ARM_GT;
10012 case LE: return ARM_LS;
10013 case LT: return ARM_MI;
10014 case NE: return ARM_NE;
10015 case EQ: return ARM_EQ;
10016 case ORDERED: return ARM_VC;
10017 case UNORDERED: return ARM_VS;
10018 case UNLT: return ARM_LT;
10019 case UNLE: return ARM_LE;
10020 case UNGT: return ARM_HI;
10021 case UNGE: return ARM_PL;
10022 /* UNEQ and LTGT do not have a representation. */
10023 case UNEQ: /* Fall through. */
10024 case LTGT: /* Fall through. */
10031 case NE: return ARM_NE;
10032 case EQ: return ARM_EQ;
10033 case GE: return ARM_LE;
10034 case GT: return ARM_LT;
10035 case LE: return ARM_GE;
10036 case LT: return ARM_GT;
10037 case GEU: return ARM_LS;
10038 case GTU: return ARM_CC;
10039 case LEU: return ARM_CS;
10040 case LTU: return ARM_HI;
10047 case LTU: return ARM_CS;
10048 case GEU: return ARM_CC;
10055 case NE: return ARM_NE;
10056 case EQ: return ARM_EQ;
10057 case GE: return ARM_GE;
10058 case GT: return ARM_GT;
10059 case LE: return ARM_LE;
10060 case LT: return ARM_LT;
10061 case GEU: return ARM_CS;
10062 case GTU: return ARM_HI;
10063 case LEU: return ARM_LS;
10064 case LTU: return ARM_CC;
10075 arm_final_prescan_insn (rtx insn)
10077 /* BODY will hold the body of INSN. */
10078 rtx body = PATTERN (insn);
10080 /* This will be 1 if trying to repeat the trick, and things need to be
10081 reversed if it appears to fail. */
10084 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
10085 taken are clobbered, even if the rtl suggests otherwise. It also
10086 means that we have to grub around within the jump expression to find
10087 out what the conditions are when the jump isn't taken. */
10088 int jump_clobbers = 0;
10090 /* If we start with a return insn, we only succeed if we find another one. */
10091 int seeking_return = 0;
10093 /* START_INSN will hold the insn from where we start looking. This is the
10094 first insn after the following code_label if REVERSE is true. */
10095 rtx start_insn = insn;
10097 /* If in state 4, check if the target branch is reached, in order to
10098 change back to state 0. */
10099 if (arm_ccfsm_state == 4)
10101 if (insn == arm_target_insn)
10103 arm_target_insn = NULL;
10104 arm_ccfsm_state = 0;
10109 /* If in state 3, it is possible to repeat the trick, if this insn is an
10110 unconditional branch to a label, and immediately following this branch
10111 is the previous target label which is only used once, and the label this
10112 branch jumps to is not too far off. */
10113 if (arm_ccfsm_state == 3)
10115 if (simplejump_p (insn))
10117 start_insn = next_nonnote_insn (start_insn);
10118 if (GET_CODE (start_insn) == BARRIER)
10120 /* XXX Isn't this always a barrier? */
10121 start_insn = next_nonnote_insn (start_insn);
10123 if (GET_CODE (start_insn) == CODE_LABEL
10124 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10125 && LABEL_NUSES (start_insn) == 1)
10130 else if (GET_CODE (body) == RETURN)
10132 start_insn = next_nonnote_insn (start_insn);
10133 if (GET_CODE (start_insn) == BARRIER)
10134 start_insn = next_nonnote_insn (start_insn);
10135 if (GET_CODE (start_insn) == CODE_LABEL
10136 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10137 && LABEL_NUSES (start_insn) == 1)
10140 seeking_return = 1;
10149 if (arm_ccfsm_state != 0 && !reverse)
10151 if (GET_CODE (insn) != JUMP_INSN)
10154 /* This jump might be paralleled with a clobber of the condition codes
10155 the jump should always come first */
10156 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
10157 body = XVECEXP (body, 0, 0);
10160 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
10161 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
10164 int fail = FALSE, succeed = FALSE;
10165 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
10166 int then_not_else = TRUE;
10167 rtx this_insn = start_insn, label = 0;
10169 /* If the jump cannot be done with one instruction, we cannot
10170 conditionally execute the instruction in the inverse case. */
10171 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
10177 /* Register the insn jumped to. */
10180 if (!seeking_return)
10181 label = XEXP (SET_SRC (body), 0);
10183 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
10184 label = XEXP (XEXP (SET_SRC (body), 1), 0);
10185 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
10187 label = XEXP (XEXP (SET_SRC (body), 2), 0);
10188 then_not_else = FALSE;
10190 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
10191 seeking_return = 1;
10192 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
10194 seeking_return = 1;
10195 then_not_else = FALSE;
10200 /* See how many insns this branch skips, and what kind of insns. If all
10201 insns are okay, and the label or unconditional branch to the same
10202 label is not too far away, succeed. */
10203 for (insns_skipped = 0;
10204 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
10208 this_insn = next_nonnote_insn (this_insn);
10212 switch (GET_CODE (this_insn))
10215 /* Succeed if it is the target label, otherwise fail since
10216 control falls in from somewhere else. */
10217 if (this_insn == label)
10221 arm_ccfsm_state = 2;
10222 this_insn = next_nonnote_insn (this_insn);
10225 arm_ccfsm_state = 1;
10233 /* Succeed if the following insn is the target label.
10235 If return insns are used then the last insn in a function
10236 will be a barrier. */
10237 this_insn = next_nonnote_insn (this_insn);
10238 if (this_insn && this_insn == label)
10242 arm_ccfsm_state = 2;
10243 this_insn = next_nonnote_insn (this_insn);
10246 arm_ccfsm_state = 1;
10254 /* If using 32-bit addresses the cc is not preserved over
10256 if (TARGET_APCS_32)
10258 /* Succeed if the following insn is the target label,
10259 or if the following two insns are a barrier and
10260 the target label. */
10261 this_insn = next_nonnote_insn (this_insn);
10262 if (this_insn && GET_CODE (this_insn) == BARRIER)
10263 this_insn = next_nonnote_insn (this_insn);
10265 if (this_insn && this_insn == label
10266 && insns_skipped < max_insns_skipped)
10270 arm_ccfsm_state = 2;
10271 this_insn = next_nonnote_insn (this_insn);
10274 arm_ccfsm_state = 1;
10283 /* If this is an unconditional branch to the same label, succeed.
10284 If it is to another label, do nothing. If it is conditional,
10286 /* XXX Probably, the tests for SET and the PC are
10289 scanbody = PATTERN (this_insn);
10290 if (GET_CODE (scanbody) == SET
10291 && GET_CODE (SET_DEST (scanbody)) == PC)
10293 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
10294 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
10296 arm_ccfsm_state = 2;
10299 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
10302 /* Fail if a conditional return is undesirable (eg on a
10303 StrongARM), but still allow this if optimizing for size. */
10304 else if (GET_CODE (scanbody) == RETURN
10305 && !use_return_insn (TRUE, NULL)
10308 else if (GET_CODE (scanbody) == RETURN
10311 arm_ccfsm_state = 2;
10314 else if (GET_CODE (scanbody) == PARALLEL)
10316 switch (get_attr_conds (this_insn))
10326 fail = TRUE; /* Unrecognized jump (eg epilogue). */
10331 /* Instructions using or affecting the condition codes make it
10333 scanbody = PATTERN (this_insn);
10334 if (!(GET_CODE (scanbody) == SET
10335 || GET_CODE (scanbody) == PARALLEL)
10336 || get_attr_conds (this_insn) != CONDS_NOCOND)
10339 /* A conditional cirrus instruction must be followed by
10340 a non Cirrus instruction. However, since we
10341 conditionalize instructions in this function and by
10342 the time we get here we can't add instructions
10343 (nops), because shorten_branches() has already been
10344 called, we will disable conditionalizing Cirrus
10345 instructions to be safe. */
10346 if (GET_CODE (scanbody) != USE
10347 && GET_CODE (scanbody) != CLOBBER
10348 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
10358 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
10359 arm_target_label = CODE_LABEL_NUMBER (label);
10360 else if (seeking_return || arm_ccfsm_state == 2)
10362 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
10364 this_insn = next_nonnote_insn (this_insn);
10365 if (this_insn && (GET_CODE (this_insn) == BARRIER
10366 || GET_CODE (this_insn) == CODE_LABEL))
10371 /* Oh, dear! we ran off the end.. give up. */
10372 recog (PATTERN (insn), insn, NULL);
10373 arm_ccfsm_state = 0;
10374 arm_target_insn = NULL;
10377 arm_target_insn = this_insn;
10386 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
10388 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
10389 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10390 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
10391 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10395 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
10398 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
10402 if (reverse || then_not_else)
10403 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10406 /* Restore recog_data (getting the attributes of other insns can
10407 destroy this array, but final.c assumes that it remains intact
10408 across this call; since the insn has been recognized already we
10409 call recog direct). */
10410 recog (PATTERN (insn), insn, NULL);
10414 /* Returns true if REGNO is a valid register
10415 for holding a quantity of tyoe MODE. */
10417 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10419 if (GET_MODE_CLASS (mode) == MODE_CC)
10420 return regno == CC_REGNUM;
10423 /* For the Thumb we only allow values bigger than SImode in
10424 registers 0 - 6, so that there is always a second low
10425 register available to hold the upper part of the value.
10426 We probably we ought to ensure that the register is the
10427 start of an even numbered register pair. */
10428 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
10430 if (IS_CIRRUS_REGNUM (regno))
10431 /* We have outlawed SI values in Cirrus registers because they
10432 reside in the lower 32 bits, but SF values reside in the
10433 upper 32 bits. This causes gcc all sorts of grief. We can't
10434 even split the registers into pairs because Cirrus SI values
10435 get sign extended to 64bits-- aldyh. */
10436 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
10438 if (IS_IWMMXT_GR_REGNUM (regno))
10439 return mode == SImode;
10441 if (IS_IWMMXT_REGNUM (regno))
10442 return VALID_IWMMXT_REG_MODE (mode);
10444 if (regno <= LAST_ARM_REGNUM)
10445 /* We allow any value to be stored in the general registers. */
10448 if ( regno == FRAME_POINTER_REGNUM
10449 || regno == ARG_POINTER_REGNUM)
10450 /* We only allow integers in the fake hard registers. */
10451 return GET_MODE_CLASS (mode) == MODE_INT;
10453 /* The only registers left are the FPA registers
10454 which we only allow to hold FP values. */
10455 return GET_MODE_CLASS (mode) == MODE_FLOAT
10456 && regno >= FIRST_ARM_FP_REGNUM
10457 && regno <= LAST_ARM_FP_REGNUM;
10461 arm_regno_class (int regno)
10465 if (regno == STACK_POINTER_REGNUM)
10467 if (regno == CC_REGNUM)
10474 if ( regno <= LAST_ARM_REGNUM
10475 || regno == FRAME_POINTER_REGNUM
10476 || regno == ARG_POINTER_REGNUM)
10477 return GENERAL_REGS;
10479 if (regno == CC_REGNUM)
10482 if (IS_CIRRUS_REGNUM (regno))
10483 return CIRRUS_REGS;
10485 if (IS_IWMMXT_REGNUM (regno))
10486 return IWMMXT_REGS;
10488 if (IS_IWMMXT_GR_REGNUM (regno))
10489 return IWMMXT_GR_REGS;
10494 /* Handle a special case when computing the offset
10495 of an argument from the frame pointer. */
10497 arm_debugger_arg_offset (int value, rtx addr)
10501 /* We are only interested if dbxout_parms() failed to compute the offset. */
10505 /* We can only cope with the case where the address is held in a register. */
10506 if (GET_CODE (addr) != REG)
10509 /* If we are using the frame pointer to point at the argument, then
10510 an offset of 0 is correct. */
10511 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
10514 /* If we are using the stack pointer to point at the
10515 argument, then an offset of 0 is correct. */
10516 if ((TARGET_THUMB || !frame_pointer_needed)
10517 && REGNO (addr) == SP_REGNUM)
10520 /* Oh dear. The argument is pointed to by a register rather
10521 than being held in a register, or being stored at a known
10522 offset from the frame pointer. Since GDB only understands
10523 those two kinds of argument we must translate the address
10524 held in the register into an offset from the frame pointer.
10525 We do this by searching through the insns for the function
10526 looking to see where this register gets its value. If the
10527 register is initialized from the frame pointer plus an offset
10528 then we are in luck and we can continue, otherwise we give up.
10530 This code is exercised by producing debugging information
10531 for a function with arguments like this:
10533 double func (double a, double b, int c, double d) {return d;}
10535 Without this code the stab for parameter 'd' will be set to
10536 an offset of 0 from the frame pointer, rather than 8. */
10538 /* The if() statement says:
10540 If the insn is a normal instruction
10541 and if the insn is setting the value in a register
10542 and if the register being set is the register holding the address of the argument
10543 and if the address is computing by an addition
10544 that involves adding to a register
10545 which is the frame pointer
10550 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10552 if ( GET_CODE (insn) == INSN
10553 && GET_CODE (PATTERN (insn)) == SET
10554 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
10555 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
10556 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
10557 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
10558 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
10561 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
10570 warning ("unable to compute real location of stacked parameter");
10571 value = 8; /* XXX magic hack */
10577 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
10580 if ((MASK) & insn_flags) \
10581 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
10585 struct builtin_description
10587 const unsigned int mask;
10588 const enum insn_code icode;
10589 const char * const name;
10590 const enum arm_builtins code;
10591 const enum rtx_code comparison;
10592 const unsigned int flag;
10595 static const struct builtin_description bdesc_2arg[] =
10597 #define IWMMXT_BUILTIN(code, string, builtin) \
10598 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
10599 ARM_BUILTIN_##builtin, 0, 0 },
10601 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
10602 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
10603 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
10604 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
10605 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
10606 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
10607 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
10608 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
10609 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
10610 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
10611 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
10612 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
10613 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
10614 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
10615 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
10616 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
10617 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
10618 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
10619 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
10620 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsh", WMULSH)
10621 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmuluh", WMULUH)
10622 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
10623 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
10624 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
10625 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
10626 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
10627 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
10628 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
10629 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
10630 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
10631 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
10632 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
10633 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
10634 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
10635 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
10636 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
10637 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
10638 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
10639 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
10640 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
10641 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
10642 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
10643 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
10644 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
10645 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
10646 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
10647 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
10648 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
10649 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
10650 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
10651 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
10652 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
10653 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
10654 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
10655 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
10656 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
10657 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
10658 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
10660 #define IWMMXT_BUILTIN2(code, builtin) \
10661 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
10663 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
10664 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
10665 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
10666 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
10667 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
10668 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
10669 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
10670 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
10671 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
10672 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
10673 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
10674 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
10675 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
10676 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
10677 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
10678 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
10679 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
10680 IWMMXT_BUILTIN2 (lshrdi3, WSRLDI)
10681 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
10682 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
10683 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
10684 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
10685 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
10686 IWMMXT_BUILTIN2 (ashrdi3, WSRADI)
10687 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
10688 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
10689 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
10690 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
10691 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
10692 IWMMXT_BUILTIN2 (rordi3, WRORDI)
10693 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
10694 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
10697 static const struct builtin_description bdesc_1arg[] =
10699 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
10700 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
10701 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
10702 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
10703 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
10704 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
10705 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
10706 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
10707 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
10708 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
10709 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
10710 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
10711 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
10712 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
10713 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
10714 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
10715 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
10716 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
10719 /* Set up all the iWMMXt builtins. This is
10720 not called if TARGET_IWMMXT is zero. */
10723 arm_init_iwmmxt_builtins (void)
10725 const struct builtin_description * d;
10727 tree endlink = void_list_node;
10730 = build_function_type (integer_type_node,
10731 tree_cons (NULL_TREE, integer_type_node, endlink));
10732 tree v8qi_ftype_v8qi_v8qi_int
10733 = build_function_type (V8QI_type_node,
10734 tree_cons (NULL_TREE, V8QI_type_node,
10735 tree_cons (NULL_TREE, V8QI_type_node,
10736 tree_cons (NULL_TREE,
10739 tree v4hi_ftype_v4hi_int
10740 = build_function_type (V4HI_type_node,
10741 tree_cons (NULL_TREE, V4HI_type_node,
10742 tree_cons (NULL_TREE, integer_type_node,
10744 tree v2si_ftype_v2si_int
10745 = build_function_type (V2SI_type_node,
10746 tree_cons (NULL_TREE, V2SI_type_node,
10747 tree_cons (NULL_TREE, integer_type_node,
10749 tree v2si_ftype_di_di
10750 = build_function_type (V2SI_type_node,
10751 tree_cons (NULL_TREE, long_long_integer_type_node,
10752 tree_cons (NULL_TREE, long_long_integer_type_node,
10754 tree di_ftype_di_int
10755 = build_function_type (long_long_integer_type_node,
10756 tree_cons (NULL_TREE, long_long_integer_type_node,
10757 tree_cons (NULL_TREE, integer_type_node,
10759 tree di_ftype_di_int_int
10760 = build_function_type (long_long_integer_type_node,
10761 tree_cons (NULL_TREE, long_long_integer_type_node,
10762 tree_cons (NULL_TREE, integer_type_node,
10763 tree_cons (NULL_TREE,
10766 tree int_ftype_v8qi
10767 = build_function_type (integer_type_node,
10768 tree_cons (NULL_TREE, V8QI_type_node,
10770 tree int_ftype_v4hi
10771 = build_function_type (integer_type_node,
10772 tree_cons (NULL_TREE, V4HI_type_node,
10774 tree int_ftype_v2si
10775 = build_function_type (integer_type_node,
10776 tree_cons (NULL_TREE, V2SI_type_node,
10778 tree int_ftype_v8qi_int
10779 = build_function_type (integer_type_node,
10780 tree_cons (NULL_TREE, V8QI_type_node,
10781 tree_cons (NULL_TREE, integer_type_node,
10783 tree int_ftype_v4hi_int
10784 = build_function_type (integer_type_node,
10785 tree_cons (NULL_TREE, V4HI_type_node,
10786 tree_cons (NULL_TREE, integer_type_node,
10788 tree int_ftype_v2si_int
10789 = build_function_type (integer_type_node,
10790 tree_cons (NULL_TREE, V2SI_type_node,
10791 tree_cons (NULL_TREE, integer_type_node,
10793 tree v8qi_ftype_v8qi_int_int
10794 = build_function_type (V8QI_type_node,
10795 tree_cons (NULL_TREE, V8QI_type_node,
10796 tree_cons (NULL_TREE, integer_type_node,
10797 tree_cons (NULL_TREE,
10800 tree v4hi_ftype_v4hi_int_int
10801 = build_function_type (V4HI_type_node,
10802 tree_cons (NULL_TREE, V4HI_type_node,
10803 tree_cons (NULL_TREE, integer_type_node,
10804 tree_cons (NULL_TREE,
10807 tree v2si_ftype_v2si_int_int
10808 = build_function_type (V2SI_type_node,
10809 tree_cons (NULL_TREE, V2SI_type_node,
10810 tree_cons (NULL_TREE, integer_type_node,
10811 tree_cons (NULL_TREE,
10814 /* Miscellaneous. */
10815 tree v8qi_ftype_v4hi_v4hi
10816 = build_function_type (V8QI_type_node,
10817 tree_cons (NULL_TREE, V4HI_type_node,
10818 tree_cons (NULL_TREE, V4HI_type_node,
10820 tree v4hi_ftype_v2si_v2si
10821 = build_function_type (V4HI_type_node,
10822 tree_cons (NULL_TREE, V2SI_type_node,
10823 tree_cons (NULL_TREE, V2SI_type_node,
10825 tree v2si_ftype_v4hi_v4hi
10826 = build_function_type (V2SI_type_node,
10827 tree_cons (NULL_TREE, V4HI_type_node,
10828 tree_cons (NULL_TREE, V4HI_type_node,
10830 tree v2si_ftype_v8qi_v8qi
10831 = build_function_type (V2SI_type_node,
10832 tree_cons (NULL_TREE, V8QI_type_node,
10833 tree_cons (NULL_TREE, V8QI_type_node,
10835 tree v4hi_ftype_v4hi_di
10836 = build_function_type (V4HI_type_node,
10837 tree_cons (NULL_TREE, V4HI_type_node,
10838 tree_cons (NULL_TREE,
10839 long_long_integer_type_node,
10841 tree v2si_ftype_v2si_di
10842 = build_function_type (V2SI_type_node,
10843 tree_cons (NULL_TREE, V2SI_type_node,
10844 tree_cons (NULL_TREE,
10845 long_long_integer_type_node,
10847 tree void_ftype_int_int
10848 = build_function_type (void_type_node,
10849 tree_cons (NULL_TREE, integer_type_node,
10850 tree_cons (NULL_TREE, integer_type_node,
10853 = build_function_type (long_long_unsigned_type_node, endlink);
10855 = build_function_type (long_long_integer_type_node,
10856 tree_cons (NULL_TREE, V8QI_type_node,
10859 = build_function_type (long_long_integer_type_node,
10860 tree_cons (NULL_TREE, V4HI_type_node,
10863 = build_function_type (long_long_integer_type_node,
10864 tree_cons (NULL_TREE, V2SI_type_node,
10866 tree v2si_ftype_v4hi
10867 = build_function_type (V2SI_type_node,
10868 tree_cons (NULL_TREE, V4HI_type_node,
10870 tree v4hi_ftype_v8qi
10871 = build_function_type (V4HI_type_node,
10872 tree_cons (NULL_TREE, V8QI_type_node,
10875 tree di_ftype_di_v4hi_v4hi
10876 = build_function_type (long_long_unsigned_type_node,
10877 tree_cons (NULL_TREE,
10878 long_long_unsigned_type_node,
10879 tree_cons (NULL_TREE, V4HI_type_node,
10880 tree_cons (NULL_TREE,
10884 tree di_ftype_v4hi_v4hi
10885 = build_function_type (long_long_unsigned_type_node,
10886 tree_cons (NULL_TREE, V4HI_type_node,
10887 tree_cons (NULL_TREE, V4HI_type_node,
10890 /* Normal vector binops. */
10891 tree v8qi_ftype_v8qi_v8qi
10892 = build_function_type (V8QI_type_node,
10893 tree_cons (NULL_TREE, V8QI_type_node,
10894 tree_cons (NULL_TREE, V8QI_type_node,
10896 tree v4hi_ftype_v4hi_v4hi
10897 = build_function_type (V4HI_type_node,
10898 tree_cons (NULL_TREE, V4HI_type_node,
10899 tree_cons (NULL_TREE, V4HI_type_node,
10901 tree v2si_ftype_v2si_v2si
10902 = build_function_type (V2SI_type_node,
10903 tree_cons (NULL_TREE, V2SI_type_node,
10904 tree_cons (NULL_TREE, V2SI_type_node,
10906 tree di_ftype_di_di
10907 = build_function_type (long_long_unsigned_type_node,
10908 tree_cons (NULL_TREE, long_long_unsigned_type_node,
10909 tree_cons (NULL_TREE,
10910 long_long_unsigned_type_node,
10913 /* Add all builtins that are more or less simple operations on two
10915 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10917 /* Use one of the operands; the target can have a different mode for
10918 mask-generating compares. */
10919 enum machine_mode mode;
10925 mode = insn_data[d->icode].operand[1].mode;
10930 type = v8qi_ftype_v8qi_v8qi;
10933 type = v4hi_ftype_v4hi_v4hi;
10936 type = v2si_ftype_v2si_v2si;
10939 type = di_ftype_di_di;
10946 def_mbuiltin (d->mask, d->name, type, d->code);
10949 /* Add the remaining MMX insns with somewhat more complicated types. */
10950 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
10951 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
10952 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
10954 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
10955 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
10956 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
10957 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
10958 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
10959 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
10961 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
10962 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
10963 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
10964 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
10965 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
10966 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
10968 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
10969 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
10970 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
10971 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
10972 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
10973 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
10975 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
10976 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
10977 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
10978 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
10979 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
10980 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
10982 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
10984 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
10985 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
10986 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
10987 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
10989 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
10990 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
10991 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
10992 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
10993 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
10994 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
10995 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
10996 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
10997 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
10999 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
11000 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
11001 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
11003 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
11004 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
11005 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
11007 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
11008 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
11009 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
11010 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
11011 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
11012 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
11014 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
11015 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
11016 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
11017 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
11018 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
11019 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
11020 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
11021 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
11022 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
11023 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
11024 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
11025 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
11027 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
11028 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
11029 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
11030 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
11032 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
11033 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
11034 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
11035 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
11036 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
11037 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
11038 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
11042 arm_init_builtins (void)
11044 if (TARGET_REALLY_IWMMXT)
11045 arm_init_iwmmxt_builtins ();
11048 /* Errors in the source file can cause expand_expr to return const0_rtx
11049 where we expect a vector. To avoid crashing, use one of the vector
11050 clear instructions. */
11053 safe_vector_operand (rtx x, enum machine_mode mode)
11055 if (x != const0_rtx)
11057 x = gen_reg_rtx (mode);
11059 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
11060 : gen_rtx_SUBREG (DImode, x, 0)));
11064 /* Subroutine of arm_expand_builtin to take care of binop insns. */
11067 arm_expand_binop_builtin (enum insn_code icode,
11068 tree arglist, rtx target)
11071 tree arg0 = TREE_VALUE (arglist);
11072 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11073 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11074 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11075 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11076 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11077 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11079 if (VECTOR_MODE_P (mode0))
11080 op0 = safe_vector_operand (op0, mode0);
11081 if (VECTOR_MODE_P (mode1))
11082 op1 = safe_vector_operand (op1, mode1);
11085 || GET_MODE (target) != tmode
11086 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11087 target = gen_reg_rtx (tmode);
11089 /* In case the insn wants input operands in modes different from
11090 the result, abort. */
11091 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
11094 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11095 op0 = copy_to_mode_reg (mode0, op0);
11096 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11097 op1 = copy_to_mode_reg (mode1, op1);
11099 pat = GEN_FCN (icode) (target, op0, op1);
11106 /* Subroutine of arm_expand_builtin to take care of unop insns. */
11109 arm_expand_unop_builtin (enum insn_code icode,
11110 tree arglist, rtx target, int do_load)
11113 tree arg0 = TREE_VALUE (arglist);
11114 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11115 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11116 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11119 || GET_MODE (target) != tmode
11120 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11121 target = gen_reg_rtx (tmode);
11123 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
11126 if (VECTOR_MODE_P (mode0))
11127 op0 = safe_vector_operand (op0, mode0);
11129 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11130 op0 = copy_to_mode_reg (mode0, op0);
11133 pat = GEN_FCN (icode) (target, op0);
11140 /* Expand an expression EXP that calls a built-in function,
11141 with result going to TARGET if that's convenient
11142 (and in mode MODE if that's convenient).
11143 SUBTARGET may be used as the target for computing one of EXP's operands.
11144 IGNORE is nonzero if the value is to be ignored. */
11147 arm_expand_builtin (tree exp,
11149 rtx subtarget ATTRIBUTE_UNUSED,
11150 enum machine_mode mode ATTRIBUTE_UNUSED,
11151 int ignore ATTRIBUTE_UNUSED)
11153 const struct builtin_description * d;
11154 enum insn_code icode;
11155 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
11156 tree arglist = TREE_OPERAND (exp, 1);
11164 int fcode = DECL_FUNCTION_CODE (fndecl);
11166 enum machine_mode tmode;
11167 enum machine_mode mode0;
11168 enum machine_mode mode1;
11169 enum machine_mode mode2;
11173 case ARM_BUILTIN_TEXTRMSB:
11174 case ARM_BUILTIN_TEXTRMUB:
11175 case ARM_BUILTIN_TEXTRMSH:
11176 case ARM_BUILTIN_TEXTRMUH:
11177 case ARM_BUILTIN_TEXTRMSW:
11178 case ARM_BUILTIN_TEXTRMUW:
11179 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
11180 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
11181 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
11182 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
11183 : CODE_FOR_iwmmxt_textrmw);
11185 arg0 = TREE_VALUE (arglist);
11186 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11187 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11188 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11189 tmode = insn_data[icode].operand[0].mode;
11190 mode0 = insn_data[icode].operand[1].mode;
11191 mode1 = insn_data[icode].operand[2].mode;
11193 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11194 op0 = copy_to_mode_reg (mode0, op0);
11195 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11197 /* @@@ better error message */
11198 error ("selector must be an immediate");
11199 return gen_reg_rtx (tmode);
11202 || GET_MODE (target) != tmode
11203 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11204 target = gen_reg_rtx (tmode);
11205 pat = GEN_FCN (icode) (target, op0, op1);
11211 case ARM_BUILTIN_TINSRB:
11212 case ARM_BUILTIN_TINSRH:
11213 case ARM_BUILTIN_TINSRW:
11214 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
11215 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
11216 : CODE_FOR_iwmmxt_tinsrw);
11217 arg0 = TREE_VALUE (arglist);
11218 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11219 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11220 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11221 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11222 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11223 tmode = insn_data[icode].operand[0].mode;
11224 mode0 = insn_data[icode].operand[1].mode;
11225 mode1 = insn_data[icode].operand[2].mode;
11226 mode2 = insn_data[icode].operand[3].mode;
11228 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11229 op0 = copy_to_mode_reg (mode0, op0);
11230 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11231 op1 = copy_to_mode_reg (mode1, op1);
11232 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11234 /* @@@ better error message */
11235 error ("selector must be an immediate");
11239 || GET_MODE (target) != tmode
11240 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11241 target = gen_reg_rtx (tmode);
11242 pat = GEN_FCN (icode) (target, op0, op1, op2);
11248 case ARM_BUILTIN_SETWCX:
11249 arg0 = TREE_VALUE (arglist);
11250 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11251 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11252 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11253 emit_insn (gen_iwmmxt_tmcr (op0, op1));
11256 case ARM_BUILTIN_GETWCX:
11257 arg0 = TREE_VALUE (arglist);
11258 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11259 target = gen_reg_rtx (SImode);
11260 emit_insn (gen_iwmmxt_tmrc (target, op0));
11263 case ARM_BUILTIN_WSHUFH:
11264 icode = CODE_FOR_iwmmxt_wshufh;
11265 arg0 = TREE_VALUE (arglist);
11266 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11267 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11268 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11269 tmode = insn_data[icode].operand[0].mode;
11270 mode1 = insn_data[icode].operand[1].mode;
11271 mode2 = insn_data[icode].operand[2].mode;
11273 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
11274 op0 = copy_to_mode_reg (mode1, op0);
11275 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
11277 /* @@@ better error message */
11278 error ("mask must be an immediate");
11282 || GET_MODE (target) != tmode
11283 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11284 target = gen_reg_rtx (tmode);
11285 pat = GEN_FCN (icode) (target, op0, op1);
11291 case ARM_BUILTIN_WSADB:
11292 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
11293 case ARM_BUILTIN_WSADH:
11294 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
11295 case ARM_BUILTIN_WSADBZ:
11296 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
11297 case ARM_BUILTIN_WSADHZ:
11298 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
11300 /* Several three-argument builtins. */
11301 case ARM_BUILTIN_WMACS:
11302 case ARM_BUILTIN_WMACU:
11303 case ARM_BUILTIN_WALIGN:
11304 case ARM_BUILTIN_TMIA:
11305 case ARM_BUILTIN_TMIAPH:
11306 case ARM_BUILTIN_TMIATT:
11307 case ARM_BUILTIN_TMIATB:
11308 case ARM_BUILTIN_TMIABT:
11309 case ARM_BUILTIN_TMIABB:
11310 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
11311 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
11312 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
11313 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
11314 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
11315 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
11316 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
11317 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
11318 : CODE_FOR_iwmmxt_walign);
11319 arg0 = TREE_VALUE (arglist);
11320 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11321 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11322 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11323 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11324 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11325 tmode = insn_data[icode].operand[0].mode;
11326 mode0 = insn_data[icode].operand[1].mode;
11327 mode1 = insn_data[icode].operand[2].mode;
11328 mode2 = insn_data[icode].operand[3].mode;
11330 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11331 op0 = copy_to_mode_reg (mode0, op0);
11332 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11333 op1 = copy_to_mode_reg (mode1, op1);
11334 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11335 op2 = copy_to_mode_reg (mode2, op2);
11337 || GET_MODE (target) != tmode
11338 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11339 target = gen_reg_rtx (tmode);
11340 pat = GEN_FCN (icode) (target, op0, op1, op2);
11346 case ARM_BUILTIN_WZERO:
11347 target = gen_reg_rtx (DImode);
11348 emit_insn (gen_iwmmxt_clrdi (target));
11355 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11356 if (d->code == (const enum arm_builtins) fcode)
11357 return arm_expand_binop_builtin (d->icode, arglist, target);
11359 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11360 if (d->code == (const enum arm_builtins) fcode)
11361 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
11363 /* @@@ Should really do something sensible here. */
11367 /* Recursively search through all of the blocks in a function
11368 checking to see if any of the variables created in that
11369 function match the RTX called 'orig'. If they do then
11370 replace them with the RTX called 'new'. */
11372 replace_symbols_in_block (tree block, rtx orig, rtx new)
11374 for (; block; block = BLOCK_CHAIN (block))
11378 if (!TREE_USED (block))
11381 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
11383 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
11384 || DECL_IGNORED_P (sym)
11385 || TREE_CODE (sym) != VAR_DECL
11386 || DECL_EXTERNAL (sym)
11387 || !rtx_equal_p (DECL_RTL (sym), orig)
11391 SET_DECL_RTL (sym, new);
11394 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
11398 /* Return the number (counting from 0) of
11399 the least significant set bit in MASK. */
11402 number_of_first_bit_set (int mask)
11407 (mask & (1 << bit)) == 0;
11414 /* Generate code to return from a thumb function.
11415 If 'reg_containing_return_addr' is -1, then the return address is
11416 actually on the stack, at the stack pointer. */
11418 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
11420 unsigned regs_available_for_popping;
11421 unsigned regs_to_pop;
11423 unsigned available;
11427 int restore_a4 = FALSE;
11429 /* Compute the registers we need to pop. */
11433 /* There is an assumption here, that if eh_ofs is not NULL, the
11434 normal return address will have been pushed. */
11435 if (reg_containing_return_addr == -1 || eh_ofs)
11437 /* When we are generating a return for __builtin_eh_return,
11438 reg_containing_return_addr must specify the return regno. */
11439 if (eh_ofs && reg_containing_return_addr == -1)
11442 regs_to_pop |= 1 << LR_REGNUM;
11446 if (TARGET_BACKTRACE)
11448 /* Restore the (ARM) frame pointer and stack pointer. */
11449 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
11453 /* If there is nothing to pop then just emit the BX instruction and
11455 if (pops_needed == 0)
11458 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11460 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11463 /* Otherwise if we are not supporting interworking and we have not created
11464 a backtrace structure and the function was not entered in ARM mode then
11465 just pop the return address straight into the PC. */
11466 else if (!TARGET_INTERWORK
11467 && !TARGET_BACKTRACE
11468 && !is_called_in_ARM_mode (current_function_decl))
11472 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
11473 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11474 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11477 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
11482 /* Find out how many of the (return) argument registers we can corrupt. */
11483 regs_available_for_popping = 0;
11485 /* If returning via __builtin_eh_return, the bottom three registers
11486 all contain information needed for the return. */
11492 /* If we can deduce the registers used from the function's
11493 return value. This is more reliable that examining
11494 regs_ever_live[] because that will be set if the register is
11495 ever used in the function, not just if the register is used
11496 to hold a return value. */
11498 if (current_function_return_rtx != 0)
11499 mode = GET_MODE (current_function_return_rtx);
11502 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11504 size = GET_MODE_SIZE (mode);
11508 /* In a void function we can use any argument register.
11509 In a function that returns a structure on the stack
11510 we can use the second and third argument registers. */
11511 if (mode == VOIDmode)
11512 regs_available_for_popping =
11513 (1 << ARG_REGISTER (1))
11514 | (1 << ARG_REGISTER (2))
11515 | (1 << ARG_REGISTER (3));
11517 regs_available_for_popping =
11518 (1 << ARG_REGISTER (2))
11519 | (1 << ARG_REGISTER (3));
11521 else if (size <= 4)
11522 regs_available_for_popping =
11523 (1 << ARG_REGISTER (2))
11524 | (1 << ARG_REGISTER (3));
11525 else if (size <= 8)
11526 regs_available_for_popping =
11527 (1 << ARG_REGISTER (3));
11530 /* Match registers to be popped with registers into which we pop them. */
11531 for (available = regs_available_for_popping,
11532 required = regs_to_pop;
11533 required != 0 && available != 0;
11534 available &= ~(available & - available),
11535 required &= ~(required & - required))
11538 /* If we have any popping registers left over, remove them. */
11540 regs_available_for_popping &= ~available;
11542 /* Otherwise if we need another popping register we can use
11543 the fourth argument register. */
11544 else if (pops_needed)
11546 /* If we have not found any free argument registers and
11547 reg a4 contains the return address, we must move it. */
11548 if (regs_available_for_popping == 0
11549 && reg_containing_return_addr == LAST_ARG_REGNUM)
11551 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
11552 reg_containing_return_addr = LR_REGNUM;
11554 else if (size > 12)
11556 /* Register a4 is being used to hold part of the return value,
11557 but we have dire need of a free, low register. */
11560 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
11563 if (reg_containing_return_addr != LAST_ARG_REGNUM)
11565 /* The fourth argument register is available. */
11566 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
11572 /* Pop as many registers as we can. */
11573 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
11574 regs_available_for_popping);
11576 /* Process the registers we popped. */
11577 if (reg_containing_return_addr == -1)
11579 /* The return address was popped into the lowest numbered register. */
11580 regs_to_pop &= ~(1 << LR_REGNUM);
11582 reg_containing_return_addr =
11583 number_of_first_bit_set (regs_available_for_popping);
11585 /* Remove this register for the mask of available registers, so that
11586 the return address will not be corrupted by further pops. */
11587 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
11590 /* If we popped other registers then handle them here. */
11591 if (regs_available_for_popping)
11595 /* Work out which register currently contains the frame pointer. */
11596 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
11598 /* Move it into the correct place. */
11599 asm_fprintf (f, "\tmov\t%r, %r\n",
11600 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
11602 /* (Temporarily) remove it from the mask of popped registers. */
11603 regs_available_for_popping &= ~(1 << frame_pointer);
11604 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
11606 if (regs_available_for_popping)
11610 /* We popped the stack pointer as well,
11611 find the register that contains it. */
11612 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
11614 /* Move it into the stack register. */
11615 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
11617 /* At this point we have popped all necessary registers, so
11618 do not worry about restoring regs_available_for_popping
11619 to its correct value:
11621 assert (pops_needed == 0)
11622 assert (regs_available_for_popping == (1 << frame_pointer))
11623 assert (regs_to_pop == (1 << STACK_POINTER)) */
11627 /* Since we have just move the popped value into the frame
11628 pointer, the popping register is available for reuse, and
11629 we know that we still have the stack pointer left to pop. */
11630 regs_available_for_popping |= (1 << frame_pointer);
11634 /* If we still have registers left on the stack, but we no longer have
11635 any registers into which we can pop them, then we must move the return
11636 address into the link register and make available the register that
11638 if (regs_available_for_popping == 0 && pops_needed > 0)
11640 regs_available_for_popping |= 1 << reg_containing_return_addr;
11642 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
11643 reg_containing_return_addr);
11645 reg_containing_return_addr = LR_REGNUM;
11648 /* If we have registers left on the stack then pop some more.
11649 We know that at most we will want to pop FP and SP. */
11650 if (pops_needed > 0)
11655 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
11656 regs_available_for_popping);
11658 /* We have popped either FP or SP.
11659 Move whichever one it is into the correct register. */
11660 popped_into = number_of_first_bit_set (regs_available_for_popping);
11661 move_to = number_of_first_bit_set (regs_to_pop);
11663 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
11665 regs_to_pop &= ~(1 << move_to);
11670 /* If we still have not popped everything then we must have only
11671 had one register available to us and we are now popping the SP. */
11672 if (pops_needed > 0)
11676 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
11677 regs_available_for_popping);
11679 popped_into = number_of_first_bit_set (regs_available_for_popping);
11681 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
11683 assert (regs_to_pop == (1 << STACK_POINTER))
11684 assert (pops_needed == 1)
11688 /* If necessary restore the a4 register. */
11691 if (reg_containing_return_addr != LR_REGNUM)
11693 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
11694 reg_containing_return_addr = LR_REGNUM;
11697 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
11701 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11703 /* Return to caller. */
11704 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11707 /* Emit code to push or pop registers to or from the stack. F is the
11708 assembly file. MASK is the registers to push or pop. PUSH is
11709 non-zero if we should push, and zero if we should pop. For debugging
11710 output, if pushing, adjust CFA_OFFSET by the amount of space added
11711 to the stack. REAL_REGS should have the same number of bits set as
11712 MASK, and will be used instead (in the same order) to describe which
11713 registers were saved - this is used to mark the save slots when we
11714 push high registers after moving them to low registers. */
11716 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
11719 int lo_mask = mask & 0xFF;
11720 int pushed_words = 0;
11722 if (lo_mask == 0 && !push && (mask & (1 << 15)))
11724 /* Special case. Do not generate a POP PC statement here, do it in
11726 thumb_exit (f, -1, NULL_RTX);
11730 fprintf (f, "\t%s\t{", push ? "push" : "pop");
11732 /* Look at the low registers first. */
11733 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
11737 asm_fprintf (f, "%r", regno);
11739 if ((lo_mask & ~1) != 0)
11746 if (push && (mask & (1 << LR_REGNUM)))
11748 /* Catch pushing the LR. */
11752 asm_fprintf (f, "%r", LR_REGNUM);
11756 else if (!push && (mask & (1 << PC_REGNUM)))
11758 /* Catch popping the PC. */
11759 if (TARGET_INTERWORK || TARGET_BACKTRACE)
11761 /* The PC is never poped directly, instead
11762 it is popped into r3 and then BX is used. */
11763 fprintf (f, "}\n");
11765 thumb_exit (f, -1, NULL_RTX);
11774 asm_fprintf (f, "%r", PC_REGNUM);
11778 fprintf (f, "}\n");
11780 if (push && pushed_words && dwarf2out_do_frame ())
11782 char *l = dwarf2out_cfi_label ();
11783 int pushed_mask = real_regs;
11785 *cfa_offset += pushed_words * 4;
11786 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
11789 pushed_mask = real_regs;
11790 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
11792 if (pushed_mask & 1)
11793 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
11799 thumb_final_prescan_insn (rtx insn)
11801 if (flag_print_asm_name)
11802 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
11803 INSN_ADDRESSES (INSN_UID (insn)));
11807 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
11809 unsigned HOST_WIDE_INT mask = 0xff;
11812 if (val == 0) /* XXX */
11815 for (i = 0; i < 25; i++)
11816 if ((val & (mask << i)) == val)
11822 /* Returns nonzero if the current function contains,
11823 or might contain a far jump. */
11825 thumb_far_jump_used_p (int in_prologue)
11829 /* This test is only important for leaf functions. */
11830 /* assert (!leaf_function_p ()); */
11832 /* If we have already decided that far jumps may be used,
11833 do not bother checking again, and always return true even if
11834 it turns out that they are not being used. Once we have made
11835 the decision that far jumps are present (and that hence the link
11836 register will be pushed onto the stack) we cannot go back on it. */
11837 if (cfun->machine->far_jump_used)
11840 /* If this function is not being called from the prologue/epilogue
11841 generation code then it must be being called from the
11842 INITIAL_ELIMINATION_OFFSET macro. */
11845 /* In this case we know that we are being asked about the elimination
11846 of the arg pointer register. If that register is not being used,
11847 then there are no arguments on the stack, and we do not have to
11848 worry that a far jump might force the prologue to push the link
11849 register, changing the stack offsets. In this case we can just
11850 return false, since the presence of far jumps in the function will
11851 not affect stack offsets.
11853 If the arg pointer is live (or if it was live, but has now been
11854 eliminated and so set to dead) then we do have to test to see if
11855 the function might contain a far jump. This test can lead to some
11856 false negatives, since before reload is completed, then length of
11857 branch instructions is not known, so gcc defaults to returning their
11858 longest length, which in turn sets the far jump attribute to true.
11860 A false negative will not result in bad code being generated, but it
11861 will result in a needless push and pop of the link register. We
11862 hope that this does not occur too often. */
11863 if (regs_ever_live [ARG_POINTER_REGNUM])
11864 cfun->machine->arg_pointer_live = 1;
11865 else if (!cfun->machine->arg_pointer_live)
11869 /* Check to see if the function contains a branch
11870 insn with the far jump attribute set. */
11871 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11873 if (GET_CODE (insn) == JUMP_INSN
11874 /* Ignore tablejump patterns. */
11875 && GET_CODE (PATTERN (insn)) != ADDR_VEC
11876 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
11877 && get_attr_far_jump (insn) == FAR_JUMP_YES
11880 /* Record the fact that we have decided that
11881 the function does use far jumps. */
11882 cfun->machine->far_jump_used = 1;
11890 /* Return nonzero if FUNC must be entered in ARM mode. */
11892 is_called_in_ARM_mode (tree func)
11894 if (TREE_CODE (func) != FUNCTION_DECL)
11897 /* Ignore the problem about functions whoes address is taken. */
11898 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
11902 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
11908 /* The bits which aren't usefully expanded as rtl. */
11910 thumb_unexpanded_epilogue (void)
11913 int live_regs_mask = 0;
11914 int high_regs_pushed = 0;
11915 int leaf_function = leaf_function_p ();
11916 int had_to_push_lr;
11917 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
11919 if (return_used_this_function)
11922 if (IS_NAKED (arm_current_func_type ()))
11925 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11926 if (THUMB_REG_PUSHED_P (regno))
11927 live_regs_mask |= 1 << regno;
11929 for (regno = 8; regno < 13; regno++)
11930 if (THUMB_REG_PUSHED_P (regno))
11931 high_regs_pushed++;
11933 /* The prolog may have pushed some high registers to use as
11934 work registers. eg the testsuite file:
11935 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
11936 compiles to produce:
11937 push {r4, r5, r6, r7, lr}
11941 as part of the prolog. We have to undo that pushing here. */
11943 if (high_regs_pushed)
11945 int mask = live_regs_mask;
11951 /* If we can deduce the registers used from the function's return value.
11952 This is more reliable that examining regs_ever_live[] because that
11953 will be set if the register is ever used in the function, not just if
11954 the register is used to hold a return value. */
11956 if (current_function_return_rtx != 0)
11957 mode = GET_MODE (current_function_return_rtx);
11960 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11962 size = GET_MODE_SIZE (mode);
11964 /* Unless we are returning a type of size > 12 register r3 is
11970 /* Oh dear! We have no low registers into which we can pop
11973 ("no low registers available for popping high registers");
11975 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
11976 if (THUMB_REG_PUSHED_P (next_hi_reg))
11979 while (high_regs_pushed)
11981 /* Find lo register(s) into which the high register(s) can
11983 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11985 if (mask & (1 << regno))
11986 high_regs_pushed--;
11987 if (high_regs_pushed == 0)
11991 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
11993 /* Pop the values into the low register(s). */
11994 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
11996 /* Move the value(s) into the high registers. */
11997 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11999 if (mask & (1 << regno))
12001 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
12004 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
12005 if (THUMB_REG_PUSHED_P (next_hi_reg))
12012 had_to_push_lr = (live_regs_mask || !leaf_function
12013 || thumb_far_jump_used_p (1));
12015 if (TARGET_BACKTRACE
12016 && ((live_regs_mask & 0xFF) == 0)
12017 && regs_ever_live [LAST_ARG_REGNUM] != 0)
12019 /* The stack backtrace structure creation code had to
12020 push R7 in order to get a work register, so we pop
12022 live_regs_mask |= (1 << LAST_LO_REGNUM);
12025 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
12028 && !is_called_in_ARM_mode (current_function_decl)
12030 live_regs_mask |= 1 << PC_REGNUM;
12032 /* Either no argument registers were pushed or a backtrace
12033 structure was created which includes an adjusted stack
12034 pointer, so just pop everything. */
12035 if (live_regs_mask)
12036 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12040 thumb_exit (asm_out_file, 2, eh_ofs);
12041 /* We have either just popped the return address into the
12042 PC or it is was kept in LR for the entire function or
12043 it is still on the stack because we do not want to
12044 return by doing a pop {pc}. */
12045 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
12046 thumb_exit (asm_out_file,
12048 && is_called_in_ARM_mode (current_function_decl)) ?
12049 -1 : LR_REGNUM, NULL_RTX);
12053 /* Pop everything but the return address. */
12054 live_regs_mask &= ~(1 << PC_REGNUM);
12056 if (live_regs_mask)
12057 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12060 if (had_to_push_lr)
12061 /* Get the return address into a temporary register. */
12062 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
12063 1 << LAST_ARG_REGNUM);
12065 /* Remove the argument registers that were pushed onto the stack. */
12066 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
12067 SP_REGNUM, SP_REGNUM,
12068 current_function_pretend_args_size);
12071 thumb_exit (asm_out_file, 2, eh_ofs);
12073 thumb_exit (asm_out_file,
12074 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
12080 /* Functions to save and restore machine-specific function data. */
12081 static struct machine_function *
12082 arm_init_machine_status (void)
12084 struct machine_function *machine;
12085 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
12087 #if ARM_FT_UNKNOWN != 0
12088 machine->func_type = ARM_FT_UNKNOWN;
12093 /* Return an RTX indicating where the return address to the
12094 calling function can be found. */
12096 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
12101 if (TARGET_APCS_32)
12102 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
12105 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
12106 GEN_INT (RETURN_ADDR_MASK26));
12107 return get_func_hard_reg_initial_val (cfun, lr);
12111 /* Do anything needed before RTL is emitted for each function. */
12113 arm_init_expanders (void)
12115 /* Arrange to initialize and mark the machine per-function status. */
12116 init_machine_status = arm_init_machine_status;
12120 thumb_get_frame_size (void)
12124 int base_size = ROUND_UP_WORD (get_frame_size ());
12125 int count_regs = 0;
12126 int entry_size = 0;
12129 if (! TARGET_THUMB)
12132 if (! TARGET_ATPCS)
12135 /* We need to know if we are a leaf function. Unfortunately, it
12136 is possible to be called after start_sequence has been called,
12137 which causes get_insns to return the insns for the sequence,
12138 not the function, which will cause leaf_function_p to return
12139 the incorrect result.
12141 To work around this, we cache the computed frame size. This
12142 works because we will only be calling RTL expanders that need
12143 to know about leaf functions once reload has completed, and the
12144 frame size cannot be changed after that time, so we can safely
12145 use the cached value. */
12147 if (reload_completed)
12148 return cfun->machine->frame_size;
12150 leaf = leaf_function_p ();
12152 /* A leaf function does not need any stack alignment if it has nothing
12154 if (leaf && base_size == 0)
12156 cfun->machine->frame_size = 0;
12160 /* We know that SP will be word aligned on entry, and we must
12161 preserve that condition at any subroutine call. But those are
12162 the only constraints. */
12164 /* Space for variadic functions. */
12165 if (current_function_pretend_args_size)
12166 entry_size += current_function_pretend_args_size;
12168 /* Space for pushed lo registers. */
12169 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12170 if (THUMB_REG_PUSHED_P (regno))
12173 /* Space for backtrace structure. */
12174 if (TARGET_BACKTRACE)
12176 if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0)
12182 if (count_regs || !leaf || thumb_far_jump_used_p (1))
12183 count_regs++; /* LR */
12185 entry_size += count_regs * 4;
12188 /* Space for pushed hi regs. */
12189 for (regno = 8; regno < 13; regno++)
12190 if (THUMB_REG_PUSHED_P (regno))
12193 entry_size += count_regs * 4;
12195 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12197 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12200 cfun->machine->frame_size = base_size;
12205 /* Generate the rest of a function's prologue. */
12207 thumb_expand_prologue (void)
12211 HOST_WIDE_INT amount = (thumb_get_frame_size ()
12212 + current_function_outgoing_args_size);
12213 unsigned long func_type;
12215 func_type = arm_current_func_type ();
12217 /* Naked functions don't have prologues. */
12218 if (IS_NAKED (func_type))
12221 if (IS_INTERRUPT (func_type))
12223 error ("interrupt Service Routines cannot be coded in Thumb mode");
12227 if (frame_pointer_needed)
12229 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
12230 RTX_FRAME_RELATED_P (insn) = 1;
12235 amount = ROUND_UP_WORD (amount);
12239 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12240 GEN_INT (- amount)));
12241 RTX_FRAME_RELATED_P (insn) = 1;
12248 /* The stack decrement is too big for an immediate value in a single
12249 insn. In theory we could issue multiple subtracts, but after
12250 three of them it becomes more space efficient to place the full
12251 value in the constant pool and load into a register. (Also the
12252 ARM debugger really likes to see only one stack decrement per
12253 function). So instead we look for a scratch register into which
12254 we can load the decrement, and then we subtract this from the
12255 stack pointer. Unfortunately on the thumb the only available
12256 scratch registers are the argument registers, and we cannot use
12257 these as they may hold arguments to the function. Instead we
12258 attempt to locate a call preserved register which is used by this
12259 function. If we can find one, then we know that it will have
12260 been pushed at the start of the prologue and so we can corrupt
12262 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
12263 if (THUMB_REG_PUSHED_P (regno)
12264 && !(frame_pointer_needed
12265 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
12268 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
12270 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
12272 /* Choose an arbitrary, non-argument low register. */
12273 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
12275 /* Save it by copying it into a high, scratch register. */
12276 emit_insn (gen_movsi (spare, reg));
12277 /* Add a USE to stop propagate_one_insn() from barfing. */
12278 emit_insn (gen_prologue_use (spare));
12280 /* Decrement the stack. */
12281 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12282 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
12283 stack_pointer_rtx, reg));
12284 RTX_FRAME_RELATED_P (insn) = 1;
12285 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
12286 plus_constant (stack_pointer_rtx,
12287 GEN_INT (- amount)));
12288 RTX_FRAME_RELATED_P (dwarf) = 1;
12290 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
12293 /* Restore the low register's original value. */
12294 emit_insn (gen_movsi (reg, spare));
12296 /* Emit a USE of the restored scratch register, so that flow
12297 analysis will not consider the restore redundant. The
12298 register won't be used again in this function and isn't
12299 restored by the epilogue. */
12300 emit_insn (gen_prologue_use (reg));
12304 reg = gen_rtx (REG, SImode, regno);
12306 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12308 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
12309 stack_pointer_rtx, reg));
12310 RTX_FRAME_RELATED_P (insn) = 1;
12311 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
12312 plus_constant (stack_pointer_rtx,
12313 GEN_INT (- amount)));
12314 RTX_FRAME_RELATED_P (dwarf) = 1;
12316 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
12322 if (current_function_profile || TARGET_NO_SCHED_PRO)
12323 emit_insn (gen_blockage ());
12327 thumb_expand_epilogue (void)
12329 HOST_WIDE_INT amount = (thumb_get_frame_size ()
12330 + current_function_outgoing_args_size);
12333 /* Naked functions don't have prologues. */
12334 if (IS_NAKED (arm_current_func_type ()))
12337 if (frame_pointer_needed)
12338 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
12341 amount = ROUND_UP_WORD (amount);
12344 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12345 GEN_INT (amount)));
12348 /* r3 is always free in the epilogue. */
12349 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
12351 emit_insn (gen_movsi (reg, GEN_INT (amount)));
12352 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
12356 /* Emit a USE (stack_pointer_rtx), so that
12357 the stack adjustment will not be deleted. */
12358 emit_insn (gen_prologue_use (stack_pointer_rtx));
12360 if (current_function_profile || TARGET_NO_SCHED_PRO)
12361 emit_insn (gen_blockage ());
12363 /* Emit a clobber for each insn that will be restored in the epilogue,
12364 so that flow2 will get register lifetimes correct. */
12365 for (regno = 0; regno < 13; regno++)
12366 if (regs_ever_live[regno] && !call_used_regs[regno])
12367 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
12369 if (! regs_ever_live[LR_REGNUM])
12370 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
12374 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12376 int live_regs_mask = 0;
12377 int high_regs_pushed = 0;
12378 int cfa_offset = 0;
12381 if (IS_NAKED (arm_current_func_type ()))
12384 if (is_called_in_ARM_mode (current_function_decl))
12388 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
12390 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
12392 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12394 /* Generate code sequence to switch us into Thumb mode. */
12395 /* The .code 32 directive has already been emitted by
12396 ASM_DECLARE_FUNCTION_NAME. */
12397 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
12398 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
12400 /* Generate a label, so that the debugger will notice the
12401 change in instruction sets. This label is also used by
12402 the assembler to bypass the ARM code when this function
12403 is called from a Thumb encoded function elsewhere in the
12404 same file. Hence the definition of STUB_NAME here must
12405 agree with the definition in gas/config/tc-arm.c. */
12407 #define STUB_NAME ".real_start_of"
12409 fprintf (f, "\t.code\t16\n");
12411 if (arm_dllexport_name_p (name))
12412 name = arm_strip_name_encoding (name);
12414 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
12415 fprintf (f, "\t.thumb_func\n");
12416 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
12419 if (current_function_pretend_args_size)
12421 if (cfun->machine->uses_anonymous_args)
12425 fprintf (f, "\tpush\t{");
12427 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
12429 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
12430 regno <= LAST_ARG_REGNUM;
12432 asm_fprintf (f, "%r%s", regno,
12433 regno == LAST_ARG_REGNUM ? "" : ", ");
12435 fprintf (f, "}\n");
12438 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
12439 SP_REGNUM, SP_REGNUM,
12440 current_function_pretend_args_size);
12442 /* We don't need to record the stores for unwinding (would it
12443 help the debugger any if we did?), but record the change in
12444 the stack pointer. */
12445 if (dwarf2out_do_frame ())
12447 char *l = dwarf2out_cfi_label ();
12448 cfa_offset = cfa_offset + current_function_pretend_args_size;
12449 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
12453 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12454 if (THUMB_REG_PUSHED_P (regno))
12455 live_regs_mask |= 1 << regno;
12457 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
12458 live_regs_mask |= 1 << LR_REGNUM;
12460 if (TARGET_BACKTRACE)
12463 int work_register = 0;
12466 /* We have been asked to create a stack backtrace structure.
12467 The code looks like this:
12471 0 sub SP, #16 Reserve space for 4 registers.
12472 2 push {R7} Get a work register.
12473 4 add R7, SP, #20 Get the stack pointer before the push.
12474 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
12475 8 mov R7, PC Get hold of the start of this code plus 12.
12476 10 str R7, [SP, #16] Store it.
12477 12 mov R7, FP Get hold of the current frame pointer.
12478 14 str R7, [SP, #4] Store it.
12479 16 mov R7, LR Get hold of the current return address.
12480 18 str R7, [SP, #12] Store it.
12481 20 add R7, SP, #16 Point at the start of the backtrace structure.
12482 22 mov FP, R7 Put this value into the frame pointer. */
12484 if ((live_regs_mask & 0xFF) == 0)
12486 /* See if the a4 register is free. */
12488 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
12489 work_register = LAST_ARG_REGNUM;
12490 else /* We must push a register of our own. */
12491 live_regs_mask |= (1 << LAST_LO_REGNUM);
12494 if (work_register == 0)
12496 /* Select a register from the list that will be pushed to
12497 use as our work register. */
12498 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
12499 if ((1 << work_register) & live_regs_mask)
12504 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
12505 SP_REGNUM, SP_REGNUM);
12507 if (dwarf2out_do_frame ())
12509 char *l = dwarf2out_cfi_label ();
12510 cfa_offset = cfa_offset + 16;
12511 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
12514 if (live_regs_mask)
12515 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
12517 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
12518 if (wr & live_regs_mask)
12521 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
12522 offset + 16 + current_function_pretend_args_size);
12524 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12527 /* Make sure that the instruction fetching the PC is in the right place
12528 to calculate "start of backtrace creation code + 12". */
12529 if (live_regs_mask)
12531 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
12532 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12534 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
12535 ARM_HARD_FRAME_POINTER_REGNUM);
12536 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12541 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
12542 ARM_HARD_FRAME_POINTER_REGNUM);
12543 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12545 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
12546 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12550 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
12551 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12553 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
12555 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
12556 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
12558 else if (live_regs_mask)
12559 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
12561 for (regno = 8; regno < 13; regno++)
12562 if (THUMB_REG_PUSHED_P (regno))
12563 high_regs_pushed++;
12565 if (high_regs_pushed)
12567 int pushable_regs = 0;
12568 int mask = live_regs_mask & 0xff;
12571 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
12572 if (THUMB_REG_PUSHED_P (next_hi_reg))
12575 pushable_regs = mask;
12577 if (pushable_regs == 0)
12579 /* Desperation time -- this probably will never happen. */
12580 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
12581 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
12582 mask = 1 << LAST_ARG_REGNUM;
12585 while (high_regs_pushed > 0)
12587 int real_regs_mask = 0;
12589 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
12591 if (mask & (1 << regno))
12593 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
12595 high_regs_pushed--;
12596 real_regs_mask |= (1 << next_hi_reg);
12598 if (high_regs_pushed)
12600 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
12602 if (THUMB_REG_PUSHED_P (next_hi_reg))
12607 mask &= ~((1 << regno) - 1);
12613 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
12616 if (pushable_regs == 0
12617 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
12618 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12622 /* Handle the case of a double word load into a low register from
12623 a computed memory address. The computed address may involve a
12624 register which is overwritten by the load. */
12626 thumb_load_double_from_address (rtx *operands)
12634 if (GET_CODE (operands[0]) != REG)
12637 if (GET_CODE (operands[1]) != MEM)
12640 /* Get the memory address. */
12641 addr = XEXP (operands[1], 0);
12643 /* Work out how the memory address is computed. */
12644 switch (GET_CODE (addr))
12647 operands[2] = gen_rtx (MEM, SImode,
12648 plus_constant (XEXP (operands[1], 0), 4));
12650 if (REGNO (operands[0]) == REGNO (addr))
12652 output_asm_insn ("ldr\t%H0, %2", operands);
12653 output_asm_insn ("ldr\t%0, %1", operands);
12657 output_asm_insn ("ldr\t%0, %1", operands);
12658 output_asm_insn ("ldr\t%H0, %2", operands);
12663 /* Compute <address> + 4 for the high order load. */
12664 operands[2] = gen_rtx (MEM, SImode,
12665 plus_constant (XEXP (operands[1], 0), 4));
12667 output_asm_insn ("ldr\t%0, %1", operands);
12668 output_asm_insn ("ldr\t%H0, %2", operands);
12672 arg1 = XEXP (addr, 0);
12673 arg2 = XEXP (addr, 1);
12675 if (CONSTANT_P (arg1))
12676 base = arg2, offset = arg1;
12678 base = arg1, offset = arg2;
12680 if (GET_CODE (base) != REG)
12683 /* Catch the case of <address> = <reg> + <reg> */
12684 if (GET_CODE (offset) == REG)
12686 int reg_offset = REGNO (offset);
12687 int reg_base = REGNO (base);
12688 int reg_dest = REGNO (operands[0]);
12690 /* Add the base and offset registers together into the
12691 higher destination register. */
12692 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
12693 reg_dest + 1, reg_base, reg_offset);
12695 /* Load the lower destination register from the address in
12696 the higher destination register. */
12697 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
12698 reg_dest, reg_dest + 1);
12700 /* Load the higher destination register from its own address
12702 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
12703 reg_dest + 1, reg_dest + 1);
12707 /* Compute <address> + 4 for the high order load. */
12708 operands[2] = gen_rtx (MEM, SImode,
12709 plus_constant (XEXP (operands[1], 0), 4));
12711 /* If the computed address is held in the low order register
12712 then load the high order register first, otherwise always
12713 load the low order register first. */
12714 if (REGNO (operands[0]) == REGNO (base))
12716 output_asm_insn ("ldr\t%H0, %2", operands);
12717 output_asm_insn ("ldr\t%0, %1", operands);
12721 output_asm_insn ("ldr\t%0, %1", operands);
12722 output_asm_insn ("ldr\t%H0, %2", operands);
12728 /* With no registers to worry about we can just load the value
12730 operands[2] = gen_rtx (MEM, SImode,
12731 plus_constant (XEXP (operands[1], 0), 4));
12733 output_asm_insn ("ldr\t%H0, %2", operands);
12734 output_asm_insn ("ldr\t%0, %1", operands);
12746 thumb_output_move_mem_multiple (int n, rtx *operands)
12753 if (REGNO (operands[4]) > REGNO (operands[5]))
12756 operands[4] = operands[5];
12759 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
12760 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
12764 if (REGNO (operands[4]) > REGNO (operands[5]))
12767 operands[4] = operands[5];
12770 if (REGNO (operands[5]) > REGNO (operands[6]))
12773 operands[5] = operands[6];
12776 if (REGNO (operands[4]) > REGNO (operands[5]))
12779 operands[4] = operands[5];
12783 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
12784 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
12794 /* Routines for generating rtl. */
12796 thumb_expand_movstrqi (rtx *operands)
12798 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
12799 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
12800 HOST_WIDE_INT len = INTVAL (operands[2]);
12801 HOST_WIDE_INT offset = 0;
12805 emit_insn (gen_movmem12b (out, in, out, in));
12811 emit_insn (gen_movmem8b (out, in, out, in));
12817 rtx reg = gen_reg_rtx (SImode);
12818 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
12819 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
12826 rtx reg = gen_reg_rtx (HImode);
12827 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
12828 plus_constant (in, offset))));
12829 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
12837 rtx reg = gen_reg_rtx (QImode);
12838 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
12839 plus_constant (in, offset))));
12840 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
12846 thumb_cmp_operand (rtx op, enum machine_mode mode)
12848 return ((GET_CODE (op) == CONST_INT
12849 && INTVAL (op) < 256
12850 && INTVAL (op) >= 0)
12851 || s_register_operand (op, mode));
12855 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
12857 return (GET_CODE (op) == CONST_INT
12859 && INTVAL (op) > -256);
12862 /* Return TRUE if a result can be stored in OP without clobbering the
12863 condition code register. Prior to reload we only accept a
12864 register. After reload we have to be able to handle memory as
12865 well, since a pseudo may not get a hard reg and reload cannot
12866 handle output-reloads on jump insns.
12868 We could possibly handle mem before reload as well, but that might
12869 complicate things with the need to handle increment
12873 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
12875 return (s_register_operand (op, mode)
12876 || ((reload_in_progress || reload_completed)
12877 && memory_operand (op, mode)));
12880 /* Handle storing a half-word to memory during reload. */
12882 thumb_reload_out_hi (rtx *operands)
12884 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
12887 /* Handle reading a half-word from memory during reload. */
12889 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
12894 /* Return the length of a function name prefix
12895 that starts with the character 'c'. */
12897 arm_get_strip_length (int c)
12901 ARM_NAME_ENCODING_LENGTHS
12906 /* Return a pointer to a function's name with any
12907 and all prefix encodings stripped from it. */
12909 arm_strip_name_encoding (const char *name)
12913 while ((skip = arm_get_strip_length (* name)))
12919 /* If there is a '*' anywhere in the name's prefix, then
12920 emit the stripped name verbatim, otherwise prepend an
12921 underscore if leading underscores are being used. */
12923 arm_asm_output_labelref (FILE *stream, const char *name)
12928 while ((skip = arm_get_strip_length (* name)))
12930 verbatim |= (*name == '*');
12935 fputs (name, stream);
12937 asm_fprintf (stream, "%U%s", name);
12942 #ifdef AOF_ASSEMBLER
12943 /* Special functions only needed when producing AOF syntax assembler. */
12947 struct pic_chain * next;
12948 const char * symname;
12951 static struct pic_chain * aof_pic_chain = NULL;
12954 aof_pic_entry (rtx x)
12956 struct pic_chain ** chainp;
12959 if (aof_pic_label == NULL_RTX)
12961 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
12964 for (offset = 0, chainp = &aof_pic_chain; *chainp;
12965 offset += 4, chainp = &(*chainp)->next)
12966 if ((*chainp)->symname == XSTR (x, 0))
12967 return plus_constant (aof_pic_label, offset);
12969 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
12970 (*chainp)->next = NULL;
12971 (*chainp)->symname = XSTR (x, 0);
12972 return plus_constant (aof_pic_label, offset);
12976 aof_dump_pic_table (FILE *f)
12978 struct pic_chain * chain;
12980 if (aof_pic_chain == NULL)
12983 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
12984 PIC_OFFSET_TABLE_REGNUM,
12985 PIC_OFFSET_TABLE_REGNUM);
12986 fputs ("|x$adcons|\n", f);
12988 for (chain = aof_pic_chain; chain; chain = chain->next)
12990 fputs ("\tDCD\t", f);
12991 assemble_name (f, chain->symname);
12996 int arm_text_section_count = 1;
12999 aof_text_section (void )
13001 static char buf[100];
13002 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
13003 arm_text_section_count++);
13005 strcat (buf, ", PIC, REENTRANT");
13009 static int arm_data_section_count = 1;
13012 aof_data_section (void)
13014 static char buf[100];
13015 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
13019 /* The AOF assembler is religiously strict about declarations of
13020 imported and exported symbols, so that it is impossible to declare
13021 a function as imported near the beginning of the file, and then to
13022 export it later on. It is, however, possible to delay the decision
13023 until all the functions in the file have been compiled. To get
13024 around this, we maintain a list of the imports and exports, and
13025 delete from it any that are subsequently defined. At the end of
13026 compilation we spit the remainder of the list out before the END
13031 struct import * next;
13035 static struct import * imports_list = NULL;
13038 aof_add_import (const char *name)
13040 struct import * new;
13042 for (new = imports_list; new; new = new->next)
13043 if (new->name == name)
13046 new = (struct import *) xmalloc (sizeof (struct import));
13047 new->next = imports_list;
13048 imports_list = new;
13053 aof_delete_import (const char *name)
13055 struct import ** old;
13057 for (old = &imports_list; *old; old = & (*old)->next)
13059 if ((*old)->name == name)
13061 *old = (*old)->next;
13067 int arm_main_function = 0;
13070 aof_dump_imports (FILE *f)
13072 /* The AOF assembler needs this to cause the startup code to be extracted
13073 from the library. Brining in __main causes the whole thing to work
13075 if (arm_main_function)
13078 fputs ("\tIMPORT __main\n", f);
13079 fputs ("\tDCD __main\n", f);
13082 /* Now dump the remaining imports. */
13083 while (imports_list)
13085 fprintf (f, "\tIMPORT\t");
13086 assemble_name (f, imports_list->name);
13088 imports_list = imports_list->next;
13093 aof_globalize_label (FILE *stream, const char *name)
13095 default_globalize_label (stream, name);
13096 if (! strcmp (name, "main"))
13097 arm_main_function = 1;
13101 aof_file_start (void)
13103 fputs ("__r0\tRN\t0\n", asm_out_file);
13104 fputs ("__a1\tRN\t0\n", asm_out_file);
13105 fputs ("__a2\tRN\t1\n", asm_out_file);
13106 fputs ("__a3\tRN\t2\n", asm_out_file);
13107 fputs ("__a4\tRN\t3\n", asm_out_file);
13108 fputs ("__v1\tRN\t4\n", asm_out_file);
13109 fputs ("__v2\tRN\t5\n", asm_out_file);
13110 fputs ("__v3\tRN\t6\n", asm_out_file);
13111 fputs ("__v4\tRN\t7\n", asm_out_file);
13112 fputs ("__v5\tRN\t8\n", asm_out_file);
13113 fputs ("__v6\tRN\t9\n", asm_out_file);
13114 fputs ("__sl\tRN\t10\n", asm_out_file);
13115 fputs ("__fp\tRN\t11\n", asm_out_file);
13116 fputs ("__ip\tRN\t12\n", asm_out_file);
13117 fputs ("__sp\tRN\t13\n", asm_out_file);
13118 fputs ("__lr\tRN\t14\n", asm_out_file);
13119 fputs ("__pc\tRN\t15\n", asm_out_file);
13120 fputs ("__f0\tFN\t0\n", asm_out_file);
13121 fputs ("__f1\tFN\t1\n", asm_out_file);
13122 fputs ("__f2\tFN\t2\n", asm_out_file);
13123 fputs ("__f3\tFN\t3\n", asm_out_file);
13124 fputs ("__f4\tFN\t4\n", asm_out_file);
13125 fputs ("__f5\tFN\t5\n", asm_out_file);
13126 fputs ("__f6\tFN\t6\n", asm_out_file);
13127 fputs ("__f7\tFN\t7\n", asm_out_file);
13132 aof_file_end (void)
13135 aof_dump_pic_table (asm_out_file);
13136 aof_dump_imports (asm_out_file);
13137 fputs ("\tEND\n", asm_out_file);
13139 #endif /* AOF_ASSEMBLER */
13141 #ifdef OBJECT_FORMAT_ELF
13142 /* Switch to an arbitrary section NAME with attributes as specified
13143 by FLAGS. ALIGN specifies any known alignment requirements for
13144 the section; 0 if the default should be used.
13146 Differs from the default elf version only in the prefix character
13147 used before the section type. */
13150 arm_elf_asm_named_section (const char *name, unsigned int flags)
13152 char flagchars[10], *f = flagchars;
13154 if (! named_section_first_declaration (name))
13156 fprintf (asm_out_file, "\t.section\t%s\n", name);
13160 if (!(flags & SECTION_DEBUG))
13162 if (flags & SECTION_WRITE)
13164 if (flags & SECTION_CODE)
13166 if (flags & SECTION_SMALL)
13168 if (flags & SECTION_MERGE)
13170 if (flags & SECTION_STRINGS)
13172 if (flags & SECTION_TLS)
13176 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
13178 if (!(flags & SECTION_NOTYPE))
13182 if (flags & SECTION_BSS)
13187 fprintf (asm_out_file, ",%%%s", type);
13189 if (flags & SECTION_ENTSIZE)
13190 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
13193 putc ('\n', asm_out_file);
13198 /* Symbols in the text segment can be accessed without indirecting via the
13199 constant pool; it may take an extra binary operation, but this is still
13200 faster than indirecting via memory. Don't do this when not optimizing,
13201 since we won't be calculating al of the offsets necessary to do this
13205 arm_encode_section_info (tree decl, rtx rtl, int first)
13207 /* This doesn't work with AOF syntax, since the string table may be in
13208 a different AREA. */
13209 #ifndef AOF_ASSEMBLER
13210 if (optimize > 0 && TREE_CONSTANT (decl)
13211 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST))
13212 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
13215 /* If we are referencing a function that is weak then encode a long call
13216 flag in the function name, otherwise if the function is static or
13217 or known to be defined in this file then encode a short call flag. */
13218 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
13220 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
13221 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
13222 else if (! TREE_PUBLIC (decl))
13223 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
13226 #endif /* !ARM_PE */
13229 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
13231 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
13232 && !strcmp (prefix, "L"))
13234 arm_ccfsm_state = 0;
13235 arm_target_insn = NULL;
13237 default_internal_label (stream, prefix, labelno);
13240 /* Output code to add DELTA to the first argument, and then jump
13241 to FUNCTION. Used for C++ multiple inheritance. */
13243 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
13244 HOST_WIDE_INT delta,
13245 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
13248 static int thunk_label = 0;
13250 int mi_delta = delta;
13251 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
13253 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
13256 mi_delta = - mi_delta;
13259 int labelno = thunk_label++;
13260 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
13261 fputs ("\tldr\tr12, ", file);
13262 assemble_name (file, label);
13263 fputc ('\n', file);
13265 while (mi_delta != 0)
13267 if ((mi_delta & (3 << shift)) == 0)
13271 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
13272 mi_op, this_regno, this_regno,
13273 mi_delta & (0xff << shift));
13274 mi_delta &= ~(0xff << shift);
13280 fprintf (file, "\tbx\tr12\n");
13281 ASM_OUTPUT_ALIGN (file, 2);
13282 assemble_name (file, label);
13283 fputs (":\n", file);
13284 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
13288 fputs ("\tb\t", file);
13289 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
13290 if (NEED_PLT_RELOC)
13291 fputs ("(PLT)", file);
13292 fputc ('\n', file);
13297 arm_emit_vector_const (FILE *file, rtx x)
13300 const char * pattern;
13302 if (GET_CODE (x) != CONST_VECTOR)
13305 switch (GET_MODE (x))
13307 case V2SImode: pattern = "%08x"; break;
13308 case V4HImode: pattern = "%04x"; break;
13309 case V8QImode: pattern = "%02x"; break;
13313 fprintf (file, "0x");
13314 for (i = CONST_VECTOR_NUNITS (x); i--;)
13318 element = CONST_VECTOR_ELT (x, i);
13319 fprintf (file, pattern, INTVAL (element));
13326 arm_output_load_gr (rtx *operands)
13333 if (GET_CODE (operands [1]) != MEM
13334 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
13335 || GET_CODE (reg = XEXP (sum, 0)) != REG
13336 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
13337 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
13338 return "wldrw%?\t%0, %1";
13340 /* Fix up an out-of-range load of a GR register. */
13341 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
13342 wcgr = operands[0];
13344 output_asm_insn ("ldr%?\t%0, %1", operands);
13346 operands[0] = wcgr;
13348 output_asm_insn ("tmcr%?\t%0, %1", operands);
13349 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);