1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static void arm_add_gc_roots (void);
63 static int arm_gen_constant (enum rtx_code, enum machine_mode, HOST_WIDE_INT,
65 static unsigned bit_count (unsigned long);
66 static int arm_address_register_rtx_p (rtx, int);
67 static int arm_legitimate_index_p (enum machine_mode, rtx, int);
68 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
69 inline static int thumb_index_register_rtx_p (rtx, int);
70 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
71 static rtx emit_multi_reg_push (int);
72 static rtx emit_sfm (int, int);
74 static bool arm_assemble_integer (rtx, unsigned int, int);
76 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
77 static arm_cc get_arm_condition_code (rtx);
78 static void init_fpa_table (void);
79 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
80 static rtx is_jump_table (rtx);
81 static const char *output_multi_immediate (rtx *, const char *, const char *,
83 static void print_multi_reg (FILE *, const char *, int, int);
84 static const char *shift_op (rtx, HOST_WIDE_INT *);
85 static struct machine_function *arm_init_machine_status (void);
86 static int number_of_first_bit_set (int);
87 static void replace_symbols_in_block (tree, rtx, rtx);
88 static void thumb_exit (FILE *, int, rtx);
89 static void thumb_pushpop (FILE *, int, int, int *, int);
90 static rtx is_jump_table (rtx);
91 static HOST_WIDE_INT get_jump_table_size (rtx);
92 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
93 static Mnode *add_minipool_forward_ref (Mfix *);
94 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
95 static Mnode *add_minipool_backward_ref (Mfix *);
96 static void assign_minipool_offsets (Mfix *);
97 static void arm_print_value (FILE *, rtx);
98 static void dump_minipool (rtx);
99 static int arm_barrier_cost (rtx);
100 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
101 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
102 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
104 static void arm_reorg (void);
105 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
106 static int current_file_function_operand (rtx);
107 static unsigned long arm_compute_save_reg0_reg12_mask (void);
108 static unsigned long arm_compute_save_reg_mask (void);
109 static unsigned long arm_isr_value (tree);
110 static unsigned long arm_compute_func_type (void);
111 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
112 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
113 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
114 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
116 static int arm_comp_type_attributes (tree, tree);
117 static void arm_set_default_type_attributes (tree);
118 static int arm_adjust_cost (rtx, rtx, rtx, int);
119 static int arm_use_dfa_pipeline_interface (void);
120 static int count_insns_for_constant (HOST_WIDE_INT, int);
121 static int arm_get_strip_length (int);
122 static bool arm_function_ok_for_sibcall (tree, tree);
123 static void arm_internal_label (FILE *, const char *, unsigned long);
124 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
126 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
127 static bool arm_rtx_costs (rtx, int, int, int *);
128 static int arm_address_cost (rtx);
129 static bool arm_memory_load_p (rtx);
130 static bool arm_cirrus_insn_p (rtx);
131 static void cirrus_reorg (rtx);
132 static void arm_init_builtins (void);
133 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
134 static void arm_init_iwmmxt_builtins (void);
135 static rtx safe_vector_operand (rtx, enum machine_mode);
136 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
137 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
138 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
140 #ifdef OBJECT_FORMAT_ELF
141 static void arm_elf_asm_named_section (const char *, unsigned int);
144 static void arm_encode_section_info (tree, rtx, int);
147 static void aof_globalize_label (FILE *, const char *);
148 static void aof_dump_imports (FILE *);
149 static void aof_dump_pic_table (FILE *);
150 static void aof_file_start (void);
151 static void aof_file_end (void);
155 /* Initialize the GCC target structure. */
156 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
157 #undef TARGET_MERGE_DECL_ATTRIBUTES
158 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
161 #undef TARGET_ATTRIBUTE_TABLE
162 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
165 #undef TARGET_ASM_BYTE_OP
166 #define TARGET_ASM_BYTE_OP "\tDCB\t"
167 #undef TARGET_ASM_ALIGNED_HI_OP
168 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
169 #undef TARGET_ASM_ALIGNED_SI_OP
170 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
171 #undef TARGET_ASM_GLOBALIZE_LABEL
172 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
173 #undef TARGET_ASM_FILE_START
174 #define TARGET_ASM_FILE_START aof_file_start
175 #undef TARGET_ASM_FILE_END
176 #define TARGET_ASM_FILE_END aof_file_end
178 #undef TARGET_ASM_ALIGNED_SI_OP
179 #define TARGET_ASM_ALIGNED_SI_OP NULL
180 #undef TARGET_ASM_INTEGER
181 #define TARGET_ASM_INTEGER arm_assemble_integer
184 #undef TARGET_ASM_FUNCTION_PROLOGUE
185 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
187 #undef TARGET_ASM_FUNCTION_EPILOGUE
188 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
190 #undef TARGET_COMP_TYPE_ATTRIBUTES
191 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
193 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
194 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
196 #undef TARGET_SCHED_ADJUST_COST
197 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
199 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
200 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
202 #undef TARGET_ENCODE_SECTION_INFO
204 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
206 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
209 #undef TARGET_STRIP_NAME_ENCODING
210 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
212 #undef TARGET_ASM_INTERNAL_LABEL
213 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
215 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
216 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
218 #undef TARGET_ASM_OUTPUT_MI_THUNK
219 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
220 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
221 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
223 #undef TARGET_RTX_COSTS
224 #define TARGET_RTX_COSTS arm_rtx_costs
225 #undef TARGET_ADDRESS_COST
226 #define TARGET_ADDRESS_COST arm_address_cost
228 #undef TARGET_MACHINE_DEPENDENT_REORG
229 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
231 #undef TARGET_INIT_BUILTINS
232 #define TARGET_INIT_BUILTINS arm_init_builtins
233 #undef TARGET_EXPAND_BUILTIN
234 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
236 struct gcc_target targetm = TARGET_INITIALIZER;
238 /* Obstack for minipool constant handling. */
239 static struct obstack minipool_obstack;
240 static char * minipool_startobj;
242 /* The maximum number of insns skipped which
243 will be conditionalised if possible. */
244 static int max_insns_skipped = 5;
246 extern FILE * asm_out_file;
248 /* True if we are currently building a constant table. */
249 int making_const_table;
251 /* Define the information needed to generate branch insns. This is
252 stored from the compare operation. */
253 rtx arm_compare_op0, arm_compare_op1;
255 /* What type of floating point are we tuning for? */
256 enum fputype arm_fpu_tune;
258 /* What type of floating point instructions are available? */
259 enum fputype arm_fpu_arch;
261 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
262 enum prog_mode_type arm_prgmode;
264 /* Set by the -mfp=... option. */
265 const char * target_fp_name = NULL;
267 /* Used to parse -mstructure_size_boundary command line option. */
268 const char * structure_size_string = NULL;
269 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
271 /* Bit values used to identify processor capabilities. */
272 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
273 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
274 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
275 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
276 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
277 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
278 #define FL_THUMB (1 << 6) /* Thumb aware */
279 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
280 #define FL_STRONG (1 << 8) /* StrongARM */
281 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
282 #define FL_XSCALE (1 << 10) /* XScale */
283 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
284 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
285 #define FL_ARCH6J (1 << 12) /* Architecture rel 6. Adds
286 media instructions. */
287 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
289 /* The bits in this mask specify which
290 instructions we are allowed to generate. */
291 static unsigned long insn_flags = 0;
293 /* The bits in this mask specify which instruction scheduling options should
294 be used. Note - there is an overlap with the FL_FAST_MULT. For some
295 hardware we want to be able to generate the multiply instructions, but to
296 tune as if they were not present in the architecture. */
297 static unsigned long tune_flags = 0;
299 /* The following are used in the arm.md file as equivalents to bits
300 in the above two flag variables. */
302 /* Nonzero if this is an "M" variant of the processor. */
303 int arm_fast_multiply = 0;
305 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
308 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
311 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
314 /* Nonzero if this chip can benefit from load scheduling. */
315 int arm_ld_sched = 0;
317 /* Nonzero if this chip is a StrongARM. */
318 int arm_is_strong = 0;
320 /* Nonzero if this chip supports Intel Wireless MMX technology. */
321 int arm_arch_iwmmxt = 0;
323 /* Nonzero if this chip is an XScale. */
324 int arm_arch_xscale = 0;
326 /* Nonzero if tuning for XScale */
327 int arm_tune_xscale = 0;
329 /* Nonzero if this chip is an ARM6 or an ARM7. */
330 int arm_is_6_or_7 = 0;
332 /* Nonzero if this chip is a Cirrus/DSP. */
333 int arm_is_cirrus = 0;
335 /* Nonzero if generating Thumb instructions. */
338 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
339 must report the mode of the memory reference from PRINT_OPERAND to
340 PRINT_OPERAND_ADDRESS. */
341 enum machine_mode output_memory_reference_mode;
343 /* The register number to be used for the PIC offset register. */
344 const char * arm_pic_register_string = NULL;
345 int arm_pic_register = INVALID_REGNUM;
347 /* Set to 1 when a return insn is output, this means that the epilogue
349 int return_used_this_function;
351 /* Set to 1 after arm_reorg has started. Reset to start at the start of
352 the next function. */
353 static int after_arm_reorg = 0;
355 /* The maximum number of insns to be used when loading a constant. */
356 static int arm_constant_limit = 3;
358 /* For an explanation of these variables, see final_prescan_insn below. */
360 enum arm_cond_code arm_current_cc;
362 int arm_target_label;
364 /* The condition codes of the ARM, and the inverse function. */
365 static const char * const arm_condition_codes[] =
367 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
368 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
371 #define streq(string1, string2) (strcmp (string1, string2) == 0)
373 /* Initialization code. */
377 const char *const name;
378 const unsigned long flags;
381 /* Not all of these give usefully different compilation alternatives,
382 but there is no simple way of generalizing them. */
383 static const struct processors all_cores[] =
387 {"arm2", FL_CO_PROC | FL_MODE26 },
388 {"arm250", FL_CO_PROC | FL_MODE26 },
389 {"arm3", FL_CO_PROC | FL_MODE26 },
390 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
391 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
392 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
393 {"arm610", FL_MODE26 | FL_MODE32 },
394 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
395 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
396 /* arm7m doesn't exist on its own, but only with D, (and I), but
397 those don't alter the code, so arm7m is sometimes used. */
398 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
399 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
400 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
401 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
402 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
403 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
404 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
405 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
406 {"arm710", FL_MODE26 | FL_MODE32 },
407 {"arm720", FL_MODE26 | FL_MODE32 },
408 {"arm710c", FL_MODE26 | FL_MODE32 },
409 {"arm7100", FL_MODE26 | FL_MODE32 },
410 {"arm7500", FL_MODE26 | FL_MODE32 },
411 /* Doesn't have an external co-proc, but does have embedded fpa. */
412 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
413 /* V4 Architecture Processors */
414 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
415 {"arm710t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
416 {"arm720t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
417 {"arm740t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
418 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
419 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
420 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
421 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
422 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
423 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
424 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
425 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
426 {"ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
427 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
428 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
429 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
430 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
431 /* V5 Architecture Processors */
432 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
433 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
434 {"arm926ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
435 {"arm1026ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
436 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
437 {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
438 /* V6 Architecture Processors */
439 {"arm1136js", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J },
440 {"arm1136jfs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J | FL_VFPV2 },
444 static const struct processors all_architectures[] =
446 /* ARM Architectures */
448 { "armv2", FL_CO_PROC | FL_MODE26 },
449 { "armv2a", FL_CO_PROC | FL_MODE26 },
450 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
451 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
452 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
453 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
454 implementations that support it, so we will leave it out for now. */
455 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
456 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
457 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
458 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
459 { "armv6j", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J },
460 { "ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
461 {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
465 /* This is a magic structure. The 'string' field is magically filled in
466 with a pointer to the value specified by the user on the command line
467 assuming that the user has specified such a value. */
469 struct arm_cpu_select arm_select[] =
471 /* string name processors */
472 { NULL, "-mcpu=", all_cores },
473 { NULL, "-march=", all_architectures },
474 { NULL, "-mtune=", all_cores }
477 /* Return the number of bits set in VALUE. */
479 bit_count (unsigned long value)
481 unsigned long count = 0;
486 value &= value - 1; /* Clear the least-significant set bit. */
492 /* Fix up any incompatible options that the user has specified.
493 This has now turned into a maze. */
495 arm_override_options (void)
499 /* Set up the flags based on the cpu/architecture selected by the user. */
500 for (i = ARRAY_SIZE (arm_select); i--;)
502 struct arm_cpu_select * ptr = arm_select + i;
504 if (ptr->string != NULL && ptr->string[0] != '\0')
506 const struct processors * sel;
508 for (sel = ptr->processors; sel->name != NULL; sel++)
509 if (streq (ptr->string, sel->name))
512 tune_flags = sel->flags;
515 /* If we have been given an architecture and a processor
516 make sure that they are compatible. We only generate
517 a warning though, and we prefer the CPU over the
519 if (insn_flags != 0 && (insn_flags ^ sel->flags))
520 warning ("switch -mcpu=%s conflicts with -march= switch",
523 insn_flags = sel->flags;
529 if (sel->name == NULL)
530 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
534 /* If the user did not specify a processor, choose one for them. */
537 const struct processors * sel;
539 static const struct cpu_default
542 const char *const name;
546 { TARGET_CPU_arm2, "arm2" },
547 { TARGET_CPU_arm6, "arm6" },
548 { TARGET_CPU_arm610, "arm610" },
549 { TARGET_CPU_arm710, "arm710" },
550 { TARGET_CPU_arm7m, "arm7m" },
551 { TARGET_CPU_arm7500fe, "arm7500fe" },
552 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
553 { TARGET_CPU_arm8, "arm8" },
554 { TARGET_CPU_arm810, "arm810" },
555 { TARGET_CPU_arm9, "arm9" },
556 { TARGET_CPU_strongarm, "strongarm" },
557 { TARGET_CPU_xscale, "xscale" },
558 { TARGET_CPU_ep9312, "ep9312" },
559 { TARGET_CPU_iwmmxt, "iwmmxt" },
560 { TARGET_CPU_arm926ej_s, "arm926ej-s" },
561 { TARGET_CPU_arm1026ej_s, "arm1026ej-s" },
562 { TARGET_CPU_arm1136j_s, "arm1136j_s" },
563 { TARGET_CPU_arm1136jf_s, "arm1136jf_s" },
564 { TARGET_CPU_generic, "arm" },
567 const struct cpu_default * def;
569 /* Find the default. */
570 for (def = cpu_defaults; def->name; def++)
571 if (def->cpu == TARGET_CPU_DEFAULT)
574 /* Make sure we found the default CPU. */
575 if (def->name == NULL)
578 /* Find the default CPU's flags. */
579 for (sel = all_cores; sel->name != NULL; sel++)
580 if (streq (def->name, sel->name))
583 if (sel->name == NULL)
586 insn_flags = sel->flags;
588 /* Now check to see if the user has specified some command line
589 switch that require certain abilities from the cpu. */
592 if (TARGET_INTERWORK || TARGET_THUMB)
594 sought |= (FL_THUMB | FL_MODE32);
596 /* Force apcs-32 to be used for interworking. */
597 target_flags |= ARM_FLAG_APCS_32;
599 /* There are no ARM processors that support both APCS-26 and
600 interworking. Therefore we force FL_MODE26 to be removed
601 from insn_flags here (if it was set), so that the search
602 below will always be able to find a compatible processor. */
603 insn_flags &= ~FL_MODE26;
605 else if (!TARGET_APCS_32)
608 if (sought != 0 && ((sought & insn_flags) != sought))
610 /* Try to locate a CPU type that supports all of the abilities
611 of the default CPU, plus the extra abilities requested by
613 for (sel = all_cores; sel->name != NULL; sel++)
614 if ((sel->flags & sought) == (sought | insn_flags))
617 if (sel->name == NULL)
619 unsigned current_bit_count = 0;
620 const struct processors * best_fit = NULL;
622 /* Ideally we would like to issue an error message here
623 saying that it was not possible to find a CPU compatible
624 with the default CPU, but which also supports the command
625 line options specified by the programmer, and so they
626 ought to use the -mcpu=<name> command line option to
627 override the default CPU type.
629 Unfortunately this does not work with multilibing. We
630 need to be able to support multilibs for -mapcs-26 and for
631 -mthumb-interwork and there is no CPU that can support both
632 options. Instead if we cannot find a cpu that has both the
633 characteristics of the default cpu and the given command line
634 options we scan the array again looking for a best match. */
635 for (sel = all_cores; sel->name != NULL; sel++)
636 if ((sel->flags & sought) == sought)
640 count = bit_count (sel->flags & insn_flags);
642 if (count >= current_bit_count)
645 current_bit_count = count;
649 if (best_fit == NULL)
655 insn_flags = sel->flags;
659 /* If tuning has not been specified, tune for whichever processor or
660 architecture has been selected. */
662 tune_flags = insn_flags;
664 /* Make sure that the processor choice does not conflict with any of the
665 other command line choices. */
666 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
668 /* If APCS-32 was not the default then it must have been set by the
669 user, so issue a warning message. If the user has specified
670 "-mapcs-32 -mcpu=arm2" then we loose here. */
671 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
672 warning ("target CPU does not support APCS-32" );
673 target_flags &= ~ARM_FLAG_APCS_32;
675 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
677 warning ("target CPU does not support APCS-26" );
678 target_flags |= ARM_FLAG_APCS_32;
681 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
683 warning ("target CPU does not support interworking" );
684 target_flags &= ~ARM_FLAG_INTERWORK;
687 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
689 warning ("target CPU does not support THUMB instructions");
690 target_flags &= ~ARM_FLAG_THUMB;
694 inform ("future releases of GCC will not support -mapcs-26");
696 if (TARGET_APCS_FRAME && TARGET_THUMB)
698 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
699 target_flags &= ~ARM_FLAG_APCS_FRAME;
702 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
703 from here where no function is being compiled currently. */
704 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
706 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
708 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
709 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
711 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
712 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
714 /* If interworking is enabled then APCS-32 must be selected as well. */
715 if (TARGET_INTERWORK)
718 warning ("interworking forces APCS-32 to be used" );
719 target_flags |= ARM_FLAG_APCS_32;
722 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
724 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
725 target_flags |= ARM_FLAG_APCS_FRAME;
728 if (TARGET_POKE_FUNCTION_NAME)
729 target_flags |= ARM_FLAG_APCS_FRAME;
731 if (TARGET_APCS_REENT && flag_pic)
732 error ("-fpic and -mapcs-reent are incompatible");
734 if (TARGET_APCS_REENT)
735 warning ("APCS reentrant code not supported. Ignored");
737 /* If this target is normally configured to use APCS frames, warn if they
738 are turned off and debugging is turned on. */
740 && write_symbols != NO_DEBUG
741 && !TARGET_APCS_FRAME
742 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
743 warning ("-g with -mno-apcs-frame may not give sensible debugging");
745 /* If stack checking is disabled, we can use r10 as the PIC register,
746 which keeps r9 available. */
748 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
750 if (TARGET_APCS_FLOAT)
751 warning ("passing floating point arguments in fp regs not yet supported");
753 /* Initialize boolean versions of the flags, for use in the arm.md file. */
754 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
755 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
756 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
757 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
758 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
760 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
761 arm_is_strong = (tune_flags & FL_STRONG) != 0;
762 thumb_code = (TARGET_ARM == 0);
763 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
764 && !(tune_flags & FL_ARCH4))) != 0;
765 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
766 arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0;
767 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
769 if (TARGET_IWMMXT && (! TARGET_ATPCS))
770 target_flags |= ARM_FLAG_ATPCS;
774 arm_fpu_tune = FPUTYPE_MAVERICK;
776 /* Ignore -mhard-float if -mcpu=ep9312. */
777 if (TARGET_HARD_FLOAT)
778 target_flags ^= ARM_FLAG_SOFT_FLOAT;
781 /* Default value for floating point code... if no co-processor
782 bus, then schedule for emulated floating point. Otherwise,
783 assume the user has an FPA.
784 Note: this does not prevent use of floating point instructions,
785 -msoft-float does that. */
786 arm_fpu_tune = (tune_flags & FL_CO_PROC) ? FPUTYPE_FPA : FPUTYPE_FPA_EMU3;
790 if (streq (target_fp_name, "2"))
791 arm_fpu_arch = FPUTYPE_FPA_EMU2;
792 else if (streq (target_fp_name, "3"))
793 arm_fpu_arch = FPUTYPE_FPA_EMU3;
795 error ("invalid floating point emulation option: -mfpe-%s",
799 arm_fpu_arch = FPUTYPE_DEFAULT;
803 if (arm_fpu_tune == FPUTYPE_FPA_EMU3)
804 arm_fpu_tune = FPUTYPE_FPA_EMU2;
805 else if (arm_fpu_tune == FPUTYPE_MAVERICK)
806 warning ("-mfpe switch not supported by ep9312 target cpu - ignored.");
807 else if (arm_fpu_tune != FPUTYPE_FPA)
808 arm_fpu_tune = FPUTYPE_FPA_EMU2;
811 /* For arm2/3 there is no need to do any scheduling if there is only
812 a floating point emulator, or we are doing software floating-point. */
813 if ((TARGET_SOFT_FLOAT || arm_fpu_tune != FPUTYPE_FPA)
814 && (tune_flags & FL_MODE32) == 0)
815 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
817 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
819 if (structure_size_string != NULL)
821 int size = strtol (structure_size_string, NULL, 0);
823 if (size == 8 || size == 32)
824 arm_structure_size_boundary = size;
826 warning ("structure size boundary can only be set to 8 or 32");
829 if (arm_pic_register_string != NULL)
831 int pic_register = decode_reg_name (arm_pic_register_string);
834 warning ("-mpic-register= is useless without -fpic");
836 /* Prevent the user from choosing an obviously stupid PIC register. */
837 else if (pic_register < 0 || call_used_regs[pic_register]
838 || pic_register == HARD_FRAME_POINTER_REGNUM
839 || pic_register == STACK_POINTER_REGNUM
840 || pic_register >= PC_REGNUM)
841 error ("unable to use '%s' for PIC register", arm_pic_register_string);
843 arm_pic_register = pic_register;
846 if (TARGET_THUMB && flag_schedule_insns)
848 /* Don't warn since it's on by default in -O2. */
849 flag_schedule_insns = 0;
854 /* There's some dispute as to whether this should be 1 or 2. However,
855 experiments seem to show that in pathological cases a setting of
856 1 degrades less severely than a setting of 2. This could change if
857 other parts of the compiler change their behavior. */
858 arm_constant_limit = 1;
860 /* If optimizing for size, bump the number of instructions that we
861 are prepared to conditionally execute (even on a StrongARM). */
862 max_insns_skipped = 6;
866 /* For processors with load scheduling, it never costs more than
867 2 cycles to load a constant, and the load scheduler may well
869 if (tune_flags & FL_LDSCHED)
870 arm_constant_limit = 1;
872 /* On XScale the longer latency of a load makes it more difficult
873 to achieve a good schedule, so it's faster to synthesize
874 constants that can be done in two insns. */
876 arm_constant_limit = 2;
878 /* StrongARM has early execution of branches, so a sequence
879 that is worth skipping is shorter. */
881 max_insns_skipped = 3;
884 /* Register global variables with the garbage collector. */
889 arm_add_gc_roots (void)
891 gcc_obstack_init(&minipool_obstack);
892 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
895 /* A table of known ARM exception types.
896 For use with the interrupt function attribute. */
900 const char *const arg;
901 const unsigned long return_value;
905 static const isr_attribute_arg isr_attribute_args [] =
907 { "IRQ", ARM_FT_ISR },
908 { "irq", ARM_FT_ISR },
909 { "FIQ", ARM_FT_FIQ },
910 { "fiq", ARM_FT_FIQ },
911 { "ABORT", ARM_FT_ISR },
912 { "abort", ARM_FT_ISR },
913 { "ABORT", ARM_FT_ISR },
914 { "abort", ARM_FT_ISR },
915 { "UNDEF", ARM_FT_EXCEPTION },
916 { "undef", ARM_FT_EXCEPTION },
917 { "SWI", ARM_FT_EXCEPTION },
918 { "swi", ARM_FT_EXCEPTION },
919 { NULL, ARM_FT_NORMAL }
922 /* Returns the (interrupt) function type of the current
923 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
926 arm_isr_value (tree argument)
928 const isr_attribute_arg * ptr;
931 /* No argument - default to IRQ. */
932 if (argument == NULL_TREE)
935 /* Get the value of the argument. */
936 if (TREE_VALUE (argument) == NULL_TREE
937 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
938 return ARM_FT_UNKNOWN;
940 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
942 /* Check it against the list of known arguments. */
943 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
944 if (streq (arg, ptr->arg))
945 return ptr->return_value;
947 /* An unrecognized interrupt type. */
948 return ARM_FT_UNKNOWN;
951 /* Computes the type of the current function. */
954 arm_compute_func_type (void)
956 unsigned long type = ARM_FT_UNKNOWN;
960 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
963 /* Decide if the current function is volatile. Such functions
964 never return, and many memory cycles can be saved by not storing
965 register values that will never be needed again. This optimization
966 was added to speed up context switching in a kernel application. */
968 && current_function_nothrow
969 && TREE_THIS_VOLATILE (current_function_decl))
970 type |= ARM_FT_VOLATILE;
972 if (current_function_needs_context)
973 type |= ARM_FT_NESTED;
975 attr = DECL_ATTRIBUTES (current_function_decl);
977 a = lookup_attribute ("naked", attr);
979 type |= ARM_FT_NAKED;
981 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
982 type |= ARM_FT_EXCEPTION_HANDLER;
985 a = lookup_attribute ("isr", attr);
987 a = lookup_attribute ("interrupt", attr);
990 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
992 type |= arm_isr_value (TREE_VALUE (a));
998 /* Returns the type of the current function. */
1001 arm_current_func_type (void)
1003 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1004 cfun->machine->func_type = arm_compute_func_type ();
1006 return cfun->machine->func_type;
1009 /* Return 1 if it is possible to return using a single instruction.
1010 If SIBLING is non-null, this is a test for a return before a sibling
1011 call. SIBLING is the call insn, so we can examine its register usage. */
1014 use_return_insn (int iscond, rtx sibling)
1017 unsigned int func_type;
1018 unsigned long saved_int_regs;
1019 unsigned HOST_WIDE_INT stack_adjust;
1021 /* Never use a return instruction before reload has run. */
1022 if (!reload_completed)
1025 func_type = arm_current_func_type ();
1027 /* Naked functions and volatile functions need special
1029 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1032 /* So do interrupt functions that use the frame pointer. */
1033 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1036 stack_adjust = arm_get_frame_size () + current_function_outgoing_args_size;
1038 /* As do variadic functions. */
1039 if (current_function_pretend_args_size
1040 || cfun->machine->uses_anonymous_args
1041 /* Or if the function calls __builtin_eh_return () */
1042 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1043 /* Or if the function calls alloca */
1044 || current_function_calls_alloca
1045 /* Or if there is a stack adjustment. However, if the stack pointer
1046 is saved on the stack, we can use a pre-incrementing stack load. */
1047 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1050 saved_int_regs = arm_compute_save_reg_mask ();
1052 /* Unfortunately, the insn
1054 ldmib sp, {..., sp, ...}
1056 triggers a bug on most SA-110 based devices, such that the stack
1057 pointer won't be correctly restored if the instruction takes a
1058 page fault. We work around this problem by popping r3 along with
1059 the other registers, since that is never slower than executing
1060 another instruction.
1062 We test for !arm_arch5 here, because code for any architecture
1063 less than this could potentially be run on one of the buggy
1065 if (stack_adjust == 4 && !arm_arch5)
1067 /* Validate that r3 is a call-clobbered register (always true in
1068 the default abi) ... */
1069 if (!call_used_regs[3])
1072 /* ... that it isn't being used for a return value (always true
1073 until we implement return-in-regs), or for a tail-call
1077 if (GET_CODE (sibling) != CALL_INSN)
1080 if (find_regno_fusage (sibling, USE, 3))
1084 /* ... and that there are no call-saved registers in r0-r2
1085 (always true in the default ABI). */
1086 if (saved_int_regs & 0x7)
1090 /* Can't be done if interworking with Thumb, and any registers have been
1092 if (TARGET_INTERWORK && saved_int_regs != 0)
1095 /* On StrongARM, conditional returns are expensive if they aren't
1096 taken and multiple registers have been stacked. */
1097 if (iscond && arm_is_strong)
1099 /* Conditional return when just the LR is stored is a simple
1100 conditional-load instruction, that's not expensive. */
1101 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1104 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1108 /* If there are saved registers but the LR isn't saved, then we need
1109 two instructions for the return. */
1110 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1113 /* Can't be done if any of the FPA regs are pushed,
1114 since this also requires an insn. */
1115 if (TARGET_HARD_FLOAT)
1116 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
1117 if (regs_ever_live[regno] && !call_used_regs[regno])
1120 if (TARGET_REALLY_IWMMXT)
1121 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1122 if (regs_ever_live[regno] && ! call_used_regs [regno])
1128 /* Return TRUE if int I is a valid immediate ARM constant. */
1131 const_ok_for_arm (HOST_WIDE_INT i)
1133 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1135 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1136 be all zero, or all one. */
1137 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1138 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1139 != ((~(unsigned HOST_WIDE_INT) 0)
1140 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1143 /* Fast return for 0 and powers of 2 */
1144 if ((i & (i - 1)) == 0)
1149 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1152 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1153 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1155 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1160 /* Return true if I is a valid constant for the operation CODE. */
1162 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1164 if (const_ok_for_arm (i))
1170 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1172 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1178 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1185 /* Emit a sequence of insns to handle a large constant.
1186 CODE is the code of the operation required, it can be any of SET, PLUS,
1187 IOR, AND, XOR, MINUS;
1188 MODE is the mode in which the operation is being performed;
1189 VAL is the integer to operate on;
1190 SOURCE is the other operand (a register, or a null-pointer for SET);
1191 SUBTARGETS means it is safe to create scratch registers if that will
1192 either produce a simpler sequence, or we will want to cse the values.
1193 Return value is the number of insns emitted. */
1196 arm_split_constant (enum rtx_code code, enum machine_mode mode,
1197 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1199 if (subtargets || code == SET
1200 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1201 && REGNO (target) != REGNO (source)))
1203 /* After arm_reorg has been called, we can't fix up expensive
1204 constants by pushing them into memory so we must synthesize
1205 them in-line, regardless of the cost. This is only likely to
1206 be more costly on chips that have load delay slots and we are
1207 compiling without running the scheduler (so no splitting
1208 occurred before the final instruction emission).
1210 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1212 if (!after_arm_reorg
1213 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1214 > arm_constant_limit + (code != SET)))
1218 /* Currently SET is the only monadic value for CODE, all
1219 the rest are diadic. */
1220 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1225 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1227 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1228 /* For MINUS, the value is subtracted from, since we never
1229 have subtraction of a constant. */
1231 emit_insn (gen_rtx_SET (VOIDmode, target,
1232 gen_rtx_MINUS (mode, temp, source)));
1234 emit_insn (gen_rtx_SET (VOIDmode, target,
1235 gen_rtx (code, mode, source, temp)));
1241 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1245 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1247 HOST_WIDE_INT temp1;
1255 if (remainder & (3 << (i - 2)))
1260 temp1 = remainder & ((0x0ff << end)
1261 | ((i < end) ? (0xff >> (32 - end)) : 0));
1262 remainder &= ~temp1;
1267 } while (remainder);
1271 /* As above, but extra parameter GENERATE which, if clear, suppresses
1275 arm_gen_constant (enum rtx_code code, enum machine_mode mode,
1276 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1281 int can_negate_initial = 0;
1284 int num_bits_set = 0;
1285 int set_sign_bit_copies = 0;
1286 int clear_sign_bit_copies = 0;
1287 int clear_zero_bit_copies = 0;
1288 int set_zero_bit_copies = 0;
1290 unsigned HOST_WIDE_INT temp1, temp2;
1291 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1293 /* Find out which operations are safe for a given CODE. Also do a quick
1294 check for degenerate cases; these can occur when DImode operations
1306 can_negate_initial = 1;
1310 if (remainder == 0xffffffff)
1313 emit_insn (gen_rtx_SET (VOIDmode, target,
1314 GEN_INT (ARM_SIGN_EXTEND (val))));
1319 if (reload_completed && rtx_equal_p (target, source))
1322 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1331 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1334 if (remainder == 0xffffffff)
1336 if (reload_completed && rtx_equal_p (target, source))
1339 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1348 if (reload_completed && rtx_equal_p (target, source))
1351 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1354 if (remainder == 0xffffffff)
1357 emit_insn (gen_rtx_SET (VOIDmode, target,
1358 gen_rtx_NOT (mode, source)));
1362 /* We don't know how to handle this yet below. */
1366 /* We treat MINUS as (val - source), since (source - val) is always
1367 passed as (source + (-val)). */
1371 emit_insn (gen_rtx_SET (VOIDmode, target,
1372 gen_rtx_NEG (mode, source)));
1375 if (const_ok_for_arm (val))
1378 emit_insn (gen_rtx_SET (VOIDmode, target,
1379 gen_rtx_MINUS (mode, GEN_INT (val),
1391 /* If we can do it in one insn get out quickly. */
1392 if (const_ok_for_arm (val)
1393 || (can_negate_initial && const_ok_for_arm (-val))
1394 || (can_invert && const_ok_for_arm (~val)))
1397 emit_insn (gen_rtx_SET (VOIDmode, target,
1398 (source ? gen_rtx (code, mode, source,
1404 /* Calculate a few attributes that may be useful for specific
1406 for (i = 31; i >= 0; i--)
1408 if ((remainder & (1 << i)) == 0)
1409 clear_sign_bit_copies++;
1414 for (i = 31; i >= 0; i--)
1416 if ((remainder & (1 << i)) != 0)
1417 set_sign_bit_copies++;
1422 for (i = 0; i <= 31; i++)
1424 if ((remainder & (1 << i)) == 0)
1425 clear_zero_bit_copies++;
1430 for (i = 0; i <= 31; i++)
1432 if ((remainder & (1 << i)) != 0)
1433 set_zero_bit_copies++;
1441 /* See if we can do this by sign_extending a constant that is known
1442 to be negative. This is a good, way of doing it, since the shift
1443 may well merge into a subsequent insn. */
1444 if (set_sign_bit_copies > 1)
1446 if (const_ok_for_arm
1447 (temp1 = ARM_SIGN_EXTEND (remainder
1448 << (set_sign_bit_copies - 1))))
1452 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1453 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1455 emit_insn (gen_ashrsi3 (target, new_src,
1456 GEN_INT (set_sign_bit_copies - 1)));
1460 /* For an inverted constant, we will need to set the low bits,
1461 these will be shifted out of harm's way. */
1462 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1463 if (const_ok_for_arm (~temp1))
1467 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1468 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1470 emit_insn (gen_ashrsi3 (target, new_src,
1471 GEN_INT (set_sign_bit_copies - 1)));
1477 /* See if we can generate this by setting the bottom (or the top)
1478 16 bits, and then shifting these into the other half of the
1479 word. We only look for the simplest cases, to do more would cost
1480 too much. Be careful, however, not to generate this when the
1481 alternative would take fewer insns. */
1482 if (val & 0xffff0000)
1484 temp1 = remainder & 0xffff0000;
1485 temp2 = remainder & 0x0000ffff;
1487 /* Overlaps outside this range are best done using other methods. */
1488 for (i = 9; i < 24; i++)
1490 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1491 && !const_ok_for_arm (temp2))
1493 rtx new_src = (subtargets
1494 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1496 insns = arm_gen_constant (code, mode, temp2, new_src,
1497 source, subtargets, generate);
1500 emit_insn (gen_rtx_SET
1503 gen_rtx_ASHIFT (mode, source,
1510 /* Don't duplicate cases already considered. */
1511 for (i = 17; i < 24; i++)
1513 if (((temp1 | (temp1 >> i)) == remainder)
1514 && !const_ok_for_arm (temp1))
1516 rtx new_src = (subtargets
1517 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1519 insns = arm_gen_constant (code, mode, temp1, new_src,
1520 source, subtargets, generate);
1524 (gen_rtx_SET (VOIDmode, target,
1527 gen_rtx_LSHIFTRT (mode, source,
1538 /* If we have IOR or XOR, and the constant can be loaded in a
1539 single instruction, and we can find a temporary to put it in,
1540 then this can be done in two instructions instead of 3-4. */
1542 /* TARGET can't be NULL if SUBTARGETS is 0 */
1543 || (reload_completed && !reg_mentioned_p (target, source)))
1545 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1549 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1551 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1552 emit_insn (gen_rtx_SET (VOIDmode, target,
1553 gen_rtx (code, mode, source, sub)));
1562 if (set_sign_bit_copies > 8
1563 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1567 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1568 rtx shift = GEN_INT (set_sign_bit_copies);
1570 emit_insn (gen_rtx_SET (VOIDmode, sub,
1572 gen_rtx_ASHIFT (mode,
1575 emit_insn (gen_rtx_SET (VOIDmode, target,
1577 gen_rtx_LSHIFTRT (mode, sub,
1583 if (set_zero_bit_copies > 8
1584 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1588 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1589 rtx shift = GEN_INT (set_zero_bit_copies);
1591 emit_insn (gen_rtx_SET (VOIDmode, sub,
1593 gen_rtx_LSHIFTRT (mode,
1596 emit_insn (gen_rtx_SET (VOIDmode, target,
1598 gen_rtx_ASHIFT (mode, sub,
1604 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1608 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1609 emit_insn (gen_rtx_SET (VOIDmode, sub,
1610 gen_rtx_NOT (mode, source)));
1613 sub = gen_reg_rtx (mode);
1614 emit_insn (gen_rtx_SET (VOIDmode, sub,
1615 gen_rtx_AND (mode, source,
1617 emit_insn (gen_rtx_SET (VOIDmode, target,
1618 gen_rtx_NOT (mode, sub)));
1625 /* See if two shifts will do 2 or more insn's worth of work. */
1626 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1628 HOST_WIDE_INT shift_mask = ((0xffffffff
1629 << (32 - clear_sign_bit_copies))
1632 if ((remainder | shift_mask) != 0xffffffff)
1636 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1637 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1638 new_src, source, subtargets, 1);
1643 rtx targ = subtargets ? NULL_RTX : target;
1644 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1645 targ, source, subtargets, 0);
1651 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1652 rtx shift = GEN_INT (clear_sign_bit_copies);
1654 emit_insn (gen_ashlsi3 (new_src, source, shift));
1655 emit_insn (gen_lshrsi3 (target, new_src, shift));
1661 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1663 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1665 if ((remainder | shift_mask) != 0xffffffff)
1669 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1671 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1672 new_src, source, subtargets, 1);
1677 rtx targ = subtargets ? NULL_RTX : target;
1679 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1680 targ, source, subtargets, 0);
1686 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1687 rtx shift = GEN_INT (clear_zero_bit_copies);
1689 emit_insn (gen_lshrsi3 (new_src, source, shift));
1690 emit_insn (gen_ashlsi3 (target, new_src, shift));
1702 for (i = 0; i < 32; i++)
1703 if (remainder & (1 << i))
1706 if (code == AND || (can_invert && num_bits_set > 16))
1707 remainder = (~remainder) & 0xffffffff;
1708 else if (code == PLUS && num_bits_set > 16)
1709 remainder = (-remainder) & 0xffffffff;
1716 /* Now try and find a way of doing the job in either two or three
1718 We start by looking for the largest block of zeros that are aligned on
1719 a 2-bit boundary, we then fill up the temps, wrapping around to the
1720 top of the word when we drop off the bottom.
1721 In the worst case this code should produce no more than four insns. */
1724 int best_consecutive_zeros = 0;
1726 for (i = 0; i < 32; i += 2)
1728 int consecutive_zeros = 0;
1730 if (!(remainder & (3 << i)))
1732 while ((i < 32) && !(remainder & (3 << i)))
1734 consecutive_zeros += 2;
1737 if (consecutive_zeros > best_consecutive_zeros)
1739 best_consecutive_zeros = consecutive_zeros;
1740 best_start = i - consecutive_zeros;
1746 /* So long as it won't require any more insns to do so, it's
1747 desirable to emit a small constant (in bits 0...9) in the last
1748 insn. This way there is more chance that it can be combined with
1749 a later addressing insn to form a pre-indexed load or store
1750 operation. Consider:
1752 *((volatile int *)0xe0000100) = 1;
1753 *((volatile int *)0xe0000110) = 2;
1755 We want this to wind up as:
1759 str rB, [rA, #0x100]
1761 str rB, [rA, #0x110]
1763 rather than having to synthesize both large constants from scratch.
1765 Therefore, we calculate how many insns would be required to emit
1766 the constant starting from `best_start', and also starting from
1767 zero (ie with bit 31 first to be output). If `best_start' doesn't
1768 yield a shorter sequence, we may as well use zero. */
1770 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1771 && (count_insns_for_constant (remainder, 0) <=
1772 count_insns_for_constant (remainder, best_start)))
1775 /* Now start emitting the insns. */
1783 if (remainder & (3 << (i - 2)))
1788 temp1 = remainder & ((0x0ff << end)
1789 | ((i < end) ? (0xff >> (32 - end)) : 0));
1790 remainder &= ~temp1;
1794 rtx new_src, temp1_rtx;
1796 if (code == SET || code == MINUS)
1798 new_src = (subtargets ? gen_reg_rtx (mode) : target);
1799 if (can_invert && code != MINUS)
1804 if (remainder && subtargets)
1805 new_src = gen_reg_rtx (mode);
1810 else if (can_negate)
1814 temp1 = trunc_int_for_mode (temp1, mode);
1815 temp1_rtx = GEN_INT (temp1);
1819 else if (code == MINUS)
1820 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
1822 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
1824 emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx));
1833 else if (code == MINUS)
1847 /* Canonicalize a comparison so that we are more likely to recognize it.
1848 This can be done for a few constant compares, where we can make the
1849 immediate value easier to load. */
1852 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
1854 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1864 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1865 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1867 *op1 = GEN_INT (i + 1);
1868 return code == GT ? GE : LT;
1874 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1875 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1877 *op1 = GEN_INT (i - 1);
1878 return code == GE ? GT : LE;
1884 if (i != ~((unsigned HOST_WIDE_INT) 0)
1885 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1887 *op1 = GEN_INT (i + 1);
1888 return code == GTU ? GEU : LTU;
1895 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1897 *op1 = GEN_INT (i - 1);
1898 return code == GEU ? GTU : LEU;
1909 /* Decide whether a type should be returned in memory (true)
1910 or in a register (false). This is called by the macro
1911 RETURN_IN_MEMORY. */
1913 arm_return_in_memory (tree type)
1917 if (!AGGREGATE_TYPE_P (type))
1918 /* All simple types are returned in registers. */
1921 size = int_size_in_bytes (type);
1925 /* ATPCS returns aggregate types in memory only if they are
1926 larger than a word (or are variable size). */
1927 return (size < 0 || size > UNITS_PER_WORD);
1930 /* For the arm-wince targets we choose to be compatible with Microsoft's
1931 ARM and Thumb compilers, which always return aggregates in memory. */
1933 /* All structures/unions bigger than one word are returned in memory.
1934 Also catch the case where int_size_in_bytes returns -1. In this case
1935 the aggregate is either huge or of variable size, and in either case
1936 we will want to return it via memory and not in a register. */
1937 if (size < 0 || size > UNITS_PER_WORD)
1940 if (TREE_CODE (type) == RECORD_TYPE)
1944 /* For a struct the APCS says that we only return in a register
1945 if the type is 'integer like' and every addressable element
1946 has an offset of zero. For practical purposes this means
1947 that the structure can have at most one non bit-field element
1948 and that this element must be the first one in the structure. */
1950 /* Find the first field, ignoring non FIELD_DECL things which will
1951 have been created by C++. */
1952 for (field = TYPE_FIELDS (type);
1953 field && TREE_CODE (field) != FIELD_DECL;
1954 field = TREE_CHAIN (field))
1958 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1960 /* Check that the first field is valid for returning in a register. */
1962 /* ... Floats are not allowed */
1963 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1966 /* ... Aggregates that are not themselves valid for returning in
1967 a register are not allowed. */
1968 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1971 /* Now check the remaining fields, if any. Only bitfields are allowed,
1972 since they are not addressable. */
1973 for (field = TREE_CHAIN (field);
1975 field = TREE_CHAIN (field))
1977 if (TREE_CODE (field) != FIELD_DECL)
1980 if (!DECL_BIT_FIELD_TYPE (field))
1987 if (TREE_CODE (type) == UNION_TYPE)
1991 /* Unions can be returned in registers if every element is
1992 integral, or can be returned in an integer register. */
1993 for (field = TYPE_FIELDS (type);
1995 field = TREE_CHAIN (field))
1997 if (TREE_CODE (field) != FIELD_DECL)
2000 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2003 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2009 #endif /* not ARM_WINCE */
2011 /* Return all other types in memory. */
2015 /* Indicate whether or not words of a double are in big-endian order. */
2018 arm_float_words_big_endian (void)
2023 /* For FPA, float words are always big-endian. For VFP, floats words
2024 follow the memory system mode. */
2026 if (TARGET_HARD_FLOAT)
2028 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
2033 return (TARGET_BIG_END ? 1 : 0);
2038 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2039 for a call to a function whose data type is FNTYPE.
2040 For a library call, FNTYPE is NULL. */
2042 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2043 rtx libname ATTRIBUTE_UNUSED,
2044 tree fndecl ATTRIBUTE_UNUSED)
2046 /* On the ARM, the offset starts at 0. */
2047 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2048 pcum->iwmmxt_nregs = 0;
2050 pcum->call_cookie = CALL_NORMAL;
2052 if (TARGET_LONG_CALLS)
2053 pcum->call_cookie = CALL_LONG;
2055 /* Check for long call/short call attributes. The attributes
2056 override any command line option. */
2059 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2060 pcum->call_cookie = CALL_SHORT;
2061 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2062 pcum->call_cookie = CALL_LONG;
2065 /* Varargs vectors are treated the same as long long.
2066 named_count avoids having to change the way arm handles 'named' */
2067 pcum->named_count = 0;
2070 if (TARGET_REALLY_IWMMXT && fntype)
2074 for (fn_arg = TYPE_ARG_TYPES (fntype);
2076 fn_arg = TREE_CHAIN (fn_arg))
2077 pcum->named_count += 1;
2079 if (! pcum->named_count)
2080 pcum->named_count = INT_MAX;
2084 /* Determine where to put an argument to a function.
2085 Value is zero to push the argument on the stack,
2086 or a hard register in which to store the argument.
2088 MODE is the argument's machine mode.
2089 TYPE is the data type of the argument (as a tree).
2090 This is null for libcalls where that information may
2092 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2093 the preceding args and about the function being called.
2094 NAMED is nonzero if this argument is a named parameter
2095 (otherwise it is an extra parameter matching an ellipsis). */
2098 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2099 tree type ATTRIBUTE_UNUSED, int named)
2101 if (TARGET_REALLY_IWMMXT)
2103 if (VECTOR_MODE_SUPPORTED_P (mode))
2105 /* varargs vectors are treated the same as long long.
2106 named_count avoids having to change the way arm handles 'named' */
2107 if (pcum->named_count <= pcum->nargs + 1)
2109 if (pcum->nregs == 1)
2111 if (pcum->nregs <= 2)
2112 return gen_rtx_REG (mode, pcum->nregs);
2116 else if (pcum->iwmmxt_nregs <= 9)
2117 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2121 else if ((mode == DImode || mode == DFmode) && pcum->nregs & 1)
2125 if (mode == VOIDmode)
2126 /* Compute operand 2 of the call insn. */
2127 return GEN_INT (pcum->call_cookie);
2129 if (!named || pcum->nregs >= NUM_ARG_REGS)
2132 return gen_rtx_REG (mode, pcum->nregs);
2135 /* Variable sized types are passed by reference. This is a GCC
2136 extension to the ARM ABI. */
2139 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2140 enum machine_mode mode ATTRIBUTE_UNUSED,
2141 tree type, int named ATTRIBUTE_UNUSED)
2143 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2146 /* Implement va_arg. */
2149 arm_va_arg (tree valist, tree type)
2151 /* Variable sized types are passed by reference. */
2152 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2154 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2155 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2158 if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), NULL) == IWMMXT_ALIGNMENT)
2163 /* Maintain 64-bit alignment of the valist pointer by
2164 constructing: valist = ((valist + (8 - 1)) & -8). */
2165 minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1);
2166 t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0);
2167 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2168 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, minus_eight);
2169 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2170 TREE_SIDE_EFFECTS (t) = 1;
2171 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2173 /* This is to stop the combine pass optimizing
2174 away the alignment adjustment. */
2175 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2178 return std_expand_builtin_va_arg (valist, type);
2181 /* Encode the current state of the #pragma [no_]long_calls. */
2184 OFF, /* No #pramgma [no_]long_calls is in effect. */
2185 LONG, /* #pragma long_calls is in effect. */
2186 SHORT /* #pragma no_long_calls is in effect. */
2189 static arm_pragma_enum arm_pragma_long_calls = OFF;
2192 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2194 arm_pragma_long_calls = LONG;
2198 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2200 arm_pragma_long_calls = SHORT;
2204 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2206 arm_pragma_long_calls = OFF;
2209 /* Table of machine attributes. */
2210 const struct attribute_spec arm_attribute_table[] =
2212 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2213 /* Function calls made to this symbol must be done indirectly, because
2214 it may lie outside of the 26 bit addressing range of a normal function
2216 { "long_call", 0, 0, false, true, true, NULL },
2217 /* Whereas these functions are always known to reside within the 26 bit
2218 addressing range. */
2219 { "short_call", 0, 0, false, true, true, NULL },
2220 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2221 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2222 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2223 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2225 /* ARM/PE has three new attributes:
2227 dllexport - for exporting a function/variable that will live in a dll
2228 dllimport - for importing a function/variable from a dll
2230 Microsoft allows multiple declspecs in one __declspec, separating
2231 them with spaces. We do NOT support this. Instead, use __declspec
2234 { "dllimport", 0, 0, true, false, false, NULL },
2235 { "dllexport", 0, 0, true, false, false, NULL },
2236 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2238 { NULL, 0, 0, false, false, false, NULL }
2241 /* Handle an attribute requiring a FUNCTION_DECL;
2242 arguments as in struct attribute_spec.handler. */
2244 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2245 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2247 if (TREE_CODE (*node) != FUNCTION_DECL)
2249 warning ("`%s' attribute only applies to functions",
2250 IDENTIFIER_POINTER (name));
2251 *no_add_attrs = true;
2257 /* Handle an "interrupt" or "isr" attribute;
2258 arguments as in struct attribute_spec.handler. */
2260 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2265 if (TREE_CODE (*node) != FUNCTION_DECL)
2267 warning ("`%s' attribute only applies to functions",
2268 IDENTIFIER_POINTER (name));
2269 *no_add_attrs = true;
2271 /* FIXME: the argument if any is checked for type attributes;
2272 should it be checked for decl ones? */
2276 if (TREE_CODE (*node) == FUNCTION_TYPE
2277 || TREE_CODE (*node) == METHOD_TYPE)
2279 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2281 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2282 *no_add_attrs = true;
2285 else if (TREE_CODE (*node) == POINTER_TYPE
2286 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2287 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2288 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2290 *node = build_type_copy (*node);
2291 TREE_TYPE (*node) = build_type_attribute_variant
2293 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2294 *no_add_attrs = true;
2298 /* Possibly pass this attribute on from the type to a decl. */
2299 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2300 | (int) ATTR_FLAG_FUNCTION_NEXT
2301 | (int) ATTR_FLAG_ARRAY_NEXT))
2303 *no_add_attrs = true;
2304 return tree_cons (name, args, NULL_TREE);
2308 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2316 /* Return 0 if the attributes for two types are incompatible, 1 if they
2317 are compatible, and 2 if they are nearly compatible (which causes a
2318 warning to be generated). */
2320 arm_comp_type_attributes (tree type1, tree type2)
2324 /* Check for mismatch of non-default calling convention. */
2325 if (TREE_CODE (type1) != FUNCTION_TYPE)
2328 /* Check for mismatched call attributes. */
2329 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2330 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2331 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2332 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2334 /* Only bother to check if an attribute is defined. */
2335 if (l1 | l2 | s1 | s2)
2337 /* If one type has an attribute, the other must have the same attribute. */
2338 if ((l1 != l2) || (s1 != s2))
2341 /* Disallow mixed attributes. */
2342 if ((l1 & s2) || (l2 & s1))
2346 /* Check for mismatched ISR attribute. */
2347 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2349 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2350 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2352 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2359 /* Encode long_call or short_call attribute by prefixing
2360 symbol name in DECL with a special character FLAG. */
2362 arm_encode_call_attribute (tree decl, int flag)
2364 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2365 int len = strlen (str);
2368 /* Do not allow weak functions to be treated as short call. */
2369 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2372 newstr = alloca (len + 2);
2374 strcpy (newstr + 1, str);
2376 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2377 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2380 /* Assigns default attributes to newly defined type. This is used to
2381 set short_call/long_call attributes for function types of
2382 functions defined inside corresponding #pragma scopes. */
2384 arm_set_default_type_attributes (tree type)
2386 /* Add __attribute__ ((long_call)) to all functions, when
2387 inside #pragma long_calls or __attribute__ ((short_call)),
2388 when inside #pragma no_long_calls. */
2389 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2391 tree type_attr_list, attr_name;
2392 type_attr_list = TYPE_ATTRIBUTES (type);
2394 if (arm_pragma_long_calls == LONG)
2395 attr_name = get_identifier ("long_call");
2396 else if (arm_pragma_long_calls == SHORT)
2397 attr_name = get_identifier ("short_call");
2401 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2402 TYPE_ATTRIBUTES (type) = type_attr_list;
2406 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2407 defined within the current compilation unit. If this cannot be
2408 determined, then 0 is returned. */
2410 current_file_function_operand (rtx sym_ref)
2412 /* This is a bit of a fib. A function will have a short call flag
2413 applied to its name if it has the short call attribute, or it has
2414 already been defined within the current compilation unit. */
2415 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2418 /* The current function is always defined within the current compilation
2419 unit. if it s a weak definition however, then this may not be the real
2420 definition of the function, and so we have to say no. */
2421 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2422 && !DECL_WEAK (current_function_decl))
2425 /* We cannot make the determination - default to returning 0. */
2429 /* Return nonzero if a 32 bit "long_call" should be generated for
2430 this call. We generate a long_call if the function:
2432 a. has an __attribute__((long call))
2433 or b. is within the scope of a #pragma long_calls
2434 or c. the -mlong-calls command line switch has been specified
2436 However we do not generate a long call if the function:
2438 d. has an __attribute__ ((short_call))
2439 or e. is inside the scope of a #pragma no_long_calls
2440 or f. has an __attribute__ ((section))
2441 or g. is defined within the current compilation unit.
2443 This function will be called by C fragments contained in the machine
2444 description file. CALL_REF and CALL_COOKIE correspond to the matched
2445 rtl operands. CALL_SYMBOL is used to distinguish between
2446 two different callers of the function. It is set to 1 in the
2447 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2448 and "call_value" patterns. This is because of the difference in the
2449 SYM_REFs passed by these patterns. */
2451 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2455 if (GET_CODE (sym_ref) != MEM)
2458 sym_ref = XEXP (sym_ref, 0);
2461 if (GET_CODE (sym_ref) != SYMBOL_REF)
2464 if (call_cookie & CALL_SHORT)
2467 if (TARGET_LONG_CALLS && flag_function_sections)
2470 if (current_file_function_operand (sym_ref))
2473 return (call_cookie & CALL_LONG)
2474 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2475 || TARGET_LONG_CALLS;
2478 /* Return nonzero if it is ok to make a tail-call to DECL. */
2480 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2482 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2484 if (cfun->machine->sibcall_blocked)
2487 /* Never tailcall something for which we have no decl, or if we
2488 are in Thumb mode. */
2489 if (decl == NULL || TARGET_THUMB)
2492 /* Get the calling method. */
2493 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2494 call_type = CALL_SHORT;
2495 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2496 call_type = CALL_LONG;
2498 /* Cannot tail-call to long calls, since these are out of range of
2499 a branch instruction. However, if not compiling PIC, we know
2500 we can reach the symbol if it is in this compilation unit. */
2501 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2504 /* If we are interworking and the function is not declared static
2505 then we can't tail-call it unless we know that it exists in this
2506 compilation unit (since it might be a Thumb routine). */
2507 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2510 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2511 if (IS_INTERRUPT (arm_current_func_type ()))
2514 /* Everything else is ok. */
2519 /* Addressing mode support functions. */
2521 /* Return nonzero if X is a legitimate immediate operand when compiling
2524 legitimate_pic_operand_p (rtx x)
2528 && (GET_CODE (x) == SYMBOL_REF
2529 || (GET_CODE (x) == CONST
2530 && GET_CODE (XEXP (x, 0)) == PLUS
2531 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2538 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2540 if (GET_CODE (orig) == SYMBOL_REF
2541 || GET_CODE (orig) == LABEL_REF)
2543 #ifndef AOF_ASSEMBLER
2544 rtx pic_ref, address;
2554 reg = gen_reg_rtx (Pmode);
2559 #ifdef AOF_ASSEMBLER
2560 /* The AOF assembler can generate relocations for these directly, and
2561 understands that the PIC register has to be added into the offset. */
2562 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2565 address = gen_reg_rtx (Pmode);
2570 emit_insn (gen_pic_load_addr_arm (address, orig));
2572 emit_insn (gen_pic_load_addr_thumb (address, orig));
2574 if ((GET_CODE (orig) == LABEL_REF
2575 || (GET_CODE (orig) == SYMBOL_REF &&
2576 SYMBOL_REF_LOCAL_P (orig)))
2578 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2581 pic_ref = gen_rtx_MEM (Pmode,
2582 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2584 RTX_UNCHANGING_P (pic_ref) = 1;
2587 insn = emit_move_insn (reg, pic_ref);
2589 current_function_uses_pic_offset_table = 1;
2590 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2592 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2596 else if (GET_CODE (orig) == CONST)
2600 if (GET_CODE (XEXP (orig, 0)) == PLUS
2601 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2609 reg = gen_reg_rtx (Pmode);
2612 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2614 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2615 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2616 base == reg ? 0 : reg);
2621 if (GET_CODE (offset) == CONST_INT)
2623 /* The base register doesn't really matter, we only want to
2624 test the index for the appropriate mode. */
2625 if (!arm_legitimate_index_p (mode, offset, 0))
2627 if (!no_new_pseudos)
2628 offset = force_reg (Pmode, offset);
2633 if (GET_CODE (offset) == CONST_INT)
2634 return plus_constant (base, INTVAL (offset));
2637 if (GET_MODE_SIZE (mode) > 4
2638 && (GET_MODE_CLASS (mode) == MODE_INT
2639 || TARGET_SOFT_FLOAT))
2641 emit_insn (gen_addsi3 (reg, base, offset));
2645 return gen_rtx_PLUS (Pmode, base, offset);
2651 /* Generate code to load the PIC register. PROLOGUE is true if
2652 called from arm_expand_prologue (in which case we want the
2653 generated insns at the start of the function); false if called
2654 by an exception receiver that needs the PIC register reloaded
2655 (in which case the insns are just dumped at the current location). */
2657 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2659 #ifndef AOF_ASSEMBLER
2660 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2661 rtx global_offset_table;
2663 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2670 l1 = gen_label_rtx ();
2672 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2673 /* On the ARM the PC register contains 'dot + 8' at the time of the
2674 addition, on the Thumb it is 'dot + 4'. */
2675 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2677 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2678 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2680 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2682 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2686 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2687 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2691 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2692 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2698 emit_insn_after (seq, get_insns ());
2702 /* Need to emit this whether or not we obey regdecls,
2703 since setjmp/longjmp can cause life info to screw up. */
2704 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2705 #endif /* AOF_ASSEMBLER */
2708 /* Return nonzero if X is valid as an ARM state addressing register. */
2710 arm_address_register_rtx_p (rtx x, int strict_p)
2714 if (GET_CODE (x) != REG)
2720 return ARM_REGNO_OK_FOR_BASE_P (regno);
2722 return (regno <= LAST_ARM_REGNUM
2723 || regno >= FIRST_PSEUDO_REGISTER
2724 || regno == FRAME_POINTER_REGNUM
2725 || regno == ARG_POINTER_REGNUM);
2728 /* Return nonzero if X is a valid ARM state address operand. */
2730 arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
2732 if (arm_address_register_rtx_p (x, strict_p))
2735 else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
2736 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2738 else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY)
2739 && GET_MODE_SIZE (mode) <= 4
2740 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2741 && GET_CODE (XEXP (x, 1)) == PLUS
2742 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2743 return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p);
2745 /* After reload constants split into minipools will have addresses
2746 from a LABEL_REF. */
2747 else if (reload_completed
2748 && (GET_CODE (x) == LABEL_REF
2749 || (GET_CODE (x) == CONST
2750 && GET_CODE (XEXP (x, 0)) == PLUS
2751 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2752 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2755 else if (mode == TImode)
2758 else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
2760 if (GET_CODE (x) == PLUS
2761 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2762 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2764 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2766 if (val == 4 || val == -4 || val == -8)
2771 else if (GET_CODE (x) == PLUS)
2773 rtx xop0 = XEXP (x, 0);
2774 rtx xop1 = XEXP (x, 1);
2776 return ((arm_address_register_rtx_p (xop0, strict_p)
2777 && arm_legitimate_index_p (mode, xop1, strict_p))
2778 || (arm_address_register_rtx_p (xop1, strict_p)
2779 && arm_legitimate_index_p (mode, xop0, strict_p)));
2783 /* Reload currently can't handle MINUS, so disable this for now */
2784 else if (GET_CODE (x) == MINUS)
2786 rtx xop0 = XEXP (x, 0);
2787 rtx xop1 = XEXP (x, 1);
2789 return (arm_address_register_rtx_p (xop0, strict_p)
2790 && arm_legitimate_index_p (mode, xop1, strict_p));
2794 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2795 && GET_CODE (x) == SYMBOL_REF
2796 && CONSTANT_POOL_ADDRESS_P (x)
2798 && symbol_mentioned_p (get_pool_constant (x))))
2801 else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC)
2802 && (GET_MODE_SIZE (mode) <= 4)
2803 && arm_address_register_rtx_p (XEXP (x, 0), strict_p))
2809 /* Return nonzero if INDEX is valid for an address index operand in
2812 arm_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
2814 HOST_WIDE_INT range;
2815 enum rtx_code code = GET_CODE (index);
2817 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
2818 return (code == CONST_INT && INTVAL (index) < 1024
2819 && INTVAL (index) > -1024
2820 && (INTVAL (index) & 3) == 0);
2823 && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode))
2824 return (code == CONST_INT
2825 && INTVAL (index) < 255
2826 && INTVAL (index) > -255);
2828 if (arm_address_register_rtx_p (index, strict_p)
2829 && GET_MODE_SIZE (mode) <= 4)
2832 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
2833 return (code == CONST_INT
2834 && INTVAL (index) < 256
2835 && INTVAL (index) > -256);
2837 /* XXX What about ldrsb? */
2838 if (GET_MODE_SIZE (mode) <= 4 && code == MULT
2839 && (!arm_arch4 || (mode) != HImode))
2841 rtx xiop0 = XEXP (index, 0);
2842 rtx xiop1 = XEXP (index, 1);
2844 return ((arm_address_register_rtx_p (xiop0, strict_p)
2845 && power_of_two_operand (xiop1, SImode))
2846 || (arm_address_register_rtx_p (xiop1, strict_p)
2847 && power_of_two_operand (xiop0, SImode)));
2850 if (GET_MODE_SIZE (mode) <= 4
2851 && (code == LSHIFTRT || code == ASHIFTRT
2852 || code == ASHIFT || code == ROTATERT)
2853 && (!arm_arch4 || (mode) != HImode))
2855 rtx op = XEXP (index, 1);
2857 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
2858 && GET_CODE (op) == CONST_INT
2860 && INTVAL (op) <= 31);
2863 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2864 load, but that has a restricted addressing range and we are unable
2865 to tell here whether that is the case. To be safe we restrict all
2866 loads to that range. */
2868 range = (mode == HImode || mode == QImode) ? 256 : 4096;
2870 range = (mode == HImode) ? 4095 : 4096;
2872 return (code == CONST_INT
2873 && INTVAL (index) < range
2874 && INTVAL (index) > -range);
2877 /* Return nonzero if X is valid as a Thumb state base register. */
2879 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
2883 if (GET_CODE (x) != REG)
2889 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
2891 return (regno <= LAST_LO_REGNUM
2892 || regno > LAST_VIRTUAL_REGISTER
2893 || regno == FRAME_POINTER_REGNUM
2894 || (GET_MODE_SIZE (mode) >= 4
2895 && (regno == STACK_POINTER_REGNUM
2896 || regno >= FIRST_PSEUDO_REGISTER
2897 || x == hard_frame_pointer_rtx
2898 || x == arg_pointer_rtx)));
2901 /* Return nonzero if x is a legitimate index register. This is the case
2902 for any base register that can access a QImode object. */
2904 thumb_index_register_rtx_p (rtx x, int strict_p)
2906 return thumb_base_register_rtx_p (x, QImode, strict_p);
2909 /* Return nonzero if x is a legitimate Thumb-state address.
2911 The AP may be eliminated to either the SP or the FP, so we use the
2912 least common denominator, e.g. SImode, and offsets from 0 to 64.
2914 ??? Verify whether the above is the right approach.
2916 ??? Also, the FP may be eliminated to the SP, so perhaps that
2917 needs special handling also.
2919 ??? Look at how the mips16 port solves this problem. It probably uses
2920 better ways to solve some of these problems.
2922 Although it is not incorrect, we don't accept QImode and HImode
2923 addresses based on the frame pointer or arg pointer until the
2924 reload pass starts. This is so that eliminating such addresses
2925 into stack based ones won't produce impossible code. */
2927 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
2929 /* ??? Not clear if this is right. Experiment. */
2930 if (GET_MODE_SIZE (mode) < 4
2931 && !(reload_in_progress || reload_completed)
2932 && (reg_mentioned_p (frame_pointer_rtx, x)
2933 || reg_mentioned_p (arg_pointer_rtx, x)
2934 || reg_mentioned_p (virtual_incoming_args_rtx, x)
2935 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
2936 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
2937 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
2940 /* Accept any base register. SP only in SImode or larger. */
2941 else if (thumb_base_register_rtx_p (x, mode, strict_p))
2944 /* This is PC relative data before arm_reorg runs. */
2945 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
2946 && GET_CODE (x) == SYMBOL_REF
2947 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
2950 /* This is PC relative data after arm_reorg runs. */
2951 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
2952 && (GET_CODE (x) == LABEL_REF
2953 || (GET_CODE (x) == CONST
2954 && GET_CODE (XEXP (x, 0)) == PLUS
2955 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2956 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2959 /* Post-inc indexing only supported for SImode and larger. */
2960 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
2961 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
2964 else if (GET_CODE (x) == PLUS)
2966 /* REG+REG address can be any two index registers. */
2967 /* We disallow FRAME+REG addressing since we know that FRAME
2968 will be replaced with STACK, and SP relative addressing only
2969 permits SP+OFFSET. */
2970 if (GET_MODE_SIZE (mode) <= 4
2971 && XEXP (x, 0) != frame_pointer_rtx
2972 && XEXP (x, 1) != frame_pointer_rtx
2973 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2974 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
2977 /* REG+const has 5-7 bit offset for non-SP registers. */
2978 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2979 || XEXP (x, 0) == arg_pointer_rtx)
2980 && GET_CODE (XEXP (x, 1)) == CONST_INT
2981 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
2984 /* REG+const has 10 bit offset for SP, but only SImode and
2985 larger is supported. */
2986 /* ??? Should probably check for DI/DFmode overflow here
2987 just like GO_IF_LEGITIMATE_OFFSET does. */
2988 else if (GET_CODE (XEXP (x, 0)) == REG
2989 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
2990 && GET_MODE_SIZE (mode) >= 4
2991 && GET_CODE (XEXP (x, 1)) == CONST_INT
2992 && INTVAL (XEXP (x, 1)) >= 0
2993 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
2994 && (INTVAL (XEXP (x, 1)) & 3) == 0)
2997 else if (GET_CODE (XEXP (x, 0)) == REG
2998 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
2999 && GET_MODE_SIZE (mode) >= 4
3000 && GET_CODE (XEXP (x, 1)) == CONST_INT
3001 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3005 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3006 && GET_MODE_SIZE (mode) == 4
3007 && GET_CODE (x) == SYMBOL_REF
3008 && CONSTANT_POOL_ADDRESS_P (x)
3010 && symbol_mentioned_p (get_pool_constant (x))))
3016 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3017 instruction of mode MODE. */
3019 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3021 switch (GET_MODE_SIZE (mode))
3024 return val >= 0 && val < 32;
3027 return val >= 0 && val < 64 && (val & 1) == 0;
3031 && (val + GET_MODE_SIZE (mode)) <= 128
3036 /* Try machine-dependent ways of modifying an illegitimate address
3037 to be legitimate. If we find one, return the new, valid address. */
3039 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3041 if (GET_CODE (x) == PLUS)
3043 rtx xop0 = XEXP (x, 0);
3044 rtx xop1 = XEXP (x, 1);
3046 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3047 xop0 = force_reg (SImode, xop0);
3049 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3050 xop1 = force_reg (SImode, xop1);
3052 if (ARM_BASE_REGISTER_RTX_P (xop0)
3053 && GET_CODE (xop1) == CONST_INT)
3055 HOST_WIDE_INT n, low_n;
3059 if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
3071 low_n = ((mode) == TImode ? 0
3072 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3076 base_reg = gen_reg_rtx (SImode);
3077 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3078 GEN_INT (n)), NULL_RTX);
3079 emit_move_insn (base_reg, val);
3080 x = (low_n == 0 ? base_reg
3081 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3083 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3084 x = gen_rtx_PLUS (SImode, xop0, xop1);
3087 /* XXX We don't allow MINUS any more -- see comment in
3088 arm_legitimate_address_p (). */
3089 else if (GET_CODE (x) == MINUS)
3091 rtx xop0 = XEXP (x, 0);
3092 rtx xop1 = XEXP (x, 1);
3094 if (CONSTANT_P (xop0))
3095 xop0 = force_reg (SImode, xop0);
3097 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3098 xop1 = force_reg (SImode, xop1);
3100 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3101 x = gen_rtx_MINUS (SImode, xop0, xop1);
3106 /* We need to find and carefully transform any SYMBOL and LABEL
3107 references; so go back to the original address expression. */
3108 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3110 if (new_x != orig_x)
3119 #define REG_OR_SUBREG_REG(X) \
3120 (GET_CODE (X) == REG \
3121 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3123 #define REG_OR_SUBREG_RTX(X) \
3124 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3126 #ifndef COSTS_N_INSNS
3127 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3129 /* Worker routine for arm_rtx_costs. */
3131 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3133 enum machine_mode mode = GET_MODE (x);
3134 enum rtx_code subcode;
3150 return COSTS_N_INSNS (1);
3153 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3156 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3163 return COSTS_N_INSNS (2) + cycles;
3165 return COSTS_N_INSNS (1) + 16;
3168 return (COSTS_N_INSNS (1)
3169 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3170 + GET_CODE (SET_DEST (x)) == MEM));
3175 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3177 if (thumb_shiftable_const (INTVAL (x)))
3178 return COSTS_N_INSNS (2);
3179 return COSTS_N_INSNS (3);
3181 else if ((outer == PLUS || outer == COMPARE)
3182 && INTVAL (x) < 256 && INTVAL (x) > -256)
3184 else if (outer == AND
3185 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3186 return COSTS_N_INSNS (1);
3187 else if (outer == ASHIFT || outer == ASHIFTRT
3188 || outer == LSHIFTRT)
3190 return COSTS_N_INSNS (2);
3196 return COSTS_N_INSNS (3);
3215 /* XXX another guess. */
3216 /* Memory costs quite a lot for the first word, but subsequent words
3217 load at the equivalent of a single insn each. */
3218 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3219 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3224 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3229 /* XXX still guessing. */
3230 switch (GET_MODE (XEXP (x, 0)))
3233 return (1 + (mode == DImode ? 4 : 0)
3234 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3237 return (4 + (mode == DImode ? 4 : 0)
3238 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3241 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3255 /* Memory costs quite a lot for the first word, but subsequent words
3256 load at the equivalent of a single insn each. */
3257 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3258 + (GET_CODE (x) == SYMBOL_REF
3259 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3265 return optimize_size ? COSTS_N_INSNS (2) : 100;
3268 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3275 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3277 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3278 + ((GET_CODE (XEXP (x, 0)) == REG
3279 || (GET_CODE (XEXP (x, 0)) == SUBREG
3280 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3282 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3283 || (GET_CODE (XEXP (x, 0)) == SUBREG
3284 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3286 + ((GET_CODE (XEXP (x, 1)) == REG
3287 || (GET_CODE (XEXP (x, 1)) == SUBREG
3288 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3289 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3294 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3295 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3296 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3297 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3300 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3301 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3302 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3303 && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
3305 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3306 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3307 && const_double_rtx_ok_for_fpa (XEXP (x, 0))))
3310 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3311 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3312 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3313 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3314 || subcode == ASHIFTRT || subcode == LSHIFTRT
3315 || subcode == ROTATE || subcode == ROTATERT
3317 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3318 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3319 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3320 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3321 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3322 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3323 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3328 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3329 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3330 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3331 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3332 && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
3336 case AND: case XOR: case IOR:
3339 /* Normally the frame registers will be spilt into reg+const during
3340 reload, so it is a bad idea to combine them with other instructions,
3341 since then they might not be moved outside of loops. As a compromise
3342 we allow integration with ops that have a constant as their second
3344 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3345 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3346 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3347 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3348 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3352 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3353 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3354 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3355 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3358 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3359 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3360 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3361 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3362 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3365 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3366 return (1 + extra_cost
3367 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3368 || subcode == LSHIFTRT || subcode == ASHIFTRT
3369 || subcode == ROTATE || subcode == ROTATERT
3371 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3372 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3373 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3374 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3375 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3376 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3382 /* There is no point basing this on the tuning, since it is always the
3383 fast variant if it exists at all. */
3384 if (arm_fast_multiply && mode == DImode
3385 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3386 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3387 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3390 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3394 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3396 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3397 & (unsigned HOST_WIDE_INT) 0xffffffff);
3398 int cost, const_ok = const_ok_for_arm (i);
3399 int j, booth_unit_size;
3401 if (arm_tune_xscale)
3403 unsigned HOST_WIDE_INT masked_const;
3405 /* The cost will be related to two insns.
3406 First a load of the constant (MOV or LDR), then a multiply. */
3409 cost += 1; /* LDR is probably more expensive because
3410 of longer result latency. */
3411 masked_const = i & 0xffff8000;
3412 if (masked_const != 0 && masked_const != 0xffff8000)
3414 masked_const = i & 0xf8000000;
3415 if (masked_const == 0 || masked_const == 0xf8000000)
3423 /* Tune as appropriate. */
3424 cost = const_ok ? 4 : 8;
3425 booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
3426 for (j = 0; i && j < 32; j += booth_unit_size)
3428 i >>= booth_unit_size;
3435 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
3436 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3437 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
3440 if (arm_fast_multiply && mode == SImode
3441 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3442 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3443 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3444 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3445 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3446 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3451 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3452 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3456 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3458 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3461 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3469 return 4 + (mode == DImode ? 4 : 0);
3472 if (GET_MODE (XEXP (x, 0)) == QImode)
3473 return (4 + (mode == DImode ? 4 : 0)
3474 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3477 switch (GET_MODE (XEXP (x, 0)))
3480 return (1 + (mode == DImode ? 4 : 0)
3481 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3484 return (4 + (mode == DImode ? 4 : 0)
3485 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3488 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3503 if (const_ok_for_arm (INTVAL (x)))
3504 return outer == SET ? 2 : -1;
3505 else if (outer == AND
3506 && const_ok_for_arm (~INTVAL (x)))
3508 else if ((outer == COMPARE
3509 || outer == PLUS || outer == MINUS)
3510 && const_ok_for_arm (-INTVAL (x)))
3521 if (const_double_rtx_ok_for_fpa (x))
3522 return outer == SET ? 2 : -1;
3523 else if ((outer == COMPARE || outer == PLUS)
3524 && neg_const_double_rtx_ok_for_fpa (x))
3534 arm_rtx_costs (rtx x, int code, int outer_code, int *total)
3536 *total = arm_rtx_costs_1 (x, code, outer_code);
3540 /* All address computations that can be done are free, but rtx cost returns
3541 the same for practically all of them. So we weight the different types
3542 of address here in the order (most pref first):
3543 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3545 arm_arm_address_cost (rtx x)
3547 enum rtx_code c = GET_CODE (x);
3549 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
3551 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
3554 if (c == PLUS || c == MINUS)
3556 char cl0 = GET_RTX_CLASS (GET_CODE (XEXP (x, 0)));
3557 char cl1 = GET_RTX_CLASS (GET_CODE (XEXP (x, 1)));
3559 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
3562 if (cl0 == '2' || cl0 == 'c' || cl1 == '2' || cl1 == 'c')
3572 arm_thumb_address_cost (rtx x)
3574 enum rtx_code c = GET_CODE (x);
3579 && GET_CODE (XEXP (x, 0)) == REG
3580 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3587 arm_address_cost (rtx x)
3589 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
3593 arm_use_dfa_pipeline_interface (void)
3599 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
3603 /* Some true dependencies can have a higher cost depending
3604 on precisely how certain input operands are used. */
3606 && REG_NOTE_KIND (link) == 0
3607 && recog_memoized (insn) >= 0
3608 && recog_memoized (dep) >= 0)
3610 int shift_opnum = get_attr_shift (insn);
3611 enum attr_type attr_type = get_attr_type (dep);
3613 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3614 operand for INSN. If we have a shifted input operand and the
3615 instruction we depend on is another ALU instruction, then we may
3616 have to account for an additional stall. */
3617 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
3619 rtx shifted_operand;
3622 /* Get the shifted operand. */
3623 extract_insn (insn);
3624 shifted_operand = recog_data.operand[shift_opnum];
3626 /* Iterate over all the operands in DEP. If we write an operand
3627 that overlaps with SHIFTED_OPERAND, then we have increase the
3628 cost of this dependency. */
3630 preprocess_constraints ();
3631 for (opno = 0; opno < recog_data.n_operands; opno++)
3633 /* We can ignore strict inputs. */
3634 if (recog_data.operand_type[opno] == OP_IN)
3637 if (reg_overlap_mentioned_p (recog_data.operand[opno],
3644 /* XXX This is not strictly true for the FPA. */
3645 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
3646 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3649 /* Call insns don't incur a stall, even if they follow a load. */
3650 if (REG_NOTE_KIND (link) == 0
3651 && GET_CODE (insn) == CALL_INSN)
3654 if ((i_pat = single_set (insn)) != NULL
3655 && GET_CODE (SET_SRC (i_pat)) == MEM
3656 && (d_pat = single_set (dep)) != NULL
3657 && GET_CODE (SET_DEST (d_pat)) == MEM)
3659 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
3660 /* This is a load after a store, there is no conflict if the load reads
3661 from a cached area. Assume that loads from the stack, and from the
3662 constant pool are cached, and that others will miss. This is a
3665 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
3666 || reg_mentioned_p (stack_pointer_rtx, src_mem)
3667 || reg_mentioned_p (frame_pointer_rtx, src_mem)
3668 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
3675 static int fpa_consts_inited = 0;
3677 static const char * const strings_fpa[8] =
3680 "4", "5", "0.5", "10"
3683 static REAL_VALUE_TYPE values_fpa[8];
3686 init_fpa_table (void)
3691 for (i = 0; i < 8; i++)
3693 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
3697 fpa_consts_inited = 1;
3700 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3702 const_double_rtx_ok_for_fpa (rtx x)
3707 if (!fpa_consts_inited)
3710 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3711 if (REAL_VALUE_MINUS_ZERO (r))
3714 for (i = 0; i < 8; i++)
3715 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3721 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3723 neg_const_double_rtx_ok_for_fpa (rtx x)
3728 if (!fpa_consts_inited)
3731 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3732 r = REAL_VALUE_NEGATE (r);
3733 if (REAL_VALUE_MINUS_ZERO (r))
3736 for (i = 0; i < 8; i++)
3737 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3743 /* Predicates for `match_operand' and `match_operator'. */
3745 /* s_register_operand is the same as register_operand, but it doesn't accept
3748 This function exists because at the time it was put in it led to better
3749 code. SUBREG(MEM) always needs a reload in the places where
3750 s_register_operand is used, and this seemed to lead to excessive
3753 s_register_operand (rtx op, enum machine_mode mode)
3755 if (GET_MODE (op) != mode && mode != VOIDmode)
3758 if (GET_CODE (op) == SUBREG)
3759 op = SUBREG_REG (op);
3761 /* We don't consider registers whose class is NO_REGS
3762 to be a register operand. */
3763 /* XXX might have to check for lo regs only for thumb ??? */
3764 return (GET_CODE (op) == REG
3765 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3766 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3769 /* A hard register operand (even before reload. */
3771 arm_hard_register_operand (rtx op, enum machine_mode mode)
3773 if (GET_MODE (op) != mode && mode != VOIDmode)
3776 return (GET_CODE (op) == REG
3777 && REGNO (op) < FIRST_PSEUDO_REGISTER);
3780 /* Only accept reg, subreg(reg), const_int. */
3782 reg_or_int_operand (rtx op, enum machine_mode mode)
3784 if (GET_CODE (op) == CONST_INT)
3787 if (GET_MODE (op) != mode && mode != VOIDmode)
3790 if (GET_CODE (op) == SUBREG)
3791 op = SUBREG_REG (op);
3793 /* We don't consider registers whose class is NO_REGS
3794 to be a register operand. */
3795 return (GET_CODE (op) == REG
3796 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3797 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3800 /* Return 1 if OP is an item in memory, given that we are in reload. */
3802 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3804 int regno = true_regnum (op);
3806 return (!CONSTANT_P (op)
3808 || (GET_CODE (op) == REG
3809 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
3812 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3813 memory access (architecture V4).
3814 MODE is QImode if called when computing constraints, or VOIDmode when
3815 emitting patterns. In this latter case we cannot use memory_operand()
3816 because it will fail on badly formed MEMs, which is precisely what we are
3819 bad_signed_byte_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3821 if (GET_CODE (op) != MEM)
3826 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3827 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3828 && (!s_register_operand (XEXP (op, 0), VOIDmode)
3829 || (!s_register_operand (XEXP (op, 1), VOIDmode)
3830 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
3833 /* Big constants are also bad. */
3834 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
3835 && (INTVAL (XEXP (op, 1)) > 0xff
3836 || -INTVAL (XEXP (op, 1)) > 0xff))
3839 /* Everything else is good, or can will automatically be made so. */
3843 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3845 arm_rhs_operand (rtx op, enum machine_mode mode)
3847 return (s_register_operand (op, mode)
3848 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
3851 /* Return TRUE for valid operands for the
3852 rhs of an ARM instruction, or a load. */
3854 arm_rhsm_operand (rtx op, enum machine_mode mode)
3856 return (s_register_operand (op, mode)
3857 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
3858 || memory_operand (op, mode));
3861 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3862 constant that is valid when negated. */
3864 arm_add_operand (rtx op, enum machine_mode mode)
3867 return thumb_cmp_operand (op, mode);
3869 return (s_register_operand (op, mode)
3870 || (GET_CODE (op) == CONST_INT
3871 && (const_ok_for_arm (INTVAL (op))
3872 || const_ok_for_arm (-INTVAL (op)))));
3875 /* Return TRUE for valid ARM constants (or when valid if negated). */
3877 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3879 return (GET_CODE (op) == CONST_INT
3880 && (const_ok_for_arm (INTVAL (op))
3881 || const_ok_for_arm (-INTVAL (op))));
3885 arm_not_operand (rtx op, enum machine_mode mode)
3887 return (s_register_operand (op, mode)
3888 || (GET_CODE (op) == CONST_INT
3889 && (const_ok_for_arm (INTVAL (op))
3890 || const_ok_for_arm (~INTVAL (op)))));
3893 /* Return TRUE if the operand is a memory reference which contains an
3894 offsettable address. */
3896 offsettable_memory_operand (rtx op, enum machine_mode mode)
3898 if (mode == VOIDmode)
3899 mode = GET_MODE (op);
3901 return (mode == GET_MODE (op)
3902 && GET_CODE (op) == MEM
3903 && offsettable_address_p (reload_completed | reload_in_progress,
3904 mode, XEXP (op, 0)));
3907 /* Return TRUE if the operand is a memory reference which is, or can be
3908 made word aligned by adjusting the offset. */
3910 alignable_memory_operand (rtx op, enum machine_mode mode)
3914 if (mode == VOIDmode)
3915 mode = GET_MODE (op);
3917 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3922 return ((GET_CODE (reg = op) == REG
3923 || (GET_CODE (op) == SUBREG
3924 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3925 || (GET_CODE (op) == PLUS
3926 && GET_CODE (XEXP (op, 1)) == CONST_INT
3927 && (GET_CODE (reg = XEXP (op, 0)) == REG
3928 || (GET_CODE (XEXP (op, 0)) == SUBREG
3929 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3930 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3933 /* Similar to s_register_operand, but does not allow hard integer
3936 f_register_operand (rtx op, enum machine_mode mode)
3938 if (GET_MODE (op) != mode && mode != VOIDmode)
3941 if (GET_CODE (op) == SUBREG)
3942 op = SUBREG_REG (op);
3944 /* We don't consider registers whose class is NO_REGS
3945 to be a register operand. */
3946 return (GET_CODE (op) == REG
3947 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3948 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
3951 /* Return TRUE for valid operands for the rhs of an FPA instruction. */
3953 fpa_rhs_operand (rtx op, enum machine_mode mode)
3955 if (s_register_operand (op, mode))
3958 if (GET_MODE (op) != mode && mode != VOIDmode)
3961 if (GET_CODE (op) == CONST_DOUBLE)
3962 return const_double_rtx_ok_for_fpa (op);
3968 fpa_add_operand (rtx op, enum machine_mode mode)
3970 if (s_register_operand (op, mode))
3973 if (GET_MODE (op) != mode && mode != VOIDmode)
3976 if (GET_CODE (op) == CONST_DOUBLE)
3977 return (const_double_rtx_ok_for_fpa (op)
3978 || neg_const_double_rtx_ok_for_fpa (op));
3983 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
3985 cirrus_memory_offset (rtx op)
3987 /* Reject eliminable registers. */
3988 if (! (reload_in_progress || reload_completed)
3989 && ( reg_mentioned_p (frame_pointer_rtx, op)
3990 || reg_mentioned_p (arg_pointer_rtx, op)
3991 || reg_mentioned_p (virtual_incoming_args_rtx, op)
3992 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
3993 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
3994 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
3997 if (GET_CODE (op) == MEM)
4003 /* Match: (mem (reg)). */
4004 if (GET_CODE (ind) == REG)
4010 if (GET_CODE (ind) == PLUS
4011 && GET_CODE (XEXP (ind, 0)) == REG
4012 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4013 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4020 /* Return nonzero if OP is a Cirrus or general register. */
4022 cirrus_register_operand (rtx op, enum machine_mode mode)
4024 if (GET_MODE (op) != mode && mode != VOIDmode)
4027 if (GET_CODE (op) == SUBREG)
4028 op = SUBREG_REG (op);
4030 return (GET_CODE (op) == REG
4031 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4032 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4035 /* Return nonzero if OP is a cirrus FP register. */
4037 cirrus_fp_register (rtx op, enum machine_mode mode)
4039 if (GET_MODE (op) != mode && mode != VOIDmode)
4042 if (GET_CODE (op) == SUBREG)
4043 op = SUBREG_REG (op);
4045 return (GET_CODE (op) == REG
4046 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4047 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4050 /* Return nonzero if OP is a 6bit constant (0..63). */
4052 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4054 return (GET_CODE (op) == CONST_INT
4056 && INTVAL (op) < 64);
4059 /* Return true if X is a register that will be eliminated later on. */
4061 arm_eliminable_register (rtx x)
4063 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
4064 || REGNO (x) == ARG_POINTER_REGNUM
4065 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
4066 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
4069 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4070 Use by the Cirrus Maverick code which has to workaround
4071 a hardware bug triggered by such instructions. */
4073 arm_memory_load_p (rtx insn)
4075 rtx body, lhs, rhs;;
4077 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4080 body = PATTERN (insn);
4082 if (GET_CODE (body) != SET)
4085 lhs = XEXP (body, 0);
4086 rhs = XEXP (body, 1);
4088 lhs = REG_OR_SUBREG_RTX (lhs);
4090 /* If the destination is not a general purpose
4091 register we do not have to worry. */
4092 if (GET_CODE (lhs) != REG
4093 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4096 /* As well as loads from memory we also have to react
4097 to loads of invalid constants which will be turned
4098 into loads from the minipool. */
4099 return (GET_CODE (rhs) == MEM
4100 || GET_CODE (rhs) == SYMBOL_REF
4101 || note_invalid_constants (insn, -1, false));
4104 /* Return TRUE if INSN is a Cirrus instruction. */
4106 arm_cirrus_insn_p (rtx insn)
4108 enum attr_cirrus attr;
4110 /* get_attr aborts on USE and CLOBBER. */
4112 || GET_CODE (insn) != INSN
4113 || GET_CODE (PATTERN (insn)) == USE
4114 || GET_CODE (PATTERN (insn)) == CLOBBER)
4117 attr = get_attr_cirrus (insn);
4119 return attr != CIRRUS_NOT;
4122 /* Cirrus reorg for invalid instruction combinations. */
4124 cirrus_reorg (rtx first)
4126 enum attr_cirrus attr;
4127 rtx body = PATTERN (first);
4131 /* Any branch must be followed by 2 non Cirrus instructions. */
4132 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4135 t = next_nonnote_insn (first);
4137 if (arm_cirrus_insn_p (t))
4140 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4144 emit_insn_after (gen_nop (), first);
4149 /* (float (blah)) is in parallel with a clobber. */
4150 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4151 body = XVECEXP (body, 0, 0);
4153 if (GET_CODE (body) == SET)
4155 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4157 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4158 be followed by a non Cirrus insn. */
4159 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4161 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4162 emit_insn_after (gen_nop (), first);
4166 else if (arm_memory_load_p (first))
4168 unsigned int arm_regno;
4170 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4171 ldr/cfmv64hr combination where the Rd field is the same
4172 in both instructions must be split with a non Cirrus
4179 /* Get Arm register number for ldr insn. */
4180 if (GET_CODE (lhs) == REG)
4181 arm_regno = REGNO (lhs);
4182 else if (GET_CODE (rhs) == REG)
4183 arm_regno = REGNO (rhs);
4188 first = next_nonnote_insn (first);
4190 if (! arm_cirrus_insn_p (first))
4193 body = PATTERN (first);
4195 /* (float (blah)) is in parallel with a clobber. */
4196 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4197 body = XVECEXP (body, 0, 0);
4199 if (GET_CODE (body) == FLOAT)
4200 body = XEXP (body, 0);
4202 if (get_attr_cirrus (first) == CIRRUS_MOVE
4203 && GET_CODE (XEXP (body, 1)) == REG
4204 && arm_regno == REGNO (XEXP (body, 1)))
4205 emit_insn_after (gen_nop (), first);
4211 /* get_attr aborts on USE and CLOBBER. */
4213 || GET_CODE (first) != INSN
4214 || GET_CODE (PATTERN (first)) == USE
4215 || GET_CODE (PATTERN (first)) == CLOBBER)
4218 attr = get_attr_cirrus (first);
4220 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4221 must be followed by a non-coprocessor instruction. */
4222 if (attr == CIRRUS_COMPARE)
4226 t = next_nonnote_insn (first);
4228 if (arm_cirrus_insn_p (t))
4231 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4235 emit_insn_after (gen_nop (), first);
4241 /* Return nonzero if OP is a constant power of two. */
4243 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4245 if (GET_CODE (op) == CONST_INT)
4247 HOST_WIDE_INT value = INTVAL (op);
4249 return value != 0 && (value & (value - 1)) == 0;
4255 /* Return TRUE for a valid operand of a DImode operation.
4256 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4257 Note that this disallows MEM(REG+REG), but allows
4258 MEM(PRE/POST_INC/DEC(REG)). */
4260 di_operand (rtx op, enum machine_mode mode)
4262 if (s_register_operand (op, mode))
4265 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4268 if (GET_CODE (op) == SUBREG)
4269 op = SUBREG_REG (op);
4271 switch (GET_CODE (op))
4278 return memory_address_p (DImode, XEXP (op, 0));
4285 /* Like di_operand, but don't accept constants. */
4287 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4289 if (s_register_operand (op, mode))
4292 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4295 if (GET_CODE (op) == SUBREG)
4296 op = SUBREG_REG (op);
4298 if (GET_CODE (op) == MEM)
4299 return memory_address_p (DImode, XEXP (op, 0));
4304 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
4305 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4306 Note that this disallows MEM(REG+REG), but allows
4307 MEM(PRE/POST_INC/DEC(REG)). */
4309 soft_df_operand (rtx op, enum machine_mode mode)
4311 if (s_register_operand (op, mode))
4314 if (mode != VOIDmode && GET_MODE (op) != mode)
4317 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4320 if (GET_CODE (op) == SUBREG)
4321 op = SUBREG_REG (op);
4323 switch (GET_CODE (op))
4329 return memory_address_p (DFmode, XEXP (op, 0));
4336 /* Like soft_df_operand, but don't accept constants. */
4338 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4340 if (s_register_operand (op, mode))
4343 if (mode != VOIDmode && GET_MODE (op) != mode)
4346 if (GET_CODE (op) == SUBREG)
4347 op = SUBREG_REG (op);
4349 if (GET_CODE (op) == MEM)
4350 return memory_address_p (DFmode, XEXP (op, 0));
4354 /* Return TRUE for valid index operands. */
4356 index_operand (rtx op, enum machine_mode mode)
4358 return (s_register_operand (op, mode)
4359 || (immediate_operand (op, mode)
4360 && (GET_CODE (op) != CONST_INT
4361 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4364 /* Return TRUE for valid shifts by a constant. This also accepts any
4365 power of two on the (somewhat overly relaxed) assumption that the
4366 shift operator in this case was a mult. */
4368 const_shift_operand (rtx op, enum machine_mode mode)
4370 return (power_of_two_operand (op, mode)
4371 || (immediate_operand (op, mode)
4372 && (GET_CODE (op) != CONST_INT
4373 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
4376 /* Return TRUE for arithmetic operators which can be combined with a multiply
4379 shiftable_operator (rtx x, enum machine_mode mode)
4383 if (GET_MODE (x) != mode)
4386 code = GET_CODE (x);
4388 return (code == PLUS || code == MINUS
4389 || code == IOR || code == XOR || code == AND);
4392 /* Return TRUE for binary logical operators. */
4394 logical_binary_operator (rtx x, enum machine_mode mode)
4398 if (GET_MODE (x) != mode)
4401 code = GET_CODE (x);
4403 return (code == IOR || code == XOR || code == AND);
4406 /* Return TRUE for shift operators. */
4408 shift_operator (rtx x,enum machine_mode mode)
4412 if (GET_MODE (x) != mode)
4415 code = GET_CODE (x);
4418 return power_of_two_operand (XEXP (x, 1), mode);
4420 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
4421 || code == ROTATERT);
4424 /* Return TRUE if x is EQ or NE. */
4426 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
4428 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
4431 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4433 arm_comparison_operator (rtx x, enum machine_mode mode)
4435 return (comparison_operator (x, mode)
4436 && GET_CODE (x) != LTGT
4437 && GET_CODE (x) != UNEQ);
4440 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4442 minmax_operator (rtx x, enum machine_mode mode)
4444 enum rtx_code code = GET_CODE (x);
4446 if (GET_MODE (x) != mode)
4449 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
4452 /* Return TRUE if this is the condition code register, if we aren't given
4453 a mode, accept any class CCmode register. */
4455 cc_register (rtx x, enum machine_mode mode)
4457 if (mode == VOIDmode)
4459 mode = GET_MODE (x);
4461 if (GET_MODE_CLASS (mode) != MODE_CC)
4465 if ( GET_MODE (x) == mode
4466 && GET_CODE (x) == REG
4467 && REGNO (x) == CC_REGNUM)
4473 /* Return TRUE if this is the condition code register, if we aren't given
4474 a mode, accept any class CCmode register which indicates a dominance
4477 dominant_cc_register (rtx x, enum machine_mode mode)
4479 if (mode == VOIDmode)
4481 mode = GET_MODE (x);
4483 if (GET_MODE_CLASS (mode) != MODE_CC)
4487 if (mode != CC_DNEmode && mode != CC_DEQmode
4488 && mode != CC_DLEmode && mode != CC_DLTmode
4489 && mode != CC_DGEmode && mode != CC_DGTmode
4490 && mode != CC_DLEUmode && mode != CC_DLTUmode
4491 && mode != CC_DGEUmode && mode != CC_DGTUmode)
4494 return cc_register (x, mode);
4497 /* Return TRUE if X references a SYMBOL_REF. */
4499 symbol_mentioned_p (rtx x)
4504 if (GET_CODE (x) == SYMBOL_REF)
4507 fmt = GET_RTX_FORMAT (GET_CODE (x));
4509 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4515 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4516 if (symbol_mentioned_p (XVECEXP (x, i, j)))
4519 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
4526 /* Return TRUE if X references a LABEL_REF. */
4528 label_mentioned_p (rtx x)
4533 if (GET_CODE (x) == LABEL_REF)
4536 fmt = GET_RTX_FORMAT (GET_CODE (x));
4537 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4543 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4544 if (label_mentioned_p (XVECEXP (x, i, j)))
4547 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
4557 enum rtx_code code = GET_CODE (x);
4561 else if (code == SMIN)
4563 else if (code == UMIN)
4565 else if (code == UMAX)
4571 /* Return 1 if memory locations are adjacent. */
4573 adjacent_mem_locations (rtx a, rtx b)
4575 if ((GET_CODE (XEXP (a, 0)) == REG
4576 || (GET_CODE (XEXP (a, 0)) == PLUS
4577 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
4578 && (GET_CODE (XEXP (b, 0)) == REG
4579 || (GET_CODE (XEXP (b, 0)) == PLUS
4580 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
4582 HOST_WIDE_INT val0 = 0, val1 = 0;
4586 if (GET_CODE (XEXP (a, 0)) == PLUS)
4588 reg0 = XEXP (XEXP (a, 0), 0);
4589 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
4594 if (GET_CODE (XEXP (b, 0)) == PLUS)
4596 reg1 = XEXP (XEXP (b, 0), 0);
4597 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
4602 /* Don't accept any offset that will require multiple
4603 instructions to handle, since this would cause the
4604 arith_adjacentmem pattern to output an overlong sequence. */
4605 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
4608 /* Don't allow an eliminable register: register elimination can make
4609 the offset too large. */
4610 if (arm_eliminable_register (reg0))
4613 val_diff = val1 - val0;
4614 return ((REGNO (reg0) == REGNO (reg1))
4615 && (val_diff == 4 || val_diff == -4));
4621 /* Return 1 if OP is a load multiple operation. It is known to be
4622 parallel and the first section will be tested. */
4624 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4626 HOST_WIDE_INT count = XVECLEN (op, 0);
4629 HOST_WIDE_INT i = 1, base = 0;
4633 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4636 /* Check to see if this might be a write-back. */
4637 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4642 /* Now check it more carefully. */
4643 if (GET_CODE (SET_DEST (elt)) != REG
4644 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4645 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4646 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4650 /* Perform a quick check so we don't blow up below. */
4652 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4653 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
4654 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
4657 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
4658 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
4660 for (; i < count; i++)
4662 elt = XVECEXP (op, 0, i);
4664 if (GET_CODE (elt) != SET
4665 || GET_CODE (SET_DEST (elt)) != REG
4666 || GET_MODE (SET_DEST (elt)) != SImode
4667 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
4668 || GET_CODE (SET_SRC (elt)) != MEM
4669 || GET_MODE (SET_SRC (elt)) != SImode
4670 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
4671 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
4672 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
4673 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
4680 /* Return 1 if OP is a store multiple operation. It is known to be
4681 parallel and the first section will be tested. */
4683 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4685 HOST_WIDE_INT count = XVECLEN (op, 0);
4688 HOST_WIDE_INT i = 1, base = 0;
4692 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4695 /* Check to see if this might be a write-back. */
4696 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4701 /* Now check it more carefully. */
4702 if (GET_CODE (SET_DEST (elt)) != REG
4703 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4704 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4705 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4709 /* Perform a quick check so we don't blow up below. */
4711 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4712 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
4713 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
4716 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
4717 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
4719 for (; i < count; i++)
4721 elt = XVECEXP (op, 0, i);
4723 if (GET_CODE (elt) != SET
4724 || GET_CODE (SET_SRC (elt)) != REG
4725 || GET_MODE (SET_SRC (elt)) != SImode
4726 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
4727 || GET_CODE (SET_DEST (elt)) != MEM
4728 || GET_MODE (SET_DEST (elt)) != SImode
4729 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
4730 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
4731 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
4732 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
4740 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
4741 HOST_WIDE_INT *load_offset)
4743 int unsorted_regs[4];
4744 HOST_WIDE_INT unsorted_offsets[4];
4749 /* Can only handle 2, 3, or 4 insns at present,
4750 though could be easily extended if required. */
4751 if (nops < 2 || nops > 4)
4754 /* Loop over the operands and check that the memory references are
4755 suitable (ie immediate offsets from the same base register). At
4756 the same time, extract the target register, and the memory
4758 for (i = 0; i < nops; i++)
4763 /* Convert a subreg of a mem into the mem itself. */
4764 if (GET_CODE (operands[nops + i]) == SUBREG)
4765 operands[nops + i] = alter_subreg (operands + (nops + i));
4767 if (GET_CODE (operands[nops + i]) != MEM)
4770 /* Don't reorder volatile memory references; it doesn't seem worth
4771 looking for the case where the order is ok anyway. */
4772 if (MEM_VOLATILE_P (operands[nops + i]))
4775 offset = const0_rtx;
4777 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4778 || (GET_CODE (reg) == SUBREG
4779 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4780 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4781 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4783 || (GET_CODE (reg) == SUBREG
4784 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4785 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4790 base_reg = REGNO (reg);
4791 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4792 ? REGNO (operands[i])
4793 : REGNO (SUBREG_REG (operands[i])));
4798 if (base_reg != (int) REGNO (reg))
4799 /* Not addressed from the same base register. */
4802 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
4803 ? REGNO (operands[i])
4804 : REGNO (SUBREG_REG (operands[i])));
4805 if (unsorted_regs[i] < unsorted_regs[order[0]])
4809 /* If it isn't an integer register, or if it overwrites the
4810 base register but isn't the last insn in the list, then
4811 we can't do this. */
4812 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
4813 || (i != nops - 1 && unsorted_regs[i] == base_reg))
4816 unsorted_offsets[i] = INTVAL (offset);
4819 /* Not a suitable memory address. */
4823 /* All the useful information has now been extracted from the
4824 operands into unsorted_regs and unsorted_offsets; additionally,
4825 order[0] has been set to the lowest numbered register in the
4826 list. Sort the registers into order, and check that the memory
4827 offsets are ascending and adjacent. */
4829 for (i = 1; i < nops; i++)
4833 order[i] = order[i - 1];
4834 for (j = 0; j < nops; j++)
4835 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4836 && (order[i] == order[i - 1]
4837 || unsorted_regs[j] < unsorted_regs[order[i]]))
4840 /* Have we found a suitable register? if not, one must be used more
4842 if (order[i] == order[i - 1])
4845 /* Is the memory address adjacent and ascending? */
4846 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4854 for (i = 0; i < nops; i++)
4855 regs[i] = unsorted_regs[order[i]];
4857 *load_offset = unsorted_offsets[order[0]];
4860 if (unsorted_offsets[order[0]] == 0)
4861 return 1; /* ldmia */
4863 if (unsorted_offsets[order[0]] == 4)
4864 return 2; /* ldmib */
4866 if (unsorted_offsets[order[nops - 1]] == 0)
4867 return 3; /* ldmda */
4869 if (unsorted_offsets[order[nops - 1]] == -4)
4870 return 4; /* ldmdb */
4872 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4873 if the offset isn't small enough. The reason 2 ldrs are faster
4874 is because these ARMs are able to do more than one cache access
4875 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4876 whilst the ARM8 has a double bandwidth cache. This means that
4877 these cores can do both an instruction fetch and a data fetch in
4878 a single cycle, so the trick of calculating the address into a
4879 scratch register (one of the result regs) and then doing a load
4880 multiple actually becomes slower (and no smaller in code size).
4881 That is the transformation
4883 ldr rd1, [rbase + offset]
4884 ldr rd2, [rbase + offset + 4]
4888 add rd1, rbase, offset
4889 ldmia rd1, {rd1, rd2}
4891 produces worse code -- '3 cycles + any stalls on rd2' instead of
4892 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4893 access per cycle, the first sequence could never complete in less
4894 than 6 cycles, whereas the ldm sequence would only take 5 and
4895 would make better use of sequential accesses if not hitting the
4898 We cheat here and test 'arm_ld_sched' which we currently know to
4899 only be true for the ARM8, ARM9 and StrongARM. If this ever
4900 changes, then the test below needs to be reworked. */
4901 if (nops == 2 && arm_ld_sched)
4904 /* Can't do it without setting up the offset, only do this if it takes
4905 no more than one insn. */
4906 return (const_ok_for_arm (unsorted_offsets[order[0]])
4907 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
4911 emit_ldm_seq (rtx *operands, int nops)
4915 HOST_WIDE_INT offset;
4919 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4922 strcpy (buf, "ldm%?ia\t");
4926 strcpy (buf, "ldm%?ib\t");
4930 strcpy (buf, "ldm%?da\t");
4934 strcpy (buf, "ldm%?db\t");
4939 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4940 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4943 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4944 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4946 output_asm_insn (buf, operands);
4948 strcpy (buf, "ldm%?ia\t");
4955 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4956 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4958 for (i = 1; i < nops; i++)
4959 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4960 reg_names[regs[i]]);
4962 strcat (buf, "}\t%@ phole ldm");
4964 output_asm_insn (buf, operands);
4969 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
4970 HOST_WIDE_INT * load_offset)
4972 int unsorted_regs[4];
4973 HOST_WIDE_INT unsorted_offsets[4];
4978 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4979 extended if required. */
4980 if (nops < 2 || nops > 4)
4983 /* Loop over the operands and check that the memory references are
4984 suitable (ie immediate offsets from the same base register). At
4985 the same time, extract the target register, and the memory
4987 for (i = 0; i < nops; i++)
4992 /* Convert a subreg of a mem into the mem itself. */
4993 if (GET_CODE (operands[nops + i]) == SUBREG)
4994 operands[nops + i] = alter_subreg (operands + (nops + i));
4996 if (GET_CODE (operands[nops + i]) != MEM)
4999 /* Don't reorder volatile memory references; it doesn't seem worth
5000 looking for the case where the order is ok anyway. */
5001 if (MEM_VOLATILE_P (operands[nops + i]))
5004 offset = const0_rtx;
5006 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5007 || (GET_CODE (reg) == SUBREG
5008 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5009 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5010 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5012 || (GET_CODE (reg) == SUBREG
5013 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5014 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5019 base_reg = REGNO (reg);
5020 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5021 ? REGNO (operands[i])
5022 : REGNO (SUBREG_REG (operands[i])));
5027 if (base_reg != (int) REGNO (reg))
5028 /* Not addressed from the same base register. */
5031 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5032 ? REGNO (operands[i])
5033 : REGNO (SUBREG_REG (operands[i])));
5034 if (unsorted_regs[i] < unsorted_regs[order[0]])
5038 /* If it isn't an integer register, then we can't do this. */
5039 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5042 unsorted_offsets[i] = INTVAL (offset);
5045 /* Not a suitable memory address. */
5049 /* All the useful information has now been extracted from the
5050 operands into unsorted_regs and unsorted_offsets; additionally,
5051 order[0] has been set to the lowest numbered register in the
5052 list. Sort the registers into order, and check that the memory
5053 offsets are ascending and adjacent. */
5055 for (i = 1; i < nops; i++)
5059 order[i] = order[i - 1];
5060 for (j = 0; j < nops; j++)
5061 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5062 && (order[i] == order[i - 1]
5063 || unsorted_regs[j] < unsorted_regs[order[i]]))
5066 /* Have we found a suitable register? if not, one must be used more
5068 if (order[i] == order[i - 1])
5071 /* Is the memory address adjacent and ascending? */
5072 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5080 for (i = 0; i < nops; i++)
5081 regs[i] = unsorted_regs[order[i]];
5083 *load_offset = unsorted_offsets[order[0]];
5086 if (unsorted_offsets[order[0]] == 0)
5087 return 1; /* stmia */
5089 if (unsorted_offsets[order[0]] == 4)
5090 return 2; /* stmib */
5092 if (unsorted_offsets[order[nops - 1]] == 0)
5093 return 3; /* stmda */
5095 if (unsorted_offsets[order[nops - 1]] == -4)
5096 return 4; /* stmdb */
5102 emit_stm_seq (rtx *operands, int nops)
5106 HOST_WIDE_INT offset;
5110 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5113 strcpy (buf, "stm%?ia\t");
5117 strcpy (buf, "stm%?ib\t");
5121 strcpy (buf, "stm%?da\t");
5125 strcpy (buf, "stm%?db\t");
5132 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5133 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5135 for (i = 1; i < nops; i++)
5136 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5137 reg_names[regs[i]]);
5139 strcat (buf, "}\t%@ phole stm");
5141 output_asm_insn (buf, operands);
5146 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5148 if (GET_CODE (op) != PARALLEL
5149 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5150 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5151 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5157 /* Routines for use in generating RTL. */
5160 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5161 int write_back, int unchanging_p, int in_struct_p,
5166 int sign = up ? 1 : -1;
5169 /* XScale has load-store double instructions, but they have stricter
5170 alignment requirements than load-store multiple, so we can not
5173 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5174 the pipeline until completion.
5182 An ldr instruction takes 1-3 cycles, but does not block the
5191 Best case ldr will always win. However, the more ldr instructions
5192 we issue, the less likely we are to be able to schedule them well.
5193 Using ldr instructions also increases code size.
5195 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5196 for counts of 3 or 4 regs. */
5197 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5203 for (i = 0; i < count; i++)
5205 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5206 RTX_UNCHANGING_P (mem) = unchanging_p;
5207 MEM_IN_STRUCT_P (mem) = in_struct_p;
5208 MEM_SCALAR_P (mem) = scalar_p;
5209 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5213 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5221 result = gen_rtx_PARALLEL (VOIDmode,
5222 rtvec_alloc (count + (write_back ? 1 : 0)));
5225 XVECEXP (result, 0, 0)
5226 = gen_rtx_SET (GET_MODE (from), from,
5227 plus_constant (from, count * 4 * sign));
5232 for (j = 0; i < count; i++, j++)
5234 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5235 RTX_UNCHANGING_P (mem) = unchanging_p;
5236 MEM_IN_STRUCT_P (mem) = in_struct_p;
5237 MEM_SCALAR_P (mem) = scalar_p;
5238 XVECEXP (result, 0, i)
5239 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5246 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5247 int write_back, int unchanging_p, int in_struct_p,
5252 int sign = up ? 1 : -1;
5255 /* See arm_gen_load_multiple for discussion of
5256 the pros/cons of ldm/stm usage for XScale. */
5257 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5263 for (i = 0; i < count; i++)
5265 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5266 RTX_UNCHANGING_P (mem) = unchanging_p;
5267 MEM_IN_STRUCT_P (mem) = in_struct_p;
5268 MEM_SCALAR_P (mem) = scalar_p;
5269 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5273 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5281 result = gen_rtx_PARALLEL (VOIDmode,
5282 rtvec_alloc (count + (write_back ? 1 : 0)));
5285 XVECEXP (result, 0, 0)
5286 = gen_rtx_SET (GET_MODE (to), to,
5287 plus_constant (to, count * 4 * sign));
5292 for (j = 0; i < count; i++, j++)
5294 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5295 RTX_UNCHANGING_P (mem) = unchanging_p;
5296 MEM_IN_STRUCT_P (mem) = in_struct_p;
5297 MEM_SCALAR_P (mem) = scalar_p;
5299 XVECEXP (result, 0, i)
5300 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5307 arm_gen_movstrqi (rtx *operands)
5309 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5312 rtx st_src, st_dst, fin_src, fin_dst;
5313 rtx part_bytes_reg = NULL;
5315 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5316 int dst_scalar_p, src_scalar_p;
5318 if (GET_CODE (operands[2]) != CONST_INT
5319 || GET_CODE (operands[3]) != CONST_INT
5320 || INTVAL (operands[2]) > 64
5321 || INTVAL (operands[3]) & 3)
5324 st_dst = XEXP (operands[0], 0);
5325 st_src = XEXP (operands[1], 0);
5327 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5328 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5329 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5330 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5331 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5332 src_scalar_p = MEM_SCALAR_P (operands[1]);
5334 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5335 fin_src = src = copy_to_mode_reg (SImode, st_src);
5337 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5338 out_words_to_go = INTVAL (operands[2]) / 4;
5339 last_bytes = INTVAL (operands[2]) & 3;
5341 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5342 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5344 for (i = 0; in_words_to_go >= 2; i+=4)
5346 if (in_words_to_go > 4)
5347 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5352 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5353 FALSE, src_unchanging_p,
5354 src_in_struct_p, src_scalar_p));
5356 if (out_words_to_go)
5358 if (out_words_to_go > 4)
5359 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5363 else if (out_words_to_go != 1)
5364 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5373 mem = gen_rtx_MEM (SImode, dst);
5374 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5375 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5376 MEM_SCALAR_P (mem) = dst_scalar_p;
5377 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5378 if (last_bytes != 0)
5379 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5383 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5384 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5387 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5388 if (out_words_to_go)
5392 mem = gen_rtx_MEM (SImode, src);
5393 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5394 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5395 MEM_SCALAR_P (mem) = src_scalar_p;
5396 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
5397 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
5399 mem = gen_rtx_MEM (SImode, dst);
5400 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5401 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5402 MEM_SCALAR_P (mem) = dst_scalar_p;
5403 emit_move_insn (mem, sreg);
5404 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
5407 if (in_words_to_go) /* Sanity check */
5413 if (in_words_to_go < 0)
5416 mem = gen_rtx_MEM (SImode, src);
5417 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5418 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5419 MEM_SCALAR_P (mem) = src_scalar_p;
5420 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5423 if (last_bytes && part_bytes_reg == NULL)
5426 if (BYTES_BIG_ENDIAN && last_bytes)
5428 rtx tmp = gen_reg_rtx (SImode);
5430 /* The bytes we want are in the top end of the word. */
5431 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
5432 GEN_INT (8 * (4 - last_bytes))));
5433 part_bytes_reg = tmp;
5437 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
5438 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5439 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5440 MEM_SCALAR_P (mem) = dst_scalar_p;
5441 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5445 tmp = gen_reg_rtx (SImode);
5446 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
5447 part_bytes_reg = tmp;
5456 mem = gen_rtx_MEM (HImode, dst);
5457 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5458 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5459 MEM_SCALAR_P (mem) = dst_scalar_p;
5460 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
5464 rtx tmp = gen_reg_rtx (SImode);
5466 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
5467 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
5468 part_bytes_reg = tmp;
5474 mem = gen_rtx_MEM (QImode, dst);
5475 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5476 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5477 MEM_SCALAR_P (mem) = dst_scalar_p;
5478 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5485 /* Generate a memory reference for a half word, such that it will be loaded
5486 into the top 16 bits of the word. We can assume that the address is
5487 known to be alignable and of the form reg, or plus (reg, const). */
5490 arm_gen_rotated_half_load (rtx memref)
5492 HOST_WIDE_INT offset = 0;
5493 rtx base = XEXP (memref, 0);
5495 if (GET_CODE (base) == PLUS)
5497 offset = INTVAL (XEXP (base, 1));
5498 base = XEXP (base, 0);
5501 /* If we aren't allowed to generate unaligned addresses, then fail. */
5502 if (TARGET_MMU_TRAPS
5503 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
5506 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
5508 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
5511 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
5514 /* Select a dominance comparison mode if possible for a test of the general
5515 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5516 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5517 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5518 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5519 In all cases OP will be either EQ or NE, but we don't need to know which
5520 here. If we are unable to support a dominance comparison we return
5521 CC mode. This will then fail to match for the RTL expressions that
5522 generate this call. */
5524 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
5526 enum rtx_code cond1, cond2;
5529 /* Currently we will probably get the wrong result if the individual
5530 comparisons are not simple. This also ensures that it is safe to
5531 reverse a comparison if necessary. */
5532 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
5534 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
5538 /* The if_then_else variant of this tests the second condition if the
5539 first passes, but is true if the first fails. Reverse the first
5540 condition to get a true "inclusive-or" expression. */
5541 if (cond_or == DOM_CC_NX_OR_Y)
5542 cond1 = reverse_condition (cond1);
5544 /* If the comparisons are not equal, and one doesn't dominate the other,
5545 then we can't do this. */
5547 && !comparison_dominates_p (cond1, cond2)
5548 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
5553 enum rtx_code temp = cond1;
5561 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
5566 case LE: return CC_DLEmode;
5567 case LEU: return CC_DLEUmode;
5568 case GE: return CC_DGEmode;
5569 case GEU: return CC_DGEUmode;
5576 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
5585 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
5594 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
5603 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
5611 /* The remaining cases only occur when both comparisons are the
5636 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
5638 /* All floating point compares return CCFP if it is an equality
5639 comparison, and CCFPE otherwise. */
5640 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5669 /* A compare with a shifted operand. Because of canonicalization, the
5670 comparison will have to be swapped when we emit the assembler. */
5671 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
5672 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5673 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
5674 || GET_CODE (x) == ROTATERT))
5677 /* This is a special case that is used by combine to allow a
5678 comparison of a shifted byte load to be split into a zero-extend
5679 followed by a comparison of the shifted integer (only valid for
5680 equalities and unsigned inequalities). */
5681 if (GET_MODE (x) == SImode
5682 && GET_CODE (x) == ASHIFT
5683 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
5684 && GET_CODE (XEXP (x, 0)) == SUBREG
5685 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
5686 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
5687 && (op == EQ || op == NE
5688 || op == GEU || op == GTU || op == LTU || op == LEU)
5689 && GET_CODE (y) == CONST_INT)
5692 /* A construct for a conditional compare, if the false arm contains
5693 0, then both conditions must be true, otherwise either condition
5694 must be true. Not all conditions are possible, so CCmode is
5695 returned if it can't be done. */
5696 if (GET_CODE (x) == IF_THEN_ELSE
5697 && (XEXP (x, 2) == const0_rtx
5698 || XEXP (x, 2) == const1_rtx)
5699 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5700 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5701 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5702 INTVAL (XEXP (x, 2)));
5704 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5705 if (GET_CODE (x) == AND
5706 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5707 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5708 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5711 if (GET_CODE (x) == IOR
5712 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5713 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5714 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5717 /* An operation (on Thumb) where we want to test for a single bit.
5718 This is done by shifting that bit up into the top bit of a
5719 scratch register; we can then branch on the sign bit. */
5721 && GET_MODE (x) == SImode
5722 && (op == EQ || op == NE)
5723 && (GET_CODE (x) == ZERO_EXTRACT))
5726 /* An operation that sets the condition codes as a side-effect, the
5727 V flag is not set correctly, so we can only use comparisons where
5728 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5730 if (GET_MODE (x) == SImode
5732 && (op == EQ || op == NE || op == LT || op == GE)
5733 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
5734 || GET_CODE (x) == AND || GET_CODE (x) == IOR
5735 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
5736 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
5737 || GET_CODE (x) == LSHIFTRT
5738 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5739 || GET_CODE (x) == ROTATERT
5740 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
5743 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
5746 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
5747 && GET_CODE (x) == PLUS
5748 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
5754 /* X and Y are two things to compare using CODE. Emit the compare insn and
5755 return the rtx for register 0 in the proper mode. FP means this is a
5756 floating point compare: I don't think that it is needed on the arm. */
5758 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
5760 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
5761 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
5763 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5764 gen_rtx_COMPARE (mode, x, y)));
5769 /* Generate a sequence of insns that will generate the correct return
5770 address mask depending on the physical architecture that the program
5773 arm_gen_return_addr_mask (void)
5775 rtx reg = gen_reg_rtx (Pmode);
5777 emit_insn (gen_return_addr_mask (reg));
5782 arm_reload_in_hi (rtx *operands)
5784 rtx ref = operands[1];
5786 HOST_WIDE_INT offset = 0;
5788 if (GET_CODE (ref) == SUBREG)
5790 offset = SUBREG_BYTE (ref);
5791 ref = SUBREG_REG (ref);
5794 if (GET_CODE (ref) == REG)
5796 /* We have a pseudo which has been spilt onto the stack; there
5797 are two cases here: the first where there is a simple
5798 stack-slot replacement and a second where the stack-slot is
5799 out of range, or is used as a subreg. */
5800 if (reg_equiv_mem[REGNO (ref)])
5802 ref = reg_equiv_mem[REGNO (ref)];
5803 base = find_replacement (&XEXP (ref, 0));
5806 /* The slot is out of range, or was dressed up in a SUBREG. */
5807 base = reg_equiv_address[REGNO (ref)];
5810 base = find_replacement (&XEXP (ref, 0));
5812 /* Handle the case where the address is too complex to be offset by 1. */
5813 if (GET_CODE (base) == MINUS
5814 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5816 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5818 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5821 else if (GET_CODE (base) == PLUS)
5823 /* The addend must be CONST_INT, or we would have dealt with it above. */
5824 HOST_WIDE_INT hi, lo;
5826 offset += INTVAL (XEXP (base, 1));
5827 base = XEXP (base, 0);
5829 /* Rework the address into a legal sequence of insns. */
5830 /* Valid range for lo is -4095 -> 4095 */
5833 : -((-offset) & 0xfff));
5835 /* Corner case, if lo is the max offset then we would be out of range
5836 once we have added the additional 1 below, so bump the msb into the
5837 pre-loading insn(s). */
5841 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5842 ^ (HOST_WIDE_INT) 0x80000000)
5843 - (HOST_WIDE_INT) 0x80000000);
5845 if (hi + lo != offset)
5850 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5852 /* Get the base address; addsi3 knows how to handle constants
5853 that require more than one insn. */
5854 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5860 /* Operands[2] may overlap operands[0] (though it won't overlap
5861 operands[1]), that's why we asked for a DImode reg -- so we can
5862 use the bit that does not overlap. */
5863 if (REGNO (operands[2]) == REGNO (operands[0]))
5864 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5866 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5868 emit_insn (gen_zero_extendqisi2 (scratch,
5869 gen_rtx_MEM (QImode,
5870 plus_constant (base,
5872 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
5873 gen_rtx_MEM (QImode,
5874 plus_constant (base,
5876 if (!BYTES_BIG_ENDIAN)
5877 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5878 gen_rtx_IOR (SImode,
5881 gen_rtx_SUBREG (SImode, operands[0], 0),
5885 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5886 gen_rtx_IOR (SImode,
5887 gen_rtx_ASHIFT (SImode, scratch,
5889 gen_rtx_SUBREG (SImode, operands[0],
5893 /* Handle storing a half-word to memory during reload by synthesizing as two
5894 byte stores. Take care not to clobber the input values until after we
5895 have moved them somewhere safe. This code assumes that if the DImode
5896 scratch in operands[2] overlaps either the input value or output address
5897 in some way, then that value must die in this insn (we absolutely need
5898 two scratch registers for some corner cases). */
5900 arm_reload_out_hi (rtx *operands)
5902 rtx ref = operands[0];
5903 rtx outval = operands[1];
5905 HOST_WIDE_INT offset = 0;
5907 if (GET_CODE (ref) == SUBREG)
5909 offset = SUBREG_BYTE (ref);
5910 ref = SUBREG_REG (ref);
5913 if (GET_CODE (ref) == REG)
5915 /* We have a pseudo which has been spilt onto the stack; there
5916 are two cases here: the first where there is a simple
5917 stack-slot replacement and a second where the stack-slot is
5918 out of range, or is used as a subreg. */
5919 if (reg_equiv_mem[REGNO (ref)])
5921 ref = reg_equiv_mem[REGNO (ref)];
5922 base = find_replacement (&XEXP (ref, 0));
5925 /* The slot is out of range, or was dressed up in a SUBREG. */
5926 base = reg_equiv_address[REGNO (ref)];
5929 base = find_replacement (&XEXP (ref, 0));
5931 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5933 /* Handle the case where the address is too complex to be offset by 1. */
5934 if (GET_CODE (base) == MINUS
5935 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5937 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5939 /* Be careful not to destroy OUTVAL. */
5940 if (reg_overlap_mentioned_p (base_plus, outval))
5942 /* Updating base_plus might destroy outval, see if we can
5943 swap the scratch and base_plus. */
5944 if (!reg_overlap_mentioned_p (scratch, outval))
5947 scratch = base_plus;
5952 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5954 /* Be conservative and copy OUTVAL into the scratch now,
5955 this should only be necessary if outval is a subreg
5956 of something larger than a word. */
5957 /* XXX Might this clobber base? I can't see how it can,
5958 since scratch is known to overlap with OUTVAL, and
5959 must be wider than a word. */
5960 emit_insn (gen_movhi (scratch_hi, outval));
5961 outval = scratch_hi;
5965 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5968 else if (GET_CODE (base) == PLUS)
5970 /* The addend must be CONST_INT, or we would have dealt with it above. */
5971 HOST_WIDE_INT hi, lo;
5973 offset += INTVAL (XEXP (base, 1));
5974 base = XEXP (base, 0);
5976 /* Rework the address into a legal sequence of insns. */
5977 /* Valid range for lo is -4095 -> 4095 */
5980 : -((-offset) & 0xfff));
5982 /* Corner case, if lo is the max offset then we would be out of range
5983 once we have added the additional 1 below, so bump the msb into the
5984 pre-loading insn(s). */
5988 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5989 ^ (HOST_WIDE_INT) 0x80000000)
5990 - (HOST_WIDE_INT) 0x80000000);
5992 if (hi + lo != offset)
5997 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5999 /* Be careful not to destroy OUTVAL. */
6000 if (reg_overlap_mentioned_p (base_plus, outval))
6002 /* Updating base_plus might destroy outval, see if we
6003 can swap the scratch and base_plus. */
6004 if (!reg_overlap_mentioned_p (scratch, outval))
6007 scratch = base_plus;
6012 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6014 /* Be conservative and copy outval into scratch now,
6015 this should only be necessary if outval is a
6016 subreg of something larger than a word. */
6017 /* XXX Might this clobber base? I can't see how it
6018 can, since scratch is known to overlap with
6020 emit_insn (gen_movhi (scratch_hi, outval));
6021 outval = scratch_hi;
6025 /* Get the base address; addsi3 knows how to handle constants
6026 that require more than one insn. */
6027 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6033 if (BYTES_BIG_ENDIAN)
6035 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6036 plus_constant (base, offset + 1)),
6037 gen_lowpart (QImode, outval)));
6038 emit_insn (gen_lshrsi3 (scratch,
6039 gen_rtx_SUBREG (SImode, outval, 0),
6041 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6042 gen_lowpart (QImode, scratch)));
6046 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6047 gen_lowpart (QImode, outval)));
6048 emit_insn (gen_lshrsi3 (scratch,
6049 gen_rtx_SUBREG (SImode, outval, 0),
6051 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6052 plus_constant (base, offset + 1)),
6053 gen_lowpart (QImode, scratch)));
6057 /* Print a symbolic form of X to the debug file, F. */
6059 arm_print_value (FILE *f, rtx x)
6061 switch (GET_CODE (x))
6064 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6068 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6076 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6078 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6079 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6087 fprintf (f, "\"%s\"", XSTR (x, 0));
6091 fprintf (f, "`%s'", XSTR (x, 0));
6095 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6099 arm_print_value (f, XEXP (x, 0));
6103 arm_print_value (f, XEXP (x, 0));
6105 arm_print_value (f, XEXP (x, 1));
6113 fprintf (f, "????");
6118 /* Routines for manipulation of the constant pool. */
6120 /* Arm instructions cannot load a large constant directly into a
6121 register; they have to come from a pc relative load. The constant
6122 must therefore be placed in the addressable range of the pc
6123 relative load. Depending on the precise pc relative load
6124 instruction the range is somewhere between 256 bytes and 4k. This
6125 means that we often have to dump a constant inside a function, and
6126 generate code to branch around it.
6128 It is important to minimize this, since the branches will slow
6129 things down and make the code larger.
6131 Normally we can hide the table after an existing unconditional
6132 branch so that there is no interruption of the flow, but in the
6133 worst case the code looks like this:
6151 We fix this by performing a scan after scheduling, which notices
6152 which instructions need to have their operands fetched from the
6153 constant table and builds the table.
6155 The algorithm starts by building a table of all the constants that
6156 need fixing up and all the natural barriers in the function (places
6157 where a constant table can be dropped without breaking the flow).
6158 For each fixup we note how far the pc-relative replacement will be
6159 able to reach and the offset of the instruction into the function.
6161 Having built the table we then group the fixes together to form
6162 tables that are as large as possible (subject to addressing
6163 constraints) and emit each table of constants after the last
6164 barrier that is within range of all the instructions in the group.
6165 If a group does not contain a barrier, then we forcibly create one
6166 by inserting a jump instruction into the flow. Once the table has
6167 been inserted, the insns are then modified to reference the
6168 relevant entry in the pool.
6170 Possible enhancements to the algorithm (not implemented) are:
6172 1) For some processors and object formats, there may be benefit in
6173 aligning the pools to the start of cache lines; this alignment
6174 would need to be taken into account when calculating addressability
6177 /* These typedefs are located at the start of this file, so that
6178 they can be used in the prototypes there. This comment is to
6179 remind readers of that fact so that the following structures
6180 can be understood more easily.
6182 typedef struct minipool_node Mnode;
6183 typedef struct minipool_fixup Mfix; */
6185 struct minipool_node
6187 /* Doubly linked chain of entries. */
6190 /* The maximum offset into the code that this entry can be placed. While
6191 pushing fixes for forward references, all entries are sorted in order
6192 of increasing max_address. */
6193 HOST_WIDE_INT max_address;
6194 /* Similarly for an entry inserted for a backwards ref. */
6195 HOST_WIDE_INT min_address;
6196 /* The number of fixes referencing this entry. This can become zero
6197 if we "unpush" an entry. In this case we ignore the entry when we
6198 come to emit the code. */
6200 /* The offset from the start of the minipool. */
6201 HOST_WIDE_INT offset;
6202 /* The value in table. */
6204 /* The mode of value. */
6205 enum machine_mode mode;
6206 /* The size of the value. With iWMMXt enabled
6207 sizes > 4 also imply an alignment of 8-bytes. */
6211 struct minipool_fixup
6215 HOST_WIDE_INT address;
6217 enum machine_mode mode;
6221 HOST_WIDE_INT forwards;
6222 HOST_WIDE_INT backwards;
6225 /* Fixes less than a word need padding out to a word boundary. */
6226 #define MINIPOOL_FIX_SIZE(mode) \
6227 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6229 static Mnode * minipool_vector_head;
6230 static Mnode * minipool_vector_tail;
6231 static rtx minipool_vector_label;
6233 /* The linked list of all minipool fixes required for this function. */
6234 Mfix * minipool_fix_head;
6235 Mfix * minipool_fix_tail;
6236 /* The fix entry for the current minipool, once it has been placed. */
6237 Mfix * minipool_barrier;
6239 /* Determines if INSN is the start of a jump table. Returns the end
6240 of the TABLE or NULL_RTX. */
6242 is_jump_table (rtx insn)
6246 if (GET_CODE (insn) == JUMP_INSN
6247 && JUMP_LABEL (insn) != NULL
6248 && ((table = next_real_insn (JUMP_LABEL (insn)))
6249 == next_real_insn (insn))
6251 && GET_CODE (table) == JUMP_INSN
6252 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6253 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6259 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6260 #define JUMP_TABLES_IN_TEXT_SECTION 0
6263 static HOST_WIDE_INT
6264 get_jump_table_size (rtx insn)
6266 /* ADDR_VECs only take room if read-only data does into the text
6268 if (JUMP_TABLES_IN_TEXT_SECTION
6269 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6274 rtx body = PATTERN (insn);
6275 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6277 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6283 /* Move a minipool fix MP from its current location to before MAX_MP.
6284 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6285 constraints may need updating. */
6287 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6288 HOST_WIDE_INT max_address)
6290 /* This should never be true and the code below assumes these are
6297 if (max_address < mp->max_address)
6298 mp->max_address = max_address;
6302 if (max_address > max_mp->max_address - mp->fix_size)
6303 mp->max_address = max_mp->max_address - mp->fix_size;
6305 mp->max_address = max_address;
6307 /* Unlink MP from its current position. Since max_mp is non-null,
6308 mp->prev must be non-null. */
6309 mp->prev->next = mp->next;
6310 if (mp->next != NULL)
6311 mp->next->prev = mp->prev;
6313 minipool_vector_tail = mp->prev;
6315 /* Re-insert it before MAX_MP. */
6317 mp->prev = max_mp->prev;
6320 if (mp->prev != NULL)
6321 mp->prev->next = mp;
6323 minipool_vector_head = mp;
6326 /* Save the new entry. */
6329 /* Scan over the preceding entries and adjust their addresses as
6331 while (mp->prev != NULL
6332 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6334 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6341 /* Add a constant to the minipool for a forward reference. Returns the
6342 node added or NULL if the constant will not fit in this pool. */
6344 add_minipool_forward_ref (Mfix *fix)
6346 /* If set, max_mp is the first pool_entry that has a lower
6347 constraint than the one we are trying to add. */
6348 Mnode * max_mp = NULL;
6349 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6352 /* If this fix's address is greater than the address of the first
6353 entry, then we can't put the fix in this pool. We subtract the
6354 size of the current fix to ensure that if the table is fully
6355 packed we still have enough room to insert this value by suffling
6356 the other fixes forwards. */
6357 if (minipool_vector_head &&
6358 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6361 /* Scan the pool to see if a constant with the same value has
6362 already been added. While we are doing this, also note the
6363 location where we must insert the constant if it doesn't already
6365 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6367 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6368 && fix->mode == mp->mode
6369 && (GET_CODE (fix->value) != CODE_LABEL
6370 || (CODE_LABEL_NUMBER (fix->value)
6371 == CODE_LABEL_NUMBER (mp->value)))
6372 && rtx_equal_p (fix->value, mp->value))
6374 /* More than one fix references this entry. */
6376 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6379 /* Note the insertion point if necessary. */
6381 && mp->max_address > max_address)
6384 /* If we are inserting an 8-bytes aligned quantity and
6385 we have not already found an insertion point, then
6386 make sure that all such 8-byte aligned quantities are
6387 placed at the start of the pool. */
6388 if (TARGET_REALLY_IWMMXT
6390 && fix->fix_size == 8
6391 && mp->fix_size != 8)
6394 max_address = mp->max_address;
6398 /* The value is not currently in the minipool, so we need to create
6399 a new entry for it. If MAX_MP is NULL, the entry will be put on
6400 the end of the list since the placement is less constrained than
6401 any existing entry. Otherwise, we insert the new fix before
6402 MAX_MP and, if necessary, adjust the constraints on the other
6404 mp = xmalloc (sizeof (* mp));
6405 mp->fix_size = fix->fix_size;
6406 mp->mode = fix->mode;
6407 mp->value = fix->value;
6409 /* Not yet required for a backwards ref. */
6410 mp->min_address = -65536;
6414 mp->max_address = max_address;
6416 mp->prev = minipool_vector_tail;
6418 if (mp->prev == NULL)
6420 minipool_vector_head = mp;
6421 minipool_vector_label = gen_label_rtx ();
6424 mp->prev->next = mp;
6426 minipool_vector_tail = mp;
6430 if (max_address > max_mp->max_address - mp->fix_size)
6431 mp->max_address = max_mp->max_address - mp->fix_size;
6433 mp->max_address = max_address;
6436 mp->prev = max_mp->prev;
6438 if (mp->prev != NULL)
6439 mp->prev->next = mp;
6441 minipool_vector_head = mp;
6444 /* Save the new entry. */
6447 /* Scan over the preceding entries and adjust their addresses as
6449 while (mp->prev != NULL
6450 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6452 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6460 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
6461 HOST_WIDE_INT min_address)
6463 HOST_WIDE_INT offset;
6465 /* This should never be true, and the code below assumes these are
6472 if (min_address > mp->min_address)
6473 mp->min_address = min_address;
6477 /* We will adjust this below if it is too loose. */
6478 mp->min_address = min_address;
6480 /* Unlink MP from its current position. Since min_mp is non-null,
6481 mp->next must be non-null. */
6482 mp->next->prev = mp->prev;
6483 if (mp->prev != NULL)
6484 mp->prev->next = mp->next;
6486 minipool_vector_head = mp->next;
6488 /* Reinsert it after MIN_MP. */
6490 mp->next = min_mp->next;
6492 if (mp->next != NULL)
6493 mp->next->prev = mp;
6495 minipool_vector_tail = mp;
6501 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6503 mp->offset = offset;
6504 if (mp->refcount > 0)
6505 offset += mp->fix_size;
6507 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
6508 mp->next->min_address = mp->min_address + mp->fix_size;
6514 /* Add a constant to the minipool for a backward reference. Returns the
6515 node added or NULL if the constant will not fit in this pool.
6517 Note that the code for insertion for a backwards reference can be
6518 somewhat confusing because the calculated offsets for each fix do
6519 not take into account the size of the pool (which is still under
6522 add_minipool_backward_ref (Mfix *fix)
6524 /* If set, min_mp is the last pool_entry that has a lower constraint
6525 than the one we are trying to add. */
6526 Mnode *min_mp = NULL;
6527 /* This can be negative, since it is only a constraint. */
6528 HOST_WIDE_INT min_address = fix->address - fix->backwards;
6531 /* If we can't reach the current pool from this insn, or if we can't
6532 insert this entry at the end of the pool without pushing other
6533 fixes out of range, then we don't try. This ensures that we
6534 can't fail later on. */
6535 if (min_address >= minipool_barrier->address
6536 || (minipool_vector_tail->min_address + fix->fix_size
6537 >= minipool_barrier->address))
6540 /* Scan the pool to see if a constant with the same value has
6541 already been added. While we are doing this, also note the
6542 location where we must insert the constant if it doesn't already
6544 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
6546 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6547 && fix->mode == mp->mode
6548 && (GET_CODE (fix->value) != CODE_LABEL
6549 || (CODE_LABEL_NUMBER (fix->value)
6550 == CODE_LABEL_NUMBER (mp->value)))
6551 && rtx_equal_p (fix->value, mp->value)
6552 /* Check that there is enough slack to move this entry to the
6553 end of the table (this is conservative). */
6555 > (minipool_barrier->address
6556 + minipool_vector_tail->offset
6557 + minipool_vector_tail->fix_size)))
6560 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
6564 mp->min_address += fix->fix_size;
6567 /* Note the insertion point if necessary. */
6568 if (mp->min_address < min_address)
6570 /* For now, we do not allow the insertion of 8-byte alignment
6571 requiring nodes anywhere but at the start of the pool. */
6572 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8 && mp->fix_size != 8)
6577 else if (mp->max_address
6578 < minipool_barrier->address + mp->offset + fix->fix_size)
6580 /* Inserting before this entry would push the fix beyond
6581 its maximum address (which can happen if we have
6582 re-located a forwards fix); force the new fix to come
6585 min_address = mp->min_address + fix->fix_size;
6587 /* If we are inserting an 8-bytes aligned quantity and
6588 we have not already found an insertion point, then
6589 make sure that all such 8-byte aligned quantities are
6590 placed at the start of the pool. */
6591 else if (TARGET_REALLY_IWMMXT
6593 && fix->fix_size == 8
6594 && mp->fix_size < 8)
6597 min_address = mp->min_address + fix->fix_size;
6602 /* We need to create a new entry. */
6603 mp = xmalloc (sizeof (* mp));
6604 mp->fix_size = fix->fix_size;
6605 mp->mode = fix->mode;
6606 mp->value = fix->value;
6608 mp->max_address = minipool_barrier->address + 65536;
6610 mp->min_address = min_address;
6615 mp->next = minipool_vector_head;
6617 if (mp->next == NULL)
6619 minipool_vector_tail = mp;
6620 minipool_vector_label = gen_label_rtx ();
6623 mp->next->prev = mp;
6625 minipool_vector_head = mp;
6629 mp->next = min_mp->next;
6633 if (mp->next != NULL)
6634 mp->next->prev = mp;
6636 minipool_vector_tail = mp;
6639 /* Save the new entry. */
6647 /* Scan over the following entries and adjust their offsets. */
6648 while (mp->next != NULL)
6650 if (mp->next->min_address < mp->min_address + mp->fix_size)
6651 mp->next->min_address = mp->min_address + mp->fix_size;
6654 mp->next->offset = mp->offset + mp->fix_size;
6656 mp->next->offset = mp->offset;
6665 assign_minipool_offsets (Mfix *barrier)
6667 HOST_WIDE_INT offset = 0;
6670 minipool_barrier = barrier;
6672 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6674 mp->offset = offset;
6676 if (mp->refcount > 0)
6677 offset += mp->fix_size;
6681 /* Output the literal table */
6683 dump_minipool (rtx scan)
6689 if (TARGET_REALLY_IWMMXT)
6690 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6691 if (mp->refcount > 0 && mp->fix_size == 8)
6698 fprintf (rtl_dump_file,
6699 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
6700 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
6702 scan = emit_label_after (gen_label_rtx (), scan);
6703 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
6704 scan = emit_label_after (minipool_vector_label, scan);
6706 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
6708 if (mp->refcount > 0)
6712 fprintf (rtl_dump_file,
6713 ";; Offset %u, min %ld, max %ld ",
6714 (unsigned) mp->offset, (unsigned long) mp->min_address,
6715 (unsigned long) mp->max_address);
6716 arm_print_value (rtl_dump_file, mp->value);
6717 fputc ('\n', rtl_dump_file);
6720 switch (mp->fix_size)
6722 #ifdef HAVE_consttable_1
6724 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
6728 #ifdef HAVE_consttable_2
6730 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
6734 #ifdef HAVE_consttable_4
6736 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
6740 #ifdef HAVE_consttable_8
6742 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
6756 minipool_vector_head = minipool_vector_tail = NULL;
6757 scan = emit_insn_after (gen_consttable_end (), scan);
6758 scan = emit_barrier_after (scan);
6761 /* Return the cost of forcibly inserting a barrier after INSN. */
6763 arm_barrier_cost (rtx insn)
6765 /* Basing the location of the pool on the loop depth is preferable,
6766 but at the moment, the basic block information seems to be
6767 corrupt by this stage of the compilation. */
6769 rtx next = next_nonnote_insn (insn);
6771 if (next != NULL && GET_CODE (next) == CODE_LABEL)
6774 switch (GET_CODE (insn))
6777 /* It will always be better to place the table before the label, rather
6786 return base_cost - 10;
6789 return base_cost + 10;
6793 /* Find the best place in the insn stream in the range
6794 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6795 Create the barrier by inserting a jump and add a new fix entry for
6798 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
6800 HOST_WIDE_INT count = 0;
6802 rtx from = fix->insn;
6803 rtx selected = from;
6805 HOST_WIDE_INT selected_address;
6807 HOST_WIDE_INT max_count = max_address - fix->address;
6808 rtx label = gen_label_rtx ();
6810 selected_cost = arm_barrier_cost (from);
6811 selected_address = fix->address;
6813 while (from && count < max_count)
6818 /* This code shouldn't have been called if there was a natural barrier
6820 if (GET_CODE (from) == BARRIER)
6823 /* Count the length of this insn. */
6824 count += get_attr_length (from);
6826 /* If there is a jump table, add its length. */
6827 tmp = is_jump_table (from);
6830 count += get_jump_table_size (tmp);
6832 /* Jump tables aren't in a basic block, so base the cost on
6833 the dispatch insn. If we select this location, we will
6834 still put the pool after the table. */
6835 new_cost = arm_barrier_cost (from);
6837 if (count < max_count && new_cost <= selected_cost)
6840 selected_cost = new_cost;
6841 selected_address = fix->address + count;
6844 /* Continue after the dispatch table. */
6845 from = NEXT_INSN (tmp);
6849 new_cost = arm_barrier_cost (from);
6851 if (count < max_count && new_cost <= selected_cost)
6854 selected_cost = new_cost;
6855 selected_address = fix->address + count;
6858 from = NEXT_INSN (from);
6861 /* Create a new JUMP_INSN that branches around a barrier. */
6862 from = emit_jump_insn_after (gen_jump (label), selected);
6863 JUMP_LABEL (from) = label;
6864 barrier = emit_barrier_after (from);
6865 emit_label_after (label, barrier);
6867 /* Create a minipool barrier entry for the new barrier. */
6868 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
6869 new_fix->insn = barrier;
6870 new_fix->address = selected_address;
6871 new_fix->next = fix->next;
6872 fix->next = new_fix;
6877 /* Record that there is a natural barrier in the insn stream at
6880 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
6882 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6885 fix->address = address;
6888 if (minipool_fix_head != NULL)
6889 minipool_fix_tail->next = fix;
6891 minipool_fix_head = fix;
6893 minipool_fix_tail = fix;
6896 /* Record INSN, which will need fixing up to load a value from the
6897 minipool. ADDRESS is the offset of the insn since the start of the
6898 function; LOC is a pointer to the part of the insn which requires
6899 fixing; VALUE is the constant that must be loaded, which is of type
6902 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
6903 enum machine_mode mode, rtx value)
6905 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6907 #ifdef AOF_ASSEMBLER
6908 /* PIC symbol references need to be converted into offsets into the
6910 /* XXX This shouldn't be done here. */
6911 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
6912 value = aof_pic_entry (value);
6913 #endif /* AOF_ASSEMBLER */
6916 fix->address = address;
6919 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
6921 fix->forwards = get_attr_pool_range (insn);
6922 fix->backwards = get_attr_neg_pool_range (insn);
6923 fix->minipool = NULL;
6925 /* If an insn doesn't have a range defined for it, then it isn't
6926 expecting to be reworked by this code. Better to abort now than
6927 to generate duff assembly code. */
6928 if (fix->forwards == 0 && fix->backwards == 0)
6931 /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary.
6932 So there might be an empty word before the start of the pool.
6933 Hence we reduce the forward range by 4 to allow for this
6935 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8)
6940 fprintf (rtl_dump_file,
6941 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6942 GET_MODE_NAME (mode),
6943 INSN_UID (insn), (unsigned long) address,
6944 -1 * (long)fix->backwards, (long)fix->forwards);
6945 arm_print_value (rtl_dump_file, fix->value);
6946 fprintf (rtl_dump_file, "\n");
6949 /* Add it to the chain of fixes. */
6952 if (minipool_fix_head != NULL)
6953 minipool_fix_tail->next = fix;
6955 minipool_fix_head = fix;
6957 minipool_fix_tail = fix;
6960 /* Scan INSN and note any of its operands that need fixing.
6961 If DO_PUSHES is false we do not actually push any of the fixups
6962 needed. The function returns TRUE is any fixups were needed/pushed.
6963 This is used by arm_memory_load_p() which needs to know about loads
6964 of constants that will be converted into minipool loads. */
6966 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
6968 bool result = false;
6971 extract_insn (insn);
6973 if (!constrain_operands (1))
6974 fatal_insn_not_found (insn);
6976 if (recog_data.n_alternatives == 0)
6979 /* Fill in recog_op_alt with information about the constraints of this insn. */
6980 preprocess_constraints ();
6982 for (opno = 0; opno < recog_data.n_operands; opno++)
6984 /* Things we need to fix can only occur in inputs. */
6985 if (recog_data.operand_type[opno] != OP_IN)
6988 /* If this alternative is a memory reference, then any mention
6989 of constants in this alternative is really to fool reload
6990 into allowing us to accept one there. We need to fix them up
6991 now so that we output the right code. */
6992 if (recog_op_alt[opno][which_alternative].memory_ok)
6994 rtx op = recog_data.operand[opno];
6996 if (CONSTANT_P (op))
6999 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7000 recog_data.operand_mode[opno], op);
7003 else if (GET_CODE (op) == MEM
7004 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7005 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7009 rtx cop = avoid_constant_pool_reference (op);
7011 /* Casting the address of something to a mode narrower
7012 than a word can cause avoid_constant_pool_reference()
7013 to return the pool reference itself. That's no good to
7014 us here. Lets just hope that we can use the
7015 constant pool value directly. */
7017 cop = get_pool_constant (XEXP (op, 0));
7019 push_minipool_fix (insn, address,
7020 recog_data.operand_loc[opno],
7021 recog_data.operand_mode[opno], cop);
7032 /* Gcc puts the pool in the wrong place for ARM, since we can only
7033 load addresses a limited distance around the pc. We do some
7034 special munging to move the constant pool values to the correct
7035 point in the code. */
7040 HOST_WIDE_INT address = 0;
7043 minipool_fix_head = minipool_fix_tail = NULL;
7045 /* The first insn must always be a note, or the code below won't
7046 scan it properly. */
7047 insn = get_insns ();
7048 if (GET_CODE (insn) != NOTE)
7051 /* Scan all the insns and record the operands that will need fixing. */
7052 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7054 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7055 && (arm_cirrus_insn_p (insn)
7056 || GET_CODE (insn) == JUMP_INSN
7057 || arm_memory_load_p (insn)))
7058 cirrus_reorg (insn);
7060 if (GET_CODE (insn) == BARRIER)
7061 push_minipool_barrier (insn, address);
7062 else if (INSN_P (insn))
7066 note_invalid_constants (insn, address, true);
7067 address += get_attr_length (insn);
7069 /* If the insn is a vector jump, add the size of the table
7070 and skip the table. */
7071 if ((table = is_jump_table (insn)) != NULL)
7073 address += get_jump_table_size (table);
7079 fix = minipool_fix_head;
7081 /* Now scan the fixups and perform the required changes. */
7086 Mfix * last_added_fix;
7087 Mfix * last_barrier = NULL;
7090 /* Skip any further barriers before the next fix. */
7091 while (fix && GET_CODE (fix->insn) == BARRIER)
7094 /* No more fixes. */
7098 last_added_fix = NULL;
7100 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7102 if (GET_CODE (ftmp->insn) == BARRIER)
7104 if (ftmp->address >= minipool_vector_head->max_address)
7107 last_barrier = ftmp;
7109 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7112 last_added_fix = ftmp; /* Keep track of the last fix added. */
7115 /* If we found a barrier, drop back to that; any fixes that we
7116 could have reached but come after the barrier will now go in
7117 the next mini-pool. */
7118 if (last_barrier != NULL)
7120 /* Reduce the refcount for those fixes that won't go into this
7122 for (fdel = last_barrier->next;
7123 fdel && fdel != ftmp;
7126 fdel->minipool->refcount--;
7127 fdel->minipool = NULL;
7130 ftmp = last_barrier;
7134 /* ftmp is first fix that we can't fit into this pool and
7135 there no natural barriers that we could use. Insert a
7136 new barrier in the code somewhere between the previous
7137 fix and this one, and arrange to jump around it. */
7138 HOST_WIDE_INT max_address;
7140 /* The last item on the list of fixes must be a barrier, so
7141 we can never run off the end of the list of fixes without
7142 last_barrier being set. */
7146 max_address = minipool_vector_head->max_address;
7147 /* Check that there isn't another fix that is in range that
7148 we couldn't fit into this pool because the pool was
7149 already too large: we need to put the pool before such an
7151 if (ftmp->address < max_address)
7152 max_address = ftmp->address;
7154 last_barrier = create_fix_barrier (last_added_fix, max_address);
7157 assign_minipool_offsets (last_barrier);
7161 if (GET_CODE (ftmp->insn) != BARRIER
7162 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7169 /* Scan over the fixes we have identified for this pool, fixing them
7170 up and adding the constants to the pool itself. */
7171 for (this_fix = fix; this_fix && ftmp != this_fix;
7172 this_fix = this_fix->next)
7173 if (GET_CODE (this_fix->insn) != BARRIER)
7176 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7177 minipool_vector_label),
7178 this_fix->minipool->offset);
7179 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7182 dump_minipool (last_barrier->insn);
7186 /* From now on we must synthesize any constants that we can't handle
7187 directly. This can happen if the RTL gets split during final
7188 instruction generation. */
7189 after_arm_reorg = 1;
7191 /* Free the minipool memory. */
7192 obstack_free (&minipool_obstack, minipool_startobj);
7195 /* Routines to output assembly language. */
7197 /* If the rtx is the correct value then return the string of the number.
7198 In this way we can ensure that valid double constants are generated even
7199 when cross compiling. */
7201 fp_immediate_constant (rtx x)
7206 if (!fpa_consts_inited)
7209 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7210 for (i = 0; i < 8; i++)
7211 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
7212 return strings_fpa[i];
7217 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7219 fp_const_from_val (REAL_VALUE_TYPE *r)
7223 if (!fpa_consts_inited)
7226 for (i = 0; i < 8; i++)
7227 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
7228 return strings_fpa[i];
7233 /* Output the operands of a LDM/STM instruction to STREAM.
7234 MASK is the ARM register set mask of which only bits 0-15 are important.
7235 REG is the base register, either the frame pointer or the stack pointer,
7236 INSTR is the possibly suffixed load or store instruction. */
7238 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7241 int not_first = FALSE;
7243 fputc ('\t', stream);
7244 asm_fprintf (stream, instr, reg);
7245 fputs (", {", stream);
7247 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7248 if (mask & (1 << i))
7251 fprintf (stream, ", ");
7253 asm_fprintf (stream, "%r", i);
7257 fprintf (stream, "}");
7259 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7260 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7261 Strictly speaking the instruction would be unpredicatble only if
7262 we were writing back the base register as well, but since we never
7263 want to generate an LDM type 2 instruction (register bank switching)
7264 which is what you get if the PC is not being loaded, we do not need
7265 to check for writeback. */
7266 if (! TARGET_APCS_32
7267 && ((mask & (1 << PC_REGNUM)) != 0))
7268 fprintf (stream, "^");
7270 fprintf (stream, "\n");
7273 /* Output a 'call' insn. */
7275 output_call (rtx *operands)
7277 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7279 if (REGNO (operands[0]) == LR_REGNUM)
7281 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
7282 output_asm_insn ("mov%?\t%0, %|lr", operands);
7285 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7287 if (TARGET_INTERWORK)
7288 output_asm_insn ("bx%?\t%0", operands);
7290 output_asm_insn ("mov%?\t%|pc, %0", operands);
7295 /* Output a 'call' insn that is a reference in memory. */
7297 output_call_mem (rtx *operands)
7299 if (TARGET_INTERWORK)
7301 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7302 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7303 output_asm_insn ("bx%?\t%|ip", operands);
7305 else if (regno_use_in (LR_REGNUM, operands[0]))
7307 /* LR is used in the memory address. We load the address in the
7308 first instruction. It's safe to use IP as the target of the
7309 load since the call will kill it anyway. */
7310 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7311 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7312 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
7316 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7317 output_asm_insn ("ldr%?\t%|pc, %0", operands);
7323 /* Output a move from arm registers to an fpa registers.
7324 OPERANDS[0] is an fpa register.
7325 OPERANDS[1] is the first registers of an arm register pair. */
7327 output_mov_long_double_fpa_from_arm (rtx *operands)
7329 int arm_reg0 = REGNO (operands[1]);
7332 if (arm_reg0 == IP_REGNUM)
7335 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7336 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7337 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7339 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
7340 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
7345 /* Output a move from an fpa register to arm registers.
7346 OPERANDS[0] is the first registers of an arm register pair.
7347 OPERANDS[1] is an fpa register. */
7349 output_mov_long_double_arm_from_fpa (rtx *operands)
7351 int arm_reg0 = REGNO (operands[0]);
7354 if (arm_reg0 == IP_REGNUM)
7357 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7358 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7359 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7361 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
7362 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
7366 /* Output a move from arm registers to arm registers of a long double
7367 OPERANDS[0] is the destination.
7368 OPERANDS[1] is the source. */
7370 output_mov_long_double_arm_from_arm (rtx *operands)
7372 /* We have to be careful here because the two might overlap. */
7373 int dest_start = REGNO (operands[0]);
7374 int src_start = REGNO (operands[1]);
7378 if (dest_start < src_start)
7380 for (i = 0; i < 3; i++)
7382 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7383 ops[1] = gen_rtx_REG (SImode, src_start + i);
7384 output_asm_insn ("mov%?\t%0, %1", ops);
7389 for (i = 2; i >= 0; i--)
7391 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7392 ops[1] = gen_rtx_REG (SImode, src_start + i);
7393 output_asm_insn ("mov%?\t%0, %1", ops);
7401 /* Output a move from arm registers to an fpa registers.
7402 OPERANDS[0] is an fpa register.
7403 OPERANDS[1] is the first registers of an arm register pair. */
7405 output_mov_double_fpa_from_arm (rtx *operands)
7407 int arm_reg0 = REGNO (operands[1]);
7410 if (arm_reg0 == IP_REGNUM)
7413 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7414 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7415 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
7416 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
7420 /* Output a move from an fpa register to arm registers.
7421 OPERANDS[0] is the first registers of an arm register pair.
7422 OPERANDS[1] is an fpa register. */
7424 output_mov_double_arm_from_fpa (rtx *operands)
7426 int arm_reg0 = REGNO (operands[0]);
7429 if (arm_reg0 == IP_REGNUM)
7432 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7433 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7434 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
7435 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
7439 /* Output a move between double words.
7440 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7441 or MEM<-REG and all MEMs must be offsettable addresses. */
7443 output_move_double (rtx *operands)
7445 enum rtx_code code0 = GET_CODE (operands[0]);
7446 enum rtx_code code1 = GET_CODE (operands[1]);
7451 int reg0 = REGNO (operands[0]);
7453 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
7457 int reg1 = REGNO (operands[1]);
7458 if (reg1 == IP_REGNUM)
7461 /* Ensure the second source is not overwritten. */
7462 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
7463 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
7465 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
7467 else if (code1 == CONST_VECTOR)
7469 HOST_WIDE_INT hint = 0;
7471 switch (GET_MODE (operands[1]))
7474 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
7475 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
7479 if (BYTES_BIG_ENDIAN)
7481 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7483 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7487 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7489 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7492 otherops[1] = GEN_INT (hint);
7495 if (BYTES_BIG_ENDIAN)
7497 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7499 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7503 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7505 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7508 operands[1] = GEN_INT (hint);
7512 if (BYTES_BIG_ENDIAN)
7514 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7516 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7518 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7520 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7524 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7526 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7528 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7530 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7533 otherops[1] = GEN_INT (hint);
7536 if (BYTES_BIG_ENDIAN)
7538 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7540 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7542 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7544 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7548 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7550 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7552 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7554 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7557 operands[1] = GEN_INT (hint);
7563 output_mov_immediate (operands);
7564 output_mov_immediate (otherops);
7566 else if (code1 == CONST_DOUBLE)
7568 if (GET_MODE (operands[1]) == DFmode)
7573 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
7574 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
7575 otherops[1] = GEN_INT (l[1]);
7576 operands[1] = GEN_INT (l[0]);
7578 else if (GET_MODE (operands[1]) != VOIDmode)
7580 else if (WORDS_BIG_ENDIAN)
7582 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7583 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7587 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7588 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7591 output_mov_immediate (operands);
7592 output_mov_immediate (otherops);
7594 else if (code1 == CONST_INT)
7596 #if HOST_BITS_PER_WIDE_INT > 32
7597 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7598 what the upper word is. */
7599 if (WORDS_BIG_ENDIAN)
7601 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7602 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7606 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7607 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7610 /* Sign extend the intval into the high-order word. */
7611 if (WORDS_BIG_ENDIAN)
7613 otherops[1] = operands[1];
7614 operands[1] = (INTVAL (operands[1]) < 0
7615 ? constm1_rtx : const0_rtx);
7618 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
7620 output_mov_immediate (otherops);
7621 output_mov_immediate (operands);
7623 else if (code1 == MEM)
7625 switch (GET_CODE (XEXP (operands[1], 0)))
7628 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
7632 abort (); /* Should never happen now. */
7636 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
7640 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
7644 abort (); /* Should never happen now. */
7649 output_asm_insn ("adr%?\t%0, %1", operands);
7650 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
7654 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
7655 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
7657 otherops[0] = operands[0];
7658 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
7659 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
7661 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
7663 if (GET_CODE (otherops[2]) == CONST_INT)
7665 switch ((int) INTVAL (otherops[2]))
7668 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
7671 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
7674 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
7678 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
7679 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
7681 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7684 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7687 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
7689 return "ldm%?ia\t%0, %M0";
7693 otherops[1] = adjust_address (operands[1], SImode, 4);
7694 /* Take care of overlapping base/data reg. */
7695 if (reg_mentioned_p (operands[0], operands[1]))
7697 output_asm_insn ("ldr%?\t%0, %1", otherops);
7698 output_asm_insn ("ldr%?\t%0, %1", operands);
7702 output_asm_insn ("ldr%?\t%0, %1", operands);
7703 output_asm_insn ("ldr%?\t%0, %1", otherops);
7709 abort (); /* Constraints should prevent this. */
7711 else if (code0 == MEM && code1 == REG)
7713 if (REGNO (operands[1]) == IP_REGNUM)
7716 switch (GET_CODE (XEXP (operands[0], 0)))
7719 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
7723 abort (); /* Should never happen now. */
7727 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
7731 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
7735 abort (); /* Should never happen now. */
7739 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
7741 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
7744 output_asm_insn ("stm%?db\t%m0, %M1", operands);
7748 output_asm_insn ("stm%?da\t%m0, %M1", operands);
7752 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
7759 otherops[0] = adjust_address (operands[0], SImode, 4);
7760 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
7761 output_asm_insn ("str%?\t%1, %0", operands);
7762 output_asm_insn ("str%?\t%1, %0", otherops);
7766 /* Constraints should prevent this. */
7773 /* Output an arbitrary MOV reg, #n.
7774 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
7776 output_mov_immediate (rtx *operands)
7778 HOST_WIDE_INT n = INTVAL (operands[1]);
7780 /* Try to use one MOV. */
7781 if (const_ok_for_arm (n))
7782 output_asm_insn ("mov%?\t%0, %1", operands);
7784 /* Try to use one MVN. */
7785 else if (const_ok_for_arm (~n))
7787 operands[1] = GEN_INT (~n);
7788 output_asm_insn ("mvn%?\t%0, %1", operands);
7795 /* If all else fails, make it out of ORRs or BICs as appropriate. */
7796 for (i = 0; i < 32; i++)
7800 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
7801 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
7803 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
7809 /* Output an ADD r, s, #n where n may be too big for one instruction.
7810 If adding zero to one register, output nothing. */
7812 output_add_immediate (rtx *operands)
7814 HOST_WIDE_INT n = INTVAL (operands[2]);
7816 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
7819 output_multi_immediate (operands,
7820 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
7823 output_multi_immediate (operands,
7824 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
7831 /* Output a multiple immediate operation.
7832 OPERANDS is the vector of operands referred to in the output patterns.
7833 INSTR1 is the output pattern to use for the first constant.
7834 INSTR2 is the output pattern to use for subsequent constants.
7835 IMMED_OP is the index of the constant slot in OPERANDS.
7836 N is the constant value. */
7838 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
7839 int immed_op, HOST_WIDE_INT n)
7841 #if HOST_BITS_PER_WIDE_INT > 32
7847 /* Quick and easy output. */
7848 operands[immed_op] = const0_rtx;
7849 output_asm_insn (instr1, operands);
7854 const char * instr = instr1;
7856 /* Note that n is never zero here (which would give no output). */
7857 for (i = 0; i < 32; i += 2)
7861 operands[immed_op] = GEN_INT (n & (255 << i));
7862 output_asm_insn (instr, operands);
7872 /* Return the appropriate ARM instruction for the operation code.
7873 The returned result should not be overwritten. OP is the rtx of the
7874 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
7877 arithmetic_instr (rtx op, int shift_first_arg)
7879 switch (GET_CODE (op))
7885 return shift_first_arg ? "rsb" : "sub";
7901 /* Ensure valid constant shifts and return the appropriate shift mnemonic
7902 for the operation code. The returned result should not be overwritten.
7903 OP is the rtx code of the shift.
7904 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
7907 shift_op (rtx op, HOST_WIDE_INT *amountp)
7910 enum rtx_code code = GET_CODE (op);
7912 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
7914 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
7915 *amountp = INTVAL (XEXP (op, 1));
7938 /* We never have to worry about the amount being other than a
7939 power of 2, since this case can never be reloaded from a reg. */
7941 *amountp = int_log2 (*amountp);
7952 /* This is not 100% correct, but follows from the desire to merge
7953 multiplication by a power of 2 with the recognizer for a
7954 shift. >=32 is not a valid shift for "asl", so we must try and
7955 output a shift that produces the correct arithmetical result.
7956 Using lsr #32 is identical except for the fact that the carry bit
7957 is not set correctly if we set the flags; but we never use the
7958 carry bit from such an operation, so we can ignore that. */
7959 if (code == ROTATERT)
7960 /* Rotate is just modulo 32. */
7962 else if (*amountp != (*amountp & 31))
7969 /* Shifts of 0 are no-ops. */
7977 /* Obtain the shift from the POWER of two. */
7979 static HOST_WIDE_INT
7980 int_log2 (HOST_WIDE_INT power)
7982 HOST_WIDE_INT shift = 0;
7984 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
7994 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7995 /bin/as is horribly restrictive. */
7996 #define MAX_ASCII_LEN 51
7999 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8004 fputs ("\t.ascii\t\"", stream);
8006 for (i = 0; i < len; i++)
8010 if (len_so_far >= MAX_ASCII_LEN)
8012 fputs ("\"\n\t.ascii\t\"", stream);
8019 fputs ("\\t", stream);
8024 fputs ("\\f", stream);
8029 fputs ("\\b", stream);
8034 fputs ("\\r", stream);
8038 case TARGET_NEWLINE:
8039 fputs ("\\n", stream);
8041 if ((c >= ' ' && c <= '~')
8043 /* This is a good place for a line break. */
8044 len_so_far = MAX_ASCII_LEN;
8051 putc ('\\', stream);
8056 if (c >= ' ' && c <= '~')
8063 fprintf (stream, "\\%03o", c);
8070 fputs ("\"\n", stream);
8073 /* Compute the register sabe mask for registers 0 through 12
8074 inclusive. This code is used by both arm_compute_save_reg_mask
8075 and arm_compute_initial_elimination_offset. */
8076 static unsigned long
8077 arm_compute_save_reg0_reg12_mask (void)
8079 unsigned long func_type = arm_current_func_type ();
8080 unsigned int save_reg_mask = 0;
8083 if (IS_INTERRUPT (func_type))
8085 unsigned int max_reg;
8086 /* Interrupt functions must not corrupt any registers,
8087 even call clobbered ones. If this is a leaf function
8088 we can just examine the registers used by the RTL, but
8089 otherwise we have to assume that whatever function is
8090 called might clobber anything, and so we have to save
8091 all the call-clobbered registers as well. */
8092 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8093 /* FIQ handlers have registers r8 - r12 banked, so
8094 we only need to check r0 - r7, Normal ISRs only
8095 bank r14 and r15, so we must check up to r12.
8096 r13 is the stack pointer which is always preserved,
8097 so we do not need to consider it here. */
8102 for (reg = 0; reg <= max_reg; reg++)
8103 if (regs_ever_live[reg]
8104 || (! current_function_is_leaf && call_used_regs [reg]))
8105 save_reg_mask |= (1 << reg);
8109 /* In the normal case we only need to save those registers
8110 which are call saved and which are used by this function. */
8111 for (reg = 0; reg <= 10; reg++)
8112 if (regs_ever_live[reg] && ! call_used_regs [reg])
8113 save_reg_mask |= (1 << reg);
8115 /* Handle the frame pointer as a special case. */
8116 if (! TARGET_APCS_FRAME
8117 && ! frame_pointer_needed
8118 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8119 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8120 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8122 /* If we aren't loading the PIC register,
8123 don't stack it even though it may be live. */
8125 && ! TARGET_SINGLE_PIC_BASE
8126 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8127 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8130 return save_reg_mask;
8133 /* Compute a bit mask of which registers need to be
8134 saved on the stack for the current function. */
8136 static unsigned long
8137 arm_compute_save_reg_mask (void)
8139 unsigned int save_reg_mask = 0;
8140 unsigned long func_type = arm_current_func_type ();
8142 if (IS_NAKED (func_type))
8143 /* This should never really happen. */
8146 /* If we are creating a stack frame, then we must save the frame pointer,
8147 IP (which will hold the old stack pointer), LR and the PC. */
8148 if (frame_pointer_needed)
8150 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8155 /* Volatile functions do not return, so there
8156 is no need to save any other registers. */
8157 if (IS_VOLATILE (func_type))
8158 return save_reg_mask;
8160 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8162 /* Decide if we need to save the link register.
8163 Interrupt routines have their own banked link register,
8164 so they never need to save it.
8165 Otherwise if we do not use the link register we do not need to save
8166 it. If we are pushing other registers onto the stack however, we
8167 can save an instruction in the epilogue by pushing the link register
8168 now and then popping it back into the PC. This incurs extra memory
8169 accesses though, so we only do it when optimizing for size, and only
8170 if we know that we will not need a fancy return sequence. */
8171 if (regs_ever_live [LR_REGNUM]
8174 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8175 save_reg_mask |= 1 << LR_REGNUM;
8177 if (cfun->machine->lr_save_eliminated)
8178 save_reg_mask &= ~ (1 << LR_REGNUM);
8180 if (TARGET_REALLY_IWMMXT
8181 && ((bit_count (save_reg_mask)
8182 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8186 /* The total number of registers that are going to be pushed
8187 onto the stack is odd. We need to ensure that the stack
8188 is 64-bit aligned before we start to save iWMMXt registers,
8189 and also before we start to create locals. (A local variable
8190 might be a double or long long which we will load/store using
8191 an iWMMXt instruction). Therefore we need to push another
8192 ARM register, so that the stack will be 64-bit aligned. We
8193 try to avoid using the arg registers (r0 -r3) as they might be
8194 used to pass values in a tail call. */
8195 for (reg = 4; reg <= 12; reg++)
8196 if ((save_reg_mask & (1 << reg)) == 0)
8200 save_reg_mask |= (1 << reg);
8203 cfun->machine->sibcall_blocked = 1;
8204 save_reg_mask |= (1 << 3);
8208 return save_reg_mask;
8211 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
8212 everything bar the final return instruction. */
8214 output_return_instruction (rtx operand, int really_return, int reverse)
8216 char conditional[10];
8219 unsigned long live_regs_mask;
8220 unsigned long func_type;
8222 func_type = arm_current_func_type ();
8224 if (IS_NAKED (func_type))
8227 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8229 /* If this function was declared non-returning, and we have
8230 found a tail call, then we have to trust that the called
8231 function won't return. */
8236 /* Otherwise, trap an attempted return by aborting. */
8238 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
8240 assemble_external_libcall (ops[1]);
8241 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
8247 if (current_function_calls_alloca && !really_return)
8250 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
8252 return_used_this_function = 1;
8254 live_regs_mask = arm_compute_save_reg_mask ();
8258 const char * return_reg;
8260 /* If we do not have any special requirements for function exit
8261 (eg interworking, or ISR) then we can load the return address
8262 directly into the PC. Otherwise we must load it into LR. */
8264 && ! TARGET_INTERWORK)
8265 return_reg = reg_names[PC_REGNUM];
8267 return_reg = reg_names[LR_REGNUM];
8269 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
8271 /* There are three possible reasons for the IP register
8272 being saved. 1) a stack frame was created, in which case
8273 IP contains the old stack pointer, or 2) an ISR routine
8274 corrupted it, or 3) it was saved to align the stack on
8275 iWMMXt. In case 1, restore IP into SP, otherwise just
8277 if (frame_pointer_needed)
8279 live_regs_mask &= ~ (1 << IP_REGNUM);
8280 live_regs_mask |= (1 << SP_REGNUM);
8284 if (! IS_INTERRUPT (func_type)
8285 && ! TARGET_REALLY_IWMMXT)
8290 /* On some ARM architectures it is faster to use LDR rather than
8291 LDM to load a single register. On other architectures, the
8292 cost is the same. In 26 bit mode, or for exception handlers,
8293 we have to use LDM to load the PC so that the CPSR is also
8295 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8297 if (live_regs_mask == (unsigned int)(1 << reg))
8300 if (reg <= LAST_ARM_REGNUM
8301 && (reg != LR_REGNUM
8303 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
8305 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
8306 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
8313 /* Generate the load multiple instruction to restore the
8314 registers. Note we can get here, even if
8315 frame_pointer_needed is true, but only if sp already
8316 points to the base of the saved core registers. */
8317 if (live_regs_mask & (1 << SP_REGNUM))
8319 unsigned HOST_WIDE_INT stack_adjust =
8320 arm_get_frame_size () + current_function_outgoing_args_size;
8322 if (stack_adjust != 0 && stack_adjust != 4)
8325 if (stack_adjust && arm_arch5)
8326 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
8329 /* If we can't use ldmib (SA110 bug), then try to pop r3
8332 live_regs_mask |= 1 << 3;
8333 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
8337 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
8339 p = instr + strlen (instr);
8341 for (reg = 0; reg <= SP_REGNUM; reg++)
8342 if (live_regs_mask & (1 << reg))
8344 int l = strlen (reg_names[reg]);
8350 memcpy (p, ", ", 2);
8354 memcpy (p, "%|", 2);
8355 memcpy (p + 2, reg_names[reg], l);
8359 if (live_regs_mask & (1 << LR_REGNUM))
8361 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
8362 /* Decide if we need to add the ^ symbol to the end of the
8363 register list. This causes the saved condition codes
8364 register to be copied into the current condition codes
8365 register. We do the copy if we are conforming to the 32-bit
8366 ABI and this is an interrupt function, or if we are
8367 conforming to the 26-bit ABI. There is a special case for
8368 the 26-bit ABI however, which is if we are writing back the
8369 stack pointer but not loading the PC. In this case adding
8370 the ^ symbol would create a type 2 LDM instruction, where
8371 writeback is UNPREDICTABLE. We are safe in leaving the ^
8372 character off in this case however, since the actual return
8373 instruction will be a MOVS which will restore the CPSR. */
8374 if ((TARGET_APCS_32 && IS_INTERRUPT (func_type))
8375 || (! TARGET_APCS_32 && really_return))
8382 output_asm_insn (instr, & operand);
8384 /* See if we need to generate an extra instruction to
8385 perform the actual function return. */
8387 && func_type != ARM_FT_INTERWORKED
8388 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
8390 /* The return has already been handled
8391 by loading the LR into the PC. */
8398 switch ((int) ARM_FUNC_TYPE (func_type))
8402 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
8405 case ARM_FT_INTERWORKED:
8406 sprintf (instr, "bx%s\t%%|lr", conditional);
8409 case ARM_FT_EXCEPTION:
8410 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
8414 /* ARMv5 implementations always provide BX, so interworking
8415 is the default unless APCS-26 is in use. */
8416 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
8417 sprintf (instr, "bx%s\t%%|lr", conditional);
8419 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
8420 conditional, TARGET_APCS_32 ? "" : "s");
8424 output_asm_insn (instr, & operand);
8430 /* Write the function name into the code section, directly preceding
8431 the function prologue.
8433 Code will be output similar to this:
8435 .ascii "arm_poke_function_name", 0
8438 .word 0xff000000 + (t1 - t0)
8439 arm_poke_function_name
8441 stmfd sp!, {fp, ip, lr, pc}
8444 When performing a stack backtrace, code can inspect the value
8445 of 'pc' stored at 'fp' + 0. If the trace function then looks
8446 at location pc - 12 and the top 8 bits are set, then we know
8447 that there is a function name embedded immediately preceding this
8448 location and has length ((pc[-3]) & 0xff000000).
8450 We assume that pc is declared as a pointer to an unsigned long.
8452 It is of no benefit to output the function name if we are assembling
8453 a leaf function. These function types will not contain a stack
8454 backtrace structure, therefore it is not possible to determine the
8457 arm_poke_function_name (FILE *stream, const char *name)
8459 unsigned long alignlength;
8460 unsigned long length;
8463 length = strlen (name) + 1;
8464 alignlength = ROUND_UP_WORD (length);
8466 ASM_OUTPUT_ASCII (stream, name, length);
8467 ASM_OUTPUT_ALIGN (stream, 2);
8468 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
8469 assemble_aligned_integer (UNITS_PER_WORD, x);
8472 /* Place some comments into the assembler stream
8473 describing the current function. */
8475 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
8477 unsigned long func_type;
8481 thumb_output_function_prologue (f, frame_size);
8486 if (arm_ccfsm_state || arm_target_insn)
8489 func_type = arm_current_func_type ();
8491 switch ((int) ARM_FUNC_TYPE (func_type))
8496 case ARM_FT_INTERWORKED:
8497 asm_fprintf (f, "\t%@ Function supports interworking.\n");
8499 case ARM_FT_EXCEPTION_HANDLER:
8500 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
8503 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
8506 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
8508 case ARM_FT_EXCEPTION:
8509 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
8513 if (IS_NAKED (func_type))
8514 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
8516 if (IS_VOLATILE (func_type))
8517 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
8519 if (IS_NESTED (func_type))
8520 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
8522 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
8523 current_function_args_size,
8524 current_function_pretend_args_size, frame_size);
8526 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
8527 frame_pointer_needed,
8528 cfun->machine->uses_anonymous_args);
8530 if (cfun->machine->lr_save_eliminated)
8531 asm_fprintf (f, "\t%@ link register save eliminated.\n");
8533 #ifdef AOF_ASSEMBLER
8535 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
8538 return_used_this_function = 0;
8542 arm_output_epilogue (rtx sibling)
8545 unsigned long saved_regs_mask;
8546 unsigned long func_type;
8547 /* Floats_offset is the offset from the "virtual" frame. In an APCS
8548 frame that is $fp + 4 for a non-variadic function. */
8549 int floats_offset = 0;
8551 int frame_size = arm_get_frame_size ();
8552 FILE * f = asm_out_file;
8553 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
8554 unsigned int lrm_count = 0;
8555 int really_return = (sibling == NULL);
8557 /* If we have already generated the return instruction
8558 then it is futile to generate anything else. */
8559 if (use_return_insn (FALSE, sibling) && return_used_this_function)
8562 func_type = arm_current_func_type ();
8564 if (IS_NAKED (func_type))
8565 /* Naked functions don't have epilogues. */
8568 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8572 /* A volatile function should never return. Call abort. */
8573 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
8574 assemble_external_libcall (op);
8575 output_asm_insn ("bl\t%a0", &op);
8580 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
8582 /* If we are throwing an exception, then we really must
8583 be doing a return, so we can't tail-call. */
8586 saved_regs_mask = arm_compute_save_reg_mask ();
8589 lrm_count = bit_count (saved_regs_mask);
8591 /* XXX We should adjust floats_offset for any anonymous args, and then
8592 re-adjust vfp_offset below to compensate. */
8594 /* Compute how far away the floats will be. */
8595 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8596 if (saved_regs_mask & (1 << reg))
8599 if (frame_pointer_needed)
8603 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8605 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8606 if (regs_ever_live[reg] && !call_used_regs[reg])
8608 floats_offset += 12;
8609 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
8610 reg, FP_REGNUM, floats_offset - vfp_offset);
8615 int start_reg = LAST_ARM_FP_REGNUM;
8617 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8619 if (regs_ever_live[reg] && !call_used_regs[reg])
8621 floats_offset += 12;
8623 /* We can't unstack more than four registers at once. */
8624 if (start_reg - reg == 3)
8626 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
8627 reg, FP_REGNUM, floats_offset - vfp_offset);
8628 start_reg = reg - 1;
8633 if (reg != start_reg)
8634 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8635 reg + 1, start_reg - reg,
8636 FP_REGNUM, floats_offset - vfp_offset);
8637 start_reg = reg - 1;
8641 /* Just in case the last register checked also needs unstacking. */
8642 if (reg != start_reg)
8643 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8644 reg + 1, start_reg - reg,
8645 FP_REGNUM, floats_offset - vfp_offset);
8650 /* The frame pointer is guaranteed to be non-double-word aligned.
8651 This is because it is set to (old_stack_pointer - 4) and the
8652 old_stack_pointer was double word aligned. Thus the offset to
8653 the iWMMXt registers to be loaded must also be non-double-word
8654 sized, so that the resultant address *is* double-word aligned.
8655 We can ignore floats_offset since that was already included in
8656 the live_regs_mask. */
8657 lrm_count += (lrm_count % 2 ? 2 : 1);
8659 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
8660 if (regs_ever_live[reg] && !call_used_regs[reg])
8662 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
8663 reg, FP_REGNUM, lrm_count * 4);
8668 /* saved_regs_mask should contain the IP, which at the time of stack
8669 frame generation actually contains the old stack pointer. So a
8670 quick way to unwind the stack is just pop the IP register directly
8671 into the stack pointer. */
8672 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
8674 saved_regs_mask &= ~ (1 << IP_REGNUM);
8675 saved_regs_mask |= (1 << SP_REGNUM);
8677 /* There are two registers left in saved_regs_mask - LR and PC. We
8678 only need to restore the LR register (the return address), but to
8679 save time we can load it directly into the PC, unless we need a
8680 special function exit sequence, or we are not really returning. */
8681 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
8682 /* Delete the LR from the register mask, so that the LR on
8683 the stack is loaded into the PC in the register mask. */
8684 saved_regs_mask &= ~ (1 << LR_REGNUM);
8686 saved_regs_mask &= ~ (1 << PC_REGNUM);
8688 /* We must use SP as the base register, because SP is one of the
8689 registers being restored. If an interrupt or page fault
8690 happens in the ldm instruction, the SP might or might not
8691 have been restored. That would be bad, as then SP will no
8692 longer indicate the safe area of stack, and we can get stack
8693 corruption. Using SP as the base register means that it will
8694 be reset correctly to the original value, should an interrupt
8695 occur. If the stack pointer already points at the right
8696 place, then omit the subtraction. */
8697 if (((frame_size + current_function_outgoing_args_size + floats_offset)
8698 != 4 * (1 + (int) bit_count (saved_regs_mask)))
8699 || current_function_calls_alloca)
8700 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
8701 4 * bit_count (saved_regs_mask));
8702 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
8704 if (IS_INTERRUPT (func_type))
8705 /* Interrupt handlers will have pushed the
8706 IP onto the stack, so restore it now. */
8707 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
8711 /* Restore stack pointer if necessary. */
8712 if (frame_size + current_function_outgoing_args_size != 0)
8714 operands[0] = operands[1] = stack_pointer_rtx;
8715 operands[2] = GEN_INT (frame_size
8716 + current_function_outgoing_args_size);
8717 output_add_immediate (operands);
8720 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8722 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8723 if (regs_ever_live[reg] && !call_used_regs[reg])
8724 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
8729 int start_reg = FIRST_ARM_FP_REGNUM;
8731 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8733 if (regs_ever_live[reg] && !call_used_regs[reg])
8735 if (reg - start_reg == 3)
8737 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
8738 start_reg, SP_REGNUM);
8739 start_reg = reg + 1;
8744 if (reg != start_reg)
8745 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8746 start_reg, reg - start_reg,
8749 start_reg = reg + 1;
8753 /* Just in case the last register checked also needs unstacking. */
8754 if (reg != start_reg)
8755 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8756 start_reg, reg - start_reg, SP_REGNUM);
8760 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
8761 if (regs_ever_live[reg] && !call_used_regs[reg])
8762 asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM);
8764 /* If we can, restore the LR into the PC. */
8765 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8767 && current_function_pretend_args_size == 0
8768 && saved_regs_mask & (1 << LR_REGNUM))
8770 saved_regs_mask &= ~ (1 << LR_REGNUM);
8771 saved_regs_mask |= (1 << PC_REGNUM);
8774 /* Load the registers off the stack. If we only have one register
8775 to load use the LDR instruction - it is faster. */
8776 if (saved_regs_mask == (1 << LR_REGNUM))
8778 /* The exception handler ignores the LR, so we do
8779 not really need to load it off the stack. */
8781 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
8783 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
8785 else if (saved_regs_mask)
8787 if (saved_regs_mask & (1 << SP_REGNUM))
8788 /* Note - write back to the stack register is not enabled
8789 (ie "ldmfd sp!..."). We know that the stack pointer is
8790 in the list of registers and if we add writeback the
8791 instruction becomes UNPREDICTABLE. */
8792 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
8794 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
8797 if (current_function_pretend_args_size)
8799 /* Unwind the pre-pushed regs. */
8800 operands[0] = operands[1] = stack_pointer_rtx;
8801 operands[2] = GEN_INT (current_function_pretend_args_size);
8802 output_add_immediate (operands);
8807 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8808 && current_function_pretend_args_size == 0
8809 && saved_regs_mask & (1 << PC_REGNUM)))
8812 /* Generate the return instruction. */
8813 switch ((int) ARM_FUNC_TYPE (func_type))
8815 case ARM_FT_EXCEPTION_HANDLER:
8816 /* Even in 26-bit mode we do a mov (rather than a movs)
8817 because we don't have the PSR bits set in the address. */
8818 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
8823 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
8826 case ARM_FT_EXCEPTION:
8827 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8830 case ARM_FT_INTERWORKED:
8831 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
8835 if (frame_pointer_needed)
8836 /* If we used the frame pointer then the return address
8837 will have been loaded off the stack directly into the
8838 PC, so there is no need to issue a MOV instruction
8841 else if (current_function_pretend_args_size == 0
8842 && (saved_regs_mask & (1 << LR_REGNUM)))
8843 /* Similarly we may have been able to load LR into the PC
8844 even if we did not create a stack frame. */
8846 else if (TARGET_APCS_32)
8847 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8849 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8857 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8858 HOST_WIDE_INT frame_size)
8862 /* ??? Probably not safe to set this here, since it assumes that a
8863 function will be emitted as assembly immediately after we generate
8864 RTL for it. This does not happen for inline functions. */
8865 return_used_this_function = 0;
8869 /* We need to take into account any stack-frame rounding. */
8870 frame_size = arm_get_frame_size ();
8872 if (use_return_insn (FALSE, NULL)
8873 && return_used_this_function
8874 && (frame_size + current_function_outgoing_args_size) != 0
8875 && !frame_pointer_needed)
8878 /* Reset the ARM-specific per-function variables. */
8879 after_arm_reorg = 0;
8883 /* Generate and emit an insn that we will recognize as a push_multi.
8884 Unfortunately, since this insn does not reflect very well the actual
8885 semantics of the operation, we need to annotate the insn for the benefit
8886 of DWARF2 frame unwind information. */
8888 emit_multi_reg_push (int mask)
8895 int dwarf_par_index;
8898 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8899 if (mask & (1 << i))
8902 if (num_regs == 0 || num_regs > 16)
8905 /* We don't record the PC in the dwarf frame information. */
8906 num_dwarf_regs = num_regs;
8907 if (mask & (1 << PC_REGNUM))
8910 /* For the body of the insn we are going to generate an UNSPEC in
8911 parallel with several USEs. This allows the insn to be recognized
8912 by the push_multi pattern in the arm.md file. The insn looks
8913 something like this:
8916 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
8917 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
8918 (use (reg:SI 11 fp))
8919 (use (reg:SI 12 ip))
8920 (use (reg:SI 14 lr))
8921 (use (reg:SI 15 pc))
8924 For the frame note however, we try to be more explicit and actually
8925 show each register being stored into the stack frame, plus a (single)
8926 decrement of the stack pointer. We do it this way in order to be
8927 friendly to the stack unwinding code, which only wants to see a single
8928 stack decrement per instruction. The RTL we generate for the note looks
8929 something like this:
8932 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
8933 (set (mem:SI (reg:SI sp)) (reg:SI r4))
8934 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
8935 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
8936 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
8939 This sequence is used both by the code to support stack unwinding for
8940 exceptions handlers and the code to generate dwarf2 frame debugging. */
8942 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
8943 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
8944 dwarf_par_index = 1;
8946 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8948 if (mask & (1 << i))
8950 reg = gen_rtx_REG (SImode, i);
8953 = gen_rtx_SET (VOIDmode,
8954 gen_rtx_MEM (BLKmode,
8955 gen_rtx_PRE_DEC (BLKmode,
8956 stack_pointer_rtx)),
8957 gen_rtx_UNSPEC (BLKmode,
8963 tmp = gen_rtx_SET (VOIDmode,
8964 gen_rtx_MEM (SImode, stack_pointer_rtx),
8966 RTX_FRAME_RELATED_P (tmp) = 1;
8967 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
8975 for (j = 1, i++; j < num_regs; i++)
8977 if (mask & (1 << i))
8979 reg = gen_rtx_REG (SImode, i);
8981 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
8985 tmp = gen_rtx_SET (VOIDmode,
8986 gen_rtx_MEM (SImode,
8987 plus_constant (stack_pointer_rtx,
8990 RTX_FRAME_RELATED_P (tmp) = 1;
8991 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
8998 par = emit_insn (par);
9000 tmp = gen_rtx_SET (SImode,
9002 gen_rtx_PLUS (SImode,
9004 GEN_INT (-4 * num_regs)));
9005 RTX_FRAME_RELATED_P (tmp) = 1;
9006 XVECEXP (dwarf, 0, 0) = tmp;
9008 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9014 emit_sfm (int base_reg, int count)
9021 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9022 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9024 reg = gen_rtx_REG (XFmode, base_reg++);
9027 = gen_rtx_SET (VOIDmode,
9028 gen_rtx_MEM (BLKmode,
9029 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9030 gen_rtx_UNSPEC (BLKmode,
9034 = gen_rtx_SET (VOIDmode,
9035 gen_rtx_MEM (XFmode,
9036 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9038 RTX_FRAME_RELATED_P (tmp) = 1;
9039 XVECEXP (dwarf, 0, count - 1) = tmp;
9041 for (i = 1; i < count; i++)
9043 reg = gen_rtx_REG (XFmode, base_reg++);
9044 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9046 tmp = gen_rtx_SET (VOIDmode,
9047 gen_rtx_MEM (XFmode,
9048 gen_rtx_PRE_DEC (BLKmode,
9049 stack_pointer_rtx)),
9051 RTX_FRAME_RELATED_P (tmp) = 1;
9052 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9055 par = emit_insn (par);
9056 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9061 /* Compute the distance from register FROM to register TO.
9062 These can be the arg pointer (26), the soft frame pointer (25),
9063 the stack pointer (13) or the hard frame pointer (11).
9064 Typical stack layout looks like this:
9066 old stack pointer -> | |
9069 | | saved arguments for
9070 | | vararg functions
9073 hard FP & arg pointer -> | | \
9081 soft frame pointer -> | | /
9091 current stack pointer -> | | /
9094 For a given function some or all of these stack components
9095 may not be needed, giving rise to the possibility of
9096 eliminating some of the registers.
9098 The values returned by this function must reflect the behavior
9099 of arm_expand_prologue() and arm_compute_save_reg_mask().
9101 The sign of the number returned reflects the direction of stack
9102 growth, so the values are positive for all eliminations except
9103 from the soft frame pointer to the hard frame pointer. */
9105 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
9107 unsigned int local_vars = arm_get_frame_size ();
9108 unsigned int outgoing_args = current_function_outgoing_args_size;
9109 unsigned int stack_frame;
9110 unsigned int call_saved_registers;
9111 unsigned long func_type;
9113 func_type = arm_current_func_type ();
9115 /* Volatile functions never return, so there is
9116 no need to save call saved registers. */
9117 call_saved_registers = 0;
9118 if (! IS_VOLATILE (func_type))
9120 unsigned int reg_mask;
9123 /* Make sure that we compute which registers will be saved
9124 on the stack using the same algorithm that is used by
9125 the prologue creation code. */
9126 reg_mask = arm_compute_save_reg_mask ();
9128 /* Now count the number of bits set in save_reg_mask.
9129 If we have already counted the registers in the stack
9130 frame, do not count them again. Non call-saved registers
9131 might be saved in the call-save area of the stack, if
9132 doing so will preserve the stack's alignment. Hence we
9133 must count them here. For each set bit we need 4 bytes
9135 if (frame_pointer_needed)
9137 call_saved_registers += 4 * bit_count (reg_mask);
9139 /* If the hard floating point registers are going to be
9140 used then they must be saved on the stack as well.
9141 Each register occupies 12 bytes of stack space. */
9142 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
9143 if (regs_ever_live[reg] && ! call_used_regs[reg])
9144 call_saved_registers += 12;
9146 if (TARGET_REALLY_IWMMXT)
9147 /* Check for the call-saved iWMMXt registers. */
9148 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9149 if (regs_ever_live[reg] && ! call_used_regs [reg])
9150 call_saved_registers += 8;
9153 /* The stack frame contains 4 registers - the old frame pointer,
9154 the old stack pointer, the return address and PC of the start
9156 stack_frame = frame_pointer_needed ? 16 : 0;
9158 /* OK, now we have enough information to compute the distances.
9159 There must be an entry in these switch tables for each pair
9160 of registers in ELIMINABLE_REGS, even if some of the entries
9161 seem to be redundant or useless. */
9164 case ARG_POINTER_REGNUM:
9167 case THUMB_HARD_FRAME_POINTER_REGNUM:
9170 case FRAME_POINTER_REGNUM:
9171 /* This is the reverse of the soft frame pointer
9172 to hard frame pointer elimination below. */
9173 if (call_saved_registers == 0 && stack_frame == 0)
9175 return (call_saved_registers + stack_frame - 4);
9177 case ARM_HARD_FRAME_POINTER_REGNUM:
9178 /* If there is no stack frame then the hard
9179 frame pointer and the arg pointer coincide. */
9180 if (stack_frame == 0 && call_saved_registers != 0)
9182 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9183 return (frame_pointer_needed
9184 && current_function_needs_context
9185 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
9187 case STACK_POINTER_REGNUM:
9188 /* If nothing has been pushed on the stack at all
9189 then this will return -4. This *is* correct! */
9190 return call_saved_registers + stack_frame + local_vars + outgoing_args - 4;
9197 case FRAME_POINTER_REGNUM:
9200 case THUMB_HARD_FRAME_POINTER_REGNUM:
9203 case ARM_HARD_FRAME_POINTER_REGNUM:
9204 /* The hard frame pointer points to the top entry in the
9205 stack frame. The soft frame pointer to the bottom entry
9206 in the stack frame. If there is no stack frame at all,
9207 then they are identical. */
9208 if (call_saved_registers == 0 && stack_frame == 0)
9210 return - (call_saved_registers + stack_frame - 4);
9212 case STACK_POINTER_REGNUM:
9213 return local_vars + outgoing_args;
9221 /* You cannot eliminate from the stack pointer.
9222 In theory you could eliminate from the hard frame
9223 pointer to the stack pointer, but this will never
9224 happen, since if a stack frame is not needed the
9225 hard frame pointer will never be used. */
9230 /* Calculate the size of the stack frame, taking into account any
9231 padding that is required to ensure stack-alignment. */
9233 arm_get_frame_size (void)
9237 int base_size = ROUND_UP_WORD (get_frame_size ());
9239 unsigned long func_type = arm_current_func_type ();
9248 /* We need to know if we are a leaf function. Unfortunately, it
9249 is possible to be called after start_sequence has been called,
9250 which causes get_insns to return the insns for the sequence,
9251 not the function, which will cause leaf_function_p to return
9252 the incorrect result.
9254 To work around this, we cache the computed frame size. This
9255 works because we will only be calling RTL expanders that need
9256 to know about leaf functions once reload has completed, and the
9257 frame size cannot be changed after that time, so we can safely
9258 use the cached value. */
9260 if (reload_completed)
9261 return cfun->machine->frame_size;
9263 leaf = leaf_function_p ();
9265 /* A leaf function does not need any stack alignment if it has nothing
9267 if (leaf && base_size == 0)
9269 cfun->machine->frame_size = 0;
9273 /* We know that SP will be word aligned on entry, and we must
9274 preserve that condition at any subroutine call. But those are
9275 the only constraints. */
9277 /* Space for variadic functions. */
9278 if (current_function_pretend_args_size)
9279 entry_size += current_function_pretend_args_size;
9281 /* Space for saved registers. */
9282 entry_size += bit_count (arm_compute_save_reg_mask ()) * 4;
9284 /* Space for saved FPA registers. */
9285 if (! IS_VOLATILE (func_type))
9287 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
9288 if (regs_ever_live[regno] && ! call_used_regs[regno])
9292 if (TARGET_REALLY_IWMMXT)
9294 /* Check for the call-saved iWMMXt registers. */
9295 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
9296 if (regs_ever_live [regno] && ! call_used_regs [regno])
9300 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9302 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9305 cfun->machine->frame_size = base_size;
9310 /* Generate the prologue instructions for entry into an ARM function. */
9312 arm_expand_prologue (void)
9318 unsigned long live_regs_mask;
9319 unsigned long func_type;
9321 int saved_pretend_args = 0;
9322 unsigned int args_to_push;
9324 func_type = arm_current_func_type ();
9326 /* Naked functions don't have prologues. */
9327 if (IS_NAKED (func_type))
9330 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9331 args_to_push = current_function_pretend_args_size;
9333 /* Compute which register we will have to save onto the stack. */
9334 live_regs_mask = arm_compute_save_reg_mask ();
9336 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
9338 if (frame_pointer_needed)
9340 if (IS_INTERRUPT (func_type))
9342 /* Interrupt functions must not corrupt any registers.
9343 Creating a frame pointer however, corrupts the IP
9344 register, so we must push it first. */
9345 insn = emit_multi_reg_push (1 << IP_REGNUM);
9347 /* Do not set RTX_FRAME_RELATED_P on this insn.
9348 The dwarf stack unwinding code only wants to see one
9349 stack decrement per function, and this is not it. If
9350 this instruction is labeled as being part of the frame
9351 creation sequence then dwarf2out_frame_debug_expr will
9352 abort when it encounters the assignment of IP to FP
9353 later on, since the use of SP here establishes SP as
9354 the CFA register and not IP.
9356 Anyway this instruction is not really part of the stack
9357 frame creation although it is part of the prologue. */
9359 else if (IS_NESTED (func_type))
9361 /* The Static chain register is the same as the IP register
9362 used as a scratch register during stack frame creation.
9363 To get around this need to find somewhere to store IP
9364 whilst the frame is being created. We try the following
9367 1. The last argument register.
9368 2. A slot on the stack above the frame. (This only
9369 works if the function is not a varargs function).
9370 3. Register r3, after pushing the argument registers
9373 Note - we only need to tell the dwarf2 backend about the SP
9374 adjustment in the second variant; the static chain register
9375 doesn't need to be unwound, as it doesn't contain a value
9376 inherited from the caller. */
9378 if (regs_ever_live[3] == 0)
9380 insn = gen_rtx_REG (SImode, 3);
9381 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9382 insn = emit_insn (insn);
9384 else if (args_to_push == 0)
9387 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
9388 insn = gen_rtx_MEM (SImode, insn);
9389 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
9390 insn = emit_insn (insn);
9394 /* Just tell the dwarf backend that we adjusted SP. */
9395 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9396 gen_rtx_PLUS (SImode, stack_pointer_rtx,
9397 GEN_INT (-fp_offset)));
9398 RTX_FRAME_RELATED_P (insn) = 1;
9399 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9400 dwarf, REG_NOTES (insn));
9404 /* Store the args on the stack. */
9405 if (cfun->machine->uses_anonymous_args)
9406 insn = emit_multi_reg_push
9407 ((0xf0 >> (args_to_push / 4)) & 0xf);
9410 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9411 GEN_INT (- args_to_push)));
9413 RTX_FRAME_RELATED_P (insn) = 1;
9415 saved_pretend_args = 1;
9416 fp_offset = args_to_push;
9419 /* Now reuse r3 to preserve IP. */
9420 insn = gen_rtx_REG (SImode, 3);
9421 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9422 (void) emit_insn (insn);
9428 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
9429 insn = gen_rtx_SET (SImode, ip_rtx, insn);
9432 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
9434 insn = emit_insn (insn);
9435 RTX_FRAME_RELATED_P (insn) = 1;
9440 /* Push the argument registers, or reserve space for them. */
9441 if (cfun->machine->uses_anonymous_args)
9442 insn = emit_multi_reg_push
9443 ((0xf0 >> (args_to_push / 4)) & 0xf);
9446 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9447 GEN_INT (- args_to_push)));
9448 RTX_FRAME_RELATED_P (insn) = 1;
9451 /* If this is an interrupt service routine, and the link register
9452 is going to be pushed, and we are not creating a stack frame,
9453 (which would involve an extra push of IP and a pop in the epilogue)
9454 subtracting four from LR now will mean that the function return
9455 can be done with a single instruction. */
9456 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
9457 && (live_regs_mask & (1 << LR_REGNUM)) != 0
9458 && ! frame_pointer_needed)
9459 emit_insn (gen_rtx_SET (SImode,
9460 gen_rtx_REG (SImode, LR_REGNUM),
9461 gen_rtx_PLUS (SImode,
9462 gen_rtx_REG (SImode, LR_REGNUM),
9467 insn = emit_multi_reg_push (live_regs_mask);
9468 RTX_FRAME_RELATED_P (insn) = 1;
9472 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9473 if (regs_ever_live[reg] && ! call_used_regs [reg])
9475 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
9476 insn = gen_rtx_MEM (V2SImode, insn);
9477 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
9478 gen_rtx_REG (V2SImode, reg)));
9479 RTX_FRAME_RELATED_P (insn) = 1;
9482 if (! IS_VOLATILE (func_type))
9484 /* Save any floating point call-saved registers used by this
9486 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9488 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
9489 if (regs_ever_live[reg] && !call_used_regs[reg])
9491 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
9492 insn = gen_rtx_MEM (XFmode, insn);
9493 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
9494 gen_rtx_REG (XFmode, reg)));
9495 RTX_FRAME_RELATED_P (insn) = 1;
9500 int start_reg = LAST_ARM_FP_REGNUM;
9502 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
9504 if (regs_ever_live[reg] && !call_used_regs[reg])
9506 if (start_reg - reg == 3)
9508 insn = emit_sfm (reg, 4);
9509 RTX_FRAME_RELATED_P (insn) = 1;
9510 start_reg = reg - 1;
9515 if (start_reg != reg)
9517 insn = emit_sfm (reg + 1, start_reg - reg);
9518 RTX_FRAME_RELATED_P (insn) = 1;
9520 start_reg = reg - 1;
9524 if (start_reg != reg)
9526 insn = emit_sfm (reg + 1, start_reg - reg);
9527 RTX_FRAME_RELATED_P (insn) = 1;
9532 if (frame_pointer_needed)
9534 /* Create the new frame pointer. */
9535 insn = GEN_INT (-(4 + args_to_push + fp_offset));
9536 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
9537 RTX_FRAME_RELATED_P (insn) = 1;
9539 if (IS_NESTED (func_type))
9541 /* Recover the static chain register. */
9542 if (regs_ever_live [3] == 0
9543 || saved_pretend_args)
9544 insn = gen_rtx_REG (SImode, 3);
9545 else /* if (current_function_pretend_args_size == 0) */
9547 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
9549 insn = gen_rtx_MEM (SImode, insn);
9552 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
9553 /* Add a USE to stop propagate_one_insn() from barfing. */
9554 emit_insn (gen_prologue_use (ip_rtx));
9558 amount = GEN_INT (-(arm_get_frame_size ()
9559 + current_function_outgoing_args_size));
9561 if (amount != const0_rtx)
9563 /* This add can produce multiple insns for a large constant, so we
9564 need to get tricky. */
9565 rtx last = get_last_insn ();
9566 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9570 last = last ? NEXT_INSN (last) : get_insns ();
9571 RTX_FRAME_RELATED_P (last) = 1;
9573 while (last != insn);
9575 /* If the frame pointer is needed, emit a special barrier that
9576 will prevent the scheduler from moving stores to the frame
9577 before the stack adjustment. */
9578 if (frame_pointer_needed)
9579 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
9580 hard_frame_pointer_rtx));
9583 /* If we are profiling, make sure no instructions are scheduled before
9584 the call to mcount. Similarly if the user has requested no
9585 scheduling in the prolog. */
9586 if (current_function_profile || TARGET_NO_SCHED_PRO)
9587 emit_insn (gen_blockage ());
9589 /* If the link register is being kept alive, with the return address in it,
9590 then make sure that it does not get reused by the ce2 pass. */
9591 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
9593 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
9594 cfun->machine->lr_save_eliminated = 1;
9598 /* If CODE is 'd', then the X is a condition operand and the instruction
9599 should only be executed if the condition is true.
9600 if CODE is 'D', then the X is a condition operand and the instruction
9601 should only be executed if the condition is false: however, if the mode
9602 of the comparison is CCFPEmode, then always execute the instruction -- we
9603 do this because in these circumstances !GE does not necessarily imply LT;
9604 in these cases the instruction pattern will take care to make sure that
9605 an instruction containing %d will follow, thereby undoing the effects of
9606 doing this instruction unconditionally.
9607 If CODE is 'N' then X is a floating point operand that must be negated
9609 If CODE is 'B' then output a bitwise inverted value of X (a const int).
9610 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9612 arm_print_operand (FILE *stream, rtx x, int code)
9617 fputs (ASM_COMMENT_START, stream);
9621 fputs (user_label_prefix, stream);
9625 fputs (REGISTER_PREFIX, stream);
9629 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
9631 if (TARGET_THUMB || current_insn_predicate != NULL)
9634 fputs (arm_condition_codes[arm_current_cc], stream);
9636 else if (current_insn_predicate)
9638 enum arm_cond_code code;
9643 code = get_arm_condition_code (current_insn_predicate);
9644 fputs (arm_condition_codes[code], stream);
9651 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9652 r = REAL_VALUE_NEGATE (r);
9653 fprintf (stream, "%s", fp_const_from_val (&r));
9658 if (GET_CODE (x) == CONST_INT)
9661 val = ARM_SIGN_EXTEND (~INTVAL (x));
9662 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
9667 output_addr_const (stream, x);
9672 fprintf (stream, "%s", arithmetic_instr (x, 1));
9675 /* Truncate Cirrus shift counts. */
9677 if (GET_CODE (x) == CONST_INT)
9679 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
9682 arm_print_operand (stream, x, 0);
9686 fprintf (stream, "%s", arithmetic_instr (x, 0));
9692 const char * shift = shift_op (x, &val);
9696 fprintf (stream, ", %s ", shift_op (x, &val));
9698 arm_print_operand (stream, XEXP (x, 1), 0);
9700 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
9705 /* An explanation of the 'Q', 'R' and 'H' register operands:
9707 In a pair of registers containing a DI or DF value the 'Q'
9708 operand returns the register number of the register containing
9709 the least significant part of the value. The 'R' operand returns
9710 the register number of the register containing the most
9711 significant part of the value.
9713 The 'H' operand returns the higher of the two register numbers.
9714 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
9715 same as the 'Q' operand, since the most significant part of the
9716 value is held in the lower number register. The reverse is true
9717 on systems where WORDS_BIG_ENDIAN is false.
9719 The purpose of these operands is to distinguish between cases
9720 where the endian-ness of the values is important (for example
9721 when they are added together), and cases where the endian-ness
9722 is irrelevant, but the order of register operations is important.
9723 For example when loading a value from memory into a register
9724 pair, the endian-ness does not matter. Provided that the value
9725 from the lower memory address is put into the lower numbered
9726 register, and the value from the higher address is put into the
9727 higher numbered register, the load will work regardless of whether
9728 the value being loaded is big-wordian or little-wordian. The
9729 order of the two register loads can matter however, if the address
9730 of the memory location is actually held in one of the registers
9731 being overwritten by the load. */
9733 if (REGNO (x) > LAST_ARM_REGNUM)
9735 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
9739 if (REGNO (x) > LAST_ARM_REGNUM)
9741 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
9745 if (REGNO (x) > LAST_ARM_REGNUM)
9747 asm_fprintf (stream, "%r", REGNO (x) + 1);
9751 asm_fprintf (stream, "%r",
9752 GET_CODE (XEXP (x, 0)) == REG
9753 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
9757 asm_fprintf (stream, "{%r-%r}",
9759 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
9763 /* CONST_TRUE_RTX means always -- that's the default. */
9764 if (x == const_true_rtx)
9767 fputs (arm_condition_codes[get_arm_condition_code (x)],
9772 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
9774 if (x == const_true_rtx)
9777 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
9778 (get_arm_condition_code (x))],
9782 /* Cirrus registers can be accessed in a variety of ways:
9783 single floating point (f)
9784 double floating point (d)
9786 64bit integer (dx). */
9787 case 'W': /* Cirrus register in F mode. */
9788 case 'X': /* Cirrus register in D mode. */
9789 case 'Y': /* Cirrus register in FX mode. */
9790 case 'Z': /* Cirrus register in DX mode. */
9791 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9794 fprintf (stream, "mv%s%s",
9797 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
9801 /* Print cirrus register in the mode specified by the register's mode. */
9804 int mode = GET_MODE (x);
9806 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9809 fprintf (stream, "mv%s%s",
9810 mode == DFmode ? "d"
9811 : mode == SImode ? "fx"
9812 : mode == DImode ? "dx"
9813 : "f", reg_names[REGNO (x)] + 2);
9819 if (GET_CODE (x) != REG
9820 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
9821 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
9822 /* Bad value for wCG register number. */
9825 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
9828 /* Print an iWMMXt control register name. */
9830 if (GET_CODE (x) != CONST_INT
9832 || INTVAL (x) >= 16)
9833 /* Bad value for wC register number. */
9837 static const char * wc_reg_names [16] =
9839 "wCID", "wCon", "wCSSF", "wCASF",
9840 "wC4", "wC5", "wC6", "wC7",
9841 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
9842 "wC12", "wC13", "wC14", "wC15"
9845 fprintf (stream, wc_reg_names [INTVAL (x)]);
9853 if (GET_CODE (x) == REG)
9854 asm_fprintf (stream, "%r", REGNO (x));
9855 else if (GET_CODE (x) == MEM)
9857 output_memory_reference_mode = GET_MODE (x);
9858 output_address (XEXP (x, 0));
9860 else if (GET_CODE (x) == CONST_DOUBLE)
9861 fprintf (stream, "#%s", fp_immediate_constant (x));
9862 else if (GET_CODE (x) == NEG)
9863 abort (); /* This should never happen now. */
9866 fputc ('#', stream);
9867 output_addr_const (stream, x);
9872 #ifndef AOF_ASSEMBLER
9873 /* Target hook for assembling integer objects. The ARM version needs to
9874 handle word-sized values specially. */
9876 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
9878 if (size == UNITS_PER_WORD && aligned_p)
9880 fputs ("\t.word\t", asm_out_file);
9881 output_addr_const (asm_out_file, x);
9883 /* Mark symbols as position independent. We only do this in the
9884 .text segment, not in the .data segment. */
9885 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
9886 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
9888 if (GET_CODE (x) == SYMBOL_REF
9889 && (CONSTANT_POOL_ADDRESS_P (x)
9890 || SYMBOL_REF_LOCAL_P (x)))
9891 fputs ("(GOTOFF)", asm_out_file);
9892 else if (GET_CODE (x) == LABEL_REF)
9893 fputs ("(GOTOFF)", asm_out_file);
9895 fputs ("(GOT)", asm_out_file);
9897 fputc ('\n', asm_out_file);
9901 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
9905 if (GET_CODE (x) != CONST_VECTOR)
9908 units = CONST_VECTOR_NUNITS (x);
9910 switch (GET_MODE (x))
9912 case V2SImode: size = 4; break;
9913 case V4HImode: size = 2; break;
9914 case V8QImode: size = 1; break;
9919 for (i = 0; i < units; i++)
9923 elt = CONST_VECTOR_ELT (x, i);
9925 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
9931 return default_assemble_integer (x, size, aligned_p);
9935 /* A finite state machine takes care of noticing whether or not instructions
9936 can be conditionally executed, and thus decrease execution time and code
9937 size by deleting branch instructions. The fsm is controlled by
9938 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
9940 /* The state of the fsm controlling condition codes are:
9941 0: normal, do nothing special
9942 1: make ASM_OUTPUT_OPCODE not output this instruction
9943 2: make ASM_OUTPUT_OPCODE not output this instruction
9944 3: make instructions conditional
9945 4: make instructions conditional
9947 State transitions (state->state by whom under condition):
9948 0 -> 1 final_prescan_insn if the `target' is a label
9949 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
9950 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
9951 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
9952 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
9953 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
9954 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
9955 (the target insn is arm_target_insn).
9957 If the jump clobbers the conditions then we use states 2 and 4.
9959 A similar thing can be done with conditional return insns.
9961 XXX In case the `target' is an unconditional branch, this conditionalising
9962 of the instructions always reduces code size, but not always execution
9963 time. But then, I want to reduce the code size to somewhere near what
9964 /bin/cc produces. */
9966 /* Returns the index of the ARM condition code string in
9967 `arm_condition_codes'. COMPARISON should be an rtx like
9968 `(eq (...) (...))'. */
9969 static enum arm_cond_code
9970 get_arm_condition_code (rtx comparison)
9972 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
9974 enum rtx_code comp_code = GET_CODE (comparison);
9976 if (GET_MODE_CLASS (mode) != MODE_CC)
9977 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
9978 XEXP (comparison, 1));
9982 case CC_DNEmode: code = ARM_NE; goto dominance;
9983 case CC_DEQmode: code = ARM_EQ; goto dominance;
9984 case CC_DGEmode: code = ARM_GE; goto dominance;
9985 case CC_DGTmode: code = ARM_GT; goto dominance;
9986 case CC_DLEmode: code = ARM_LE; goto dominance;
9987 case CC_DLTmode: code = ARM_LT; goto dominance;
9988 case CC_DGEUmode: code = ARM_CS; goto dominance;
9989 case CC_DGTUmode: code = ARM_HI; goto dominance;
9990 case CC_DLEUmode: code = ARM_LS; goto dominance;
9991 case CC_DLTUmode: code = ARM_CC;
9994 if (comp_code != EQ && comp_code != NE)
9997 if (comp_code == EQ)
9998 return ARM_INVERSE_CONDITION_CODE (code);
10004 case NE: return ARM_NE;
10005 case EQ: return ARM_EQ;
10006 case GE: return ARM_PL;
10007 case LT: return ARM_MI;
10014 case NE: return ARM_NE;
10015 case EQ: return ARM_EQ;
10022 case NE: return ARM_MI;
10023 case EQ: return ARM_PL;
10029 /* These encodings assume that AC=1 in the FPA system control
10030 byte. This allows us to handle all cases except UNEQ and
10034 case GE: return ARM_GE;
10035 case GT: return ARM_GT;
10036 case LE: return ARM_LS;
10037 case LT: return ARM_MI;
10038 case NE: return ARM_NE;
10039 case EQ: return ARM_EQ;
10040 case ORDERED: return ARM_VC;
10041 case UNORDERED: return ARM_VS;
10042 case UNLT: return ARM_LT;
10043 case UNLE: return ARM_LE;
10044 case UNGT: return ARM_HI;
10045 case UNGE: return ARM_PL;
10046 /* UNEQ and LTGT do not have a representation. */
10047 case UNEQ: /* Fall through. */
10048 case LTGT: /* Fall through. */
10055 case NE: return ARM_NE;
10056 case EQ: return ARM_EQ;
10057 case GE: return ARM_LE;
10058 case GT: return ARM_LT;
10059 case LE: return ARM_GE;
10060 case LT: return ARM_GT;
10061 case GEU: return ARM_LS;
10062 case GTU: return ARM_CC;
10063 case LEU: return ARM_CS;
10064 case LTU: return ARM_HI;
10071 case LTU: return ARM_CS;
10072 case GEU: return ARM_CC;
10079 case NE: return ARM_NE;
10080 case EQ: return ARM_EQ;
10081 case GE: return ARM_GE;
10082 case GT: return ARM_GT;
10083 case LE: return ARM_LE;
10084 case LT: return ARM_LT;
10085 case GEU: return ARM_CS;
10086 case GTU: return ARM_HI;
10087 case LEU: return ARM_LS;
10088 case LTU: return ARM_CC;
10099 arm_final_prescan_insn (rtx insn)
10101 /* BODY will hold the body of INSN. */
10102 rtx body = PATTERN (insn);
10104 /* This will be 1 if trying to repeat the trick, and things need to be
10105 reversed if it appears to fail. */
10108 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
10109 taken are clobbered, even if the rtl suggests otherwise. It also
10110 means that we have to grub around within the jump expression to find
10111 out what the conditions are when the jump isn't taken. */
10112 int jump_clobbers = 0;
10114 /* If we start with a return insn, we only succeed if we find another one. */
10115 int seeking_return = 0;
10117 /* START_INSN will hold the insn from where we start looking. This is the
10118 first insn after the following code_label if REVERSE is true. */
10119 rtx start_insn = insn;
10121 /* If in state 4, check if the target branch is reached, in order to
10122 change back to state 0. */
10123 if (arm_ccfsm_state == 4)
10125 if (insn == arm_target_insn)
10127 arm_target_insn = NULL;
10128 arm_ccfsm_state = 0;
10133 /* If in state 3, it is possible to repeat the trick, if this insn is an
10134 unconditional branch to a label, and immediately following this branch
10135 is the previous target label which is only used once, and the label this
10136 branch jumps to is not too far off. */
10137 if (arm_ccfsm_state == 3)
10139 if (simplejump_p (insn))
10141 start_insn = next_nonnote_insn (start_insn);
10142 if (GET_CODE (start_insn) == BARRIER)
10144 /* XXX Isn't this always a barrier? */
10145 start_insn = next_nonnote_insn (start_insn);
10147 if (GET_CODE (start_insn) == CODE_LABEL
10148 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10149 && LABEL_NUSES (start_insn) == 1)
10154 else if (GET_CODE (body) == RETURN)
10156 start_insn = next_nonnote_insn (start_insn);
10157 if (GET_CODE (start_insn) == BARRIER)
10158 start_insn = next_nonnote_insn (start_insn);
10159 if (GET_CODE (start_insn) == CODE_LABEL
10160 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10161 && LABEL_NUSES (start_insn) == 1)
10164 seeking_return = 1;
10173 if (arm_ccfsm_state != 0 && !reverse)
10175 if (GET_CODE (insn) != JUMP_INSN)
10178 /* This jump might be paralleled with a clobber of the condition codes
10179 the jump should always come first */
10180 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
10181 body = XVECEXP (body, 0, 0);
10184 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
10185 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
10188 int fail = FALSE, succeed = FALSE;
10189 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
10190 int then_not_else = TRUE;
10191 rtx this_insn = start_insn, label = 0;
10193 /* If the jump cannot be done with one instruction, we cannot
10194 conditionally execute the instruction in the inverse case. */
10195 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
10201 /* Register the insn jumped to. */
10204 if (!seeking_return)
10205 label = XEXP (SET_SRC (body), 0);
10207 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
10208 label = XEXP (XEXP (SET_SRC (body), 1), 0);
10209 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
10211 label = XEXP (XEXP (SET_SRC (body), 2), 0);
10212 then_not_else = FALSE;
10214 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
10215 seeking_return = 1;
10216 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
10218 seeking_return = 1;
10219 then_not_else = FALSE;
10224 /* See how many insns this branch skips, and what kind of insns. If all
10225 insns are okay, and the label or unconditional branch to the same
10226 label is not too far away, succeed. */
10227 for (insns_skipped = 0;
10228 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
10232 this_insn = next_nonnote_insn (this_insn);
10236 switch (GET_CODE (this_insn))
10239 /* Succeed if it is the target label, otherwise fail since
10240 control falls in from somewhere else. */
10241 if (this_insn == label)
10245 arm_ccfsm_state = 2;
10246 this_insn = next_nonnote_insn (this_insn);
10249 arm_ccfsm_state = 1;
10257 /* Succeed if the following insn is the target label.
10259 If return insns are used then the last insn in a function
10260 will be a barrier. */
10261 this_insn = next_nonnote_insn (this_insn);
10262 if (this_insn && this_insn == label)
10266 arm_ccfsm_state = 2;
10267 this_insn = next_nonnote_insn (this_insn);
10270 arm_ccfsm_state = 1;
10278 /* If using 32-bit addresses the cc is not preserved over
10280 if (TARGET_APCS_32)
10282 /* Succeed if the following insn is the target label,
10283 or if the following two insns are a barrier and
10284 the target label. */
10285 this_insn = next_nonnote_insn (this_insn);
10286 if (this_insn && GET_CODE (this_insn) == BARRIER)
10287 this_insn = next_nonnote_insn (this_insn);
10289 if (this_insn && this_insn == label
10290 && insns_skipped < max_insns_skipped)
10294 arm_ccfsm_state = 2;
10295 this_insn = next_nonnote_insn (this_insn);
10298 arm_ccfsm_state = 1;
10307 /* If this is an unconditional branch to the same label, succeed.
10308 If it is to another label, do nothing. If it is conditional,
10310 /* XXX Probably, the tests for SET and the PC are
10313 scanbody = PATTERN (this_insn);
10314 if (GET_CODE (scanbody) == SET
10315 && GET_CODE (SET_DEST (scanbody)) == PC)
10317 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
10318 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
10320 arm_ccfsm_state = 2;
10323 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
10326 /* Fail if a conditional return is undesirable (eg on a
10327 StrongARM), but still allow this if optimizing for size. */
10328 else if (GET_CODE (scanbody) == RETURN
10329 && !use_return_insn (TRUE, NULL)
10332 else if (GET_CODE (scanbody) == RETURN
10335 arm_ccfsm_state = 2;
10338 else if (GET_CODE (scanbody) == PARALLEL)
10340 switch (get_attr_conds (this_insn))
10350 fail = TRUE; /* Unrecognized jump (eg epilogue). */
10355 /* Instructions using or affecting the condition codes make it
10357 scanbody = PATTERN (this_insn);
10358 if (!(GET_CODE (scanbody) == SET
10359 || GET_CODE (scanbody) == PARALLEL)
10360 || get_attr_conds (this_insn) != CONDS_NOCOND)
10363 /* A conditional cirrus instruction must be followed by
10364 a non Cirrus instruction. However, since we
10365 conditionalize instructions in this function and by
10366 the time we get here we can't add instructions
10367 (nops), because shorten_branches() has already been
10368 called, we will disable conditionalizing Cirrus
10369 instructions to be safe. */
10370 if (GET_CODE (scanbody) != USE
10371 && GET_CODE (scanbody) != CLOBBER
10372 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
10382 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
10383 arm_target_label = CODE_LABEL_NUMBER (label);
10384 else if (seeking_return || arm_ccfsm_state == 2)
10386 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
10388 this_insn = next_nonnote_insn (this_insn);
10389 if (this_insn && (GET_CODE (this_insn) == BARRIER
10390 || GET_CODE (this_insn) == CODE_LABEL))
10395 /* Oh, dear! we ran off the end.. give up. */
10396 recog (PATTERN (insn), insn, NULL);
10397 arm_ccfsm_state = 0;
10398 arm_target_insn = NULL;
10401 arm_target_insn = this_insn;
10410 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
10412 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
10413 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10414 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
10415 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10419 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
10422 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
10426 if (reverse || then_not_else)
10427 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10430 /* Restore recog_data (getting the attributes of other insns can
10431 destroy this array, but final.c assumes that it remains intact
10432 across this call; since the insn has been recognized already we
10433 call recog direct). */
10434 recog (PATTERN (insn), insn, NULL);
10438 /* Returns true if REGNO is a valid register
10439 for holding a quantity of tyoe MODE. */
10441 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10443 if (GET_MODE_CLASS (mode) == MODE_CC)
10444 return regno == CC_REGNUM;
10447 /* For the Thumb we only allow values bigger than SImode in
10448 registers 0 - 6, so that there is always a second low
10449 register available to hold the upper part of the value.
10450 We probably we ought to ensure that the register is the
10451 start of an even numbered register pair. */
10452 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
10454 if (IS_CIRRUS_REGNUM (regno))
10455 /* We have outlawed SI values in Cirrus registers because they
10456 reside in the lower 32 bits, but SF values reside in the
10457 upper 32 bits. This causes gcc all sorts of grief. We can't
10458 even split the registers into pairs because Cirrus SI values
10459 get sign extended to 64bits-- aldyh. */
10460 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
10462 if (IS_IWMMXT_GR_REGNUM (regno))
10463 return mode == SImode;
10465 if (IS_IWMMXT_REGNUM (regno))
10466 return VALID_IWMMXT_REG_MODE (mode);
10468 if (regno <= LAST_ARM_REGNUM)
10469 /* We allow any value to be stored in the general registers. */
10472 if ( regno == FRAME_POINTER_REGNUM
10473 || regno == ARG_POINTER_REGNUM)
10474 /* We only allow integers in the fake hard registers. */
10475 return GET_MODE_CLASS (mode) == MODE_INT;
10477 /* The only registers left are the FPA registers
10478 which we only allow to hold FP values. */
10479 return GET_MODE_CLASS (mode) == MODE_FLOAT
10480 && regno >= FIRST_ARM_FP_REGNUM
10481 && regno <= LAST_ARM_FP_REGNUM;
10485 arm_regno_class (int regno)
10489 if (regno == STACK_POINTER_REGNUM)
10491 if (regno == CC_REGNUM)
10498 if ( regno <= LAST_ARM_REGNUM
10499 || regno == FRAME_POINTER_REGNUM
10500 || regno == ARG_POINTER_REGNUM)
10501 return GENERAL_REGS;
10503 if (regno == CC_REGNUM)
10506 if (IS_CIRRUS_REGNUM (regno))
10507 return CIRRUS_REGS;
10509 if (IS_IWMMXT_REGNUM (regno))
10510 return IWMMXT_REGS;
10512 if (IS_IWMMXT_GR_REGNUM (regno))
10513 return IWMMXT_GR_REGS;
10518 /* Handle a special case when computing the offset
10519 of an argument from the frame pointer. */
10521 arm_debugger_arg_offset (int value, rtx addr)
10525 /* We are only interested if dbxout_parms() failed to compute the offset. */
10529 /* We can only cope with the case where the address is held in a register. */
10530 if (GET_CODE (addr) != REG)
10533 /* If we are using the frame pointer to point at the argument, then
10534 an offset of 0 is correct. */
10535 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
10538 /* If we are using the stack pointer to point at the
10539 argument, then an offset of 0 is correct. */
10540 if ((TARGET_THUMB || !frame_pointer_needed)
10541 && REGNO (addr) == SP_REGNUM)
10544 /* Oh dear. The argument is pointed to by a register rather
10545 than being held in a register, or being stored at a known
10546 offset from the frame pointer. Since GDB only understands
10547 those two kinds of argument we must translate the address
10548 held in the register into an offset from the frame pointer.
10549 We do this by searching through the insns for the function
10550 looking to see where this register gets its value. If the
10551 register is initialized from the frame pointer plus an offset
10552 then we are in luck and we can continue, otherwise we give up.
10554 This code is exercised by producing debugging information
10555 for a function with arguments like this:
10557 double func (double a, double b, int c, double d) {return d;}
10559 Without this code the stab for parameter 'd' will be set to
10560 an offset of 0 from the frame pointer, rather than 8. */
10562 /* The if() statement says:
10564 If the insn is a normal instruction
10565 and if the insn is setting the value in a register
10566 and if the register being set is the register holding the address of the argument
10567 and if the address is computing by an addition
10568 that involves adding to a register
10569 which is the frame pointer
10574 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10576 if ( GET_CODE (insn) == INSN
10577 && GET_CODE (PATTERN (insn)) == SET
10578 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
10579 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
10580 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
10581 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
10582 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
10585 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
10594 warning ("unable to compute real location of stacked parameter");
10595 value = 8; /* XXX magic hack */
10601 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
10604 if ((MASK) & insn_flags) \
10605 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
10609 struct builtin_description
10611 const unsigned int mask;
10612 const enum insn_code icode;
10613 const char * const name;
10614 const enum arm_builtins code;
10615 const enum rtx_code comparison;
10616 const unsigned int flag;
10619 static const struct builtin_description bdesc_2arg[] =
10621 #define IWMMXT_BUILTIN(code, string, builtin) \
10622 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
10623 ARM_BUILTIN_##builtin, 0, 0 },
10625 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
10626 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
10627 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
10628 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
10629 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
10630 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
10631 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
10632 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
10633 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
10634 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
10635 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
10636 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
10637 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
10638 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
10639 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
10640 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
10641 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
10642 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
10643 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
10644 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsh", WMULSH)
10645 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmuluh", WMULUH)
10646 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
10647 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
10648 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
10649 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
10650 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
10651 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
10652 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
10653 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
10654 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
10655 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
10656 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
10657 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
10658 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
10659 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
10660 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
10661 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
10662 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
10663 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
10664 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
10665 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
10666 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
10667 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
10668 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
10669 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
10670 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
10671 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
10672 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
10673 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
10674 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
10675 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
10676 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
10677 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
10678 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
10679 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
10680 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
10681 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
10682 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
10684 #define IWMMXT_BUILTIN2(code, builtin) \
10685 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
10687 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
10688 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
10689 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
10690 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
10691 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
10692 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
10693 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
10694 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
10695 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
10696 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
10697 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
10698 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
10699 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
10700 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
10701 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
10702 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
10703 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
10704 IWMMXT_BUILTIN2 (lshrdi3, WSRLDI)
10705 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
10706 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
10707 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
10708 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
10709 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
10710 IWMMXT_BUILTIN2 (ashrdi3, WSRADI)
10711 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
10712 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
10713 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
10714 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
10715 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
10716 IWMMXT_BUILTIN2 (rordi3, WRORDI)
10717 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
10718 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
10721 static const struct builtin_description bdesc_1arg[] =
10723 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
10724 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
10725 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
10726 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
10727 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
10728 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
10729 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
10730 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
10731 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
10732 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
10733 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
10734 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
10735 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
10736 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
10737 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
10738 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
10739 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
10740 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
10743 /* Set up all the iWMMXt builtins. This is
10744 not called if TARGET_IWMMXT is zero. */
10747 arm_init_iwmmxt_builtins (void)
10749 const struct builtin_description * d;
10751 tree endlink = void_list_node;
10754 = build_function_type (integer_type_node,
10755 tree_cons (NULL_TREE, integer_type_node, endlink));
10756 tree v8qi_ftype_v8qi_v8qi_int
10757 = build_function_type (V8QI_type_node,
10758 tree_cons (NULL_TREE, V8QI_type_node,
10759 tree_cons (NULL_TREE, V8QI_type_node,
10760 tree_cons (NULL_TREE,
10763 tree v4hi_ftype_v4hi_int
10764 = build_function_type (V4HI_type_node,
10765 tree_cons (NULL_TREE, V4HI_type_node,
10766 tree_cons (NULL_TREE, integer_type_node,
10768 tree v2si_ftype_v2si_int
10769 = build_function_type (V2SI_type_node,
10770 tree_cons (NULL_TREE, V2SI_type_node,
10771 tree_cons (NULL_TREE, integer_type_node,
10773 tree v2si_ftype_di_di
10774 = build_function_type (V2SI_type_node,
10775 tree_cons (NULL_TREE, long_long_integer_type_node,
10776 tree_cons (NULL_TREE, long_long_integer_type_node,
10778 tree di_ftype_di_int
10779 = build_function_type (long_long_integer_type_node,
10780 tree_cons (NULL_TREE, long_long_integer_type_node,
10781 tree_cons (NULL_TREE, integer_type_node,
10783 tree di_ftype_di_int_int
10784 = build_function_type (long_long_integer_type_node,
10785 tree_cons (NULL_TREE, long_long_integer_type_node,
10786 tree_cons (NULL_TREE, integer_type_node,
10787 tree_cons (NULL_TREE,
10790 tree int_ftype_v8qi
10791 = build_function_type (integer_type_node,
10792 tree_cons (NULL_TREE, V8QI_type_node,
10794 tree int_ftype_v4hi
10795 = build_function_type (integer_type_node,
10796 tree_cons (NULL_TREE, V4HI_type_node,
10798 tree int_ftype_v2si
10799 = build_function_type (integer_type_node,
10800 tree_cons (NULL_TREE, V2SI_type_node,
10802 tree int_ftype_v8qi_int
10803 = build_function_type (integer_type_node,
10804 tree_cons (NULL_TREE, V8QI_type_node,
10805 tree_cons (NULL_TREE, integer_type_node,
10807 tree int_ftype_v4hi_int
10808 = build_function_type (integer_type_node,
10809 tree_cons (NULL_TREE, V4HI_type_node,
10810 tree_cons (NULL_TREE, integer_type_node,
10812 tree int_ftype_v2si_int
10813 = build_function_type (integer_type_node,
10814 tree_cons (NULL_TREE, V2SI_type_node,
10815 tree_cons (NULL_TREE, integer_type_node,
10817 tree v8qi_ftype_v8qi_int_int
10818 = build_function_type (V8QI_type_node,
10819 tree_cons (NULL_TREE, V8QI_type_node,
10820 tree_cons (NULL_TREE, integer_type_node,
10821 tree_cons (NULL_TREE,
10824 tree v4hi_ftype_v4hi_int_int
10825 = build_function_type (V4HI_type_node,
10826 tree_cons (NULL_TREE, V4HI_type_node,
10827 tree_cons (NULL_TREE, integer_type_node,
10828 tree_cons (NULL_TREE,
10831 tree v2si_ftype_v2si_int_int
10832 = build_function_type (V2SI_type_node,
10833 tree_cons (NULL_TREE, V2SI_type_node,
10834 tree_cons (NULL_TREE, integer_type_node,
10835 tree_cons (NULL_TREE,
10838 /* Miscellaneous. */
10839 tree v8qi_ftype_v4hi_v4hi
10840 = build_function_type (V8QI_type_node,
10841 tree_cons (NULL_TREE, V4HI_type_node,
10842 tree_cons (NULL_TREE, V4HI_type_node,
10844 tree v4hi_ftype_v2si_v2si
10845 = build_function_type (V4HI_type_node,
10846 tree_cons (NULL_TREE, V2SI_type_node,
10847 tree_cons (NULL_TREE, V2SI_type_node,
10849 tree v2si_ftype_v4hi_v4hi
10850 = build_function_type (V2SI_type_node,
10851 tree_cons (NULL_TREE, V4HI_type_node,
10852 tree_cons (NULL_TREE, V4HI_type_node,
10854 tree v2si_ftype_v8qi_v8qi
10855 = build_function_type (V2SI_type_node,
10856 tree_cons (NULL_TREE, V8QI_type_node,
10857 tree_cons (NULL_TREE, V8QI_type_node,
10859 tree v4hi_ftype_v4hi_di
10860 = build_function_type (V4HI_type_node,
10861 tree_cons (NULL_TREE, V4HI_type_node,
10862 tree_cons (NULL_TREE,
10863 long_long_integer_type_node,
10865 tree v2si_ftype_v2si_di
10866 = build_function_type (V2SI_type_node,
10867 tree_cons (NULL_TREE, V2SI_type_node,
10868 tree_cons (NULL_TREE,
10869 long_long_integer_type_node,
10871 tree void_ftype_int_int
10872 = build_function_type (void_type_node,
10873 tree_cons (NULL_TREE, integer_type_node,
10874 tree_cons (NULL_TREE, integer_type_node,
10877 = build_function_type (long_long_unsigned_type_node, endlink);
10879 = build_function_type (long_long_integer_type_node,
10880 tree_cons (NULL_TREE, V8QI_type_node,
10883 = build_function_type (long_long_integer_type_node,
10884 tree_cons (NULL_TREE, V4HI_type_node,
10887 = build_function_type (long_long_integer_type_node,
10888 tree_cons (NULL_TREE, V2SI_type_node,
10890 tree v2si_ftype_v4hi
10891 = build_function_type (V2SI_type_node,
10892 tree_cons (NULL_TREE, V4HI_type_node,
10894 tree v4hi_ftype_v8qi
10895 = build_function_type (V4HI_type_node,
10896 tree_cons (NULL_TREE, V8QI_type_node,
10899 tree di_ftype_di_v4hi_v4hi
10900 = build_function_type (long_long_unsigned_type_node,
10901 tree_cons (NULL_TREE,
10902 long_long_unsigned_type_node,
10903 tree_cons (NULL_TREE, V4HI_type_node,
10904 tree_cons (NULL_TREE,
10908 tree di_ftype_v4hi_v4hi
10909 = build_function_type (long_long_unsigned_type_node,
10910 tree_cons (NULL_TREE, V4HI_type_node,
10911 tree_cons (NULL_TREE, V4HI_type_node,
10914 /* Normal vector binops. */
10915 tree v8qi_ftype_v8qi_v8qi
10916 = build_function_type (V8QI_type_node,
10917 tree_cons (NULL_TREE, V8QI_type_node,
10918 tree_cons (NULL_TREE, V8QI_type_node,
10920 tree v4hi_ftype_v4hi_v4hi
10921 = build_function_type (V4HI_type_node,
10922 tree_cons (NULL_TREE, V4HI_type_node,
10923 tree_cons (NULL_TREE, V4HI_type_node,
10925 tree v2si_ftype_v2si_v2si
10926 = build_function_type (V2SI_type_node,
10927 tree_cons (NULL_TREE, V2SI_type_node,
10928 tree_cons (NULL_TREE, V2SI_type_node,
10930 tree di_ftype_di_di
10931 = build_function_type (long_long_unsigned_type_node,
10932 tree_cons (NULL_TREE, long_long_unsigned_type_node,
10933 tree_cons (NULL_TREE,
10934 long_long_unsigned_type_node,
10937 /* Add all builtins that are more or less simple operations on two
10939 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10941 /* Use one of the operands; the target can have a different mode for
10942 mask-generating compares. */
10943 enum machine_mode mode;
10949 mode = insn_data[d->icode].operand[1].mode;
10954 type = v8qi_ftype_v8qi_v8qi;
10957 type = v4hi_ftype_v4hi_v4hi;
10960 type = v2si_ftype_v2si_v2si;
10963 type = di_ftype_di_di;
10970 def_mbuiltin (d->mask, d->name, type, d->code);
10973 /* Add the remaining MMX insns with somewhat more complicated types. */
10974 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
10975 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
10976 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
10978 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
10979 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
10980 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
10981 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
10982 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
10983 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
10985 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
10986 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
10987 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
10988 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
10989 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
10990 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
10992 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
10993 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
10994 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
10995 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
10996 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
10997 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
10999 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
11000 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
11001 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
11002 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
11003 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
11004 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
11006 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
11008 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
11009 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
11010 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
11011 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
11013 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
11014 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
11015 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
11016 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
11017 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
11018 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
11019 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
11020 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
11021 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
11023 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
11024 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
11025 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
11027 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
11028 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
11029 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
11031 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
11032 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
11033 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
11034 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
11035 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
11036 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
11038 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
11039 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
11040 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
11041 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
11042 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
11043 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
11044 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
11045 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
11046 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
11047 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
11048 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
11049 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
11051 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
11052 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
11053 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
11054 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
11056 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
11057 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
11058 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
11059 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
11060 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
11061 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
11062 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
11066 arm_init_builtins (void)
11068 if (TARGET_REALLY_IWMMXT)
11069 arm_init_iwmmxt_builtins ();
11072 /* Errors in the source file can cause expand_expr to return const0_rtx
11073 where we expect a vector. To avoid crashing, use one of the vector
11074 clear instructions. */
11077 safe_vector_operand (rtx x, enum machine_mode mode)
11079 if (x != const0_rtx)
11081 x = gen_reg_rtx (mode);
11083 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
11084 : gen_rtx_SUBREG (DImode, x, 0)));
11088 /* Subroutine of arm_expand_builtin to take care of binop insns. */
11091 arm_expand_binop_builtin (enum insn_code icode,
11092 tree arglist, rtx target)
11095 tree arg0 = TREE_VALUE (arglist);
11096 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11097 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11098 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11099 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11100 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11101 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11103 if (VECTOR_MODE_P (mode0))
11104 op0 = safe_vector_operand (op0, mode0);
11105 if (VECTOR_MODE_P (mode1))
11106 op1 = safe_vector_operand (op1, mode1);
11109 || GET_MODE (target) != tmode
11110 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11111 target = gen_reg_rtx (tmode);
11113 /* In case the insn wants input operands in modes different from
11114 the result, abort. */
11115 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
11118 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11119 op0 = copy_to_mode_reg (mode0, op0);
11120 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11121 op1 = copy_to_mode_reg (mode1, op1);
11123 pat = GEN_FCN (icode) (target, op0, op1);
11130 /* Subroutine of arm_expand_builtin to take care of unop insns. */
11133 arm_expand_unop_builtin (enum insn_code icode,
11134 tree arglist, rtx target, int do_load)
11137 tree arg0 = TREE_VALUE (arglist);
11138 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11139 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11140 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11143 || GET_MODE (target) != tmode
11144 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11145 target = gen_reg_rtx (tmode);
11147 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
11150 if (VECTOR_MODE_P (mode0))
11151 op0 = safe_vector_operand (op0, mode0);
11153 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11154 op0 = copy_to_mode_reg (mode0, op0);
11157 pat = GEN_FCN (icode) (target, op0);
11164 /* Expand an expression EXP that calls a built-in function,
11165 with result going to TARGET if that's convenient
11166 (and in mode MODE if that's convenient).
11167 SUBTARGET may be used as the target for computing one of EXP's operands.
11168 IGNORE is nonzero if the value is to be ignored. */
11171 arm_expand_builtin (tree exp,
11173 rtx subtarget ATTRIBUTE_UNUSED,
11174 enum machine_mode mode ATTRIBUTE_UNUSED,
11175 int ignore ATTRIBUTE_UNUSED)
11177 const struct builtin_description * d;
11178 enum insn_code icode;
11179 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
11180 tree arglist = TREE_OPERAND (exp, 1);
11188 int fcode = DECL_FUNCTION_CODE (fndecl);
11190 enum machine_mode tmode;
11191 enum machine_mode mode0;
11192 enum machine_mode mode1;
11193 enum machine_mode mode2;
11197 case ARM_BUILTIN_TEXTRMSB:
11198 case ARM_BUILTIN_TEXTRMUB:
11199 case ARM_BUILTIN_TEXTRMSH:
11200 case ARM_BUILTIN_TEXTRMUH:
11201 case ARM_BUILTIN_TEXTRMSW:
11202 case ARM_BUILTIN_TEXTRMUW:
11203 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
11204 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
11205 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
11206 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
11207 : CODE_FOR_iwmmxt_textrmw);
11209 arg0 = TREE_VALUE (arglist);
11210 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11211 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11212 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11213 tmode = insn_data[icode].operand[0].mode;
11214 mode0 = insn_data[icode].operand[1].mode;
11215 mode1 = insn_data[icode].operand[2].mode;
11217 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11218 op0 = copy_to_mode_reg (mode0, op0);
11219 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11221 /* @@@ better error message */
11222 error ("selector must be an immediate");
11223 return gen_reg_rtx (tmode);
11226 || GET_MODE (target) != tmode
11227 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11228 target = gen_reg_rtx (tmode);
11229 pat = GEN_FCN (icode) (target, op0, op1);
11235 case ARM_BUILTIN_TINSRB:
11236 case ARM_BUILTIN_TINSRH:
11237 case ARM_BUILTIN_TINSRW:
11238 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
11239 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
11240 : CODE_FOR_iwmmxt_tinsrw);
11241 arg0 = TREE_VALUE (arglist);
11242 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11243 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11244 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11245 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11246 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11247 tmode = insn_data[icode].operand[0].mode;
11248 mode0 = insn_data[icode].operand[1].mode;
11249 mode1 = insn_data[icode].operand[2].mode;
11250 mode2 = insn_data[icode].operand[3].mode;
11252 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11253 op0 = copy_to_mode_reg (mode0, op0);
11254 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11255 op1 = copy_to_mode_reg (mode1, op1);
11256 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11258 /* @@@ better error message */
11259 error ("selector must be an immediate");
11263 || GET_MODE (target) != tmode
11264 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11265 target = gen_reg_rtx (tmode);
11266 pat = GEN_FCN (icode) (target, op0, op1, op2);
11272 case ARM_BUILTIN_SETWCX:
11273 arg0 = TREE_VALUE (arglist);
11274 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11275 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11276 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11277 emit_insn (gen_iwmmxt_tmcr (op0, op1));
11280 case ARM_BUILTIN_GETWCX:
11281 arg0 = TREE_VALUE (arglist);
11282 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11283 target = gen_reg_rtx (SImode);
11284 emit_insn (gen_iwmmxt_tmrc (target, op0));
11287 case ARM_BUILTIN_WSHUFH:
11288 icode = CODE_FOR_iwmmxt_wshufh;
11289 arg0 = TREE_VALUE (arglist);
11290 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11291 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11292 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11293 tmode = insn_data[icode].operand[0].mode;
11294 mode1 = insn_data[icode].operand[1].mode;
11295 mode2 = insn_data[icode].operand[2].mode;
11297 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
11298 op0 = copy_to_mode_reg (mode1, op0);
11299 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
11301 /* @@@ better error message */
11302 error ("mask must be an immediate");
11306 || GET_MODE (target) != tmode
11307 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11308 target = gen_reg_rtx (tmode);
11309 pat = GEN_FCN (icode) (target, op0, op1);
11315 case ARM_BUILTIN_WSADB:
11316 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
11317 case ARM_BUILTIN_WSADH:
11318 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
11319 case ARM_BUILTIN_WSADBZ:
11320 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
11321 case ARM_BUILTIN_WSADHZ:
11322 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
11324 /* Several three-argument builtins. */
11325 case ARM_BUILTIN_WMACS:
11326 case ARM_BUILTIN_WMACU:
11327 case ARM_BUILTIN_WALIGN:
11328 case ARM_BUILTIN_TMIA:
11329 case ARM_BUILTIN_TMIAPH:
11330 case ARM_BUILTIN_TMIATT:
11331 case ARM_BUILTIN_TMIATB:
11332 case ARM_BUILTIN_TMIABT:
11333 case ARM_BUILTIN_TMIABB:
11334 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
11335 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
11336 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
11337 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
11338 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
11339 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
11340 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
11341 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
11342 : CODE_FOR_iwmmxt_walign);
11343 arg0 = TREE_VALUE (arglist);
11344 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11345 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11346 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11347 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11348 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11349 tmode = insn_data[icode].operand[0].mode;
11350 mode0 = insn_data[icode].operand[1].mode;
11351 mode1 = insn_data[icode].operand[2].mode;
11352 mode2 = insn_data[icode].operand[3].mode;
11354 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11355 op0 = copy_to_mode_reg (mode0, op0);
11356 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11357 op1 = copy_to_mode_reg (mode1, op1);
11358 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11359 op2 = copy_to_mode_reg (mode2, op2);
11361 || GET_MODE (target) != tmode
11362 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11363 target = gen_reg_rtx (tmode);
11364 pat = GEN_FCN (icode) (target, op0, op1, op2);
11370 case ARM_BUILTIN_WZERO:
11371 target = gen_reg_rtx (DImode);
11372 emit_insn (gen_iwmmxt_clrdi (target));
11379 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11380 if (d->code == (const enum arm_builtins) fcode)
11381 return arm_expand_binop_builtin (d->icode, arglist, target);
11383 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11384 if (d->code == (const enum arm_builtins) fcode)
11385 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
11387 /* @@@ Should really do something sensible here. */
11391 /* Recursively search through all of the blocks in a function
11392 checking to see if any of the variables created in that
11393 function match the RTX called 'orig'. If they do then
11394 replace them with the RTX called 'new'. */
11396 replace_symbols_in_block (tree block, rtx orig, rtx new)
11398 for (; block; block = BLOCK_CHAIN (block))
11402 if (!TREE_USED (block))
11405 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
11407 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
11408 || DECL_IGNORED_P (sym)
11409 || TREE_CODE (sym) != VAR_DECL
11410 || DECL_EXTERNAL (sym)
11411 || !rtx_equal_p (DECL_RTL (sym), orig)
11415 SET_DECL_RTL (sym, new);
11418 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
11422 /* Return the number (counting from 0) of
11423 the least significant set bit in MASK. */
11426 number_of_first_bit_set (int mask)
11431 (mask & (1 << bit)) == 0;
11438 /* Generate code to return from a thumb function.
11439 If 'reg_containing_return_addr' is -1, then the return address is
11440 actually on the stack, at the stack pointer. */
11442 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
11444 unsigned regs_available_for_popping;
11445 unsigned regs_to_pop;
11447 unsigned available;
11451 int restore_a4 = FALSE;
11453 /* Compute the registers we need to pop. */
11457 /* There is an assumption here, that if eh_ofs is not NULL, the
11458 normal return address will have been pushed. */
11459 if (reg_containing_return_addr == -1 || eh_ofs)
11461 /* When we are generating a return for __builtin_eh_return,
11462 reg_containing_return_addr must specify the return regno. */
11463 if (eh_ofs && reg_containing_return_addr == -1)
11466 regs_to_pop |= 1 << LR_REGNUM;
11470 if (TARGET_BACKTRACE)
11472 /* Restore the (ARM) frame pointer and stack pointer. */
11473 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
11477 /* If there is nothing to pop then just emit the BX instruction and
11479 if (pops_needed == 0)
11482 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11484 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11487 /* Otherwise if we are not supporting interworking and we have not created
11488 a backtrace structure and the function was not entered in ARM mode then
11489 just pop the return address straight into the PC. */
11490 else if (!TARGET_INTERWORK
11491 && !TARGET_BACKTRACE
11492 && !is_called_in_ARM_mode (current_function_decl))
11496 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
11497 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11498 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11501 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
11506 /* Find out how many of the (return) argument registers we can corrupt. */
11507 regs_available_for_popping = 0;
11509 /* If returning via __builtin_eh_return, the bottom three registers
11510 all contain information needed for the return. */
11516 /* If we can deduce the registers used from the function's
11517 return value. This is more reliable that examining
11518 regs_ever_live[] because that will be set if the register is
11519 ever used in the function, not just if the register is used
11520 to hold a return value. */
11522 if (current_function_return_rtx != 0)
11523 mode = GET_MODE (current_function_return_rtx);
11526 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11528 size = GET_MODE_SIZE (mode);
11532 /* In a void function we can use any argument register.
11533 In a function that returns a structure on the stack
11534 we can use the second and third argument registers. */
11535 if (mode == VOIDmode)
11536 regs_available_for_popping =
11537 (1 << ARG_REGISTER (1))
11538 | (1 << ARG_REGISTER (2))
11539 | (1 << ARG_REGISTER (3));
11541 regs_available_for_popping =
11542 (1 << ARG_REGISTER (2))
11543 | (1 << ARG_REGISTER (3));
11545 else if (size <= 4)
11546 regs_available_for_popping =
11547 (1 << ARG_REGISTER (2))
11548 | (1 << ARG_REGISTER (3));
11549 else if (size <= 8)
11550 regs_available_for_popping =
11551 (1 << ARG_REGISTER (3));
11554 /* Match registers to be popped with registers into which we pop them. */
11555 for (available = regs_available_for_popping,
11556 required = regs_to_pop;
11557 required != 0 && available != 0;
11558 available &= ~(available & - available),
11559 required &= ~(required & - required))
11562 /* If we have any popping registers left over, remove them. */
11564 regs_available_for_popping &= ~available;
11566 /* Otherwise if we need another popping register we can use
11567 the fourth argument register. */
11568 else if (pops_needed)
11570 /* If we have not found any free argument registers and
11571 reg a4 contains the return address, we must move it. */
11572 if (regs_available_for_popping == 0
11573 && reg_containing_return_addr == LAST_ARG_REGNUM)
11575 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
11576 reg_containing_return_addr = LR_REGNUM;
11578 else if (size > 12)
11580 /* Register a4 is being used to hold part of the return value,
11581 but we have dire need of a free, low register. */
11584 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
11587 if (reg_containing_return_addr != LAST_ARG_REGNUM)
11589 /* The fourth argument register is available. */
11590 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
11596 /* Pop as many registers as we can. */
11597 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
11598 regs_available_for_popping);
11600 /* Process the registers we popped. */
11601 if (reg_containing_return_addr == -1)
11603 /* The return address was popped into the lowest numbered register. */
11604 regs_to_pop &= ~(1 << LR_REGNUM);
11606 reg_containing_return_addr =
11607 number_of_first_bit_set (regs_available_for_popping);
11609 /* Remove this register for the mask of available registers, so that
11610 the return address will not be corrupted by further pops. */
11611 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
11614 /* If we popped other registers then handle them here. */
11615 if (regs_available_for_popping)
11619 /* Work out which register currently contains the frame pointer. */
11620 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
11622 /* Move it into the correct place. */
11623 asm_fprintf (f, "\tmov\t%r, %r\n",
11624 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
11626 /* (Temporarily) remove it from the mask of popped registers. */
11627 regs_available_for_popping &= ~(1 << frame_pointer);
11628 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
11630 if (regs_available_for_popping)
11634 /* We popped the stack pointer as well,
11635 find the register that contains it. */
11636 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
11638 /* Move it into the stack register. */
11639 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
11641 /* At this point we have popped all necessary registers, so
11642 do not worry about restoring regs_available_for_popping
11643 to its correct value:
11645 assert (pops_needed == 0)
11646 assert (regs_available_for_popping == (1 << frame_pointer))
11647 assert (regs_to_pop == (1 << STACK_POINTER)) */
11651 /* Since we have just move the popped value into the frame
11652 pointer, the popping register is available for reuse, and
11653 we know that we still have the stack pointer left to pop. */
11654 regs_available_for_popping |= (1 << frame_pointer);
11658 /* If we still have registers left on the stack, but we no longer have
11659 any registers into which we can pop them, then we must move the return
11660 address into the link register and make available the register that
11662 if (regs_available_for_popping == 0 && pops_needed > 0)
11664 regs_available_for_popping |= 1 << reg_containing_return_addr;
11666 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
11667 reg_containing_return_addr);
11669 reg_containing_return_addr = LR_REGNUM;
11672 /* If we have registers left on the stack then pop some more.
11673 We know that at most we will want to pop FP and SP. */
11674 if (pops_needed > 0)
11679 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
11680 regs_available_for_popping);
11682 /* We have popped either FP or SP.
11683 Move whichever one it is into the correct register. */
11684 popped_into = number_of_first_bit_set (regs_available_for_popping);
11685 move_to = number_of_first_bit_set (regs_to_pop);
11687 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
11689 regs_to_pop &= ~(1 << move_to);
11694 /* If we still have not popped everything then we must have only
11695 had one register available to us and we are now popping the SP. */
11696 if (pops_needed > 0)
11700 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
11701 regs_available_for_popping);
11703 popped_into = number_of_first_bit_set (regs_available_for_popping);
11705 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
11707 assert (regs_to_pop == (1 << STACK_POINTER))
11708 assert (pops_needed == 1)
11712 /* If necessary restore the a4 register. */
11715 if (reg_containing_return_addr != LR_REGNUM)
11717 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
11718 reg_containing_return_addr = LR_REGNUM;
11721 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
11725 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11727 /* Return to caller. */
11728 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11731 /* Emit code to push or pop registers to or from the stack. F is the
11732 assembly file. MASK is the registers to push or pop. PUSH is
11733 non-zero if we should push, and zero if we should pop. For debugging
11734 output, if pushing, adjust CFA_OFFSET by the amount of space added
11735 to the stack. REAL_REGS should have the same number of bits set as
11736 MASK, and will be used instead (in the same order) to describe which
11737 registers were saved - this is used to mark the save slots when we
11738 push high registers after moving them to low registers. */
11740 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
11743 int lo_mask = mask & 0xFF;
11744 int pushed_words = 0;
11746 if (lo_mask == 0 && !push && (mask & (1 << 15)))
11748 /* Special case. Do not generate a POP PC statement here, do it in
11750 thumb_exit (f, -1, NULL_RTX);
11754 fprintf (f, "\t%s\t{", push ? "push" : "pop");
11756 /* Look at the low registers first. */
11757 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
11761 asm_fprintf (f, "%r", regno);
11763 if ((lo_mask & ~1) != 0)
11770 if (push && (mask & (1 << LR_REGNUM)))
11772 /* Catch pushing the LR. */
11776 asm_fprintf (f, "%r", LR_REGNUM);
11780 else if (!push && (mask & (1 << PC_REGNUM)))
11782 /* Catch popping the PC. */
11783 if (TARGET_INTERWORK || TARGET_BACKTRACE)
11785 /* The PC is never poped directly, instead
11786 it is popped into r3 and then BX is used. */
11787 fprintf (f, "}\n");
11789 thumb_exit (f, -1, NULL_RTX);
11798 asm_fprintf (f, "%r", PC_REGNUM);
11802 fprintf (f, "}\n");
11804 if (push && pushed_words && dwarf2out_do_frame ())
11806 char *l = dwarf2out_cfi_label ();
11807 int pushed_mask = real_regs;
11809 *cfa_offset += pushed_words * 4;
11810 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
11813 pushed_mask = real_regs;
11814 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
11816 if (pushed_mask & 1)
11817 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
11823 thumb_final_prescan_insn (rtx insn)
11825 if (flag_print_asm_name)
11826 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
11827 INSN_ADDRESSES (INSN_UID (insn)));
11831 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
11833 unsigned HOST_WIDE_INT mask = 0xff;
11836 if (val == 0) /* XXX */
11839 for (i = 0; i < 25; i++)
11840 if ((val & (mask << i)) == val)
11846 /* Returns nonzero if the current function contains,
11847 or might contain a far jump. */
11849 thumb_far_jump_used_p (int in_prologue)
11853 /* This test is only important for leaf functions. */
11854 /* assert (!leaf_function_p ()); */
11856 /* If we have already decided that far jumps may be used,
11857 do not bother checking again, and always return true even if
11858 it turns out that they are not being used. Once we have made
11859 the decision that far jumps are present (and that hence the link
11860 register will be pushed onto the stack) we cannot go back on it. */
11861 if (cfun->machine->far_jump_used)
11864 /* If this function is not being called from the prologue/epilogue
11865 generation code then it must be being called from the
11866 INITIAL_ELIMINATION_OFFSET macro. */
11869 /* In this case we know that we are being asked about the elimination
11870 of the arg pointer register. If that register is not being used,
11871 then there are no arguments on the stack, and we do not have to
11872 worry that a far jump might force the prologue to push the link
11873 register, changing the stack offsets. In this case we can just
11874 return false, since the presence of far jumps in the function will
11875 not affect stack offsets.
11877 If the arg pointer is live (or if it was live, but has now been
11878 eliminated and so set to dead) then we do have to test to see if
11879 the function might contain a far jump. This test can lead to some
11880 false negatives, since before reload is completed, then length of
11881 branch instructions is not known, so gcc defaults to returning their
11882 longest length, which in turn sets the far jump attribute to true.
11884 A false negative will not result in bad code being generated, but it
11885 will result in a needless push and pop of the link register. We
11886 hope that this does not occur too often. */
11887 if (regs_ever_live [ARG_POINTER_REGNUM])
11888 cfun->machine->arg_pointer_live = 1;
11889 else if (!cfun->machine->arg_pointer_live)
11893 /* Check to see if the function contains a branch
11894 insn with the far jump attribute set. */
11895 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11897 if (GET_CODE (insn) == JUMP_INSN
11898 /* Ignore tablejump patterns. */
11899 && GET_CODE (PATTERN (insn)) != ADDR_VEC
11900 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
11901 && get_attr_far_jump (insn) == FAR_JUMP_YES
11904 /* Record the fact that we have decided that
11905 the function does use far jumps. */
11906 cfun->machine->far_jump_used = 1;
11914 /* Return nonzero if FUNC must be entered in ARM mode. */
11916 is_called_in_ARM_mode (tree func)
11918 if (TREE_CODE (func) != FUNCTION_DECL)
11921 /* Ignore the problem about functions whoes address is taken. */
11922 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
11926 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
11932 /* The bits which aren't usefully expanded as rtl. */
11934 thumb_unexpanded_epilogue (void)
11937 int live_regs_mask = 0;
11938 int high_regs_pushed = 0;
11939 int leaf_function = leaf_function_p ();
11940 int had_to_push_lr;
11941 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
11943 if (return_used_this_function)
11946 if (IS_NAKED (arm_current_func_type ()))
11949 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11950 if (THUMB_REG_PUSHED_P (regno))
11951 live_regs_mask |= 1 << regno;
11953 for (regno = 8; regno < 13; regno++)
11954 if (THUMB_REG_PUSHED_P (regno))
11955 high_regs_pushed++;
11957 /* The prolog may have pushed some high registers to use as
11958 work registers. eg the testsuite file:
11959 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
11960 compiles to produce:
11961 push {r4, r5, r6, r7, lr}
11965 as part of the prolog. We have to undo that pushing here. */
11967 if (high_regs_pushed)
11969 int mask = live_regs_mask;
11975 /* If we can deduce the registers used from the function's return value.
11976 This is more reliable that examining regs_ever_live[] because that
11977 will be set if the register is ever used in the function, not just if
11978 the register is used to hold a return value. */
11980 if (current_function_return_rtx != 0)
11981 mode = GET_MODE (current_function_return_rtx);
11984 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11986 size = GET_MODE_SIZE (mode);
11988 /* Unless we are returning a type of size > 12 register r3 is
11994 /* Oh dear! We have no low registers into which we can pop
11997 ("no low registers available for popping high registers");
11999 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12000 if (THUMB_REG_PUSHED_P (next_hi_reg))
12003 while (high_regs_pushed)
12005 /* Find lo register(s) into which the high register(s) can
12007 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12009 if (mask & (1 << regno))
12010 high_regs_pushed--;
12011 if (high_regs_pushed == 0)
12015 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
12017 /* Pop the values into the low register(s). */
12018 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
12020 /* Move the value(s) into the high registers. */
12021 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12023 if (mask & (1 << regno))
12025 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
12028 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
12029 if (THUMB_REG_PUSHED_P (next_hi_reg))
12036 had_to_push_lr = (live_regs_mask || !leaf_function
12037 || thumb_far_jump_used_p (1));
12039 if (TARGET_BACKTRACE
12040 && ((live_regs_mask & 0xFF) == 0)
12041 && regs_ever_live [LAST_ARG_REGNUM] != 0)
12043 /* The stack backtrace structure creation code had to
12044 push R7 in order to get a work register, so we pop
12046 live_regs_mask |= (1 << LAST_LO_REGNUM);
12049 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
12052 && !is_called_in_ARM_mode (current_function_decl)
12054 live_regs_mask |= 1 << PC_REGNUM;
12056 /* Either no argument registers were pushed or a backtrace
12057 structure was created which includes an adjusted stack
12058 pointer, so just pop everything. */
12059 if (live_regs_mask)
12060 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12064 thumb_exit (asm_out_file, 2, eh_ofs);
12065 /* We have either just popped the return address into the
12066 PC or it is was kept in LR for the entire function or
12067 it is still on the stack because we do not want to
12068 return by doing a pop {pc}. */
12069 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
12070 thumb_exit (asm_out_file,
12072 && is_called_in_ARM_mode (current_function_decl)) ?
12073 -1 : LR_REGNUM, NULL_RTX);
12077 /* Pop everything but the return address. */
12078 live_regs_mask &= ~(1 << PC_REGNUM);
12080 if (live_regs_mask)
12081 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
12084 if (had_to_push_lr)
12085 /* Get the return address into a temporary register. */
12086 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
12087 1 << LAST_ARG_REGNUM);
12089 /* Remove the argument registers that were pushed onto the stack. */
12090 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
12091 SP_REGNUM, SP_REGNUM,
12092 current_function_pretend_args_size);
12095 thumb_exit (asm_out_file, 2, eh_ofs);
12097 thumb_exit (asm_out_file,
12098 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
12104 /* Functions to save and restore machine-specific function data. */
12105 static struct machine_function *
12106 arm_init_machine_status (void)
12108 struct machine_function *machine;
12109 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
12111 #if ARM_FT_UNKNOWN != 0
12112 machine->func_type = ARM_FT_UNKNOWN;
12117 /* Return an RTX indicating where the return address to the
12118 calling function can be found. */
12120 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
12125 if (TARGET_APCS_32)
12126 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
12129 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
12130 GEN_INT (RETURN_ADDR_MASK26));
12131 return get_func_hard_reg_initial_val (cfun, lr);
12135 /* Do anything needed before RTL is emitted for each function. */
12137 arm_init_expanders (void)
12139 /* Arrange to initialize and mark the machine per-function status. */
12140 init_machine_status = arm_init_machine_status;
12144 thumb_get_frame_size (void)
12148 int base_size = ROUND_UP_WORD (get_frame_size ());
12149 int count_regs = 0;
12150 int entry_size = 0;
12153 if (! TARGET_THUMB)
12156 if (! TARGET_ATPCS)
12159 /* We need to know if we are a leaf function. Unfortunately, it
12160 is possible to be called after start_sequence has been called,
12161 which causes get_insns to return the insns for the sequence,
12162 not the function, which will cause leaf_function_p to return
12163 the incorrect result.
12165 To work around this, we cache the computed frame size. This
12166 works because we will only be calling RTL expanders that need
12167 to know about leaf functions once reload has completed, and the
12168 frame size cannot be changed after that time, so we can safely
12169 use the cached value. */
12171 if (reload_completed)
12172 return cfun->machine->frame_size;
12174 leaf = leaf_function_p ();
12176 /* A leaf function does not need any stack alignment if it has nothing
12178 if (leaf && base_size == 0)
12180 cfun->machine->frame_size = 0;
12184 /* We know that SP will be word aligned on entry, and we must
12185 preserve that condition at any subroutine call. But those are
12186 the only constraints. */
12188 /* Space for variadic functions. */
12189 if (current_function_pretend_args_size)
12190 entry_size += current_function_pretend_args_size;
12192 /* Space for pushed lo registers. */
12193 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12194 if (THUMB_REG_PUSHED_P (regno))
12197 /* Space for backtrace structure. */
12198 if (TARGET_BACKTRACE)
12200 if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0)
12206 if (count_regs || !leaf || thumb_far_jump_used_p (1))
12207 count_regs++; /* LR */
12209 entry_size += count_regs * 4;
12212 /* Space for pushed hi regs. */
12213 for (regno = 8; regno < 13; regno++)
12214 if (THUMB_REG_PUSHED_P (regno))
12217 entry_size += count_regs * 4;
12219 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12221 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12224 cfun->machine->frame_size = base_size;
12229 /* Generate the rest of a function's prologue. */
12231 thumb_expand_prologue (void)
12235 HOST_WIDE_INT amount = (thumb_get_frame_size ()
12236 + current_function_outgoing_args_size);
12237 unsigned long func_type;
12239 func_type = arm_current_func_type ();
12241 /* Naked functions don't have prologues. */
12242 if (IS_NAKED (func_type))
12245 if (IS_INTERRUPT (func_type))
12247 error ("interrupt Service Routines cannot be coded in Thumb mode");
12251 if (frame_pointer_needed)
12253 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
12254 RTX_FRAME_RELATED_P (insn) = 1;
12259 amount = ROUND_UP_WORD (amount);
12263 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12264 GEN_INT (- amount)));
12265 RTX_FRAME_RELATED_P (insn) = 1;
12272 /* The stack decrement is too big for an immediate value in a single
12273 insn. In theory we could issue multiple subtracts, but after
12274 three of them it becomes more space efficient to place the full
12275 value in the constant pool and load into a register. (Also the
12276 ARM debugger really likes to see only one stack decrement per
12277 function). So instead we look for a scratch register into which
12278 we can load the decrement, and then we subtract this from the
12279 stack pointer. Unfortunately on the thumb the only available
12280 scratch registers are the argument registers, and we cannot use
12281 these as they may hold arguments to the function. Instead we
12282 attempt to locate a call preserved register which is used by this
12283 function. If we can find one, then we know that it will have
12284 been pushed at the start of the prologue and so we can corrupt
12286 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
12287 if (THUMB_REG_PUSHED_P (regno)
12288 && !(frame_pointer_needed
12289 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
12292 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
12294 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
12296 /* Choose an arbitrary, non-argument low register. */
12297 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
12299 /* Save it by copying it into a high, scratch register. */
12300 emit_insn (gen_movsi (spare, reg));
12301 /* Add a USE to stop propagate_one_insn() from barfing. */
12302 emit_insn (gen_prologue_use (spare));
12304 /* Decrement the stack. */
12305 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12306 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
12307 stack_pointer_rtx, reg));
12308 RTX_FRAME_RELATED_P (insn) = 1;
12309 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
12310 plus_constant (stack_pointer_rtx,
12311 GEN_INT (- amount)));
12312 RTX_FRAME_RELATED_P (dwarf) = 1;
12314 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
12317 /* Restore the low register's original value. */
12318 emit_insn (gen_movsi (reg, spare));
12320 /* Emit a USE of the restored scratch register, so that flow
12321 analysis will not consider the restore redundant. The
12322 register won't be used again in this function and isn't
12323 restored by the epilogue. */
12324 emit_insn (gen_prologue_use (reg));
12328 reg = gen_rtx (REG, SImode, regno);
12330 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12332 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
12333 stack_pointer_rtx, reg));
12334 RTX_FRAME_RELATED_P (insn) = 1;
12335 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
12336 plus_constant (stack_pointer_rtx,
12337 GEN_INT (- amount)));
12338 RTX_FRAME_RELATED_P (dwarf) = 1;
12340 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
12346 if (current_function_profile || TARGET_NO_SCHED_PRO)
12347 emit_insn (gen_blockage ());
12351 thumb_expand_epilogue (void)
12353 HOST_WIDE_INT amount = (thumb_get_frame_size ()
12354 + current_function_outgoing_args_size);
12357 /* Naked functions don't have prologues. */
12358 if (IS_NAKED (arm_current_func_type ()))
12361 if (frame_pointer_needed)
12362 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
12365 amount = ROUND_UP_WORD (amount);
12368 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12369 GEN_INT (amount)));
12372 /* r3 is always free in the epilogue. */
12373 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
12375 emit_insn (gen_movsi (reg, GEN_INT (amount)));
12376 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
12380 /* Emit a USE (stack_pointer_rtx), so that
12381 the stack adjustment will not be deleted. */
12382 emit_insn (gen_prologue_use (stack_pointer_rtx));
12384 if (current_function_profile || TARGET_NO_SCHED_PRO)
12385 emit_insn (gen_blockage ());
12387 /* Emit a clobber for each insn that will be restored in the epilogue,
12388 so that flow2 will get register lifetimes correct. */
12389 for (regno = 0; regno < 13; regno++)
12390 if (regs_ever_live[regno] && !call_used_regs[regno])
12391 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
12393 if (! regs_ever_live[LR_REGNUM])
12394 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
12398 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12400 int live_regs_mask = 0;
12401 int high_regs_pushed = 0;
12402 int cfa_offset = 0;
12405 if (IS_NAKED (arm_current_func_type ()))
12408 if (is_called_in_ARM_mode (current_function_decl))
12412 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
12414 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
12416 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12418 /* Generate code sequence to switch us into Thumb mode. */
12419 /* The .code 32 directive has already been emitted by
12420 ASM_DECLARE_FUNCTION_NAME. */
12421 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
12422 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
12424 /* Generate a label, so that the debugger will notice the
12425 change in instruction sets. This label is also used by
12426 the assembler to bypass the ARM code when this function
12427 is called from a Thumb encoded function elsewhere in the
12428 same file. Hence the definition of STUB_NAME here must
12429 agree with the definition in gas/config/tc-arm.c. */
12431 #define STUB_NAME ".real_start_of"
12433 fprintf (f, "\t.code\t16\n");
12435 if (arm_dllexport_name_p (name))
12436 name = arm_strip_name_encoding (name);
12438 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
12439 fprintf (f, "\t.thumb_func\n");
12440 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
12443 if (current_function_pretend_args_size)
12445 if (cfun->machine->uses_anonymous_args)
12449 fprintf (f, "\tpush\t{");
12451 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
12453 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
12454 regno <= LAST_ARG_REGNUM;
12456 asm_fprintf (f, "%r%s", regno,
12457 regno == LAST_ARG_REGNUM ? "" : ", ");
12459 fprintf (f, "}\n");
12462 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
12463 SP_REGNUM, SP_REGNUM,
12464 current_function_pretend_args_size);
12466 /* We don't need to record the stores for unwinding (would it
12467 help the debugger any if we did?), but record the change in
12468 the stack pointer. */
12469 if (dwarf2out_do_frame ())
12471 char *l = dwarf2out_cfi_label ();
12472 cfa_offset = cfa_offset + current_function_pretend_args_size;
12473 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
12477 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12478 if (THUMB_REG_PUSHED_P (regno))
12479 live_regs_mask |= 1 << regno;
12481 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
12482 live_regs_mask |= 1 << LR_REGNUM;
12484 if (TARGET_BACKTRACE)
12487 int work_register = 0;
12490 /* We have been asked to create a stack backtrace structure.
12491 The code looks like this:
12495 0 sub SP, #16 Reserve space for 4 registers.
12496 2 push {R7} Get a work register.
12497 4 add R7, SP, #20 Get the stack pointer before the push.
12498 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
12499 8 mov R7, PC Get hold of the start of this code plus 12.
12500 10 str R7, [SP, #16] Store it.
12501 12 mov R7, FP Get hold of the current frame pointer.
12502 14 str R7, [SP, #4] Store it.
12503 16 mov R7, LR Get hold of the current return address.
12504 18 str R7, [SP, #12] Store it.
12505 20 add R7, SP, #16 Point at the start of the backtrace structure.
12506 22 mov FP, R7 Put this value into the frame pointer. */
12508 if ((live_regs_mask & 0xFF) == 0)
12510 /* See if the a4 register is free. */
12512 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
12513 work_register = LAST_ARG_REGNUM;
12514 else /* We must push a register of our own. */
12515 live_regs_mask |= (1 << LAST_LO_REGNUM);
12518 if (work_register == 0)
12520 /* Select a register from the list that will be pushed to
12521 use as our work register. */
12522 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
12523 if ((1 << work_register) & live_regs_mask)
12528 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
12529 SP_REGNUM, SP_REGNUM);
12531 if (dwarf2out_do_frame ())
12533 char *l = dwarf2out_cfi_label ();
12534 cfa_offset = cfa_offset + 16;
12535 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
12538 if (live_regs_mask)
12539 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
12541 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
12542 if (wr & live_regs_mask)
12545 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
12546 offset + 16 + current_function_pretend_args_size);
12548 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12551 /* Make sure that the instruction fetching the PC is in the right place
12552 to calculate "start of backtrace creation code + 12". */
12553 if (live_regs_mask)
12555 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
12556 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12558 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
12559 ARM_HARD_FRAME_POINTER_REGNUM);
12560 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12565 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
12566 ARM_HARD_FRAME_POINTER_REGNUM);
12567 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12569 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
12570 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12574 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
12575 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12577 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
12579 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
12580 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
12582 else if (live_regs_mask)
12583 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
12585 for (regno = 8; regno < 13; regno++)
12586 if (THUMB_REG_PUSHED_P (regno))
12587 high_regs_pushed++;
12589 if (high_regs_pushed)
12591 int pushable_regs = 0;
12592 int mask = live_regs_mask & 0xff;
12595 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
12596 if (THUMB_REG_PUSHED_P (next_hi_reg))
12599 pushable_regs = mask;
12601 if (pushable_regs == 0)
12603 /* Desperation time -- this probably will never happen. */
12604 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
12605 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
12606 mask = 1 << LAST_ARG_REGNUM;
12609 while (high_regs_pushed > 0)
12611 int real_regs_mask = 0;
12613 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
12615 if (mask & (1 << regno))
12617 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
12619 high_regs_pushed--;
12620 real_regs_mask |= (1 << next_hi_reg);
12622 if (high_regs_pushed)
12624 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
12626 if (THUMB_REG_PUSHED_P (next_hi_reg))
12631 mask &= ~((1 << regno) - 1);
12637 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
12640 if (pushable_regs == 0
12641 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
12642 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12646 /* Handle the case of a double word load into a low register from
12647 a computed memory address. The computed address may involve a
12648 register which is overwritten by the load. */
12650 thumb_load_double_from_address (rtx *operands)
12658 if (GET_CODE (operands[0]) != REG)
12661 if (GET_CODE (operands[1]) != MEM)
12664 /* Get the memory address. */
12665 addr = XEXP (operands[1], 0);
12667 /* Work out how the memory address is computed. */
12668 switch (GET_CODE (addr))
12671 operands[2] = gen_rtx (MEM, SImode,
12672 plus_constant (XEXP (operands[1], 0), 4));
12674 if (REGNO (operands[0]) == REGNO (addr))
12676 output_asm_insn ("ldr\t%H0, %2", operands);
12677 output_asm_insn ("ldr\t%0, %1", operands);
12681 output_asm_insn ("ldr\t%0, %1", operands);
12682 output_asm_insn ("ldr\t%H0, %2", operands);
12687 /* Compute <address> + 4 for the high order load. */
12688 operands[2] = gen_rtx (MEM, SImode,
12689 plus_constant (XEXP (operands[1], 0), 4));
12691 output_asm_insn ("ldr\t%0, %1", operands);
12692 output_asm_insn ("ldr\t%H0, %2", operands);
12696 arg1 = XEXP (addr, 0);
12697 arg2 = XEXP (addr, 1);
12699 if (CONSTANT_P (arg1))
12700 base = arg2, offset = arg1;
12702 base = arg1, offset = arg2;
12704 if (GET_CODE (base) != REG)
12707 /* Catch the case of <address> = <reg> + <reg> */
12708 if (GET_CODE (offset) == REG)
12710 int reg_offset = REGNO (offset);
12711 int reg_base = REGNO (base);
12712 int reg_dest = REGNO (operands[0]);
12714 /* Add the base and offset registers together into the
12715 higher destination register. */
12716 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
12717 reg_dest + 1, reg_base, reg_offset);
12719 /* Load the lower destination register from the address in
12720 the higher destination register. */
12721 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
12722 reg_dest, reg_dest + 1);
12724 /* Load the higher destination register from its own address
12726 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
12727 reg_dest + 1, reg_dest + 1);
12731 /* Compute <address> + 4 for the high order load. */
12732 operands[2] = gen_rtx (MEM, SImode,
12733 plus_constant (XEXP (operands[1], 0), 4));
12735 /* If the computed address is held in the low order register
12736 then load the high order register first, otherwise always
12737 load the low order register first. */
12738 if (REGNO (operands[0]) == REGNO (base))
12740 output_asm_insn ("ldr\t%H0, %2", operands);
12741 output_asm_insn ("ldr\t%0, %1", operands);
12745 output_asm_insn ("ldr\t%0, %1", operands);
12746 output_asm_insn ("ldr\t%H0, %2", operands);
12752 /* With no registers to worry about we can just load the value
12754 operands[2] = gen_rtx (MEM, SImode,
12755 plus_constant (XEXP (operands[1], 0), 4));
12757 output_asm_insn ("ldr\t%H0, %2", operands);
12758 output_asm_insn ("ldr\t%0, %1", operands);
12770 thumb_output_move_mem_multiple (int n, rtx *operands)
12777 if (REGNO (operands[4]) > REGNO (operands[5]))
12780 operands[4] = operands[5];
12783 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
12784 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
12788 if (REGNO (operands[4]) > REGNO (operands[5]))
12791 operands[4] = operands[5];
12794 if (REGNO (operands[5]) > REGNO (operands[6]))
12797 operands[5] = operands[6];
12800 if (REGNO (operands[4]) > REGNO (operands[5]))
12803 operands[4] = operands[5];
12807 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
12808 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
12818 /* Routines for generating rtl. */
12820 thumb_expand_movstrqi (rtx *operands)
12822 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
12823 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
12824 HOST_WIDE_INT len = INTVAL (operands[2]);
12825 HOST_WIDE_INT offset = 0;
12829 emit_insn (gen_movmem12b (out, in, out, in));
12835 emit_insn (gen_movmem8b (out, in, out, in));
12841 rtx reg = gen_reg_rtx (SImode);
12842 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
12843 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
12850 rtx reg = gen_reg_rtx (HImode);
12851 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
12852 plus_constant (in, offset))));
12853 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
12861 rtx reg = gen_reg_rtx (QImode);
12862 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
12863 plus_constant (in, offset))));
12864 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
12870 thumb_cmp_operand (rtx op, enum machine_mode mode)
12872 return ((GET_CODE (op) == CONST_INT
12873 && INTVAL (op) < 256
12874 && INTVAL (op) >= 0)
12875 || s_register_operand (op, mode));
12879 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
12881 return (GET_CODE (op) == CONST_INT
12883 && INTVAL (op) > -256);
12886 /* Return TRUE if a result can be stored in OP without clobbering the
12887 condition code register. Prior to reload we only accept a
12888 register. After reload we have to be able to handle memory as
12889 well, since a pseudo may not get a hard reg and reload cannot
12890 handle output-reloads on jump insns.
12892 We could possibly handle mem before reload as well, but that might
12893 complicate things with the need to handle increment
12897 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
12899 return (s_register_operand (op, mode)
12900 || ((reload_in_progress || reload_completed)
12901 && memory_operand (op, mode)));
12904 /* Handle storing a half-word to memory during reload. */
12906 thumb_reload_out_hi (rtx *operands)
12908 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
12911 /* Handle reading a half-word from memory during reload. */
12913 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
12918 /* Return the length of a function name prefix
12919 that starts with the character 'c'. */
12921 arm_get_strip_length (int c)
12925 ARM_NAME_ENCODING_LENGTHS
12930 /* Return a pointer to a function's name with any
12931 and all prefix encodings stripped from it. */
12933 arm_strip_name_encoding (const char *name)
12937 while ((skip = arm_get_strip_length (* name)))
12943 /* If there is a '*' anywhere in the name's prefix, then
12944 emit the stripped name verbatim, otherwise prepend an
12945 underscore if leading underscores are being used. */
12947 arm_asm_output_labelref (FILE *stream, const char *name)
12952 while ((skip = arm_get_strip_length (* name)))
12954 verbatim |= (*name == '*');
12959 fputs (name, stream);
12961 asm_fprintf (stream, "%U%s", name);
12966 #ifdef AOF_ASSEMBLER
12967 /* Special functions only needed when producing AOF syntax assembler. */
12971 struct pic_chain * next;
12972 const char * symname;
12975 static struct pic_chain * aof_pic_chain = NULL;
12978 aof_pic_entry (rtx x)
12980 struct pic_chain ** chainp;
12983 if (aof_pic_label == NULL_RTX)
12985 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
12988 for (offset = 0, chainp = &aof_pic_chain; *chainp;
12989 offset += 4, chainp = &(*chainp)->next)
12990 if ((*chainp)->symname == XSTR (x, 0))
12991 return plus_constant (aof_pic_label, offset);
12993 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
12994 (*chainp)->next = NULL;
12995 (*chainp)->symname = XSTR (x, 0);
12996 return plus_constant (aof_pic_label, offset);
13000 aof_dump_pic_table (FILE *f)
13002 struct pic_chain * chain;
13004 if (aof_pic_chain == NULL)
13007 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13008 PIC_OFFSET_TABLE_REGNUM,
13009 PIC_OFFSET_TABLE_REGNUM);
13010 fputs ("|x$adcons|\n", f);
13012 for (chain = aof_pic_chain; chain; chain = chain->next)
13014 fputs ("\tDCD\t", f);
13015 assemble_name (f, chain->symname);
13020 int arm_text_section_count = 1;
13023 aof_text_section (void )
13025 static char buf[100];
13026 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
13027 arm_text_section_count++);
13029 strcat (buf, ", PIC, REENTRANT");
13033 static int arm_data_section_count = 1;
13036 aof_data_section (void)
13038 static char buf[100];
13039 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
13043 /* The AOF assembler is religiously strict about declarations of
13044 imported and exported symbols, so that it is impossible to declare
13045 a function as imported near the beginning of the file, and then to
13046 export it later on. It is, however, possible to delay the decision
13047 until all the functions in the file have been compiled. To get
13048 around this, we maintain a list of the imports and exports, and
13049 delete from it any that are subsequently defined. At the end of
13050 compilation we spit the remainder of the list out before the END
13055 struct import * next;
13059 static struct import * imports_list = NULL;
13062 aof_add_import (const char *name)
13064 struct import * new;
13066 for (new = imports_list; new; new = new->next)
13067 if (new->name == name)
13070 new = (struct import *) xmalloc (sizeof (struct import));
13071 new->next = imports_list;
13072 imports_list = new;
13077 aof_delete_import (const char *name)
13079 struct import ** old;
13081 for (old = &imports_list; *old; old = & (*old)->next)
13083 if ((*old)->name == name)
13085 *old = (*old)->next;
13091 int arm_main_function = 0;
13094 aof_dump_imports (FILE *f)
13096 /* The AOF assembler needs this to cause the startup code to be extracted
13097 from the library. Brining in __main causes the whole thing to work
13099 if (arm_main_function)
13102 fputs ("\tIMPORT __main\n", f);
13103 fputs ("\tDCD __main\n", f);
13106 /* Now dump the remaining imports. */
13107 while (imports_list)
13109 fprintf (f, "\tIMPORT\t");
13110 assemble_name (f, imports_list->name);
13112 imports_list = imports_list->next;
13117 aof_globalize_label (FILE *stream, const char *name)
13119 default_globalize_label (stream, name);
13120 if (! strcmp (name, "main"))
13121 arm_main_function = 1;
13125 aof_file_start (void)
13127 fputs ("__r0\tRN\t0\n", asm_out_file);
13128 fputs ("__a1\tRN\t0\n", asm_out_file);
13129 fputs ("__a2\tRN\t1\n", asm_out_file);
13130 fputs ("__a3\tRN\t2\n", asm_out_file);
13131 fputs ("__a4\tRN\t3\n", asm_out_file);
13132 fputs ("__v1\tRN\t4\n", asm_out_file);
13133 fputs ("__v2\tRN\t5\n", asm_out_file);
13134 fputs ("__v3\tRN\t6\n", asm_out_file);
13135 fputs ("__v4\tRN\t7\n", asm_out_file);
13136 fputs ("__v5\tRN\t8\n", asm_out_file);
13137 fputs ("__v6\tRN\t9\n", asm_out_file);
13138 fputs ("__sl\tRN\t10\n", asm_out_file);
13139 fputs ("__fp\tRN\t11\n", asm_out_file);
13140 fputs ("__ip\tRN\t12\n", asm_out_file);
13141 fputs ("__sp\tRN\t13\n", asm_out_file);
13142 fputs ("__lr\tRN\t14\n", asm_out_file);
13143 fputs ("__pc\tRN\t15\n", asm_out_file);
13144 fputs ("__f0\tFN\t0\n", asm_out_file);
13145 fputs ("__f1\tFN\t1\n", asm_out_file);
13146 fputs ("__f2\tFN\t2\n", asm_out_file);
13147 fputs ("__f3\tFN\t3\n", asm_out_file);
13148 fputs ("__f4\tFN\t4\n", asm_out_file);
13149 fputs ("__f5\tFN\t5\n", asm_out_file);
13150 fputs ("__f6\tFN\t6\n", asm_out_file);
13151 fputs ("__f7\tFN\t7\n", asm_out_file);
13156 aof_file_end (void)
13159 aof_dump_pic_table (asm_out_file);
13160 aof_dump_imports (asm_out_file);
13161 fputs ("\tEND\n", asm_out_file);
13163 #endif /* AOF_ASSEMBLER */
13165 #ifdef OBJECT_FORMAT_ELF
13166 /* Switch to an arbitrary section NAME with attributes as specified
13167 by FLAGS. ALIGN specifies any known alignment requirements for
13168 the section; 0 if the default should be used.
13170 Differs from the default elf version only in the prefix character
13171 used before the section type. */
13174 arm_elf_asm_named_section (const char *name, unsigned int flags)
13176 char flagchars[10], *f = flagchars;
13178 if (! named_section_first_declaration (name))
13180 fprintf (asm_out_file, "\t.section\t%s\n", name);
13184 if (!(flags & SECTION_DEBUG))
13186 if (flags & SECTION_WRITE)
13188 if (flags & SECTION_CODE)
13190 if (flags & SECTION_SMALL)
13192 if (flags & SECTION_MERGE)
13194 if (flags & SECTION_STRINGS)
13196 if (flags & SECTION_TLS)
13200 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
13202 if (!(flags & SECTION_NOTYPE))
13206 if (flags & SECTION_BSS)
13211 fprintf (asm_out_file, ",%%%s", type);
13213 if (flags & SECTION_ENTSIZE)
13214 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
13217 putc ('\n', asm_out_file);
13222 /* Symbols in the text segment can be accessed without indirecting via the
13223 constant pool; it may take an extra binary operation, but this is still
13224 faster than indirecting via memory. Don't do this when not optimizing,
13225 since we won't be calculating al of the offsets necessary to do this
13229 arm_encode_section_info (tree decl, rtx rtl, int first)
13231 /* This doesn't work with AOF syntax, since the string table may be in
13232 a different AREA. */
13233 #ifndef AOF_ASSEMBLER
13234 if (optimize > 0 && TREE_CONSTANT (decl)
13235 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST))
13236 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
13239 /* If we are referencing a function that is weak then encode a long call
13240 flag in the function name, otherwise if the function is static or
13241 or known to be defined in this file then encode a short call flag. */
13242 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
13244 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
13245 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
13246 else if (! TREE_PUBLIC (decl))
13247 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
13250 #endif /* !ARM_PE */
13253 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
13255 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
13256 && !strcmp (prefix, "L"))
13258 arm_ccfsm_state = 0;
13259 arm_target_insn = NULL;
13261 default_internal_label (stream, prefix, labelno);
13264 /* Output code to add DELTA to the first argument, and then jump
13265 to FUNCTION. Used for C++ multiple inheritance. */
13267 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
13268 HOST_WIDE_INT delta,
13269 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
13272 static int thunk_label = 0;
13274 int mi_delta = delta;
13275 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
13277 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
13280 mi_delta = - mi_delta;
13283 int labelno = thunk_label++;
13284 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
13285 fputs ("\tldr\tr12, ", file);
13286 assemble_name (file, label);
13287 fputc ('\n', file);
13289 while (mi_delta != 0)
13291 if ((mi_delta & (3 << shift)) == 0)
13295 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
13296 mi_op, this_regno, this_regno,
13297 mi_delta & (0xff << shift));
13298 mi_delta &= ~(0xff << shift);
13304 fprintf (file, "\tbx\tr12\n");
13305 ASM_OUTPUT_ALIGN (file, 2);
13306 assemble_name (file, label);
13307 fputs (":\n", file);
13308 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
13312 fputs ("\tb\t", file);
13313 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
13314 if (NEED_PLT_RELOC)
13315 fputs ("(PLT)", file);
13316 fputc ('\n', file);
13321 arm_emit_vector_const (FILE *file, rtx x)
13324 const char * pattern;
13326 if (GET_CODE (x) != CONST_VECTOR)
13329 switch (GET_MODE (x))
13331 case V2SImode: pattern = "%08x"; break;
13332 case V4HImode: pattern = "%04x"; break;
13333 case V8QImode: pattern = "%02x"; break;
13337 fprintf (file, "0x");
13338 for (i = CONST_VECTOR_NUNITS (x); i--;)
13342 element = CONST_VECTOR_ELT (x, i);
13343 fprintf (file, pattern, INTVAL (element));
13350 arm_output_load_gr (rtx *operands)
13357 if (GET_CODE (operands [1]) != MEM
13358 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
13359 || GET_CODE (reg = XEXP (sum, 0)) != REG
13360 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
13361 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
13362 return "wldrw%?\t%0, %1";
13364 /* Fix up an out-of-range load of a GR register. */
13365 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
13366 wcgr = operands[0];
13368 output_asm_insn ("ldr%?\t%0, %1", operands);
13370 operands[0] = wcgr;
13372 output_asm_insn ("tmcr%?\t%0, %1", operands);
13373 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);