1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
71 inline static int thumb_index_register_rtx_p (rtx, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
75 static rtx emit_sfm (int, int);
76 static int arm_size_return_regs (void);
78 static bool arm_assemble_integer (rtx, unsigned int, int);
80 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
81 static arm_cc get_arm_condition_code (rtx);
82 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
83 static rtx is_jump_table (rtx);
84 static const char *output_multi_immediate (rtx *, const char *, const char *,
86 static const char *shift_op (rtx, HOST_WIDE_INT *);
87 static struct machine_function *arm_init_machine_status (void);
88 static void thumb_exit (FILE *, int);
89 static rtx is_jump_table (rtx);
90 static HOST_WIDE_INT get_jump_table_size (rtx);
91 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
92 static Mnode *add_minipool_forward_ref (Mfix *);
93 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_backward_ref (Mfix *);
95 static void assign_minipool_offsets (Mfix *);
96 static void arm_print_value (FILE *, rtx);
97 static void dump_minipool (rtx);
98 static int arm_barrier_cost (rtx);
99 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
100 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
101 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
105 static int current_file_function_operand (rtx);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree);
109 static unsigned long arm_compute_func_type (void);
110 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
111 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
112 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
113 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
115 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
116 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
118 static int arm_comp_type_attributes (tree, tree);
119 static void arm_set_default_type_attributes (tree);
120 static int arm_adjust_cost (rtx, rtx, rtx, int);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_size_rtx_costs (rtx, int, int, int *);
129 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
131 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
132 static bool arm_9e_rtx_costs (rtx, int, int, int *);
133 static int arm_address_cost (rtx);
134 static bool arm_memory_load_p (rtx);
135 static bool arm_cirrus_insn_p (rtx);
136 static void cirrus_reorg (rtx);
137 static void arm_init_builtins (void);
138 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
139 static void arm_init_iwmmxt_builtins (void);
140 static rtx safe_vector_operand (rtx, enum machine_mode);
141 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
142 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
143 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
144 static void emit_constant_insn (rtx cond, rtx pattern);
145 static rtx emit_set_insn (rtx, rtx);
146 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
149 #ifdef OBJECT_FORMAT_ELF
150 static void arm_elf_asm_constructor (rtx, int);
153 static void arm_encode_section_info (tree, rtx, int);
156 static void arm_file_end (void);
159 static void aof_globalize_label (FILE *, const char *);
160 static void aof_dump_imports (FILE *);
161 static void aof_dump_pic_table (FILE *);
162 static void aof_file_start (void);
163 static void aof_file_end (void);
164 static void aof_asm_init_sections (void);
166 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
168 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
169 enum machine_mode, tree, bool);
170 static bool arm_promote_prototypes (tree);
171 static bool arm_default_short_enums (void);
172 static bool arm_align_anon_bitfield (void);
173 static bool arm_return_in_msb (tree);
174 static bool arm_must_pass_in_stack (enum machine_mode, tree);
175 #ifdef TARGET_UNWIND_INFO
176 static void arm_unwind_emit (FILE *, rtx);
177 static bool arm_output_ttype (rtx);
180 static tree arm_cxx_guard_type (void);
181 static bool arm_cxx_guard_mask_bit (void);
182 static tree arm_get_cookie_size (tree);
183 static bool arm_cookie_has_size (void);
184 static bool arm_cxx_cdtor_returns_this (void);
185 static bool arm_cxx_key_method_may_be_inline (void);
186 static void arm_cxx_determine_class_data_visibility (tree);
187 static bool arm_cxx_class_data_always_comdat (void);
188 static bool arm_cxx_use_aeabi_atexit (void);
189 static void arm_init_libfuncs (void);
190 static bool arm_handle_option (size_t, const char *, int);
191 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
192 static bool arm_cannot_copy_insn_p (rtx);
193 static bool arm_tls_symbol_p (rtx x);
196 /* Initialize the GCC target structure. */
197 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
198 #undef TARGET_MERGE_DECL_ATTRIBUTES
199 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
202 #undef TARGET_ATTRIBUTE_TABLE
203 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
205 #undef TARGET_ASM_FILE_END
206 #define TARGET_ASM_FILE_END arm_file_end
209 #undef TARGET_ASM_BYTE_OP
210 #define TARGET_ASM_BYTE_OP "\tDCB\t"
211 #undef TARGET_ASM_ALIGNED_HI_OP
212 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
213 #undef TARGET_ASM_ALIGNED_SI_OP
214 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
215 #undef TARGET_ASM_GLOBALIZE_LABEL
216 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
217 #undef TARGET_ASM_FILE_START
218 #define TARGET_ASM_FILE_START aof_file_start
219 #undef TARGET_ASM_FILE_END
220 #define TARGET_ASM_FILE_END aof_file_end
222 #undef TARGET_ASM_ALIGNED_SI_OP
223 #define TARGET_ASM_ALIGNED_SI_OP NULL
224 #undef TARGET_ASM_INTEGER
225 #define TARGET_ASM_INTEGER arm_assemble_integer
228 #undef TARGET_ASM_FUNCTION_PROLOGUE
229 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
231 #undef TARGET_ASM_FUNCTION_EPILOGUE
232 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
234 #undef TARGET_DEFAULT_TARGET_FLAGS
235 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
236 #undef TARGET_HANDLE_OPTION
237 #define TARGET_HANDLE_OPTION arm_handle_option
239 #undef TARGET_COMP_TYPE_ATTRIBUTES
240 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
242 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
243 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
245 #undef TARGET_SCHED_ADJUST_COST
246 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
248 #undef TARGET_ENCODE_SECTION_INFO
250 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
252 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
255 #undef TARGET_STRIP_NAME_ENCODING
256 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
258 #undef TARGET_ASM_INTERNAL_LABEL
259 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
261 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
262 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
264 #undef TARGET_ASM_OUTPUT_MI_THUNK
265 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
266 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
267 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
269 /* This will be overridden in arm_override_options. */
270 #undef TARGET_RTX_COSTS
271 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
272 #undef TARGET_ADDRESS_COST
273 #define TARGET_ADDRESS_COST arm_address_cost
275 #undef TARGET_SHIFT_TRUNCATION_MASK
276 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
277 #undef TARGET_VECTOR_MODE_SUPPORTED_P
278 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
280 #undef TARGET_MACHINE_DEPENDENT_REORG
281 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
283 #undef TARGET_INIT_BUILTINS
284 #define TARGET_INIT_BUILTINS arm_init_builtins
285 #undef TARGET_EXPAND_BUILTIN
286 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
288 #undef TARGET_INIT_LIBFUNCS
289 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
291 #undef TARGET_PROMOTE_FUNCTION_ARGS
292 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
293 #undef TARGET_PROMOTE_FUNCTION_RETURN
294 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
295 #undef TARGET_PROMOTE_PROTOTYPES
296 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
297 #undef TARGET_PASS_BY_REFERENCE
298 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
299 #undef TARGET_ARG_PARTIAL_BYTES
300 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
302 #undef TARGET_SETUP_INCOMING_VARARGS
303 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
305 #undef TARGET_DEFAULT_SHORT_ENUMS
306 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
308 #undef TARGET_ALIGN_ANON_BITFIELD
309 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
311 #undef TARGET_NARROW_VOLATILE_BITFIELD
312 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
314 #undef TARGET_CXX_GUARD_TYPE
315 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
317 #undef TARGET_CXX_GUARD_MASK_BIT
318 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
320 #undef TARGET_CXX_GET_COOKIE_SIZE
321 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
323 #undef TARGET_CXX_COOKIE_HAS_SIZE
324 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
326 #undef TARGET_CXX_CDTOR_RETURNS_THIS
327 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
329 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
330 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
332 #undef TARGET_CXX_USE_AEABI_ATEXIT
333 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
335 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
336 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
337 arm_cxx_determine_class_data_visibility
339 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
340 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
342 #undef TARGET_RETURN_IN_MSB
343 #define TARGET_RETURN_IN_MSB arm_return_in_msb
345 #undef TARGET_MUST_PASS_IN_STACK
346 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
348 #ifdef TARGET_UNWIND_INFO
349 #undef TARGET_UNWIND_EMIT
350 #define TARGET_UNWIND_EMIT arm_unwind_emit
352 /* EABI unwinding tables use a different format for the typeinfo tables. */
353 #undef TARGET_ASM_TTYPE
354 #define TARGET_ASM_TTYPE arm_output_ttype
356 #undef TARGET_ARM_EABI_UNWINDER
357 #define TARGET_ARM_EABI_UNWINDER true
358 #endif /* TARGET_UNWIND_INFO */
360 #undef TARGET_CANNOT_COPY_INSN_P
361 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
364 #undef TARGET_HAVE_TLS
365 #define TARGET_HAVE_TLS true
368 #undef TARGET_CANNOT_FORCE_CONST_MEM
369 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
371 struct gcc_target targetm = TARGET_INITIALIZER;
373 /* Obstack for minipool constant handling. */
374 static struct obstack minipool_obstack;
375 static char * minipool_startobj;
377 /* The maximum number of insns skipped which
378 will be conditionalised if possible. */
379 static int max_insns_skipped = 5;
381 extern FILE * asm_out_file;
383 /* True if we are currently building a constant table. */
384 int making_const_table;
386 /* Define the information needed to generate branch insns. This is
387 stored from the compare operation. */
388 rtx arm_compare_op0, arm_compare_op1;
390 /* The processor for which instructions should be scheduled. */
391 enum processor_type arm_tune = arm_none;
393 /* Which floating point model to use. */
394 enum arm_fp_model arm_fp_model;
396 /* Which floating point hardware is available. */
397 enum fputype arm_fpu_arch;
399 /* Which floating point hardware to schedule for. */
400 enum fputype arm_fpu_tune;
402 /* Whether to use floating point hardware. */
403 enum float_abi_type arm_float_abi;
405 /* Which ABI to use. */
406 enum arm_abi_type arm_abi;
408 /* Which thread pointer model to use. */
409 enum arm_tp_type target_thread_pointer = TP_AUTO;
411 /* Used to parse -mstructure_size_boundary command line option. */
412 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
414 /* Used for Thumb call_via trampolines. */
415 rtx thumb_call_via_label[14];
416 static int thumb_call_reg_needed;
418 /* Bit values used to identify processor capabilities. */
419 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
420 #define FL_ARCH3M (1 << 1) /* Extended multiply */
421 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
422 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
423 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
424 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
425 #define FL_THUMB (1 << 6) /* Thumb aware */
426 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
427 #define FL_STRONG (1 << 8) /* StrongARM */
428 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
429 #define FL_XSCALE (1 << 10) /* XScale */
430 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
431 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
432 media instructions. */
433 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
434 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
435 Note: ARM6 & 7 derivatives only. */
436 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
438 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
440 #define FL_FOR_ARCH2 0
441 #define FL_FOR_ARCH3 FL_MODE32
442 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
443 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
444 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
445 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
446 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
447 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
448 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
449 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
450 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
451 #define FL_FOR_ARCH6J FL_FOR_ARCH6
452 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
453 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
454 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
456 /* The bits in this mask specify which
457 instructions we are allowed to generate. */
458 static unsigned long insn_flags = 0;
460 /* The bits in this mask specify which instruction scheduling options should
462 static unsigned long tune_flags = 0;
464 /* The following are used in the arm.md file as equivalents to bits
465 in the above two flag variables. */
467 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
470 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
473 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
476 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
479 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
482 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
485 /* Nonzero if this chip supports the ARM 6K extensions. */
488 /* Nonzero if this chip can benefit from load scheduling. */
489 int arm_ld_sched = 0;
491 /* Nonzero if this chip is a StrongARM. */
492 int arm_tune_strongarm = 0;
494 /* Nonzero if this chip is a Cirrus variant. */
495 int arm_arch_cirrus = 0;
497 /* Nonzero if this chip supports Intel Wireless MMX technology. */
498 int arm_arch_iwmmxt = 0;
500 /* Nonzero if this chip is an XScale. */
501 int arm_arch_xscale = 0;
503 /* Nonzero if tuning for XScale */
504 int arm_tune_xscale = 0;
506 /* Nonzero if we want to tune for stores that access the write-buffer.
507 This typically means an ARM6 or ARM7 with MMU or MPU. */
508 int arm_tune_wbuf = 0;
510 /* Nonzero if generating Thumb instructions. */
513 /* Nonzero if we should define __THUMB_INTERWORK__ in the
515 XXX This is a bit of a hack, it's intended to help work around
516 problems in GLD which doesn't understand that armv5t code is
517 interworking clean. */
518 int arm_cpp_interwork = 0;
520 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
521 must report the mode of the memory reference from PRINT_OPERAND to
522 PRINT_OPERAND_ADDRESS. */
523 enum machine_mode output_memory_reference_mode;
525 /* The register number to be used for the PIC offset register. */
526 unsigned arm_pic_register = INVALID_REGNUM;
528 /* Set to 1 when a return insn is output, this means that the epilogue
530 int return_used_this_function;
532 /* Set to 1 after arm_reorg has started. Reset to start at the start of
533 the next function. */
534 static int after_arm_reorg = 0;
536 /* The maximum number of insns to be used when loading a constant. */
537 static int arm_constant_limit = 3;
539 /* For an explanation of these variables, see final_prescan_insn below. */
541 enum arm_cond_code arm_current_cc;
543 int arm_target_label;
545 /* The condition codes of the ARM, and the inverse function. */
546 static const char * const arm_condition_codes[] =
548 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
549 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
552 #define streq(string1, string2) (strcmp (string1, string2) == 0)
554 /* Initialization code. */
558 const char *const name;
559 enum processor_type core;
561 const unsigned long flags;
562 bool (* rtx_costs) (rtx, int, int, int *);
565 /* Not all of these give usefully different compilation alternatives,
566 but there is no simple way of generalizing them. */
567 static const struct processors all_cores[] =
570 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
571 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
572 #include "arm-cores.def"
574 {NULL, arm_none, NULL, 0, NULL}
577 static const struct processors all_architectures[] =
579 /* ARM Architectures */
580 /* We don't specify rtx_costs here as it will be figured out
583 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
584 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
585 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
586 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
587 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
588 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
589 implementations that support it, so we will leave it out for now. */
590 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
591 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
592 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
593 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
594 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
595 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
596 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
597 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
598 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
599 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
600 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
601 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
602 {NULL, arm_none, NULL, 0 , NULL}
605 struct arm_cpu_select
609 const struct processors * processors;
612 /* This is a magic structure. The 'string' field is magically filled in
613 with a pointer to the value specified by the user on the command line
614 assuming that the user has specified such a value. */
616 static struct arm_cpu_select arm_select[] =
618 /* string name processors */
619 { NULL, "-mcpu=", all_cores },
620 { NULL, "-march=", all_architectures },
621 { NULL, "-mtune=", all_cores }
624 /* Defines representing the indexes into the above table. */
625 #define ARM_OPT_SET_CPU 0
626 #define ARM_OPT_SET_ARCH 1
627 #define ARM_OPT_SET_TUNE 2
629 /* The name of the preprocessor macro to define for this architecture. */
631 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
640 /* Available values for -mfpu=. */
642 static const struct fpu_desc all_fpus[] =
644 {"fpa", FPUTYPE_FPA},
645 {"fpe2", FPUTYPE_FPA_EMU2},
646 {"fpe3", FPUTYPE_FPA_EMU2},
647 {"maverick", FPUTYPE_MAVERICK},
652 /* Floating point models used by the different hardware.
653 See fputype in arm.h. */
655 static const enum fputype fp_model_for_fpu[] =
657 /* No FP hardware. */
658 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
659 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
660 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
661 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
662 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
663 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
670 enum float_abi_type abi_type;
674 /* Available values for -mfloat-abi=. */
676 static const struct float_abi all_float_abis[] =
678 {"soft", ARM_FLOAT_ABI_SOFT},
679 {"softfp", ARM_FLOAT_ABI_SOFTFP},
680 {"hard", ARM_FLOAT_ABI_HARD}
687 enum arm_abi_type abi_type;
691 /* Available values for -mabi=. */
693 static const struct abi_name arm_all_abis[] =
695 {"apcs-gnu", ARM_ABI_APCS},
696 {"atpcs", ARM_ABI_ATPCS},
697 {"aapcs", ARM_ABI_AAPCS},
698 {"iwmmxt", ARM_ABI_IWMMXT},
699 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
702 /* Supported TLS relocations. */
712 /* Emit an insn that's a simple single-set. Both the operands must be known
715 emit_set_insn (rtx x, rtx y)
717 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
720 /* Return the number of bits set in VALUE. */
722 bit_count (unsigned long value)
724 unsigned long count = 0;
729 value &= value - 1; /* Clear the least-significant set bit. */
735 /* Set up library functions unique to ARM. */
738 arm_init_libfuncs (void)
740 /* There are no special library functions unless we are using the
745 /* The functions below are described in Section 4 of the "Run-Time
746 ABI for the ARM architecture", Version 1.0. */
748 /* Double-precision floating-point arithmetic. Table 2. */
749 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
750 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
751 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
752 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
753 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
755 /* Double-precision comparisons. Table 3. */
756 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
757 set_optab_libfunc (ne_optab, DFmode, NULL);
758 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
759 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
760 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
761 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
762 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
764 /* Single-precision floating-point arithmetic. Table 4. */
765 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
766 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
767 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
768 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
769 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
771 /* Single-precision comparisons. Table 5. */
772 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
773 set_optab_libfunc (ne_optab, SFmode, NULL);
774 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
775 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
776 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
777 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
778 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
780 /* Floating-point to integer conversions. Table 6. */
781 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
782 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
783 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
784 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
785 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
786 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
787 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
788 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
790 /* Conversions between floating types. Table 7. */
791 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
792 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
794 /* Integer to floating-point conversions. Table 8. */
795 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
796 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
797 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
798 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
799 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
800 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
801 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
802 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
804 /* Long long. Table 9. */
805 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
806 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
807 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
808 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
809 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
810 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
811 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
812 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
814 /* Integer (32/32->32) division. \S 4.3.1. */
815 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
816 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
818 /* The divmod functions are designed so that they can be used for
819 plain division, even though they return both the quotient and the
820 remainder. The quotient is returned in the usual location (i.e.,
821 r0 for SImode, {r0, r1} for DImode), just as would be expected
822 for an ordinary division routine. Because the AAPCS calling
823 conventions specify that all of { r0, r1, r2, r3 } are
824 callee-saved registers, there is no need to tell the compiler
825 explicitly that those registers are clobbered by these
827 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
828 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
830 /* For SImode division the ABI provides div-without-mod routines,
832 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
833 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
835 /* We don't have mod libcalls. Fortunately gcc knows how to use the
836 divmod libcalls instead. */
837 set_optab_libfunc (smod_optab, DImode, NULL);
838 set_optab_libfunc (umod_optab, DImode, NULL);
839 set_optab_libfunc (smod_optab, SImode, NULL);
840 set_optab_libfunc (umod_optab, SImode, NULL);
843 /* Implement TARGET_HANDLE_OPTION. */
846 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
851 arm_select[1].string = arg;
855 arm_select[0].string = arg;
858 case OPT_mhard_float:
859 target_float_abi_name = "hard";
862 case OPT_msoft_float:
863 target_float_abi_name = "soft";
867 arm_select[2].string = arg;
875 /* Fix up any incompatible options that the user has specified.
876 This has now turned into a maze. */
878 arm_override_options (void)
881 enum processor_type target_arch_cpu = arm_none;
883 /* Set up the flags based on the cpu/architecture selected by the user. */
884 for (i = ARRAY_SIZE (arm_select); i--;)
886 struct arm_cpu_select * ptr = arm_select + i;
888 if (ptr->string != NULL && ptr->string[0] != '\0')
890 const struct processors * sel;
892 for (sel = ptr->processors; sel->name != NULL; sel++)
893 if (streq (ptr->string, sel->name))
895 /* Set the architecture define. */
896 if (i != ARM_OPT_SET_TUNE)
897 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
899 /* Determine the processor core for which we should
900 tune code-generation. */
901 if (/* -mcpu= is a sensible default. */
903 /* -mtune= overrides -mcpu= and -march=. */
904 || i == ARM_OPT_SET_TUNE)
905 arm_tune = (enum processor_type) (sel - ptr->processors);
907 /* Remember the CPU associated with this architecture.
908 If no other option is used to set the CPU type,
909 we'll use this to guess the most suitable tuning
911 if (i == ARM_OPT_SET_ARCH)
912 target_arch_cpu = sel->core;
914 if (i != ARM_OPT_SET_TUNE)
916 /* If we have been given an architecture and a processor
917 make sure that they are compatible. We only generate
918 a warning though, and we prefer the CPU over the
920 if (insn_flags != 0 && (insn_flags ^ sel->flags))
921 warning (0, "switch -mcpu=%s conflicts with -march= switch",
924 insn_flags = sel->flags;
930 if (sel->name == NULL)
931 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
935 /* Guess the tuning options from the architecture if necessary. */
936 if (arm_tune == arm_none)
937 arm_tune = target_arch_cpu;
939 /* If the user did not specify a processor, choose one for them. */
942 const struct processors * sel;
944 enum processor_type cpu;
946 cpu = TARGET_CPU_DEFAULT;
949 #ifdef SUBTARGET_CPU_DEFAULT
950 /* Use the subtarget default CPU if none was specified by
952 cpu = SUBTARGET_CPU_DEFAULT;
954 /* Default to ARM6. */
958 sel = &all_cores[cpu];
960 insn_flags = sel->flags;
962 /* Now check to see if the user has specified some command line
963 switch that require certain abilities from the cpu. */
966 if (TARGET_INTERWORK || TARGET_THUMB)
968 sought |= (FL_THUMB | FL_MODE32);
970 /* There are no ARM processors that support both APCS-26 and
971 interworking. Therefore we force FL_MODE26 to be removed
972 from insn_flags here (if it was set), so that the search
973 below will always be able to find a compatible processor. */
974 insn_flags &= ~FL_MODE26;
977 if (sought != 0 && ((sought & insn_flags) != sought))
979 /* Try to locate a CPU type that supports all of the abilities
980 of the default CPU, plus the extra abilities requested by
982 for (sel = all_cores; sel->name != NULL; sel++)
983 if ((sel->flags & sought) == (sought | insn_flags))
986 if (sel->name == NULL)
988 unsigned current_bit_count = 0;
989 const struct processors * best_fit = NULL;
991 /* Ideally we would like to issue an error message here
992 saying that it was not possible to find a CPU compatible
993 with the default CPU, but which also supports the command
994 line options specified by the programmer, and so they
995 ought to use the -mcpu=<name> command line option to
996 override the default CPU type.
998 If we cannot find a cpu that has both the
999 characteristics of the default cpu and the given
1000 command line options we scan the array again looking
1001 for a best match. */
1002 for (sel = all_cores; sel->name != NULL; sel++)
1003 if ((sel->flags & sought) == sought)
1007 count = bit_count (sel->flags & insn_flags);
1009 if (count >= current_bit_count)
1012 current_bit_count = count;
1016 gcc_assert (best_fit);
1020 insn_flags = sel->flags;
1022 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1023 if (arm_tune == arm_none)
1024 arm_tune = (enum processor_type) (sel - all_cores);
1027 /* The processor for which we should tune should now have been
1029 gcc_assert (arm_tune != arm_none);
1031 tune_flags = all_cores[(int)arm_tune].flags;
1033 targetm.rtx_costs = arm_size_rtx_costs;
1035 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
1037 /* Make sure that the processor choice does not conflict with any of the
1038 other command line choices. */
1039 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
1041 warning (0, "target CPU does not support interworking" );
1042 target_flags &= ~MASK_INTERWORK;
1045 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1047 warning (0, "target CPU does not support THUMB instructions");
1048 target_flags &= ~MASK_THUMB;
1051 if (TARGET_APCS_FRAME && TARGET_THUMB)
1053 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1054 target_flags &= ~MASK_APCS_FRAME;
1057 /* Callee super interworking implies thumb interworking. Adding
1058 this to the flags here simplifies the logic elsewhere. */
1059 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1060 target_flags |= MASK_INTERWORK;
1062 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1063 from here where no function is being compiled currently. */
1064 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1065 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1067 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1068 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1070 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1071 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1073 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1075 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1076 target_flags |= MASK_APCS_FRAME;
1079 if (TARGET_POKE_FUNCTION_NAME)
1080 target_flags |= MASK_APCS_FRAME;
1082 if (TARGET_APCS_REENT && flag_pic)
1083 error ("-fpic and -mapcs-reent are incompatible");
1085 if (TARGET_APCS_REENT)
1086 warning (0, "APCS reentrant code not supported. Ignored");
1088 /* If this target is normally configured to use APCS frames, warn if they
1089 are turned off and debugging is turned on. */
1091 && write_symbols != NO_DEBUG
1092 && !TARGET_APCS_FRAME
1093 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1094 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1096 /* If stack checking is disabled, we can use r10 as the PIC register,
1097 which keeps r9 available. */
1098 if (flag_pic && TARGET_SINGLE_PIC_BASE)
1099 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
1101 if (TARGET_APCS_FLOAT)
1102 warning (0, "passing floating point arguments in fp regs not yet supported");
1104 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1105 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1106 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1107 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1108 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1109 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1110 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1111 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1112 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1113 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1115 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1116 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1117 thumb_code = (TARGET_ARM == 0);
1118 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1119 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1120 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1122 /* V5 code we generate is completely interworking capable, so we turn off
1123 TARGET_INTERWORK here to avoid many tests later on. */
1125 /* XXX However, we must pass the right pre-processor defines to CPP
1126 or GLD can get confused. This is a hack. */
1127 if (TARGET_INTERWORK)
1128 arm_cpp_interwork = 1;
1131 target_flags &= ~MASK_INTERWORK;
1133 if (target_abi_name)
1135 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1137 if (streq (arm_all_abis[i].name, target_abi_name))
1139 arm_abi = arm_all_abis[i].abi_type;
1143 if (i == ARRAY_SIZE (arm_all_abis))
1144 error ("invalid ABI option: -mabi=%s", target_abi_name);
1147 arm_abi = ARM_DEFAULT_ABI;
1149 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1150 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1152 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1153 error ("iwmmxt abi requires an iwmmxt capable cpu");
1155 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1156 if (target_fpu_name == NULL && target_fpe_name != NULL)
1158 if (streq (target_fpe_name, "2"))
1159 target_fpu_name = "fpe2";
1160 else if (streq (target_fpe_name, "3"))
1161 target_fpu_name = "fpe3";
1163 error ("invalid floating point emulation option: -mfpe=%s",
1166 if (target_fpu_name != NULL)
1168 /* The user specified a FPU. */
1169 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1171 if (streq (all_fpus[i].name, target_fpu_name))
1173 arm_fpu_arch = all_fpus[i].fpu;
1174 arm_fpu_tune = arm_fpu_arch;
1175 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1179 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1180 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1184 #ifdef FPUTYPE_DEFAULT
1185 /* Use the default if it is specified for this platform. */
1186 arm_fpu_arch = FPUTYPE_DEFAULT;
1187 arm_fpu_tune = FPUTYPE_DEFAULT;
1189 /* Pick one based on CPU type. */
1190 /* ??? Some targets assume FPA is the default.
1191 if ((insn_flags & FL_VFP) != 0)
1192 arm_fpu_arch = FPUTYPE_VFP;
1195 if (arm_arch_cirrus)
1196 arm_fpu_arch = FPUTYPE_MAVERICK;
1198 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1200 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1201 arm_fpu_tune = FPUTYPE_FPA;
1203 arm_fpu_tune = arm_fpu_arch;
1204 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1205 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1208 if (target_float_abi_name != NULL)
1210 /* The user specified a FP ABI. */
1211 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1213 if (streq (all_float_abis[i].name, target_float_abi_name))
1215 arm_float_abi = all_float_abis[i].abi_type;
1219 if (i == ARRAY_SIZE (all_float_abis))
1220 error ("invalid floating point abi: -mfloat-abi=%s",
1221 target_float_abi_name);
1224 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1226 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1227 sorry ("-mfloat-abi=hard and VFP");
1229 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1230 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1231 will ever exist. GCC makes no attempt to support this combination. */
1232 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1233 sorry ("iWMMXt and hardware floating point");
1235 /* If soft-float is specified then don't use FPU. */
1236 if (TARGET_SOFT_FLOAT)
1237 arm_fpu_arch = FPUTYPE_NONE;
1239 /* For arm2/3 there is no need to do any scheduling if there is only
1240 a floating point emulator, or we are doing software floating-point. */
1241 if ((TARGET_SOFT_FLOAT
1242 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1243 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1244 && (tune_flags & FL_MODE32) == 0)
1245 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1247 if (target_thread_switch)
1249 if (strcmp (target_thread_switch, "soft") == 0)
1250 target_thread_pointer = TP_SOFT;
1251 else if (strcmp (target_thread_switch, "auto") == 0)
1252 target_thread_pointer = TP_AUTO;
1253 else if (strcmp (target_thread_switch, "cp15") == 0)
1254 target_thread_pointer = TP_CP15;
1256 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1259 /* Use the cp15 method if it is available. */
1260 if (target_thread_pointer == TP_AUTO)
1262 if (arm_arch6k && !TARGET_THUMB)
1263 target_thread_pointer = TP_CP15;
1265 target_thread_pointer = TP_SOFT;
1268 if (TARGET_HARD_TP && TARGET_THUMB)
1269 error ("can not use -mtp=cp15 with -mthumb");
1271 /* Override the default structure alignment for AAPCS ABI. */
1272 if (TARGET_AAPCS_BASED)
1273 arm_structure_size_boundary = 8;
1275 if (structure_size_string != NULL)
1277 int size = strtol (structure_size_string, NULL, 0);
1279 if (size == 8 || size == 32
1280 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1281 arm_structure_size_boundary = size;
1283 warning (0, "structure size boundary can only be set to %s",
1284 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1287 if (arm_pic_register_string != NULL)
1289 int pic_register = decode_reg_name (arm_pic_register_string);
1292 warning (0, "-mpic-register= is useless without -fpic");
1294 /* Prevent the user from choosing an obviously stupid PIC register. */
1295 else if (pic_register < 0 || call_used_regs[pic_register]
1296 || pic_register == HARD_FRAME_POINTER_REGNUM
1297 || pic_register == STACK_POINTER_REGNUM
1298 || pic_register >= PC_REGNUM)
1299 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1301 arm_pic_register = pic_register;
1304 if (TARGET_THUMB && flag_schedule_insns)
1306 /* Don't warn since it's on by default in -O2. */
1307 flag_schedule_insns = 0;
1312 arm_constant_limit = 1;
1314 /* If optimizing for size, bump the number of instructions that we
1315 are prepared to conditionally execute (even on a StrongARM). */
1316 max_insns_skipped = 6;
1320 /* For processors with load scheduling, it never costs more than
1321 2 cycles to load a constant, and the load scheduler may well
1322 reduce that to 1. */
1324 arm_constant_limit = 1;
1326 /* On XScale the longer latency of a load makes it more difficult
1327 to achieve a good schedule, so it's faster to synthesize
1328 constants that can be done in two insns. */
1329 if (arm_tune_xscale)
1330 arm_constant_limit = 2;
1332 /* StrongARM has early execution of branches, so a sequence
1333 that is worth skipping is shorter. */
1334 if (arm_tune_strongarm)
1335 max_insns_skipped = 3;
1338 /* Register global variables with the garbage collector. */
1339 arm_add_gc_roots ();
1343 arm_add_gc_roots (void)
1345 gcc_obstack_init(&minipool_obstack);
1346 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1349 /* A table of known ARM exception types.
1350 For use with the interrupt function attribute. */
1354 const char *const arg;
1355 const unsigned long return_value;
1359 static const isr_attribute_arg isr_attribute_args [] =
1361 { "IRQ", ARM_FT_ISR },
1362 { "irq", ARM_FT_ISR },
1363 { "FIQ", ARM_FT_FIQ },
1364 { "fiq", ARM_FT_FIQ },
1365 { "ABORT", ARM_FT_ISR },
1366 { "abort", ARM_FT_ISR },
1367 { "ABORT", ARM_FT_ISR },
1368 { "abort", ARM_FT_ISR },
1369 { "UNDEF", ARM_FT_EXCEPTION },
1370 { "undef", ARM_FT_EXCEPTION },
1371 { "SWI", ARM_FT_EXCEPTION },
1372 { "swi", ARM_FT_EXCEPTION },
1373 { NULL, ARM_FT_NORMAL }
1376 /* Returns the (interrupt) function type of the current
1377 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1379 static unsigned long
1380 arm_isr_value (tree argument)
1382 const isr_attribute_arg * ptr;
1385 /* No argument - default to IRQ. */
1386 if (argument == NULL_TREE)
1389 /* Get the value of the argument. */
1390 if (TREE_VALUE (argument) == NULL_TREE
1391 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1392 return ARM_FT_UNKNOWN;
1394 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1396 /* Check it against the list of known arguments. */
1397 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1398 if (streq (arg, ptr->arg))
1399 return ptr->return_value;
1401 /* An unrecognized interrupt type. */
1402 return ARM_FT_UNKNOWN;
1405 /* Computes the type of the current function. */
1407 static unsigned long
1408 arm_compute_func_type (void)
1410 unsigned long type = ARM_FT_UNKNOWN;
1414 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1416 /* Decide if the current function is volatile. Such functions
1417 never return, and many memory cycles can be saved by not storing
1418 register values that will never be needed again. This optimization
1419 was added to speed up context switching in a kernel application. */
1421 && (TREE_NOTHROW (current_function_decl)
1422 || !(flag_unwind_tables
1423 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
1424 && TREE_THIS_VOLATILE (current_function_decl))
1425 type |= ARM_FT_VOLATILE;
1427 if (cfun->static_chain_decl != NULL)
1428 type |= ARM_FT_NESTED;
1430 attr = DECL_ATTRIBUTES (current_function_decl);
1432 a = lookup_attribute ("naked", attr);
1434 type |= ARM_FT_NAKED;
1436 a = lookup_attribute ("isr", attr);
1438 a = lookup_attribute ("interrupt", attr);
1441 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1443 type |= arm_isr_value (TREE_VALUE (a));
1448 /* Returns the type of the current function. */
1451 arm_current_func_type (void)
1453 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1454 cfun->machine->func_type = arm_compute_func_type ();
1456 return cfun->machine->func_type;
1459 /* Return 1 if it is possible to return using a single instruction.
1460 If SIBLING is non-null, this is a test for a return before a sibling
1461 call. SIBLING is the call insn, so we can examine its register usage. */
1464 use_return_insn (int iscond, rtx sibling)
1467 unsigned int func_type;
1468 unsigned long saved_int_regs;
1469 unsigned HOST_WIDE_INT stack_adjust;
1470 arm_stack_offsets *offsets;
1472 /* Never use a return instruction before reload has run. */
1473 if (!reload_completed)
1476 func_type = arm_current_func_type ();
1478 /* Naked functions and volatile functions need special
1480 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1483 /* So do interrupt functions that use the frame pointer. */
1484 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1487 offsets = arm_get_frame_offsets ();
1488 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1490 /* As do variadic functions. */
1491 if (current_function_pretend_args_size
1492 || cfun->machine->uses_anonymous_args
1493 /* Or if the function calls __builtin_eh_return () */
1494 || current_function_calls_eh_return
1495 /* Or if the function calls alloca */
1496 || current_function_calls_alloca
1497 /* Or if there is a stack adjustment. However, if the stack pointer
1498 is saved on the stack, we can use a pre-incrementing stack load. */
1499 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1502 saved_int_regs = arm_compute_save_reg_mask ();
1504 /* Unfortunately, the insn
1506 ldmib sp, {..., sp, ...}
1508 triggers a bug on most SA-110 based devices, such that the stack
1509 pointer won't be correctly restored if the instruction takes a
1510 page fault. We work around this problem by popping r3 along with
1511 the other registers, since that is never slower than executing
1512 another instruction.
1514 We test for !arm_arch5 here, because code for any architecture
1515 less than this could potentially be run on one of the buggy
1517 if (stack_adjust == 4 && !arm_arch5)
1519 /* Validate that r3 is a call-clobbered register (always true in
1520 the default abi) ... */
1521 if (!call_used_regs[3])
1524 /* ... that it isn't being used for a return value ... */
1525 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1528 /* ... or for a tail-call argument ... */
1531 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1533 if (find_regno_fusage (sibling, USE, 3))
1537 /* ... and that there are no call-saved registers in r0-r2
1538 (always true in the default ABI). */
1539 if (saved_int_regs & 0x7)
1543 /* Can't be done if interworking with Thumb, and any registers have been
1545 if (TARGET_INTERWORK && saved_int_regs != 0)
1548 /* On StrongARM, conditional returns are expensive if they aren't
1549 taken and multiple registers have been stacked. */
1550 if (iscond && arm_tune_strongarm)
1552 /* Conditional return when just the LR is stored is a simple
1553 conditional-load instruction, that's not expensive. */
1554 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1558 && arm_pic_register != INVALID_REGNUM
1559 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1563 /* If there are saved registers but the LR isn't saved, then we need
1564 two instructions for the return. */
1565 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1568 /* Can't be done if any of the FPA regs are pushed,
1569 since this also requires an insn. */
1570 if (TARGET_HARD_FLOAT && TARGET_FPA)
1571 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1572 if (regs_ever_live[regno] && !call_used_regs[regno])
1575 /* Likewise VFP regs. */
1576 if (TARGET_HARD_FLOAT && TARGET_VFP)
1577 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1578 if (regs_ever_live[regno] && !call_used_regs[regno])
1581 if (TARGET_REALLY_IWMMXT)
1582 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1583 if (regs_ever_live[regno] && ! call_used_regs [regno])
1589 /* Return TRUE if int I is a valid immediate ARM constant. */
1592 const_ok_for_arm (HOST_WIDE_INT i)
1596 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1597 be all zero, or all one. */
1598 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1599 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1600 != ((~(unsigned HOST_WIDE_INT) 0)
1601 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1604 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1606 /* Fast return for 0 and small values. We must do this for zero, since
1607 the code below can't handle that one case. */
1608 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1611 /* Get the number of trailing zeros, rounded down to the nearest even
1613 lowbit = (ffs ((int) i) - 1) & ~1;
1615 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1617 else if (lowbit <= 4
1618 && ((i & ~0xc000003f) == 0
1619 || (i & ~0xf000000f) == 0
1620 || (i & ~0xfc000003) == 0))
1626 /* Return true if I is a valid constant for the operation CODE. */
1628 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1630 if (const_ok_for_arm (i))
1636 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1638 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1644 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1651 /* Emit a sequence of insns to handle a large constant.
1652 CODE is the code of the operation required, it can be any of SET, PLUS,
1653 IOR, AND, XOR, MINUS;
1654 MODE is the mode in which the operation is being performed;
1655 VAL is the integer to operate on;
1656 SOURCE is the other operand (a register, or a null-pointer for SET);
1657 SUBTARGETS means it is safe to create scratch registers if that will
1658 either produce a simpler sequence, or we will want to cse the values.
1659 Return value is the number of insns emitted. */
1662 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1663 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1667 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1668 cond = COND_EXEC_TEST (PATTERN (insn));
1672 if (subtargets || code == SET
1673 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1674 && REGNO (target) != REGNO (source)))
1676 /* After arm_reorg has been called, we can't fix up expensive
1677 constants by pushing them into memory so we must synthesize
1678 them in-line, regardless of the cost. This is only likely to
1679 be more costly on chips that have load delay slots and we are
1680 compiling without running the scheduler (so no splitting
1681 occurred before the final instruction emission).
1683 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1685 if (!after_arm_reorg
1687 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1689 > arm_constant_limit + (code != SET)))
1693 /* Currently SET is the only monadic value for CODE, all
1694 the rest are diadic. */
1695 emit_set_insn (target, GEN_INT (val));
1700 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1702 emit_set_insn (temp, GEN_INT (val));
1703 /* For MINUS, the value is subtracted from, since we never
1704 have subtraction of a constant. */
1706 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
1708 emit_set_insn (target,
1709 gen_rtx_fmt_ee (code, mode, source, temp));
1715 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1720 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1722 HOST_WIDE_INT temp1;
1730 if (remainder & (3 << (i - 2)))
1735 temp1 = remainder & ((0x0ff << end)
1736 | ((i < end) ? (0xff >> (32 - end)) : 0));
1737 remainder &= ~temp1;
1742 } while (remainder);
1746 /* Emit an instruction with the indicated PATTERN. If COND is
1747 non-NULL, conditionalize the execution of the instruction on COND
1751 emit_constant_insn (rtx cond, rtx pattern)
1754 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1755 emit_insn (pattern);
1758 /* As above, but extra parameter GENERATE which, if clear, suppresses
1762 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1763 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1768 int can_negate_initial = 0;
1771 int num_bits_set = 0;
1772 int set_sign_bit_copies = 0;
1773 int clear_sign_bit_copies = 0;
1774 int clear_zero_bit_copies = 0;
1775 int set_zero_bit_copies = 0;
1777 unsigned HOST_WIDE_INT temp1, temp2;
1778 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1780 /* Find out which operations are safe for a given CODE. Also do a quick
1781 check for degenerate cases; these can occur when DImode operations
1793 can_negate_initial = 1;
1797 if (remainder == 0xffffffff)
1800 emit_constant_insn (cond,
1801 gen_rtx_SET (VOIDmode, target,
1802 GEN_INT (ARM_SIGN_EXTEND (val))));
1807 if (reload_completed && rtx_equal_p (target, source))
1810 emit_constant_insn (cond,
1811 gen_rtx_SET (VOIDmode, target, source));
1820 emit_constant_insn (cond,
1821 gen_rtx_SET (VOIDmode, target, const0_rtx));
1824 if (remainder == 0xffffffff)
1826 if (reload_completed && rtx_equal_p (target, source))
1829 emit_constant_insn (cond,
1830 gen_rtx_SET (VOIDmode, target, source));
1839 if (reload_completed && rtx_equal_p (target, source))
1842 emit_constant_insn (cond,
1843 gen_rtx_SET (VOIDmode, target, source));
1847 /* We don't know how to handle other cases yet. */
1848 gcc_assert (remainder == 0xffffffff);
1851 emit_constant_insn (cond,
1852 gen_rtx_SET (VOIDmode, target,
1853 gen_rtx_NOT (mode, source)));
1857 /* We treat MINUS as (val - source), since (source - val) is always
1858 passed as (source + (-val)). */
1862 emit_constant_insn (cond,
1863 gen_rtx_SET (VOIDmode, target,
1864 gen_rtx_NEG (mode, source)));
1867 if (const_ok_for_arm (val))
1870 emit_constant_insn (cond,
1871 gen_rtx_SET (VOIDmode, target,
1872 gen_rtx_MINUS (mode, GEN_INT (val),
1884 /* If we can do it in one insn get out quickly. */
1885 if (const_ok_for_arm (val)
1886 || (can_negate_initial && const_ok_for_arm (-val))
1887 || (can_invert && const_ok_for_arm (~val)))
1890 emit_constant_insn (cond,
1891 gen_rtx_SET (VOIDmode, target,
1893 ? gen_rtx_fmt_ee (code, mode, source,
1899 /* Calculate a few attributes that may be useful for specific
1901 for (i = 31; i >= 0; i--)
1903 if ((remainder & (1 << i)) == 0)
1904 clear_sign_bit_copies++;
1909 for (i = 31; i >= 0; i--)
1911 if ((remainder & (1 << i)) != 0)
1912 set_sign_bit_copies++;
1917 for (i = 0; i <= 31; i++)
1919 if ((remainder & (1 << i)) == 0)
1920 clear_zero_bit_copies++;
1925 for (i = 0; i <= 31; i++)
1927 if ((remainder & (1 << i)) != 0)
1928 set_zero_bit_copies++;
1936 /* See if we can do this by sign_extending a constant that is known
1937 to be negative. This is a good, way of doing it, since the shift
1938 may well merge into a subsequent insn. */
1939 if (set_sign_bit_copies > 1)
1941 if (const_ok_for_arm
1942 (temp1 = ARM_SIGN_EXTEND (remainder
1943 << (set_sign_bit_copies - 1))))
1947 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1948 emit_constant_insn (cond,
1949 gen_rtx_SET (VOIDmode, new_src,
1951 emit_constant_insn (cond,
1952 gen_ashrsi3 (target, new_src,
1953 GEN_INT (set_sign_bit_copies - 1)));
1957 /* For an inverted constant, we will need to set the low bits,
1958 these will be shifted out of harm's way. */
1959 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1960 if (const_ok_for_arm (~temp1))
1964 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1965 emit_constant_insn (cond,
1966 gen_rtx_SET (VOIDmode, new_src,
1968 emit_constant_insn (cond,
1969 gen_ashrsi3 (target, new_src,
1970 GEN_INT (set_sign_bit_copies - 1)));
1976 /* See if we can calculate the value as the difference between two
1977 valid immediates. */
1978 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
1980 int topshift = clear_sign_bit_copies & ~1;
1982 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
1983 & (0xff000000 >> topshift));
1985 /* If temp1 is zero, then that means the 9 most significant
1986 bits of remainder were 1 and we've caused it to overflow.
1987 When topshift is 0 we don't need to do anything since we
1988 can borrow from 'bit 32'. */
1989 if (temp1 == 0 && topshift != 0)
1990 temp1 = 0x80000000 >> (topshift - 1);
1992 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
1994 if (const_ok_for_arm (temp2))
1998 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1999 emit_constant_insn (cond,
2000 gen_rtx_SET (VOIDmode, new_src,
2002 emit_constant_insn (cond,
2003 gen_addsi3 (target, new_src,
2011 /* See if we can generate this by setting the bottom (or the top)
2012 16 bits, and then shifting these into the other half of the
2013 word. We only look for the simplest cases, to do more would cost
2014 too much. Be careful, however, not to generate this when the
2015 alternative would take fewer insns. */
2016 if (val & 0xffff0000)
2018 temp1 = remainder & 0xffff0000;
2019 temp2 = remainder & 0x0000ffff;
2021 /* Overlaps outside this range are best done using other methods. */
2022 for (i = 9; i < 24; i++)
2024 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
2025 && !const_ok_for_arm (temp2))
2027 rtx new_src = (subtargets
2028 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2030 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
2031 source, subtargets, generate);
2039 gen_rtx_ASHIFT (mode, source,
2046 /* Don't duplicate cases already considered. */
2047 for (i = 17; i < 24; i++)
2049 if (((temp1 | (temp1 >> i)) == remainder)
2050 && !const_ok_for_arm (temp1))
2052 rtx new_src = (subtargets
2053 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2055 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
2056 source, subtargets, generate);
2061 gen_rtx_SET (VOIDmode, target,
2064 gen_rtx_LSHIFTRT (mode, source,
2075 /* If we have IOR or XOR, and the constant can be loaded in a
2076 single instruction, and we can find a temporary to put it in,
2077 then this can be done in two instructions instead of 3-4. */
2079 /* TARGET can't be NULL if SUBTARGETS is 0 */
2080 || (reload_completed && !reg_mentioned_p (target, source)))
2082 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2086 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2088 emit_constant_insn (cond,
2089 gen_rtx_SET (VOIDmode, sub,
2091 emit_constant_insn (cond,
2092 gen_rtx_SET (VOIDmode, target,
2093 gen_rtx_fmt_ee (code, mode,
2103 if (set_sign_bit_copies > 8
2104 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2108 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2109 rtx shift = GEN_INT (set_sign_bit_copies);
2113 gen_rtx_SET (VOIDmode, sub,
2115 gen_rtx_ASHIFT (mode,
2120 gen_rtx_SET (VOIDmode, target,
2122 gen_rtx_LSHIFTRT (mode, sub,
2128 if (set_zero_bit_copies > 8
2129 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2133 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2134 rtx shift = GEN_INT (set_zero_bit_copies);
2138 gen_rtx_SET (VOIDmode, sub,
2140 gen_rtx_LSHIFTRT (mode,
2145 gen_rtx_SET (VOIDmode, target,
2147 gen_rtx_ASHIFT (mode, sub,
2153 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2157 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2158 emit_constant_insn (cond,
2159 gen_rtx_SET (VOIDmode, sub,
2160 gen_rtx_NOT (mode, source)));
2163 sub = gen_reg_rtx (mode);
2164 emit_constant_insn (cond,
2165 gen_rtx_SET (VOIDmode, sub,
2166 gen_rtx_AND (mode, source,
2168 emit_constant_insn (cond,
2169 gen_rtx_SET (VOIDmode, target,
2170 gen_rtx_NOT (mode, sub)));
2177 /* See if two shifts will do 2 or more insn's worth of work. */
2178 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2180 HOST_WIDE_INT shift_mask = ((0xffffffff
2181 << (32 - clear_sign_bit_copies))
2184 if ((remainder | shift_mask) != 0xffffffff)
2188 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2189 insns = arm_gen_constant (AND, mode, cond,
2190 remainder | shift_mask,
2191 new_src, source, subtargets, 1);
2196 rtx targ = subtargets ? NULL_RTX : target;
2197 insns = arm_gen_constant (AND, mode, cond,
2198 remainder | shift_mask,
2199 targ, source, subtargets, 0);
2205 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2206 rtx shift = GEN_INT (clear_sign_bit_copies);
2208 emit_insn (gen_ashlsi3 (new_src, source, shift));
2209 emit_insn (gen_lshrsi3 (target, new_src, shift));
2215 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2217 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2219 if ((remainder | shift_mask) != 0xffffffff)
2223 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2225 insns = arm_gen_constant (AND, mode, cond,
2226 remainder | shift_mask,
2227 new_src, source, subtargets, 1);
2232 rtx targ = subtargets ? NULL_RTX : target;
2234 insns = arm_gen_constant (AND, mode, cond,
2235 remainder | shift_mask,
2236 targ, source, subtargets, 0);
2242 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2243 rtx shift = GEN_INT (clear_zero_bit_copies);
2245 emit_insn (gen_lshrsi3 (new_src, source, shift));
2246 emit_insn (gen_ashlsi3 (target, new_src, shift));
2258 for (i = 0; i < 32; i++)
2259 if (remainder & (1 << i))
2262 if (code == AND || (can_invert && num_bits_set > 16))
2263 remainder = (~remainder) & 0xffffffff;
2264 else if (code == PLUS && num_bits_set > 16)
2265 remainder = (-remainder) & 0xffffffff;
2272 /* Now try and find a way of doing the job in either two or three
2274 We start by looking for the largest block of zeros that are aligned on
2275 a 2-bit boundary, we then fill up the temps, wrapping around to the
2276 top of the word when we drop off the bottom.
2277 In the worst case this code should produce no more than four insns. */
2280 int best_consecutive_zeros = 0;
2282 for (i = 0; i < 32; i += 2)
2284 int consecutive_zeros = 0;
2286 if (!(remainder & (3 << i)))
2288 while ((i < 32) && !(remainder & (3 << i)))
2290 consecutive_zeros += 2;
2293 if (consecutive_zeros > best_consecutive_zeros)
2295 best_consecutive_zeros = consecutive_zeros;
2296 best_start = i - consecutive_zeros;
2302 /* So long as it won't require any more insns to do so, it's
2303 desirable to emit a small constant (in bits 0...9) in the last
2304 insn. This way there is more chance that it can be combined with
2305 a later addressing insn to form a pre-indexed load or store
2306 operation. Consider:
2308 *((volatile int *)0xe0000100) = 1;
2309 *((volatile int *)0xe0000110) = 2;
2311 We want this to wind up as:
2315 str rB, [rA, #0x100]
2317 str rB, [rA, #0x110]
2319 rather than having to synthesize both large constants from scratch.
2321 Therefore, we calculate how many insns would be required to emit
2322 the constant starting from `best_start', and also starting from
2323 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2324 yield a shorter sequence, we may as well use zero. */
2326 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2327 && (count_insns_for_constant (remainder, 0) <=
2328 count_insns_for_constant (remainder, best_start)))
2331 /* Now start emitting the insns. */
2339 if (remainder & (3 << (i - 2)))
2344 temp1 = remainder & ((0x0ff << end)
2345 | ((i < end) ? (0xff >> (32 - end)) : 0));
2346 remainder &= ~temp1;
2350 rtx new_src, temp1_rtx;
2352 if (code == SET || code == MINUS)
2354 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2355 if (can_invert && code != MINUS)
2360 if (remainder && subtargets)
2361 new_src = gen_reg_rtx (mode);
2366 else if (can_negate)
2370 temp1 = trunc_int_for_mode (temp1, mode);
2371 temp1_rtx = GEN_INT (temp1);
2375 else if (code == MINUS)
2376 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2378 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2380 emit_constant_insn (cond,
2381 gen_rtx_SET (VOIDmode, new_src,
2391 else if (code == MINUS)
2405 /* Canonicalize a comparison so that we are more likely to recognize it.
2406 This can be done for a few constant compares, where we can make the
2407 immediate value easier to load. */
2410 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2413 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2414 unsigned HOST_WIDE_INT maxval;
2415 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2426 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2428 *op1 = GEN_INT (i + 1);
2429 return code == GT ? GE : LT;
2436 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2438 *op1 = GEN_INT (i - 1);
2439 return code == GE ? GT : LE;
2445 if (i != ~((unsigned HOST_WIDE_INT) 0)
2446 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2448 *op1 = GEN_INT (i + 1);
2449 return code == GTU ? GEU : LTU;
2456 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2458 *op1 = GEN_INT (i - 1);
2459 return code == GEU ? GTU : LEU;
2471 /* Define how to find the value returned by a function. */
2474 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2476 enum machine_mode mode;
2477 int unsignedp ATTRIBUTE_UNUSED;
2478 rtx r ATTRIBUTE_UNUSED;
2480 mode = TYPE_MODE (type);
2481 /* Promote integer types. */
2482 if (INTEGRAL_TYPE_P (type))
2483 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2485 /* Promotes small structs returned in a register to full-word size
2486 for big-endian AAPCS. */
2487 if (arm_return_in_msb (type))
2489 HOST_WIDE_INT size = int_size_in_bytes (type);
2490 if (size % UNITS_PER_WORD != 0)
2492 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2493 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2497 return LIBCALL_VALUE(mode);
2500 /* Determine the amount of memory needed to store the possible return
2501 registers of an untyped call. */
2503 arm_apply_result_size (void)
2509 if (TARGET_HARD_FLOAT_ABI)
2513 if (TARGET_MAVERICK)
2516 if (TARGET_IWMMXT_ABI)
2523 /* Decide whether a type should be returned in memory (true)
2524 or in a register (false). This is called by the macro
2525 RETURN_IN_MEMORY. */
2527 arm_return_in_memory (tree type)
2531 if (!AGGREGATE_TYPE_P (type) &&
2532 (TREE_CODE (type) != VECTOR_TYPE) &&
2533 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2534 /* All simple types are returned in registers.
2535 For AAPCS, complex types are treated the same as aggregates. */
2538 size = int_size_in_bytes (type);
2540 if (arm_abi != ARM_ABI_APCS)
2542 /* ATPCS and later return aggregate types in memory only if they are
2543 larger than a word (or are variable size). */
2544 return (size < 0 || size > UNITS_PER_WORD);
2547 /* To maximize backwards compatibility with previous versions of gcc,
2548 return vectors up to 4 words in registers. */
2549 if (TREE_CODE (type) == VECTOR_TYPE)
2550 return (size < 0 || size > (4 * UNITS_PER_WORD));
2552 /* For the arm-wince targets we choose to be compatible with Microsoft's
2553 ARM and Thumb compilers, which always return aggregates in memory. */
2555 /* All structures/unions bigger than one word are returned in memory.
2556 Also catch the case where int_size_in_bytes returns -1. In this case
2557 the aggregate is either huge or of variable size, and in either case
2558 we will want to return it via memory and not in a register. */
2559 if (size < 0 || size > UNITS_PER_WORD)
2562 if (TREE_CODE (type) == RECORD_TYPE)
2566 /* For a struct the APCS says that we only return in a register
2567 if the type is 'integer like' and every addressable element
2568 has an offset of zero. For practical purposes this means
2569 that the structure can have at most one non bit-field element
2570 and that this element must be the first one in the structure. */
2572 /* Find the first field, ignoring non FIELD_DECL things which will
2573 have been created by C++. */
2574 for (field = TYPE_FIELDS (type);
2575 field && TREE_CODE (field) != FIELD_DECL;
2576 field = TREE_CHAIN (field))
2580 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2582 /* Check that the first field is valid for returning in a register. */
2584 /* ... Floats are not allowed */
2585 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2588 /* ... Aggregates that are not themselves valid for returning in
2589 a register are not allowed. */
2590 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2593 /* Now check the remaining fields, if any. Only bitfields are allowed,
2594 since they are not addressable. */
2595 for (field = TREE_CHAIN (field);
2597 field = TREE_CHAIN (field))
2599 if (TREE_CODE (field) != FIELD_DECL)
2602 if (!DECL_BIT_FIELD_TYPE (field))
2609 if (TREE_CODE (type) == UNION_TYPE)
2613 /* Unions can be returned in registers if every element is
2614 integral, or can be returned in an integer register. */
2615 for (field = TYPE_FIELDS (type);
2617 field = TREE_CHAIN (field))
2619 if (TREE_CODE (field) != FIELD_DECL)
2622 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2625 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2631 #endif /* not ARM_WINCE */
2633 /* Return all other types in memory. */
2637 /* Indicate whether or not words of a double are in big-endian order. */
2640 arm_float_words_big_endian (void)
2642 if (TARGET_MAVERICK)
2645 /* For FPA, float words are always big-endian. For VFP, floats words
2646 follow the memory system mode. */
2654 return (TARGET_BIG_END ? 1 : 0);
2659 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2660 for a call to a function whose data type is FNTYPE.
2661 For a library call, FNTYPE is NULL. */
2663 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2664 rtx libname ATTRIBUTE_UNUSED,
2665 tree fndecl ATTRIBUTE_UNUSED)
2667 /* On the ARM, the offset starts at 0. */
2669 pcum->iwmmxt_nregs = 0;
2670 pcum->can_split = true;
2672 pcum->call_cookie = CALL_NORMAL;
2674 if (TARGET_LONG_CALLS)
2675 pcum->call_cookie = CALL_LONG;
2677 /* Check for long call/short call attributes. The attributes
2678 override any command line option. */
2681 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2682 pcum->call_cookie = CALL_SHORT;
2683 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2684 pcum->call_cookie = CALL_LONG;
2687 /* Varargs vectors are treated the same as long long.
2688 named_count avoids having to change the way arm handles 'named' */
2689 pcum->named_count = 0;
2692 if (TARGET_REALLY_IWMMXT && fntype)
2696 for (fn_arg = TYPE_ARG_TYPES (fntype);
2698 fn_arg = TREE_CHAIN (fn_arg))
2699 pcum->named_count += 1;
2701 if (! pcum->named_count)
2702 pcum->named_count = INT_MAX;
2707 /* Return true if mode/type need doubleword alignment. */
2709 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2711 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2712 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2716 /* Determine where to put an argument to a function.
2717 Value is zero to push the argument on the stack,
2718 or a hard register in which to store the argument.
2720 MODE is the argument's machine mode.
2721 TYPE is the data type of the argument (as a tree).
2722 This is null for libcalls where that information may
2724 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2725 the preceding args and about the function being called.
2726 NAMED is nonzero if this argument is a named parameter
2727 (otherwise it is an extra parameter matching an ellipsis). */
2730 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2731 tree type, int named)
2735 /* Varargs vectors are treated the same as long long.
2736 named_count avoids having to change the way arm handles 'named' */
2737 if (TARGET_IWMMXT_ABI
2738 && arm_vector_mode_supported_p (mode)
2739 && pcum->named_count > pcum->nargs + 1)
2741 if (pcum->iwmmxt_nregs <= 9)
2742 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2745 pcum->can_split = false;
2750 /* Put doubleword aligned quantities in even register pairs. */
2752 && ARM_DOUBLEWORD_ALIGN
2753 && arm_needs_doubleword_align (mode, type))
2756 if (mode == VOIDmode)
2757 /* Compute operand 2 of the call insn. */
2758 return GEN_INT (pcum->call_cookie);
2760 /* Only allow splitting an arg between regs and memory if all preceding
2761 args were allocated to regs. For args passed by reference we only count
2762 the reference pointer. */
2763 if (pcum->can_split)
2766 nregs = ARM_NUM_REGS2 (mode, type);
2768 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2771 return gen_rtx_REG (mode, pcum->nregs);
2775 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2776 tree type, bool named ATTRIBUTE_UNUSED)
2778 int nregs = pcum->nregs;
2780 if (arm_vector_mode_supported_p (mode))
2783 if (NUM_ARG_REGS > nregs
2784 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2786 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
2791 /* Variable sized types are passed by reference. This is a GCC
2792 extension to the ARM ABI. */
2795 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2796 enum machine_mode mode ATTRIBUTE_UNUSED,
2797 tree type, bool named ATTRIBUTE_UNUSED)
2799 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2802 /* Encode the current state of the #pragma [no_]long_calls. */
2805 OFF, /* No #pragma [no_]long_calls is in effect. */
2806 LONG, /* #pragma long_calls is in effect. */
2807 SHORT /* #pragma no_long_calls is in effect. */
2810 static arm_pragma_enum arm_pragma_long_calls = OFF;
2813 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2815 arm_pragma_long_calls = LONG;
2819 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2821 arm_pragma_long_calls = SHORT;
2825 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2827 arm_pragma_long_calls = OFF;
2830 /* Table of machine attributes. */
2831 const struct attribute_spec arm_attribute_table[] =
2833 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2834 /* Function calls made to this symbol must be done indirectly, because
2835 it may lie outside of the 26 bit addressing range of a normal function
2837 { "long_call", 0, 0, false, true, true, NULL },
2838 /* Whereas these functions are always known to reside within the 26 bit
2839 addressing range. */
2840 { "short_call", 0, 0, false, true, true, NULL },
2841 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2842 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2843 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2844 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2846 /* ARM/PE has three new attributes:
2848 dllexport - for exporting a function/variable that will live in a dll
2849 dllimport - for importing a function/variable from a dll
2851 Microsoft allows multiple declspecs in one __declspec, separating
2852 them with spaces. We do NOT support this. Instead, use __declspec
2855 { "dllimport", 0, 0, true, false, false, NULL },
2856 { "dllexport", 0, 0, true, false, false, NULL },
2857 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2858 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2859 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2860 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2861 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
2863 { NULL, 0, 0, false, false, false, NULL }
2866 /* Handle an attribute requiring a FUNCTION_DECL;
2867 arguments as in struct attribute_spec.handler. */
2869 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2870 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2872 if (TREE_CODE (*node) != FUNCTION_DECL)
2874 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2875 IDENTIFIER_POINTER (name));
2876 *no_add_attrs = true;
2882 /* Handle an "interrupt" or "isr" attribute;
2883 arguments as in struct attribute_spec.handler. */
2885 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2890 if (TREE_CODE (*node) != FUNCTION_DECL)
2892 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2893 IDENTIFIER_POINTER (name));
2894 *no_add_attrs = true;
2896 /* FIXME: the argument if any is checked for type attributes;
2897 should it be checked for decl ones? */
2901 if (TREE_CODE (*node) == FUNCTION_TYPE
2902 || TREE_CODE (*node) == METHOD_TYPE)
2904 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2906 warning (OPT_Wattributes, "%qs attribute ignored",
2907 IDENTIFIER_POINTER (name));
2908 *no_add_attrs = true;
2911 else if (TREE_CODE (*node) == POINTER_TYPE
2912 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2913 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2914 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2916 *node = build_variant_type_copy (*node);
2917 TREE_TYPE (*node) = build_type_attribute_variant
2919 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2920 *no_add_attrs = true;
2924 /* Possibly pass this attribute on from the type to a decl. */
2925 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2926 | (int) ATTR_FLAG_FUNCTION_NEXT
2927 | (int) ATTR_FLAG_ARRAY_NEXT))
2929 *no_add_attrs = true;
2930 return tree_cons (name, args, NULL_TREE);
2934 warning (OPT_Wattributes, "%qs attribute ignored",
2935 IDENTIFIER_POINTER (name));
2943 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
2944 /* Handle the "notshared" attribute. This attribute is another way of
2945 requesting hidden visibility. ARM's compiler supports
2946 "__declspec(notshared)"; we support the same thing via an
2950 arm_handle_notshared_attribute (tree *node,
2951 tree name ATTRIBUTE_UNUSED,
2952 tree args ATTRIBUTE_UNUSED,
2953 int flags ATTRIBUTE_UNUSED,
2956 tree decl = TYPE_NAME (*node);
2960 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
2961 DECL_VISIBILITY_SPECIFIED (decl) = 1;
2962 *no_add_attrs = false;
2968 /* Return 0 if the attributes for two types are incompatible, 1 if they
2969 are compatible, and 2 if they are nearly compatible (which causes a
2970 warning to be generated). */
2972 arm_comp_type_attributes (tree type1, tree type2)
2976 /* Check for mismatch of non-default calling convention. */
2977 if (TREE_CODE (type1) != FUNCTION_TYPE)
2980 /* Check for mismatched call attributes. */
2981 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2982 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2983 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2984 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2986 /* Only bother to check if an attribute is defined. */
2987 if (l1 | l2 | s1 | s2)
2989 /* If one type has an attribute, the other must have the same attribute. */
2990 if ((l1 != l2) || (s1 != s2))
2993 /* Disallow mixed attributes. */
2994 if ((l1 & s2) || (l2 & s1))
2998 /* Check for mismatched ISR attribute. */
2999 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3001 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3002 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3004 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3011 /* Encode long_call or short_call attribute by prefixing
3012 symbol name in DECL with a special character FLAG. */
3014 arm_encode_call_attribute (tree decl, int flag)
3016 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3017 int len = strlen (str);
3020 /* Do not allow weak functions to be treated as short call. */
3021 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
3024 newstr = alloca (len + 2);
3026 strcpy (newstr + 1, str);
3028 newstr = (char *) ggc_alloc_string (newstr, len + 1);
3029 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3032 /* Assigns default attributes to newly defined type. This is used to
3033 set short_call/long_call attributes for function types of
3034 functions defined inside corresponding #pragma scopes. */
3036 arm_set_default_type_attributes (tree type)
3038 /* Add __attribute__ ((long_call)) to all functions, when
3039 inside #pragma long_calls or __attribute__ ((short_call)),
3040 when inside #pragma no_long_calls. */
3041 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3043 tree type_attr_list, attr_name;
3044 type_attr_list = TYPE_ATTRIBUTES (type);
3046 if (arm_pragma_long_calls == LONG)
3047 attr_name = get_identifier ("long_call");
3048 else if (arm_pragma_long_calls == SHORT)
3049 attr_name = get_identifier ("short_call");
3053 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3054 TYPE_ATTRIBUTES (type) = type_attr_list;
3058 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
3059 defined within the current compilation unit. If this cannot be
3060 determined, then 0 is returned. */
3062 current_file_function_operand (rtx sym_ref)
3064 /* This is a bit of a fib. A function will have a short call flag
3065 applied to its name if it has the short call attribute, or it has
3066 already been defined within the current compilation unit. */
3067 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
3070 /* The current function is always defined within the current compilation
3071 unit. If it s a weak definition however, then this may not be the real
3072 definition of the function, and so we have to say no. */
3073 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
3074 && !DECL_WEAK (current_function_decl))
3077 /* We cannot make the determination - default to returning 0. */
3081 /* Return nonzero if a 32 bit "long_call" should be generated for
3082 this call. We generate a long_call if the function:
3084 a. has an __attribute__((long call))
3085 or b. is within the scope of a #pragma long_calls
3086 or c. the -mlong-calls command line switch has been specified
3088 1. -ffunction-sections is in effect
3089 or 2. the current function has __attribute__ ((section))
3090 or 3. the target function has __attribute__ ((section))
3092 However we do not generate a long call if the function:
3094 d. has an __attribute__ ((short_call))
3095 or e. is inside the scope of a #pragma no_long_calls
3096 or f. is defined within the current compilation unit.
3098 This function will be called by C fragments contained in the machine
3099 description file. SYM_REF and CALL_COOKIE correspond to the matched
3100 rtl operands. CALL_SYMBOL is used to distinguish between
3101 two different callers of the function. It is set to 1 in the
3102 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
3103 and "call_value" patterns. This is because of the difference in the
3104 SYM_REFs passed by these patterns. */
3106 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
3110 if (GET_CODE (sym_ref) != MEM)
3113 sym_ref = XEXP (sym_ref, 0);
3116 if (GET_CODE (sym_ref) != SYMBOL_REF)
3119 if (call_cookie & CALL_SHORT)
3122 if (TARGET_LONG_CALLS)
3124 if (flag_function_sections
3125 || DECL_SECTION_NAME (current_function_decl))
3126 /* c.3 is handled by the definition of the
3127 ARM_DECLARE_FUNCTION_SIZE macro. */
3131 if (current_file_function_operand (sym_ref))
3134 return (call_cookie & CALL_LONG)
3135 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
3136 || TARGET_LONG_CALLS;
3139 /* Return nonzero if it is ok to make a tail-call to DECL. */
3141 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3143 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
3145 if (cfun->machine->sibcall_blocked)
3148 /* Never tailcall something for which we have no decl, or if we
3149 are in Thumb mode. */
3150 if (decl == NULL || TARGET_THUMB)
3153 /* Get the calling method. */
3154 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3155 call_type = CALL_SHORT;
3156 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
3157 call_type = CALL_LONG;
3159 /* Cannot tail-call to long calls, since these are out of range of
3160 a branch instruction. However, if not compiling PIC, we know
3161 we can reach the symbol if it is in this compilation unit. */
3162 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
3165 /* If we are interworking and the function is not declared static
3166 then we can't tail-call it unless we know that it exists in this
3167 compilation unit (since it might be a Thumb routine). */
3168 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3171 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3172 if (IS_INTERRUPT (arm_current_func_type ()))
3175 /* Everything else is ok. */
3180 /* Addressing mode support functions. */
3182 /* Return nonzero if X is a legitimate immediate operand when compiling
3183 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3185 legitimate_pic_operand_p (rtx x)
3187 if (GET_CODE (x) == SYMBOL_REF
3188 || (GET_CODE (x) == CONST
3189 && GET_CODE (XEXP (x, 0)) == PLUS
3190 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3197 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3199 if (GET_CODE (orig) == SYMBOL_REF
3200 || GET_CODE (orig) == LABEL_REF)
3202 #ifndef AOF_ASSEMBLER
3203 rtx pic_ref, address;
3208 /* If this function doesn't have a pic register, create one now.
3209 A lot of the logic here is made obscure by the fact that this
3210 routine gets called as part of the rtx cost estimation
3211 process. We don't want those calls to affect any assumptions
3212 about the real function; and further, we can't call
3213 entry_of_function() until we start the real expansion
3215 if (!current_function_uses_pic_offset_table)
3217 gcc_assert (!no_new_pseudos);
3218 if (arm_pic_register != INVALID_REGNUM)
3220 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3222 /* Play games to avoid marking the function as needing pic
3223 if we are being called as part of the cost-estimation
3226 current_function_uses_pic_offset_table = 1;
3232 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3234 /* Play games to avoid marking the function as needing pic
3235 if we are being called as part of the cost-estimation
3239 current_function_uses_pic_offset_table = 1;
3242 arm_load_pic_register (0UL);
3246 emit_insn_after (seq, entry_of_function ());
3253 gcc_assert (!no_new_pseudos);
3254 reg = gen_reg_rtx (Pmode);
3259 #ifdef AOF_ASSEMBLER
3260 /* The AOF assembler can generate relocations for these directly, and
3261 understands that the PIC register has to be added into the offset. */
3262 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3265 address = gen_reg_rtx (Pmode);
3270 emit_insn (gen_pic_load_addr_arm (address, orig));
3272 emit_insn (gen_pic_load_addr_thumb (address, orig));
3274 if ((GET_CODE (orig) == LABEL_REF
3275 || (GET_CODE (orig) == SYMBOL_REF &&
3276 SYMBOL_REF_LOCAL_P (orig)))
3278 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
3281 pic_ref = gen_const_mem (Pmode,
3282 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
3286 insn = emit_move_insn (reg, pic_ref);
3288 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3290 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3294 else if (GET_CODE (orig) == CONST)
3298 if (GET_CODE (XEXP (orig, 0)) == PLUS
3299 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
3302 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3303 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3308 gcc_assert (!no_new_pseudos);
3309 reg = gen_reg_rtx (Pmode);
3312 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3314 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3315 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3316 base == reg ? 0 : reg);
3318 if (GET_CODE (offset) == CONST_INT)
3320 /* The base register doesn't really matter, we only want to
3321 test the index for the appropriate mode. */
3322 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3324 gcc_assert (!no_new_pseudos);
3325 offset = force_reg (Pmode, offset);
3328 if (GET_CODE (offset) == CONST_INT)
3329 return plus_constant (base, INTVAL (offset));
3332 if (GET_MODE_SIZE (mode) > 4
3333 && (GET_MODE_CLASS (mode) == MODE_INT
3334 || TARGET_SOFT_FLOAT))
3336 emit_insn (gen_addsi3 (reg, base, offset));
3340 return gen_rtx_PLUS (Pmode, base, offset);
3347 /* Find a spare low register to use during the prolog of a function. */
3350 thumb_find_work_register (unsigned long pushed_regs_mask)
3354 /* Check the argument registers first as these are call-used. The
3355 register allocation order means that sometimes r3 might be used
3356 but earlier argument registers might not, so check them all. */
3357 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3358 if (!regs_ever_live[reg])
3361 /* Before going on to check the call-saved registers we can try a couple
3362 more ways of deducing that r3 is available. The first is when we are
3363 pushing anonymous arguments onto the stack and we have less than 4
3364 registers worth of fixed arguments(*). In this case r3 will be part of
3365 the variable argument list and so we can be sure that it will be
3366 pushed right at the start of the function. Hence it will be available
3367 for the rest of the prologue.
3368 (*): ie current_function_pretend_args_size is greater than 0. */
3369 if (cfun->machine->uses_anonymous_args
3370 && current_function_pretend_args_size > 0)
3371 return LAST_ARG_REGNUM;
3373 /* The other case is when we have fixed arguments but less than 4 registers
3374 worth. In this case r3 might be used in the body of the function, but
3375 it is not being used to convey an argument into the function. In theory
3376 we could just check current_function_args_size to see how many bytes are
3377 being passed in argument registers, but it seems that it is unreliable.
3378 Sometimes it will have the value 0 when in fact arguments are being
3379 passed. (See testcase execute/20021111-1.c for an example). So we also
3380 check the args_info.nregs field as well. The problem with this field is
3381 that it makes no allowances for arguments that are passed to the
3382 function but which are not used. Hence we could miss an opportunity
3383 when a function has an unused argument in r3. But it is better to be
3384 safe than to be sorry. */
3385 if (! cfun->machine->uses_anonymous_args
3386 && current_function_args_size >= 0
3387 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3388 && cfun->args_info.nregs < 4)
3389 return LAST_ARG_REGNUM;
3391 /* Otherwise look for a call-saved register that is going to be pushed. */
3392 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3393 if (pushed_regs_mask & (1 << reg))
3396 /* Something went wrong - thumb_compute_save_reg_mask()
3397 should have arranged for a suitable register to be pushed. */
3401 static GTY(()) int pic_labelno;
3403 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3407 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
3409 #ifndef AOF_ASSEMBLER
3410 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx;
3411 rtx global_offset_table;
3413 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3416 gcc_assert (flag_pic);
3418 /* We use an UNSPEC rather than a LABEL_REF because this label never appears
3419 in the code stream. */
3421 labelno = GEN_INT (pic_labelno++);
3422 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3423 l1 = gen_rtx_CONST (VOIDmode, l1);
3425 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3426 /* On the ARM the PC register contains 'dot + 8' at the time of the
3427 addition, on the Thumb it is 'dot + 4'. */
3428 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3430 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3431 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3433 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3435 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3439 emit_insn (gen_pic_load_addr_arm (cfun->machine->pic_reg, pic_rtx));
3440 emit_insn (gen_pic_add_dot_plus_eight (cfun->machine->pic_reg,
3441 cfun->machine->pic_reg, labelno));
3445 if (arm_pic_register != INVALID_REGNUM
3446 && REGNO (cfun->machine->pic_reg) > LAST_LO_REGNUM)
3448 /* We will have pushed the pic register, so we should always be
3449 able to find a work register. */
3450 pic_tmp = gen_rtx_REG (SImode,
3451 thumb_find_work_register (saved_regs));
3452 emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx));
3453 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3456 emit_insn (gen_pic_load_addr_thumb (cfun->machine->pic_reg, pic_rtx));
3457 emit_insn (gen_pic_add_dot_plus_four (cfun->machine->pic_reg,
3458 cfun->machine->pic_reg, labelno));
3461 /* Need to emit this whether or not we obey regdecls,
3462 since setjmp/longjmp can cause life info to screw up. */
3463 emit_insn (gen_rtx_USE (VOIDmode, cfun->machine->pic_reg));
3464 #endif /* AOF_ASSEMBLER */
3468 /* Return nonzero if X is valid as an ARM state addressing register. */
3470 arm_address_register_rtx_p (rtx x, int strict_p)
3474 if (GET_CODE (x) != REG)
3480 return ARM_REGNO_OK_FOR_BASE_P (regno);
3482 return (regno <= LAST_ARM_REGNUM
3483 || regno >= FIRST_PSEUDO_REGISTER
3484 || regno == FRAME_POINTER_REGNUM
3485 || regno == ARG_POINTER_REGNUM);
3488 /* Return TRUE if this rtx is the difference of a symbol and a label,
3489 and will reduce to a PC-relative relocation in the object file.
3490 Expressions like this can be left alone when generating PIC, rather
3491 than forced through the GOT. */
3493 pcrel_constant_p (rtx x)
3495 if (GET_CODE (x) == MINUS)
3496 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3501 /* Return nonzero if X is a valid ARM state address operand. */
3503 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3507 enum rtx_code code = GET_CODE (x);
3509 if (arm_address_register_rtx_p (x, strict_p))
3512 use_ldrd = (TARGET_LDRD
3514 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3516 if (code == POST_INC || code == PRE_DEC
3517 || ((code == PRE_INC || code == POST_DEC)
3518 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3519 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3521 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3522 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3523 && GET_CODE (XEXP (x, 1)) == PLUS
3524 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3526 rtx addend = XEXP (XEXP (x, 1), 1);
3528 /* Don't allow ldrd post increment by register because it's hard
3529 to fixup invalid register choices. */
3531 && GET_CODE (x) == POST_MODIFY
3532 && GET_CODE (addend) == REG)
3535 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3536 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3539 /* After reload constants split into minipools will have addresses
3540 from a LABEL_REF. */
3541 else if (reload_completed
3542 && (code == LABEL_REF
3544 && GET_CODE (XEXP (x, 0)) == PLUS
3545 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3546 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3549 else if (mode == TImode)
3552 else if (code == PLUS)
3554 rtx xop0 = XEXP (x, 0);
3555 rtx xop1 = XEXP (x, 1);
3557 return ((arm_address_register_rtx_p (xop0, strict_p)
3558 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3559 || (arm_address_register_rtx_p (xop1, strict_p)
3560 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3564 /* Reload currently can't handle MINUS, so disable this for now */
3565 else if (GET_CODE (x) == MINUS)
3567 rtx xop0 = XEXP (x, 0);
3568 rtx xop1 = XEXP (x, 1);
3570 return (arm_address_register_rtx_p (xop0, strict_p)
3571 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3575 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3576 && code == SYMBOL_REF
3577 && CONSTANT_POOL_ADDRESS_P (x)
3579 && symbol_mentioned_p (get_pool_constant (x))
3580 && ! pcrel_constant_p (get_pool_constant (x))))
3586 /* Return nonzero if INDEX is valid for an address index operand in
3589 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3592 HOST_WIDE_INT range;
3593 enum rtx_code code = GET_CODE (index);
3595 /* Standard coprocessor addressing modes. */
3596 if (TARGET_HARD_FLOAT
3597 && (TARGET_FPA || TARGET_MAVERICK)
3598 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3599 || (TARGET_MAVERICK && mode == DImode)))
3600 return (code == CONST_INT && INTVAL (index) < 1024
3601 && INTVAL (index) > -1024
3602 && (INTVAL (index) & 3) == 0);
3604 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3606 /* For DImode assume values will usually live in core regs
3607 and only allow LDRD addressing modes. */
3608 if (!TARGET_LDRD || mode != DImode)
3609 return (code == CONST_INT
3610 && INTVAL (index) < 1024
3611 && INTVAL (index) > -1024
3612 && (INTVAL (index) & 3) == 0);
3615 if (arm_address_register_rtx_p (index, strict_p)
3616 && (GET_MODE_SIZE (mode) <= 4))
3619 if (mode == DImode || mode == DFmode)
3621 if (code == CONST_INT)
3623 HOST_WIDE_INT val = INTVAL (index);
3626 return val > -256 && val < 256;
3628 return val > -4096 && val < 4092;
3631 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3634 if (GET_MODE_SIZE (mode) <= 4
3637 || (mode == QImode && outer == SIGN_EXTEND))))
3641 rtx xiop0 = XEXP (index, 0);
3642 rtx xiop1 = XEXP (index, 1);
3644 return ((arm_address_register_rtx_p (xiop0, strict_p)
3645 && power_of_two_operand (xiop1, SImode))
3646 || (arm_address_register_rtx_p (xiop1, strict_p)
3647 && power_of_two_operand (xiop0, SImode)));
3649 else if (code == LSHIFTRT || code == ASHIFTRT
3650 || code == ASHIFT || code == ROTATERT)
3652 rtx op = XEXP (index, 1);
3654 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3655 && GET_CODE (op) == CONST_INT
3657 && INTVAL (op) <= 31);
3661 /* For ARM v4 we may be doing a sign-extend operation during the
3665 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3671 range = (mode == HImode) ? 4095 : 4096;
3673 return (code == CONST_INT
3674 && INTVAL (index) < range
3675 && INTVAL (index) > -range);
3678 /* Return nonzero if X is valid as a Thumb state base register. */
3680 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3684 if (GET_CODE (x) != REG)
3690 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3692 return (regno <= LAST_LO_REGNUM
3693 || regno > LAST_VIRTUAL_REGISTER
3694 || regno == FRAME_POINTER_REGNUM
3695 || (GET_MODE_SIZE (mode) >= 4
3696 && (regno == STACK_POINTER_REGNUM
3697 || regno >= FIRST_PSEUDO_REGISTER
3698 || x == hard_frame_pointer_rtx
3699 || x == arg_pointer_rtx)));
3702 /* Return nonzero if x is a legitimate index register. This is the case
3703 for any base register that can access a QImode object. */
3705 thumb_index_register_rtx_p (rtx x, int strict_p)
3707 return thumb_base_register_rtx_p (x, QImode, strict_p);
3710 /* Return nonzero if x is a legitimate Thumb-state address.
3712 The AP may be eliminated to either the SP or the FP, so we use the
3713 least common denominator, e.g. SImode, and offsets from 0 to 64.
3715 ??? Verify whether the above is the right approach.
3717 ??? Also, the FP may be eliminated to the SP, so perhaps that
3718 needs special handling also.
3720 ??? Look at how the mips16 port solves this problem. It probably uses
3721 better ways to solve some of these problems.
3723 Although it is not incorrect, we don't accept QImode and HImode
3724 addresses based on the frame pointer or arg pointer until the
3725 reload pass starts. This is so that eliminating such addresses
3726 into stack based ones won't produce impossible code. */
3728 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3730 /* ??? Not clear if this is right. Experiment. */
3731 if (GET_MODE_SIZE (mode) < 4
3732 && !(reload_in_progress || reload_completed)
3733 && (reg_mentioned_p (frame_pointer_rtx, x)
3734 || reg_mentioned_p (arg_pointer_rtx, x)
3735 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3736 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3737 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3738 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3741 /* Accept any base register. SP only in SImode or larger. */
3742 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3745 /* This is PC relative data before arm_reorg runs. */
3746 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3747 && GET_CODE (x) == SYMBOL_REF
3748 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
3751 /* This is PC relative data after arm_reorg runs. */
3752 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3753 && (GET_CODE (x) == LABEL_REF
3754 || (GET_CODE (x) == CONST
3755 && GET_CODE (XEXP (x, 0)) == PLUS
3756 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3757 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3760 /* Post-inc indexing only supported for SImode and larger. */
3761 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3762 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3765 else if (GET_CODE (x) == PLUS)
3767 /* REG+REG address can be any two index registers. */
3768 /* We disallow FRAME+REG addressing since we know that FRAME
3769 will be replaced with STACK, and SP relative addressing only
3770 permits SP+OFFSET. */
3771 if (GET_MODE_SIZE (mode) <= 4
3772 && XEXP (x, 0) != frame_pointer_rtx
3773 && XEXP (x, 1) != frame_pointer_rtx
3774 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3775 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3778 /* REG+const has 5-7 bit offset for non-SP registers. */
3779 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3780 || XEXP (x, 0) == arg_pointer_rtx)
3781 && GET_CODE (XEXP (x, 1)) == CONST_INT
3782 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3785 /* REG+const has 10 bit offset for SP, but only SImode and
3786 larger is supported. */
3787 /* ??? Should probably check for DI/DFmode overflow here
3788 just like GO_IF_LEGITIMATE_OFFSET does. */
3789 else if (GET_CODE (XEXP (x, 0)) == REG
3790 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3791 && GET_MODE_SIZE (mode) >= 4
3792 && GET_CODE (XEXP (x, 1)) == CONST_INT
3793 && INTVAL (XEXP (x, 1)) >= 0
3794 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3795 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3798 else if (GET_CODE (XEXP (x, 0)) == REG
3799 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3800 && GET_MODE_SIZE (mode) >= 4
3801 && GET_CODE (XEXP (x, 1)) == CONST_INT
3802 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3806 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3807 && GET_MODE_SIZE (mode) == 4
3808 && GET_CODE (x) == SYMBOL_REF
3809 && CONSTANT_POOL_ADDRESS_P (x)
3811 && symbol_mentioned_p (get_pool_constant (x))
3812 && ! pcrel_constant_p (get_pool_constant (x))))
3818 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3819 instruction of mode MODE. */
3821 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3823 switch (GET_MODE_SIZE (mode))
3826 return val >= 0 && val < 32;
3829 return val >= 0 && val < 64 && (val & 1) == 0;
3833 && (val + GET_MODE_SIZE (mode)) <= 128
3838 /* Build the SYMBOL_REF for __tls_get_addr. */
3840 static GTY(()) rtx tls_get_addr_libfunc;
3843 get_tls_get_addr (void)
3845 if (!tls_get_addr_libfunc)
3846 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
3847 return tls_get_addr_libfunc;
3851 arm_load_tp (rtx target)
3854 target = gen_reg_rtx (SImode);
3858 /* Can return in any reg. */
3859 emit_insn (gen_load_tp_hard (target));
3863 /* Always returned in r0. Immediately copy the result into a pseudo,
3864 otherwise other uses of r0 (e.g. setting up function arguments) may
3865 clobber the value. */
3869 emit_insn (gen_load_tp_soft ());
3871 tmp = gen_rtx_REG (SImode, 0);
3872 emit_move_insn (target, tmp);
3878 load_tls_operand (rtx x, rtx reg)
3882 if (reg == NULL_RTX)
3883 reg = gen_reg_rtx (SImode);
3885 tmp = gen_rtx_CONST (SImode, x);
3887 emit_move_insn (reg, tmp);
3893 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
3895 rtx insns, label, labelno, sum;
3899 labelno = GEN_INT (pic_labelno++);
3900 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3901 label = gen_rtx_CONST (VOIDmode, label);
3903 sum = gen_rtx_UNSPEC (Pmode,
3904 gen_rtvec (4, x, GEN_INT (reloc), label,
3905 GEN_INT (TARGET_ARM ? 8 : 4)),
3907 reg = load_tls_operand (sum, reg);
3910 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
3912 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
3914 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
3915 Pmode, 1, reg, Pmode);
3917 insns = get_insns ();
3924 legitimize_tls_address (rtx x, rtx reg)
3926 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
3927 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
3931 case TLS_MODEL_GLOBAL_DYNAMIC:
3932 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
3933 dest = gen_reg_rtx (Pmode);
3934 emit_libcall_block (insns, dest, ret, x);
3937 case TLS_MODEL_LOCAL_DYNAMIC:
3938 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
3940 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3941 share the LDM result with other LD model accesses. */
3942 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
3944 dest = gen_reg_rtx (Pmode);
3945 emit_libcall_block (insns, dest, ret, eqv);
3947 /* Load the addend. */
3948 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
3950 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
3951 return gen_rtx_PLUS (Pmode, dest, addend);
3953 case TLS_MODEL_INITIAL_EXEC:
3954 labelno = GEN_INT (pic_labelno++);
3955 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3956 label = gen_rtx_CONST (VOIDmode, label);
3957 sum = gen_rtx_UNSPEC (Pmode,
3958 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
3959 GEN_INT (TARGET_ARM ? 8 : 4)),
3961 reg = load_tls_operand (sum, reg);
3964 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
3967 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
3968 emit_move_insn (reg, gen_const_mem (SImode, reg));
3971 tp = arm_load_tp (NULL_RTX);
3973 return gen_rtx_PLUS (Pmode, tp, reg);
3975 case TLS_MODEL_LOCAL_EXEC:
3976 tp = arm_load_tp (NULL_RTX);
3978 reg = gen_rtx_UNSPEC (Pmode,
3979 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
3981 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
3983 return gen_rtx_PLUS (Pmode, tp, reg);
3990 /* Try machine-dependent ways of modifying an illegitimate address
3991 to be legitimate. If we find one, return the new, valid address. */
3993 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3995 if (arm_tls_symbol_p (x))
3996 return legitimize_tls_address (x, NULL_RTX);
3998 if (GET_CODE (x) == PLUS)
4000 rtx xop0 = XEXP (x, 0);
4001 rtx xop1 = XEXP (x, 1);
4003 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4004 xop0 = force_reg (SImode, xop0);
4006 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4007 xop1 = force_reg (SImode, xop1);
4009 if (ARM_BASE_REGISTER_RTX_P (xop0)
4010 && GET_CODE (xop1) == CONST_INT)
4012 HOST_WIDE_INT n, low_n;
4016 /* VFP addressing modes actually allow greater offsets, but for
4017 now we just stick with the lowest common denominator. */
4019 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
4031 low_n = ((mode) == TImode ? 0
4032 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4036 base_reg = gen_reg_rtx (SImode);
4037 val = force_operand (plus_constant (xop0, n), NULL_RTX);
4038 emit_move_insn (base_reg, val);
4039 x = plus_constant (base_reg, low_n);
4041 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4042 x = gen_rtx_PLUS (SImode, xop0, xop1);
4045 /* XXX We don't allow MINUS any more -- see comment in
4046 arm_legitimate_address_p (). */
4047 else if (GET_CODE (x) == MINUS)
4049 rtx xop0 = XEXP (x, 0);
4050 rtx xop1 = XEXP (x, 1);
4052 if (CONSTANT_P (xop0))
4053 xop0 = force_reg (SImode, xop0);
4055 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4056 xop1 = force_reg (SImode, xop1);
4058 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4059 x = gen_rtx_MINUS (SImode, xop0, xop1);
4062 /* Make sure to take full advantage of the pre-indexed addressing mode
4063 with absolute addresses which often allows for the base register to
4064 be factorized for multiple adjacent memory references, and it might
4065 even allows for the mini pool to be avoided entirely. */
4066 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4069 HOST_WIDE_INT mask, base, index;
4072 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
4073 use a 8 bit index. So let's use a 12 bit index for SImode only and
4074 hope that arm_gen_constant will enable ldrb to use more bits. */
4075 bits = (mode == SImode) ? 12 : 8;
4076 mask = (1 << bits) - 1;
4077 base = INTVAL (x) & ~mask;
4078 index = INTVAL (x) & mask;
4079 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
4081 /* It'll most probably be more efficient to generate the base
4082 with more bits set and use a negative index instead. */
4086 base_reg = force_reg (SImode, GEN_INT (base));
4087 x = plus_constant (base_reg, index);
4092 /* We need to find and carefully transform any SYMBOL and LABEL
4093 references; so go back to the original address expression. */
4094 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4096 if (new_x != orig_x)
4104 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4105 to be legitimate. If we find one, return the new, valid address. */
4107 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4109 if (arm_tls_symbol_p (x))
4110 return legitimize_tls_address (x, NULL_RTX);
4112 if (GET_CODE (x) == PLUS
4113 && GET_CODE (XEXP (x, 1)) == CONST_INT
4114 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
4115 || INTVAL (XEXP (x, 1)) < 0))
4117 rtx xop0 = XEXP (x, 0);
4118 rtx xop1 = XEXP (x, 1);
4119 HOST_WIDE_INT offset = INTVAL (xop1);
4121 /* Try and fold the offset into a biasing of the base register and
4122 then offsetting that. Don't do this when optimizing for space
4123 since it can cause too many CSEs. */
4124 if (optimize_size && offset >= 0
4125 && offset < 256 + 31 * GET_MODE_SIZE (mode))
4127 HOST_WIDE_INT delta;
4130 delta = offset - (256 - GET_MODE_SIZE (mode));
4131 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4132 delta = 31 * GET_MODE_SIZE (mode);
4134 delta = offset & (~31 * GET_MODE_SIZE (mode));
4136 xop0 = force_operand (plus_constant (xop0, offset - delta),
4138 x = plus_constant (xop0, delta);
4140 else if (offset < 0 && offset > -256)
4141 /* Small negative offsets are best done with a subtract before the
4142 dereference, forcing these into a register normally takes two
4144 x = force_operand (x, NULL_RTX);
4147 /* For the remaining cases, force the constant into a register. */
4148 xop1 = force_reg (SImode, xop1);
4149 x = gen_rtx_PLUS (SImode, xop0, xop1);
4152 else if (GET_CODE (x) == PLUS
4153 && s_register_operand (XEXP (x, 1), SImode)
4154 && !s_register_operand (XEXP (x, 0), SImode))
4156 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
4158 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
4163 /* We need to find and carefully transform any SYMBOL and LABEL
4164 references; so go back to the original address expression. */
4165 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4167 if (new_x != orig_x)
4175 thumb_legitimize_reload_address (rtx *x_p,
4176 enum machine_mode mode,
4177 int opnum, int type,
4178 int ind_levels ATTRIBUTE_UNUSED)
4182 if (GET_CODE (x) == PLUS
4183 && GET_MODE_SIZE (mode) < 4
4184 && REG_P (XEXP (x, 0))
4185 && XEXP (x, 0) == stack_pointer_rtx
4186 && GET_CODE (XEXP (x, 1)) == CONST_INT
4187 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4192 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4193 Pmode, VOIDmode, 0, 0, opnum, type);
4197 /* If both registers are hi-regs, then it's better to reload the
4198 entire expression rather than each register individually. That
4199 only requires one reload register rather than two. */
4200 if (GET_CODE (x) == PLUS
4201 && REG_P (XEXP (x, 0))
4202 && REG_P (XEXP (x, 1))
4203 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
4204 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
4209 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4210 Pmode, VOIDmode, 0, 0, opnum, type);
4217 /* Test for various thread-local symbols. */
4219 /* Return TRUE if X is a thread-local symbol. */
4222 arm_tls_symbol_p (rtx x)
4224 if (! TARGET_HAVE_TLS)
4227 if (GET_CODE (x) != SYMBOL_REF)
4230 return SYMBOL_REF_TLS_MODEL (x) != 0;
4233 /* Helper for arm_tls_referenced_p. */
4236 arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4238 if (GET_CODE (*x) == SYMBOL_REF)
4239 return SYMBOL_REF_TLS_MODEL (*x) != 0;
4241 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4242 TLS offsets, not real symbol references. */
4243 if (GET_CODE (*x) == UNSPEC
4244 && XINT (*x, 1) == UNSPEC_TLS)
4250 /* Return TRUE if X contains any TLS symbol references. */
4253 arm_tls_referenced_p (rtx x)
4255 if (! TARGET_HAVE_TLS)
4258 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
4261 #define REG_OR_SUBREG_REG(X) \
4262 (GET_CODE (X) == REG \
4263 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4265 #define REG_OR_SUBREG_RTX(X) \
4266 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4268 #ifndef COSTS_N_INSNS
4269 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4272 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
4274 enum machine_mode mode = GET_MODE (x);
4287 return COSTS_N_INSNS (1);
4290 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4293 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
4300 return COSTS_N_INSNS (2) + cycles;
4302 return COSTS_N_INSNS (1) + 16;
4305 return (COSTS_N_INSNS (1)
4306 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
4307 + GET_CODE (SET_DEST (x)) == MEM));
4312 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
4314 if (thumb_shiftable_const (INTVAL (x)))
4315 return COSTS_N_INSNS (2);
4316 return COSTS_N_INSNS (3);
4318 else if ((outer == PLUS || outer == COMPARE)
4319 && INTVAL (x) < 256 && INTVAL (x) > -256)
4321 else if (outer == AND
4322 && INTVAL (x) < 256 && INTVAL (x) >= -256)
4323 return COSTS_N_INSNS (1);
4324 else if (outer == ASHIFT || outer == ASHIFTRT
4325 || outer == LSHIFTRT)
4327 return COSTS_N_INSNS (2);
4333 return COSTS_N_INSNS (3);
4351 /* XXX another guess. */
4352 /* Memory costs quite a lot for the first word, but subsequent words
4353 load at the equivalent of a single insn each. */
4354 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4355 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4360 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4365 /* XXX still guessing. */
4366 switch (GET_MODE (XEXP (x, 0)))
4369 return (1 + (mode == DImode ? 4 : 0)
4370 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4373 return (4 + (mode == DImode ? 4 : 0)
4374 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4377 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4389 /* Worker routine for arm_rtx_costs. */
4391 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4393 enum machine_mode mode = GET_MODE (x);
4394 enum rtx_code subcode;
4400 /* Memory costs quite a lot for the first word, but subsequent words
4401 load at the equivalent of a single insn each. */
4402 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4403 + (GET_CODE (x) == SYMBOL_REF
4404 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4410 return optimize_size ? COSTS_N_INSNS (2) : 100;
4413 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4420 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4422 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4423 + ((GET_CODE (XEXP (x, 0)) == REG
4424 || (GET_CODE (XEXP (x, 0)) == SUBREG
4425 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4427 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4428 || (GET_CODE (XEXP (x, 0)) == SUBREG
4429 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4431 + ((GET_CODE (XEXP (x, 1)) == REG
4432 || (GET_CODE (XEXP (x, 1)) == SUBREG
4433 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4434 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4439 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4440 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4441 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4442 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4445 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4446 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4447 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4448 && arm_const_double_rtx (XEXP (x, 1))))
4450 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4451 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4452 && arm_const_double_rtx (XEXP (x, 0))))
4455 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4456 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4457 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4458 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4459 || subcode == ASHIFTRT || subcode == LSHIFTRT
4460 || subcode == ROTATE || subcode == ROTATERT
4462 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4463 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4464 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4465 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4466 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4467 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4468 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4473 if (GET_CODE (XEXP (x, 0)) == MULT)
4475 extra_cost = rtx_cost (XEXP (x, 0), code);
4476 if (!REG_OR_SUBREG_REG (XEXP (x, 1)))
4477 extra_cost += 4 * ARM_NUM_REGS (mode);
4481 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4482 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4483 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4484 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4485 && arm_const_double_rtx (XEXP (x, 1))))
4489 case AND: case XOR: case IOR:
4492 /* Normally the frame registers will be spilt into reg+const during
4493 reload, so it is a bad idea to combine them with other instructions,
4494 since then they might not be moved outside of loops. As a compromise
4495 we allow integration with ops that have a constant as their second
4497 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4498 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4499 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4500 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4501 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4505 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4506 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4507 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4508 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4511 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4512 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4513 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4514 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4515 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4518 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4519 return (1 + extra_cost
4520 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4521 || subcode == LSHIFTRT || subcode == ASHIFTRT
4522 || subcode == ROTATE || subcode == ROTATERT
4524 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4525 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4526 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4527 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4528 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4529 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4535 /* This should have been handled by the CPU specific routines. */
4539 if (arm_arch3m && mode == SImode
4540 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4541 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4542 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4543 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4544 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4545 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4550 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4551 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4555 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4557 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4560 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4568 return 4 + (mode == DImode ? 4 : 0);
4571 if (GET_MODE (XEXP (x, 0)) == QImode)
4572 return (4 + (mode == DImode ? 4 : 0)
4573 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4576 switch (GET_MODE (XEXP (x, 0)))
4579 return (1 + (mode == DImode ? 4 : 0)
4580 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4583 return (4 + (mode == DImode ? 4 : 0)
4584 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4587 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4602 if (const_ok_for_arm (INTVAL (x)))
4603 return outer == SET ? 2 : -1;
4604 else if (outer == AND
4605 && const_ok_for_arm (~INTVAL (x)))
4607 else if ((outer == COMPARE
4608 || outer == PLUS || outer == MINUS)
4609 && const_ok_for_arm (-INTVAL (x)))
4620 if (arm_const_double_rtx (x))
4621 return outer == SET ? 2 : -1;
4622 else if ((outer == COMPARE || outer == PLUS)
4623 && neg_const_double_rtx_ok_for_fpa (x))
4632 /* RTX costs when optimizing for size. */
4634 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
4636 enum machine_mode mode = GET_MODE (x);
4640 /* XXX TBD. For now, use the standard costs. */
4641 *total = thumb_rtx_costs (x, code, outer_code);
4648 /* A memory access costs 1 insn if the mode is small, or the address is
4649 a single register, otherwise it costs one insn per word. */
4650 if (REG_P (XEXP (x, 0)))
4651 *total = COSTS_N_INSNS (1);
4653 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4660 /* Needs a libcall, so it costs about this. */
4661 *total = COSTS_N_INSNS (2);
4665 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4667 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
4675 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
4677 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
4680 else if (mode == SImode)
4682 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
4683 /* Slightly disparage register shifts, but not by much. */
4684 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4685 *total += 1 + rtx_cost (XEXP (x, 1), code);
4689 /* Needs a libcall. */
4690 *total = COSTS_N_INSNS (2);
4694 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4696 *total = COSTS_N_INSNS (1);
4702 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
4703 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
4705 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
4706 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
4707 || subcode1 == ROTATE || subcode1 == ROTATERT
4708 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
4709 || subcode1 == ASHIFTRT)
4711 /* It's just the cost of the two operands. */
4716 *total = COSTS_N_INSNS (1);
4720 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4724 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4726 *total = COSTS_N_INSNS (1);
4731 case AND: case XOR: case IOR:
4734 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
4736 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
4737 || subcode == LSHIFTRT || subcode == ASHIFTRT
4738 || (code == AND && subcode == NOT))
4740 /* It's just the cost of the two operands. */
4746 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4750 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4754 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4755 *total = COSTS_N_INSNS (1);
4758 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4767 if (cc_register (XEXP (x, 0), VOIDmode))
4770 *total = COSTS_N_INSNS (1);
4774 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4775 *total = COSTS_N_INSNS (1);
4777 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
4782 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
4784 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4785 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4788 *total += COSTS_N_INSNS (1);
4793 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4795 switch (GET_MODE (XEXP (x, 0)))
4798 *total += COSTS_N_INSNS (1);
4802 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4808 *total += COSTS_N_INSNS (2);
4813 *total += COSTS_N_INSNS (1);
4818 if (const_ok_for_arm (INTVAL (x)))
4819 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
4820 else if (const_ok_for_arm (~INTVAL (x)))
4821 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
4822 else if (const_ok_for_arm (-INTVAL (x)))
4824 if (outer_code == COMPARE || outer_code == PLUS
4825 || outer_code == MINUS)
4828 *total = COSTS_N_INSNS (1);
4831 *total = COSTS_N_INSNS (2);
4837 *total = COSTS_N_INSNS (2);
4841 *total = COSTS_N_INSNS (4);
4845 if (mode != VOIDmode)
4846 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4848 *total = COSTS_N_INSNS (4); /* How knows? */
4853 /* RTX costs for cores with a slow MUL implementation. */
4856 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4858 enum machine_mode mode = GET_MODE (x);
4862 *total = thumb_rtx_costs (x, code, outer_code);
4869 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4876 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4878 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4879 & (unsigned HOST_WIDE_INT) 0xffffffff);
4880 int cost, const_ok = const_ok_for_arm (i);
4881 int j, booth_unit_size;
4883 /* Tune as appropriate. */
4884 cost = const_ok ? 4 : 8;
4885 booth_unit_size = 2;
4886 for (j = 0; i && j < 32; j += booth_unit_size)
4888 i >>= booth_unit_size;
4896 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4897 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4901 *total = arm_rtx_costs_1 (x, code, outer_code);
4907 /* RTX cost for cores with a fast multiply unit (M variants). */
4910 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4912 enum machine_mode mode = GET_MODE (x);
4916 *total = thumb_rtx_costs (x, code, outer_code);
4923 /* There is no point basing this on the tuning, since it is always the
4924 fast variant if it exists at all. */
4926 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4927 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4928 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4935 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4942 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4944 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4945 & (unsigned HOST_WIDE_INT) 0xffffffff);
4946 int cost, const_ok = const_ok_for_arm (i);
4947 int j, booth_unit_size;
4949 /* Tune as appropriate. */
4950 cost = const_ok ? 4 : 8;
4951 booth_unit_size = 8;
4952 for (j = 0; i && j < 32; j += booth_unit_size)
4954 i >>= booth_unit_size;
4962 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4963 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4967 *total = arm_rtx_costs_1 (x, code, outer_code);
4973 /* RTX cost for XScale CPUs. */
4976 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
4978 enum machine_mode mode = GET_MODE (x);
4982 *total = thumb_rtx_costs (x, code, outer_code);
4989 /* There is no point basing this on the tuning, since it is always the
4990 fast variant if it exists at all. */
4992 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4993 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4994 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5001 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5008 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5010 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5011 & (unsigned HOST_WIDE_INT) 0xffffffff);
5012 int cost, const_ok = const_ok_for_arm (i);
5013 unsigned HOST_WIDE_INT masked_const;
5015 /* The cost will be related to two insns.
5016 First a load of the constant (MOV or LDR), then a multiply. */
5019 cost += 1; /* LDR is probably more expensive because
5020 of longer result latency. */
5021 masked_const = i & 0xffff8000;
5022 if (masked_const != 0 && masked_const != 0xffff8000)
5024 masked_const = i & 0xf8000000;
5025 if (masked_const == 0 || masked_const == 0xf8000000)
5034 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5035 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5039 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5040 will stall until the multiplication is complete. */
5041 if (GET_CODE (XEXP (x, 0)) == MULT)
5042 *total = 4 + rtx_cost (XEXP (x, 0), code);
5044 *total = arm_rtx_costs_1 (x, code, outer_code);
5048 *total = arm_rtx_costs_1 (x, code, outer_code);
5054 /* RTX costs for 9e (and later) cores. */
5057 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
5059 enum machine_mode mode = GET_MODE (x);
5068 *total = COSTS_N_INSNS (3);
5072 *total = thumb_rtx_costs (x, code, outer_code);
5080 /* There is no point basing this on the tuning, since it is always the
5081 fast variant if it exists at all. */
5083 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5084 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5085 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5092 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5109 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
5110 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
5114 *total = arm_rtx_costs_1 (x, code, outer_code);
5118 /* All address computations that can be done are free, but rtx cost returns
5119 the same for practically all of them. So we weight the different types
5120 of address here in the order (most pref first):
5121 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5123 arm_arm_address_cost (rtx x)
5125 enum rtx_code c = GET_CODE (x);
5127 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
5129 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
5132 if (c == PLUS || c == MINUS)
5134 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5137 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
5147 arm_thumb_address_cost (rtx x)
5149 enum rtx_code c = GET_CODE (x);
5154 && GET_CODE (XEXP (x, 0)) == REG
5155 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5162 arm_address_cost (rtx x)
5164 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
5168 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
5172 /* Some true dependencies can have a higher cost depending
5173 on precisely how certain input operands are used. */
5175 && REG_NOTE_KIND (link) == 0
5176 && recog_memoized (insn) >= 0
5177 && recog_memoized (dep) >= 0)
5179 int shift_opnum = get_attr_shift (insn);
5180 enum attr_type attr_type = get_attr_type (dep);
5182 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5183 operand for INSN. If we have a shifted input operand and the
5184 instruction we depend on is another ALU instruction, then we may
5185 have to account for an additional stall. */
5186 if (shift_opnum != 0
5187 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
5189 rtx shifted_operand;
5192 /* Get the shifted operand. */
5193 extract_insn (insn);
5194 shifted_operand = recog_data.operand[shift_opnum];
5196 /* Iterate over all the operands in DEP. If we write an operand
5197 that overlaps with SHIFTED_OPERAND, then we have increase the
5198 cost of this dependency. */
5200 preprocess_constraints ();
5201 for (opno = 0; opno < recog_data.n_operands; opno++)
5203 /* We can ignore strict inputs. */
5204 if (recog_data.operand_type[opno] == OP_IN)
5207 if (reg_overlap_mentioned_p (recog_data.operand[opno],
5214 /* XXX This is not strictly true for the FPA. */
5215 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
5216 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
5219 /* Call insns don't incur a stall, even if they follow a load. */
5220 if (REG_NOTE_KIND (link) == 0
5221 && GET_CODE (insn) == CALL_INSN)
5224 if ((i_pat = single_set (insn)) != NULL
5225 && GET_CODE (SET_SRC (i_pat)) == MEM
5226 && (d_pat = single_set (dep)) != NULL
5227 && GET_CODE (SET_DEST (d_pat)) == MEM)
5229 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
5230 /* This is a load after a store, there is no conflict if the load reads
5231 from a cached area. Assume that loads from the stack, and from the
5232 constant pool are cached, and that others will miss. This is a
5235 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
5236 || reg_mentioned_p (stack_pointer_rtx, src_mem)
5237 || reg_mentioned_p (frame_pointer_rtx, src_mem)
5238 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
5245 static int fp_consts_inited = 0;
5247 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5248 static const char * const strings_fp[8] =
5251 "4", "5", "0.5", "10"
5254 static REAL_VALUE_TYPE values_fp[8];
5257 init_fp_table (void)
5263 fp_consts_inited = 1;
5265 fp_consts_inited = 8;
5267 for (i = 0; i < fp_consts_inited; i++)
5269 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
5274 /* Return TRUE if rtx X is a valid immediate FP constant. */
5276 arm_const_double_rtx (rtx x)
5281 if (!fp_consts_inited)
5284 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5285 if (REAL_VALUE_MINUS_ZERO (r))
5288 for (i = 0; i < fp_consts_inited; i++)
5289 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5295 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5297 neg_const_double_rtx_ok_for_fpa (rtx x)
5302 if (!fp_consts_inited)
5305 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5306 r = REAL_VALUE_NEGATE (r);
5307 if (REAL_VALUE_MINUS_ZERO (r))
5310 for (i = 0; i < 8; i++)
5311 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5317 /* Predicates for `match_operand' and `match_operator'. */
5319 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5321 cirrus_memory_offset (rtx op)
5323 /* Reject eliminable registers. */
5324 if (! (reload_in_progress || reload_completed)
5325 && ( reg_mentioned_p (frame_pointer_rtx, op)
5326 || reg_mentioned_p (arg_pointer_rtx, op)
5327 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5328 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5329 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5330 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5333 if (GET_CODE (op) == MEM)
5339 /* Match: (mem (reg)). */
5340 if (GET_CODE (ind) == REG)
5346 if (GET_CODE (ind) == PLUS
5347 && GET_CODE (XEXP (ind, 0)) == REG
5348 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5349 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
5356 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5357 WB if true if writeback address modes are allowed. */
5360 arm_coproc_mem_operand (rtx op, bool wb)
5364 /* Reject eliminable registers. */
5365 if (! (reload_in_progress || reload_completed)
5366 && ( reg_mentioned_p (frame_pointer_rtx, op)
5367 || reg_mentioned_p (arg_pointer_rtx, op)
5368 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5369 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5370 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5371 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5374 /* Constants are converted into offsets from labels. */
5375 if (GET_CODE (op) != MEM)
5380 if (reload_completed
5381 && (GET_CODE (ind) == LABEL_REF
5382 || (GET_CODE (ind) == CONST
5383 && GET_CODE (XEXP (ind, 0)) == PLUS
5384 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
5385 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
5388 /* Match: (mem (reg)). */
5389 if (GET_CODE (ind) == REG)
5390 return arm_address_register_rtx_p (ind, 0);
5392 /* Autoincremment addressing modes. */
5394 && (GET_CODE (ind) == PRE_INC
5395 || GET_CODE (ind) == POST_INC
5396 || GET_CODE (ind) == PRE_DEC
5397 || GET_CODE (ind) == POST_DEC))
5398 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
5401 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
5402 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
5403 && GET_CODE (XEXP (ind, 1)) == PLUS
5404 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
5405 ind = XEXP (ind, 1);
5410 if (GET_CODE (ind) == PLUS
5411 && GET_CODE (XEXP (ind, 0)) == REG
5412 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5413 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5414 && INTVAL (XEXP (ind, 1)) > -1024
5415 && INTVAL (XEXP (ind, 1)) < 1024
5416 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5422 /* Return true if X is a register that will be eliminated later on. */
5424 arm_eliminable_register (rtx x)
5426 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5427 || REGNO (x) == ARG_POINTER_REGNUM
5428 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5429 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5432 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5433 coprocessor registers. Otherwise return NO_REGS. */
5436 coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
5438 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
5441 return GENERAL_REGS;
5444 /* Values which must be returned in the most-significant end of the return
5448 arm_return_in_msb (tree valtype)
5450 return (TARGET_AAPCS_BASED
5452 && (AGGREGATE_TYPE_P (valtype)
5453 || TREE_CODE (valtype) == COMPLEX_TYPE));
5456 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5457 Use by the Cirrus Maverick code which has to workaround
5458 a hardware bug triggered by such instructions. */
5460 arm_memory_load_p (rtx insn)
5462 rtx body, lhs, rhs;;
5464 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
5467 body = PATTERN (insn);
5469 if (GET_CODE (body) != SET)
5472 lhs = XEXP (body, 0);
5473 rhs = XEXP (body, 1);
5475 lhs = REG_OR_SUBREG_RTX (lhs);
5477 /* If the destination is not a general purpose
5478 register we do not have to worry. */
5479 if (GET_CODE (lhs) != REG
5480 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
5483 /* As well as loads from memory we also have to react
5484 to loads of invalid constants which will be turned
5485 into loads from the minipool. */
5486 return (GET_CODE (rhs) == MEM
5487 || GET_CODE (rhs) == SYMBOL_REF
5488 || note_invalid_constants (insn, -1, false));
5491 /* Return TRUE if INSN is a Cirrus instruction. */
5493 arm_cirrus_insn_p (rtx insn)
5495 enum attr_cirrus attr;
5497 /* get_attr cannot accept USE or CLOBBER. */
5499 || GET_CODE (insn) != INSN
5500 || GET_CODE (PATTERN (insn)) == USE
5501 || GET_CODE (PATTERN (insn)) == CLOBBER)
5504 attr = get_attr_cirrus (insn);
5506 return attr != CIRRUS_NOT;
5509 /* Cirrus reorg for invalid instruction combinations. */
5511 cirrus_reorg (rtx first)
5513 enum attr_cirrus attr;
5514 rtx body = PATTERN (first);
5518 /* Any branch must be followed by 2 non Cirrus instructions. */
5519 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
5522 t = next_nonnote_insn (first);
5524 if (arm_cirrus_insn_p (t))
5527 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5531 emit_insn_after (gen_nop (), first);
5536 /* (float (blah)) is in parallel with a clobber. */
5537 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5538 body = XVECEXP (body, 0, 0);
5540 if (GET_CODE (body) == SET)
5542 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
5544 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5545 be followed by a non Cirrus insn. */
5546 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
5548 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
5549 emit_insn_after (gen_nop (), first);
5553 else if (arm_memory_load_p (first))
5555 unsigned int arm_regno;
5557 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5558 ldr/cfmv64hr combination where the Rd field is the same
5559 in both instructions must be split with a non Cirrus
5566 /* Get Arm register number for ldr insn. */
5567 if (GET_CODE (lhs) == REG)
5568 arm_regno = REGNO (lhs);
5571 gcc_assert (GET_CODE (rhs) == REG);
5572 arm_regno = REGNO (rhs);
5576 first = next_nonnote_insn (first);
5578 if (! arm_cirrus_insn_p (first))
5581 body = PATTERN (first);
5583 /* (float (blah)) is in parallel with a clobber. */
5584 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
5585 body = XVECEXP (body, 0, 0);
5587 if (GET_CODE (body) == FLOAT)
5588 body = XEXP (body, 0);
5590 if (get_attr_cirrus (first) == CIRRUS_MOVE
5591 && GET_CODE (XEXP (body, 1)) == REG
5592 && arm_regno == REGNO (XEXP (body, 1)))
5593 emit_insn_after (gen_nop (), first);
5599 /* get_attr cannot accept USE or CLOBBER. */
5601 || GET_CODE (first) != INSN
5602 || GET_CODE (PATTERN (first)) == USE
5603 || GET_CODE (PATTERN (first)) == CLOBBER)
5606 attr = get_attr_cirrus (first);
5608 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5609 must be followed by a non-coprocessor instruction. */
5610 if (attr == CIRRUS_COMPARE)
5614 t = next_nonnote_insn (first);
5616 if (arm_cirrus_insn_p (t))
5619 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5623 emit_insn_after (gen_nop (), first);
5629 /* Return TRUE if X references a SYMBOL_REF. */
5631 symbol_mentioned_p (rtx x)
5636 if (GET_CODE (x) == SYMBOL_REF)
5639 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
5640 are constant offsets, not symbols. */
5641 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
5644 fmt = GET_RTX_FORMAT (GET_CODE (x));
5646 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5652 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5653 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5656 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5663 /* Return TRUE if X references a LABEL_REF. */
5665 label_mentioned_p (rtx x)
5670 if (GET_CODE (x) == LABEL_REF)
5673 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
5674 instruction, but they are constant offsets, not symbols. */
5675 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
5678 fmt = GET_RTX_FORMAT (GET_CODE (x));
5679 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5685 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5686 if (label_mentioned_p (XVECEXP (x, i, j)))
5689 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5697 tls_mentioned_p (rtx x)
5699 switch (GET_CODE (x))
5702 return tls_mentioned_p (XEXP (x, 0));
5705 if (XINT (x, 1) == UNSPEC_TLS)
5713 /* Must not copy a SET whose source operand is PC-relative. */
5716 arm_cannot_copy_insn_p (rtx insn)
5718 rtx pat = PATTERN (insn);
5720 if (GET_CODE (pat) == PARALLEL
5721 && GET_CODE (XVECEXP (pat, 0, 0)) == SET)
5723 rtx rhs = SET_SRC (XVECEXP (pat, 0, 0));
5725 if (GET_CODE (rhs) == UNSPEC
5726 && XINT (rhs, 1) == UNSPEC_PIC_BASE)
5729 if (GET_CODE (rhs) == MEM
5730 && GET_CODE (XEXP (rhs, 0)) == UNSPEC
5731 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE)
5741 enum rtx_code code = GET_CODE (x);
5758 /* Return 1 if memory locations are adjacent. */
5760 adjacent_mem_locations (rtx a, rtx b)
5762 /* We don't guarantee to preserve the order of these memory refs. */
5763 if (volatile_refs_p (a) || volatile_refs_p (b))
5766 if ((GET_CODE (XEXP (a, 0)) == REG
5767 || (GET_CODE (XEXP (a, 0)) == PLUS
5768 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5769 && (GET_CODE (XEXP (b, 0)) == REG
5770 || (GET_CODE (XEXP (b, 0)) == PLUS
5771 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5773 HOST_WIDE_INT val0 = 0, val1 = 0;
5777 if (GET_CODE (XEXP (a, 0)) == PLUS)
5779 reg0 = XEXP (XEXP (a, 0), 0);
5780 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5785 if (GET_CODE (XEXP (b, 0)) == PLUS)
5787 reg1 = XEXP (XEXP (b, 0), 0);
5788 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5793 /* Don't accept any offset that will require multiple
5794 instructions to handle, since this would cause the
5795 arith_adjacentmem pattern to output an overlong sequence. */
5796 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5799 /* Don't allow an eliminable register: register elimination can make
5800 the offset too large. */
5801 if (arm_eliminable_register (reg0))
5804 val_diff = val1 - val0;
5808 /* If the target has load delay slots, then there's no benefit
5809 to using an ldm instruction unless the offset is zero and
5810 we are optimizing for size. */
5811 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
5812 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
5813 && (val_diff == 4 || val_diff == -4));
5816 return ((REGNO (reg0) == REGNO (reg1))
5817 && (val_diff == 4 || val_diff == -4));
5824 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5825 HOST_WIDE_INT *load_offset)
5827 int unsorted_regs[4];
5828 HOST_WIDE_INT unsorted_offsets[4];
5833 /* Can only handle 2, 3, or 4 insns at present,
5834 though could be easily extended if required. */
5835 gcc_assert (nops >= 2 && nops <= 4);
5837 /* Loop over the operands and check that the memory references are
5838 suitable (i.e. immediate offsets from the same base register). At
5839 the same time, extract the target register, and the memory
5841 for (i = 0; i < nops; i++)
5846 /* Convert a subreg of a mem into the mem itself. */
5847 if (GET_CODE (operands[nops + i]) == SUBREG)
5848 operands[nops + i] = alter_subreg (operands + (nops + i));
5850 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
5852 /* Don't reorder volatile memory references; it doesn't seem worth
5853 looking for the case where the order is ok anyway. */
5854 if (MEM_VOLATILE_P (operands[nops + i]))
5857 offset = const0_rtx;
5859 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5860 || (GET_CODE (reg) == SUBREG
5861 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5862 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5863 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5865 || (GET_CODE (reg) == SUBREG
5866 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5867 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5872 base_reg = REGNO (reg);
5873 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5874 ? REGNO (operands[i])
5875 : REGNO (SUBREG_REG (operands[i])));
5880 if (base_reg != (int) REGNO (reg))
5881 /* Not addressed from the same base register. */
5884 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5885 ? REGNO (operands[i])
5886 : REGNO (SUBREG_REG (operands[i])));
5887 if (unsorted_regs[i] < unsorted_regs[order[0]])
5891 /* If it isn't an integer register, or if it overwrites the
5892 base register but isn't the last insn in the list, then
5893 we can't do this. */
5894 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5895 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5898 unsorted_offsets[i] = INTVAL (offset);
5901 /* Not a suitable memory address. */
5905 /* All the useful information has now been extracted from the
5906 operands into unsorted_regs and unsorted_offsets; additionally,
5907 order[0] has been set to the lowest numbered register in the
5908 list. Sort the registers into order, and check that the memory
5909 offsets are ascending and adjacent. */
5911 for (i = 1; i < nops; i++)
5915 order[i] = order[i - 1];
5916 for (j = 0; j < nops; j++)
5917 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5918 && (order[i] == order[i - 1]
5919 || unsorted_regs[j] < unsorted_regs[order[i]]))
5922 /* Have we found a suitable register? if not, one must be used more
5924 if (order[i] == order[i - 1])
5927 /* Is the memory address adjacent and ascending? */
5928 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5936 for (i = 0; i < nops; i++)
5937 regs[i] = unsorted_regs[order[i]];
5939 *load_offset = unsorted_offsets[order[0]];
5942 if (unsorted_offsets[order[0]] == 0)
5943 return 1; /* ldmia */
5945 if (unsorted_offsets[order[0]] == 4)
5946 return 2; /* ldmib */
5948 if (unsorted_offsets[order[nops - 1]] == 0)
5949 return 3; /* ldmda */
5951 if (unsorted_offsets[order[nops - 1]] == -4)
5952 return 4; /* ldmdb */
5954 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5955 if the offset isn't small enough. The reason 2 ldrs are faster
5956 is because these ARMs are able to do more than one cache access
5957 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5958 whilst the ARM8 has a double bandwidth cache. This means that
5959 these cores can do both an instruction fetch and a data fetch in
5960 a single cycle, so the trick of calculating the address into a
5961 scratch register (one of the result regs) and then doing a load
5962 multiple actually becomes slower (and no smaller in code size).
5963 That is the transformation
5965 ldr rd1, [rbase + offset]
5966 ldr rd2, [rbase + offset + 4]
5970 add rd1, rbase, offset
5971 ldmia rd1, {rd1, rd2}
5973 produces worse code -- '3 cycles + any stalls on rd2' instead of
5974 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5975 access per cycle, the first sequence could never complete in less
5976 than 6 cycles, whereas the ldm sequence would only take 5 and
5977 would make better use of sequential accesses if not hitting the
5980 We cheat here and test 'arm_ld_sched' which we currently know to
5981 only be true for the ARM8, ARM9 and StrongARM. If this ever
5982 changes, then the test below needs to be reworked. */
5983 if (nops == 2 && arm_ld_sched)
5986 /* Can't do it without setting up the offset, only do this if it takes
5987 no more than one insn. */
5988 return (const_ok_for_arm (unsorted_offsets[order[0]])
5989 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5993 emit_ldm_seq (rtx *operands, int nops)
5997 HOST_WIDE_INT offset;
6001 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6004 strcpy (buf, "ldm%?ia\t");
6008 strcpy (buf, "ldm%?ib\t");
6012 strcpy (buf, "ldm%?da\t");
6016 strcpy (buf, "ldm%?db\t");
6021 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6022 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6025 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6026 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6028 output_asm_insn (buf, operands);
6030 strcpy (buf, "ldm%?ia\t");
6037 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6038 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6040 for (i = 1; i < nops; i++)
6041 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6042 reg_names[regs[i]]);
6044 strcat (buf, "}\t%@ phole ldm");
6046 output_asm_insn (buf, operands);
6051 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6052 HOST_WIDE_INT * load_offset)
6054 int unsorted_regs[4];
6055 HOST_WIDE_INT unsorted_offsets[4];
6060 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6061 extended if required. */
6062 gcc_assert (nops >= 2 && nops <= 4);
6064 /* Loop over the operands and check that the memory references are
6065 suitable (i.e. immediate offsets from the same base register). At
6066 the same time, extract the target register, and the memory
6068 for (i = 0; i < nops; i++)
6073 /* Convert a subreg of a mem into the mem itself. */
6074 if (GET_CODE (operands[nops + i]) == SUBREG)
6075 operands[nops + i] = alter_subreg (operands + (nops + i));
6077 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6079 /* Don't reorder volatile memory references; it doesn't seem worth
6080 looking for the case where the order is ok anyway. */
6081 if (MEM_VOLATILE_P (operands[nops + i]))
6084 offset = const0_rtx;
6086 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6087 || (GET_CODE (reg) == SUBREG
6088 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6089 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6090 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6092 || (GET_CODE (reg) == SUBREG
6093 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6094 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6099 base_reg = REGNO (reg);
6100 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6101 ? REGNO (operands[i])
6102 : REGNO (SUBREG_REG (operands[i])));
6107 if (base_reg != (int) REGNO (reg))
6108 /* Not addressed from the same base register. */
6111 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6112 ? REGNO (operands[i])
6113 : REGNO (SUBREG_REG (operands[i])));
6114 if (unsorted_regs[i] < unsorted_regs[order[0]])
6118 /* If it isn't an integer register, then we can't do this. */
6119 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
6122 unsorted_offsets[i] = INTVAL (offset);
6125 /* Not a suitable memory address. */
6129 /* All the useful information has now been extracted from the
6130 operands into unsorted_regs and unsorted_offsets; additionally,
6131 order[0] has been set to the lowest numbered register in the
6132 list. Sort the registers into order, and check that the memory
6133 offsets are ascending and adjacent. */
6135 for (i = 1; i < nops; i++)
6139 order[i] = order[i - 1];
6140 for (j = 0; j < nops; j++)
6141 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6142 && (order[i] == order[i - 1]
6143 || unsorted_regs[j] < unsorted_regs[order[i]]))
6146 /* Have we found a suitable register? if not, one must be used more
6148 if (order[i] == order[i - 1])
6151 /* Is the memory address adjacent and ascending? */
6152 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6160 for (i = 0; i < nops; i++)
6161 regs[i] = unsorted_regs[order[i]];
6163 *load_offset = unsorted_offsets[order[0]];
6166 if (unsorted_offsets[order[0]] == 0)
6167 return 1; /* stmia */
6169 if (unsorted_offsets[order[0]] == 4)
6170 return 2; /* stmib */
6172 if (unsorted_offsets[order[nops - 1]] == 0)
6173 return 3; /* stmda */
6175 if (unsorted_offsets[order[nops - 1]] == -4)
6176 return 4; /* stmdb */
6182 emit_stm_seq (rtx *operands, int nops)
6186 HOST_WIDE_INT offset;
6190 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6193 strcpy (buf, "stm%?ia\t");
6197 strcpy (buf, "stm%?ib\t");
6201 strcpy (buf, "stm%?da\t");
6205 strcpy (buf, "stm%?db\t");
6212 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6213 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6215 for (i = 1; i < nops; i++)
6216 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6217 reg_names[regs[i]]);
6219 strcat (buf, "}\t%@ phole stm");
6221 output_asm_insn (buf, operands);
6225 /* Routines for use in generating RTL. */
6228 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
6229 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6231 HOST_WIDE_INT offset = *offsetp;
6234 int sign = up ? 1 : -1;
6237 /* XScale has load-store double instructions, but they have stricter
6238 alignment requirements than load-store multiple, so we cannot
6241 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6242 the pipeline until completion.
6250 An ldr instruction takes 1-3 cycles, but does not block the
6259 Best case ldr will always win. However, the more ldr instructions
6260 we issue, the less likely we are to be able to schedule them well.
6261 Using ldr instructions also increases code size.
6263 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6264 for counts of 3 or 4 regs. */
6265 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6271 for (i = 0; i < count; i++)
6273 addr = plus_constant (from, i * 4 * sign);
6274 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6275 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
6281 emit_move_insn (from, plus_constant (from, count * 4 * sign));
6291 result = gen_rtx_PARALLEL (VOIDmode,
6292 rtvec_alloc (count + (write_back ? 1 : 0)));
6295 XVECEXP (result, 0, 0)
6296 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
6301 for (j = 0; i < count; i++, j++)
6303 addr = plus_constant (from, j * 4 * sign);
6304 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6305 XVECEXP (result, 0, i)
6306 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
6317 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
6318 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6320 HOST_WIDE_INT offset = *offsetp;
6323 int sign = up ? 1 : -1;
6326 /* See arm_gen_load_multiple for discussion of
6327 the pros/cons of ldm/stm usage for XScale. */
6328 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6334 for (i = 0; i < count; i++)
6336 addr = plus_constant (to, i * 4 * sign);
6337 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6338 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
6344 emit_move_insn (to, plus_constant (to, count * 4 * sign));
6354 result = gen_rtx_PARALLEL (VOIDmode,
6355 rtvec_alloc (count + (write_back ? 1 : 0)));
6358 XVECEXP (result, 0, 0)
6359 = gen_rtx_SET (VOIDmode, to,
6360 plus_constant (to, count * 4 * sign));
6365 for (j = 0; i < count; i++, j++)
6367 addr = plus_constant (to, j * 4 * sign);
6368 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6369 XVECEXP (result, 0, i)
6370 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
6381 arm_gen_movmemqi (rtx *operands)
6383 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
6384 HOST_WIDE_INT srcoffset, dstoffset;
6386 rtx src, dst, srcbase, dstbase;
6387 rtx part_bytes_reg = NULL;
6390 if (GET_CODE (operands[2]) != CONST_INT
6391 || GET_CODE (operands[3]) != CONST_INT
6392 || INTVAL (operands[2]) > 64
6393 || INTVAL (operands[3]) & 3)
6396 dstbase = operands[0];
6397 srcbase = operands[1];
6399 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
6400 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
6402 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
6403 out_words_to_go = INTVAL (operands[2]) / 4;
6404 last_bytes = INTVAL (operands[2]) & 3;
6405 dstoffset = srcoffset = 0;
6407 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6408 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6410 for (i = 0; in_words_to_go >= 2; i+=4)
6412 if (in_words_to_go > 4)
6413 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6414 srcbase, &srcoffset));
6416 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6417 FALSE, srcbase, &srcoffset));
6419 if (out_words_to_go)
6421 if (out_words_to_go > 4)
6422 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6423 dstbase, &dstoffset));
6424 else if (out_words_to_go != 1)
6425 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6429 dstbase, &dstoffset));
6432 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6433 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6434 if (last_bytes != 0)
6436 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6442 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6443 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6446 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6447 if (out_words_to_go)
6451 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6452 sreg = copy_to_reg (mem);
6454 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6455 emit_move_insn (mem, sreg);
6458 gcc_assert (!in_words_to_go); /* Sanity check */
6463 gcc_assert (in_words_to_go > 0);
6465 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6466 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6469 gcc_assert (!last_bytes || part_bytes_reg);
6471 if (BYTES_BIG_ENDIAN && last_bytes)
6473 rtx tmp = gen_reg_rtx (SImode);
6475 /* The bytes we want are in the top end of the word. */
6476 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6477 GEN_INT (8 * (4 - last_bytes))));
6478 part_bytes_reg = tmp;
6482 mem = adjust_automodify_address (dstbase, QImode,
6483 plus_constant (dst, last_bytes - 1),
6484 dstoffset + last_bytes - 1);
6485 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6489 tmp = gen_reg_rtx (SImode);
6490 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6491 part_bytes_reg = tmp;
6500 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
6501 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6505 rtx tmp = gen_reg_rtx (SImode);
6506 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6507 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6508 part_bytes_reg = tmp;
6515 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
6516 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6523 /* Select a dominance comparison mode if possible for a test of the general
6524 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6525 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6526 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6527 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6528 In all cases OP will be either EQ or NE, but we don't need to know which
6529 here. If we are unable to support a dominance comparison we return
6530 CC mode. This will then fail to match for the RTL expressions that
6531 generate this call. */
6533 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6535 enum rtx_code cond1, cond2;
6538 /* Currently we will probably get the wrong result if the individual
6539 comparisons are not simple. This also ensures that it is safe to
6540 reverse a comparison if necessary. */
6541 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6543 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6547 /* The if_then_else variant of this tests the second condition if the
6548 first passes, but is true if the first fails. Reverse the first
6549 condition to get a true "inclusive-or" expression. */
6550 if (cond_or == DOM_CC_NX_OR_Y)
6551 cond1 = reverse_condition (cond1);
6553 /* If the comparisons are not equal, and one doesn't dominate the other,
6554 then we can't do this. */
6556 && !comparison_dominates_p (cond1, cond2)
6557 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6562 enum rtx_code temp = cond1;
6570 if (cond_or == DOM_CC_X_AND_Y)
6575 case EQ: return CC_DEQmode;
6576 case LE: return CC_DLEmode;
6577 case LEU: return CC_DLEUmode;
6578 case GE: return CC_DGEmode;
6579 case GEU: return CC_DGEUmode;
6580 default: gcc_unreachable ();
6584 if (cond_or == DOM_CC_X_AND_Y)
6600 if (cond_or == DOM_CC_X_AND_Y)
6616 if (cond_or == DOM_CC_X_AND_Y)
6632 if (cond_or == DOM_CC_X_AND_Y)
6647 /* The remaining cases only occur when both comparisons are the
6650 gcc_assert (cond1 == cond2);
6654 gcc_assert (cond1 == cond2);
6658 gcc_assert (cond1 == cond2);
6662 gcc_assert (cond1 == cond2);
6666 gcc_assert (cond1 == cond2);
6675 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6677 /* All floating point compares return CCFP if it is an equality
6678 comparison, and CCFPE otherwise. */
6679 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6699 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6708 /* A compare with a shifted operand. Because of canonicalization, the
6709 comparison will have to be swapped when we emit the assembler. */
6710 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6711 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6712 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6713 || GET_CODE (x) == ROTATERT))
6716 /* This operation is performed swapped, but since we only rely on the Z
6717 flag we don't need an additional mode. */
6718 if (GET_MODE (y) == SImode && REG_P (y)
6719 && GET_CODE (x) == NEG
6720 && (op == EQ || op == NE))
6723 /* This is a special case that is used by combine to allow a
6724 comparison of a shifted byte load to be split into a zero-extend
6725 followed by a comparison of the shifted integer (only valid for
6726 equalities and unsigned inequalities). */
6727 if (GET_MODE (x) == SImode
6728 && GET_CODE (x) == ASHIFT
6729 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6730 && GET_CODE (XEXP (x, 0)) == SUBREG
6731 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6732 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6733 && (op == EQ || op == NE
6734 || op == GEU || op == GTU || op == LTU || op == LEU)
6735 && GET_CODE (y) == CONST_INT)
6738 /* A construct for a conditional compare, if the false arm contains
6739 0, then both conditions must be true, otherwise either condition
6740 must be true. Not all conditions are possible, so CCmode is
6741 returned if it can't be done. */
6742 if (GET_CODE (x) == IF_THEN_ELSE
6743 && (XEXP (x, 2) == const0_rtx
6744 || XEXP (x, 2) == const1_rtx)
6745 && COMPARISON_P (XEXP (x, 0))
6746 && COMPARISON_P (XEXP (x, 1)))
6747 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6748 INTVAL (XEXP (x, 2)));
6750 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6751 if (GET_CODE (x) == AND
6752 && COMPARISON_P (XEXP (x, 0))
6753 && COMPARISON_P (XEXP (x, 1)))
6754 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6757 if (GET_CODE (x) == IOR
6758 && COMPARISON_P (XEXP (x, 0))
6759 && COMPARISON_P (XEXP (x, 1)))
6760 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6763 /* An operation (on Thumb) where we want to test for a single bit.
6764 This is done by shifting that bit up into the top bit of a
6765 scratch register; we can then branch on the sign bit. */
6767 && GET_MODE (x) == SImode
6768 && (op == EQ || op == NE)
6769 && GET_CODE (x) == ZERO_EXTRACT
6770 && XEXP (x, 1) == const1_rtx)
6773 /* An operation that sets the condition codes as a side-effect, the
6774 V flag is not set correctly, so we can only use comparisons where
6775 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6777 if (GET_MODE (x) == SImode
6779 && (op == EQ || op == NE || op == LT || op == GE)
6780 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6781 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6782 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6783 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6784 || GET_CODE (x) == LSHIFTRT
6785 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6786 || GET_CODE (x) == ROTATERT
6787 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6790 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6793 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6794 && GET_CODE (x) == PLUS
6795 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6801 /* X and Y are two things to compare using CODE. Emit the compare insn and
6802 return the rtx for register 0 in the proper mode. FP means this is a
6803 floating point compare: I don't think that it is needed on the arm. */
6805 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6807 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6808 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6810 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
6815 /* Generate a sequence of insns that will generate the correct return
6816 address mask depending on the physical architecture that the program
6819 arm_gen_return_addr_mask (void)
6821 rtx reg = gen_reg_rtx (Pmode);
6823 emit_insn (gen_return_addr_mask (reg));
6828 arm_reload_in_hi (rtx *operands)
6830 rtx ref = operands[1];
6832 HOST_WIDE_INT offset = 0;
6834 if (GET_CODE (ref) == SUBREG)
6836 offset = SUBREG_BYTE (ref);
6837 ref = SUBREG_REG (ref);
6840 if (GET_CODE (ref) == REG)
6842 /* We have a pseudo which has been spilt onto the stack; there
6843 are two cases here: the first where there is a simple
6844 stack-slot replacement and a second where the stack-slot is
6845 out of range, or is used as a subreg. */
6846 if (reg_equiv_mem[REGNO (ref)])
6848 ref = reg_equiv_mem[REGNO (ref)];
6849 base = find_replacement (&XEXP (ref, 0));
6852 /* The slot is out of range, or was dressed up in a SUBREG. */
6853 base = reg_equiv_address[REGNO (ref)];
6856 base = find_replacement (&XEXP (ref, 0));
6858 /* Handle the case where the address is too complex to be offset by 1. */
6859 if (GET_CODE (base) == MINUS
6860 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6862 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6864 emit_set_insn (base_plus, base);
6867 else if (GET_CODE (base) == PLUS)
6869 /* The addend must be CONST_INT, or we would have dealt with it above. */
6870 HOST_WIDE_INT hi, lo;
6872 offset += INTVAL (XEXP (base, 1));
6873 base = XEXP (base, 0);
6875 /* Rework the address into a legal sequence of insns. */
6876 /* Valid range for lo is -4095 -> 4095 */
6879 : -((-offset) & 0xfff));
6881 /* Corner case, if lo is the max offset then we would be out of range
6882 once we have added the additional 1 below, so bump the msb into the
6883 pre-loading insn(s). */
6887 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6888 ^ (HOST_WIDE_INT) 0x80000000)
6889 - (HOST_WIDE_INT) 0x80000000);
6891 gcc_assert (hi + lo == offset);
6895 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6897 /* Get the base address; addsi3 knows how to handle constants
6898 that require more than one insn. */
6899 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6905 /* Operands[2] may overlap operands[0] (though it won't overlap
6906 operands[1]), that's why we asked for a DImode reg -- so we can
6907 use the bit that does not overlap. */
6908 if (REGNO (operands[2]) == REGNO (operands[0]))
6909 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6911 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6913 emit_insn (gen_zero_extendqisi2 (scratch,
6914 gen_rtx_MEM (QImode,
6915 plus_constant (base,
6917 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6918 gen_rtx_MEM (QImode,
6919 plus_constant (base,
6921 if (!BYTES_BIG_ENDIAN)
6922 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
6923 gen_rtx_IOR (SImode,
6926 gen_rtx_SUBREG (SImode, operands[0], 0),
6930 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
6931 gen_rtx_IOR (SImode,
6932 gen_rtx_ASHIFT (SImode, scratch,
6934 gen_rtx_SUBREG (SImode, operands[0], 0)));
6937 /* Handle storing a half-word to memory during reload by synthesizing as two
6938 byte stores. Take care not to clobber the input values until after we
6939 have moved them somewhere safe. This code assumes that if the DImode
6940 scratch in operands[2] overlaps either the input value or output address
6941 in some way, then that value must die in this insn (we absolutely need
6942 two scratch registers for some corner cases). */
6944 arm_reload_out_hi (rtx *operands)
6946 rtx ref = operands[0];
6947 rtx outval = operands[1];
6949 HOST_WIDE_INT offset = 0;
6951 if (GET_CODE (ref) == SUBREG)
6953 offset = SUBREG_BYTE (ref);
6954 ref = SUBREG_REG (ref);
6957 if (GET_CODE (ref) == REG)
6959 /* We have a pseudo which has been spilt onto the stack; there
6960 are two cases here: the first where there is a simple
6961 stack-slot replacement and a second where the stack-slot is
6962 out of range, or is used as a subreg. */
6963 if (reg_equiv_mem[REGNO (ref)])
6965 ref = reg_equiv_mem[REGNO (ref)];
6966 base = find_replacement (&XEXP (ref, 0));
6969 /* The slot is out of range, or was dressed up in a SUBREG. */
6970 base = reg_equiv_address[REGNO (ref)];
6973 base = find_replacement (&XEXP (ref, 0));
6975 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6977 /* Handle the case where the address is too complex to be offset by 1. */
6978 if (GET_CODE (base) == MINUS
6979 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6981 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6983 /* Be careful not to destroy OUTVAL. */
6984 if (reg_overlap_mentioned_p (base_plus, outval))
6986 /* Updating base_plus might destroy outval, see if we can
6987 swap the scratch and base_plus. */
6988 if (!reg_overlap_mentioned_p (scratch, outval))
6991 scratch = base_plus;
6996 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6998 /* Be conservative and copy OUTVAL into the scratch now,
6999 this should only be necessary if outval is a subreg
7000 of something larger than a word. */
7001 /* XXX Might this clobber base? I can't see how it can,
7002 since scratch is known to overlap with OUTVAL, and
7003 must be wider than a word. */
7004 emit_insn (gen_movhi (scratch_hi, outval));
7005 outval = scratch_hi;
7009 emit_set_insn (base_plus, base);
7012 else if (GET_CODE (base) == PLUS)
7014 /* The addend must be CONST_INT, or we would have dealt with it above. */
7015 HOST_WIDE_INT hi, lo;
7017 offset += INTVAL (XEXP (base, 1));
7018 base = XEXP (base, 0);
7020 /* Rework the address into a legal sequence of insns. */
7021 /* Valid range for lo is -4095 -> 4095 */
7024 : -((-offset) & 0xfff));
7026 /* Corner case, if lo is the max offset then we would be out of range
7027 once we have added the additional 1 below, so bump the msb into the
7028 pre-loading insn(s). */
7032 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7033 ^ (HOST_WIDE_INT) 0x80000000)
7034 - (HOST_WIDE_INT) 0x80000000);
7036 gcc_assert (hi + lo == offset);
7040 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7042 /* Be careful not to destroy OUTVAL. */
7043 if (reg_overlap_mentioned_p (base_plus, outval))
7045 /* Updating base_plus might destroy outval, see if we
7046 can swap the scratch and base_plus. */
7047 if (!reg_overlap_mentioned_p (scratch, outval))
7050 scratch = base_plus;
7055 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7057 /* Be conservative and copy outval into scratch now,
7058 this should only be necessary if outval is a
7059 subreg of something larger than a word. */
7060 /* XXX Might this clobber base? I can't see how it
7061 can, since scratch is known to overlap with
7063 emit_insn (gen_movhi (scratch_hi, outval));
7064 outval = scratch_hi;
7068 /* Get the base address; addsi3 knows how to handle constants
7069 that require more than one insn. */
7070 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7076 if (BYTES_BIG_ENDIAN)
7078 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7079 plus_constant (base, offset + 1)),
7080 gen_lowpart (QImode, outval)));
7081 emit_insn (gen_lshrsi3 (scratch,
7082 gen_rtx_SUBREG (SImode, outval, 0),
7084 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7085 gen_lowpart (QImode, scratch)));
7089 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7090 gen_lowpart (QImode, outval)));
7091 emit_insn (gen_lshrsi3 (scratch,
7092 gen_rtx_SUBREG (SImode, outval, 0),
7094 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7095 plus_constant (base, offset + 1)),
7096 gen_lowpart (QImode, scratch)));
7100 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7101 (padded to the size of a word) should be passed in a register. */
7104 arm_must_pass_in_stack (enum machine_mode mode, tree type)
7106 if (TARGET_AAPCS_BASED)
7107 return must_pass_in_stack_var_size (mode, type);
7109 return must_pass_in_stack_var_size_or_pad (mode, type);
7113 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7114 Return true if an argument passed on the stack should be padded upwards,
7115 i.e. if the least-significant byte has useful data.
7116 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7117 aggregate types are placed in the lowest memory address. */
7120 arm_pad_arg_upward (enum machine_mode mode, tree type)
7122 if (!TARGET_AAPCS_BASED)
7123 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
7125 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
7132 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7133 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7134 byte of the register has useful data, and return the opposite if the
7135 most significant byte does.
7136 For AAPCS, small aggregates and small complex types are always padded
7140 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
7141 tree type, int first ATTRIBUTE_UNUSED)
7143 if (TARGET_AAPCS_BASED
7145 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
7146 && int_size_in_bytes (type) <= 4)
7149 /* Otherwise, use default padding. */
7150 return !BYTES_BIG_ENDIAN;
7154 /* Print a symbolic form of X to the debug file, F. */
7156 arm_print_value (FILE *f, rtx x)
7158 switch (GET_CODE (x))
7161 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
7165 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
7173 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
7175 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
7176 if (i < (CONST_VECTOR_NUNITS (x) - 1))
7184 fprintf (f, "\"%s\"", XSTR (x, 0));
7188 fprintf (f, "`%s'", XSTR (x, 0));
7192 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
7196 arm_print_value (f, XEXP (x, 0));
7200 arm_print_value (f, XEXP (x, 0));
7202 arm_print_value (f, XEXP (x, 1));
7210 fprintf (f, "????");
7215 /* Routines for manipulation of the constant pool. */
7217 /* Arm instructions cannot load a large constant directly into a
7218 register; they have to come from a pc relative load. The constant
7219 must therefore be placed in the addressable range of the pc
7220 relative load. Depending on the precise pc relative load
7221 instruction the range is somewhere between 256 bytes and 4k. This
7222 means that we often have to dump a constant inside a function, and
7223 generate code to branch around it.
7225 It is important to minimize this, since the branches will slow
7226 things down and make the code larger.
7228 Normally we can hide the table after an existing unconditional
7229 branch so that there is no interruption of the flow, but in the
7230 worst case the code looks like this:
7248 We fix this by performing a scan after scheduling, which notices
7249 which instructions need to have their operands fetched from the
7250 constant table and builds the table.
7252 The algorithm starts by building a table of all the constants that
7253 need fixing up and all the natural barriers in the function (places
7254 where a constant table can be dropped without breaking the flow).
7255 For each fixup we note how far the pc-relative replacement will be
7256 able to reach and the offset of the instruction into the function.
7258 Having built the table we then group the fixes together to form
7259 tables that are as large as possible (subject to addressing
7260 constraints) and emit each table of constants after the last
7261 barrier that is within range of all the instructions in the group.
7262 If a group does not contain a barrier, then we forcibly create one
7263 by inserting a jump instruction into the flow. Once the table has
7264 been inserted, the insns are then modified to reference the
7265 relevant entry in the pool.
7267 Possible enhancements to the algorithm (not implemented) are:
7269 1) For some processors and object formats, there may be benefit in
7270 aligning the pools to the start of cache lines; this alignment
7271 would need to be taken into account when calculating addressability
7274 /* These typedefs are located at the start of this file, so that
7275 they can be used in the prototypes there. This comment is to
7276 remind readers of that fact so that the following structures
7277 can be understood more easily.
7279 typedef struct minipool_node Mnode;
7280 typedef struct minipool_fixup Mfix; */
7282 struct minipool_node
7284 /* Doubly linked chain of entries. */
7287 /* The maximum offset into the code that this entry can be placed. While
7288 pushing fixes for forward references, all entries are sorted in order
7289 of increasing max_address. */
7290 HOST_WIDE_INT max_address;
7291 /* Similarly for an entry inserted for a backwards ref. */
7292 HOST_WIDE_INT min_address;
7293 /* The number of fixes referencing this entry. This can become zero
7294 if we "unpush" an entry. In this case we ignore the entry when we
7295 come to emit the code. */
7297 /* The offset from the start of the minipool. */
7298 HOST_WIDE_INT offset;
7299 /* The value in table. */
7301 /* The mode of value. */
7302 enum machine_mode mode;
7303 /* The size of the value. With iWMMXt enabled
7304 sizes > 4 also imply an alignment of 8-bytes. */
7308 struct minipool_fixup
7312 HOST_WIDE_INT address;
7314 enum machine_mode mode;
7318 HOST_WIDE_INT forwards;
7319 HOST_WIDE_INT backwards;
7322 /* Fixes less than a word need padding out to a word boundary. */
7323 #define MINIPOOL_FIX_SIZE(mode) \
7324 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7326 static Mnode * minipool_vector_head;
7327 static Mnode * minipool_vector_tail;
7328 static rtx minipool_vector_label;
7329 static int minipool_pad;
7331 /* The linked list of all minipool fixes required for this function. */
7332 Mfix * minipool_fix_head;
7333 Mfix * minipool_fix_tail;
7334 /* The fix entry for the current minipool, once it has been placed. */
7335 Mfix * minipool_barrier;
7337 /* Determines if INSN is the start of a jump table. Returns the end
7338 of the TABLE or NULL_RTX. */
7340 is_jump_table (rtx insn)
7344 if (GET_CODE (insn) == JUMP_INSN
7345 && JUMP_LABEL (insn) != NULL
7346 && ((table = next_real_insn (JUMP_LABEL (insn)))
7347 == next_real_insn (insn))
7349 && GET_CODE (table) == JUMP_INSN
7350 && (GET_CODE (PATTERN (table)) == ADDR_VEC
7351 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
7357 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7358 #define JUMP_TABLES_IN_TEXT_SECTION 0
7361 static HOST_WIDE_INT
7362 get_jump_table_size (rtx insn)
7364 /* ADDR_VECs only take room if read-only data does into the text
7366 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
7368 rtx body = PATTERN (insn);
7369 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
7371 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
7377 /* Move a minipool fix MP from its current location to before MAX_MP.
7378 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7379 constraints may need updating. */
7381 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
7382 HOST_WIDE_INT max_address)
7384 /* The code below assumes these are different. */
7385 gcc_assert (mp != max_mp);
7389 if (max_address < mp->max_address)
7390 mp->max_address = max_address;
7394 if (max_address > max_mp->max_address - mp->fix_size)
7395 mp->max_address = max_mp->max_address - mp->fix_size;
7397 mp->max_address = max_address;
7399 /* Unlink MP from its current position. Since max_mp is non-null,
7400 mp->prev must be non-null. */
7401 mp->prev->next = mp->next;
7402 if (mp->next != NULL)
7403 mp->next->prev = mp->prev;
7405 minipool_vector_tail = mp->prev;
7407 /* Re-insert it before MAX_MP. */
7409 mp->prev = max_mp->prev;
7412 if (mp->prev != NULL)
7413 mp->prev->next = mp;
7415 minipool_vector_head = mp;
7418 /* Save the new entry. */
7421 /* Scan over the preceding entries and adjust their addresses as
7423 while (mp->prev != NULL
7424 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7426 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7433 /* Add a constant to the minipool for a forward reference. Returns the
7434 node added or NULL if the constant will not fit in this pool. */
7436 add_minipool_forward_ref (Mfix *fix)
7438 /* If set, max_mp is the first pool_entry that has a lower
7439 constraint than the one we are trying to add. */
7440 Mnode * max_mp = NULL;
7441 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
7444 /* If the minipool starts before the end of FIX->INSN then this FIX
7445 can not be placed into the current pool. Furthermore, adding the
7446 new constant pool entry may cause the pool to start FIX_SIZE bytes
7448 if (minipool_vector_head &&
7449 (fix->address + get_attr_length (fix->insn)
7450 >= minipool_vector_head->max_address - fix->fix_size))
7453 /* Scan the pool to see if a constant with the same value has
7454 already been added. While we are doing this, also note the
7455 location where we must insert the constant if it doesn't already
7457 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7459 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7460 && fix->mode == mp->mode
7461 && (GET_CODE (fix->value) != CODE_LABEL
7462 || (CODE_LABEL_NUMBER (fix->value)
7463 == CODE_LABEL_NUMBER (mp->value)))
7464 && rtx_equal_p (fix->value, mp->value))
7466 /* More than one fix references this entry. */
7468 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7471 /* Note the insertion point if necessary. */
7473 && mp->max_address > max_address)
7476 /* If we are inserting an 8-bytes aligned quantity and
7477 we have not already found an insertion point, then
7478 make sure that all such 8-byte aligned quantities are
7479 placed at the start of the pool. */
7480 if (ARM_DOUBLEWORD_ALIGN
7482 && fix->fix_size == 8
7483 && mp->fix_size != 8)
7486 max_address = mp->max_address;
7490 /* The value is not currently in the minipool, so we need to create
7491 a new entry for it. If MAX_MP is NULL, the entry will be put on
7492 the end of the list since the placement is less constrained than
7493 any existing entry. Otherwise, we insert the new fix before
7494 MAX_MP and, if necessary, adjust the constraints on the other
7497 mp->fix_size = fix->fix_size;
7498 mp->mode = fix->mode;
7499 mp->value = fix->value;
7501 /* Not yet required for a backwards ref. */
7502 mp->min_address = -65536;
7506 mp->max_address = max_address;
7508 mp->prev = minipool_vector_tail;
7510 if (mp->prev == NULL)
7512 minipool_vector_head = mp;
7513 minipool_vector_label = gen_label_rtx ();
7516 mp->prev->next = mp;
7518 minipool_vector_tail = mp;
7522 if (max_address > max_mp->max_address - mp->fix_size)
7523 mp->max_address = max_mp->max_address - mp->fix_size;
7525 mp->max_address = max_address;
7528 mp->prev = max_mp->prev;
7530 if (mp->prev != NULL)
7531 mp->prev->next = mp;
7533 minipool_vector_head = mp;
7536 /* Save the new entry. */
7539 /* Scan over the preceding entries and adjust their addresses as
7541 while (mp->prev != NULL
7542 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7544 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7552 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7553 HOST_WIDE_INT min_address)
7555 HOST_WIDE_INT offset;
7557 /* The code below assumes these are different. */
7558 gcc_assert (mp != min_mp);
7562 if (min_address > mp->min_address)
7563 mp->min_address = min_address;
7567 /* We will adjust this below if it is too loose. */
7568 mp->min_address = min_address;
7570 /* Unlink MP from its current position. Since min_mp is non-null,
7571 mp->next must be non-null. */
7572 mp->next->prev = mp->prev;
7573 if (mp->prev != NULL)
7574 mp->prev->next = mp->next;
7576 minipool_vector_head = mp->next;
7578 /* Reinsert it after MIN_MP. */
7580 mp->next = min_mp->next;
7582 if (mp->next != NULL)
7583 mp->next->prev = mp;
7585 minipool_vector_tail = mp;
7591 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7593 mp->offset = offset;
7594 if (mp->refcount > 0)
7595 offset += mp->fix_size;
7597 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7598 mp->next->min_address = mp->min_address + mp->fix_size;
7604 /* Add a constant to the minipool for a backward reference. Returns the
7605 node added or NULL if the constant will not fit in this pool.
7607 Note that the code for insertion for a backwards reference can be
7608 somewhat confusing because the calculated offsets for each fix do
7609 not take into account the size of the pool (which is still under
7612 add_minipool_backward_ref (Mfix *fix)
7614 /* If set, min_mp is the last pool_entry that has a lower constraint
7615 than the one we are trying to add. */
7616 Mnode *min_mp = NULL;
7617 /* This can be negative, since it is only a constraint. */
7618 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7621 /* If we can't reach the current pool from this insn, or if we can't
7622 insert this entry at the end of the pool without pushing other
7623 fixes out of range, then we don't try. This ensures that we
7624 can't fail later on. */
7625 if (min_address >= minipool_barrier->address
7626 || (minipool_vector_tail->min_address + fix->fix_size
7627 >= minipool_barrier->address))
7630 /* Scan the pool to see if a constant with the same value has
7631 already been added. While we are doing this, also note the
7632 location where we must insert the constant if it doesn't already
7634 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7636 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7637 && fix->mode == mp->mode
7638 && (GET_CODE (fix->value) != CODE_LABEL
7639 || (CODE_LABEL_NUMBER (fix->value)
7640 == CODE_LABEL_NUMBER (mp->value)))
7641 && rtx_equal_p (fix->value, mp->value)
7642 /* Check that there is enough slack to move this entry to the
7643 end of the table (this is conservative). */
7645 > (minipool_barrier->address
7646 + minipool_vector_tail->offset
7647 + minipool_vector_tail->fix_size)))
7650 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7654 mp->min_address += fix->fix_size;
7657 /* Note the insertion point if necessary. */
7658 if (mp->min_address < min_address)
7660 /* For now, we do not allow the insertion of 8-byte alignment
7661 requiring nodes anywhere but at the start of the pool. */
7662 if (ARM_DOUBLEWORD_ALIGN
7663 && fix->fix_size == 8 && mp->fix_size != 8)
7668 else if (mp->max_address
7669 < minipool_barrier->address + mp->offset + fix->fix_size)
7671 /* Inserting before this entry would push the fix beyond
7672 its maximum address (which can happen if we have
7673 re-located a forwards fix); force the new fix to come
7676 min_address = mp->min_address + fix->fix_size;
7678 /* If we are inserting an 8-bytes aligned quantity and
7679 we have not already found an insertion point, then
7680 make sure that all such 8-byte aligned quantities are
7681 placed at the start of the pool. */
7682 else if (ARM_DOUBLEWORD_ALIGN
7684 && fix->fix_size == 8
7685 && mp->fix_size < 8)
7688 min_address = mp->min_address + fix->fix_size;
7693 /* We need to create a new entry. */
7695 mp->fix_size = fix->fix_size;
7696 mp->mode = fix->mode;
7697 mp->value = fix->value;
7699 mp->max_address = minipool_barrier->address + 65536;
7701 mp->min_address = min_address;
7706 mp->next = minipool_vector_head;
7708 if (mp->next == NULL)
7710 minipool_vector_tail = mp;
7711 minipool_vector_label = gen_label_rtx ();
7714 mp->next->prev = mp;
7716 minipool_vector_head = mp;
7720 mp->next = min_mp->next;
7724 if (mp->next != NULL)
7725 mp->next->prev = mp;
7727 minipool_vector_tail = mp;
7730 /* Save the new entry. */
7738 /* Scan over the following entries and adjust their offsets. */
7739 while (mp->next != NULL)
7741 if (mp->next->min_address < mp->min_address + mp->fix_size)
7742 mp->next->min_address = mp->min_address + mp->fix_size;
7745 mp->next->offset = mp->offset + mp->fix_size;
7747 mp->next->offset = mp->offset;
7756 assign_minipool_offsets (Mfix *barrier)
7758 HOST_WIDE_INT offset = 0;
7761 minipool_barrier = barrier;
7763 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7765 mp->offset = offset;
7767 if (mp->refcount > 0)
7768 offset += mp->fix_size;
7772 /* Output the literal table */
7774 dump_minipool (rtx scan)
7780 if (ARM_DOUBLEWORD_ALIGN)
7781 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7782 if (mp->refcount > 0 && mp->fix_size == 8)
7790 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7791 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7793 scan = emit_label_after (gen_label_rtx (), scan);
7794 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7795 scan = emit_label_after (minipool_vector_label, scan);
7797 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7799 if (mp->refcount > 0)
7804 ";; Offset %u, min %ld, max %ld ",
7805 (unsigned) mp->offset, (unsigned long) mp->min_address,
7806 (unsigned long) mp->max_address);
7807 arm_print_value (dump_file, mp->value);
7808 fputc ('\n', dump_file);
7811 switch (mp->fix_size)
7813 #ifdef HAVE_consttable_1
7815 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7819 #ifdef HAVE_consttable_2
7821 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7825 #ifdef HAVE_consttable_4
7827 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7831 #ifdef HAVE_consttable_8
7833 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7846 minipool_vector_head = minipool_vector_tail = NULL;
7847 scan = emit_insn_after (gen_consttable_end (), scan);
7848 scan = emit_barrier_after (scan);
7851 /* Return the cost of forcibly inserting a barrier after INSN. */
7853 arm_barrier_cost (rtx insn)
7855 /* Basing the location of the pool on the loop depth is preferable,
7856 but at the moment, the basic block information seems to be
7857 corrupt by this stage of the compilation. */
7859 rtx next = next_nonnote_insn (insn);
7861 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7864 switch (GET_CODE (insn))
7867 /* It will always be better to place the table before the label, rather
7876 return base_cost - 10;
7879 return base_cost + 10;
7883 /* Find the best place in the insn stream in the range
7884 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7885 Create the barrier by inserting a jump and add a new fix entry for
7888 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7890 HOST_WIDE_INT count = 0;
7892 rtx from = fix->insn;
7893 /* The instruction after which we will insert the jump. */
7894 rtx selected = NULL;
7896 /* The address at which the jump instruction will be placed. */
7897 HOST_WIDE_INT selected_address;
7899 HOST_WIDE_INT max_count = max_address - fix->address;
7900 rtx label = gen_label_rtx ();
7902 selected_cost = arm_barrier_cost (from);
7903 selected_address = fix->address;
7905 while (from && count < max_count)
7910 /* This code shouldn't have been called if there was a natural barrier
7912 gcc_assert (GET_CODE (from) != BARRIER);
7914 /* Count the length of this insn. */
7915 count += get_attr_length (from);
7917 /* If there is a jump table, add its length. */
7918 tmp = is_jump_table (from);
7921 count += get_jump_table_size (tmp);
7923 /* Jump tables aren't in a basic block, so base the cost on
7924 the dispatch insn. If we select this location, we will
7925 still put the pool after the table. */
7926 new_cost = arm_barrier_cost (from);
7928 if (count < max_count
7929 && (!selected || new_cost <= selected_cost))
7932 selected_cost = new_cost;
7933 selected_address = fix->address + count;
7936 /* Continue after the dispatch table. */
7937 from = NEXT_INSN (tmp);
7941 new_cost = arm_barrier_cost (from);
7943 if (count < max_count
7944 && (!selected || new_cost <= selected_cost))
7947 selected_cost = new_cost;
7948 selected_address = fix->address + count;
7951 from = NEXT_INSN (from);
7954 /* Make sure that we found a place to insert the jump. */
7955 gcc_assert (selected);
7957 /* Create a new JUMP_INSN that branches around a barrier. */
7958 from = emit_jump_insn_after (gen_jump (label), selected);
7959 JUMP_LABEL (from) = label;
7960 barrier = emit_barrier_after (from);
7961 emit_label_after (label, barrier);
7963 /* Create a minipool barrier entry for the new barrier. */
7964 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7965 new_fix->insn = barrier;
7966 new_fix->address = selected_address;
7967 new_fix->next = fix->next;
7968 fix->next = new_fix;
7973 /* Record that there is a natural barrier in the insn stream at
7976 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7978 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7981 fix->address = address;
7984 if (minipool_fix_head != NULL)
7985 minipool_fix_tail->next = fix;
7987 minipool_fix_head = fix;
7989 minipool_fix_tail = fix;
7992 /* Record INSN, which will need fixing up to load a value from the
7993 minipool. ADDRESS is the offset of the insn since the start of the
7994 function; LOC is a pointer to the part of the insn which requires
7995 fixing; VALUE is the constant that must be loaded, which is of type
7998 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7999 enum machine_mode mode, rtx value)
8001 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8003 #ifdef AOF_ASSEMBLER
8004 /* PIC symbol references need to be converted into offsets into the
8006 /* XXX This shouldn't be done here. */
8007 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
8008 value = aof_pic_entry (value);
8009 #endif /* AOF_ASSEMBLER */
8012 fix->address = address;
8015 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
8017 fix->forwards = get_attr_pool_range (insn);
8018 fix->backwards = get_attr_neg_pool_range (insn);
8019 fix->minipool = NULL;
8021 /* If an insn doesn't have a range defined for it, then it isn't
8022 expecting to be reworked by this code. Better to stop now than
8023 to generate duff assembly code. */
8024 gcc_assert (fix->forwards || fix->backwards);
8026 /* If an entry requires 8-byte alignment then assume all constant pools
8027 require 4 bytes of padding. Trying to do this later on a per-pool
8028 basis is awkward because existing pool entries have to be modified. */
8029 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
8035 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8036 GET_MODE_NAME (mode),
8037 INSN_UID (insn), (unsigned long) address,
8038 -1 * (long)fix->backwards, (long)fix->forwards);
8039 arm_print_value (dump_file, fix->value);
8040 fprintf (dump_file, "\n");
8043 /* Add it to the chain of fixes. */
8046 if (minipool_fix_head != NULL)
8047 minipool_fix_tail->next = fix;
8049 minipool_fix_head = fix;
8051 minipool_fix_tail = fix;
8054 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8055 Returns the number of insns needed, or 99 if we don't know how to
8058 arm_const_double_inline_cost (rtx val)
8060 rtx lowpart, highpart;
8061 enum machine_mode mode;
8063 mode = GET_MODE (val);
8065 if (mode == VOIDmode)
8068 gcc_assert (GET_MODE_SIZE (mode) == 8);
8070 lowpart = gen_lowpart (SImode, val);
8071 highpart = gen_highpart_mode (SImode, mode, val);
8073 gcc_assert (GET_CODE (lowpart) == CONST_INT);
8074 gcc_assert (GET_CODE (highpart) == CONST_INT);
8076 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
8077 NULL_RTX, NULL_RTX, 0, 0)
8078 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
8079 NULL_RTX, NULL_RTX, 0, 0));
8082 /* Return true if it is worthwhile to split a 64-bit constant into two
8083 32-bit operations. This is the case if optimizing for size, or
8084 if we have load delay slots, or if one 32-bit part can be done with
8085 a single data operation. */
8087 arm_const_double_by_parts (rtx val)
8089 enum machine_mode mode = GET_MODE (val);
8092 if (optimize_size || arm_ld_sched)
8095 if (mode == VOIDmode)
8098 part = gen_highpart_mode (SImode, mode, val);
8100 gcc_assert (GET_CODE (part) == CONST_INT);
8102 if (const_ok_for_arm (INTVAL (part))
8103 || const_ok_for_arm (~INTVAL (part)))
8106 part = gen_lowpart (SImode, val);
8108 gcc_assert (GET_CODE (part) == CONST_INT);
8110 if (const_ok_for_arm (INTVAL (part))
8111 || const_ok_for_arm (~INTVAL (part)))
8117 /* Scan INSN and note any of its operands that need fixing.
8118 If DO_PUSHES is false we do not actually push any of the fixups
8119 needed. The function returns TRUE if any fixups were needed/pushed.
8120 This is used by arm_memory_load_p() which needs to know about loads
8121 of constants that will be converted into minipool loads. */
8123 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
8125 bool result = false;
8128 extract_insn (insn);
8130 if (!constrain_operands (1))
8131 fatal_insn_not_found (insn);
8133 if (recog_data.n_alternatives == 0)
8136 /* Fill in recog_op_alt with information about the constraints of
8138 preprocess_constraints ();
8140 for (opno = 0; opno < recog_data.n_operands; opno++)
8142 /* Things we need to fix can only occur in inputs. */
8143 if (recog_data.operand_type[opno] != OP_IN)
8146 /* If this alternative is a memory reference, then any mention
8147 of constants in this alternative is really to fool reload
8148 into allowing us to accept one there. We need to fix them up
8149 now so that we output the right code. */
8150 if (recog_op_alt[opno][which_alternative].memory_ok)
8152 rtx op = recog_data.operand[opno];
8154 if (CONSTANT_P (op))
8157 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
8158 recog_data.operand_mode[opno], op);
8161 else if (GET_CODE (op) == MEM
8162 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
8163 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
8167 rtx cop = avoid_constant_pool_reference (op);
8169 /* Casting the address of something to a mode narrower
8170 than a word can cause avoid_constant_pool_reference()
8171 to return the pool reference itself. That's no good to
8172 us here. Lets just hope that we can use the
8173 constant pool value directly. */
8175 cop = get_pool_constant (XEXP (op, 0));
8177 push_minipool_fix (insn, address,
8178 recog_data.operand_loc[opno],
8179 recog_data.operand_mode[opno], cop);
8190 /* Gcc puts the pool in the wrong place for ARM, since we can only
8191 load addresses a limited distance around the pc. We do some
8192 special munging to move the constant pool values to the correct
8193 point in the code. */
8198 HOST_WIDE_INT address = 0;
8201 minipool_fix_head = minipool_fix_tail = NULL;
8203 /* The first insn must always be a note, or the code below won't
8204 scan it properly. */
8205 insn = get_insns ();
8206 gcc_assert (GET_CODE (insn) == NOTE);
8209 /* Scan all the insns and record the operands that will need fixing. */
8210 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
8212 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8213 && (arm_cirrus_insn_p (insn)
8214 || GET_CODE (insn) == JUMP_INSN
8215 || arm_memory_load_p (insn)))
8216 cirrus_reorg (insn);
8218 if (GET_CODE (insn) == BARRIER)
8219 push_minipool_barrier (insn, address);
8220 else if (INSN_P (insn))
8224 note_invalid_constants (insn, address, true);
8225 address += get_attr_length (insn);
8227 /* If the insn is a vector jump, add the size of the table
8228 and skip the table. */
8229 if ((table = is_jump_table (insn)) != NULL)
8231 address += get_jump_table_size (table);
8237 fix = minipool_fix_head;
8239 /* Now scan the fixups and perform the required changes. */
8244 Mfix * last_added_fix;
8245 Mfix * last_barrier = NULL;
8248 /* Skip any further barriers before the next fix. */
8249 while (fix && GET_CODE (fix->insn) == BARRIER)
8252 /* No more fixes. */
8256 last_added_fix = NULL;
8258 for (ftmp = fix; ftmp; ftmp = ftmp->next)
8260 if (GET_CODE (ftmp->insn) == BARRIER)
8262 if (ftmp->address >= minipool_vector_head->max_address)
8265 last_barrier = ftmp;
8267 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
8270 last_added_fix = ftmp; /* Keep track of the last fix added. */
8273 /* If we found a barrier, drop back to that; any fixes that we
8274 could have reached but come after the barrier will now go in
8275 the next mini-pool. */
8276 if (last_barrier != NULL)
8278 /* Reduce the refcount for those fixes that won't go into this
8280 for (fdel = last_barrier->next;
8281 fdel && fdel != ftmp;
8284 fdel->minipool->refcount--;
8285 fdel->minipool = NULL;
8288 ftmp = last_barrier;
8292 /* ftmp is first fix that we can't fit into this pool and
8293 there no natural barriers that we could use. Insert a
8294 new barrier in the code somewhere between the previous
8295 fix and this one, and arrange to jump around it. */
8296 HOST_WIDE_INT max_address;
8298 /* The last item on the list of fixes must be a barrier, so
8299 we can never run off the end of the list of fixes without
8300 last_barrier being set. */
8303 max_address = minipool_vector_head->max_address;
8304 /* Check that there isn't another fix that is in range that
8305 we couldn't fit into this pool because the pool was
8306 already too large: we need to put the pool before such an
8307 instruction. The pool itself may come just after the
8308 fix because create_fix_barrier also allows space for a
8309 jump instruction. */
8310 if (ftmp->address < max_address)
8311 max_address = ftmp->address + 1;
8313 last_barrier = create_fix_barrier (last_added_fix, max_address);
8316 assign_minipool_offsets (last_barrier);
8320 if (GET_CODE (ftmp->insn) != BARRIER
8321 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
8328 /* Scan over the fixes we have identified for this pool, fixing them
8329 up and adding the constants to the pool itself. */
8330 for (this_fix = fix; this_fix && ftmp != this_fix;
8331 this_fix = this_fix->next)
8332 if (GET_CODE (this_fix->insn) != BARRIER)
8335 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
8336 minipool_vector_label),
8337 this_fix->minipool->offset);
8338 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
8341 dump_minipool (last_barrier->insn);
8345 /* From now on we must synthesize any constants that we can't handle
8346 directly. This can happen if the RTL gets split during final
8347 instruction generation. */
8348 after_arm_reorg = 1;
8350 /* Free the minipool memory. */
8351 obstack_free (&minipool_obstack, minipool_startobj);
8354 /* Routines to output assembly language. */
8356 /* If the rtx is the correct value then return the string of the number.
8357 In this way we can ensure that valid double constants are generated even
8358 when cross compiling. */
8360 fp_immediate_constant (rtx x)
8365 if (!fp_consts_inited)
8368 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8369 for (i = 0; i < 8; i++)
8370 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8371 return strings_fp[i];
8376 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8378 fp_const_from_val (REAL_VALUE_TYPE *r)
8382 if (!fp_consts_inited)
8385 for (i = 0; i < 8; i++)
8386 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
8387 return strings_fp[i];
8392 /* Output the operands of a LDM/STM instruction to STREAM.
8393 MASK is the ARM register set mask of which only bits 0-15 are important.
8394 REG is the base register, either the frame pointer or the stack pointer,
8395 INSTR is the possibly suffixed load or store instruction. */
8398 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
8402 bool not_first = FALSE;
8404 fputc ('\t', stream);
8405 asm_fprintf (stream, instr, reg);
8406 fputs (", {", stream);
8408 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8409 if (mask & (1 << i))
8412 fprintf (stream, ", ");
8414 asm_fprintf (stream, "%r", i);
8418 fprintf (stream, "}\n");
8422 /* Output a FLDMX instruction to STREAM.
8423 BASE if the register containing the address.
8424 REG and COUNT specify the register range.
8425 Extra registers may be added to avoid hardware bugs. */
8428 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
8432 /* Workaround ARM10 VFPr1 bug. */
8433 if (count == 2 && !arm_arch6)
8440 fputc ('\t', stream);
8441 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
8443 for (i = reg; i < reg + count; i++)
8446 fputs (", ", stream);
8447 asm_fprintf (stream, "d%d", i);
8449 fputs ("}\n", stream);
8454 /* Output the assembly for a store multiple. */
8457 vfp_output_fstmx (rtx * operands)
8464 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
8465 p = strlen (pattern);
8467 gcc_assert (GET_CODE (operands[1]) == REG);
8469 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8470 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8472 p += sprintf (&pattern[p], ", d%d", base + i);
8474 strcpy (&pattern[p], "}");
8476 output_asm_insn (pattern, operands);
8481 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8482 number of bytes pushed. */
8485 vfp_emit_fstmx (int base_reg, int count)
8492 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8493 register pairs are stored by a store multiple insn. We avoid this
8494 by pushing an extra pair. */
8495 if (count == 2 && !arm_arch6)
8497 if (base_reg == LAST_VFP_REGNUM - 3)
8502 /* ??? The frame layout is implementation defined. We describe
8503 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8504 We really need some way of representing the whole block so that the
8505 unwinder can figure it out at runtime. */
8506 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8507 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8509 reg = gen_rtx_REG (DFmode, base_reg);
8513 = gen_rtx_SET (VOIDmode,
8514 gen_frame_mem (BLKmode,
8515 gen_rtx_PRE_DEC (BLKmode,
8516 stack_pointer_rtx)),
8517 gen_rtx_UNSPEC (BLKmode,
8521 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8522 plus_constant (stack_pointer_rtx, -(count * 8 + 4)));
8523 RTX_FRAME_RELATED_P (tmp) = 1;
8524 XVECEXP (dwarf, 0, 0) = tmp;
8526 tmp = gen_rtx_SET (VOIDmode,
8527 gen_frame_mem (DFmode, stack_pointer_rtx),
8529 RTX_FRAME_RELATED_P (tmp) = 1;
8530 XVECEXP (dwarf, 0, 1) = tmp;
8532 for (i = 1; i < count; i++)
8534 reg = gen_rtx_REG (DFmode, base_reg);
8536 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8538 tmp = gen_rtx_SET (VOIDmode,
8539 gen_frame_mem (DFmode,
8540 plus_constant (stack_pointer_rtx,
8543 RTX_FRAME_RELATED_P (tmp) = 1;
8544 XVECEXP (dwarf, 0, i + 1) = tmp;
8547 par = emit_insn (par);
8548 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8550 RTX_FRAME_RELATED_P (par) = 1;
8552 return count * 8 + 4;
8556 /* Output a 'call' insn. */
8558 output_call (rtx *operands)
8560 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
8562 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8563 if (REGNO (operands[0]) == LR_REGNUM)
8565 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8566 output_asm_insn ("mov%?\t%0, %|lr", operands);
8569 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8571 if (TARGET_INTERWORK || arm_arch4t)
8572 output_asm_insn ("bx%?\t%0", operands);
8574 output_asm_insn ("mov%?\t%|pc, %0", operands);
8579 /* Output a 'call' insn that is a reference in memory. */
8581 output_call_mem (rtx *operands)
8583 if (TARGET_INTERWORK && !arm_arch5)
8585 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8586 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8587 output_asm_insn ("bx%?\t%|ip", operands);
8589 else if (regno_use_in (LR_REGNUM, operands[0]))
8591 /* LR is used in the memory address. We load the address in the
8592 first instruction. It's safe to use IP as the target of the
8593 load since the call will kill it anyway. */
8594 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8596 output_asm_insn ("blx%?\t%|ip", operands);
8599 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8601 output_asm_insn ("bx%?\t%|ip", operands);
8603 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8608 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8609 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8616 /* Output a move from arm registers to an fpa registers.
8617 OPERANDS[0] is an fpa register.
8618 OPERANDS[1] is the first registers of an arm register pair. */
8620 output_mov_long_double_fpa_from_arm (rtx *operands)
8622 int arm_reg0 = REGNO (operands[1]);
8625 gcc_assert (arm_reg0 != IP_REGNUM);
8627 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8628 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8629 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8631 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8632 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8637 /* Output a move from an fpa register to arm registers.
8638 OPERANDS[0] is the first registers of an arm register pair.
8639 OPERANDS[1] is an fpa register. */
8641 output_mov_long_double_arm_from_fpa (rtx *operands)
8643 int arm_reg0 = REGNO (operands[0]);
8646 gcc_assert (arm_reg0 != IP_REGNUM);
8648 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8649 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8650 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8652 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8653 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8657 /* Output a move from arm registers to arm registers of a long double
8658 OPERANDS[0] is the destination.
8659 OPERANDS[1] is the source. */
8661 output_mov_long_double_arm_from_arm (rtx *operands)
8663 /* We have to be careful here because the two might overlap. */
8664 int dest_start = REGNO (operands[0]);
8665 int src_start = REGNO (operands[1]);
8669 if (dest_start < src_start)
8671 for (i = 0; i < 3; i++)
8673 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8674 ops[1] = gen_rtx_REG (SImode, src_start + i);
8675 output_asm_insn ("mov%?\t%0, %1", ops);
8680 for (i = 2; i >= 0; i--)
8682 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8683 ops[1] = gen_rtx_REG (SImode, src_start + i);
8684 output_asm_insn ("mov%?\t%0, %1", ops);
8692 /* Output a move from arm registers to an fpa registers.
8693 OPERANDS[0] is an fpa register.
8694 OPERANDS[1] is the first registers of an arm register pair. */
8696 output_mov_double_fpa_from_arm (rtx *operands)
8698 int arm_reg0 = REGNO (operands[1]);
8701 gcc_assert (arm_reg0 != IP_REGNUM);
8703 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8704 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8705 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8706 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8710 /* Output a move from an fpa register to arm registers.
8711 OPERANDS[0] is the first registers of an arm register pair.
8712 OPERANDS[1] is an fpa register. */
8714 output_mov_double_arm_from_fpa (rtx *operands)
8716 int arm_reg0 = REGNO (operands[0]);
8719 gcc_assert (arm_reg0 != IP_REGNUM);
8721 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8722 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8723 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8724 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8728 /* Output a move between double words.
8729 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8730 or MEM<-REG and all MEMs must be offsettable addresses. */
8732 output_move_double (rtx *operands)
8734 enum rtx_code code0 = GET_CODE (operands[0]);
8735 enum rtx_code code1 = GET_CODE (operands[1]);
8740 int reg0 = REGNO (operands[0]);
8742 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8744 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
8746 switch (GET_CODE (XEXP (operands[1], 0)))
8749 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8753 gcc_assert (TARGET_LDRD);
8754 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8758 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8762 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8766 gcc_assert (TARGET_LDRD);
8767 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8772 otherops[0] = operands[0];
8773 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8774 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8776 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8778 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8780 /* Registers overlap so split out the increment. */
8781 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8782 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8786 /* IWMMXT allows offsets larger than ldrd can handle,
8787 fix these up with a pair of ldr. */
8788 if (GET_CODE (otherops[2]) == CONST_INT
8789 && (INTVAL(otherops[2]) <= -256
8790 || INTVAL(otherops[2]) >= 256))
8792 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
8793 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8794 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
8797 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8802 /* IWMMXT allows offsets larger than ldrd can handle,
8803 fix these up with a pair of ldr. */
8804 if (GET_CODE (otherops[2]) == CONST_INT
8805 && (INTVAL(otherops[2]) <= -256
8806 || INTVAL(otherops[2]) >= 256))
8808 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8809 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
8810 otherops[0] = operands[0];
8811 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
8814 /* We only allow constant increments, so this is safe. */
8815 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8821 output_asm_insn ("adr%?\t%0, %1", operands);
8822 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8826 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8827 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8829 otherops[0] = operands[0];
8830 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8831 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8833 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8835 if (GET_CODE (otherops[2]) == CONST_INT)
8837 switch ((int) INTVAL (otherops[2]))
8840 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8843 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8846 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8851 && (GET_CODE (otherops[2]) == REG
8852 || (GET_CODE (otherops[2]) == CONST_INT
8853 && INTVAL (otherops[2]) > -256
8854 && INTVAL (otherops[2]) < 256)))
8856 if (reg_overlap_mentioned_p (otherops[0],
8859 /* Swap base and index registers over to
8860 avoid a conflict. */
8861 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8862 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8864 /* If both registers conflict, it will usually
8865 have been fixed by a splitter. */
8866 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8868 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8869 output_asm_insn ("ldr%?d\t%0, [%1]",
8873 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops);
8877 if (GET_CODE (otherops[2]) == CONST_INT)
8879 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8880 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8882 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8885 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8888 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8890 return "ldm%?ia\t%0, %M0";
8894 otherops[1] = adjust_address (operands[1], SImode, 4);
8895 /* Take care of overlapping base/data reg. */
8896 if (reg_mentioned_p (operands[0], operands[1]))
8898 output_asm_insn ("ldr%?\t%0, %1", otherops);
8899 output_asm_insn ("ldr%?\t%0, %1", operands);
8903 output_asm_insn ("ldr%?\t%0, %1", operands);
8904 output_asm_insn ("ldr%?\t%0, %1", otherops);
8911 /* Constraints should ensure this. */
8912 gcc_assert (code0 == MEM && code1 == REG);
8913 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
8915 switch (GET_CODE (XEXP (operands[0], 0)))
8918 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8922 gcc_assert (TARGET_LDRD);
8923 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8927 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8931 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8935 gcc_assert (TARGET_LDRD);
8936 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8941 otherops[0] = operands[1];
8942 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8943 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8945 /* IWMMXT allows offsets larger than ldrd can handle,
8946 fix these up with a pair of ldr. */
8947 if (GET_CODE (otherops[2]) == CONST_INT
8948 && (INTVAL(otherops[2]) <= -256
8949 || INTVAL(otherops[2]) >= 256))
8952 reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8953 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8955 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
8957 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
8962 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
8963 otherops[0] = operands[1];
8964 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
8967 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8968 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8970 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8974 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8975 if (GET_CODE (otherops[2]) == CONST_INT)
8977 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8980 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8984 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8988 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8993 && (GET_CODE (otherops[2]) == REG
8994 || (GET_CODE (otherops[2]) == CONST_INT
8995 && INTVAL (otherops[2]) > -256
8996 && INTVAL (otherops[2]) < 256)))
8998 otherops[0] = operands[1];
8999 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
9000 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
9006 otherops[0] = adjust_address (operands[0], SImode, 4);
9007 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9008 output_asm_insn ("str%?\t%1, %0", operands);
9009 output_asm_insn ("str%?\t%1, %0", otherops);
9016 /* Output an ADD r, s, #n where n may be too big for one instruction.
9017 If adding zero to one register, output nothing. */
9019 output_add_immediate (rtx *operands)
9021 HOST_WIDE_INT n = INTVAL (operands[2]);
9023 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
9026 output_multi_immediate (operands,
9027 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
9030 output_multi_immediate (operands,
9031 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
9038 /* Output a multiple immediate operation.
9039 OPERANDS is the vector of operands referred to in the output patterns.
9040 INSTR1 is the output pattern to use for the first constant.
9041 INSTR2 is the output pattern to use for subsequent constants.
9042 IMMED_OP is the index of the constant slot in OPERANDS.
9043 N is the constant value. */
9045 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
9046 int immed_op, HOST_WIDE_INT n)
9048 #if HOST_BITS_PER_WIDE_INT > 32
9054 /* Quick and easy output. */
9055 operands[immed_op] = const0_rtx;
9056 output_asm_insn (instr1, operands);
9061 const char * instr = instr1;
9063 /* Note that n is never zero here (which would give no output). */
9064 for (i = 0; i < 32; i += 2)
9068 operands[immed_op] = GEN_INT (n & (255 << i));
9069 output_asm_insn (instr, operands);
9079 /* Return the appropriate ARM instruction for the operation code.
9080 The returned result should not be overwritten. OP is the rtx of the
9081 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9084 arithmetic_instr (rtx op, int shift_first_arg)
9086 switch (GET_CODE (op))
9092 return shift_first_arg ? "rsb" : "sub";
9108 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9109 for the operation code. The returned result should not be overwritten.
9110 OP is the rtx code of the shift.
9111 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9114 shift_op (rtx op, HOST_WIDE_INT *amountp)
9117 enum rtx_code code = GET_CODE (op);
9119 switch (GET_CODE (XEXP (op, 1)))
9127 *amountp = INTVAL (XEXP (op, 1));
9149 gcc_assert (*amountp != -1);
9150 *amountp = 32 - *amountp;
9159 /* We never have to worry about the amount being other than a
9160 power of 2, since this case can never be reloaded from a reg. */
9161 gcc_assert (*amountp != -1);
9162 *amountp = int_log2 (*amountp);
9171 /* This is not 100% correct, but follows from the desire to merge
9172 multiplication by a power of 2 with the recognizer for a
9173 shift. >=32 is not a valid shift for "asl", so we must try and
9174 output a shift that produces the correct arithmetical result.
9175 Using lsr #32 is identical except for the fact that the carry bit
9176 is not set correctly if we set the flags; but we never use the
9177 carry bit from such an operation, so we can ignore that. */
9178 if (code == ROTATERT)
9179 /* Rotate is just modulo 32. */
9181 else if (*amountp != (*amountp & 31))
9188 /* Shifts of 0 are no-ops. */
9196 /* Obtain the shift from the POWER of two. */
9198 static HOST_WIDE_INT
9199 int_log2 (HOST_WIDE_INT power)
9201 HOST_WIDE_INT shift = 0;
9203 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
9205 gcc_assert (shift <= 31);
9212 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9213 because /bin/as is horribly restrictive. The judgement about
9214 whether or not each character is 'printable' (and can be output as
9215 is) or not (and must be printed with an octal escape) must be made
9216 with reference to the *host* character set -- the situation is
9217 similar to that discussed in the comments above pp_c_char in
9218 c-pretty-print.c. */
9220 #define MAX_ASCII_LEN 51
9223 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
9228 fputs ("\t.ascii\t\"", stream);
9230 for (i = 0; i < len; i++)
9234 if (len_so_far >= MAX_ASCII_LEN)
9236 fputs ("\"\n\t.ascii\t\"", stream);
9242 if (c == '\\' || c == '\"')
9244 putc ('\\', stream);
9252 fprintf (stream, "\\%03o", c);
9257 fputs ("\"\n", stream);
9260 /* Compute the register save mask for registers 0 through 12
9261 inclusive. This code is used by arm_compute_save_reg_mask. */
9263 static unsigned long
9264 arm_compute_save_reg0_reg12_mask (void)
9266 unsigned long func_type = arm_current_func_type ();
9267 unsigned long save_reg_mask = 0;
9270 if (IS_INTERRUPT (func_type))
9272 unsigned int max_reg;
9273 /* Interrupt functions must not corrupt any registers,
9274 even call clobbered ones. If this is a leaf function
9275 we can just examine the registers used by the RTL, but
9276 otherwise we have to assume that whatever function is
9277 called might clobber anything, and so we have to save
9278 all the call-clobbered registers as well. */
9279 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
9280 /* FIQ handlers have registers r8 - r12 banked, so
9281 we only need to check r0 - r7, Normal ISRs only
9282 bank r14 and r15, so we must check up to r12.
9283 r13 is the stack pointer which is always preserved,
9284 so we do not need to consider it here. */
9289 for (reg = 0; reg <= max_reg; reg++)
9290 if (regs_ever_live[reg]
9291 || (! current_function_is_leaf && call_used_regs [reg]))
9292 save_reg_mask |= (1 << reg);
9294 /* Also save the pic base register if necessary. */
9296 && !TARGET_SINGLE_PIC_BASE
9297 && arm_pic_register != INVALID_REGNUM
9298 && current_function_uses_pic_offset_table)
9299 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9303 /* In the normal case we only need to save those registers
9304 which are call saved and which are used by this function. */
9305 for (reg = 0; reg <= 10; reg++)
9306 if (regs_ever_live[reg] && ! call_used_regs [reg])
9307 save_reg_mask |= (1 << reg);
9309 /* Handle the frame pointer as a special case. */
9310 if (! TARGET_APCS_FRAME
9311 && ! frame_pointer_needed
9312 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
9313 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
9314 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9316 /* If we aren't loading the PIC register,
9317 don't stack it even though it may be live. */
9319 && !TARGET_SINGLE_PIC_BASE
9320 && arm_pic_register != INVALID_REGNUM
9321 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
9322 || current_function_uses_pic_offset_table))
9323 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9326 /* Save registers so the exception handler can modify them. */
9327 if (current_function_calls_eh_return)
9333 reg = EH_RETURN_DATA_REGNO (i);
9334 if (reg == INVALID_REGNUM)
9336 save_reg_mask |= 1 << reg;
9340 return save_reg_mask;
9343 /* Compute a bit mask of which registers need to be
9344 saved on the stack for the current function. */
9346 static unsigned long
9347 arm_compute_save_reg_mask (void)
9349 unsigned int save_reg_mask = 0;
9350 unsigned long func_type = arm_current_func_type ();
9352 if (IS_NAKED (func_type))
9353 /* This should never really happen. */
9356 /* If we are creating a stack frame, then we must save the frame pointer,
9357 IP (which will hold the old stack pointer), LR and the PC. */
9358 if (frame_pointer_needed)
9360 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
9365 /* Volatile functions do not return, so there
9366 is no need to save any other registers. */
9367 if (IS_VOLATILE (func_type))
9368 return save_reg_mask;
9370 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
9372 /* Decide if we need to save the link register.
9373 Interrupt routines have their own banked link register,
9374 so they never need to save it.
9375 Otherwise if we do not use the link register we do not need to save
9376 it. If we are pushing other registers onto the stack however, we
9377 can save an instruction in the epilogue by pushing the link register
9378 now and then popping it back into the PC. This incurs extra memory
9379 accesses though, so we only do it when optimizing for size, and only
9380 if we know that we will not need a fancy return sequence. */
9381 if (regs_ever_live [LR_REGNUM]
9384 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9385 && !current_function_calls_eh_return))
9386 save_reg_mask |= 1 << LR_REGNUM;
9388 if (cfun->machine->lr_save_eliminated)
9389 save_reg_mask &= ~ (1 << LR_REGNUM);
9391 if (TARGET_REALLY_IWMMXT
9392 && ((bit_count (save_reg_mask)
9393 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9397 /* The total number of registers that are going to be pushed
9398 onto the stack is odd. We need to ensure that the stack
9399 is 64-bit aligned before we start to save iWMMXt registers,
9400 and also before we start to create locals. (A local variable
9401 might be a double or long long which we will load/store using
9402 an iWMMXt instruction). Therefore we need to push another
9403 ARM register, so that the stack will be 64-bit aligned. We
9404 try to avoid using the arg registers (r0 -r3) as they might be
9405 used to pass values in a tail call. */
9406 for (reg = 4; reg <= 12; reg++)
9407 if ((save_reg_mask & (1 << reg)) == 0)
9411 save_reg_mask |= (1 << reg);
9414 cfun->machine->sibcall_blocked = 1;
9415 save_reg_mask |= (1 << 3);
9419 return save_reg_mask;
9423 /* Compute a bit mask of which registers need to be
9424 saved on the stack for the current function. */
9425 static unsigned long
9426 thumb_compute_save_reg_mask (void)
9432 for (reg = 0; reg < 12; reg ++)
9433 if (regs_ever_live[reg] && !call_used_regs[reg])
9437 && !TARGET_SINGLE_PIC_BASE
9438 && arm_pic_register != INVALID_REGNUM
9439 && current_function_uses_pic_offset_table)
9440 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9442 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
9443 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
9444 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
9446 /* LR will also be pushed if any lo regs are pushed. */
9447 if (mask & 0xff || thumb_force_lr_save ())
9448 mask |= (1 << LR_REGNUM);
9450 /* Make sure we have a low work register if we need one.
9451 We will need one if we are going to push a high register,
9452 but we are not currently intending to push a low register. */
9453 if ((mask & 0xff) == 0
9454 && ((mask & 0x0f00) || TARGET_BACKTRACE))
9456 /* Use thumb_find_work_register to choose which register
9457 we will use. If the register is live then we will
9458 have to push it. Use LAST_LO_REGNUM as our fallback
9459 choice for the register to select. */
9460 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
9462 if (! call_used_regs[reg])
9470 /* Return the number of bytes required to save VFP registers. */
9472 arm_get_vfp_saved_size (void)
9479 /* Space for saved VFP registers. */
9480 if (TARGET_HARD_FLOAT && TARGET_VFP)
9483 for (regno = FIRST_VFP_REGNUM;
9484 regno < LAST_VFP_REGNUM;
9487 if ((!regs_ever_live[regno] || call_used_regs[regno])
9488 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9492 /* Workaround ARM10 VFPr1 bug. */
9493 if (count == 2 && !arm_arch6)
9495 saved += count * 8 + 4;
9504 if (count == 2 && !arm_arch6)
9506 saved += count * 8 + 4;
9513 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9514 everything bar the final return instruction. */
9516 output_return_instruction (rtx operand, int really_return, int reverse)
9518 char conditional[10];
9521 unsigned long live_regs_mask;
9522 unsigned long func_type;
9523 arm_stack_offsets *offsets;
9525 func_type = arm_current_func_type ();
9527 if (IS_NAKED (func_type))
9530 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9532 /* If this function was declared non-returning, and we have
9533 found a tail call, then we have to trust that the called
9534 function won't return. */
9539 /* Otherwise, trap an attempted return by aborting. */
9541 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9543 assemble_external_libcall (ops[1]);
9544 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9550 gcc_assert (!current_function_calls_alloca || really_return);
9552 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9554 return_used_this_function = 1;
9556 live_regs_mask = arm_compute_save_reg_mask ();
9560 const char * return_reg;
9562 /* If we do not have any special requirements for function exit
9563 (e.g. interworking, or ISR) then we can load the return address
9564 directly into the PC. Otherwise we must load it into LR. */
9566 && ! TARGET_INTERWORK)
9567 return_reg = reg_names[PC_REGNUM];
9569 return_reg = reg_names[LR_REGNUM];
9571 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9573 /* There are three possible reasons for the IP register
9574 being saved. 1) a stack frame was created, in which case
9575 IP contains the old stack pointer, or 2) an ISR routine
9576 corrupted it, or 3) it was saved to align the stack on
9577 iWMMXt. In case 1, restore IP into SP, otherwise just
9579 if (frame_pointer_needed)
9581 live_regs_mask &= ~ (1 << IP_REGNUM);
9582 live_regs_mask |= (1 << SP_REGNUM);
9585 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
9588 /* On some ARM architectures it is faster to use LDR rather than
9589 LDM to load a single register. On other architectures, the
9590 cost is the same. In 26 bit mode, or for exception handlers,
9591 we have to use LDM to load the PC so that the CPSR is also
9593 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9594 if (live_regs_mask == (1U << reg))
9597 if (reg <= LAST_ARM_REGNUM
9598 && (reg != LR_REGNUM
9600 || ! IS_INTERRUPT (func_type)))
9602 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9603 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9610 /* Generate the load multiple instruction to restore the
9611 registers. Note we can get here, even if
9612 frame_pointer_needed is true, but only if sp already
9613 points to the base of the saved core registers. */
9614 if (live_regs_mask & (1 << SP_REGNUM))
9616 unsigned HOST_WIDE_INT stack_adjust;
9618 offsets = arm_get_frame_offsets ();
9619 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9620 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
9622 if (stack_adjust && arm_arch5)
9623 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9626 /* If we can't use ldmib (SA110 bug),
9627 then try to pop r3 instead. */
9629 live_regs_mask |= 1 << 3;
9630 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9634 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9636 p = instr + strlen (instr);
9638 for (reg = 0; reg <= SP_REGNUM; reg++)
9639 if (live_regs_mask & (1 << reg))
9641 int l = strlen (reg_names[reg]);
9647 memcpy (p, ", ", 2);
9651 memcpy (p, "%|", 2);
9652 memcpy (p + 2, reg_names[reg], l);
9656 if (live_regs_mask & (1 << LR_REGNUM))
9658 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9659 /* If returning from an interrupt, restore the CPSR. */
9660 if (IS_INTERRUPT (func_type))
9667 output_asm_insn (instr, & operand);
9669 /* See if we need to generate an extra instruction to
9670 perform the actual function return. */
9672 && func_type != ARM_FT_INTERWORKED
9673 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9675 /* The return has already been handled
9676 by loading the LR into the PC. */
9683 switch ((int) ARM_FUNC_TYPE (func_type))
9687 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9690 case ARM_FT_INTERWORKED:
9691 sprintf (instr, "bx%s\t%%|lr", conditional);
9694 case ARM_FT_EXCEPTION:
9695 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9699 /* Use bx if it's available. */
9700 if (arm_arch5 || arm_arch4t)
9701 sprintf (instr, "bx%s\t%%|lr", conditional);
9703 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9707 output_asm_insn (instr, & operand);
9713 /* Write the function name into the code section, directly preceding
9714 the function prologue.
9716 Code will be output similar to this:
9718 .ascii "arm_poke_function_name", 0
9721 .word 0xff000000 + (t1 - t0)
9722 arm_poke_function_name
9724 stmfd sp!, {fp, ip, lr, pc}
9727 When performing a stack backtrace, code can inspect the value
9728 of 'pc' stored at 'fp' + 0. If the trace function then looks
9729 at location pc - 12 and the top 8 bits are set, then we know
9730 that there is a function name embedded immediately preceding this
9731 location and has length ((pc[-3]) & 0xff000000).
9733 We assume that pc is declared as a pointer to an unsigned long.
9735 It is of no benefit to output the function name if we are assembling
9736 a leaf function. These function types will not contain a stack
9737 backtrace structure, therefore it is not possible to determine the
9740 arm_poke_function_name (FILE *stream, const char *name)
9742 unsigned long alignlength;
9743 unsigned long length;
9746 length = strlen (name) + 1;
9747 alignlength = ROUND_UP_WORD (length);
9749 ASM_OUTPUT_ASCII (stream, name, length);
9750 ASM_OUTPUT_ALIGN (stream, 2);
9751 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9752 assemble_aligned_integer (UNITS_PER_WORD, x);
9755 /* Place some comments into the assembler stream
9756 describing the current function. */
9758 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9760 unsigned long func_type;
9764 thumb_output_function_prologue (f, frame_size);
9769 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
9771 func_type = arm_current_func_type ();
9773 switch ((int) ARM_FUNC_TYPE (func_type))
9778 case ARM_FT_INTERWORKED:
9779 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9782 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9785 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9787 case ARM_FT_EXCEPTION:
9788 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9792 if (IS_NAKED (func_type))
9793 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9795 if (IS_VOLATILE (func_type))
9796 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9798 if (IS_NESTED (func_type))
9799 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9801 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9802 current_function_args_size,
9803 current_function_pretend_args_size, frame_size);
9805 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9806 frame_pointer_needed,
9807 cfun->machine->uses_anonymous_args);
9809 if (cfun->machine->lr_save_eliminated)
9810 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9812 if (current_function_calls_eh_return)
9813 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
9815 #ifdef AOF_ASSEMBLER
9817 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9820 return_used_this_function = 0;
9824 arm_output_epilogue (rtx sibling)
9827 unsigned long saved_regs_mask;
9828 unsigned long func_type;
9829 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9830 frame that is $fp + 4 for a non-variadic function. */
9831 int floats_offset = 0;
9833 FILE * f = asm_out_file;
9834 unsigned int lrm_count = 0;
9835 int really_return = (sibling == NULL);
9837 arm_stack_offsets *offsets;
9839 /* If we have already generated the return instruction
9840 then it is futile to generate anything else. */
9841 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9844 func_type = arm_current_func_type ();
9846 if (IS_NAKED (func_type))
9847 /* Naked functions don't have epilogues. */
9850 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9854 /* A volatile function should never return. Call abort. */
9855 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9856 assemble_external_libcall (op);
9857 output_asm_insn ("bl\t%a0", &op);
9862 /* If we are throwing an exception, then we really must be doing a
9863 return, so we can't tail-call. */
9864 gcc_assert (!current_function_calls_eh_return || really_return);
9866 offsets = arm_get_frame_offsets ();
9867 saved_regs_mask = arm_compute_save_reg_mask ();
9870 lrm_count = bit_count (saved_regs_mask);
9872 floats_offset = offsets->saved_args;
9873 /* Compute how far away the floats will be. */
9874 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9875 if (saved_regs_mask & (1 << reg))
9878 if (frame_pointer_needed)
9880 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9881 int vfp_offset = offsets->frame;
9883 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9885 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9886 if (regs_ever_live[reg] && !call_used_regs[reg])
9888 floats_offset += 12;
9889 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9890 reg, FP_REGNUM, floats_offset - vfp_offset);
9895 start_reg = LAST_FPA_REGNUM;
9897 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9899 if (regs_ever_live[reg] && !call_used_regs[reg])
9901 floats_offset += 12;
9903 /* We can't unstack more than four registers at once. */
9904 if (start_reg - reg == 3)
9906 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9907 reg, FP_REGNUM, floats_offset - vfp_offset);
9908 start_reg = reg - 1;
9913 if (reg != start_reg)
9914 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9915 reg + 1, start_reg - reg,
9916 FP_REGNUM, floats_offset - vfp_offset);
9917 start_reg = reg - 1;
9921 /* Just in case the last register checked also needs unstacking. */
9922 if (reg != start_reg)
9923 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9924 reg + 1, start_reg - reg,
9925 FP_REGNUM, floats_offset - vfp_offset);
9928 if (TARGET_HARD_FLOAT && TARGET_VFP)
9932 /* The fldmx insn does not have base+offset addressing modes,
9933 so we use IP to hold the address. */
9934 saved_size = arm_get_vfp_saved_size ();
9938 floats_offset += saved_size;
9939 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9940 FP_REGNUM, floats_offset - vfp_offset);
9942 start_reg = FIRST_VFP_REGNUM;
9943 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9945 if ((!regs_ever_live[reg] || call_used_regs[reg])
9946 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9948 if (start_reg != reg)
9949 arm_output_fldmx (f, IP_REGNUM,
9950 (start_reg - FIRST_VFP_REGNUM) / 2,
9951 (reg - start_reg) / 2);
9952 start_reg = reg + 2;
9955 if (start_reg != reg)
9956 arm_output_fldmx (f, IP_REGNUM,
9957 (start_reg - FIRST_VFP_REGNUM) / 2,
9958 (reg - start_reg) / 2);
9963 /* The frame pointer is guaranteed to be non-double-word aligned.
9964 This is because it is set to (old_stack_pointer - 4) and the
9965 old_stack_pointer was double word aligned. Thus the offset to
9966 the iWMMXt registers to be loaded must also be non-double-word
9967 sized, so that the resultant address *is* double-word aligned.
9968 We can ignore floats_offset since that was already included in
9969 the live_regs_mask. */
9970 lrm_count += (lrm_count % 2 ? 2 : 1);
9972 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9973 if (regs_ever_live[reg] && !call_used_regs[reg])
9975 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9976 reg, FP_REGNUM, lrm_count * 4);
9981 /* saved_regs_mask should contain the IP, which at the time of stack
9982 frame generation actually contains the old stack pointer. So a
9983 quick way to unwind the stack is just pop the IP register directly
9984 into the stack pointer. */
9985 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
9986 saved_regs_mask &= ~ (1 << IP_REGNUM);
9987 saved_regs_mask |= (1 << SP_REGNUM);
9989 /* There are two registers left in saved_regs_mask - LR and PC. We
9990 only need to restore the LR register (the return address), but to
9991 save time we can load it directly into the PC, unless we need a
9992 special function exit sequence, or we are not really returning. */
9994 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9995 && !current_function_calls_eh_return)
9996 /* Delete the LR from the register mask, so that the LR on
9997 the stack is loaded into the PC in the register mask. */
9998 saved_regs_mask &= ~ (1 << LR_REGNUM);
10000 saved_regs_mask &= ~ (1 << PC_REGNUM);
10002 /* We must use SP as the base register, because SP is one of the
10003 registers being restored. If an interrupt or page fault
10004 happens in the ldm instruction, the SP might or might not
10005 have been restored. That would be bad, as then SP will no
10006 longer indicate the safe area of stack, and we can get stack
10007 corruption. Using SP as the base register means that it will
10008 be reset correctly to the original value, should an interrupt
10009 occur. If the stack pointer already points at the right
10010 place, then omit the subtraction. */
10011 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
10012 || current_function_calls_alloca)
10013 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
10014 4 * bit_count (saved_regs_mask));
10015 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
10017 if (IS_INTERRUPT (func_type))
10018 /* Interrupt handlers will have pushed the
10019 IP onto the stack, so restore it now. */
10020 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
10024 /* Restore stack pointer if necessary. */
10025 if (offsets->outgoing_args != offsets->saved_regs)
10027 operands[0] = operands[1] = stack_pointer_rtx;
10028 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
10029 output_add_immediate (operands);
10032 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10034 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10035 if (regs_ever_live[reg] && !call_used_regs[reg])
10036 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
10041 start_reg = FIRST_FPA_REGNUM;
10043 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10045 if (regs_ever_live[reg] && !call_used_regs[reg])
10047 if (reg - start_reg == 3)
10049 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
10050 start_reg, SP_REGNUM);
10051 start_reg = reg + 1;
10056 if (reg != start_reg)
10057 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10058 start_reg, reg - start_reg,
10061 start_reg = reg + 1;
10065 /* Just in case the last register checked also needs unstacking. */
10066 if (reg != start_reg)
10067 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10068 start_reg, reg - start_reg, SP_REGNUM);
10071 if (TARGET_HARD_FLOAT && TARGET_VFP)
10073 start_reg = FIRST_VFP_REGNUM;
10074 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10076 if ((!regs_ever_live[reg] || call_used_regs[reg])
10077 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10079 if (start_reg != reg)
10080 arm_output_fldmx (f, SP_REGNUM,
10081 (start_reg - FIRST_VFP_REGNUM) / 2,
10082 (reg - start_reg) / 2);
10083 start_reg = reg + 2;
10086 if (start_reg != reg)
10087 arm_output_fldmx (f, SP_REGNUM,
10088 (start_reg - FIRST_VFP_REGNUM) / 2,
10089 (reg - start_reg) / 2);
10092 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10093 if (regs_ever_live[reg] && !call_used_regs[reg])
10094 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
10096 /* If we can, restore the LR into the PC. */
10097 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10099 && current_function_pretend_args_size == 0
10100 && saved_regs_mask & (1 << LR_REGNUM)
10101 && !current_function_calls_eh_return)
10103 saved_regs_mask &= ~ (1 << LR_REGNUM);
10104 saved_regs_mask |= (1 << PC_REGNUM);
10107 /* Load the registers off the stack. If we only have one register
10108 to load use the LDR instruction - it is faster. */
10109 if (saved_regs_mask == (1 << LR_REGNUM))
10111 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
10113 else if (saved_regs_mask)
10115 if (saved_regs_mask & (1 << SP_REGNUM))
10116 /* Note - write back to the stack register is not enabled
10117 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10118 in the list of registers and if we add writeback the
10119 instruction becomes UNPREDICTABLE. */
10120 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
10122 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
10125 if (current_function_pretend_args_size)
10127 /* Unwind the pre-pushed regs. */
10128 operands[0] = operands[1] = stack_pointer_rtx;
10129 operands[2] = GEN_INT (current_function_pretend_args_size);
10130 output_add_immediate (operands);
10134 /* We may have already restored PC directly from the stack. */
10135 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
10138 /* Stack adjustment for exception handler. */
10139 if (current_function_calls_eh_return)
10140 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
10141 ARM_EH_STACKADJ_REGNUM);
10143 /* Generate the return instruction. */
10144 switch ((int) ARM_FUNC_TYPE (func_type))
10148 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
10151 case ARM_FT_EXCEPTION:
10152 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10155 case ARM_FT_INTERWORKED:
10156 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10160 if (arm_arch5 || arm_arch4t)
10161 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10163 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10171 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10172 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
10174 arm_stack_offsets *offsets;
10180 /* Emit any call-via-reg trampolines that are needed for v4t support
10181 of call_reg and call_value_reg type insns. */
10182 for (regno = 0; regno < LR_REGNUM; regno++)
10184 rtx label = cfun->machine->call_via[regno];
10188 switch_to_section (function_section (current_function_decl));
10189 targetm.asm_out.internal_label (asm_out_file, "L",
10190 CODE_LABEL_NUMBER (label));
10191 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
10195 /* ??? Probably not safe to set this here, since it assumes that a
10196 function will be emitted as assembly immediately after we generate
10197 RTL for it. This does not happen for inline functions. */
10198 return_used_this_function = 0;
10202 /* We need to take into account any stack-frame rounding. */
10203 offsets = arm_get_frame_offsets ();
10205 gcc_assert (!use_return_insn (FALSE, NULL)
10206 || !return_used_this_function
10207 || offsets->saved_regs == offsets->outgoing_args
10208 || frame_pointer_needed);
10210 /* Reset the ARM-specific per-function variables. */
10211 after_arm_reorg = 0;
10215 /* Generate and emit an insn that we will recognize as a push_multi.
10216 Unfortunately, since this insn does not reflect very well the actual
10217 semantics of the operation, we need to annotate the insn for the benefit
10218 of DWARF2 frame unwind information. */
10220 emit_multi_reg_push (unsigned long mask)
10223 int num_dwarf_regs;
10227 int dwarf_par_index;
10230 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10231 if (mask & (1 << i))
10234 gcc_assert (num_regs && num_regs <= 16);
10236 /* We don't record the PC in the dwarf frame information. */
10237 num_dwarf_regs = num_regs;
10238 if (mask & (1 << PC_REGNUM))
10241 /* For the body of the insn we are going to generate an UNSPEC in
10242 parallel with several USEs. This allows the insn to be recognized
10243 by the push_multi pattern in the arm.md file. The insn looks
10244 something like this:
10247 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10248 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10249 (use (reg:SI 11 fp))
10250 (use (reg:SI 12 ip))
10251 (use (reg:SI 14 lr))
10252 (use (reg:SI 15 pc))
10255 For the frame note however, we try to be more explicit and actually
10256 show each register being stored into the stack frame, plus a (single)
10257 decrement of the stack pointer. We do it this way in order to be
10258 friendly to the stack unwinding code, which only wants to see a single
10259 stack decrement per instruction. The RTL we generate for the note looks
10260 something like this:
10263 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10264 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10265 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10266 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10267 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10270 This sequence is used both by the code to support stack unwinding for
10271 exceptions handlers and the code to generate dwarf2 frame debugging. */
10273 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
10274 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
10275 dwarf_par_index = 1;
10277 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10279 if (mask & (1 << i))
10281 reg = gen_rtx_REG (SImode, i);
10283 XVECEXP (par, 0, 0)
10284 = gen_rtx_SET (VOIDmode,
10285 gen_frame_mem (BLKmode,
10286 gen_rtx_PRE_DEC (BLKmode,
10287 stack_pointer_rtx)),
10288 gen_rtx_UNSPEC (BLKmode,
10289 gen_rtvec (1, reg),
10290 UNSPEC_PUSH_MULT));
10292 if (i != PC_REGNUM)
10294 tmp = gen_rtx_SET (VOIDmode,
10295 gen_frame_mem (SImode, stack_pointer_rtx),
10297 RTX_FRAME_RELATED_P (tmp) = 1;
10298 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
10306 for (j = 1, i++; j < num_regs; i++)
10308 if (mask & (1 << i))
10310 reg = gen_rtx_REG (SImode, i);
10312 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
10314 if (i != PC_REGNUM)
10317 = gen_rtx_SET (VOIDmode,
10318 gen_frame_mem (SImode,
10319 plus_constant (stack_pointer_rtx,
10322 RTX_FRAME_RELATED_P (tmp) = 1;
10323 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
10330 par = emit_insn (par);
10332 tmp = gen_rtx_SET (VOIDmode,
10334 plus_constant (stack_pointer_rtx, -4 * num_regs));
10335 RTX_FRAME_RELATED_P (tmp) = 1;
10336 XVECEXP (dwarf, 0, 0) = tmp;
10338 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10343 /* Calculate the size of the return value that is passed in registers. */
10345 arm_size_return_regs (void)
10347 enum machine_mode mode;
10349 if (current_function_return_rtx != 0)
10350 mode = GET_MODE (current_function_return_rtx);
10352 mode = DECL_MODE (DECL_RESULT (current_function_decl));
10354 return GET_MODE_SIZE (mode);
10358 emit_sfm (int base_reg, int count)
10365 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10366 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
10368 reg = gen_rtx_REG (XFmode, base_reg++);
10370 XVECEXP (par, 0, 0)
10371 = gen_rtx_SET (VOIDmode,
10372 gen_frame_mem (BLKmode,
10373 gen_rtx_PRE_DEC (BLKmode,
10374 stack_pointer_rtx)),
10375 gen_rtx_UNSPEC (BLKmode,
10376 gen_rtvec (1, reg),
10377 UNSPEC_PUSH_MULT));
10378 tmp = gen_rtx_SET (VOIDmode,
10379 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
10380 RTX_FRAME_RELATED_P (tmp) = 1;
10381 XVECEXP (dwarf, 0, 1) = tmp;
10383 for (i = 1; i < count; i++)
10385 reg = gen_rtx_REG (XFmode, base_reg++);
10386 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
10388 tmp = gen_rtx_SET (VOIDmode,
10389 gen_frame_mem (XFmode,
10390 plus_constant (stack_pointer_rtx,
10393 RTX_FRAME_RELATED_P (tmp) = 1;
10394 XVECEXP (dwarf, 0, i + 1) = tmp;
10397 tmp = gen_rtx_SET (VOIDmode,
10399 plus_constant (stack_pointer_rtx, -12 * count));
10401 RTX_FRAME_RELATED_P (tmp) = 1;
10402 XVECEXP (dwarf, 0, 0) = tmp;
10404 par = emit_insn (par);
10405 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10411 /* Return true if the current function needs to save/restore LR. */
10414 thumb_force_lr_save (void)
10416 return !cfun->machine->lr_save_eliminated
10417 && (!leaf_function_p ()
10418 || thumb_far_jump_used_p ()
10419 || regs_ever_live [LR_REGNUM]);
10423 /* Compute the distance from register FROM to register TO.
10424 These can be the arg pointer (26), the soft frame pointer (25),
10425 the stack pointer (13) or the hard frame pointer (11).
10426 In thumb mode r7 is used as the soft frame pointer, if needed.
10427 Typical stack layout looks like this:
10429 old stack pointer -> | |
10432 | | saved arguments for
10433 | | vararg functions
10436 hard FP & arg pointer -> | | \
10444 soft frame pointer -> | | /
10449 locals base pointer -> | | /
10454 current stack pointer -> | | /
10457 For a given function some or all of these stack components
10458 may not be needed, giving rise to the possibility of
10459 eliminating some of the registers.
10461 The values returned by this function must reflect the behavior
10462 of arm_expand_prologue() and arm_compute_save_reg_mask().
10464 The sign of the number returned reflects the direction of stack
10465 growth, so the values are positive for all eliminations except
10466 from the soft frame pointer to the hard frame pointer.
10468 SFP may point just inside the local variables block to ensure correct
10472 /* Calculate stack offsets. These are used to calculate register elimination
10473 offsets and in prologue/epilogue code. */
10475 static arm_stack_offsets *
10476 arm_get_frame_offsets (void)
10478 struct arm_stack_offsets *offsets;
10479 unsigned long func_type;
10482 HOST_WIDE_INT frame_size;
10484 offsets = &cfun->machine->stack_offsets;
10486 /* We need to know if we are a leaf function. Unfortunately, it
10487 is possible to be called after start_sequence has been called,
10488 which causes get_insns to return the insns for the sequence,
10489 not the function, which will cause leaf_function_p to return
10490 the incorrect result.
10492 to know about leaf functions once reload has completed, and the
10493 frame size cannot be changed after that time, so we can safely
10494 use the cached value. */
10496 if (reload_completed)
10499 /* Initially this is the size of the local variables. It will translated
10500 into an offset once we have determined the size of preceding data. */
10501 frame_size = ROUND_UP_WORD (get_frame_size ());
10503 leaf = leaf_function_p ();
10505 /* Space for variadic functions. */
10506 offsets->saved_args = current_function_pretend_args_size;
10508 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10512 unsigned int regno;
10514 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10516 /* We know that SP will be doubleword aligned on entry, and we must
10517 preserve that condition at any subroutine call. We also require the
10518 soft frame pointer to be doubleword aligned. */
10520 if (TARGET_REALLY_IWMMXT)
10522 /* Check for the call-saved iWMMXt registers. */
10523 for (regno = FIRST_IWMMXT_REGNUM;
10524 regno <= LAST_IWMMXT_REGNUM;
10526 if (regs_ever_live [regno] && ! call_used_regs [regno])
10530 func_type = arm_current_func_type ();
10531 if (! IS_VOLATILE (func_type))
10533 /* Space for saved FPA registers. */
10534 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10535 if (regs_ever_live[regno] && ! call_used_regs[regno])
10538 /* Space for saved VFP registers. */
10539 if (TARGET_HARD_FLOAT && TARGET_VFP)
10540 saved += arm_get_vfp_saved_size ();
10543 else /* TARGET_THUMB */
10545 saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
10546 if (TARGET_BACKTRACE)
10550 /* Saved registers include the stack frame. */
10551 offsets->saved_regs = offsets->saved_args + saved;
10552 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
10553 /* A leaf function does not need any stack alignment if it has nothing
10555 if (leaf && frame_size == 0)
10557 offsets->outgoing_args = offsets->soft_frame;
10561 /* Ensure SFP has the correct alignment. */
10562 if (ARM_DOUBLEWORD_ALIGN
10563 && (offsets->soft_frame & 7))
10564 offsets->soft_frame += 4;
10566 offsets->locals_base = offsets->soft_frame + frame_size;
10567 offsets->outgoing_args = (offsets->locals_base
10568 + current_function_outgoing_args_size);
10570 if (ARM_DOUBLEWORD_ALIGN)
10572 /* Ensure SP remains doubleword aligned. */
10573 if (offsets->outgoing_args & 7)
10574 offsets->outgoing_args += 4;
10575 gcc_assert (!(offsets->outgoing_args & 7));
10582 /* Calculate the relative offsets for the different stack pointers. Positive
10583 offsets are in the direction of stack growth. */
10586 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10588 arm_stack_offsets *offsets;
10590 offsets = arm_get_frame_offsets ();
10592 /* OK, now we have enough information to compute the distances.
10593 There must be an entry in these switch tables for each pair
10594 of registers in ELIMINABLE_REGS, even if some of the entries
10595 seem to be redundant or useless. */
10598 case ARG_POINTER_REGNUM:
10601 case THUMB_HARD_FRAME_POINTER_REGNUM:
10604 case FRAME_POINTER_REGNUM:
10605 /* This is the reverse of the soft frame pointer
10606 to hard frame pointer elimination below. */
10607 return offsets->soft_frame - offsets->saved_args;
10609 case ARM_HARD_FRAME_POINTER_REGNUM:
10610 /* If there is no stack frame then the hard
10611 frame pointer and the arg pointer coincide. */
10612 if (offsets->frame == offsets->saved_regs)
10614 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10615 return (frame_pointer_needed
10616 && cfun->static_chain_decl != NULL
10617 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10619 case STACK_POINTER_REGNUM:
10620 /* If nothing has been pushed on the stack at all
10621 then this will return -4. This *is* correct! */
10622 return offsets->outgoing_args - (offsets->saved_args + 4);
10625 gcc_unreachable ();
10627 gcc_unreachable ();
10629 case FRAME_POINTER_REGNUM:
10632 case THUMB_HARD_FRAME_POINTER_REGNUM:
10635 case ARM_HARD_FRAME_POINTER_REGNUM:
10636 /* The hard frame pointer points to the top entry in the
10637 stack frame. The soft frame pointer to the bottom entry
10638 in the stack frame. If there is no stack frame at all,
10639 then they are identical. */
10641 return offsets->frame - offsets->soft_frame;
10643 case STACK_POINTER_REGNUM:
10644 return offsets->outgoing_args - offsets->soft_frame;
10647 gcc_unreachable ();
10649 gcc_unreachable ();
10652 /* You cannot eliminate from the stack pointer.
10653 In theory you could eliminate from the hard frame
10654 pointer to the stack pointer, but this will never
10655 happen, since if a stack frame is not needed the
10656 hard frame pointer will never be used. */
10657 gcc_unreachable ();
10662 /* Generate the prologue instructions for entry into an ARM function. */
10664 arm_expand_prologue (void)
10670 unsigned long live_regs_mask;
10671 unsigned long func_type;
10673 int saved_pretend_args = 0;
10674 int saved_regs = 0;
10675 unsigned HOST_WIDE_INT args_to_push;
10676 arm_stack_offsets *offsets;
10678 func_type = arm_current_func_type ();
10680 /* Naked functions don't have prologues. */
10681 if (IS_NAKED (func_type))
10684 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10685 args_to_push = current_function_pretend_args_size;
10687 /* Compute which register we will have to save onto the stack. */
10688 live_regs_mask = arm_compute_save_reg_mask ();
10690 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10692 if (frame_pointer_needed)
10694 if (IS_INTERRUPT (func_type))
10696 /* Interrupt functions must not corrupt any registers.
10697 Creating a frame pointer however, corrupts the IP
10698 register, so we must push it first. */
10699 insn = emit_multi_reg_push (1 << IP_REGNUM);
10701 /* Do not set RTX_FRAME_RELATED_P on this insn.
10702 The dwarf stack unwinding code only wants to see one
10703 stack decrement per function, and this is not it. If
10704 this instruction is labeled as being part of the frame
10705 creation sequence then dwarf2out_frame_debug_expr will
10706 die when it encounters the assignment of IP to FP
10707 later on, since the use of SP here establishes SP as
10708 the CFA register and not IP.
10710 Anyway this instruction is not really part of the stack
10711 frame creation although it is part of the prologue. */
10713 else if (IS_NESTED (func_type))
10715 /* The Static chain register is the same as the IP register
10716 used as a scratch register during stack frame creation.
10717 To get around this need to find somewhere to store IP
10718 whilst the frame is being created. We try the following
10721 1. The last argument register.
10722 2. A slot on the stack above the frame. (This only
10723 works if the function is not a varargs function).
10724 3. Register r3, after pushing the argument registers
10727 Note - we only need to tell the dwarf2 backend about the SP
10728 adjustment in the second variant; the static chain register
10729 doesn't need to be unwound, as it doesn't contain a value
10730 inherited from the caller. */
10732 if (regs_ever_live[3] == 0)
10733 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
10734 else if (args_to_push == 0)
10738 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10739 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
10742 /* Just tell the dwarf backend that we adjusted SP. */
10743 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10744 plus_constant (stack_pointer_rtx,
10746 RTX_FRAME_RELATED_P (insn) = 1;
10747 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10748 dwarf, REG_NOTES (insn));
10752 /* Store the args on the stack. */
10753 if (cfun->machine->uses_anonymous_args)
10754 insn = emit_multi_reg_push
10755 ((0xf0 >> (args_to_push / 4)) & 0xf);
10758 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10759 GEN_INT (- args_to_push)));
10761 RTX_FRAME_RELATED_P (insn) = 1;
10763 saved_pretend_args = 1;
10764 fp_offset = args_to_push;
10767 /* Now reuse r3 to preserve IP. */
10768 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
10772 insn = emit_set_insn (ip_rtx,
10773 plus_constant (stack_pointer_rtx, fp_offset));
10774 RTX_FRAME_RELATED_P (insn) = 1;
10779 /* Push the argument registers, or reserve space for them. */
10780 if (cfun->machine->uses_anonymous_args)
10781 insn = emit_multi_reg_push
10782 ((0xf0 >> (args_to_push / 4)) & 0xf);
10785 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10786 GEN_INT (- args_to_push)));
10787 RTX_FRAME_RELATED_P (insn) = 1;
10790 /* If this is an interrupt service routine, and the link register
10791 is going to be pushed, and we are not creating a stack frame,
10792 (which would involve an extra push of IP and a pop in the epilogue)
10793 subtracting four from LR now will mean that the function return
10794 can be done with a single instruction. */
10795 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10796 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10797 && ! frame_pointer_needed)
10799 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
10801 emit_set_insn (lr, plus_constant (lr, -4));
10804 if (live_regs_mask)
10806 insn = emit_multi_reg_push (live_regs_mask);
10807 saved_regs += bit_count (live_regs_mask) * 4;
10808 RTX_FRAME_RELATED_P (insn) = 1;
10812 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10813 if (regs_ever_live[reg] && ! call_used_regs [reg])
10815 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10816 insn = gen_frame_mem (V2SImode, insn);
10817 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
10818 RTX_FRAME_RELATED_P (insn) = 1;
10822 if (! IS_VOLATILE (func_type))
10826 /* Save any floating point call-saved registers used by this
10828 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10830 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10831 if (regs_ever_live[reg] && !call_used_regs[reg])
10833 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10834 insn = gen_frame_mem (XFmode, insn);
10835 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
10836 RTX_FRAME_RELATED_P (insn) = 1;
10842 start_reg = LAST_FPA_REGNUM;
10844 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10846 if (regs_ever_live[reg] && !call_used_regs[reg])
10848 if (start_reg - reg == 3)
10850 insn = emit_sfm (reg, 4);
10851 RTX_FRAME_RELATED_P (insn) = 1;
10853 start_reg = reg - 1;
10858 if (start_reg != reg)
10860 insn = emit_sfm (reg + 1, start_reg - reg);
10861 RTX_FRAME_RELATED_P (insn) = 1;
10862 saved_regs += (start_reg - reg) * 12;
10864 start_reg = reg - 1;
10868 if (start_reg != reg)
10870 insn = emit_sfm (reg + 1, start_reg - reg);
10871 saved_regs += (start_reg - reg) * 12;
10872 RTX_FRAME_RELATED_P (insn) = 1;
10875 if (TARGET_HARD_FLOAT && TARGET_VFP)
10877 start_reg = FIRST_VFP_REGNUM;
10879 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10881 if ((!regs_ever_live[reg] || call_used_regs[reg])
10882 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10884 if (start_reg != reg)
10885 saved_regs += vfp_emit_fstmx (start_reg,
10886 (reg - start_reg) / 2);
10887 start_reg = reg + 2;
10890 if (start_reg != reg)
10891 saved_regs += vfp_emit_fstmx (start_reg,
10892 (reg - start_reg) / 2);
10896 if (frame_pointer_needed)
10898 /* Create the new frame pointer. */
10899 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10900 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10901 RTX_FRAME_RELATED_P (insn) = 1;
10903 if (IS_NESTED (func_type))
10905 /* Recover the static chain register. */
10906 if (regs_ever_live [3] == 0
10907 || saved_pretend_args)
10908 insn = gen_rtx_REG (SImode, 3);
10909 else /* if (current_function_pretend_args_size == 0) */
10911 insn = plus_constant (hard_frame_pointer_rtx, 4);
10912 insn = gen_frame_mem (SImode, insn);
10915 emit_set_insn (ip_rtx, insn);
10916 /* Add a USE to stop propagate_one_insn() from barfing. */
10917 emit_insn (gen_prologue_use (ip_rtx));
10921 offsets = arm_get_frame_offsets ();
10922 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10924 /* This add can produce multiple insns for a large constant, so we
10925 need to get tricky. */
10926 rtx last = get_last_insn ();
10928 amount = GEN_INT (offsets->saved_args + saved_regs
10929 - offsets->outgoing_args);
10931 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10935 last = last ? NEXT_INSN (last) : get_insns ();
10936 RTX_FRAME_RELATED_P (last) = 1;
10938 while (last != insn);
10940 /* If the frame pointer is needed, emit a special barrier that
10941 will prevent the scheduler from moving stores to the frame
10942 before the stack adjustment. */
10943 if (frame_pointer_needed)
10944 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10945 hard_frame_pointer_rtx));
10949 if (flag_pic && arm_pic_register != INVALID_REGNUM)
10950 arm_load_pic_register (0UL);
10952 /* If we are profiling, make sure no instructions are scheduled before
10953 the call to mcount. Similarly if the user has requested no
10954 scheduling in the prolog. Similarly if we want non-call exceptions
10955 using the EABI unwinder, to prevent faulting instructions from being
10956 swapped with a stack adjustment. */
10957 if (current_function_profile || !TARGET_SCHED_PROLOG
10958 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
10959 emit_insn (gen_blockage ());
10961 /* If the link register is being kept alive, with the return address in it,
10962 then make sure that it does not get reused by the ce2 pass. */
10963 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10965 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10966 cfun->machine->lr_save_eliminated = 1;
10970 /* If CODE is 'd', then the X is a condition operand and the instruction
10971 should only be executed if the condition is true.
10972 if CODE is 'D', then the X is a condition operand and the instruction
10973 should only be executed if the condition is false: however, if the mode
10974 of the comparison is CCFPEmode, then always execute the instruction -- we
10975 do this because in these circumstances !GE does not necessarily imply LT;
10976 in these cases the instruction pattern will take care to make sure that
10977 an instruction containing %d will follow, thereby undoing the effects of
10978 doing this instruction unconditionally.
10979 If CODE is 'N' then X is a floating point operand that must be negated
10981 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10982 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10984 arm_print_operand (FILE *stream, rtx x, int code)
10989 fputs (ASM_COMMENT_START, stream);
10993 fputs (user_label_prefix, stream);
10997 fputs (REGISTER_PREFIX, stream);
11001 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
11005 output_operand_lossage ("predicated Thumb instruction");
11008 if (current_insn_predicate != NULL)
11010 output_operand_lossage
11011 ("predicated instruction in conditional sequence");
11015 fputs (arm_condition_codes[arm_current_cc], stream);
11017 else if (current_insn_predicate)
11019 enum arm_cond_code code;
11023 output_operand_lossage ("predicated Thumb instruction");
11027 code = get_arm_condition_code (current_insn_predicate);
11028 fputs (arm_condition_codes[code], stream);
11035 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11036 r = REAL_VALUE_NEGATE (r);
11037 fprintf (stream, "%s", fp_const_from_val (&r));
11042 if (GET_CODE (x) == CONST_INT)
11045 val = ARM_SIGN_EXTEND (~INTVAL (x));
11046 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
11050 putc ('~', stream);
11051 output_addr_const (stream, x);
11056 fprintf (stream, "%s", arithmetic_instr (x, 1));
11059 /* Truncate Cirrus shift counts. */
11061 if (GET_CODE (x) == CONST_INT)
11063 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
11066 arm_print_operand (stream, x, 0);
11070 fprintf (stream, "%s", arithmetic_instr (x, 0));
11078 if (!shift_operator (x, SImode))
11080 output_operand_lossage ("invalid shift operand");
11084 shift = shift_op (x, &val);
11088 fprintf (stream, ", %s ", shift);
11090 arm_print_operand (stream, XEXP (x, 1), 0);
11092 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
11097 /* An explanation of the 'Q', 'R' and 'H' register operands:
11099 In a pair of registers containing a DI or DF value the 'Q'
11100 operand returns the register number of the register containing
11101 the least significant part of the value. The 'R' operand returns
11102 the register number of the register containing the most
11103 significant part of the value.
11105 The 'H' operand returns the higher of the two register numbers.
11106 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11107 same as the 'Q' operand, since the most significant part of the
11108 value is held in the lower number register. The reverse is true
11109 on systems where WORDS_BIG_ENDIAN is false.
11111 The purpose of these operands is to distinguish between cases
11112 where the endian-ness of the values is important (for example
11113 when they are added together), and cases where the endian-ness
11114 is irrelevant, but the order of register operations is important.
11115 For example when loading a value from memory into a register
11116 pair, the endian-ness does not matter. Provided that the value
11117 from the lower memory address is put into the lower numbered
11118 register, and the value from the higher address is put into the
11119 higher numbered register, the load will work regardless of whether
11120 the value being loaded is big-wordian or little-wordian. The
11121 order of the two register loads can matter however, if the address
11122 of the memory location is actually held in one of the registers
11123 being overwritten by the load. */
11125 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11127 output_operand_lossage ("invalid operand for code '%c'", code);
11131 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
11135 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11137 output_operand_lossage ("invalid operand for code '%c'", code);
11141 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
11145 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
11147 output_operand_lossage ("invalid operand for code '%c'", code);
11151 asm_fprintf (stream, "%r", REGNO (x) + 1);
11155 asm_fprintf (stream, "%r",
11156 GET_CODE (XEXP (x, 0)) == REG
11157 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
11161 asm_fprintf (stream, "{%r-%r}",
11163 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
11167 /* CONST_TRUE_RTX means always -- that's the default. */
11168 if (x == const_true_rtx)
11171 if (!COMPARISON_P (x))
11173 output_operand_lossage ("invalid operand for code '%c'", code);
11177 fputs (arm_condition_codes[get_arm_condition_code (x)],
11182 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
11183 want to do that. */
11184 if (x == const_true_rtx)
11186 output_operand_lossage ("instruction never exectued");
11189 if (!COMPARISON_P (x))
11191 output_operand_lossage ("invalid operand for code '%c'", code);
11195 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
11196 (get_arm_condition_code (x))],
11200 /* Cirrus registers can be accessed in a variety of ways:
11201 single floating point (f)
11202 double floating point (d)
11204 64bit integer (dx). */
11205 case 'W': /* Cirrus register in F mode. */
11206 case 'X': /* Cirrus register in D mode. */
11207 case 'Y': /* Cirrus register in FX mode. */
11208 case 'Z': /* Cirrus register in DX mode. */
11209 gcc_assert (GET_CODE (x) == REG
11210 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
11212 fprintf (stream, "mv%s%s",
11214 : code == 'X' ? "d"
11215 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
11219 /* Print cirrus register in the mode specified by the register's mode. */
11222 int mode = GET_MODE (x);
11224 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
11226 output_operand_lossage ("invalid operand for code '%c'", code);
11230 fprintf (stream, "mv%s%s",
11231 mode == DFmode ? "d"
11232 : mode == SImode ? "fx"
11233 : mode == DImode ? "dx"
11234 : "f", reg_names[REGNO (x)] + 2);
11240 if (GET_CODE (x) != REG
11241 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
11242 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
11243 /* Bad value for wCG register number. */
11245 output_operand_lossage ("invalid operand for code '%c'", code);
11250 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
11253 /* Print an iWMMXt control register name. */
11255 if (GET_CODE (x) != CONST_INT
11257 || INTVAL (x) >= 16)
11258 /* Bad value for wC register number. */
11260 output_operand_lossage ("invalid operand for code '%c'", code);
11266 static const char * wc_reg_names [16] =
11268 "wCID", "wCon", "wCSSF", "wCASF",
11269 "wC4", "wC5", "wC6", "wC7",
11270 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11271 "wC12", "wC13", "wC14", "wC15"
11274 fprintf (stream, wc_reg_names [INTVAL (x)]);
11278 /* Print a VFP double precision register name. */
11281 int mode = GET_MODE (x);
11284 if (mode != DImode && mode != DFmode)
11286 output_operand_lossage ("invalid operand for code '%c'", code);
11290 if (GET_CODE (x) != REG
11291 || !IS_VFP_REGNUM (REGNO (x)))
11293 output_operand_lossage ("invalid operand for code '%c'", code);
11297 num = REGNO(x) - FIRST_VFP_REGNUM;
11300 output_operand_lossage ("invalid operand for code '%c'", code);
11304 fprintf (stream, "d%d", num >> 1);
11311 output_operand_lossage ("missing operand");
11315 switch (GET_CODE (x))
11318 asm_fprintf (stream, "%r", REGNO (x));
11322 output_memory_reference_mode = GET_MODE (x);
11323 output_address (XEXP (x, 0));
11327 fprintf (stream, "#%s", fp_immediate_constant (x));
11331 gcc_assert (GET_CODE (x) != NEG);
11332 fputc ('#', stream);
11333 output_addr_const (stream, x);
11339 #ifndef AOF_ASSEMBLER
11340 /* Target hook for assembling integer objects. The ARM version needs to
11341 handle word-sized values specially. */
11343 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
11345 if (size == UNITS_PER_WORD && aligned_p)
11347 fputs ("\t.word\t", asm_out_file);
11348 output_addr_const (asm_out_file, x);
11350 /* Mark symbols as position independent. We only do this in the
11351 .text segment, not in the .data segment. */
11352 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
11353 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
11355 if (GET_CODE (x) == SYMBOL_REF
11356 && (CONSTANT_POOL_ADDRESS_P (x)
11357 || SYMBOL_REF_LOCAL_P (x)))
11358 fputs ("(GOTOFF)", asm_out_file);
11359 else if (GET_CODE (x) == LABEL_REF)
11360 fputs ("(GOTOFF)", asm_out_file);
11362 fputs ("(GOT)", asm_out_file);
11364 fputc ('\n', asm_out_file);
11368 if (arm_vector_mode_supported_p (GET_MODE (x)))
11372 gcc_assert (GET_CODE (x) == CONST_VECTOR);
11374 units = CONST_VECTOR_NUNITS (x);
11376 switch (GET_MODE (x))
11378 case V2SImode: size = 4; break;
11379 case V4HImode: size = 2; break;
11380 case V8QImode: size = 1; break;
11382 gcc_unreachable ();
11385 for (i = 0; i < units; i++)
11389 elt = CONST_VECTOR_ELT (x, i);
11391 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
11397 return default_assemble_integer (x, size, aligned_p);
11401 /* Add a function to the list of static constructors. */
11404 arm_elf_asm_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
11406 if (!TARGET_AAPCS_BASED)
11408 default_named_section_asm_out_constructor (symbol, priority);
11412 /* Put these in the .init_array section, using a special relocation. */
11413 switch_to_section (ctors_section);
11414 assemble_align (POINTER_SIZE);
11415 fputs ("\t.word\t", asm_out_file);
11416 output_addr_const (asm_out_file, symbol);
11417 fputs ("(target1)\n", asm_out_file);
11421 /* A finite state machine takes care of noticing whether or not instructions
11422 can be conditionally executed, and thus decrease execution time and code
11423 size by deleting branch instructions. The fsm is controlled by
11424 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11426 /* The state of the fsm controlling condition codes are:
11427 0: normal, do nothing special
11428 1: make ASM_OUTPUT_OPCODE not output this instruction
11429 2: make ASM_OUTPUT_OPCODE not output this instruction
11430 3: make instructions conditional
11431 4: make instructions conditional
11433 State transitions (state->state by whom under condition):
11434 0 -> 1 final_prescan_insn if the `target' is a label
11435 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11436 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11437 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11438 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11439 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11440 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11441 (the target insn is arm_target_insn).
11443 If the jump clobbers the conditions then we use states 2 and 4.
11445 A similar thing can be done with conditional return insns.
11447 XXX In case the `target' is an unconditional branch, this conditionalising
11448 of the instructions always reduces code size, but not always execution
11449 time. But then, I want to reduce the code size to somewhere near what
11450 /bin/cc produces. */
11452 /* Returns the index of the ARM condition code string in
11453 `arm_condition_codes'. COMPARISON should be an rtx like
11454 `(eq (...) (...))'. */
11455 static enum arm_cond_code
11456 get_arm_condition_code (rtx comparison)
11458 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
11460 enum rtx_code comp_code = GET_CODE (comparison);
11462 if (GET_MODE_CLASS (mode) != MODE_CC)
11463 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
11464 XEXP (comparison, 1));
11468 case CC_DNEmode: code = ARM_NE; goto dominance;
11469 case CC_DEQmode: code = ARM_EQ; goto dominance;
11470 case CC_DGEmode: code = ARM_GE; goto dominance;
11471 case CC_DGTmode: code = ARM_GT; goto dominance;
11472 case CC_DLEmode: code = ARM_LE; goto dominance;
11473 case CC_DLTmode: code = ARM_LT; goto dominance;
11474 case CC_DGEUmode: code = ARM_CS; goto dominance;
11475 case CC_DGTUmode: code = ARM_HI; goto dominance;
11476 case CC_DLEUmode: code = ARM_LS; goto dominance;
11477 case CC_DLTUmode: code = ARM_CC;
11480 gcc_assert (comp_code == EQ || comp_code == NE);
11482 if (comp_code == EQ)
11483 return ARM_INVERSE_CONDITION_CODE (code);
11489 case NE: return ARM_NE;
11490 case EQ: return ARM_EQ;
11491 case GE: return ARM_PL;
11492 case LT: return ARM_MI;
11493 default: gcc_unreachable ();
11499 case NE: return ARM_NE;
11500 case EQ: return ARM_EQ;
11501 default: gcc_unreachable ();
11507 case NE: return ARM_MI;
11508 case EQ: return ARM_PL;
11509 default: gcc_unreachable ();
11514 /* These encodings assume that AC=1 in the FPA system control
11515 byte. This allows us to handle all cases except UNEQ and
11519 case GE: return ARM_GE;
11520 case GT: return ARM_GT;
11521 case LE: return ARM_LS;
11522 case LT: return ARM_MI;
11523 case NE: return ARM_NE;
11524 case EQ: return ARM_EQ;
11525 case ORDERED: return ARM_VC;
11526 case UNORDERED: return ARM_VS;
11527 case UNLT: return ARM_LT;
11528 case UNLE: return ARM_LE;
11529 case UNGT: return ARM_HI;
11530 case UNGE: return ARM_PL;
11531 /* UNEQ and LTGT do not have a representation. */
11532 case UNEQ: /* Fall through. */
11533 case LTGT: /* Fall through. */
11534 default: gcc_unreachable ();
11540 case NE: return ARM_NE;
11541 case EQ: return ARM_EQ;
11542 case GE: return ARM_LE;
11543 case GT: return ARM_LT;
11544 case LE: return ARM_GE;
11545 case LT: return ARM_GT;
11546 case GEU: return ARM_LS;
11547 case GTU: return ARM_CC;
11548 case LEU: return ARM_CS;
11549 case LTU: return ARM_HI;
11550 default: gcc_unreachable ();
11556 case LTU: return ARM_CS;
11557 case GEU: return ARM_CC;
11558 default: gcc_unreachable ();
11564 case NE: return ARM_NE;
11565 case EQ: return ARM_EQ;
11566 case GE: return ARM_GE;
11567 case GT: return ARM_GT;
11568 case LE: return ARM_LE;
11569 case LT: return ARM_LT;
11570 case GEU: return ARM_CS;
11571 case GTU: return ARM_HI;
11572 case LEU: return ARM_LS;
11573 case LTU: return ARM_CC;
11574 default: gcc_unreachable ();
11577 default: gcc_unreachable ();
11582 arm_final_prescan_insn (rtx insn)
11584 /* BODY will hold the body of INSN. */
11585 rtx body = PATTERN (insn);
11587 /* This will be 1 if trying to repeat the trick, and things need to be
11588 reversed if it appears to fail. */
11591 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11592 taken are clobbered, even if the rtl suggests otherwise. It also
11593 means that we have to grub around within the jump expression to find
11594 out what the conditions are when the jump isn't taken. */
11595 int jump_clobbers = 0;
11597 /* If we start with a return insn, we only succeed if we find another one. */
11598 int seeking_return = 0;
11600 /* START_INSN will hold the insn from where we start looking. This is the
11601 first insn after the following code_label if REVERSE is true. */
11602 rtx start_insn = insn;
11604 /* If in state 4, check if the target branch is reached, in order to
11605 change back to state 0. */
11606 if (arm_ccfsm_state == 4)
11608 if (insn == arm_target_insn)
11610 arm_target_insn = NULL;
11611 arm_ccfsm_state = 0;
11616 /* If in state 3, it is possible to repeat the trick, if this insn is an
11617 unconditional branch to a label, and immediately following this branch
11618 is the previous target label which is only used once, and the label this
11619 branch jumps to is not too far off. */
11620 if (arm_ccfsm_state == 3)
11622 if (simplejump_p (insn))
11624 start_insn = next_nonnote_insn (start_insn);
11625 if (GET_CODE (start_insn) == BARRIER)
11627 /* XXX Isn't this always a barrier? */
11628 start_insn = next_nonnote_insn (start_insn);
11630 if (GET_CODE (start_insn) == CODE_LABEL
11631 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11632 && LABEL_NUSES (start_insn) == 1)
11637 else if (GET_CODE (body) == RETURN)
11639 start_insn = next_nonnote_insn (start_insn);
11640 if (GET_CODE (start_insn) == BARRIER)
11641 start_insn = next_nonnote_insn (start_insn);
11642 if (GET_CODE (start_insn) == CODE_LABEL
11643 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11644 && LABEL_NUSES (start_insn) == 1)
11647 seeking_return = 1;
11656 gcc_assert (!arm_ccfsm_state || reverse);
11657 if (GET_CODE (insn) != JUMP_INSN)
11660 /* This jump might be paralleled with a clobber of the condition codes
11661 the jump should always come first */
11662 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11663 body = XVECEXP (body, 0, 0);
11666 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11667 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11670 int fail = FALSE, succeed = FALSE;
11671 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11672 int then_not_else = TRUE;
11673 rtx this_insn = start_insn, label = 0;
11675 /* If the jump cannot be done with one instruction, we cannot
11676 conditionally execute the instruction in the inverse case. */
11677 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11683 /* Register the insn jumped to. */
11686 if (!seeking_return)
11687 label = XEXP (SET_SRC (body), 0);
11689 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11690 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11691 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11693 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11694 then_not_else = FALSE;
11696 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11697 seeking_return = 1;
11698 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11700 seeking_return = 1;
11701 then_not_else = FALSE;
11704 gcc_unreachable ();
11706 /* See how many insns this branch skips, and what kind of insns. If all
11707 insns are okay, and the label or unconditional branch to the same
11708 label is not too far away, succeed. */
11709 for (insns_skipped = 0;
11710 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11714 this_insn = next_nonnote_insn (this_insn);
11718 switch (GET_CODE (this_insn))
11721 /* Succeed if it is the target label, otherwise fail since
11722 control falls in from somewhere else. */
11723 if (this_insn == label)
11727 arm_ccfsm_state = 2;
11728 this_insn = next_nonnote_insn (this_insn);
11731 arm_ccfsm_state = 1;
11739 /* Succeed if the following insn is the target label.
11741 If return insns are used then the last insn in a function
11742 will be a barrier. */
11743 this_insn = next_nonnote_insn (this_insn);
11744 if (this_insn && this_insn == label)
11748 arm_ccfsm_state = 2;
11749 this_insn = next_nonnote_insn (this_insn);
11752 arm_ccfsm_state = 1;
11760 /* The AAPCS says that conditional calls should not be
11761 used since they make interworking inefficient (the
11762 linker can't transform BL<cond> into BLX). That's
11763 only a problem if the machine has BLX. */
11770 /* Succeed if the following insn is the target label, or
11771 if the following two insns are a barrier and the
11773 this_insn = next_nonnote_insn (this_insn);
11774 if (this_insn && GET_CODE (this_insn) == BARRIER)
11775 this_insn = next_nonnote_insn (this_insn);
11777 if (this_insn && this_insn == label
11778 && insns_skipped < max_insns_skipped)
11782 arm_ccfsm_state = 2;
11783 this_insn = next_nonnote_insn (this_insn);
11786 arm_ccfsm_state = 1;
11794 /* If this is an unconditional branch to the same label, succeed.
11795 If it is to another label, do nothing. If it is conditional,
11797 /* XXX Probably, the tests for SET and the PC are
11800 scanbody = PATTERN (this_insn);
11801 if (GET_CODE (scanbody) == SET
11802 && GET_CODE (SET_DEST (scanbody)) == PC)
11804 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11805 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11807 arm_ccfsm_state = 2;
11810 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11813 /* Fail if a conditional return is undesirable (e.g. on a
11814 StrongARM), but still allow this if optimizing for size. */
11815 else if (GET_CODE (scanbody) == RETURN
11816 && !use_return_insn (TRUE, NULL)
11819 else if (GET_CODE (scanbody) == RETURN
11822 arm_ccfsm_state = 2;
11825 else if (GET_CODE (scanbody) == PARALLEL)
11827 switch (get_attr_conds (this_insn))
11837 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
11842 /* Instructions using or affecting the condition codes make it
11844 scanbody = PATTERN (this_insn);
11845 if (!(GET_CODE (scanbody) == SET
11846 || GET_CODE (scanbody) == PARALLEL)
11847 || get_attr_conds (this_insn) != CONDS_NOCOND)
11850 /* A conditional cirrus instruction must be followed by
11851 a non Cirrus instruction. However, since we
11852 conditionalize instructions in this function and by
11853 the time we get here we can't add instructions
11854 (nops), because shorten_branches() has already been
11855 called, we will disable conditionalizing Cirrus
11856 instructions to be safe. */
11857 if (GET_CODE (scanbody) != USE
11858 && GET_CODE (scanbody) != CLOBBER
11859 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11869 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11870 arm_target_label = CODE_LABEL_NUMBER (label);
11873 gcc_assert (seeking_return || arm_ccfsm_state == 2);
11875 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11877 this_insn = next_nonnote_insn (this_insn);
11878 gcc_assert (!this_insn
11879 || (GET_CODE (this_insn) != BARRIER
11880 && GET_CODE (this_insn) != CODE_LABEL));
11884 /* Oh, dear! we ran off the end.. give up. */
11885 recog (PATTERN (insn), insn, NULL);
11886 arm_ccfsm_state = 0;
11887 arm_target_insn = NULL;
11890 arm_target_insn = this_insn;
11894 gcc_assert (!reverse);
11896 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11898 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11899 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11900 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11901 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11905 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11908 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11912 if (reverse || then_not_else)
11913 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11916 /* Restore recog_data (getting the attributes of other insns can
11917 destroy this array, but final.c assumes that it remains intact
11918 across this call; since the insn has been recognized already we
11919 call recog direct). */
11920 recog (PATTERN (insn), insn, NULL);
11924 /* Returns true if REGNO is a valid register
11925 for holding a quantity of type MODE. */
11927 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11929 if (GET_MODE_CLASS (mode) == MODE_CC)
11930 return (regno == CC_REGNUM
11931 || (TARGET_HARD_FLOAT && TARGET_VFP
11932 && regno == VFPCC_REGNUM));
11935 /* For the Thumb we only allow values bigger than SImode in
11936 registers 0 - 6, so that there is always a second low
11937 register available to hold the upper part of the value.
11938 We probably we ought to ensure that the register is the
11939 start of an even numbered register pair. */
11940 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11942 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
11943 && IS_CIRRUS_REGNUM (regno))
11944 /* We have outlawed SI values in Cirrus registers because they
11945 reside in the lower 32 bits, but SF values reside in the
11946 upper 32 bits. This causes gcc all sorts of grief. We can't
11947 even split the registers into pairs because Cirrus SI values
11948 get sign extended to 64bits-- aldyh. */
11949 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11951 if (TARGET_HARD_FLOAT && TARGET_VFP
11952 && IS_VFP_REGNUM (regno))
11954 if (mode == SFmode || mode == SImode)
11957 /* DFmode values are only valid in even register pairs. */
11958 if (mode == DFmode)
11959 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11963 if (TARGET_REALLY_IWMMXT)
11965 if (IS_IWMMXT_GR_REGNUM (regno))
11966 return mode == SImode;
11968 if (IS_IWMMXT_REGNUM (regno))
11969 return VALID_IWMMXT_REG_MODE (mode);
11972 /* We allow any value to be stored in the general registers.
11973 Restrict doubleword quantities to even register pairs so that we can
11975 if (regno <= LAST_ARM_REGNUM)
11976 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11978 if (regno == FRAME_POINTER_REGNUM
11979 || regno == ARG_POINTER_REGNUM)
11980 /* We only allow integers in the fake hard registers. */
11981 return GET_MODE_CLASS (mode) == MODE_INT;
11983 /* The only registers left are the FPA registers
11984 which we only allow to hold FP values. */
11985 return (TARGET_HARD_FLOAT && TARGET_FPA
11986 && GET_MODE_CLASS (mode) == MODE_FLOAT
11987 && regno >= FIRST_FPA_REGNUM
11988 && regno <= LAST_FPA_REGNUM);
11992 arm_regno_class (int regno)
11996 if (regno == STACK_POINTER_REGNUM)
11998 if (regno == CC_REGNUM)
12005 if ( regno <= LAST_ARM_REGNUM
12006 || regno == FRAME_POINTER_REGNUM
12007 || regno == ARG_POINTER_REGNUM)
12008 return GENERAL_REGS;
12010 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
12013 if (IS_CIRRUS_REGNUM (regno))
12014 return CIRRUS_REGS;
12016 if (IS_VFP_REGNUM (regno))
12019 if (IS_IWMMXT_REGNUM (regno))
12020 return IWMMXT_REGS;
12022 if (IS_IWMMXT_GR_REGNUM (regno))
12023 return IWMMXT_GR_REGS;
12028 /* Handle a special case when computing the offset
12029 of an argument from the frame pointer. */
12031 arm_debugger_arg_offset (int value, rtx addr)
12035 /* We are only interested if dbxout_parms() failed to compute the offset. */
12039 /* We can only cope with the case where the address is held in a register. */
12040 if (GET_CODE (addr) != REG)
12043 /* If we are using the frame pointer to point at the argument, then
12044 an offset of 0 is correct. */
12045 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
12048 /* If we are using the stack pointer to point at the
12049 argument, then an offset of 0 is correct. */
12050 if ((TARGET_THUMB || !frame_pointer_needed)
12051 && REGNO (addr) == SP_REGNUM)
12054 /* Oh dear. The argument is pointed to by a register rather
12055 than being held in a register, or being stored at a known
12056 offset from the frame pointer. Since GDB only understands
12057 those two kinds of argument we must translate the address
12058 held in the register into an offset from the frame pointer.
12059 We do this by searching through the insns for the function
12060 looking to see where this register gets its value. If the
12061 register is initialized from the frame pointer plus an offset
12062 then we are in luck and we can continue, otherwise we give up.
12064 This code is exercised by producing debugging information
12065 for a function with arguments like this:
12067 double func (double a, double b, int c, double d) {return d;}
12069 Without this code the stab for parameter 'd' will be set to
12070 an offset of 0 from the frame pointer, rather than 8. */
12072 /* The if() statement says:
12074 If the insn is a normal instruction
12075 and if the insn is setting the value in a register
12076 and if the register being set is the register holding the address of the argument
12077 and if the address is computing by an addition
12078 that involves adding to a register
12079 which is the frame pointer
12084 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12086 if ( GET_CODE (insn) == INSN
12087 && GET_CODE (PATTERN (insn)) == SET
12088 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
12089 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
12090 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
12091 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
12092 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
12095 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
12104 warning (0, "unable to compute real location of stacked parameter");
12105 value = 8; /* XXX magic hack */
12111 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
12114 if ((MASK) & insn_flags) \
12115 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
12116 BUILT_IN_MD, NULL, NULL_TREE); \
12120 struct builtin_description
12122 const unsigned int mask;
12123 const enum insn_code icode;
12124 const char * const name;
12125 const enum arm_builtins code;
12126 const enum rtx_code comparison;
12127 const unsigned int flag;
12130 static const struct builtin_description bdesc_2arg[] =
12132 #define IWMMXT_BUILTIN(code, string, builtin) \
12133 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
12134 ARM_BUILTIN_##builtin, 0, 0 },
12136 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
12137 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
12138 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
12139 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
12140 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
12141 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
12142 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
12143 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
12144 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
12145 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
12146 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
12147 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
12148 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
12149 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
12150 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
12151 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
12152 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
12153 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
12154 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
12155 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
12156 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
12157 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
12158 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
12159 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
12160 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
12161 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
12162 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
12163 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
12164 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
12165 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
12166 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
12167 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
12168 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
12169 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
12170 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
12171 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
12172 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
12173 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
12174 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
12175 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
12176 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
12177 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
12178 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
12179 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
12180 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
12181 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
12182 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
12183 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
12184 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
12185 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
12186 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
12187 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
12188 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
12189 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
12190 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
12191 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
12192 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
12193 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
12195 #define IWMMXT_BUILTIN2(code, builtin) \
12196 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12198 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
12199 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
12200 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
12201 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
12202 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
12203 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
12204 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
12205 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
12206 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
12207 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
12208 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
12209 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
12210 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
12211 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
12212 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
12213 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
12214 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
12215 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
12216 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
12217 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
12218 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
12219 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
12220 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
12221 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
12222 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
12223 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
12224 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
12225 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
12226 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
12227 IWMMXT_BUILTIN2 (rordi3, WRORDI)
12228 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
12229 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
12232 static const struct builtin_description bdesc_1arg[] =
12234 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
12235 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
12236 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
12237 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
12238 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
12239 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
12240 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
12241 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
12242 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
12243 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
12244 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
12245 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
12246 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
12247 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
12248 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
12249 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
12250 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
12251 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
12254 /* Set up all the iWMMXt builtins. This is
12255 not called if TARGET_IWMMXT is zero. */
12258 arm_init_iwmmxt_builtins (void)
12260 const struct builtin_description * d;
12262 tree endlink = void_list_node;
12264 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
12265 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
12266 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
12269 = build_function_type (integer_type_node,
12270 tree_cons (NULL_TREE, integer_type_node, endlink));
12271 tree v8qi_ftype_v8qi_v8qi_int
12272 = build_function_type (V8QI_type_node,
12273 tree_cons (NULL_TREE, V8QI_type_node,
12274 tree_cons (NULL_TREE, V8QI_type_node,
12275 tree_cons (NULL_TREE,
12278 tree v4hi_ftype_v4hi_int
12279 = build_function_type (V4HI_type_node,
12280 tree_cons (NULL_TREE, V4HI_type_node,
12281 tree_cons (NULL_TREE, integer_type_node,
12283 tree v2si_ftype_v2si_int
12284 = build_function_type (V2SI_type_node,
12285 tree_cons (NULL_TREE, V2SI_type_node,
12286 tree_cons (NULL_TREE, integer_type_node,
12288 tree v2si_ftype_di_di
12289 = build_function_type (V2SI_type_node,
12290 tree_cons (NULL_TREE, long_long_integer_type_node,
12291 tree_cons (NULL_TREE, long_long_integer_type_node,
12293 tree di_ftype_di_int
12294 = build_function_type (long_long_integer_type_node,
12295 tree_cons (NULL_TREE, long_long_integer_type_node,
12296 tree_cons (NULL_TREE, integer_type_node,
12298 tree di_ftype_di_int_int
12299 = build_function_type (long_long_integer_type_node,
12300 tree_cons (NULL_TREE, long_long_integer_type_node,
12301 tree_cons (NULL_TREE, integer_type_node,
12302 tree_cons (NULL_TREE,
12305 tree int_ftype_v8qi
12306 = build_function_type (integer_type_node,
12307 tree_cons (NULL_TREE, V8QI_type_node,
12309 tree int_ftype_v4hi
12310 = build_function_type (integer_type_node,
12311 tree_cons (NULL_TREE, V4HI_type_node,
12313 tree int_ftype_v2si
12314 = build_function_type (integer_type_node,
12315 tree_cons (NULL_TREE, V2SI_type_node,
12317 tree int_ftype_v8qi_int
12318 = build_function_type (integer_type_node,
12319 tree_cons (NULL_TREE, V8QI_type_node,
12320 tree_cons (NULL_TREE, integer_type_node,
12322 tree int_ftype_v4hi_int
12323 = build_function_type (integer_type_node,
12324 tree_cons (NULL_TREE, V4HI_type_node,
12325 tree_cons (NULL_TREE, integer_type_node,
12327 tree int_ftype_v2si_int
12328 = build_function_type (integer_type_node,
12329 tree_cons (NULL_TREE, V2SI_type_node,
12330 tree_cons (NULL_TREE, integer_type_node,
12332 tree v8qi_ftype_v8qi_int_int
12333 = build_function_type (V8QI_type_node,
12334 tree_cons (NULL_TREE, V8QI_type_node,
12335 tree_cons (NULL_TREE, integer_type_node,
12336 tree_cons (NULL_TREE,
12339 tree v4hi_ftype_v4hi_int_int
12340 = build_function_type (V4HI_type_node,
12341 tree_cons (NULL_TREE, V4HI_type_node,
12342 tree_cons (NULL_TREE, integer_type_node,
12343 tree_cons (NULL_TREE,
12346 tree v2si_ftype_v2si_int_int
12347 = build_function_type (V2SI_type_node,
12348 tree_cons (NULL_TREE, V2SI_type_node,
12349 tree_cons (NULL_TREE, integer_type_node,
12350 tree_cons (NULL_TREE,
12353 /* Miscellaneous. */
12354 tree v8qi_ftype_v4hi_v4hi
12355 = build_function_type (V8QI_type_node,
12356 tree_cons (NULL_TREE, V4HI_type_node,
12357 tree_cons (NULL_TREE, V4HI_type_node,
12359 tree v4hi_ftype_v2si_v2si
12360 = build_function_type (V4HI_type_node,
12361 tree_cons (NULL_TREE, V2SI_type_node,
12362 tree_cons (NULL_TREE, V2SI_type_node,
12364 tree v2si_ftype_v4hi_v4hi
12365 = build_function_type (V2SI_type_node,
12366 tree_cons (NULL_TREE, V4HI_type_node,
12367 tree_cons (NULL_TREE, V4HI_type_node,
12369 tree v2si_ftype_v8qi_v8qi
12370 = build_function_type (V2SI_type_node,
12371 tree_cons (NULL_TREE, V8QI_type_node,
12372 tree_cons (NULL_TREE, V8QI_type_node,
12374 tree v4hi_ftype_v4hi_di
12375 = build_function_type (V4HI_type_node,
12376 tree_cons (NULL_TREE, V4HI_type_node,
12377 tree_cons (NULL_TREE,
12378 long_long_integer_type_node,
12380 tree v2si_ftype_v2si_di
12381 = build_function_type (V2SI_type_node,
12382 tree_cons (NULL_TREE, V2SI_type_node,
12383 tree_cons (NULL_TREE,
12384 long_long_integer_type_node,
12386 tree void_ftype_int_int
12387 = build_function_type (void_type_node,
12388 tree_cons (NULL_TREE, integer_type_node,
12389 tree_cons (NULL_TREE, integer_type_node,
12392 = build_function_type (long_long_unsigned_type_node, endlink);
12394 = build_function_type (long_long_integer_type_node,
12395 tree_cons (NULL_TREE, V8QI_type_node,
12398 = build_function_type (long_long_integer_type_node,
12399 tree_cons (NULL_TREE, V4HI_type_node,
12402 = build_function_type (long_long_integer_type_node,
12403 tree_cons (NULL_TREE, V2SI_type_node,
12405 tree v2si_ftype_v4hi
12406 = build_function_type (V2SI_type_node,
12407 tree_cons (NULL_TREE, V4HI_type_node,
12409 tree v4hi_ftype_v8qi
12410 = build_function_type (V4HI_type_node,
12411 tree_cons (NULL_TREE, V8QI_type_node,
12414 tree di_ftype_di_v4hi_v4hi
12415 = build_function_type (long_long_unsigned_type_node,
12416 tree_cons (NULL_TREE,
12417 long_long_unsigned_type_node,
12418 tree_cons (NULL_TREE, V4HI_type_node,
12419 tree_cons (NULL_TREE,
12423 tree di_ftype_v4hi_v4hi
12424 = build_function_type (long_long_unsigned_type_node,
12425 tree_cons (NULL_TREE, V4HI_type_node,
12426 tree_cons (NULL_TREE, V4HI_type_node,
12429 /* Normal vector binops. */
12430 tree v8qi_ftype_v8qi_v8qi
12431 = build_function_type (V8QI_type_node,
12432 tree_cons (NULL_TREE, V8QI_type_node,
12433 tree_cons (NULL_TREE, V8QI_type_node,
12435 tree v4hi_ftype_v4hi_v4hi
12436 = build_function_type (V4HI_type_node,
12437 tree_cons (NULL_TREE, V4HI_type_node,
12438 tree_cons (NULL_TREE, V4HI_type_node,
12440 tree v2si_ftype_v2si_v2si
12441 = build_function_type (V2SI_type_node,
12442 tree_cons (NULL_TREE, V2SI_type_node,
12443 tree_cons (NULL_TREE, V2SI_type_node,
12445 tree di_ftype_di_di
12446 = build_function_type (long_long_unsigned_type_node,
12447 tree_cons (NULL_TREE, long_long_unsigned_type_node,
12448 tree_cons (NULL_TREE,
12449 long_long_unsigned_type_node,
12452 /* Add all builtins that are more or less simple operations on two
12454 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12456 /* Use one of the operands; the target can have a different mode for
12457 mask-generating compares. */
12458 enum machine_mode mode;
12464 mode = insn_data[d->icode].operand[1].mode;
12469 type = v8qi_ftype_v8qi_v8qi;
12472 type = v4hi_ftype_v4hi_v4hi;
12475 type = v2si_ftype_v2si_v2si;
12478 type = di_ftype_di_di;
12482 gcc_unreachable ();
12485 def_mbuiltin (d->mask, d->name, type, d->code);
12488 /* Add the remaining MMX insns with somewhat more complicated types. */
12489 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
12490 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
12491 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
12493 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
12494 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
12495 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
12496 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
12497 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
12498 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
12500 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
12501 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
12502 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
12503 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
12504 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
12505 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
12507 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
12508 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
12509 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
12510 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
12511 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
12512 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
12514 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
12515 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
12516 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
12517 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
12518 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
12519 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
12521 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12523 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12524 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12525 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12526 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12528 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12529 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12530 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12531 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12532 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12533 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12534 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12535 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12536 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12538 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12539 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12540 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12542 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12543 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12544 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12546 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12547 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12548 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12549 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12550 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12551 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12553 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12554 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12555 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12556 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12557 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12558 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12559 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12560 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12561 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12562 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12563 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12564 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12566 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12567 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12568 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12569 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12571 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12572 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12573 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12574 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12575 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12576 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12577 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12581 arm_init_tls_builtins (void)
12584 tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL);
12585 tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow);
12587 ftype = build_function_type (ptr_type_node, void_list_node);
12588 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
12589 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
12590 NULL, const_nothrow);
12594 arm_init_builtins (void)
12596 arm_init_tls_builtins ();
12598 if (TARGET_REALLY_IWMMXT)
12599 arm_init_iwmmxt_builtins ();
12602 /* Errors in the source file can cause expand_expr to return const0_rtx
12603 where we expect a vector. To avoid crashing, use one of the vector
12604 clear instructions. */
12607 safe_vector_operand (rtx x, enum machine_mode mode)
12609 if (x != const0_rtx)
12611 x = gen_reg_rtx (mode);
12613 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12614 : gen_rtx_SUBREG (DImode, x, 0)));
12618 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12621 arm_expand_binop_builtin (enum insn_code icode,
12622 tree arglist, rtx target)
12625 tree arg0 = TREE_VALUE (arglist);
12626 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12627 rtx op0 = expand_normal (arg0);
12628 rtx op1 = expand_normal (arg1);
12629 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12630 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12631 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12633 if (VECTOR_MODE_P (mode0))
12634 op0 = safe_vector_operand (op0, mode0);
12635 if (VECTOR_MODE_P (mode1))
12636 op1 = safe_vector_operand (op1, mode1);
12639 || GET_MODE (target) != tmode
12640 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12641 target = gen_reg_rtx (tmode);
12643 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
12645 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12646 op0 = copy_to_mode_reg (mode0, op0);
12647 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12648 op1 = copy_to_mode_reg (mode1, op1);
12650 pat = GEN_FCN (icode) (target, op0, op1);
12657 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12660 arm_expand_unop_builtin (enum insn_code icode,
12661 tree arglist, rtx target, int do_load)
12664 tree arg0 = TREE_VALUE (arglist);
12665 rtx op0 = expand_normal (arg0);
12666 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12667 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12670 || GET_MODE (target) != tmode
12671 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12672 target = gen_reg_rtx (tmode);
12674 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12677 if (VECTOR_MODE_P (mode0))
12678 op0 = safe_vector_operand (op0, mode0);
12680 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12681 op0 = copy_to_mode_reg (mode0, op0);
12684 pat = GEN_FCN (icode) (target, op0);
12691 /* Expand an expression EXP that calls a built-in function,
12692 with result going to TARGET if that's convenient
12693 (and in mode MODE if that's convenient).
12694 SUBTARGET may be used as the target for computing one of EXP's operands.
12695 IGNORE is nonzero if the value is to be ignored. */
12698 arm_expand_builtin (tree exp,
12700 rtx subtarget ATTRIBUTE_UNUSED,
12701 enum machine_mode mode ATTRIBUTE_UNUSED,
12702 int ignore ATTRIBUTE_UNUSED)
12704 const struct builtin_description * d;
12705 enum insn_code icode;
12706 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12707 tree arglist = TREE_OPERAND (exp, 1);
12715 int fcode = DECL_FUNCTION_CODE (fndecl);
12717 enum machine_mode tmode;
12718 enum machine_mode mode0;
12719 enum machine_mode mode1;
12720 enum machine_mode mode2;
12724 case ARM_BUILTIN_TEXTRMSB:
12725 case ARM_BUILTIN_TEXTRMUB:
12726 case ARM_BUILTIN_TEXTRMSH:
12727 case ARM_BUILTIN_TEXTRMUH:
12728 case ARM_BUILTIN_TEXTRMSW:
12729 case ARM_BUILTIN_TEXTRMUW:
12730 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12731 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12732 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12733 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12734 : CODE_FOR_iwmmxt_textrmw);
12736 arg0 = TREE_VALUE (arglist);
12737 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12738 op0 = expand_normal (arg0);
12739 op1 = expand_normal (arg1);
12740 tmode = insn_data[icode].operand[0].mode;
12741 mode0 = insn_data[icode].operand[1].mode;
12742 mode1 = insn_data[icode].operand[2].mode;
12744 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12745 op0 = copy_to_mode_reg (mode0, op0);
12746 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12748 /* @@@ better error message */
12749 error ("selector must be an immediate");
12750 return gen_reg_rtx (tmode);
12753 || GET_MODE (target) != tmode
12754 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12755 target = gen_reg_rtx (tmode);
12756 pat = GEN_FCN (icode) (target, op0, op1);
12762 case ARM_BUILTIN_TINSRB:
12763 case ARM_BUILTIN_TINSRH:
12764 case ARM_BUILTIN_TINSRW:
12765 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12766 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12767 : CODE_FOR_iwmmxt_tinsrw);
12768 arg0 = TREE_VALUE (arglist);
12769 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12770 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12771 op0 = expand_normal (arg0);
12772 op1 = expand_normal (arg1);
12773 op2 = expand_normal (arg2);
12774 tmode = insn_data[icode].operand[0].mode;
12775 mode0 = insn_data[icode].operand[1].mode;
12776 mode1 = insn_data[icode].operand[2].mode;
12777 mode2 = insn_data[icode].operand[3].mode;
12779 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12780 op0 = copy_to_mode_reg (mode0, op0);
12781 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12782 op1 = copy_to_mode_reg (mode1, op1);
12783 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12785 /* @@@ better error message */
12786 error ("selector must be an immediate");
12790 || GET_MODE (target) != tmode
12791 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12792 target = gen_reg_rtx (tmode);
12793 pat = GEN_FCN (icode) (target, op0, op1, op2);
12799 case ARM_BUILTIN_SETWCX:
12800 arg0 = TREE_VALUE (arglist);
12801 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12802 op0 = force_reg (SImode, expand_normal (arg0));
12803 op1 = expand_normal (arg1);
12804 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12807 case ARM_BUILTIN_GETWCX:
12808 arg0 = TREE_VALUE (arglist);
12809 op0 = expand_normal (arg0);
12810 target = gen_reg_rtx (SImode);
12811 emit_insn (gen_iwmmxt_tmrc (target, op0));
12814 case ARM_BUILTIN_WSHUFH:
12815 icode = CODE_FOR_iwmmxt_wshufh;
12816 arg0 = TREE_VALUE (arglist);
12817 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12818 op0 = expand_normal (arg0);
12819 op1 = expand_normal (arg1);
12820 tmode = insn_data[icode].operand[0].mode;
12821 mode1 = insn_data[icode].operand[1].mode;
12822 mode2 = insn_data[icode].operand[2].mode;
12824 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12825 op0 = copy_to_mode_reg (mode1, op0);
12826 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12828 /* @@@ better error message */
12829 error ("mask must be an immediate");
12833 || GET_MODE (target) != tmode
12834 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12835 target = gen_reg_rtx (tmode);
12836 pat = GEN_FCN (icode) (target, op0, op1);
12842 case ARM_BUILTIN_WSADB:
12843 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12844 case ARM_BUILTIN_WSADH:
12845 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12846 case ARM_BUILTIN_WSADBZ:
12847 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12848 case ARM_BUILTIN_WSADHZ:
12849 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12851 /* Several three-argument builtins. */
12852 case ARM_BUILTIN_WMACS:
12853 case ARM_BUILTIN_WMACU:
12854 case ARM_BUILTIN_WALIGN:
12855 case ARM_BUILTIN_TMIA:
12856 case ARM_BUILTIN_TMIAPH:
12857 case ARM_BUILTIN_TMIATT:
12858 case ARM_BUILTIN_TMIATB:
12859 case ARM_BUILTIN_TMIABT:
12860 case ARM_BUILTIN_TMIABB:
12861 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12862 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12863 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12864 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12865 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12866 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12867 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12868 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12869 : CODE_FOR_iwmmxt_walign);
12870 arg0 = TREE_VALUE (arglist);
12871 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12872 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12873 op0 = expand_normal (arg0);
12874 op1 = expand_normal (arg1);
12875 op2 = expand_normal (arg2);
12876 tmode = insn_data[icode].operand[0].mode;
12877 mode0 = insn_data[icode].operand[1].mode;
12878 mode1 = insn_data[icode].operand[2].mode;
12879 mode2 = insn_data[icode].operand[3].mode;
12881 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12882 op0 = copy_to_mode_reg (mode0, op0);
12883 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12884 op1 = copy_to_mode_reg (mode1, op1);
12885 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12886 op2 = copy_to_mode_reg (mode2, op2);
12888 || GET_MODE (target) != tmode
12889 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12890 target = gen_reg_rtx (tmode);
12891 pat = GEN_FCN (icode) (target, op0, op1, op2);
12897 case ARM_BUILTIN_WZERO:
12898 target = gen_reg_rtx (DImode);
12899 emit_insn (gen_iwmmxt_clrdi (target));
12902 case ARM_BUILTIN_THREAD_POINTER:
12903 return arm_load_tp (target);
12909 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12910 if (d->code == (const enum arm_builtins) fcode)
12911 return arm_expand_binop_builtin (d->icode, arglist, target);
12913 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12914 if (d->code == (const enum arm_builtins) fcode)
12915 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12917 /* @@@ Should really do something sensible here. */
12921 /* Return the number (counting from 0) of
12922 the least significant set bit in MASK. */
12925 number_of_first_bit_set (unsigned mask)
12930 (mask & (1 << bit)) == 0;
12937 /* Emit code to push or pop registers to or from the stack. F is the
12938 assembly file. MASK is the registers to push or pop. PUSH is
12939 nonzero if we should push, and zero if we should pop. For debugging
12940 output, if pushing, adjust CFA_OFFSET by the amount of space added
12941 to the stack. REAL_REGS should have the same number of bits set as
12942 MASK, and will be used instead (in the same order) to describe which
12943 registers were saved - this is used to mark the save slots when we
12944 push high registers after moving them to low registers. */
12946 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
12947 unsigned long real_regs)
12950 int lo_mask = mask & 0xFF;
12951 int pushed_words = 0;
12955 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
12957 /* Special case. Do not generate a POP PC statement here, do it in
12959 thumb_exit (f, -1);
12963 if (ARM_EABI_UNWIND_TABLES && push)
12965 fprintf (f, "\t.save\t{");
12966 for (regno = 0; regno < 15; regno++)
12968 if (real_regs & (1 << regno))
12970 if (real_regs & ((1 << regno) -1))
12972 asm_fprintf (f, "%r", regno);
12975 fprintf (f, "}\n");
12978 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12980 /* Look at the low registers first. */
12981 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12985 asm_fprintf (f, "%r", regno);
12987 if ((lo_mask & ~1) != 0)
12994 if (push && (mask & (1 << LR_REGNUM)))
12996 /* Catch pushing the LR. */
13000 asm_fprintf (f, "%r", LR_REGNUM);
13004 else if (!push && (mask & (1 << PC_REGNUM)))
13006 /* Catch popping the PC. */
13007 if (TARGET_INTERWORK || TARGET_BACKTRACE
13008 || current_function_calls_eh_return)
13010 /* The PC is never poped directly, instead
13011 it is popped into r3 and then BX is used. */
13012 fprintf (f, "}\n");
13014 thumb_exit (f, -1);
13023 asm_fprintf (f, "%r", PC_REGNUM);
13027 fprintf (f, "}\n");
13029 if (push && pushed_words && dwarf2out_do_frame ())
13031 char *l = dwarf2out_cfi_label ();
13032 int pushed_mask = real_regs;
13034 *cfa_offset += pushed_words * 4;
13035 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
13038 pushed_mask = real_regs;
13039 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
13041 if (pushed_mask & 1)
13042 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
13047 /* Generate code to return from a thumb function.
13048 If 'reg_containing_return_addr' is -1, then the return address is
13049 actually on the stack, at the stack pointer. */
13051 thumb_exit (FILE *f, int reg_containing_return_addr)
13053 unsigned regs_available_for_popping;
13054 unsigned regs_to_pop;
13056 unsigned available;
13060 int restore_a4 = FALSE;
13062 /* Compute the registers we need to pop. */
13066 if (reg_containing_return_addr == -1)
13068 regs_to_pop |= 1 << LR_REGNUM;
13072 if (TARGET_BACKTRACE)
13074 /* Restore the (ARM) frame pointer and stack pointer. */
13075 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
13079 /* If there is nothing to pop then just emit the BX instruction and
13081 if (pops_needed == 0)
13083 if (current_function_calls_eh_return)
13084 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
13086 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
13089 /* Otherwise if we are not supporting interworking and we have not created
13090 a backtrace structure and the function was not entered in ARM mode then
13091 just pop the return address straight into the PC. */
13092 else if (!TARGET_INTERWORK
13093 && !TARGET_BACKTRACE
13094 && !is_called_in_ARM_mode (current_function_decl)
13095 && !current_function_calls_eh_return)
13097 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
13101 /* Find out how many of the (return) argument registers we can corrupt. */
13102 regs_available_for_popping = 0;
13104 /* If returning via __builtin_eh_return, the bottom three registers
13105 all contain information needed for the return. */
13106 if (current_function_calls_eh_return)
13110 /* If we can deduce the registers used from the function's
13111 return value. This is more reliable that examining
13112 regs_ever_live[] because that will be set if the register is
13113 ever used in the function, not just if the register is used
13114 to hold a return value. */
13116 if (current_function_return_rtx != 0)
13117 mode = GET_MODE (current_function_return_rtx);
13119 mode = DECL_MODE (DECL_RESULT (current_function_decl));
13121 size = GET_MODE_SIZE (mode);
13125 /* In a void function we can use any argument register.
13126 In a function that returns a structure on the stack
13127 we can use the second and third argument registers. */
13128 if (mode == VOIDmode)
13129 regs_available_for_popping =
13130 (1 << ARG_REGISTER (1))
13131 | (1 << ARG_REGISTER (2))
13132 | (1 << ARG_REGISTER (3));
13134 regs_available_for_popping =
13135 (1 << ARG_REGISTER (2))
13136 | (1 << ARG_REGISTER (3));
13138 else if (size <= 4)
13139 regs_available_for_popping =
13140 (1 << ARG_REGISTER (2))
13141 | (1 << ARG_REGISTER (3));
13142 else if (size <= 8)
13143 regs_available_for_popping =
13144 (1 << ARG_REGISTER (3));
13147 /* Match registers to be popped with registers into which we pop them. */
13148 for (available = regs_available_for_popping,
13149 required = regs_to_pop;
13150 required != 0 && available != 0;
13151 available &= ~(available & - available),
13152 required &= ~(required & - required))
13155 /* If we have any popping registers left over, remove them. */
13157 regs_available_for_popping &= ~available;
13159 /* Otherwise if we need another popping register we can use
13160 the fourth argument register. */
13161 else if (pops_needed)
13163 /* If we have not found any free argument registers and
13164 reg a4 contains the return address, we must move it. */
13165 if (regs_available_for_popping == 0
13166 && reg_containing_return_addr == LAST_ARG_REGNUM)
13168 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
13169 reg_containing_return_addr = LR_REGNUM;
13171 else if (size > 12)
13173 /* Register a4 is being used to hold part of the return value,
13174 but we have dire need of a free, low register. */
13177 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
13180 if (reg_containing_return_addr != LAST_ARG_REGNUM)
13182 /* The fourth argument register is available. */
13183 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
13189 /* Pop as many registers as we can. */
13190 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13191 regs_available_for_popping);
13193 /* Process the registers we popped. */
13194 if (reg_containing_return_addr == -1)
13196 /* The return address was popped into the lowest numbered register. */
13197 regs_to_pop &= ~(1 << LR_REGNUM);
13199 reg_containing_return_addr =
13200 number_of_first_bit_set (regs_available_for_popping);
13202 /* Remove this register for the mask of available registers, so that
13203 the return address will not be corrupted by further pops. */
13204 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
13207 /* If we popped other registers then handle them here. */
13208 if (regs_available_for_popping)
13212 /* Work out which register currently contains the frame pointer. */
13213 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
13215 /* Move it into the correct place. */
13216 asm_fprintf (f, "\tmov\t%r, %r\n",
13217 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
13219 /* (Temporarily) remove it from the mask of popped registers. */
13220 regs_available_for_popping &= ~(1 << frame_pointer);
13221 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
13223 if (regs_available_for_popping)
13227 /* We popped the stack pointer as well,
13228 find the register that contains it. */
13229 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
13231 /* Move it into the stack register. */
13232 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
13234 /* At this point we have popped all necessary registers, so
13235 do not worry about restoring regs_available_for_popping
13236 to its correct value:
13238 assert (pops_needed == 0)
13239 assert (regs_available_for_popping == (1 << frame_pointer))
13240 assert (regs_to_pop == (1 << STACK_POINTER)) */
13244 /* Since we have just move the popped value into the frame
13245 pointer, the popping register is available for reuse, and
13246 we know that we still have the stack pointer left to pop. */
13247 regs_available_for_popping |= (1 << frame_pointer);
13251 /* If we still have registers left on the stack, but we no longer have
13252 any registers into which we can pop them, then we must move the return
13253 address into the link register and make available the register that
13255 if (regs_available_for_popping == 0 && pops_needed > 0)
13257 regs_available_for_popping |= 1 << reg_containing_return_addr;
13259 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
13260 reg_containing_return_addr);
13262 reg_containing_return_addr = LR_REGNUM;
13265 /* If we have registers left on the stack then pop some more.
13266 We know that at most we will want to pop FP and SP. */
13267 if (pops_needed > 0)
13272 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13273 regs_available_for_popping);
13275 /* We have popped either FP or SP.
13276 Move whichever one it is into the correct register. */
13277 popped_into = number_of_first_bit_set (regs_available_for_popping);
13278 move_to = number_of_first_bit_set (regs_to_pop);
13280 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
13282 regs_to_pop &= ~(1 << move_to);
13287 /* If we still have not popped everything then we must have only
13288 had one register available to us and we are now popping the SP. */
13289 if (pops_needed > 0)
13293 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13294 regs_available_for_popping);
13296 popped_into = number_of_first_bit_set (regs_available_for_popping);
13298 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
13300 assert (regs_to_pop == (1 << STACK_POINTER))
13301 assert (pops_needed == 1)
13305 /* If necessary restore the a4 register. */
13308 if (reg_containing_return_addr != LR_REGNUM)
13310 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
13311 reg_containing_return_addr = LR_REGNUM;
13314 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13317 if (current_function_calls_eh_return)
13318 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
13320 /* Return to caller. */
13321 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
13326 thumb_final_prescan_insn (rtx insn)
13328 if (flag_print_asm_name)
13329 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
13330 INSN_ADDRESSES (INSN_UID (insn)));
13334 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
13336 unsigned HOST_WIDE_INT mask = 0xff;
13339 if (val == 0) /* XXX */
13342 for (i = 0; i < 25; i++)
13343 if ((val & (mask << i)) == val)
13349 /* Returns nonzero if the current function contains,
13350 or might contain a far jump. */
13352 thumb_far_jump_used_p (void)
13356 /* This test is only important for leaf functions. */
13357 /* assert (!leaf_function_p ()); */
13359 /* If we have already decided that far jumps may be used,
13360 do not bother checking again, and always return true even if
13361 it turns out that they are not being used. Once we have made
13362 the decision that far jumps are present (and that hence the link
13363 register will be pushed onto the stack) we cannot go back on it. */
13364 if (cfun->machine->far_jump_used)
13367 /* If this function is not being called from the prologue/epilogue
13368 generation code then it must be being called from the
13369 INITIAL_ELIMINATION_OFFSET macro. */
13370 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
13372 /* In this case we know that we are being asked about the elimination
13373 of the arg pointer register. If that register is not being used,
13374 then there are no arguments on the stack, and we do not have to
13375 worry that a far jump might force the prologue to push the link
13376 register, changing the stack offsets. In this case we can just
13377 return false, since the presence of far jumps in the function will
13378 not affect stack offsets.
13380 If the arg pointer is live (or if it was live, but has now been
13381 eliminated and so set to dead) then we do have to test to see if
13382 the function might contain a far jump. This test can lead to some
13383 false negatives, since before reload is completed, then length of
13384 branch instructions is not known, so gcc defaults to returning their
13385 longest length, which in turn sets the far jump attribute to true.
13387 A false negative will not result in bad code being generated, but it
13388 will result in a needless push and pop of the link register. We
13389 hope that this does not occur too often.
13391 If we need doubleword stack alignment this could affect the other
13392 elimination offsets so we can't risk getting it wrong. */
13393 if (regs_ever_live [ARG_POINTER_REGNUM])
13394 cfun->machine->arg_pointer_live = 1;
13395 else if (!cfun->machine->arg_pointer_live)
13399 /* Check to see if the function contains a branch
13400 insn with the far jump attribute set. */
13401 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13403 if (GET_CODE (insn) == JUMP_INSN
13404 /* Ignore tablejump patterns. */
13405 && GET_CODE (PATTERN (insn)) != ADDR_VEC
13406 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
13407 && get_attr_far_jump (insn) == FAR_JUMP_YES
13410 /* Record the fact that we have decided that
13411 the function does use far jumps. */
13412 cfun->machine->far_jump_used = 1;
13420 /* Return nonzero if FUNC must be entered in ARM mode. */
13422 is_called_in_ARM_mode (tree func)
13424 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
13426 /* Ignore the problem about functions whose address is taken. */
13427 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
13431 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
13437 /* The bits which aren't usefully expanded as rtl. */
13439 thumb_unexpanded_epilogue (void)
13442 unsigned long live_regs_mask = 0;
13443 int high_regs_pushed = 0;
13444 int had_to_push_lr;
13447 if (return_used_this_function)
13450 if (IS_NAKED (arm_current_func_type ()))
13453 live_regs_mask = thumb_compute_save_reg_mask ();
13454 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13456 /* If we can deduce the registers used from the function's return value.
13457 This is more reliable that examining regs_ever_live[] because that
13458 will be set if the register is ever used in the function, not just if
13459 the register is used to hold a return value. */
13460 size = arm_size_return_regs ();
13462 /* The prolog may have pushed some high registers to use as
13463 work registers. e.g. the testsuite file:
13464 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13465 compiles to produce:
13466 push {r4, r5, r6, r7, lr}
13470 as part of the prolog. We have to undo that pushing here. */
13472 if (high_regs_pushed)
13474 unsigned long mask = live_regs_mask & 0xff;
13477 /* The available low registers depend on the size of the value we are
13485 /* Oh dear! We have no low registers into which we can pop
13488 ("no low registers available for popping high registers");
13490 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
13491 if (live_regs_mask & (1 << next_hi_reg))
13494 while (high_regs_pushed)
13496 /* Find lo register(s) into which the high register(s) can
13498 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13500 if (mask & (1 << regno))
13501 high_regs_pushed--;
13502 if (high_regs_pushed == 0)
13506 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13508 /* Pop the values into the low register(s). */
13509 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13511 /* Move the value(s) into the high registers. */
13512 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13514 if (mask & (1 << regno))
13516 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13519 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13520 if (live_regs_mask & (1 << next_hi_reg))
13525 live_regs_mask &= ~0x0f00;
13528 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
13529 live_regs_mask &= 0xff;
13531 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13533 /* Pop the return address into the PC. */
13534 if (had_to_push_lr)
13535 live_regs_mask |= 1 << PC_REGNUM;
13537 /* Either no argument registers were pushed or a backtrace
13538 structure was created which includes an adjusted stack
13539 pointer, so just pop everything. */
13540 if (live_regs_mask)
13541 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13544 /* We have either just popped the return address into the
13545 PC or it is was kept in LR for the entire function. */
13546 if (!had_to_push_lr)
13547 thumb_exit (asm_out_file, LR_REGNUM);
13551 /* Pop everything but the return address. */
13552 if (live_regs_mask)
13553 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13556 if (had_to_push_lr)
13560 /* We have no free low regs, so save one. */
13561 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
13565 /* Get the return address into a temporary register. */
13566 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13567 1 << LAST_ARG_REGNUM);
13571 /* Move the return address to lr. */
13572 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
13574 /* Restore the low register. */
13575 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
13580 regno = LAST_ARG_REGNUM;
13585 /* Remove the argument registers that were pushed onto the stack. */
13586 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13587 SP_REGNUM, SP_REGNUM,
13588 current_function_pretend_args_size);
13590 thumb_exit (asm_out_file, regno);
13596 /* Functions to save and restore machine-specific function data. */
13597 static struct machine_function *
13598 arm_init_machine_status (void)
13600 struct machine_function *machine;
13601 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13603 #if ARM_FT_UNKNOWN != 0
13604 machine->func_type = ARM_FT_UNKNOWN;
13609 /* Return an RTX indicating where the return address to the
13610 calling function can be found. */
13612 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13617 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13620 /* Do anything needed before RTL is emitted for each function. */
13622 arm_init_expanders (void)
13624 /* Arrange to initialize and mark the machine per-function status. */
13625 init_machine_status = arm_init_machine_status;
13627 /* This is to stop the combine pass optimizing away the alignment
13628 adjustment of va_arg. */
13629 /* ??? It is claimed that this should not be necessary. */
13631 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
13635 /* Like arm_compute_initial_elimination offset. Simpler because there
13636 isn't an ABI specified frame pointer for Thumb. Instead, we set it
13637 to point at the base of the local variables after static stack
13638 space for a function has been allocated. */
13641 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13643 arm_stack_offsets *offsets;
13645 offsets = arm_get_frame_offsets ();
13649 case ARG_POINTER_REGNUM:
13652 case STACK_POINTER_REGNUM:
13653 return offsets->outgoing_args - offsets->saved_args;
13655 case FRAME_POINTER_REGNUM:
13656 return offsets->soft_frame - offsets->saved_args;
13658 case ARM_HARD_FRAME_POINTER_REGNUM:
13659 return offsets->saved_regs - offsets->saved_args;
13661 case THUMB_HARD_FRAME_POINTER_REGNUM:
13662 return offsets->locals_base - offsets->saved_args;
13665 gcc_unreachable ();
13669 case FRAME_POINTER_REGNUM:
13672 case STACK_POINTER_REGNUM:
13673 return offsets->outgoing_args - offsets->soft_frame;
13675 case ARM_HARD_FRAME_POINTER_REGNUM:
13676 return offsets->saved_regs - offsets->soft_frame;
13678 case THUMB_HARD_FRAME_POINTER_REGNUM:
13679 return offsets->locals_base - offsets->soft_frame;
13682 gcc_unreachable ();
13687 gcc_unreachable ();
13692 /* Generate the rest of a function's prologue. */
13694 thumb_expand_prologue (void)
13698 HOST_WIDE_INT amount;
13699 arm_stack_offsets *offsets;
13700 unsigned long func_type;
13702 unsigned long live_regs_mask;
13704 func_type = arm_current_func_type ();
13706 /* Naked functions don't have prologues. */
13707 if (IS_NAKED (func_type))
13710 if (IS_INTERRUPT (func_type))
13712 error ("interrupt Service Routines cannot be coded in Thumb mode");
13716 live_regs_mask = thumb_compute_save_reg_mask ();
13717 /* Load the pic register before setting the frame pointer,
13718 so we can use r7 as a temporary work register. */
13719 if (flag_pic && arm_pic_register != INVALID_REGNUM)
13720 arm_load_pic_register (live_regs_mask);
13722 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
13723 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
13724 stack_pointer_rtx);
13726 offsets = arm_get_frame_offsets ();
13727 amount = offsets->outgoing_args - offsets->saved_regs;
13732 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13733 GEN_INT (- amount)));
13734 RTX_FRAME_RELATED_P (insn) = 1;
13740 /* The stack decrement is too big for an immediate value in a single
13741 insn. In theory we could issue multiple subtracts, but after
13742 three of them it becomes more space efficient to place the full
13743 value in the constant pool and load into a register. (Also the
13744 ARM debugger really likes to see only one stack decrement per
13745 function). So instead we look for a scratch register into which
13746 we can load the decrement, and then we subtract this from the
13747 stack pointer. Unfortunately on the thumb the only available
13748 scratch registers are the argument registers, and we cannot use
13749 these as they may hold arguments to the function. Instead we
13750 attempt to locate a call preserved register which is used by this
13751 function. If we can find one, then we know that it will have
13752 been pushed at the start of the prologue and so we can corrupt
13754 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13755 if (live_regs_mask & (1 << regno)
13756 && !(frame_pointer_needed
13757 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13760 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13762 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13764 /* Choose an arbitrary, non-argument low register. */
13765 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13767 /* Save it by copying it into a high, scratch register. */
13768 emit_insn (gen_movsi (spare, reg));
13769 /* Add a USE to stop propagate_one_insn() from barfing. */
13770 emit_insn (gen_prologue_use (spare));
13772 /* Decrement the stack. */
13773 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13774 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13775 stack_pointer_rtx, reg));
13776 RTX_FRAME_RELATED_P (insn) = 1;
13777 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
13778 plus_constant (stack_pointer_rtx,
13780 RTX_FRAME_RELATED_P (dwarf) = 1;
13782 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13785 /* Restore the low register's original value. */
13786 emit_insn (gen_movsi (reg, spare));
13788 /* Emit a USE of the restored scratch register, so that flow
13789 analysis will not consider the restore redundant. The
13790 register won't be used again in this function and isn't
13791 restored by the epilogue. */
13792 emit_insn (gen_prologue_use (reg));
13796 reg = gen_rtx_REG (SImode, regno);
13798 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13800 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13801 stack_pointer_rtx, reg));
13802 RTX_FRAME_RELATED_P (insn) = 1;
13803 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
13804 plus_constant (stack_pointer_rtx,
13806 RTX_FRAME_RELATED_P (dwarf) = 1;
13808 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13814 if (frame_pointer_needed)
13816 amount = offsets->outgoing_args - offsets->locals_base;
13819 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
13820 stack_pointer_rtx, GEN_INT (amount)));
13823 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
13824 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
13825 hard_frame_pointer_rtx,
13826 stack_pointer_rtx));
13827 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
13828 plus_constant (stack_pointer_rtx, amount));
13829 RTX_FRAME_RELATED_P (dwarf) = 1;
13830 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13834 RTX_FRAME_RELATED_P (insn) = 1;
13837 /* If we are profiling, make sure no instructions are scheduled before
13838 the call to mcount. Similarly if the user has requested no
13839 scheduling in the prolog. Similarly if we want non-call exceptions
13840 using the EABI unwinder, to prevent faulting instructions from being
13841 swapped with a stack adjustment. */
13842 if (current_function_profile || !TARGET_SCHED_PROLOG
13843 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
13844 emit_insn (gen_blockage ());
13846 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13847 if (live_regs_mask & 0xff)
13848 cfun->machine->lr_save_eliminated = 0;
13850 /* If the link register is being kept alive, with the return address in it,
13851 then make sure that it does not get reused by the ce2 pass. */
13852 if (cfun->machine->lr_save_eliminated)
13853 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13858 thumb_expand_epilogue (void)
13860 HOST_WIDE_INT amount;
13861 arm_stack_offsets *offsets;
13864 /* Naked functions don't have prologues. */
13865 if (IS_NAKED (arm_current_func_type ()))
13868 offsets = arm_get_frame_offsets ();
13869 amount = offsets->outgoing_args - offsets->saved_regs;
13871 if (frame_pointer_needed)
13873 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13874 amount = offsets->locals_base - offsets->saved_regs;
13880 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13881 GEN_INT (amount)));
13884 /* r3 is always free in the epilogue. */
13885 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13887 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13888 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13892 /* Emit a USE (stack_pointer_rtx), so that
13893 the stack adjustment will not be deleted. */
13894 emit_insn (gen_prologue_use (stack_pointer_rtx));
13896 if (current_function_profile || !TARGET_SCHED_PROLOG)
13897 emit_insn (gen_blockage ());
13899 /* Emit a clobber for each insn that will be restored in the epilogue,
13900 so that flow2 will get register lifetimes correct. */
13901 for (regno = 0; regno < 13; regno++)
13902 if (regs_ever_live[regno] && !call_used_regs[regno])
13903 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13905 if (! regs_ever_live[LR_REGNUM])
13906 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13910 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13912 unsigned long live_regs_mask = 0;
13913 unsigned long l_mask;
13914 unsigned high_regs_pushed = 0;
13915 int cfa_offset = 0;
13918 if (IS_NAKED (arm_current_func_type ()))
13921 if (is_called_in_ARM_mode (current_function_decl))
13925 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
13926 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
13928 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13930 /* Generate code sequence to switch us into Thumb mode. */
13931 /* The .code 32 directive has already been emitted by
13932 ASM_DECLARE_FUNCTION_NAME. */
13933 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13934 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13936 /* Generate a label, so that the debugger will notice the
13937 change in instruction sets. This label is also used by
13938 the assembler to bypass the ARM code when this function
13939 is called from a Thumb encoded function elsewhere in the
13940 same file. Hence the definition of STUB_NAME here must
13941 agree with the definition in gas/config/tc-arm.c. */
13943 #define STUB_NAME ".real_start_of"
13945 fprintf (f, "\t.code\t16\n");
13947 if (arm_dllexport_name_p (name))
13948 name = arm_strip_name_encoding (name);
13950 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13951 fprintf (f, "\t.thumb_func\n");
13952 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13955 if (current_function_pretend_args_size)
13957 /* Output unwind directive for the stack adjustment. */
13958 if (ARM_EABI_UNWIND_TABLES)
13959 fprintf (f, "\t.pad #%d\n",
13960 current_function_pretend_args_size);
13962 if (cfun->machine->uses_anonymous_args)
13966 fprintf (f, "\tpush\t{");
13968 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13970 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13971 regno <= LAST_ARG_REGNUM;
13973 asm_fprintf (f, "%r%s", regno,
13974 regno == LAST_ARG_REGNUM ? "" : ", ");
13976 fprintf (f, "}\n");
13979 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13980 SP_REGNUM, SP_REGNUM,
13981 current_function_pretend_args_size);
13983 /* We don't need to record the stores for unwinding (would it
13984 help the debugger any if we did?), but record the change in
13985 the stack pointer. */
13986 if (dwarf2out_do_frame ())
13988 char *l = dwarf2out_cfi_label ();
13990 cfa_offset = cfa_offset + current_function_pretend_args_size;
13991 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13995 /* Get the registers we are going to push. */
13996 live_regs_mask = thumb_compute_save_reg_mask ();
13997 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
13998 l_mask = live_regs_mask & 0x40ff;
13999 /* Then count how many other high registers will need to be pushed. */
14000 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14002 if (TARGET_BACKTRACE)
14005 unsigned work_register;
14007 /* We have been asked to create a stack backtrace structure.
14008 The code looks like this:
14012 0 sub SP, #16 Reserve space for 4 registers.
14013 2 push {R7} Push low registers.
14014 4 add R7, SP, #20 Get the stack pointer before the push.
14015 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
14016 8 mov R7, PC Get hold of the start of this code plus 12.
14017 10 str R7, [SP, #16] Store it.
14018 12 mov R7, FP Get hold of the current frame pointer.
14019 14 str R7, [SP, #4] Store it.
14020 16 mov R7, LR Get hold of the current return address.
14021 18 str R7, [SP, #12] Store it.
14022 20 add R7, SP, #16 Point at the start of the backtrace structure.
14023 22 mov FP, R7 Put this value into the frame pointer. */
14025 work_register = thumb_find_work_register (live_regs_mask);
14027 if (ARM_EABI_UNWIND_TABLES)
14028 asm_fprintf (f, "\t.pad #16\n");
14031 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
14032 SP_REGNUM, SP_REGNUM);
14034 if (dwarf2out_do_frame ())
14036 char *l = dwarf2out_cfi_label ();
14038 cfa_offset = cfa_offset + 16;
14039 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
14044 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14045 offset = bit_count (l_mask) * UNITS_PER_WORD;
14050 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14051 offset + 16 + current_function_pretend_args_size);
14053 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14056 /* Make sure that the instruction fetching the PC is in the right place
14057 to calculate "start of backtrace creation code + 12". */
14060 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14061 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14063 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14064 ARM_HARD_FRAME_POINTER_REGNUM);
14065 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14070 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
14071 ARM_HARD_FRAME_POINTER_REGNUM);
14072 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14074 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
14075 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14079 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
14080 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
14082 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
14084 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
14085 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
14087 /* Optimization: If we are not pushing any low registers but we are going
14088 to push some high registers then delay our first push. This will just
14089 be a push of LR and we can combine it with the push of the first high
14091 else if ((l_mask & 0xff) != 0
14092 || (high_regs_pushed == 0 && l_mask))
14093 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
14095 if (high_regs_pushed)
14097 unsigned pushable_regs;
14098 unsigned next_hi_reg;
14100 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
14101 if (live_regs_mask & (1 << next_hi_reg))
14104 pushable_regs = l_mask & 0xff;
14106 if (pushable_regs == 0)
14107 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
14109 while (high_regs_pushed > 0)
14111 unsigned long real_regs_mask = 0;
14113 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
14115 if (pushable_regs & (1 << regno))
14117 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
14119 high_regs_pushed --;
14120 real_regs_mask |= (1 << next_hi_reg);
14122 if (high_regs_pushed)
14124 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
14126 if (live_regs_mask & (1 << next_hi_reg))
14131 pushable_regs &= ~((1 << regno) - 1);
14137 /* If we had to find a work register and we have not yet
14138 saved the LR then add it to the list of regs to push. */
14139 if (l_mask == (1 << LR_REGNUM))
14141 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
14143 real_regs_mask | (1 << LR_REGNUM));
14147 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
14152 /* Handle the case of a double word load into a low register from
14153 a computed memory address. The computed address may involve a
14154 register which is overwritten by the load. */
14156 thumb_load_double_from_address (rtx *operands)
14164 gcc_assert (GET_CODE (operands[0]) == REG);
14165 gcc_assert (GET_CODE (operands[1]) == MEM);
14167 /* Get the memory address. */
14168 addr = XEXP (operands[1], 0);
14170 /* Work out how the memory address is computed. */
14171 switch (GET_CODE (addr))
14174 operands[2] = adjust_address (operands[1], SImode, 4);
14176 if (REGNO (operands[0]) == REGNO (addr))
14178 output_asm_insn ("ldr\t%H0, %2", operands);
14179 output_asm_insn ("ldr\t%0, %1", operands);
14183 output_asm_insn ("ldr\t%0, %1", operands);
14184 output_asm_insn ("ldr\t%H0, %2", operands);
14189 /* Compute <address> + 4 for the high order load. */
14190 operands[2] = adjust_address (operands[1], SImode, 4);
14192 output_asm_insn ("ldr\t%0, %1", operands);
14193 output_asm_insn ("ldr\t%H0, %2", operands);
14197 arg1 = XEXP (addr, 0);
14198 arg2 = XEXP (addr, 1);
14200 if (CONSTANT_P (arg1))
14201 base = arg2, offset = arg1;
14203 base = arg1, offset = arg2;
14205 gcc_assert (GET_CODE (base) == REG);
14207 /* Catch the case of <address> = <reg> + <reg> */
14208 if (GET_CODE (offset) == REG)
14210 int reg_offset = REGNO (offset);
14211 int reg_base = REGNO (base);
14212 int reg_dest = REGNO (operands[0]);
14214 /* Add the base and offset registers together into the
14215 higher destination register. */
14216 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
14217 reg_dest + 1, reg_base, reg_offset);
14219 /* Load the lower destination register from the address in
14220 the higher destination register. */
14221 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
14222 reg_dest, reg_dest + 1);
14224 /* Load the higher destination register from its own address
14226 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
14227 reg_dest + 1, reg_dest + 1);
14231 /* Compute <address> + 4 for the high order load. */
14232 operands[2] = adjust_address (operands[1], SImode, 4);
14234 /* If the computed address is held in the low order register
14235 then load the high order register first, otherwise always
14236 load the low order register first. */
14237 if (REGNO (operands[0]) == REGNO (base))
14239 output_asm_insn ("ldr\t%H0, %2", operands);
14240 output_asm_insn ("ldr\t%0, %1", operands);
14244 output_asm_insn ("ldr\t%0, %1", operands);
14245 output_asm_insn ("ldr\t%H0, %2", operands);
14251 /* With no registers to worry about we can just load the value
14253 operands[2] = adjust_address (operands[1], SImode, 4);
14255 output_asm_insn ("ldr\t%H0, %2", operands);
14256 output_asm_insn ("ldr\t%0, %1", operands);
14260 gcc_unreachable ();
14267 thumb_output_move_mem_multiple (int n, rtx *operands)
14274 if (REGNO (operands[4]) > REGNO (operands[5]))
14277 operands[4] = operands[5];
14280 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
14281 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
14285 if (REGNO (operands[4]) > REGNO (operands[5]))
14288 operands[4] = operands[5];
14291 if (REGNO (operands[5]) > REGNO (operands[6]))
14294 operands[5] = operands[6];
14297 if (REGNO (operands[4]) > REGNO (operands[5]))
14300 operands[4] = operands[5];
14304 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
14305 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
14309 gcc_unreachable ();
14315 /* Output a call-via instruction for thumb state. */
14317 thumb_call_via_reg (rtx reg)
14319 int regno = REGNO (reg);
14322 gcc_assert (regno < LR_REGNUM);
14324 /* If we are in the normal text section we can use a single instance
14325 per compilation unit. If we are doing function sections, then we need
14326 an entry per section, since we can't rely on reachability. */
14327 if (in_section == text_section)
14329 thumb_call_reg_needed = 1;
14331 if (thumb_call_via_label[regno] == NULL)
14332 thumb_call_via_label[regno] = gen_label_rtx ();
14333 labelp = thumb_call_via_label + regno;
14337 if (cfun->machine->call_via[regno] == NULL)
14338 cfun->machine->call_via[regno] = gen_label_rtx ();
14339 labelp = cfun->machine->call_via + regno;
14342 output_asm_insn ("bl\t%a0", labelp);
14346 /* Routines for generating rtl. */
14348 thumb_expand_movmemqi (rtx *operands)
14350 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
14351 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
14352 HOST_WIDE_INT len = INTVAL (operands[2]);
14353 HOST_WIDE_INT offset = 0;
14357 emit_insn (gen_movmem12b (out, in, out, in));
14363 emit_insn (gen_movmem8b (out, in, out, in));
14369 rtx reg = gen_reg_rtx (SImode);
14370 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
14371 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
14378 rtx reg = gen_reg_rtx (HImode);
14379 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
14380 plus_constant (in, offset))));
14381 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
14389 rtx reg = gen_reg_rtx (QImode);
14390 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
14391 plus_constant (in, offset))));
14392 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
14398 thumb_reload_out_hi (rtx *operands)
14400 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
14403 /* Handle reading a half-word from memory during reload. */
14405 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
14407 gcc_unreachable ();
14410 /* Return the length of a function name prefix
14411 that starts with the character 'c'. */
14413 arm_get_strip_length (int c)
14417 ARM_NAME_ENCODING_LENGTHS
14422 /* Return a pointer to a function's name with any
14423 and all prefix encodings stripped from it. */
14425 arm_strip_name_encoding (const char *name)
14429 while ((skip = arm_get_strip_length (* name)))
14435 /* If there is a '*' anywhere in the name's prefix, then
14436 emit the stripped name verbatim, otherwise prepend an
14437 underscore if leading underscores are being used. */
14439 arm_asm_output_labelref (FILE *stream, const char *name)
14444 while ((skip = arm_get_strip_length (* name)))
14446 verbatim |= (*name == '*');
14451 fputs (name, stream);
14453 asm_fprintf (stream, "%U%s", name);
14457 arm_file_end (void)
14461 if (! thumb_call_reg_needed)
14464 switch_to_section (text_section);
14465 asm_fprintf (asm_out_file, "\t.code 16\n");
14466 ASM_OUTPUT_ALIGN (asm_out_file, 1);
14468 for (regno = 0; regno < LR_REGNUM; regno++)
14470 rtx label = thumb_call_via_label[regno];
14474 targetm.asm_out.internal_label (asm_out_file, "L",
14475 CODE_LABEL_NUMBER (label));
14476 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
14483 #ifdef AOF_ASSEMBLER
14484 /* Special functions only needed when producing AOF syntax assembler. */
14488 struct pic_chain * next;
14489 const char * symname;
14492 static struct pic_chain * aof_pic_chain = NULL;
14495 aof_pic_entry (rtx x)
14497 struct pic_chain ** chainp;
14500 if (aof_pic_label == NULL_RTX)
14502 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
14505 for (offset = 0, chainp = &aof_pic_chain; *chainp;
14506 offset += 4, chainp = &(*chainp)->next)
14507 if ((*chainp)->symname == XSTR (x, 0))
14508 return plus_constant (aof_pic_label, offset);
14510 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
14511 (*chainp)->next = NULL;
14512 (*chainp)->symname = XSTR (x, 0);
14513 return plus_constant (aof_pic_label, offset);
14517 aof_dump_pic_table (FILE *f)
14519 struct pic_chain * chain;
14521 if (aof_pic_chain == NULL)
14524 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
14525 PIC_OFFSET_TABLE_REGNUM,
14526 PIC_OFFSET_TABLE_REGNUM);
14527 fputs ("|x$adcons|\n", f);
14529 for (chain = aof_pic_chain; chain; chain = chain->next)
14531 fputs ("\tDCD\t", f);
14532 assemble_name (f, chain->symname);
14537 int arm_text_section_count = 1;
14539 /* A get_unnamed_section callback for switching to the text section. */
14542 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
14544 fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY",
14545 arm_text_section_count++);
14547 fprintf (asm_out_file, ", PIC, REENTRANT");
14548 fprintf (asm_out_file, "\n");
14551 static int arm_data_section_count = 1;
14553 /* A get_unnamed_section callback for switching to the data section. */
14556 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
14558 fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n",
14559 arm_data_section_count++);
14562 /* Implement TARGET_ASM_INIT_SECTIONS.
14564 AOF Assembler syntax is a nightmare when it comes to areas, since once
14565 we change from one area to another, we can't go back again. Instead,
14566 we must create a new area with the same attributes and add the new output
14567 to that. Unfortunately, there is nothing we can do here to guarantee that
14568 two areas with the same attributes will be linked adjacently in the
14569 resulting executable, so we have to be careful not to do pc-relative
14570 addressing across such boundaries. */
14573 aof_asm_init_sections (void)
14575 text_section = get_unnamed_section (SECTION_CODE,
14576 aof_output_text_section_asm_op, NULL);
14577 data_section = get_unnamed_section (SECTION_WRITE,
14578 aof_output_data_section_asm_op, NULL);
14579 readonly_data_section = text_section;
14583 zero_init_section (void)
14585 static int zero_init_count = 1;
14587 fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++);
14591 /* The AOF assembler is religiously strict about declarations of
14592 imported and exported symbols, so that it is impossible to declare
14593 a function as imported near the beginning of the file, and then to
14594 export it later on. It is, however, possible to delay the decision
14595 until all the functions in the file have been compiled. To get
14596 around this, we maintain a list of the imports and exports, and
14597 delete from it any that are subsequently defined. At the end of
14598 compilation we spit the remainder of the list out before the END
14603 struct import * next;
14607 static struct import * imports_list = NULL;
14610 aof_add_import (const char *name)
14612 struct import * new;
14614 for (new = imports_list; new; new = new->next)
14615 if (new->name == name)
14618 new = (struct import *) xmalloc (sizeof (struct import));
14619 new->next = imports_list;
14620 imports_list = new;
14625 aof_delete_import (const char *name)
14627 struct import ** old;
14629 for (old = &imports_list; *old; old = & (*old)->next)
14631 if ((*old)->name == name)
14633 *old = (*old)->next;
14639 int arm_main_function = 0;
14642 aof_dump_imports (FILE *f)
14644 /* The AOF assembler needs this to cause the startup code to be extracted
14645 from the library. Brining in __main causes the whole thing to work
14647 if (arm_main_function)
14649 switch_to_section (text_section);
14650 fputs ("\tIMPORT __main\n", f);
14651 fputs ("\tDCD __main\n", f);
14654 /* Now dump the remaining imports. */
14655 while (imports_list)
14657 fprintf (f, "\tIMPORT\t");
14658 assemble_name (f, imports_list->name);
14660 imports_list = imports_list->next;
14665 aof_globalize_label (FILE *stream, const char *name)
14667 default_globalize_label (stream, name);
14668 if (! strcmp (name, "main"))
14669 arm_main_function = 1;
14673 aof_file_start (void)
14675 fputs ("__r0\tRN\t0\n", asm_out_file);
14676 fputs ("__a1\tRN\t0\n", asm_out_file);
14677 fputs ("__a2\tRN\t1\n", asm_out_file);
14678 fputs ("__a3\tRN\t2\n", asm_out_file);
14679 fputs ("__a4\tRN\t3\n", asm_out_file);
14680 fputs ("__v1\tRN\t4\n", asm_out_file);
14681 fputs ("__v2\tRN\t5\n", asm_out_file);
14682 fputs ("__v3\tRN\t6\n", asm_out_file);
14683 fputs ("__v4\tRN\t7\n", asm_out_file);
14684 fputs ("__v5\tRN\t8\n", asm_out_file);
14685 fputs ("__v6\tRN\t9\n", asm_out_file);
14686 fputs ("__sl\tRN\t10\n", asm_out_file);
14687 fputs ("__fp\tRN\t11\n", asm_out_file);
14688 fputs ("__ip\tRN\t12\n", asm_out_file);
14689 fputs ("__sp\tRN\t13\n", asm_out_file);
14690 fputs ("__lr\tRN\t14\n", asm_out_file);
14691 fputs ("__pc\tRN\t15\n", asm_out_file);
14692 fputs ("__f0\tFN\t0\n", asm_out_file);
14693 fputs ("__f1\tFN\t1\n", asm_out_file);
14694 fputs ("__f2\tFN\t2\n", asm_out_file);
14695 fputs ("__f3\tFN\t3\n", asm_out_file);
14696 fputs ("__f4\tFN\t4\n", asm_out_file);
14697 fputs ("__f5\tFN\t5\n", asm_out_file);
14698 fputs ("__f6\tFN\t6\n", asm_out_file);
14699 fputs ("__f7\tFN\t7\n", asm_out_file);
14700 switch_to_section (text_section);
14704 aof_file_end (void)
14707 aof_dump_pic_table (asm_out_file);
14709 aof_dump_imports (asm_out_file);
14710 fputs ("\tEND\n", asm_out_file);
14712 #endif /* AOF_ASSEMBLER */
14715 /* Symbols in the text segment can be accessed without indirecting via the
14716 constant pool; it may take an extra binary operation, but this is still
14717 faster than indirecting via memory. Don't do this when not optimizing,
14718 since we won't be calculating al of the offsets necessary to do this
14722 arm_encode_section_info (tree decl, rtx rtl, int first)
14724 /* This doesn't work with AOF syntax, since the string table may be in
14725 a different AREA. */
14726 #ifndef AOF_ASSEMBLER
14727 if (optimize > 0 && TREE_CONSTANT (decl))
14728 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14731 /* If we are referencing a function that is weak then encode a long call
14732 flag in the function name, otherwise if the function is static or
14733 or known to be defined in this file then encode a short call flag. */
14734 if (first && DECL_P (decl))
14736 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14737 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14738 else if (! TREE_PUBLIC (decl))
14739 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14742 default_encode_section_info (decl, rtl, first);
14744 #endif /* !ARM_PE */
14747 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14749 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14750 && !strcmp (prefix, "L"))
14752 arm_ccfsm_state = 0;
14753 arm_target_insn = NULL;
14755 default_internal_label (stream, prefix, labelno);
14758 /* Output code to add DELTA to the first argument, and then jump
14759 to FUNCTION. Used for C++ multiple inheritance. */
14761 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14762 HOST_WIDE_INT delta,
14763 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14766 static int thunk_label = 0;
14769 int mi_delta = delta;
14770 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14772 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14775 mi_delta = - mi_delta;
14778 int labelno = thunk_label++;
14779 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14780 fputs ("\tldr\tr12, ", file);
14781 assemble_name (file, label);
14782 fputc ('\n', file);
14785 /* If we are generating PIC, the ldr instruction below loads
14786 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
14787 the address of the add + 8, so we have:
14789 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
14792 Note that we have "+ 1" because some versions of GNU ld
14793 don't set the low bit of the result for R_ARM_REL32
14794 relocations against thumb function symbols. */
14795 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
14796 assemble_name (file, labelpc);
14797 fputs (":\n", file);
14798 fputs ("\tadd\tr12, pc, r12\n", file);
14801 while (mi_delta != 0)
14803 if ((mi_delta & (3 << shift)) == 0)
14807 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14808 mi_op, this_regno, this_regno,
14809 mi_delta & (0xff << shift));
14810 mi_delta &= ~(0xff << shift);
14816 fprintf (file, "\tbx\tr12\n");
14817 ASM_OUTPUT_ALIGN (file, 2);
14818 assemble_name (file, label);
14819 fputs (":\n", file);
14822 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
14823 rtx tem = XEXP (DECL_RTL (function), 0);
14824 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
14825 tem = gen_rtx_MINUS (GET_MODE (tem),
14827 gen_rtx_SYMBOL_REF (Pmode,
14828 ggc_strdup (labelpc)));
14829 assemble_integer (tem, 4, BITS_PER_WORD, 1);
14832 /* Output ".word .LTHUNKn". */
14833 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14837 fputs ("\tb\t", file);
14838 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14839 if (NEED_PLT_RELOC)
14840 fputs ("(PLT)", file);
14841 fputc ('\n', file);
14846 arm_emit_vector_const (FILE *file, rtx x)
14849 const char * pattern;
14851 gcc_assert (GET_CODE (x) == CONST_VECTOR);
14853 switch (GET_MODE (x))
14855 case V2SImode: pattern = "%08x"; break;
14856 case V4HImode: pattern = "%04x"; break;
14857 case V8QImode: pattern = "%02x"; break;
14858 default: gcc_unreachable ();
14861 fprintf (file, "0x");
14862 for (i = CONST_VECTOR_NUNITS (x); i--;)
14866 element = CONST_VECTOR_ELT (x, i);
14867 fprintf (file, pattern, INTVAL (element));
14874 arm_output_load_gr (rtx *operands)
14881 if (GET_CODE (operands [1]) != MEM
14882 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14883 || GET_CODE (reg = XEXP (sum, 0)) != REG
14884 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14885 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14886 return "wldrw%?\t%0, %1";
14888 /* Fix up an out-of-range load of a GR register. */
14889 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14890 wcgr = operands[0];
14892 output_asm_insn ("ldr%?\t%0, %1", operands);
14894 operands[0] = wcgr;
14896 output_asm_insn ("tmcr%?\t%0, %1", operands);
14897 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14902 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14904 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14905 named arg and all anonymous args onto the stack.
14906 XXX I know the prologue shouldn't be pushing registers, but it is faster
14910 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14911 enum machine_mode mode ATTRIBUTE_UNUSED,
14912 tree type ATTRIBUTE_UNUSED,
14914 int second_time ATTRIBUTE_UNUSED)
14916 cfun->machine->uses_anonymous_args = 1;
14917 if (cum->nregs < NUM_ARG_REGS)
14918 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14921 /* Return nonzero if the CONSUMER instruction (a store) does not need
14922 PRODUCER's value to calculate the address. */
14925 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14927 rtx value = PATTERN (producer);
14928 rtx addr = PATTERN (consumer);
14930 if (GET_CODE (value) == COND_EXEC)
14931 value = COND_EXEC_CODE (value);
14932 if (GET_CODE (value) == PARALLEL)
14933 value = XVECEXP (value, 0, 0);
14934 value = XEXP (value, 0);
14935 if (GET_CODE (addr) == COND_EXEC)
14936 addr = COND_EXEC_CODE (addr);
14937 if (GET_CODE (addr) == PARALLEL)
14938 addr = XVECEXP (addr, 0, 0);
14939 addr = XEXP (addr, 0);
14941 return !reg_overlap_mentioned_p (value, addr);
14944 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14945 have an early register shift value or amount dependency on the
14946 result of PRODUCER. */
14949 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14951 rtx value = PATTERN (producer);
14952 rtx op = PATTERN (consumer);
14955 if (GET_CODE (value) == COND_EXEC)
14956 value = COND_EXEC_CODE (value);
14957 if (GET_CODE (value) == PARALLEL)
14958 value = XVECEXP (value, 0, 0);
14959 value = XEXP (value, 0);
14960 if (GET_CODE (op) == COND_EXEC)
14961 op = COND_EXEC_CODE (op);
14962 if (GET_CODE (op) == PARALLEL)
14963 op = XVECEXP (op, 0, 0);
14966 early_op = XEXP (op, 0);
14967 /* This is either an actual independent shift, or a shift applied to
14968 the first operand of another operation. We want the whole shift
14970 if (GET_CODE (early_op) == REG)
14973 return !reg_overlap_mentioned_p (value, early_op);
14976 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14977 have an early register shift value dependency on the result of
14981 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14983 rtx value = PATTERN (producer);
14984 rtx op = PATTERN (consumer);
14987 if (GET_CODE (value) == COND_EXEC)
14988 value = COND_EXEC_CODE (value);
14989 if (GET_CODE (value) == PARALLEL)
14990 value = XVECEXP (value, 0, 0);
14991 value = XEXP (value, 0);
14992 if (GET_CODE (op) == COND_EXEC)
14993 op = COND_EXEC_CODE (op);
14994 if (GET_CODE (op) == PARALLEL)
14995 op = XVECEXP (op, 0, 0);
14998 early_op = XEXP (op, 0);
15000 /* This is either an actual independent shift, or a shift applied to
15001 the first operand of another operation. We want the value being
15002 shifted, in either case. */
15003 if (GET_CODE (early_op) != REG)
15004 early_op = XEXP (early_op, 0);
15006 return !reg_overlap_mentioned_p (value, early_op);
15009 /* Return nonzero if the CONSUMER (a mul or mac op) does not
15010 have an early register mult dependency on the result of
15014 arm_no_early_mul_dep (rtx producer, rtx consumer)
15016 rtx value = PATTERN (producer);
15017 rtx op = PATTERN (consumer);
15019 if (GET_CODE (value) == COND_EXEC)
15020 value = COND_EXEC_CODE (value);
15021 if (GET_CODE (value) == PARALLEL)
15022 value = XVECEXP (value, 0, 0);
15023 value = XEXP (value, 0);
15024 if (GET_CODE (op) == COND_EXEC)
15025 op = COND_EXEC_CODE (op);
15026 if (GET_CODE (op) == PARALLEL)
15027 op = XVECEXP (op, 0, 0);
15030 return (GET_CODE (op) == PLUS
15031 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
15035 /* We can't rely on the caller doing the proper promotion when
15036 using APCS or ATPCS. */
15039 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
15041 return !TARGET_AAPCS_BASED;
15045 /* AAPCS based ABIs use short enums by default. */
15048 arm_default_short_enums (void)
15050 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
15054 /* AAPCS requires that anonymous bitfields affect structure alignment. */
15057 arm_align_anon_bitfield (void)
15059 return TARGET_AAPCS_BASED;
15063 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
15066 arm_cxx_guard_type (void)
15068 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
15072 /* The EABI says test the least significant bit of a guard variable. */
15075 arm_cxx_guard_mask_bit (void)
15077 return TARGET_AAPCS_BASED;
15081 /* The EABI specifies that all array cookies are 8 bytes long. */
15084 arm_get_cookie_size (tree type)
15088 if (!TARGET_AAPCS_BASED)
15089 return default_cxx_get_cookie_size (type);
15091 size = build_int_cst (sizetype, 8);
15096 /* The EABI says that array cookies should also contain the element size. */
15099 arm_cookie_has_size (void)
15101 return TARGET_AAPCS_BASED;
15105 /* The EABI says constructors and destructors should return a pointer to
15106 the object constructed/destroyed. */
15109 arm_cxx_cdtor_returns_this (void)
15111 return TARGET_AAPCS_BASED;
15114 /* The EABI says that an inline function may never be the key
15118 arm_cxx_key_method_may_be_inline (void)
15120 return !TARGET_AAPCS_BASED;
15124 arm_cxx_determine_class_data_visibility (tree decl)
15126 if (!TARGET_AAPCS_BASED)
15129 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
15130 is exported. However, on systems without dynamic vague linkage,
15131 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
15132 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
15133 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
15135 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
15136 DECL_VISIBILITY_SPECIFIED (decl) = 1;
15140 arm_cxx_class_data_always_comdat (void)
15142 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
15143 vague linkage if the class has no key function. */
15144 return !TARGET_AAPCS_BASED;
15148 /* The EABI says __aeabi_atexit should be used to register static
15152 arm_cxx_use_aeabi_atexit (void)
15154 return TARGET_AAPCS_BASED;
15159 arm_set_return_address (rtx source, rtx scratch)
15161 arm_stack_offsets *offsets;
15162 HOST_WIDE_INT delta;
15164 unsigned long saved_regs;
15166 saved_regs = arm_compute_save_reg_mask ();
15168 if ((saved_regs & (1 << LR_REGNUM)) == 0)
15169 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
15172 if (frame_pointer_needed)
15173 addr = plus_constant(hard_frame_pointer_rtx, -4);
15176 /* LR will be the first saved register. */
15177 offsets = arm_get_frame_offsets ();
15178 delta = offsets->outgoing_args - (offsets->frame + 4);
15183 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
15184 GEN_INT (delta & ~4095)));
15189 addr = stack_pointer_rtx;
15191 addr = plus_constant (addr, delta);
15193 emit_move_insn (gen_frame_mem (Pmode, addr), source);
15199 thumb_set_return_address (rtx source, rtx scratch)
15201 arm_stack_offsets *offsets;
15202 HOST_WIDE_INT delta;
15205 unsigned long mask;
15207 emit_insn (gen_rtx_USE (VOIDmode, source));
15209 mask = thumb_compute_save_reg_mask ();
15210 if (mask & (1 << LR_REGNUM))
15212 offsets = arm_get_frame_offsets ();
15214 /* Find the saved regs. */
15215 if (frame_pointer_needed)
15217 delta = offsets->soft_frame - offsets->saved_args;
15218 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
15222 delta = offsets->outgoing_args - offsets->saved_args;
15225 /* Allow for the stack frame. */
15226 if (TARGET_BACKTRACE)
15228 /* The link register is always the first saved register. */
15231 /* Construct the address. */
15232 addr = gen_rtx_REG (SImode, reg);
15233 if ((reg != SP_REGNUM && delta >= 128)
15236 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
15237 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
15241 addr = plus_constant (addr, delta);
15243 emit_move_insn (gen_frame_mem (Pmode, addr), source);
15246 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
15249 /* Implements target hook vector_mode_supported_p. */
15251 arm_vector_mode_supported_p (enum machine_mode mode)
15253 if ((mode == V2SImode)
15254 || (mode == V4HImode)
15255 || (mode == V8QImode))
15261 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
15262 ARM insns and therefore guarantee that the shift count is modulo 256.
15263 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
15264 guarantee no particular behavior for out-of-range counts. */
15266 static unsigned HOST_WIDE_INT
15267 arm_shift_truncation_mask (enum machine_mode mode)
15269 return mode == SImode ? 255 : 0;
15273 /* Map internal gcc register numbers to DWARF2 register numbers. */
15276 arm_dbx_register_number (unsigned int regno)
15281 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
15282 compatibility. The EABI defines them as registers 96-103. */
15283 if (IS_FPA_REGNUM (regno))
15284 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
15286 if (IS_VFP_REGNUM (regno))
15287 return 64 + regno - FIRST_VFP_REGNUM;
15289 if (IS_IWMMXT_GR_REGNUM (regno))
15290 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
15292 if (IS_IWMMXT_REGNUM (regno))
15293 return 112 + regno - FIRST_IWMMXT_REGNUM;
15295 gcc_unreachable ();
15299 #ifdef TARGET_UNWIND_INFO
15300 /* Emit unwind directives for a store-multiple instruction. This should
15301 only ever be generated by the function prologue code, so we expect it
15302 to have a particular form. */
15305 arm_unwind_emit_stm (FILE * asm_out_file, rtx p)
15308 HOST_WIDE_INT offset;
15309 HOST_WIDE_INT nregs;
15315 /* First insn will adjust the stack pointer. */
15316 e = XVECEXP (p, 0, 0);
15317 if (GET_CODE (e) != SET
15318 || GET_CODE (XEXP (e, 0)) != REG
15319 || REGNO (XEXP (e, 0)) != SP_REGNUM
15320 || GET_CODE (XEXP (e, 1)) != PLUS)
15323 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
15324 nregs = XVECLEN (p, 0) - 1;
15326 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
15329 /* The function prologue may also push pc, but not annotate it as it is
15330 never restored. We turn this into a stack pointer adjustment. */
15331 if (nregs * 4 == offset - 4)
15333 fprintf (asm_out_file, "\t.pad #4\n");
15338 else if (IS_VFP_REGNUM (reg))
15340 /* FPA register saves use an additional word. */
15344 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
15346 /* FPA registers are done differently. */
15347 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
15351 /* Unknown register type. */
15354 /* If the stack increment doesn't match the size of the saved registers,
15355 something has gone horribly wrong. */
15356 if (offset != nregs * reg_size)
15359 fprintf (asm_out_file, "\t.save {");
15363 /* The remaining insns will describe the stores. */
15364 for (i = 1; i <= nregs; i++)
15366 /* Expect (set (mem <addr>) (reg)).
15367 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
15368 e = XVECEXP (p, 0, i);
15369 if (GET_CODE (e) != SET
15370 || GET_CODE (XEXP (e, 0)) != MEM
15371 || GET_CODE (XEXP (e, 1)) != REG)
15374 reg = REGNO (XEXP (e, 1));
15379 fprintf (asm_out_file, ", ");
15380 /* We can't use %r for vfp because we need to use the
15381 double precision register names. */
15382 if (IS_VFP_REGNUM (reg))
15383 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
15385 asm_fprintf (asm_out_file, "%r", reg);
15387 #ifdef ENABLE_CHECKING
15388 /* Check that the addresses are consecutive. */
15389 e = XEXP (XEXP (e, 0), 0);
15390 if (GET_CODE (e) == PLUS)
15392 offset += reg_size;
15393 if (GET_CODE (XEXP (e, 0)) != REG
15394 || REGNO (XEXP (e, 0)) != SP_REGNUM
15395 || GET_CODE (XEXP (e, 1)) != CONST_INT
15396 || offset != INTVAL (XEXP (e, 1)))
15400 || GET_CODE (e) != REG
15401 || REGNO (e) != SP_REGNUM)
15405 fprintf (asm_out_file, "}\n");
15408 /* Emit unwind directives for a SET. */
15411 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
15418 switch (GET_CODE (e0))
15421 /* Pushing a single register. */
15422 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
15423 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
15424 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
15427 asm_fprintf (asm_out_file, "\t.save ");
15428 if (IS_VFP_REGNUM (REGNO (e1)))
15429 asm_fprintf(asm_out_file, "{d%d}\n",
15430 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
15432 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
15436 if (REGNO (e0) == SP_REGNUM)
15438 /* A stack increment. */
15439 if (GET_CODE (e1) != PLUS
15440 || GET_CODE (XEXP (e1, 0)) != REG
15441 || REGNO (XEXP (e1, 0)) != SP_REGNUM
15442 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
15445 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
15446 -INTVAL (XEXP (e1, 1)));
15448 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
15450 HOST_WIDE_INT offset;
15453 if (GET_CODE (e1) == PLUS)
15455 if (GET_CODE (XEXP (e1, 0)) != REG
15456 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
15458 reg = REGNO (XEXP (e1, 0));
15459 offset = INTVAL (XEXP (e1, 1));
15460 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
15461 HARD_FRAME_POINTER_REGNUM, reg,
15462 INTVAL (XEXP (e1, 1)));
15464 else if (GET_CODE (e1) == REG)
15467 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
15468 HARD_FRAME_POINTER_REGNUM, reg);
15473 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
15475 /* Move from sp to reg. */
15476 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
15478 else if (GET_CODE (e1) == PLUS
15479 && GET_CODE (XEXP (e1, 0)) == REG
15480 && REGNO (XEXP (e1, 0)) == SP_REGNUM
15481 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
15483 /* Set reg to offset from sp. */
15484 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
15485 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
15497 /* Emit unwind directives for the given insn. */
15500 arm_unwind_emit (FILE * asm_out_file, rtx insn)
15504 if (!ARM_EABI_UNWIND_TABLES)
15507 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
15510 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
15512 pat = XEXP (pat, 0);
15514 pat = PATTERN (insn);
15516 switch (GET_CODE (pat))
15519 arm_unwind_emit_set (asm_out_file, pat);
15523 /* Store multiple. */
15524 arm_unwind_emit_stm (asm_out_file, pat);
15533 /* Output a reference from a function exception table to the type_info
15534 object X. The EABI specifies that the symbol should be relocated by
15535 an R_ARM_TARGET2 relocation. */
15538 arm_output_ttype (rtx x)
15540 fputs ("\t.word\t", asm_out_file);
15541 output_addr_const (asm_out_file, x);
15542 /* Use special relocations for symbol references. */
15543 if (GET_CODE (x) != CONST_INT)
15544 fputs ("(TARGET2)", asm_out_file);
15545 fputc ('\n', asm_out_file);
15549 #endif /* TARGET_UNWIND_INFO */
15552 /* Output unwind directives for the start/end of a function. */
15555 arm_output_fn_unwind (FILE * f, bool prologue)
15557 if (!ARM_EABI_UNWIND_TABLES)
15561 fputs ("\t.fnstart\n", f);
15563 fputs ("\t.fnend\n", f);
15567 arm_emit_tls_decoration (FILE *fp, rtx x)
15569 enum tls_reloc reloc;
15572 val = XVECEXP (x, 0, 0);
15573 reloc = INTVAL (XVECEXP (x, 0, 1));
15575 output_addr_const (fp, val);
15580 fputs ("(tlsgd)", fp);
15583 fputs ("(tlsldm)", fp);
15586 fputs ("(tlsldo)", fp);
15589 fputs ("(gottpoff)", fp);
15592 fputs ("(tpoff)", fp);
15595 gcc_unreachable ();
15603 fputs (" + (. - ", fp);
15604 output_addr_const (fp, XVECEXP (x, 0, 2));
15606 output_addr_const (fp, XVECEXP (x, 0, 3));
15617 arm_output_addr_const_extra (FILE *fp, rtx x)
15619 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
15620 return arm_emit_tls_decoration (fp, x);
15621 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
15624 int labelno = INTVAL (XVECEXP (x, 0, 0));
15626 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
15627 assemble_name_raw (fp, label);
15631 else if (GET_CODE (x) == CONST_VECTOR)
15632 return arm_emit_vector_const (fp, x);
15637 #include "gt-arm.h"