1 /* Subroutines for insn-output.c for Intel X86.
2 Copyright (C) 1988, 92, 94-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
43 #ifdef EXTRA_CONSTRAINT
44 /* If EXTRA_CONSTRAINT is defined, then the 'S'
45 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
46 asm statements that need 'S' for class SIREG will break. */
47 error EXTRA_CONSTRAINT conflicts with S constraint letter
48 /* The previous line used to be #error, but some compilers barf
49 even if the conditional was untrue. */
52 #ifndef CHECK_STACK_LIMIT
53 #define CHECK_STACK_LIMIT -1
56 #define PIC_REG_USED \
57 (flag_pic && (current_function_uses_pic_offset_table \
58 || current_function_uses_const_pool \
59 || profile_flag || profile_block_flag))
61 /* Type of an operand for ix86_{binary,unary}_operator_ok */
69 /* Processor costs (relative to an add) */
70 struct processor_costs i386_cost = { /* 386 specific costs */
71 1, /* cost of an add instruction */
72 1, /* cost of a lea instruction */
73 3, /* variable shift costs */
74 2, /* constant shift costs */
75 6, /* cost of starting a multiply */
76 1, /* cost of multiply per each bit set */
77 23 /* cost of a divide/mod */
80 struct processor_costs i486_cost = { /* 486 specific costs */
81 1, /* cost of an add instruction */
82 1, /* cost of a lea instruction */
83 3, /* variable shift costs */
84 2, /* constant shift costs */
85 12, /* cost of starting a multiply */
86 1, /* cost of multiply per each bit set */
87 40 /* cost of a divide/mod */
90 struct processor_costs pentium_cost = {
91 1, /* cost of an add instruction */
92 1, /* cost of a lea instruction */
93 4, /* variable shift costs */
94 1, /* constant shift costs */
95 11, /* cost of starting a multiply */
96 0, /* cost of multiply per each bit set */
97 25 /* cost of a divide/mod */
100 struct processor_costs pentiumpro_cost = {
101 1, /* cost of an add instruction */
102 1, /* cost of a lea instruction */
103 3, /* variable shift costs */
104 1, /* constant shift costs */
105 4, /* cost of starting a multiply */
106 0, /* cost of multiply per each bit set */
107 17 /* cost of a divide/mod */
110 /* We use decoding time together with execution time.
111 To get correct vale add 1 for short decodable, 2 for long decodable
112 and 4 for vector decodable instruction to execution time and divide
113 by two (because CPU is able to do two insns at a time). */
115 struct processor_costs k6_cost = {
116 1, /* cost of an add instruction */
117 1, /* cost of a lea instruction */
118 1, /* variable shift costs */
119 1, /* constant shift costs */
120 3, /* cost of starting a multiply */
121 0, /* cost of multiply per each bit set */
122 20 /* cost of a divide/mod */
125 struct processor_costs *ix86_cost = &pentium_cost;
127 /* Processor feature/optimization bitmasks. */
128 #define m_386 (1<<PROCESSOR_I386)
129 #define m_486 (1<<PROCESSOR_I486)
130 #define m_PENT (1<<PROCESSOR_PENTIUM)
131 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
132 #define m_K6 (1<<PROCESSOR_K6)
134 const int x86_use_leave = m_386 | m_K6;
135 const int x86_push_memory = m_386 | m_K6;
136 const int x86_zero_extend_with_and = m_486 | m_PENT;
137 const int x86_movx = m_386 | m_PPRO | m_K6;
138 const int x86_double_with_add = ~(m_386 | m_PENT | m_PPRO);
139 const int x86_use_bit_test = m_386;
140 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO;
141 const int x86_use_q_reg = m_PENT | m_PPRO | m_K6;
142 const int x86_use_any_reg = m_486;
143 const int x86_cmove = m_PPRO;
144 const int x86_deep_branch = m_PPRO| m_K6;
146 #define AT_BP(mode) (gen_rtx_MEM ((mode), frame_pointer_rtx))
148 extern FILE *asm_out_file;
149 extern char *strcat ();
151 static void ix86_epilogue PROTO((int));
152 static void ix86_prologue PROTO((int));
154 char *singlemove_string ();
155 char *output_move_const_single ();
156 char *output_fp_cc0_set ();
158 char *hi_reg_name[] = HI_REGISTER_NAMES;
159 char *qi_reg_name[] = QI_REGISTER_NAMES;
160 char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
162 /* Array of the smallest class containing reg number REGNO, indexed by
163 REGNO. Used by REGNO_REG_CLASS in i386.h. */
165 enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
168 AREG, DREG, CREG, BREG,
170 SIREG, DIREG, INDEX_REGS, GENERAL_REGS,
172 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
173 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
178 /* Test and compare insns in i386.md store the information needed to
179 generate branch and scc insns here. */
181 struct rtx_def *i386_compare_op0 = NULL_RTX;
182 struct rtx_def *i386_compare_op1 = NULL_RTX;
183 struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)();
185 /* which cpu are we scheduling for */
186 enum processor_type ix86_cpu;
188 /* which instruction set architecture to use. */
191 /* Strings to hold which cpu and instruction set architecture to use. */
192 char *ix86_cpu_string; /* for -mcpu=<xxx> */
193 char *ix86_arch_string; /* for -march=<xxx> */
195 /* Register allocation order */
196 char *i386_reg_alloc_order;
197 static char regs_allocated[FIRST_PSEUDO_REGISTER];
199 /* # of registers to use to pass arguments. */
200 char *i386_regparm_string;
202 /* i386_regparm_string as a number */
205 /* Alignment to use for loops and jumps: */
207 /* Power of two alignment for loops. */
208 char *i386_align_loops_string;
210 /* Power of two alignment for non-loop jumps. */
211 char *i386_align_jumps_string;
213 /* Power of two alignment for stack boundary in bytes. */
214 char *i386_preferred_stack_boundary_string;
216 /* Preferred alignment for stack boundary in bits. */
217 int i386_preferred_stack_boundary;
219 /* Values 1-5: see jump.c */
220 int i386_branch_cost;
221 char *i386_branch_cost_string;
223 /* Power of two alignment for functions. */
224 int i386_align_funcs;
225 char *i386_align_funcs_string;
227 /* Power of two alignment for loops. */
228 int i386_align_loops;
230 /* Power of two alignment for non-loop jumps. */
231 int i386_align_jumps;
233 /* Sometimes certain combinations of command options do not make
234 sense on a particular target machine. You can define a macro
235 `OVERRIDE_OPTIONS' to take account of this. This macro, if
236 defined, is executed once just after all the command options have
239 Don't use this macro to turn on various extra optimizations for
240 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
250 char *name; /* Canonical processor name. */
251 enum processor_type processor; /* Processor type enum value. */
252 struct processor_costs *cost; /* Processor costs */
253 int target_enable; /* Target flags to enable. */
254 int target_disable; /* Target flags to disable. */
255 } processor_target_table[] = {
256 {PROCESSOR_I386_STRING, PROCESSOR_I386, &i386_cost, 0, 0},
257 {PROCESSOR_I486_STRING, PROCESSOR_I486, &i486_cost, 0, 0},
258 {PROCESSOR_I586_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
259 {PROCESSOR_PENTIUM_STRING, PROCESSOR_PENTIUM, &pentium_cost, 0, 0},
260 {PROCESSOR_I686_STRING, PROCESSOR_PENTIUMPRO, &pentiumpro_cost, 0, 0},
261 {PROCESSOR_PENTIUMPRO_STRING, PROCESSOR_PENTIUMPRO,
262 &pentiumpro_cost, 0, 0},
263 {PROCESSOR_K6_STRING, PROCESSOR_K6, &k6_cost, 0, 0}
266 int ptt_size = sizeof (processor_target_table) / sizeof (struct ptt);
268 #ifdef SUBTARGET_OVERRIDE_OPTIONS
269 SUBTARGET_OVERRIDE_OPTIONS;
272 /* Validate registers in register allocation order. */
273 if (i386_reg_alloc_order)
275 for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
281 case 'a': regno = 0; break;
282 case 'd': regno = 1; break;
283 case 'c': regno = 2; break;
284 case 'b': regno = 3; break;
285 case 'S': regno = 4; break;
286 case 'D': regno = 5; break;
287 case 'B': regno = 6; break;
289 default: fatal ("Register '%c' is unknown", ch);
292 if (regs_allocated[regno])
293 fatal ("Register '%c' already specified in allocation order", ch);
295 regs_allocated[regno] = 1;
299 if (ix86_arch_string == 0)
301 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
302 if (ix86_cpu_string == 0)
303 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
306 for (i = 0; i < ptt_size; i++)
307 if (! strcmp (ix86_arch_string, processor_target_table[i].name))
309 ix86_arch = processor_target_table[i].processor;
310 if (ix86_cpu_string == 0)
311 ix86_cpu_string = processor_target_table[i].name;
317 error ("bad value (%s) for -march= switch", ix86_arch_string);
318 ix86_arch_string = PROCESSOR_PENTIUM_STRING;
319 ix86_arch = PROCESSOR_DEFAULT;
322 if (ix86_cpu_string == 0)
323 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
325 for (j = 0; j < ptt_size; j++)
326 if (! strcmp (ix86_cpu_string, processor_target_table[j].name))
328 ix86_cpu = processor_target_table[j].processor;
329 ix86_cost = processor_target_table[j].cost;
330 if (i > j && (int) ix86_arch >= (int) PROCESSOR_K6)
331 error ("-mcpu=%s does not support -march=%s",
332 ix86_cpu_string, ix86_arch_string);
334 target_flags |= processor_target_table[j].target_enable;
335 target_flags &= ~processor_target_table[j].target_disable;
341 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
342 ix86_cpu_string = PROCESSOR_DEFAULT_STRING;
343 ix86_cpu = PROCESSOR_DEFAULT;
346 /* Validate -mregparm= value. */
347 if (i386_regparm_string)
349 i386_regparm = atoi (i386_regparm_string);
350 if (i386_regparm < 0 || i386_regparm > REGPARM_MAX)
351 fatal ("-mregparm=%d is not between 0 and %d",
352 i386_regparm, REGPARM_MAX);
355 /* The 486 suffers more from non-aligned cache line fills, and the
356 larger code size results in a larger cache foot-print and more misses.
357 The 486 has a 16 byte cache line, pentium and pentiumpro have a 32 byte
359 def_align = (TARGET_486) ? 4 : 2;
361 /* Validate -malign-loops= value, or provide default. */
362 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
363 i386_align_loops = 4;
365 i386_align_loops = 2;
367 if (i386_align_loops_string)
369 i386_align_loops = atoi (i386_align_loops_string);
370 if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN)
371 fatal ("-malign-loops=%d is not between 0 and %d",
372 i386_align_loops, MAX_CODE_ALIGN);
375 /* Validate -malign-jumps= value, or provide default. */
376 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
377 i386_align_jumps = 4;
379 i386_align_jumps = def_align;
381 if (i386_align_jumps_string)
383 i386_align_jumps = atoi (i386_align_jumps_string);
384 if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN)
385 fatal ("-malign-jumps=%d is not between 0 and %d",
386 i386_align_jumps, MAX_CODE_ALIGN);
389 /* Validate -malign-functions= value, or provide default. */
390 i386_align_funcs = def_align;
391 if (i386_align_funcs_string)
393 i386_align_funcs = atoi (i386_align_funcs_string);
394 if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN)
395 fatal ("-malign-functions=%d is not between 0 and %d",
396 i386_align_funcs, MAX_CODE_ALIGN);
399 /* Validate -mpreferred_stack_boundary= value, or provide default.
400 The default of 128 bits is for Pentium III's SSE __m128. */
401 i386_preferred_stack_boundary = 128;
402 if (i386_preferred_stack_boundary_string)
404 i = atoi (i386_preferred_stack_boundary_string);
406 fatal ("-mpreferred_stack_boundary=%d is not between 2 and 31", i);
407 i386_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
410 /* Validate -mbranch-cost= value, or provide default. */
411 i386_branch_cost = 1;
412 if (i386_branch_cost_string)
414 i386_branch_cost = atoi (i386_branch_cost_string);
415 if (i386_branch_cost < 0 || i386_branch_cost > 5)
416 fatal ("-mbranch-cost=%d is not between 0 and 5", i386_branch_cost);
419 /* Keep nonleaf frame pointers. */
420 if (TARGET_OMIT_LEAF_FRAME_POINTER)
421 flag_omit_frame_pointer = 1;
424 /* A C statement (sans semicolon) to choose the order in which to
425 allocate hard registers for pseudo-registers local to a basic
428 Store the desired register order in the array `reg_alloc_order'.
429 Element 0 should be the register to allocate first; element 1, the
430 next register; and so on.
432 The macro body should not assume anything about the contents of
433 `reg_alloc_order' before execution of the macro.
435 On most machines, it is not necessary to define this macro. */
438 order_regs_for_local_alloc ()
442 /* User specified the register allocation order. */
444 if (i386_reg_alloc_order)
446 for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++)
452 case 'a': regno = 0; break;
453 case 'd': regno = 1; break;
454 case 'c': regno = 2; break;
455 case 'b': regno = 3; break;
456 case 'S': regno = 4; break;
457 case 'D': regno = 5; break;
458 case 'B': regno = 6; break;
461 reg_alloc_order[order++] = regno;
464 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
466 if (! regs_allocated[i])
467 reg_alloc_order[order++] = i;
471 /* If user did not specify a register allocation order, use natural order. */
474 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
475 reg_alloc_order[i] = i;
480 optimization_options (level, size)
482 int size ATTRIBUTE_UNUSED;
484 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
485 make the problem with not enough registers even worse. */
486 #ifdef INSN_SCHEDULING
488 flag_schedule_insns = 0;
492 /* Sign-extend a 16-bit constant */
495 i386_sext16_if_const (op)
498 if (GET_CODE (op) == CONST_INT)
500 HOST_WIDE_INT val = INTVAL (op);
501 HOST_WIDE_INT sext_val;
503 sext_val = val | ~0xffff;
505 sext_val = val & 0xffff;
507 op = GEN_INT (sext_val);
512 /* Return nonzero if the rtx is aligned */
515 i386_aligned_reg_p (regno)
518 return (regno == STACK_POINTER_REGNUM
519 || (! flag_omit_frame_pointer && regno == FRAME_POINTER_REGNUM));
526 /* Registers and immediate operands are always "aligned". */
527 if (GET_CODE (op) != MEM)
530 /* Don't even try to do any aligned optimizations with volatiles. */
531 if (MEM_VOLATILE_P (op))
534 /* Get address of memory operand. */
537 switch (GET_CODE (op))
544 /* Match "reg + offset" */
546 if (GET_CODE (XEXP (op, 1)) != CONST_INT)
548 if (INTVAL (XEXP (op, 1)) & 3)
552 if (GET_CODE (op) != REG)
555 /* ... fall through ... */
558 return i386_aligned_reg_p (REGNO (op));
567 /* Return nonzero if INSN looks like it won't compute useful cc bits
568 as a side effect. This information is only a hint. */
571 i386_cc_probably_useless_p (insn)
574 return ! next_cc0_user (insn);
577 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
578 attribute for DECL. The attributes in ATTRIBUTES have previously been
582 i386_valid_decl_attribute_p (decl, attributes, identifier, args)
583 tree decl ATTRIBUTE_UNUSED;
584 tree attributes ATTRIBUTE_UNUSED;
585 tree identifier ATTRIBUTE_UNUSED;
586 tree args ATTRIBUTE_UNUSED;
591 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
592 attribute for TYPE. The attributes in ATTRIBUTES have previously been
596 i386_valid_type_attribute_p (type, attributes, identifier, args)
598 tree attributes ATTRIBUTE_UNUSED;
602 if (TREE_CODE (type) != FUNCTION_TYPE
603 && TREE_CODE (type) != METHOD_TYPE
604 && TREE_CODE (type) != FIELD_DECL
605 && TREE_CODE (type) != TYPE_DECL)
608 /* Stdcall attribute says callee is responsible for popping arguments
609 if they are not variable. */
610 if (is_attribute_p ("stdcall", identifier))
611 return (args == NULL_TREE);
613 /* Cdecl attribute says the callee is a normal C declaration. */
614 if (is_attribute_p ("cdecl", identifier))
615 return (args == NULL_TREE);
617 /* Regparm attribute specifies how many integer arguments are to be
618 passed in registers. */
619 if (is_attribute_p ("regparm", identifier))
623 if (! args || TREE_CODE (args) != TREE_LIST
624 || TREE_CHAIN (args) != NULL_TREE
625 || TREE_VALUE (args) == NULL_TREE)
628 cst = TREE_VALUE (args);
629 if (TREE_CODE (cst) != INTEGER_CST)
632 if (TREE_INT_CST_HIGH (cst) != 0
633 || TREE_INT_CST_LOW (cst) < 0
634 || TREE_INT_CST_LOW (cst) > REGPARM_MAX)
643 /* Return 0 if the attributes for two types are incompatible, 1 if they
644 are compatible, and 2 if they are nearly compatible (which causes a
645 warning to be generated). */
648 i386_comp_type_attributes (type1, type2)
652 /* Check for mismatch of non-default calling convention. */
653 char *rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
655 if (TREE_CODE (type1) != FUNCTION_TYPE)
658 /* Check for mismatched return types (cdecl vs stdcall). */
659 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
660 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
666 /* Value is the number of bytes of arguments automatically
667 popped when returning from a subroutine call.
668 FUNDECL is the declaration node of the function (as a tree),
669 FUNTYPE is the data type of the function (as a tree),
670 or for a library call it is an identifier node for the subroutine name.
671 SIZE is the number of bytes of arguments passed on the stack.
673 On the 80386, the RTD insn may be used to pop them if the number
674 of args is fixed, but if the number is variable then the caller
675 must pop them all. RTD can't be used for library calls now
676 because the library is compiled with the Unix compiler.
677 Use of RTD is a selectable option, since it is incompatible with
678 standard Unix calling sequences. If the option is not selected,
679 the caller must always pop the args.
681 The attribute stdcall is equivalent to RTD on a per module basis. */
684 i386_return_pops_args (fundecl, funtype, size)
689 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
691 /* Cdecl functions override -mrtd, and never pop the stack. */
692 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
694 /* Stdcall functions will pop the stack if not variable args. */
695 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype)))
699 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
700 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
705 /* Lose any fake structure return argument. */
706 if (aggregate_value_p (TREE_TYPE (funtype)))
707 return GET_MODE_SIZE (Pmode);
713 /* Argument support functions. */
715 /* Initialize a variable CUM of type CUMULATIVE_ARGS
716 for a call to a function whose data type is FNTYPE.
717 For a library call, FNTYPE is 0. */
720 init_cumulative_args (cum, fntype, libname)
721 CUMULATIVE_ARGS *cum; /* Argument info to initialize */
722 tree fntype; /* tree ptr for function decl */
723 rtx libname; /* SYMBOL_REF of library name or 0 */
725 static CUMULATIVE_ARGS zero_cum;
726 tree param, next_param;
728 if (TARGET_DEBUG_ARG)
730 fprintf (stderr, "\ninit_cumulative_args (");
732 fprintf (stderr, "fntype code = %s, ret code = %s",
733 tree_code_name[(int) TREE_CODE (fntype)],
734 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
736 fprintf (stderr, "no fntype");
739 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
744 /* Set up the number of registers to use for passing arguments. */
745 cum->nregs = i386_regparm;
748 tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype));
751 cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
754 /* Determine if this function has variable arguments. This is
755 indicated by the last argument being 'void_type_mode' if there
756 are no variable arguments. If there are variable arguments, then
757 we won't pass anything in registers */
761 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
762 param != 0; param = next_param)
764 next_param = TREE_CHAIN (param);
765 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
770 if (TARGET_DEBUG_ARG)
771 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
776 /* Update the data in CUM to advance over an argument
777 of mode MODE and data type TYPE.
778 (TYPE is null for libcalls where that information may not be available.) */
781 function_arg_advance (cum, mode, type, named)
782 CUMULATIVE_ARGS *cum; /* current arg information */
783 enum machine_mode mode; /* current arg mode */
784 tree type; /* type of the argument or 0 if lib support */
785 int named; /* whether or not the argument was named */
788 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
789 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
791 if (TARGET_DEBUG_ARG)
793 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n",
794 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
809 /* Define where to put the arguments to a function.
810 Value is zero to push the argument on the stack,
811 or a hard register in which to store the argument.
813 MODE is the argument's machine mode.
814 TYPE is the data type of the argument (as a tree).
815 This is null for libcalls where that information may
817 CUM is a variable of type CUMULATIVE_ARGS which gives info about
818 the preceding args and about the function being called.
819 NAMED is nonzero if this argument is a named parameter
820 (otherwise it is an extra parameter matching an ellipsis). */
823 function_arg (cum, mode, type, named)
824 CUMULATIVE_ARGS *cum; /* current arg information */
825 enum machine_mode mode; /* current arg mode */
826 tree type; /* type of the argument or 0 if lib support */
827 int named; /* != 0 for normal args, == 0 for ... args */
831 = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
832 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
836 /* For now, pass fp/complex values on the stack. */
845 if (words <= cum->nregs)
846 ret = gen_rtx_REG (mode, cum->regno);
850 if (TARGET_DEBUG_ARG)
853 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d",
854 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
857 fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]);
859 fprintf (stderr, ", stack");
861 fprintf (stderr, " )\n");
867 /* For an arg passed partly in registers and partly in memory,
868 this is the number of registers used.
869 For args passed entirely in registers or entirely in memory, zero. */
872 function_arg_partial_nregs (cum, mode, type, named)
873 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; /* current arg information */
874 enum machine_mode mode ATTRIBUTE_UNUSED; /* current arg mode */
875 tree type ATTRIBUTE_UNUSED; /* type of the argument or 0 if lib support */
876 int named ATTRIBUTE_UNUSED; /* != 0 for normal args, == 0 for ... args */
882 singlemove_string (operands)
886 if (GET_CODE (operands[0]) == MEM
887 && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC)
889 if (XEXP (x, 0) != stack_pointer_rtx)
893 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
894 return output_move_const_single (operands);
895 else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG)
896 return AS2 (mov%L0,%1,%0);
897 else if (CONSTANT_P (operands[1]))
898 return AS2 (mov%L0,%1,%0);
901 output_asm_insn ("push%L1 %1", operands);
906 /* Output an insn to add the constant N to the register X. */
917 output_asm_insn (AS1 (dec%L0,%0), xops);
919 output_asm_insn (AS1 (inc%L0,%0), xops);
920 else if (n < 0 || n == 128)
922 xops[1] = GEN_INT (-n);
923 output_asm_insn (AS2 (sub%L0,%1,%0), xops);
927 xops[1] = GEN_INT (n);
928 output_asm_insn (AS2 (add%L0,%1,%0), xops);
932 /* Output assembler code to perform a doubleword move insn
933 with operands OPERANDS. */
936 output_move_double (operands)
939 enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
943 int dest_overlapped_low = 0;
944 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
949 /* First classify both operands. */
951 if (REG_P (operands[0]))
953 else if (offsettable_memref_p (operands[0]))
955 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
957 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
959 else if (GET_CODE (operands[0]) == MEM)
964 if (REG_P (operands[1]))
966 else if (CONSTANT_P (operands[1]))
968 else if (offsettable_memref_p (operands[1]))
970 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
972 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
974 else if (GET_CODE (operands[1]) == MEM)
979 /* Check for the cases that are not supposed to happen
980 either due to the operand constraints or the fact
981 that all memory operands on the x86 are offsettable.
982 Abort if we get one, because generating code for these
985 if (optype0 == RNDOP || optype1 == RNDOP
986 || optype0 == MEMOP || optype1 == MEMOP)
989 /* If one operand is decrementing and one is incrementing
990 decrement the former register explicitly
991 and change that operand into ordinary indexing. */
993 if (optype0 == PUSHOP && optype1 == POPOP)
995 /* ??? Can this ever happen on i386? */
996 operands[0] = XEXP (XEXP (operands[0], 0), 0);
997 asm_add (-size, operands[0]);
998 if (GET_MODE (operands[1]) == XFmode)
999 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
1000 else if (GET_MODE (operands[0]) == DFmode)
1001 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
1003 operands[0] = gen_rtx_MEM (DImode, operands[0]);
1007 if (optype0 == POPOP && optype1 == PUSHOP)
1009 /* ??? Can this ever happen on i386? */
1010 operands[1] = XEXP (XEXP (operands[1], 0), 0);
1011 asm_add (-size, operands[1]);
1012 if (GET_MODE (operands[1]) == XFmode)
1013 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
1014 else if (GET_MODE (operands[1]) == DFmode)
1015 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
1017 operands[1] = gen_rtx_MEM (DImode, operands[1]);
1021 /* Ok, we can do one word at a time.
1022 Normally we do the low-numbered word first,
1023 but if either operand is autodecrementing then we
1024 do the high-numbered word first.
1026 In either case, set up in LATEHALF the operands to use
1027 for the high-numbered word and in some cases alter the
1028 operands in OPERANDS to be suitable for the low-numbered word. */
1032 if (optype0 == REGOP)
1034 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1035 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
1037 else if (optype0 == OFFSOP)
1039 middlehalf[0] = adj_offsettable_operand (operands[0], 4);
1040 latehalf[0] = adj_offsettable_operand (operands[0], 8);
1044 middlehalf[0] = operands[0];
1045 latehalf[0] = operands[0];
1048 if (optype1 == REGOP)
1050 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1051 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1053 else if (optype1 == OFFSOP)
1055 middlehalf[1] = adj_offsettable_operand (operands[1], 4);
1056 latehalf[1] = adj_offsettable_operand (operands[1], 8);
1058 else if (optype1 == CNSTOP)
1060 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1062 REAL_VALUE_TYPE r; long l[3];
1064 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1065 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1066 operands[1] = GEN_INT (l[0]);
1067 middlehalf[1] = GEN_INT (l[1]);
1068 latehalf[1] = GEN_INT (l[2]);
1070 else if (CONSTANT_P (operands[1]))
1071 /* No non-CONST_DOUBLE constant should ever appear here. */
1076 middlehalf[1] = operands[1];
1077 latehalf[1] = operands[1];
1083 /* Size is not 12. */
1085 if (optype0 == REGOP)
1086 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1087 else if (optype0 == OFFSOP)
1088 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1090 latehalf[0] = operands[0];
1092 if (optype1 == REGOP)
1093 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1094 else if (optype1 == OFFSOP)
1095 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1096 else if (optype1 == CNSTOP)
1097 split_double (operands[1], &operands[1], &latehalf[1]);
1099 latehalf[1] = operands[1];
1102 /* If insn is effectively movd N (sp),-(sp) then we will do the
1103 high word first. We should use the adjusted operand 1
1104 (which is N+4 (sp) or N+8 (sp))
1105 for the low word and middle word as well,
1106 to compensate for the first decrement of sp. */
1107 if (optype0 == PUSHOP
1108 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1109 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
1110 middlehalf[1] = operands[1] = latehalf[1];
1112 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1113 if the upper part of reg N does not appear in the MEM, arrange to
1114 emit the move late-half first. Otherwise, compute the MEM address
1115 into the upper part of N and use that as a pointer to the memory
1117 if (optype0 == REGOP && optype1 == OFFSOP)
1119 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1120 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1122 /* If both halves of dest are used in the src memory address,
1123 compute the address into latehalf of dest. */
1125 xops[0] = latehalf[0];
1126 xops[1] = XEXP (operands[1], 0);
1127 output_asm_insn (AS2 (lea%L0,%a1,%0), xops);
1128 if (GET_MODE (operands[1]) == XFmode)
1130 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
1131 middlehalf[1] = adj_offsettable_operand (operands[1], size-8);
1132 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1136 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
1137 latehalf[1] = adj_offsettable_operand (operands[1], size-4);
1142 && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0)))
1144 /* Check for two regs used by both source and dest. */
1145 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
1146 || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
1149 /* Only the middle reg conflicts; simply put it last. */
1150 output_asm_insn (singlemove_string (operands), operands);
1151 output_asm_insn (singlemove_string (latehalf), latehalf);
1152 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1156 else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
1157 /* If the low half of dest is mentioned in the source memory
1158 address, the arrange to emit the move late half first. */
1159 dest_overlapped_low = 1;
1162 /* If one or both operands autodecrementing,
1163 do the two words, high-numbered first. */
1165 /* Likewise, the first move would clobber the source of the second one,
1166 do them in the other order. This happens only for registers;
1167 such overlap can't happen in memory unless the user explicitly
1168 sets it up, and that is an undefined circumstance. */
1171 if (optype0 == PUSHOP || optype1 == PUSHOP
1172 || (optype0 == REGOP && optype1 == REGOP
1173 && REGNO (operands[0]) == REGNO (latehalf[1]))
1174 || dest_overlapped_low)
1177 if (optype0 == PUSHOP || optype1 == PUSHOP
1178 || (optype0 == REGOP && optype1 == REGOP
1179 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
1180 || REGNO (operands[0]) == REGNO (latehalf[1])))
1181 || dest_overlapped_low)
1183 /* Do the high-numbered word. */
1184 output_asm_insn (singlemove_string (latehalf), latehalf);
1187 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1189 /* Do low-numbered word. */
1190 return singlemove_string (operands);
1193 /* Normal case: do the two words, low-numbered first. */
1195 output_asm_insn (singlemove_string (operands), operands);
1197 /* Do the middle one of the three words for long double */
1199 output_asm_insn (singlemove_string (middlehalf), middlehalf);
1201 /* Do the high-numbered word. */
1202 output_asm_insn (singlemove_string (latehalf), latehalf);
1207 #define MAX_TMPS 2 /* max temporary registers used */
1209 /* Output the appropriate code to move push memory on the stack */
1212 output_move_pushmem (operands, insn, length, tmp_start, n_operands)
1224 } tmp_info[MAX_TMPS];
1226 rtx src = operands[1];
1229 int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src);
1230 int stack_offset = 0;
1234 if (! offsettable_memref_p (src))
1235 fatal_insn ("Source is not offsettable", insn);
1237 if ((length & 3) != 0)
1238 fatal_insn ("Pushing non-word aligned size", insn);
1240 /* Figure out which temporary registers we have available */
1241 for (i = tmp_start; i < n_operands; i++)
1243 if (GET_CODE (operands[i]) == REG)
1245 if (reg_overlap_mentioned_p (operands[i], src))
1248 tmp_info[ max_tmps++ ].xops[1] = operands[i];
1249 if (max_tmps == MAX_TMPS)
1255 for (offset = length - 4; offset >= 0; offset -= 4)
1257 xops[0] = adj_offsettable_operand (src, offset + stack_offset);
1258 output_asm_insn (AS1(push%L0,%0), xops);
1264 for (offset = length - 4; offset >= 0; )
1266 for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++)
1268 tmp_info[num_tmps].load = AS2(mov%L0,%0,%1);
1269 tmp_info[num_tmps].push = AS1(push%L0,%1);
1270 tmp_info[num_tmps].xops[0]
1271 = adj_offsettable_operand (src, offset + stack_offset);
1275 for (i = 0; i < num_tmps; i++)
1276 output_asm_insn (tmp_info[i].load, tmp_info[i].xops);
1278 for (i = 0; i < num_tmps; i++)
1279 output_asm_insn (tmp_info[i].push, tmp_info[i].xops);
1282 stack_offset += 4*num_tmps;
1289 standard_80387_constant_p (x)
1292 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
1297 if (setjmp (handler))
1300 set_float_handler (handler);
1301 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1302 is0 = REAL_VALUES_EQUAL (d, dconst0) && !REAL_VALUE_MINUS_ZERO (d);
1303 is1 = REAL_VALUES_EQUAL (d, dconst1);
1304 set_float_handler (NULL_PTR);
1312 /* Note that on the 80387, other constants, such as pi,
1313 are much slower to load as standard constants
1314 than to load from doubles in memory! */
1315 /* ??? Not true on K6: all constants are equal cost. */
1322 output_move_const_single (operands)
1325 if (FP_REG_P (operands[0]))
1327 int conval = standard_80387_constant_p (operands[1]);
1336 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1338 REAL_VALUE_TYPE r; long l;
1340 if (GET_MODE (operands[1]) == XFmode)
1343 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1344 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1345 operands[1] = GEN_INT (l);
1348 return singlemove_string (operands);
1351 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1352 reference and a constant. */
1355 symbolic_operand (op, mode)
1357 enum machine_mode mode ATTRIBUTE_UNUSED;
1359 switch (GET_CODE (op))
1367 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1368 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1369 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1376 /* Return nonzero if OP is a constant shift count small enough to
1377 encode into an lea instruction. */
1380 small_shift_operand (op, mode)
1382 enum machine_mode mode ATTRIBUTE_UNUSED;
1384 return (GET_CODE (op) == CONST_INT && INTVAL (op) > 0 && INTVAL (op) < 4);
1387 /* Test for a valid operand for a call instruction.
1388 Don't allow the arg pointer register or virtual regs
1389 since they may change into reg + const, which the patterns
1390 can't handle yet. */
1393 call_insn_operand (op, mode)
1395 enum machine_mode mode ATTRIBUTE_UNUSED;
1397 if (GET_CODE (op) == MEM
1398 && ((CONSTANT_ADDRESS_P (XEXP (op, 0))
1399 /* This makes a difference for PIC. */
1400 && general_operand (XEXP (op, 0), Pmode))
1401 || (GET_CODE (XEXP (op, 0)) == REG
1402 && XEXP (op, 0) != arg_pointer_rtx
1403 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1404 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1410 /* Like call_insn_operand but allow (mem (symbol_ref ...))
1414 expander_call_insn_operand (op, mode)
1416 enum machine_mode mode ATTRIBUTE_UNUSED;
1418 if (GET_CODE (op) == MEM
1419 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
1420 || (GET_CODE (XEXP (op, 0)) == REG
1421 && XEXP (op, 0) != arg_pointer_rtx
1422 && ! (REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
1423 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
1429 /* Return 1 if OP is a comparison operator that can use the condition code
1430 generated by an arithmetic operation. */
1433 arithmetic_comparison_operator (op, mode)
1435 enum machine_mode mode;
1439 if (mode != VOIDmode && mode != GET_MODE (op))
1442 code = GET_CODE (op);
1443 if (GET_RTX_CLASS (code) != '<')
1446 return (code != GT && code != LE);
1450 ix86_logical_operator (op, mode)
1452 enum machine_mode mode ATTRIBUTE_UNUSED;
1454 return GET_CODE (op) == AND || GET_CODE (op) == IOR || GET_CODE (op) == XOR;
1458 /* Returns 1 if OP contains a symbol reference */
1461 symbolic_reference_mentioned_p (op)
1467 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1470 fmt = GET_RTX_FORMAT (GET_CODE (op));
1471 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
1477 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
1478 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
1482 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
1489 /* Attempt to expand a binary operator. Make the expansion closer to the
1490 actual machine, then just general_operand, which will allow 3 separate
1491 memory references (one output, two input) in a single insn. Return
1492 whether the insn fails, or succeeds. */
1495 ix86_expand_binary_operator (code, mode, operands)
1497 enum machine_mode mode;
1502 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
1503 if (GET_RTX_CLASS (code) == 'c'
1504 && (rtx_equal_p (operands[0], operands[2])
1505 || immediate_operand (operands[1], mode)))
1507 rtx temp = operands[1];
1508 operands[1] = operands[2];
1512 /* If optimizing, copy to regs to improve CSE */
1513 if (TARGET_PSEUDO && optimize
1514 && ((reload_in_progress | reload_completed) == 0))
1516 if (GET_CODE (operands[1]) == MEM
1517 && ! rtx_equal_p (operands[0], operands[1]))
1518 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1520 if (GET_CODE (operands[2]) == MEM)
1521 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1523 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1525 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1527 emit_move_insn (temp, operands[1]);
1533 if (!ix86_binary_operator_ok (code, mode, operands))
1535 /* If not optimizing, try to make a valid insn (optimize code
1536 previously did this above to improve chances of CSE) */
1538 if ((! TARGET_PSEUDO || !optimize)
1539 && ((reload_in_progress | reload_completed) == 0)
1540 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM))
1543 if (GET_CODE (operands[1]) == MEM
1544 && ! rtx_equal_p (operands[0], operands[1]))
1546 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1550 if (GET_CODE (operands[2]) == MEM)
1552 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
1556 if (GET_CODE (operands[1]) == CONST_INT && code == MINUS)
1558 rtx temp = gen_reg_rtx (GET_MODE (operands[0]));
1560 emit_move_insn (temp, operands[1]);
1565 if (modified && ! ix86_binary_operator_ok (code, mode, operands))
1575 /* Return TRUE or FALSE depending on whether the binary operator meets the
1576 appropriate constraints. */
1579 ix86_binary_operator_ok (code, mode, operands)
1581 enum machine_mode mode ATTRIBUTE_UNUSED;
1584 return (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
1585 && (GET_CODE (operands[1]) != CONST_INT || GET_RTX_CLASS (code) == 'c');
1588 /* Attempt to expand a unary operator. Make the expansion closer to the
1589 actual machine, then just general_operand, which will allow 2 separate
1590 memory references (one output, one input) in a single insn. Return
1591 whether the insn fails, or succeeds. */
1594 ix86_expand_unary_operator (code, mode, operands)
1596 enum machine_mode mode;
1599 /* If optimizing, copy to regs to improve CSE */
1602 && ((reload_in_progress | reload_completed) == 0)
1603 && GET_CODE (operands[1]) == MEM)
1604 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1606 if (! ix86_unary_operator_ok (code, mode, operands))
1608 if ((! TARGET_PSEUDO || optimize == 0)
1609 && ((reload_in_progress | reload_completed) == 0)
1610 && GET_CODE (operands[1]) == MEM)
1612 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
1613 if (! ix86_unary_operator_ok (code, mode, operands))
1623 /* Return TRUE or FALSE depending on whether the unary operator meets the
1624 appropriate constraints. */
1627 ix86_unary_operator_ok (code, mode, operands)
1628 enum rtx_code code ATTRIBUTE_UNUSED;
1629 enum machine_mode mode ATTRIBUTE_UNUSED;
1630 rtx operands[2] ATTRIBUTE_UNUSED;
1635 static rtx pic_label_rtx;
1636 static char pic_label_name [256];
1637 static int pic_label_no = 0;
1639 /* This function generates code for -fpic that loads %ebx with
1640 the return address of the caller and then returns. */
1643 asm_output_function_prefix (file, name)
1645 char *name ATTRIBUTE_UNUSED;
1648 xops[0] = pic_offset_table_rtx;
1649 xops[1] = stack_pointer_rtx;
1651 /* Deep branch prediction favors having a return for every call. */
1652 if (PIC_REG_USED && TARGET_DEEP_BRANCH_PREDICTION)
1656 if (pic_label_rtx == 0)
1658 pic_label_rtx = gen_label_rtx ();
1659 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
1660 LABEL_NAME (pic_label_rtx) = pic_label_name;
1663 prologue_node = make_node (FUNCTION_DECL);
1664 DECL_RESULT (prologue_node) = 0;
1666 /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an
1667 internal (non-global) label that's being emitted, it didn't make
1668 sense to have .type information for local labels. This caused
1669 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving
1670 me debug info for a label that you're declaring non-global?) this
1671 was changed to call ASM_OUTPUT_LABEL() instead. */
1674 ASM_OUTPUT_LABEL (file, pic_label_name);
1675 output_asm_insn ("movl (%1),%0", xops);
1676 output_asm_insn ("ret", xops);
1680 /* Generate the assembly code for function entry.
1681 FILE is an stdio stream to output the code to.
1682 SIZE is an int: how many units of temporary storage to allocate. */
1685 function_prologue (file, size)
1686 FILE *file ATTRIBUTE_UNUSED;
1687 int size ATTRIBUTE_UNUSED;
1689 if (TARGET_SCHEDULE_PROLOGUE)
1698 /* Expand the prologue into a bunch of separate insns. */
1701 ix86_expand_prologue ()
1703 if (! TARGET_SCHEDULE_PROLOGUE)
1710 load_pic_register (do_rtl)
1715 if (TARGET_DEEP_BRANCH_PREDICTION)
1717 xops[0] = pic_offset_table_rtx;
1718 if (pic_label_rtx == 0)
1720 pic_label_rtx = gen_label_rtx ();
1721 ASM_GENERATE_INTERNAL_LABEL (pic_label_name, "LPR", pic_label_no++);
1722 LABEL_NAME (pic_label_rtx) = pic_label_name;
1725 xops[1] = gen_rtx_MEM (QImode,
1726 gen_rtx (SYMBOL_REF, Pmode,
1727 LABEL_NAME (pic_label_rtx)));
1731 emit_insn (gen_prologue_get_pc (xops[0], xops[1]));
1732 emit_insn (gen_prologue_set_got (xops[0],
1733 #ifdef YES_UNDERSCORES
1734 gen_rtx_SYMBOL_REF (Pmode,
1735 "$__GLOBAL_OFFSET_TABLE_"),
1737 gen_rtx_SYMBOL_REF (Pmode,
1738 "$_GLOBAL_OFFSET_TABLE_"),
1744 output_asm_insn (AS1 (call,%X1), xops);
1745 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_,%0", xops);
1752 xops[0] = pic_offset_table_rtx;
1753 xops[1] = gen_label_rtx ();
1757 /* We can't put a raw CODE_LABEL into the RTL, and we can't emit
1758 a new CODE_LABEL after reload, so we need a single pattern to
1759 emit the 3 necessary instructions. */
1760 emit_insn (gen_prologue_get_pc_and_set_got (xops[0]));
1764 output_asm_insn (AS1 (call,%P1), xops);
1765 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1766 CODE_LABEL_NUMBER (xops[1]));
1767 output_asm_insn (AS1 (pop%L0,%0), xops);
1768 output_asm_insn ("addl $%__GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops);
1772 /* When -fpic, we must emit a scheduling barrier, so that the instruction
1773 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
1774 moved before any instruction which implicitly uses the got. */
1777 emit_insn (gen_blockage ());
1780 /* Compute the size of local storage taking into consideration the
1781 desired stack alignment which is to be maintained. Also determine
1782 the number of registers saved below the local storage. */
1785 ix86_compute_frame_size (size, nregs_on_stack)
1787 int *nregs_on_stack;
1793 int pic_reg_used = PIC_REG_USED;
1794 HOST_WIDE_INT total_size;
1796 limit = frame_pointer_needed
1797 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
1801 for (regno = limit - 1; regno >= 0; regno--)
1802 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1803 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1807 total_size = size + (nregs * UNITS_PER_WORD);
1809 #ifdef PREFERRED_STACK_BOUNDARY
1812 int preferred_alignment = PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT;
1815 if (frame_pointer_needed)
1816 offset += UNITS_PER_WORD;
1818 total_size += offset;
1820 padding = ((total_size + preferred_alignment - 1)
1821 & -preferred_alignment) - total_size;
1823 if (padding < (((offset + preferred_alignment - 1)
1824 & -preferred_alignment) - offset))
1825 padding += preferred_alignment;
1827 /* Don't bother aligning the stack of a leaf function
1828 which doesn't allocate any stack slots. */
1829 if (size == 0 && current_function_is_leaf)
1835 *nregs_on_stack = nregs;
1837 return size + padding;
1841 ix86_prologue (do_rtl)
1847 int pic_reg_used = PIC_REG_USED;
1848 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), (int *)0);
1850 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
1852 xops[0] = stack_pointer_rtx;
1853 xops[1] = frame_pointer_rtx;
1854 xops[2] = GEN_INT (tsize);
1856 if (frame_pointer_needed)
1860 insn = emit_insn (gen_rtx (SET, VOIDmode,
1861 gen_rtx_MEM (SImode,
1862 gen_rtx (PRE_DEC, SImode,
1863 stack_pointer_rtx)),
1864 frame_pointer_rtx));
1866 RTX_FRAME_RELATED_P (insn) = 1;
1867 insn = emit_move_insn (xops[1], xops[0]);
1868 RTX_FRAME_RELATED_P (insn) = 1;
1873 output_asm_insn ("push%L1 %1", xops);
1874 #ifdef INCOMING_RETURN_ADDR_RTX
1875 if (dwarf2out_do_frame ())
1877 char *l = dwarf2out_cfi_label ();
1879 cfa_store_offset += 4;
1880 cfa_offset = cfa_store_offset;
1881 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
1882 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, - cfa_store_offset);
1886 output_asm_insn (AS2 (mov%L0,%0,%1), xops);
1887 #ifdef INCOMING_RETURN_ADDR_RTX
1888 if (dwarf2out_do_frame ())
1889 dwarf2out_def_cfa ("", FRAME_POINTER_REGNUM, cfa_offset);
1896 else if (! TARGET_STACK_PROBE || tsize < CHECK_STACK_LIMIT)
1900 insn = emit_insn (gen_prologue_set_stack_ptr (xops[2]));
1901 RTX_FRAME_RELATED_P (insn) = 1;
1905 output_asm_insn (AS2 (sub%L0,%2,%0), xops);
1906 #ifdef INCOMING_RETURN_ADDR_RTX
1907 if (dwarf2out_do_frame ())
1909 cfa_store_offset += tsize;
1910 if (! frame_pointer_needed)
1912 cfa_offset = cfa_store_offset;
1913 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
1921 xops[3] = gen_rtx_REG (SImode, 0);
1923 emit_move_insn (xops[3], xops[2]);
1925 output_asm_insn (AS2 (mov%L0,%2,%3), xops);
1927 xops[3] = gen_rtx_MEM (FUNCTION_MODE,
1928 gen_rtx (SYMBOL_REF, Pmode, "_alloca"));
1931 emit_call_insn (gen_rtx (CALL, VOIDmode, xops[3], const0_rtx));
1933 output_asm_insn (AS1 (call,%P3), xops);
1936 /* Note If use enter it is NOT reversed args.
1937 This one is not reversed from intel!!
1938 I think enter is slower. Also sdb doesn't like it.
1939 But if you want it the code is:
1941 xops[3] = const0_rtx;
1942 output_asm_insn ("enter %2,%3", xops);
1946 limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
1947 for (regno = limit - 1; regno >= 0; regno--)
1948 if ((regs_ever_live[regno] && ! call_used_regs[regno])
1949 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1951 xops[0] = gen_rtx_REG (SImode, regno);
1954 insn = emit_insn (gen_rtx (SET, VOIDmode,
1955 gen_rtx_MEM (SImode,
1956 gen_rtx (PRE_DEC, SImode,
1957 stack_pointer_rtx)),
1960 RTX_FRAME_RELATED_P (insn) = 1;
1964 output_asm_insn ("push%L0 %0", xops);
1965 #ifdef INCOMING_RETURN_ADDR_RTX
1966 if (dwarf2out_do_frame ())
1968 char *l = dwarf2out_cfi_label ();
1970 cfa_store_offset += 4;
1971 if (! frame_pointer_needed)
1973 cfa_offset = cfa_store_offset;
1974 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
1977 dwarf2out_reg_save (l, regno, - cfa_store_offset);
1983 #ifdef SUBTARGET_PROLOGUE
1988 load_pic_register (do_rtl);
1990 /* If we are profiling, make sure no instructions are scheduled before
1991 the call to mcount. However, if -fpic, the above call will have
1993 if ((profile_flag || profile_block_flag)
1994 && ! pic_reg_used && do_rtl)
1995 emit_insn (gen_blockage ());
1998 /* Return 1 if it is appropriate to emit `ret' instructions in the
1999 body of a function. Do this only if the epilogue is simple, needing a
2000 couple of insns. Prior to reloading, we can't tell how many registers
2001 must be saved, so return 0 then. Return 0 if there is no frame
2002 marker to de-allocate.
2004 If NON_SAVING_SETJMP is defined and true, then it is not possible
2005 for the epilogue to be simple, so return 0. This is a special case
2006 since NON_SAVING_SETJMP will not cause regs_ever_live to change
2007 until final, but jump_optimize may need to know sooner if a
2011 ix86_can_use_return_insn_p ()
2015 int reglimit = (frame_pointer_needed
2016 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
2018 #ifdef NON_SAVING_SETJMP
2019 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
2023 if (! reload_completed)
2026 for (regno = reglimit - 1; regno >= 0; regno--)
2027 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2028 || (regno == PIC_OFFSET_TABLE_REGNUM && PIC_REG_USED))
2031 return nregs == 0 || ! frame_pointer_needed;
2034 /* This function generates the assembly code for function exit.
2035 FILE is an stdio stream to output the code to.
2036 SIZE is an int: how many units of temporary storage to deallocate. */
2039 function_epilogue (file, size)
2040 FILE *file ATTRIBUTE_UNUSED;
2041 int size ATTRIBUTE_UNUSED;
2046 /* Restore function stack, frame, and registers. */
2049 ix86_expand_epilogue ()
2055 ix86_epilogue (do_rtl)
2062 int pic_reg_used = PIC_REG_USED;
2063 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
2064 HOST_WIDE_INT offset;
2065 HOST_WIDE_INT tsize = ix86_compute_frame_size (get_frame_size (), &nregs);
2067 /* sp is often unreliable so we may have to go off the frame pointer. */
2069 offset = -(tsize + nregs * UNITS_PER_WORD);
2071 xops[2] = stack_pointer_rtx;
2073 /* When -fpic, we must emit a scheduling barrier, so that the instruction
2074 that restores %ebx (which is PIC_OFFSET_TABLE_REGNUM), does not get
2075 moved before any instruction which implicitly uses the got. This
2076 includes any instruction which uses a SYMBOL_REF or a LABEL_REF.
2078 Alternatively, this could be fixed by making the dependence on the
2079 PIC_OFFSET_TABLE_REGNUM explicit in the RTL. */
2081 if (flag_pic || profile_flag || profile_block_flag)
2082 emit_insn (gen_blockage ());
2084 /* If we're only restoring one register and sp is not valid then
2085 using a move instruction to restore the register since it's
2086 less work than reloading sp and popping the register. Otherwise,
2087 restore sp (if necessary) and pop the registers. */
2089 limit = frame_pointer_needed
2090 ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM;
2092 if (nregs > 1 || sp_valid)
2096 xops[0] = adj_offsettable_operand (AT_BP (QImode), offset);
2098 emit_insn (gen_movsi_lea (xops[2], XEXP (xops[0], 0)));
2100 output_asm_insn (AS2 (lea%L2,%0,%2), xops);
2103 for (regno = 0; regno < limit; regno++)
2104 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2105 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2107 xops[0] = gen_rtx_REG (SImode, regno);
2110 emit_insn (gen_pop (xops[0]));
2112 output_asm_insn ("pop%L0 %0", xops);
2117 for (regno = 0; regno < limit; regno++)
2118 if ((regs_ever_live[regno] && ! call_used_regs[regno])
2119 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
2121 xops[0] = gen_rtx_REG (SImode, regno);
2122 xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset);
2125 emit_move_insn (xops[0], xops[1]);
2127 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
2132 if (frame_pointer_needed)
2134 /* If not an i386, mov & pop is faster than "leave". */
2136 if (TARGET_USE_LEAVE)
2139 emit_insn (gen_leave());
2141 output_asm_insn ("leave", xops);
2145 xops[0] = frame_pointer_rtx;
2146 xops[1] = stack_pointer_rtx;
2150 emit_insn (gen_epilogue_set_stack_ptr());
2151 emit_insn (gen_pop (xops[0]));
2155 output_asm_insn (AS2 (mov%L2,%0,%2), xops);
2156 output_asm_insn ("pop%L0 %0", xops);
2163 /* Intel's docs say that for 4 or 8 bytes of stack frame one should
2164 use `pop' and not `add'. */
2165 int use_pop = tsize == 4;
2167 /* Use two pops only for the Pentium processors. */
2168 if (tsize == 8 && !TARGET_386 && !TARGET_486)
2170 rtx retval = current_function_return_rtx;
2172 xops[1] = gen_rtx_REG (SImode, 1); /* %edx */
2174 /* This case is a bit more complex. Since we cannot pop into
2175 %ecx twice we need a second register. But this is only
2176 available if the return value is not of DImode in which
2177 case the %edx register is not available. */
2178 use_pop = (retval == NULL
2179 || ! reg_overlap_mentioned_p (xops[1], retval));
2184 xops[0] = gen_rtx_REG (SImode, 2); /* %ecx */
2188 /* We have to prevent the two pops here from being scheduled.
2189 GCC otherwise would try in some situation to put other
2190 instructions in between them which has a bad effect. */
2191 emit_insn (gen_blockage ());
2192 emit_insn (gen_pop (xops[0]));
2194 emit_insn (gen_pop (xops[1]));
2198 output_asm_insn ("pop%L0 %0", xops);
2200 output_asm_insn ("pop%L1 %1", xops);
2205 /* If there is no frame pointer, we must still release the frame. */
2206 xops[0] = GEN_INT (tsize);
2209 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2210 gen_rtx (PLUS, SImode, xops[2], xops[0])));
2212 output_asm_insn (AS2 (add%L2,%0,%2), xops);
2216 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
2217 if (profile_block_flag == 2)
2219 FUNCTION_BLOCK_PROFILER_EXIT(file);
2223 if (current_function_pops_args && current_function_args_size)
2225 xops[1] = GEN_INT (current_function_pops_args);
2227 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
2228 asked to pop more, pop return address, do explicit add, and jump
2229 indirectly to the caller. */
2231 if (current_function_pops_args >= 32768)
2233 /* ??? Which register to use here? */
2234 xops[0] = gen_rtx_REG (SImode, 2);
2238 emit_insn (gen_pop (xops[0]));
2239 emit_insn (gen_rtx (SET, VOIDmode, xops[2],
2240 gen_rtx (PLUS, SImode, xops[1], xops[2])));
2241 emit_jump_insn (xops[0]);
2245 output_asm_insn ("pop%L0 %0", xops);
2246 output_asm_insn (AS2 (add%L2,%1,%2), xops);
2247 output_asm_insn ("jmp %*%0", xops);
2253 emit_jump_insn (gen_return_pop_internal (xops[1]));
2255 output_asm_insn ("ret %1", xops);
2261 emit_jump_insn (gen_return_internal ());
2263 output_asm_insn ("ret", xops);
2267 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2268 that is a valid memory address for an instruction.
2269 The MODE argument is the machine mode for the MEM expression
2270 that wants to use this address.
2272 On x86, legitimate addresses are:
2273 base movl (base),reg
2274 displacement movl disp,reg
2275 base + displacement movl disp(base),reg
2276 index + base movl (base,index),reg
2277 (index + base) + displacement movl disp(base,index),reg
2278 index*scale movl (,index,scale),reg
2279 index*scale + disp movl disp(,index,scale),reg
2280 index*scale + base movl (base,index,scale),reg
2281 (index*scale + base) + disp movl disp(base,index,scale),reg
2283 In each case, scale can be 1, 2, 4, 8. */
2285 /* This is exactly the same as print_operand_addr, except that
2286 it recognizes addresses instead of printing them.
2288 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2289 convert common non-canonical forms to canonical form so that they will
2292 #define ADDR_INVALID(msg,insn) \
2294 if (TARGET_DEBUG_ADDR) \
2296 fprintf (stderr, msg); \
2302 legitimate_pic_address_disp_p (disp)
2305 if (GET_CODE (disp) != CONST)
2307 disp = XEXP (disp, 0);
2309 if (GET_CODE (disp) == PLUS)
2311 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
2313 disp = XEXP (disp, 0);
2316 if (GET_CODE (disp) != UNSPEC
2317 || XVECLEN (disp, 0) != 1)
2320 /* Must be @GOT or @GOTOFF. */
2321 if (XINT (disp, 1) != 6
2322 && XINT (disp, 1) != 7)
2325 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2326 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
2333 legitimate_address_p (mode, addr, strict)
2334 enum machine_mode mode;
2338 rtx base = NULL_RTX;
2339 rtx indx = NULL_RTX;
2340 rtx scale = NULL_RTX;
2341 rtx disp = NULL_RTX;
2343 if (TARGET_DEBUG_ADDR)
2346 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
2347 GET_MODE_NAME (mode), strict);
2352 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
2355 else if (GET_CODE (addr) == PLUS)
2357 rtx op0 = XEXP (addr, 0);
2358 rtx op1 = XEXP (addr, 1);
2359 enum rtx_code code0 = GET_CODE (op0);
2360 enum rtx_code code1 = GET_CODE (op1);
2362 if (code0 == REG || code0 == SUBREG)
2364 if (code1 == REG || code1 == SUBREG)
2366 indx = op0; /* index + base */
2372 base = op0; /* base + displacement */
2377 else if (code0 == MULT)
2379 indx = XEXP (op0, 0);
2380 scale = XEXP (op0, 1);
2382 if (code1 == REG || code1 == SUBREG)
2383 base = op1; /* index*scale + base */
2386 disp = op1; /* index*scale + disp */
2389 else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
2391 indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */
2392 scale = XEXP (XEXP (op0, 0), 1);
2393 base = XEXP (op0, 1);
2397 else if (code0 == PLUS)
2399 indx = XEXP (op0, 0); /* index + base + disp */
2400 base = XEXP (op0, 1);
2406 ADDR_INVALID ("PLUS subcode is not valid.\n", op0);
2411 else if (GET_CODE (addr) == MULT)
2413 indx = XEXP (addr, 0); /* index*scale */
2414 scale = XEXP (addr, 1);
2418 disp = addr; /* displacement */
2420 /* Allow arg pointer and stack pointer as index if there is not scaling */
2421 if (base && indx && !scale
2422 && (indx == arg_pointer_rtx || indx == stack_pointer_rtx))
2429 /* Validate base register:
2431 Don't allow SUBREG's here, it can lead to spill failures when the base
2432 is one word out of a two word structure, which is represented internally
2437 if (GET_CODE (base) != REG)
2439 ADDR_INVALID ("Base is not a register.\n", base);
2443 if (GET_MODE (base) != Pmode)
2445 ADDR_INVALID ("Base is not in Pmode.\n", base);
2449 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base))
2450 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base)))
2452 ADDR_INVALID ("Base is not valid.\n", base);
2457 /* Validate index register:
2459 Don't allow SUBREG's here, it can lead to spill failures when the index
2460 is one word out of a two word structure, which is represented internally
2464 if (GET_CODE (indx) != REG)
2466 ADDR_INVALID ("Index is not a register.\n", indx);
2470 if (GET_MODE (indx) != Pmode)
2472 ADDR_INVALID ("Index is not in Pmode.\n", indx);
2476 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (indx))
2477 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (indx)))
2479 ADDR_INVALID ("Index is not valid.\n", indx);
2484 abort (); /* scale w/o index invalid */
2486 /* Validate scale factor: */
2489 HOST_WIDE_INT value;
2491 if (GET_CODE (scale) != CONST_INT)
2493 ADDR_INVALID ("Scale is not valid.\n", scale);
2497 value = INTVAL (scale);
2498 if (value != 1 && value != 2 && value != 4 && value != 8)
2500 ADDR_INVALID ("Scale is not a good multiplier.\n", scale);
2505 /* Validate displacement. */
2508 if (!CONSTANT_ADDRESS_P (disp))
2510 ADDR_INVALID ("Displacement is not valid.\n", disp);
2514 else if (GET_CODE (disp) == CONST_DOUBLE)
2516 ADDR_INVALID ("Displacement is a const_double.\n", disp);
2520 if (flag_pic && SYMBOLIC_CONST (disp))
2522 if (! legitimate_pic_address_disp_p (disp))
2524 ADDR_INVALID ("Displacement is an invalid PIC construct.\n",
2529 if (base != pic_offset_table_rtx
2530 && (indx != pic_offset_table_rtx || scale != NULL_RTX))
2532 ADDR_INVALID ("PIC displacement against invalid base.\n", disp);
2537 else if (HALF_PIC_P ())
2539 if (! HALF_PIC_ADDRESS_P (disp)
2540 || (base != NULL_RTX || indx != NULL_RTX))
2542 ADDR_INVALID ("Displacement is an invalid half-pic reference.\n",
2549 if (TARGET_DEBUG_ADDR)
2550 fprintf (stderr, "Address is valid.\n");
2552 /* Everything looks valid, return true */
2556 /* Return a legitimate reference for ORIG (an address) using the
2557 register REG. If REG is 0, a new pseudo is generated.
2559 There are two types of references that must be handled:
2561 1. Global data references must load the address from the GOT, via
2562 the PIC reg. An insn is emitted to do this load, and the reg is
2565 2. Static data references, constant pool addresses, and code labels
2566 compute the address as an offset from the GOT, whose base is in
2567 the PIC reg. Static data objects have SYMBOL_REF_FLAG set to
2568 differentiate them from global data objects. The returned
2569 address is the PIC reg + an unspec constant.
2571 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2572 reg also appears in the address. */
2575 legitimize_pic_address (orig, reg)
2583 if (GET_CODE (addr) == LABEL_REF
2584 || (GET_CODE (addr) == SYMBOL_REF
2585 && (CONSTANT_POOL_ADDRESS_P (addr)
2586 || SYMBOL_REF_FLAG (addr))))
2588 /* This symbol may be referenced via a displacement from the PIC
2589 base address (@GOTOFF). */
2591 current_function_uses_pic_offset_table = 1;
2592 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 7);
2593 new = gen_rtx_CONST (VOIDmode, new);
2594 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2598 emit_move_insn (reg, new);
2602 else if (GET_CODE (addr) == SYMBOL_REF)
2604 /* This symbol must be referenced via a load from the
2605 Global Offset Table (@GOT). */
2607 current_function_uses_pic_offset_table = 1;
2608 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, addr), 6);
2609 new = gen_rtx_CONST (VOIDmode, new);
2610 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2611 new = gen_rtx_MEM (Pmode, new);
2612 RTX_UNCHANGING_P (new) = 1;
2615 reg = gen_reg_rtx (Pmode);
2616 emit_move_insn (reg, new);
2621 if (GET_CODE (addr) == CONST)
2623 addr = XEXP (addr, 0);
2624 if (GET_CODE (addr) == UNSPEC)
2626 /* Check that the unspec is one of the ones we generate? */
2628 else if (GET_CODE (addr) != PLUS)
2631 if (GET_CODE (addr) == PLUS)
2633 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
2635 /* Check first to see if this is a constant offset from a @GOTOFF
2636 symbol reference. */
2637 if ((GET_CODE (op0) == LABEL_REF
2638 || (GET_CODE (op0) == SYMBOL_REF
2639 && (CONSTANT_POOL_ADDRESS_P (op0)
2640 || SYMBOL_REF_FLAG (op0))))
2641 && GET_CODE (op1) == CONST_INT)
2643 current_function_uses_pic_offset_table = 1;
2644 new = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, op0), 7);
2645 new = gen_rtx_PLUS (VOIDmode, new, op1);
2646 new = gen_rtx_CONST (VOIDmode, new);
2647 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
2651 emit_move_insn (reg, new);
2657 base = legitimize_pic_address (XEXP (addr, 0), reg);
2658 new = legitimize_pic_address (XEXP (addr, 1),
2659 base == reg ? NULL_RTX : reg);
2661 if (GET_CODE (new) == CONST_INT)
2662 new = plus_constant (base, INTVAL (new));
2665 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
2667 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
2668 new = XEXP (new, 1);
2670 new = gen_rtx_PLUS (Pmode, base, new);
2678 /* Emit insns to move operands[1] into operands[0]. */
2681 emit_pic_move (operands, mode)
2683 enum machine_mode mode ATTRIBUTE_UNUSED;
2685 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
2687 if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
2688 operands[1] = force_reg (Pmode, operands[1]);
2690 operands[1] = legitimize_pic_address (operands[1], temp);
2693 /* Try machine-dependent ways of modifying an illegitimate address
2694 to be legitimate. If we find one, return the new, valid address.
2695 This macro is used in only one place: `memory_address' in explow.c.
2697 OLDX is the address as it was before break_out_memory_refs was called.
2698 In some cases it is useful to look at this to decide what needs to be done.
2700 MODE and WIN are passed so that this macro can use
2701 GO_IF_LEGITIMATE_ADDRESS.
2703 It is always safe for this macro to do nothing. It exists to recognize
2704 opportunities to optimize the output.
2706 For the 80386, we handle X+REG by loading X into a register R and
2707 using R+REG. R will go in a general reg and indexing will be used.
2708 However, if REG is a broken-out memory address or multiplication,
2709 nothing needs to be done because REG can certainly go in a general reg.
2711 When -fpic is used, special handling is needed for symbolic references.
2712 See comments by legitimize_pic_address in i386.c for details. */
2715 legitimize_address (x, oldx, mode)
2717 register rtx oldx ATTRIBUTE_UNUSED;
2718 enum machine_mode mode;
2723 if (TARGET_DEBUG_ADDR)
2725 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
2726 GET_MODE_NAME (mode));
2730 if (flag_pic && SYMBOLIC_CONST (x))
2731 return legitimize_pic_address (x, 0);
2733 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2734 if (GET_CODE (x) == ASHIFT
2735 && GET_CODE (XEXP (x, 1)) == CONST_INT
2736 && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4)
2739 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
2740 GEN_INT (1 << log));
2743 if (GET_CODE (x) == PLUS)
2745 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
2747 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2748 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2749 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4)
2752 XEXP (x, 0) = gen_rtx (MULT, Pmode,
2753 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
2754 GEN_INT (1 << log));
2757 if (GET_CODE (XEXP (x, 1)) == ASHIFT
2758 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2759 && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4)
2762 XEXP (x, 1) = gen_rtx (MULT, Pmode,
2763 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
2764 GEN_INT (1 << log));
2767 /* Put multiply first if it isn't already. */
2768 if (GET_CODE (XEXP (x, 1)) == MULT)
2770 rtx tmp = XEXP (x, 0);
2771 XEXP (x, 0) = XEXP (x, 1);
2776 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2777 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2778 created by virtual register instantiation, register elimination, and
2779 similar optimizations. */
2780 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
2783 x = gen_rtx (PLUS, Pmode,
2784 gen_rtx (PLUS, Pmode, XEXP (x, 0),
2785 XEXP (XEXP (x, 1), 0)),
2786 XEXP (XEXP (x, 1), 1));
2790 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2791 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2792 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2793 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2794 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2795 && CONSTANT_P (XEXP (x, 1)))
2798 rtx other = NULL_RTX;
2800 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2802 constant = XEXP (x, 1);
2803 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2805 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2807 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2808 other = XEXP (x, 1);
2816 x = gen_rtx (PLUS, Pmode,
2817 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
2818 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2819 plus_constant (other, INTVAL (constant)));
2823 if (changed && legitimate_address_p (mode, x, FALSE))
2826 if (GET_CODE (XEXP (x, 0)) == MULT)
2829 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
2832 if (GET_CODE (XEXP (x, 1)) == MULT)
2835 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
2839 && GET_CODE (XEXP (x, 1)) == REG
2840 && GET_CODE (XEXP (x, 0)) == REG)
2843 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
2846 x = legitimize_pic_address (x, 0);
2849 if (changed && legitimate_address_p (mode, x, FALSE))
2852 if (GET_CODE (XEXP (x, 0)) == REG)
2854 register rtx temp = gen_reg_rtx (Pmode);
2855 register rtx val = force_operand (XEXP (x, 1), temp);
2857 emit_move_insn (temp, val);
2863 else if (GET_CODE (XEXP (x, 1)) == REG)
2865 register rtx temp = gen_reg_rtx (Pmode);
2866 register rtx val = force_operand (XEXP (x, 0), temp);
2868 emit_move_insn (temp, val);
2878 /* Print an integer constant expression in assembler syntax. Addition
2879 and subtraction are the only arithmetic that may appear in these
2880 expressions. FILE is the stdio stream to write to, X is the rtx, and
2881 CODE is the operand print code from the output string. */
2884 output_pic_addr_const (file, x, code)
2891 switch (GET_CODE (x))
2901 assemble_name (file, XSTR (x, 0));
2902 if (code == 'P' && ! SYMBOL_REF_FLAG (x))
2903 fputs ("@PLT", file);
2910 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
2911 assemble_name (asm_out_file, buf);
2915 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
2919 /* This used to output parentheses around the expression,
2920 but that does not work on the 386 (either ATT or BSD assembler). */
2921 output_pic_addr_const (file, XEXP (x, 0), code);
2925 if (GET_MODE (x) == VOIDmode)
2927 /* We can use %d if the number is <32 bits and positive. */
2928 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
2929 fprintf (file, "0x%lx%08lx",
2930 (unsigned long) CONST_DOUBLE_HIGH (x),
2931 (unsigned long) CONST_DOUBLE_LOW (x));
2933 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
2936 /* We can't handle floating point constants;
2937 PRINT_OPERAND must handle them. */
2938 output_operand_lossage ("floating constant misused");
2942 /* Some assemblers need integer constants to appear first. */
2943 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
2945 output_pic_addr_const (file, XEXP (x, 0), code);
2946 fprintf (file, "+");
2947 output_pic_addr_const (file, XEXP (x, 1), code);
2949 else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2951 output_pic_addr_const (file, XEXP (x, 1), code);
2952 fprintf (file, "+");
2953 output_pic_addr_const (file, XEXP (x, 0), code);
2960 output_pic_addr_const (file, XEXP (x, 0), code);
2961 fprintf (file, "-");
2962 output_pic_addr_const (file, XEXP (x, 1), code);
2966 if (XVECLEN (x, 0) != 1)
2968 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
2969 switch (XINT (x, 1))
2972 fputs ("@GOT", file);
2975 fputs ("@GOTOFF", file);
2978 fputs ("@PLT", file);
2981 output_operand_lossage ("invalid UNSPEC as operand");
2987 output_operand_lossage ("invalid expression as operand");
2992 put_jump_code (code, reverse, file)
2997 int flags = cc_prev_status.flags;
2998 int ieee = (TARGET_IEEE_FP && (flags & CC_IN_80387)
2999 && !(cc_prev_status.flags & CC_FCOMI));
3002 if (flags & CC_Z_IN_NOT_C)
3006 fputs (reverse ? "c" : "nc", file);
3010 fputs (reverse ? "nc" : "c", file);
3021 suffix = reverse ? "ae" : "b";
3026 suffix = reverse ? "ne" : "e";
3029 suffix = reverse ? "ne" : "e";
3032 suffix = reverse ? "e" : "ne";
3037 fputs (suffix, file);
3040 if (flags & CC_TEST_AX)
3042 if ((flags & CC_NO_OVERFLOW) && (code == LE || code == GT))
3045 code = reverse_condition (code);
3057 suffix = flags & CC_IN_80387 ? "a" : "g";
3065 if (flags & CC_NO_OVERFLOW)
3068 suffix = flags & CC_IN_80387 ? "b" : "l";
3076 if (flags & CC_NO_OVERFLOW)
3079 suffix = flags & CC_IN_80387 ? "ae" : "ge";
3087 suffix = flags & CC_IN_80387 ? "be" : "le";
3097 fputs (suffix, file);
3100 /* Append the correct conditional move suffix which corresponds to CODE. */
3103 put_condition_code (code, reverse_cc, mode, file)
3106 enum mode_class mode;
3109 int ieee = (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)
3110 && ! (cc_prev_status.flags & CC_FCOMI));
3111 if (reverse_cc && ! ieee)
3112 code = reverse_condition (code);
3114 if (mode == MODE_INT)
3118 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3125 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3132 if (cc_prev_status.flags & CC_NO_OVERFLOW)
3147 if (cc_prev_status.flags & CC_NO_OVERFLOW)
3170 output_operand_lossage ("Invalid %%C operand");
3173 else if (mode == MODE_FLOAT)
3177 fputs (ieee ? (reverse_cc ? "ne" : "e") : "ne", file);
3180 fputs (ieee ? (reverse_cc ? "ne" : "e") : "e", file);
3183 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3186 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3189 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3192 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3195 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nb", file);
3198 fputs (ieee ? (reverse_cc ? "ne" : "e") : "nbe", file);
3201 fputs (ieee ? (reverse_cc ? "nb" : "b") : "be", file);
3204 fputs (ieee ? (reverse_cc ? "ne" : "e") : "b", file);
3207 output_operand_lossage ("Invalid %%C operand");
3212 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
3213 C -- print opcode suffix for set/cmov insn.
3214 c -- like C, but print reversed condition
3215 F -- print opcode suffix for fcmov insn.
3216 f -- like F, but print reversed condition
3217 D -- print the opcode suffix for a jump
3218 d -- like D, but print reversed condition
3219 R -- print the prefix for register names.
3220 z -- print the opcode suffix for the size of the current operand.
3221 * -- print a star (in certain assembler syntax)
3222 w -- print the operand as if it's a "word" (HImode) even if it isn't.
3223 J -- print the appropriate jump operand.
3224 s -- print a shift double count, followed by the assemblers argument
3226 b -- print the QImode name of the register for the indicated operand.
3227 %b0 would print %al if operands[0] is reg 0.
3228 w -- likewise, print the HImode name of the register.
3229 k -- likewise, print the SImode name of the register.
3230 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
3231 y -- print "st(0)" instead of "st" as a register.
3232 P -- print as a PIC constant
3233 _ -- output "_" if YES_UNDERSCORES */
3236 print_operand (file, x, code)
3251 #ifdef YES_UNDERSCORES
3257 PUT_OP_SIZE (code, 'l', file);
3261 PUT_OP_SIZE (code, 'w', file);
3265 PUT_OP_SIZE (code, 'b', file);
3269 PUT_OP_SIZE (code, 'l', file);
3273 PUT_OP_SIZE (code, 's', file);
3277 PUT_OP_SIZE (code, 't', file);
3281 /* 387 opcodes don't get size suffixes if the operands are
3284 if (STACK_REG_P (x))
3287 /* this is the size of op from size of operand */
3288 switch (GET_MODE_SIZE (GET_MODE (x)))
3291 #ifdef HAVE_GAS_FILDS_FISTS
3292 PUT_OP_SIZE ('W', 's', file);
3297 if (GET_MODE (x) == SFmode)
3299 PUT_OP_SIZE ('S', 's', file);
3303 PUT_OP_SIZE ('L', 'l', file);
3307 PUT_OP_SIZE ('T', 't', file);
3311 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
3313 #ifdef GAS_MNEMONICS
3314 PUT_OP_SIZE ('Q', 'q', file);
3317 PUT_OP_SIZE ('Q', 'l', file); /* Fall through */
3321 PUT_OP_SIZE ('Q', 'l', file);
3338 switch (GET_CODE (x))
3340 /* These conditions are appropriate for testing the result
3341 of an arithmetic operation, not for a compare operation.
3342 Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume
3343 CC_Z_IN_NOT_C false and not floating point. */
3344 case NE: fputs ("jne", file); return;
3345 case EQ: fputs ("je", file); return;
3346 case GE: fputs ("jns", file); return;
3347 case LT: fputs ("js", file); return;
3348 case GEU: fputs ("jmp", file); return;
3349 case GTU: fputs ("jne", file); return;
3350 case LEU: fputs ("je", file); return;
3351 case LTU: fputs ("#branch never", file); return;
3353 /* no matching branches for GT nor LE */
3360 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
3362 PRINT_OPERAND (file, x, 0);
3363 fputs (AS2C (,) + 1, file);
3369 put_jump_code (GET_CODE (x), 0, file);
3373 put_jump_code (GET_CODE (x), 1, file);
3376 /* This is used by the conditional move instructions. */
3378 put_condition_code (GET_CODE (x), 0, MODE_INT, file);
3381 /* Like above, but reverse condition */
3383 put_condition_code (GET_CODE (x), 1, MODE_INT, file); return;
3386 put_condition_code (GET_CODE (x), 0, MODE_FLOAT, file);
3389 /* Like above, but reverse condition */
3391 put_condition_code (GET_CODE (x), 1, MODE_FLOAT, file);
3398 sprintf (str, "invalid operand code `%c'", code);
3399 output_operand_lossage (str);
3404 if (GET_CODE (x) == REG)
3406 PRINT_REG (x, code, file);
3409 else if (GET_CODE (x) == MEM)
3411 PRINT_PTR (x, file);
3412 if (CONSTANT_ADDRESS_P (XEXP (x, 0)))
3415 output_pic_addr_const (file, XEXP (x, 0), code);
3417 output_addr_const (file, XEXP (x, 0));
3420 output_address (XEXP (x, 0));
3423 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
3428 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3429 REAL_VALUE_TO_TARGET_SINGLE (r, l);
3430 PRINT_IMMED_PREFIX (file);
3431 fprintf (file, "0x%lx", l);
3434 /* These float cases don't actually occur as immediate operands. */
3435 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
3440 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3441 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3442 fprintf (file, "%s", dstr);
3445 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
3450 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3451 REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr);
3452 fprintf (file, "%s", dstr);
3458 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3459 PRINT_IMMED_PREFIX (file);
3460 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
3461 || GET_CODE (x) == LABEL_REF)
3462 PRINT_OFFSET_PREFIX (file);
3465 output_pic_addr_const (file, x, code);
3467 output_addr_const (file, x);
3471 /* Print a memory operand whose address is ADDR. */
3474 print_operand_address (file, addr)
3478 register rtx reg1, reg2, breg, ireg;
3481 switch (GET_CODE (addr))
3484 /* ESI addressing makes instruction vector decoded on the K6. We can
3485 avoid this by ESI+0 addressing. */
3486 if (REGNO_REG_CLASS (REGNO (addr)) == SIREG
3487 && ix86_cpu == PROCESSOR_K6 && !optimize_size)
3488 output_addr_const (file, const0_rtx);
3490 fprintf (file, "%se", RP);
3491 fputs (hi_reg_name[REGNO (addr)], file);
3501 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
3503 offset = XEXP (addr, 0);
3504 addr = XEXP (addr, 1);
3506 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
3508 offset = XEXP (addr, 1);
3509 addr = XEXP (addr, 0);
3512 if (GET_CODE (addr) != PLUS)
3514 else if (GET_CODE (XEXP (addr, 0)) == MULT)
3515 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3516 else if (GET_CODE (XEXP (addr, 1)) == MULT)
3517 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3518 else if (GET_CODE (XEXP (addr, 0)) == REG)
3519 reg1 = XEXP (addr, 0), addr = XEXP (addr, 1);
3520 else if (GET_CODE (XEXP (addr, 1)) == REG)
3521 reg1 = XEXP (addr, 1), addr = XEXP (addr, 0);
3523 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT)
3540 if ((reg1 && GET_CODE (reg1) == MULT)
3541 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
3546 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
3552 if (ireg != 0 || breg != 0)
3559 output_pic_addr_const (file, addr, 0);
3560 else if (GET_CODE (addr) == LABEL_REF)
3561 output_asm_label (addr);
3563 output_addr_const (file, addr);
3566 if (ireg != 0 && GET_CODE (ireg) == MULT)
3568 scale = INTVAL (XEXP (ireg, 1));
3569 ireg = XEXP (ireg, 0);
3572 /* The stack pointer can only appear as a base register,
3573 never an index register, so exchange the regs if it is wrong. */
3575 if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM)
3584 /* output breg+ireg*scale */
3585 PRINT_B_I_S (breg, ireg, scale, file);
3593 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
3595 scale = INTVAL (XEXP (addr, 0));
3596 ireg = XEXP (addr, 1);
3600 scale = INTVAL (XEXP (addr, 1));
3601 ireg = XEXP (addr, 0);
3604 /* (reg,reg,) is shorter than (,reg,2). */
3607 PRINT_B_I_S (ireg, ireg, 1, file);
3611 output_addr_const (file, const0_rtx);
3612 PRINT_B_I_S (NULL_RTX, ireg, scale, file);
3618 if (GET_CODE (addr) == CONST_INT
3619 && INTVAL (addr) < 0x8000
3620 && INTVAL (addr) >= -0x8000)
3621 fprintf (file, "%d", (int) INTVAL (addr));
3625 output_pic_addr_const (file, addr, 0);
3627 output_addr_const (file, addr);
3632 /* Set the cc_status for the results of an insn whose pattern is EXP.
3633 On the 80386, we assume that only test and compare insns, as well
3634 as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, BSF, ASHIFT,
3635 ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully.
3636 Also, we assume that jumps, moves and sCOND don't affect the condition
3637 codes. All else clobbers the condition codes, by assumption.
3639 We assume that ALL integer add, minus, etc. instructions effect the
3640 condition codes. This MUST be consistent with i386.md.
3642 We don't record any float test or compare - the redundant test &
3643 compare check in final.c does not handle stack-like regs correctly. */
3646 notice_update_cc (exp)
3649 if (GET_CODE (exp) == SET)
3651 /* Jumps do not alter the cc's. */
3652 if (SET_DEST (exp) == pc_rtx)
3655 /* Moving register or memory into a register:
3656 it doesn't alter the cc's, but it might invalidate
3657 the RTX's which we remember the cc's came from.
3658 (Note that moving a constant 0 or 1 MAY set the cc's). */
3659 if (REG_P (SET_DEST (exp))
3660 && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM
3661 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'
3662 || GET_CODE (SET_SRC (exp)) == IF_THEN_ELSE))
3664 if (cc_status.value1
3665 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3666 cc_status.value1 = 0;
3668 if (cc_status.value2
3669 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3670 cc_status.value2 = 0;
3675 /* Moving register into memory doesn't alter the cc's.
3676 It may invalidate the RTX's which we remember the cc's came from. */
3677 if (GET_CODE (SET_DEST (exp)) == MEM
3678 && (REG_P (SET_SRC (exp))
3679 || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<'))
3681 if (cc_status.value1
3682 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))
3683 cc_status.value1 = 0;
3684 if (cc_status.value2
3685 && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))
3686 cc_status.value2 = 0;
3691 /* Function calls clobber the cc's. */
3692 else if (GET_CODE (SET_SRC (exp)) == CALL)
3698 /* Tests and compares set the cc's in predictable ways. */
3699 else if (SET_DEST (exp) == cc0_rtx)
3702 cc_status.value1 = SET_SRC (exp);
3706 /* Certain instructions effect the condition codes. */
3707 else if (GET_MODE (SET_SRC (exp)) == SImode
3708 || GET_MODE (SET_SRC (exp)) == HImode
3709 || GET_MODE (SET_SRC (exp)) == QImode)
3710 switch (GET_CODE (SET_SRC (exp)))
3712 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
3713 /* Shifts on the 386 don't set the condition codes if the
3714 shift count is zero. */
3715 if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT)
3721 /* We assume that the CONST_INT is non-zero (this rtx would
3722 have been deleted if it were zero. */
3724 case PLUS: case MINUS: case NEG:
3725 case AND: case IOR: case XOR:
3726 cc_status.flags = CC_NO_OVERFLOW;
3727 cc_status.value1 = SET_SRC (exp);
3728 cc_status.value2 = SET_DEST (exp);
3731 /* This is the bsf pattern used by ffs. */
3733 if (XINT (SET_SRC (exp), 1) == 5)
3735 /* Only the Z flag is defined after bsf. */
3737 = CC_NOT_POSITIVE | CC_NOT_NEGATIVE | CC_NO_OVERFLOW;
3738 cc_status.value1 = XVECEXP (SET_SRC (exp), 0, 0);
3739 cc_status.value2 = 0;
3752 else if (GET_CODE (exp) == PARALLEL
3753 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3755 if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx)
3757 if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx)
3761 if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0))))
3763 cc_status.flags |= CC_IN_80387;
3764 if (TARGET_CMOVE && stack_regs_mentioned_p
3765 (XEXP (SET_SRC (XVECEXP (exp, 0, 0)), 1)))
3766 cc_status.flags |= CC_FCOMI;
3769 cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0));
3781 /* Split one or more DImode RTL references into pairs of SImode
3782 references. The RTL can be REG, offsettable MEM, integer constant, or
3783 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3784 split and "num" is its length. lo_half and hi_half are output arrays
3785 that parallel "operands". */
3788 split_di (operands, num, lo_half, hi_half)
3791 rtx lo_half[], hi_half[];
3795 rtx op = operands[num];
3796 if (! reload_completed)
3798 lo_half[num] = gen_lowpart (SImode, op);
3799 hi_half[num] = gen_highpart (SImode, op);
3801 else if (GET_CODE (op) == REG)
3803 lo_half[num] = gen_rtx_REG (SImode, REGNO (op));
3804 hi_half[num] = gen_rtx_REG (SImode, REGNO (op) + 1);
3806 else if (CONSTANT_P (op))
3807 split_double (op, &lo_half[num], &hi_half[num]);
3808 else if (offsettable_memref_p (op))
3810 rtx lo_addr = XEXP (op, 0);
3811 rtx hi_addr = XEXP (adj_offsettable_operand (op, 4), 0);
3812 lo_half[num] = change_address (op, SImode, lo_addr);
3813 hi_half[num] = change_address (op, SImode, hi_addr);
3820 /* Return 1 if this is a valid binary operation on a 387.
3821 OP is the expression matched, and MODE is its mode. */
3824 binary_387_op (op, mode)
3826 enum machine_mode mode;
3828 if (mode != VOIDmode && mode != GET_MODE (op))
3831 switch (GET_CODE (op))
3837 return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT;
3844 /* Return 1 if this is a valid shift or rotate operation on a 386.
3845 OP is the expression matched, and MODE is its mode. */
3850 enum machine_mode mode;
3852 rtx operand = XEXP (op, 0);
3854 if (mode != VOIDmode && mode != GET_MODE (op))
3857 if (GET_MODE (operand) != GET_MODE (op)
3858 || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
3861 return (GET_CODE (op) == ASHIFT
3862 || GET_CODE (op) == ASHIFTRT
3863 || GET_CODE (op) == LSHIFTRT
3864 || GET_CODE (op) == ROTATE
3865 || GET_CODE (op) == ROTATERT);
3868 /* Return 1 if OP is COMPARE rtx with mode VOIDmode.
3869 MODE is not used. */
3872 VOIDmode_compare_op (op, mode)
3874 enum machine_mode mode ATTRIBUTE_UNUSED;
3876 return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode;
3879 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
3880 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
3881 is the expression of the binary operation. The output may either be
3882 emitted here, or returned to the caller, like all output_* functions.
3884 There is no guarantee that the operands are the same mode, as they
3885 might be within FLOAT or FLOAT_EXTEND expressions. */
3888 output_387_binary_op (insn, operands)
3894 static char buf[100];
3896 switch (GET_CODE (operands[3]))
3918 strcpy (buf, base_op);
3920 switch (GET_CODE (operands[3]))
3924 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
3927 operands[2] = operands[1];
3931 if (GET_CODE (operands[2]) == MEM)
3932 return strcat (buf, AS1 (%z2,%2));
3934 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
3937 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3939 if (STACK_TOP_P (operands[0]))
3940 return strcat (buf, AS2 (p,%0,%2));
3942 return strcat (buf, AS2 (p,%2,%0));
3945 if (STACK_TOP_P (operands[0]))
3946 return strcat (buf, AS2C (%y2,%0));
3948 return strcat (buf, AS2C (%2,%0));
3952 if (GET_CODE (operands[1]) == MEM)
3953 return strcat (buf, AS1 (r%z1,%1));
3955 if (GET_CODE (operands[2]) == MEM)
3956 return strcat (buf, AS1 (%z2,%2));
3958 if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2]))
3961 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
3963 if (STACK_TOP_P (operands[0]))
3964 return strcat (buf, AS2 (p,%0,%2));
3966 return strcat (buf, AS2 (rp,%2,%0));
3969 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3971 if (STACK_TOP_P (operands[0]))
3972 return strcat (buf, AS2 (rp,%0,%1));
3974 return strcat (buf, AS2 (p,%1,%0));
3977 if (STACK_TOP_P (operands[0]))
3979 if (STACK_TOP_P (operands[1]))
3980 return strcat (buf, AS2C (%y2,%0));
3982 return strcat (buf, AS2 (r,%y1,%0));
3984 else if (STACK_TOP_P (operands[1]))
3985 return strcat (buf, AS2C (%1,%0));
3987 return strcat (buf, AS2 (r,%2,%0));
3994 /* Output code for INSN to convert a float to a signed int. OPERANDS
3995 are the insn operands. The input may be SFmode, DFmode, or XFmode
3996 and the output operand may be SImode or DImode. As a special case,
3997 make sure that the 387 stack top dies if the output mode is DImode,
3998 because the hardware requires this. */
4001 output_fix_trunc (insn, operands)
4005 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4008 if (! STACK_TOP_P (operands[1]))
4011 if (GET_MODE (operands[0]) == DImode && ! stack_top_dies)
4014 xops[0] = GEN_INT (0x0c00);
4015 xops[1] = operands[5];
4017 output_asm_insn (AS1 (fnstc%W2,%2), operands);
4018 output_asm_insn (AS2 (mov%W5,%2,%w5), operands);
4019 output_asm_insn (AS2 (or%W1,%0,%w1), xops);
4020 output_asm_insn (AS2 (mov%W3,%w5,%3), operands);
4021 output_asm_insn (AS1 (fldc%W3,%3), operands);
4023 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[4] : operands[0];
4026 output_asm_insn (AS1 (fistp%z0,%y0), xops);
4028 output_asm_insn (AS1 (fist%z0,%y0), xops);
4030 if (NON_STACK_REG_P (operands[0]))
4032 if (GET_MODE (operands[0]) == SImode)
4033 output_asm_insn (AS2 (mov%L0,%4,%0), operands);
4036 xops[0] = operands[0];
4037 xops[1] = operands[4];
4038 output_asm_insn (output_move_double (xops), xops);
4042 return AS1 (fldc%W2,%2);
4045 /* Output code for INSN to extend a float. OPERANDS are the insn
4046 operands. The output may be DFmode or XFmode and the input operand
4047 may be SFmode or DFmode. Operands 2 and 3 are scratch memory and
4048 are only necessary if operands 0 or 1 are non-stack registers. */
4051 output_float_extend (insn, operands)
4055 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4058 if (! STACK_TOP_P (operands[0]) && ! STACK_TOP_P (operands[1]))
4061 if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1]) && stack_top_dies)
4064 if (STACK_TOP_P (operands[0]) )
4066 if (NON_STACK_REG_P (operands[1]))
4068 if (GET_MODE (operands[1]) == SFmode)
4069 output_asm_insn (AS2 (mov%L0,%1,%2), operands);
4072 xops[0] = operands[2];
4073 xops[1] = operands[1];
4074 output_asm_insn (output_move_double (xops), xops);
4078 xops[0] = NON_STACK_REG_P (operands[1]) ? operands[2] : operands[1];
4080 output_asm_insn (AS1 (fld%z0,%y0), xops);
4084 xops[0] = NON_STACK_REG_P (operands[0]) ? operands[3] : operands[0];
4087 || (GET_CODE (xops[0]) == MEM && GET_MODE (xops[0]) == XFmode))
4089 output_asm_insn (AS1 (fstp%z0,%y0), xops);
4090 if (! stack_top_dies)
4091 output_asm_insn (AS1 (fld%z0,%y0), xops);
4094 output_asm_insn (AS1 (fst%z0,%y0), xops);
4096 if (NON_STACK_REG_P (operands[0]))
4098 xops[0] = operands[0];
4099 xops[1] = operands[3];
4100 output_asm_insn (output_move_double (xops), xops);
4105 /* Output code for INSN to compare OPERANDS. The two operands might
4106 not have the same mode: one might be within a FLOAT or FLOAT_EXTEND
4107 expression. If the compare is in mode CCFPEQmode, use an opcode that
4108 will not fault if a qNaN is present. */
4111 output_float_compare (insn, operands)
4116 rtx body = XVECEXP (PATTERN (insn), 0, 0);
4117 int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode;
4122 if (TARGET_CMOVE && STACK_REG_P (operands[1])
4123 && STACK_REG_P (operands[0]))
4125 cc_status.flags |= CC_FCOMI;
4126 cc_prev_status.flags &= ~CC_TEST_AX;
4129 if (! STACK_TOP_P (operands[0]))
4132 operands[0] = operands[1];
4134 cc_status.flags |= CC_REVERSED;
4137 if (! STACK_TOP_P (operands[0]))
4140 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
4142 if (STACK_REG_P (operands[1])
4144 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4145 && REGNO (operands[1]) == FIRST_STACK_REG + 1)
4147 /* If both the top of the 387 stack dies, and the other operand
4148 is also a stack register that dies, then this must be a
4149 `fcompp' float compare */
4151 if (unordered_compare)
4153 if (cc_status.flags & CC_FCOMI)
4155 output_asm_insn (AS2 (fucomip,%y1,%0), operands);
4156 output_asm_insn (AS1 (fstp, %y0), operands);
4157 if (!TARGET_IEEE_FP)
4161 output_asm_insn ("fucompp", operands);
4165 if (cc_status.flags & CC_FCOMI)
4167 output_asm_insn (AS2 (fcomip, %y1,%0), operands);
4168 output_asm_insn (AS1 (fstp, %y0), operands);
4169 if (!TARGET_IEEE_FP)
4173 output_asm_insn ("fcompp", operands);
4178 static char buf[100];
4180 /* Decide if this is a float compare or an unordered float compare. */
4182 if (unordered_compare)
4183 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fucomi" : "fucom");
4185 strcpy (buf, (cc_status.flags & CC_FCOMI) ? "fcomi" : "fcom");
4187 /* Modify the opcode if the 387 stack is to be popped. */
4192 if (cc_status.flags & CC_FCOMI)
4194 output_asm_insn (strcat (buf, AS2 (%z1,%y1,%0)), operands);
4195 if (!TARGET_IEEE_FP)
4199 output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands);
4202 /* Now retrieve the condition code. */
4205 char *r = output_fp_cc0_set (insn);
4206 if (r[0]) output_asm_insn (r, operands);
4210 /* We emit fstp instruction after integer comparsions to improve
4212 for (i = 0; i < 2 ; i++)
4214 if (STACK_REG_P (operands[i])
4215 && find_regno_note (insn, REG_DEAD, REGNO (operands[i]))
4216 && REGNO (operands[i]) != FIRST_STACK_REG
4217 && (!stack_top_dies || REGNO (operands[i]) != FIRST_STACK_REG + 1))
4220 xexp[0] = gen_rtx_REG (DFmode,
4221 REGNO (operands[i]) - (stack_top_dies != 0));
4222 output_asm_insn (AS1 (fstp, %y0), xexp);
4231 /* Output opcodes to transfer the results of FP compare or test INSN
4232 from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the
4233 result of the compare or test is unordered, no comparison operator
4234 succeeds except NE. Return an output template, if any. */
4237 output_fp_cc0_set (insn)
4244 if (!(cc_status.flags & CC_FCOMI))
4246 xops[0] = gen_rtx_REG (HImode, 0);
4247 output_asm_insn (AS1 (fnsts%W0,%0), xops);
4250 if (! TARGET_IEEE_FP)
4252 if (!(cc_status.flags & CC_REVERSED))
4254 next = next_cc0_user (insn);
4256 if (GET_CODE (PATTERN (next)) == SET
4257 && SET_DEST (PATTERN (next)) == pc_rtx
4258 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4259 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4260 else if (GET_CODE (PATTERN (next)) == SET)
4261 code = GET_CODE (SET_SRC (PATTERN (next)));
4265 if (code == GT || code == LT || code == EQ || code == NE
4266 || code == LE || code == GE)
4268 /* We will test eax directly. */
4269 cc_status.flags |= CC_TEST_AX;
4277 next = next_cc0_user (insn);
4278 if (next == NULL_RTX)
4281 if (GET_CODE (PATTERN (next)) == SET
4282 && SET_DEST (PATTERN (next)) == pc_rtx
4283 && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4284 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4285 else if (GET_CODE (PATTERN (next)) == SET)
4287 if (GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE)
4288 code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0));
4290 code = GET_CODE (SET_SRC (PATTERN (next)));
4293 else if (GET_CODE (PATTERN (next)) == PARALLEL
4294 && GET_CODE (XVECEXP (PATTERN (next), 0, 0)) == SET)
4296 if (GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0))) == IF_THEN_ELSE)
4297 code = GET_CODE (XEXP (SET_SRC (XVECEXP (PATTERN (next), 0, 0)), 0));
4299 code = GET_CODE (SET_SRC (XVECEXP (PATTERN (next), 0, 0)));
4304 if (cc_status.flags & CC_FCOMI)
4306 /* It is very tricky. We have to do it right. */
4308 xops [0] = gen_rtx_REG (QImode, 0);
4317 output_asm_insn (AS1 (setb,%b0), xops);
4318 output_asm_insn (AS1 (setp,%h0), xops);
4319 output_asm_insn (AS2 (cmp%B0,%b0,%h0), xops);
4323 output_asm_insn (AS1 (setbe,%b0), xops);
4324 output_asm_insn (AS1 (setnp,%h0), xops);
4325 output_asm_insn (AS2 (xor%B0,%b0,%h0), xops);
4330 output_asm_insn (AS1 (setne,%b0), xops);
4331 output_asm_insn (AS1 (setp,%h0), xops);
4332 output_asm_insn (AS2 (or%B0,%b0,%h0), xops);
4345 xops[0] = gen_rtx_REG (QImode, 0);
4350 xops[1] = GEN_INT (0x45);
4351 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4356 xops[1] = GEN_INT (0x45);
4357 xops[2] = GEN_INT (0x01);
4358 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4359 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4364 xops[1] = GEN_INT (0x05);
4365 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4370 xops[1] = GEN_INT (0x45);
4371 xops[2] = GEN_INT (0x40);
4372 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4373 output_asm_insn (AS1 (dec%B0,%h0), xops);
4374 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4379 xops[1] = GEN_INT (0x45);
4380 xops[2] = GEN_INT (0x40);
4381 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4382 output_asm_insn (AS2 (cmp%B0,%2,%h0), xops);
4387 xops[1] = GEN_INT (0x44);
4388 xops[2] = GEN_INT (0x40);
4389 output_asm_insn (AS2 (and%B0,%1,%h0), xops);
4390 output_asm_insn (AS2 (xor%B0,%2,%h0), xops);
4406 #define MAX_386_STACK_LOCALS 2
4408 static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4410 /* Define the structure for the machine field in struct function. */
4411 struct machine_function
4413 rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS];
4415 char pic_label_name[256];
4418 /* Functions to save and restore i386_stack_locals.
4419 These will be called, via pointer variables,
4420 from push_function_context and pop_function_context. */
4423 save_386_machine_status (p)
4427 = (struct machine_function *) xmalloc (sizeof (struct machine_function));
4428 bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals,
4429 sizeof i386_stack_locals);
4430 p->machine->pic_label_rtx = pic_label_rtx;
4431 bcopy (pic_label_name, p->machine->pic_label_name, 256);
4435 restore_386_machine_status (p)
4438 bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals,
4439 sizeof i386_stack_locals);
4440 pic_label_rtx = p->machine->pic_label_rtx;
4441 bcopy (p->machine->pic_label_name, pic_label_name, 256);
4446 /* Clear stack slot assignments remembered from previous functions.
4447 This is called from INIT_EXPANDERS once before RTL is emitted for each
4451 clear_386_stack_locals ()
4453 enum machine_mode mode;
4456 for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE;
4457 mode = (enum machine_mode) ((int) mode + 1))
4458 for (n = 0; n < MAX_386_STACK_LOCALS; n++)
4459 i386_stack_locals[(int) mode][n] = NULL_RTX;
4461 pic_label_rtx = NULL_RTX;
4462 bzero (pic_label_name, 256);
4463 /* Arrange to save and restore i386_stack_locals around nested functions. */
4464 save_machine_status = save_386_machine_status;
4465 restore_machine_status = restore_386_machine_status;
4468 /* Return a MEM corresponding to a stack slot with mode MODE.
4469 Allocate a new slot if necessary.
4471 The RTL for a function can have several slots available: N is
4472 which slot to use. */
4475 assign_386_stack_local (mode, n)
4476 enum machine_mode mode;
4479 if (n < 0 || n >= MAX_386_STACK_LOCALS)
4482 if (i386_stack_locals[(int) mode][n] == NULL_RTX)
4483 i386_stack_locals[(int) mode][n]
4484 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
4486 return i386_stack_locals[(int) mode][n];
4491 enum machine_mode mode ATTRIBUTE_UNUSED;
4493 return (GET_CODE (op) == MULT);
4498 enum machine_mode mode ATTRIBUTE_UNUSED;
4500 return (GET_CODE (op) == DIV);
4504 /* Create a new copy of an rtx.
4505 Recursively copies the operands of the rtx,
4506 except for those few rtx codes that are sharable.
4507 Doesn't share CONST */
4515 register RTX_CODE code;
4516 register char *format_ptr;
4518 code = GET_CODE (orig);
4531 /* SCRATCH must be shared because they represent distinct values. */
4536 /* CONST can be shared if it contains a SYMBOL_REF. If it contains
4537 a LABEL_REF, it isn't sharable. */
4538 if (GET_CODE (XEXP (orig, 0)) == PLUS
4539 && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
4540 && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT)
4544 /* A MEM with a constant address is not sharable. The problem is that
4545 the constant address may need to be reloaded. If the mem is shared,
4546 then reloading one copy of this mem will cause all copies to appear
4547 to have been reloaded. */
4550 copy = rtx_alloc (code);
4551 PUT_MODE (copy, GET_MODE (orig));
4552 copy->in_struct = orig->in_struct;
4553 copy->volatil = orig->volatil;
4554 copy->unchanging = orig->unchanging;
4555 copy->integrated = orig->integrated;
4557 copy->is_spill_rtx = orig->is_spill_rtx;
4559 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
4561 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
4563 switch (*format_ptr++)
4566 XEXP (copy, i) = XEXP (orig, i);
4567 if (XEXP (orig, i) != NULL)
4568 XEXP (copy, i) = copy_rtx (XEXP (orig, i));
4573 XEXP (copy, i) = XEXP (orig, i);
4578 XVEC (copy, i) = XVEC (orig, i);
4579 if (XVEC (orig, i) != NULL)
4581 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
4582 for (j = 0; j < XVECLEN (copy, i); j++)
4583 XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j));
4588 XWINT (copy, i) = XWINT (orig, i);
4592 XINT (copy, i) = XINT (orig, i);
4597 XSTR (copy, i) = XSTR (orig, i);
4608 /* Try to rewrite a memory address to make it valid */
4611 rewrite_address (mem_rtx)
4614 rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx;
4616 int offset_adjust = 0;
4617 int was_only_offset = 0;
4618 rtx mem_addr = XEXP (mem_rtx, 0);
4619 char *storage = oballoc (0);
4621 int is_spill_rtx = 0;
4623 in_struct = MEM_IN_STRUCT_P (mem_rtx);
4624 is_spill_rtx = RTX_IS_SPILL_P (mem_rtx);
4626 if (GET_CODE (mem_addr) == PLUS
4627 && GET_CODE (XEXP (mem_addr, 1)) == PLUS
4628 && GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG)
4630 /* This part is utilized by the combiner. */
4632 = gen_rtx (PLUS, GET_MODE (mem_addr),
4633 gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)),
4634 XEXP (mem_addr, 0), XEXP (XEXP (mem_addr, 1), 0)),
4635 XEXP (XEXP (mem_addr, 1), 1));
4637 if (memory_address_p (GET_MODE (mem_rtx), ret_rtx))
4639 XEXP (mem_rtx, 0) = ret_rtx;
4640 RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx;
4647 /* This part is utilized by loop.c.
4648 If the address contains PLUS (reg,const) and this pattern is invalid
4649 in this case - try to rewrite the address to make it valid. */
4650 storage = oballoc (0);
4651 index_rtx = base_rtx = offset_rtx = NULL;
4653 /* Find the base index and offset elements of the memory address. */
4654 if (GET_CODE (mem_addr) == PLUS)
4656 if (GET_CODE (XEXP (mem_addr, 0)) == REG)
4658 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4659 base_rtx = XEXP (mem_addr, 1), index_rtx = XEXP (mem_addr, 0);
4661 base_rtx = XEXP (mem_addr, 0), offset_rtx = XEXP (mem_addr, 1);
4664 else if (GET_CODE (XEXP (mem_addr, 0)) == MULT)
4666 index_rtx = XEXP (mem_addr, 0);
4667 if (GET_CODE (XEXP (mem_addr, 1)) == REG)
4668 base_rtx = XEXP (mem_addr, 1);
4670 offset_rtx = XEXP (mem_addr, 1);
4673 else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS)
4675 if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS
4676 && GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT
4677 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0))
4679 && (GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1))
4681 && (GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1))
4683 && GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG
4684 && GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF)
4686 index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0);
4687 offset_rtx = XEXP (mem_addr, 1);
4688 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4689 offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1));
4693 offset_rtx = XEXP (mem_addr, 1);
4694 index_rtx = XEXP (XEXP (mem_addr, 0), 0);
4695 base_rtx = XEXP (XEXP (mem_addr, 0), 1);
4699 else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT)
4701 was_only_offset = 1;
4704 offset_rtx = XEXP (mem_addr, 1);
4705 offset_adjust = INTVAL (XEXP (mem_addr, 0));
4706 if (offset_adjust == 0)
4708 XEXP (mem_rtx, 0) = offset_rtx;
4709 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4719 else if (GET_CODE (mem_addr) == MULT)
4720 index_rtx = mem_addr;
4727 if (index_rtx != 0 && GET_CODE (index_rtx) == MULT)
4729 if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT)
4735 scale_rtx = XEXP (index_rtx, 1);
4736 scale = INTVAL (scale_rtx);
4737 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4740 /* Now find which of the elements are invalid and try to fix them. */
4741 if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL)
4743 offset_adjust = INTVAL (index_rtx) * scale;
4745 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4746 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4747 else if (offset_rtx == 0)
4748 offset_rtx = const0_rtx;
4750 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4751 XEXP (mem_rtx, 0) = offset_rtx;
4755 if (base_rtx && GET_CODE (base_rtx) == PLUS
4756 && GET_CODE (XEXP (base_rtx, 0)) == REG
4757 && GET_CODE (XEXP (base_rtx, 1)) == CONST_INT)
4759 offset_adjust += INTVAL (XEXP (base_rtx, 1));
4760 base_rtx = copy_all_rtx (XEXP (base_rtx, 0));
4763 else if (base_rtx && GET_CODE (base_rtx) == CONST_INT)
4765 offset_adjust += INTVAL (base_rtx);
4769 if (index_rtx && GET_CODE (index_rtx) == PLUS
4770 && GET_CODE (XEXP (index_rtx, 0)) == REG
4771 && GET_CODE (XEXP (index_rtx, 1)) == CONST_INT)
4773 offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale;
4774 index_rtx = copy_all_rtx (XEXP (index_rtx, 0));
4779 if (! LEGITIMATE_INDEX_P (index_rtx)
4780 && ! (index_rtx == stack_pointer_rtx && scale == 1
4781 && base_rtx == NULL))
4790 if (! LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG)
4797 if (offset_adjust != 0)
4799 if (offset_rtx != 0 && CONSTANT_P (offset_rtx))
4800 offset_rtx = plus_constant (offset_rtx, offset_adjust);
4802 offset_rtx = const0_rtx;
4810 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx),
4811 gen_rtx (MULT, GET_MODE (index_rtx),
4812 index_rtx, scale_rtx),
4815 if (GET_CODE (offset_rtx) != CONST_INT
4816 || INTVAL (offset_rtx) != 0)
4817 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4818 ret_rtx, offset_rtx);
4822 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
4823 index_rtx, base_rtx);
4825 if (GET_CODE (offset_rtx) != CONST_INT
4826 || INTVAL (offset_rtx) != 0)
4827 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4828 ret_rtx, offset_rtx);
4835 ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx),
4836 index_rtx, scale_rtx);
4838 if (GET_CODE (offset_rtx) != CONST_INT
4839 || INTVAL (offset_rtx) != 0)
4840 ret_rtx = gen_rtx (PLUS, GET_MODE (ret_rtx),
4841 ret_rtx, offset_rtx);
4845 if (GET_CODE (offset_rtx) == CONST_INT
4846 && INTVAL (offset_rtx) == 0)
4847 ret_rtx = index_rtx;
4849 ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx),
4850 index_rtx, offset_rtx);
4858 if (GET_CODE (offset_rtx) == CONST_INT
4859 && INTVAL (offset_rtx) == 0)
4862 ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx,
4865 else if (was_only_offset)
4866 ret_rtx = offset_rtx;
4874 XEXP (mem_rtx, 0) = ret_rtx;
4875 RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx;
4886 /* Return 1 if the first insn to set cc before INSN also sets the register
4887 REG_RTX; otherwise return 0. */
4889 last_to_set_cc (reg_rtx, insn)
4892 rtx prev_insn = PREV_INSN (insn);
4896 if (GET_CODE (prev_insn) == NOTE)
4899 else if (GET_CODE (prev_insn) == INSN)
4901 if (GET_CODE (PATTERN (prev_insn)) != SET)
4904 if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx))
4906 if (sets_condition_code (SET_SRC (PATTERN (prev_insn))))
4912 else if (! doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn))))
4919 prev_insn = PREV_INSN (prev_insn);
4926 doesnt_set_condition_code (pat)
4929 switch (GET_CODE (pat))
4942 sets_condition_code (pat)
4945 switch (GET_CODE (pat))
4967 str_immediate_operand (op, mode)
4969 enum machine_mode mode ATTRIBUTE_UNUSED;
4971 if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0)
4981 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4982 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
4983 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
4984 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode))
4990 /* Return 1 if the mode of the SET_DEST of insn is floating point
4991 and it is not an fld or a move from memory to memory.
4992 Otherwise return 0 */
4998 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
4999 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
5000 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
5001 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
5002 && GET_CODE (SET_DEST (PATTERN (insn))) == REG
5003 && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG
5004 && GET_CODE (SET_SRC (PATTERN (insn))) != MEM)
5010 /* Return 1 if the mode of the SET_DEST of INSN is floating point and is
5011 memory and the source is a register. */
5017 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5018 && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode
5019 || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode
5020 || GET_MODE (SET_DEST (PATTERN (insn))) == XFmode)
5021 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
5022 && GET_CODE (SET_SRC (PATTERN (insn))) == REG)
5028 /* Return 1 if DEP_INSN sets a register which INSN uses as a base
5029 or index to reference memory.
5030 otherwise return 0 */
5033 agi_dependent (insn, dep_insn)
5036 int push = 0, push_dep = 0;
5037 if (GET_CODE (dep_insn) == INSN
5038 && GET_CODE (PATTERN (dep_insn)) == SET
5039 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG
5040 && reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn))
5043 if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET
5044 && GET_CODE (SET_DEST (PATTERN (insn))) == MEM
5045 && push_operand (SET_DEST (PATTERN (insn)),
5046 GET_MODE (SET_DEST (PATTERN (insn)))))
5049 if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET
5050 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM
5051 && push_operand (SET_DEST (PATTERN (dep_insn)),
5052 GET_MODE (SET_DEST (PATTERN (dep_insn)))))
5055 /* CPUs contain special hardware to allow two pushes. */
5056 if (push && push_dep)
5059 /* Push operation implicitly change stack pointer causing AGI stalls. */
5060 if (push_dep && reg_mentioned_in_mem (stack_pointer_rtx, insn))
5063 /* Push also implicitly read stack pointer. */
5064 if (push && modified_in_p (stack_pointer_rtx, dep_insn))
5070 /* Return 1 if reg is used in rtl as a base or index for a memory ref
5071 otherwise return 0. */
5074 reg_mentioned_in_mem (reg, rtl)
5079 register enum rtx_code code;
5084 code = GET_CODE (rtl);
5102 if (code == MEM && reg_mentioned_p (reg, rtl))
5105 fmt = GET_RTX_FORMAT (code);
5106 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5110 for (j = XVECLEN (rtl, i) - 1; j >= 0; j--)
5111 if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j)))
5115 else if (fmt[i] == 'e' && reg_mentioned_in_mem (reg, XEXP (rtl, i)))
5122 /* Output the appropriate insns for doing strlen if not just doing repnz; scasb
5124 operands[0] = result, initialized with the startaddress
5125 operands[1] = alignment of the address.
5126 operands[2] = scratch register, initialized with the startaddress when
5127 not aligned, otherwise undefined
5129 This is just the body. It needs the initialisations mentioned above and
5130 some address computing at the end. These things are done in i386.md. */
5133 output_strlen_unroll (operands)
5138 xops[0] = operands[0]; /* Result */
5139 /* operands[1]; * Alignment */
5140 xops[1] = operands[2]; /* Scratch */
5141 xops[2] = GEN_INT (0);
5142 xops[3] = GEN_INT (2);
5143 xops[4] = GEN_INT (3);
5144 xops[5] = GEN_INT (4);
5145 /* xops[6] = gen_label_rtx (); * label when aligned to 3-byte */
5146 /* xops[7] = gen_label_rtx (); * label when aligned to 2-byte */
5147 xops[8] = gen_label_rtx (); /* label of main loop */
5149 if (TARGET_USE_Q_REG && QI_REG_P (xops[1]))
5150 xops[9] = gen_label_rtx (); /* pentium optimisation */
5152 xops[10] = gen_label_rtx (); /* end label 2 */
5153 xops[11] = gen_label_rtx (); /* end label 1 */
5154 xops[12] = gen_label_rtx (); /* end label */
5155 /* xops[13] * Temporary used */
5156 xops[14] = GEN_INT (0xff);
5157 xops[15] = GEN_INT (0xff00);
5158 xops[16] = GEN_INT (0xff0000);
5159 xops[17] = GEN_INT (0xff000000);
5161 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
5163 /* Is there a known alignment and is it less than 4? */
5164 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) < 4)
5166 /* Is there a known alignment and is it not 2? */
5167 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5169 xops[6] = gen_label_rtx (); /* Label when aligned to 3-byte */
5170 xops[7] = gen_label_rtx (); /* Label when aligned to 2-byte */
5172 /* Leave just the 3 lower bits.
5173 If this is a q-register, then the high part is used later
5174 therefore use andl rather than andb. */
5175 output_asm_insn (AS2 (and%L1,%4,%1), xops);
5177 /* Is aligned to 4-byte address when zero */
5178 output_asm_insn (AS1 (je,%l8), xops);
5180 /* Side-effect even Parity when %eax == 3 */
5181 output_asm_insn (AS1 (jp,%6), xops);
5183 /* Is it aligned to 2 bytes ? */
5184 if (QI_REG_P (xops[1]))
5185 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
5187 output_asm_insn (AS2 (cmp%L1,%3,%1), xops);
5189 output_asm_insn (AS1 (je,%7), xops);
5193 /* Since the alignment is 2, we have to check 2 or 0 bytes;
5194 check if is aligned to 4 - byte. */
5195 output_asm_insn (AS2 (and%L1,%3,%1), xops);
5197 /* Is aligned to 4-byte address when zero */
5198 output_asm_insn (AS1 (je,%l8), xops);
5201 xops[13] = gen_rtx_MEM (QImode, xops[0]);
5203 /* Now compare the bytes; compare with the high part of a q-reg
5204 gives shorter code. */
5205 if (QI_REG_P (xops[1]))
5207 /* Compare the first n unaligned byte on a byte per byte basis. */
5208 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5210 /* When zero we reached the end. */
5211 output_asm_insn (AS1 (je,%l12), xops);
5213 /* Increment the address. */
5214 output_asm_insn (AS1 (inc%L0,%0), xops);
5216 /* Not needed with an alignment of 2 */
5217 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5219 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5220 CODE_LABEL_NUMBER (xops[7]));
5221 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5222 output_asm_insn (AS1 (je,%l12), xops);
5223 output_asm_insn (AS1 (inc%L0,%0), xops);
5225 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5226 CODE_LABEL_NUMBER (xops[6]));
5229 output_asm_insn (AS2 (cmp%B1,%h1,%13), xops);
5233 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5234 output_asm_insn (AS1 (je,%l12), xops);
5235 output_asm_insn (AS1 (inc%L0,%0), xops);
5237 /* Not needed with an alignment of 2 */
5238 if (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 2)
5240 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5241 CODE_LABEL_NUMBER (xops[7]));
5242 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5243 output_asm_insn (AS1 (je,%l12), xops);
5244 output_asm_insn (AS1 (inc%L0,%0), xops);
5246 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5247 CODE_LABEL_NUMBER (xops[6]));
5250 output_asm_insn (AS2 (cmp%B13,%2,%13), xops);
5253 output_asm_insn (AS1 (je,%l12), xops);
5254 output_asm_insn (AS1 (inc%L0,%0), xops);
5257 /* Generate loop to check 4 bytes at a time. It is not a good idea to
5258 align this loop. It gives only huge programs, but does not help to
5260 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[8]));
5262 xops[13] = gen_rtx_MEM (SImode, xops[0]);
5263 output_asm_insn (AS2 (mov%L1,%13,%1), xops);
5265 if (QI_REG_P (xops[1]))
5267 /* On i586 it is faster to combine the hi- and lo- part as
5268 a kind of lookahead. If anding both yields zero, then one
5269 of both *could* be zero, otherwise none of both is zero;
5270 this saves one instruction, on i486 this is slower
5271 tested with P-90, i486DX2-66, AMD486DX2-66 */
5274 output_asm_insn (AS2 (test%B1,%h1,%b1), xops);
5275 output_asm_insn (AS1 (jne,%l9), xops);
5278 /* Check first byte. */
5279 output_asm_insn (AS2 (test%B1,%b1,%b1), xops);
5280 output_asm_insn (AS1 (je,%l12), xops);
5282 /* Check second byte. */
5283 output_asm_insn (AS2 (test%B1,%h1,%h1), xops);
5284 output_asm_insn (AS1 (je,%l11), xops);
5287 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5288 CODE_LABEL_NUMBER (xops[9]));
5293 /* Check first byte. */
5294 output_asm_insn (AS2 (test%L1,%14,%1), xops);
5295 output_asm_insn (AS1 (je,%l12), xops);
5297 /* Check second byte. */
5298 output_asm_insn (AS2 (test%L1,%15,%1), xops);
5299 output_asm_insn (AS1 (je,%l11), xops);
5302 /* Check third byte. */
5303 output_asm_insn (AS2 (test%L1,%16,%1), xops);
5304 output_asm_insn (AS1 (je,%l10), xops);
5306 /* Check fourth byte and increment address. */
5307 output_asm_insn (AS2 (add%L0,%5,%0), xops);
5308 output_asm_insn (AS2 (test%L1,%17,%1), xops);
5309 output_asm_insn (AS1 (jne,%l8), xops);
5311 /* Now generate fixups when the compare stops within a 4-byte word. */
5312 output_asm_insn (AS2 (sub%L0,%4,%0), xops);
5314 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[10]));
5315 output_asm_insn (AS1 (inc%L0,%0), xops);
5317 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[11]));
5318 output_asm_insn (AS1 (inc%L0,%0), xops);
5320 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (xops[12]));
5326 output_fp_conditional_move (which_alternative, operands)
5327 int which_alternative;
5330 enum rtx_code code = GET_CODE (operands[1]);
5332 /* This should never happen. */
5333 if (!(cc_prev_status.flags & CC_IN_80387)
5334 && (code == GT || code == LE || code == GE || code == LT))
5337 switch (which_alternative)
5340 /* r <- cond ? arg : r */
5341 output_asm_insn (AS2 (fcmov%F1,%2,%0), operands);
5345 /* r <- cond ? r : arg */
5346 output_asm_insn (AS2 (fcmov%f1,%3,%0), operands);
5357 output_int_conditional_move (which_alternative, operands)
5358 int which_alternative;
5361 enum rtx_code code = GET_CODE (operands[1]);
5363 /* This is very tricky. We have to do it right. For a code segement
5372 final_scan_insn () may delete the insn which sets CC. We have to
5373 tell final_scan_insn () if it should be reinserted. When CODE is
5374 GT or LE, we have to check the CC_NO_OVERFLOW bit and return
5375 NULL_PTR to tell final to reinsert the test insn because the
5376 conditional move cannot be handled properly without it. */
5377 if ((code == GT || code == LE)
5378 && (cc_prev_status.flags & CC_NO_OVERFLOW))
5381 switch (which_alternative)
5384 /* r <- cond ? arg : r */
5385 output_asm_insn (AS2 (cmov%C1,%2,%0), operands);
5389 /* r <- cond ? r : arg */
5390 output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
5401 x86_adjust_cost (insn, link, dep_insn, cost)
5402 rtx insn, link, dep_insn;
5407 if (GET_CODE (dep_insn) == CALL_INSN || GET_CODE (insn) == JUMP_INSN)
5410 if (GET_CODE (dep_insn) == INSN
5411 && GET_CODE (PATTERN (dep_insn)) == SET
5412 && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG
5413 && GET_CODE (insn) == INSN
5414 && GET_CODE (PATTERN (insn)) == SET
5415 && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
5416 SET_SRC (PATTERN (insn))))
5422 case PROCESSOR_PENTIUM:
5423 if (cost != 0 && is_fp_insn (insn) && is_fp_insn (dep_insn)
5424 && !is_fp_dest (dep_insn))
5427 if (agi_dependent (insn, dep_insn))
5428 return cost ? cost + 1 : 2;
5430 if (GET_CODE (insn) == INSN
5431 && GET_CODE (PATTERN (insn)) == SET
5432 && SET_DEST (PATTERN (insn)) == cc0_rtx
5433 && (next_inst = next_nonnote_insn (insn))
5434 && GET_CODE (next_inst) == JUMP_INSN)
5435 /* compare probably paired with jump */
5438 /* Stores stalls one cycle longer than other insns. */
5439 if (is_fp_insn (insn) && cost && is_fp_store (dep_insn))
5444 if (!is_fp_dest (dep_insn))
5446 if(!agi_dependent (insn, dep_insn))
5452 if (is_fp_store (insn) && is_fp_insn (dep_insn)
5453 && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn))
5454 && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))
5455 && (GET_CODE (NEXT_INSN (insn)) == INSN)
5456 && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN)
5457 && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) == NOTE)
5458 && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn))))
5459 == NOTE_INSN_LOOP_END))
5467 /* Output assembly code for a left shift.
5469 Always use "sal" when shifting a memory operand or for a non constant
5472 When optimizing for size, we know that src == dest, and we should always
5473 use "sal". If src != dest, then copy src to dest and use "sal".
5475 Pentium and PPro (speed):
5477 When src == dest, use "add" for a shift counts of one, else use
5478 "sal". If we modeled Pentium AGI stalls and U/V pipelining better we
5479 would want to generate lea for some shifts on the Pentium.
5481 When src != dest, use "lea" for small shift counts. Otherwise,
5482 copy src to dest and use the normal shifting code. Exception for
5483 TARGET_DOUBLE_WITH_ADD. */
5486 output_ashl (insn, operands)
5487 rtx insn, *operands;
5489 /* Handle case where srcreg != dstreg. */
5490 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
5492 if (TARGET_DOUBLE_WITH_ADD && INTVAL (operands[2]) == 1)
5493 switch (GET_MODE (operands[0]))
5496 output_asm_insn (AS2 (mov%L0,%1,%0), operands);
5497 return AS2 (add%L0,%1,%0);
5499 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands);
5500 if (i386_cc_probably_useless_p (insn))
5503 return AS2 (add%L0,%k1,%k0);
5505 return AS2 (add%W0,%k1,%k0);
5507 output_asm_insn (AS2 (mov%B0,%1,%0), operands);
5508 return AS2 (add%B0,%1,%0);
5516 /* This should be extremely rare (impossible?). We can not encode a
5517 shift of the stack pointer using an lea instruction. So copy the
5518 stack pointer into the destination register and use an lea. */
5519 if (operands[1] == stack_pointer_rtx)
5521 output_asm_insn (AS2 (mov%L0,%k1,%k0), operands);
5522 operands[1] = operands[0];
5525 /* For shifts up to and including 3 bits, use lea. */
5526 operands[1] = gen_rtx_MULT (SImode,
5527 gen_rtx_REG (SImode, REGNO (operands[1])),
5528 GEN_INT (1 << INTVAL (operands[2])));
5529 return AS2 (lea%L0,%a1,%k0);
5533 /* Source and destination match. */
5535 /* Handle variable shift. */
5536 if (REG_P (operands[2]))
5537 switch (GET_MODE (operands[0]))
5540 return AS2 (sal%L0,%b2,%0);
5542 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
5545 return AS2 (sal%L0,%b2,%k0);
5548 return AS2 (sal%W0,%b2,%0);
5550 return AS2 (sal%B0,%b2,%0);
5555 /* Always perform shift by 1 using an add instruction. */
5556 if (REG_P (operands[0]) && operands[2] == const1_rtx)
5557 switch (GET_MODE (operands[0]))
5560 return AS2 (add%L0,%0,%0);
5562 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
5565 return AS2 (add%L0,%k0,%k0);
5568 return AS2 (add%W0,%0,%0);
5570 return AS2 (add%B0,%0,%0);
5576 /* ??? Currently disabled. Because our model of Pentium is far from being
5577 exact, this change will need some benchmarking. */
5578 /* Shift reg by 2 or 3 use an lea instruction for Pentium if this is
5579 insn is expected to issue into the V pipe (the insn's mode will be
5580 TImode for a U pipe, and !TImode for a V pipe instruction). */
5582 && REG_P (operands[0])
5583 && GET_CODE (operands[2]) == CONST_INT
5584 && INTVAL (operands[2]) <= 3
5585 && (int)ix86_cpu == (int)PROCESSOR_PENTIUM
5586 && GET_MODE (insn) != TImode)
5589 operands[1] = gen_rtx_MULT (SImode, gen_rtx_REG (SImode, REGNO (operands[1])),
5590 GEN_INT (1 << INTVAL (operands[2])));
5591 return AS2 (lea%L0,%a1,%0);
5595 /* Otherwise use a shift instruction. */
5596 switch (GET_MODE (operands[0]))
5599 return AS2 (sal%L0,%2,%0);
5601 if (REG_P (operands[0]) && i386_cc_probably_useless_p (insn))
5604 return AS2 (sal%L0,%2,%k0);
5607 return AS2 (sal%W0,%2,%0);
5609 return AS2 (sal%B0,%2,%0);
5615 /* Given the memory address ADDR, calculate the length of the address or
5616 the length of just the displacement (controlled by DISP_LENGTH).
5618 The length returned does not include the one-byte modrm, opcode,
5622 memory_address_info (addr, disp_length)
5626 rtx base, index, disp, scale;
5630 if (GET_CODE (addr) == PRE_DEC
5631 || GET_CODE (addr) == POST_INC)
5634 /* Register Indirect. */
5635 if (register_operand (addr, Pmode))
5637 /* Special cases: ebp and esp need the two-byte modrm form.
5639 We change [ESI] to [ESI+0] on the K6 when not optimizing
5641 if (addr == stack_pointer_rtx
5642 || addr == arg_pointer_rtx
5643 || addr == frame_pointer_rtx
5644 || (REGNO_REG_CLASS (REGNO (addr)) == SIREG
5645 && ix86_cpu == PROCESSOR_K6 && !optimize_size))
5651 /* Direct Addressing. */
5652 if (CONSTANT_P (addr))
5655 index = base = disp = scale = NULL_RTX;
5656 op0 = XEXP (addr, 0);
5657 op1 = XEXP (addr, 1);
5659 if (GET_CODE (addr) == PLUS)
5661 if (register_operand (op0, Pmode))
5663 if (register_operand (op1, Pmode))
5664 index = op0, base = op1;
5666 base = op0, disp = op1;
5668 else if (GET_CODE (op0) == MULT)
5670 index = XEXP (op0, 0);
5671 scale = XEXP (op0, 1);
5672 if (register_operand (op1, Pmode))
5677 else if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == MULT)
5679 index = XEXP (XEXP (op0, 0), 0);
5680 scale = XEXP (XEXP (op0, 0), 1);
5681 base = XEXP (op0, 1);
5684 else if (GET_CODE (op0) == PLUS)
5686 index = XEXP (op0, 0);
5687 base = XEXP (op0, 1);
5693 else if (GET_CODE (addr) == MULT
5694 /* We're called for lea too, which implements ashift on occasion. */
5695 || GET_CODE (addr) == ASHIFT)
5697 index = XEXP (addr, 0);
5698 scale = XEXP (addr, 1);
5703 /* Allow arg pointer and stack pointer as index if there is not scaling */
5704 if (base && index && !scale
5705 && (index == stack_pointer_rtx
5706 || index == arg_pointer_rtx
5707 || index == frame_pointer_rtx))
5714 /* Special case: ebp cannot be encoded as a base without a displacement. */
5715 if (base == frame_pointer_rtx && !disp)
5718 /* Scaling can not be encoded without base or displacement.
5719 Except for scale == 1 where we can encode reg + reg instead of reg * 2. */
5721 && (!scale || GET_CODE (scale) != CONST_INT || (INTVAL (scale) != 1)))
5724 /* Find the length of the displacement constant. */
5728 if (GET_CODE (disp) == CONST_INT
5729 && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K'))
5735 /* An index requires the two-byte modrm form. Not important
5736 if we are computing just length of the displacement. */
5737 if (index && ! disp_length)