1 ;; Itanium2 DFA descriptions for insn scheduling and bundling.
2 ;; Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc.
3 ;; Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA. */
23 /* This is description of pipeline hazards based on DFA. The
24 following constructions can be used for this:
26 o define_cpu_unit string [string]) describes a cpu functional unit
29 1st operand: Names of cpu function units.
30 2nd operand: Name of automaton (see comments for
33 All define_reservations and define_cpu_units should have unique
34 names which cannot be "nothing".
36 o (exclusion_set string string) means that each CPU function unit
37 in the first string cannot be reserved simultaneously with each
38 unit whose name is in the second string and vise versa. CPU
39 units in the string are separated by commas. For example, it is
40 useful for description CPU with fully pipelined floating point
41 functional unit which can execute simultaneously only single
42 floating point insns or only double floating point insns.
44 o (presence_set string string) means that each CPU function unit in
45 the first string cannot be reserved unless at least one of
46 pattern of units whose names are in the second string is
47 reserved. This is an asymmetric relation. CPU units or unit
48 patterns in the strings are separated by commas. Pattern is one
49 unit name or unit names separated by white-spaces.
51 For example, it is useful for description that slot1 is reserved
52 after slot0 reservation for a VLIW processor. We could describe
53 it by the following construction
55 (presence_set "slot1" "slot0")
57 Or slot1 is reserved only after slot0 and unit b0 reservation.
58 In this case we could write
60 (presence_set "slot1" "slot0 b0")
62 All CPU functional units in a set should belong to the same
65 o (final_presence_set string string) is analogous to
66 `presence_set'. The difference between them is when checking is
67 done. When an instruction is issued in given automaton state
68 reflecting all current and planned unit reservations, the
69 automaton state is changed. The first state is a source state,
70 the second one is a result state. Checking for `presence_set' is
71 done on the source state reservation, checking for
72 `final_presence_set' is done on the result reservation. This
73 construction is useful to describe a reservation which is
74 actually two subsequent reservations. For example, if we use
76 (presence_set "slot1" "slot0")
78 the following insn will be never issued (because slot1 requires
79 slot0 which is absent in the source state).
81 (define_reservation "insn_and_nop" "slot0 + slot1")
83 but it can be issued if we use analogous `final_presence_set'.
85 o (absence_set string string) means that each CPU function unit in
86 the first string can be reserved only if each pattern of units
87 whose names are in the second string is not reserved. This is an
88 asymmetric relation (actually exclusion set is analogous to this
89 one but it is symmetric). CPU units or unit patterns in the
90 string are separated by commas. Pattern is one unit name or unit
91 names separated by white-spaces.
93 For example, it is useful for description that slot0 cannot be
94 reserved after slot1 or slot2 reservation for a VLIW processor.
95 We could describe it by the following construction
97 (absence_set "slot2" "slot0, slot1")
99 Or slot2 cannot be reserved if slot0 and unit b0 are reserved or
100 slot1 and unit b1 are reserved . In this case we could write
102 (absence_set "slot2" "slot0 b0, slot1 b1")
104 All CPU functional units in a set should to belong the same
107 o (final_absence_set string string) is analogous to `absence_set' but
108 checking is done on the result (state) reservation. See comments
109 for final_presence_set.
111 o (define_bypass number out_insn_names in_insn_names) names bypass with
112 given latency (the first number) from insns given by the first
113 string (see define_insn_reservation) into insns given by the
114 second string. Insn names in the strings are separated by
117 o (define_automaton string) describes names of an automaton
118 generated and used for pipeline hazards recognition. The names
119 are separated by comma. Actually it is possibly to generate the
120 single automaton but unfortunately it can be very large. If we
121 use more one automata, the summary size of the automata usually
122 is less than the single one. The automaton name is used in
123 define_cpu_unit. All automata should have unique names.
125 o (automata_option string) describes option for generation of
126 automata. Currently there are the following options:
128 o "no-minimization" which makes no minimization of automata.
129 This is only worth to do when we are debugging the description
130 and need to look more accurately at reservations of states.
132 o "ndfa" which makes automata with nondetermenistic reservation
135 o (define_reservation string string) names reservation (the first
136 string) of cpu functional units (the 2nd string). Sometimes unit
137 reservations for different insns contain common parts. In such
138 case, you describe common part and use one its name (the 1st
139 parameter) in regular expression in define_insn_reservation. All
140 define_reservations, define results and define_cpu_units should
141 have unique names which cannot be "nothing".
143 o (define_insn_reservation name default_latency condition regexpr)
144 describes reservation of cpu functional units (the 3nd operand)
145 for instruction which is selected by the condition (the 2nd
146 parameter). The first parameter is used for output of debugging
147 information. The reservations are described by a regular
148 expression according the following syntax:
150 regexp = regexp "," oneof
153 oneof = oneof "|" allof
156 allof = allof "+" repeat
159 repeat = element "*" number
162 element = cpu_function_name
168 1. "," is used for describing start of the next cycle in
171 2. "|" is used for describing the reservation described by the
172 first regular expression *or* the reservation described by
173 the second regular expression *or* etc.
175 3. "+" is used for describing the reservation described by the
176 first regular expression *and* the reservation described by
177 the second regular expression *and* etc.
179 4. "*" is used for convenience and simply means sequence in
180 which the regular expression are repeated NUMBER times with
181 cycle advancing (see ",").
183 5. cpu function unit name which means reservation.
185 6. reservation name -- see define_reservation.
187 7. string "nothing" means no units reservation.
191 (define_automaton "two")
193 ;; All possible combinations of bundles/syllables
194 (define_cpu_unit "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
195 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" "two")
196 (define_cpu_unit "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\
197 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." "two")
198 (define_cpu_unit "2_0mii., 2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\
199 2_0mib., 2_0mmb., 2_0mfb." "two")
201 (define_cpu_unit "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\
202 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" "two")
203 (define_cpu_unit "2_1mi.i, 2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\
204 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx." "two")
205 (define_cpu_unit "2_1mii., 2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\
206 2_1mib., 2_1mmb., 2_1mfb." "two")
209 (exclusion_set "2_0m.ii" "2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
210 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
211 (exclusion_set "2_0m.mi" "2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib,\
212 2_0m.mb, 2_0m.fb, 2_0m.lx")
213 (exclusion_set "2_0m.fi" "2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb,\
215 (exclusion_set "2_0m.mf" "2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb,\
217 (exclusion_set "2_0b.bb" "2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
218 (exclusion_set "2_0m.bb" "2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
219 (exclusion_set "2_0m.ib" "2_0m.mb, 2_0m.fb, 2_0m.lx")
220 (exclusion_set "2_0m.mb" "2_0m.fb, 2_0m.lx")
221 (exclusion_set "2_0m.fb" "2_0m.lx")
224 (exclusion_set "2_0mi.i" "2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\
225 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
226 (exclusion_set "2_0mm.i" "2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\
227 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
228 (exclusion_set "2_0mf.i" "2_0mm.f, 2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b,\
230 (exclusion_set "2_0mm.f" "2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b,\
232 (exclusion_set "2_0bb.b" "2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
233 (exclusion_set "2_0mb.b" "2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
234 (exclusion_set "2_0mi.b" "2_0mm.b, 2_0mf.b, 2_0mlx.")
235 (exclusion_set "2_0mm.b" "2_0mf.b, 2_0mlx.")
236 (exclusion_set "2_0mf.b" "2_0mlx.")
239 (exclusion_set "2_0mii." "2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\
240 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.")
241 (exclusion_set "2_0mmi." "2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\
242 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.")
243 (exclusion_set "2_0mfi." "2_0mmf., 2_0bbb., 2_0mbb., 2_0mib., 2_0mmb.,\
245 (exclusion_set "2_0mmf." "2_0bbb., 2_0mbb., 2_0mib., 2_0mmb., 2_0mfb.,\
247 (exclusion_set "2_0bbb." "2_0mbb., 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.")
248 (exclusion_set "2_0mbb." "2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.")
249 (exclusion_set "2_0mib." "2_0mmb., 2_0mfb., 2_0mlx.")
250 (exclusion_set "2_0mmb." "2_0mfb., 2_0mlx.")
251 (exclusion_set "2_0mfb." "2_0mlx.")
254 (exclusion_set "2_1m.ii" "2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\
255 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx")
256 (exclusion_set "2_1m.mi" "2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib,\
257 2_1m.mb, 2_1m.fb, 2_1m.lx")
258 (exclusion_set "2_1m.fi" "2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb,\
260 (exclusion_set "2_1m.mf" "2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb,\
262 (exclusion_set "2_1b.bb" "2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx")
263 (exclusion_set "2_1m.bb" "2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx")
264 (exclusion_set "2_1m.ib" "2_1m.mb, 2_1m.fb, 2_1m.lx")
265 (exclusion_set "2_1m.mb" "2_1m.fb, 2_1m.lx")
266 (exclusion_set "2_1m.fb" "2_1m.lx")
269 (exclusion_set "2_1mi.i" "2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\
270 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.")
271 (exclusion_set "2_1mm.i" "2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\
272 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.")
273 (exclusion_set "2_1mf.i" "2_1mm.f, 2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b,\
275 (exclusion_set "2_1mm.f" "2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b,\
277 (exclusion_set "2_1bb.b" "2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.")
278 (exclusion_set "2_1mb.b" "2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.")
279 (exclusion_set "2_1mi.b" "2_1mm.b, 2_1mf.b, 2_1mlx.")
280 (exclusion_set "2_1mm.b" "2_1mf.b, 2_1mlx.")
281 (exclusion_set "2_1mf.b" "2_1mlx.")
284 (exclusion_set "2_1mii." "2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\
285 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.")
286 (exclusion_set "2_1mmi." "2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\
287 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.")
288 (exclusion_set "2_1mfi." "2_1mmf., 2_1bbb., 2_1mbb., 2_1mib., 2_1mmb.,\
290 (exclusion_set "2_1mmf." "2_1bbb., 2_1mbb., 2_1mib., 2_1mmb., 2_1mfb.,\
292 (exclusion_set "2_1bbb." "2_1mbb., 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.")
293 (exclusion_set "2_1mbb." "2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.")
294 (exclusion_set "2_1mib." "2_1mmb., 2_1mfb., 2_1mlx.")
295 (exclusion_set "2_1mmb." "2_1mfb., 2_1mlx.")
296 (exclusion_set "2_1mfb." "2_1mlx.")
298 (final_presence_set "2_0mi.i" "2_0m.ii")
299 (final_presence_set "2_0mii." "2_0mi.i")
300 (final_presence_set "2_1mi.i" "2_1m.ii")
301 (final_presence_set "2_1mii." "2_1mi.i")
303 (final_presence_set "2_0mm.i" "2_0m.mi")
304 (final_presence_set "2_0mmi." "2_0mm.i")
305 (final_presence_set "2_1mm.i" "2_1m.mi")
306 (final_presence_set "2_1mmi." "2_1mm.i")
308 (final_presence_set "2_0mf.i" "2_0m.fi")
309 (final_presence_set "2_0mfi." "2_0mf.i")
310 (final_presence_set "2_1mf.i" "2_1m.fi")
311 (final_presence_set "2_1mfi." "2_1mf.i")
313 (final_presence_set "2_0mm.f" "2_0m.mf")
314 (final_presence_set "2_0mmf." "2_0mm.f")
315 (final_presence_set "2_1mm.f" "2_1m.mf")
316 (final_presence_set "2_1mmf." "2_1mm.f")
318 (final_presence_set "2_0bb.b" "2_0b.bb")
319 (final_presence_set "2_0bbb." "2_0bb.b")
320 (final_presence_set "2_1bb.b" "2_1b.bb")
321 (final_presence_set "2_1bbb." "2_1bb.b")
323 (final_presence_set "2_0mb.b" "2_0m.bb")
324 (final_presence_set "2_0mbb." "2_0mb.b")
325 (final_presence_set "2_1mb.b" "2_1m.bb")
326 (final_presence_set "2_1mbb." "2_1mb.b")
328 (final_presence_set "2_0mi.b" "2_0m.ib")
329 (final_presence_set "2_0mib." "2_0mi.b")
330 (final_presence_set "2_1mi.b" "2_1m.ib")
331 (final_presence_set "2_1mib." "2_1mi.b")
333 (final_presence_set "2_0mm.b" "2_0m.mb")
334 (final_presence_set "2_0mmb." "2_0mm.b")
335 (final_presence_set "2_1mm.b" "2_1m.mb")
336 (final_presence_set "2_1mmb." "2_1mm.b")
338 (final_presence_set "2_0mf.b" "2_0m.fb")
339 (final_presence_set "2_0mfb." "2_0mf.b")
340 (final_presence_set "2_1mf.b" "2_1m.fb")
341 (final_presence_set "2_1mfb." "2_1mf.b")
343 (final_presence_set "2_0mlx." "2_0m.lx")
344 (final_presence_set "2_1mlx." "2_1m.lx")
346 ;; The following reflects the dual issue bundle types table.
347 ;; We could place all possible combinations here because impossible
348 ;; combinations would go away by the subsequent constrains.
351 "2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.")
352 (final_presence_set "2_1b.bb" "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mlx.")
354 "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1m.bb,2_1m.ib,2_1m.mb,2_1m.fb"
355 "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.")
357 ;; Ports/units (nb means nop.b insn issued into given port):
359 "2_um0, 2_um1, 2_um2, 2_um3, 2_ui0, 2_ui1, 2_uf0, 2_uf1,\
360 2_ub0, 2_ub1, 2_ub2, 2_unb0, 2_unb1, 2_unb2" "two")
362 (exclusion_set "2_ub0" "2_unb0")
363 (exclusion_set "2_ub1" "2_unb1")
364 (exclusion_set "2_ub2" "2_unb2")
366 ;; The following rules are used to decrease number of alternatives.
367 ;; They are consequences of Itanium2 microarchitecture. They also
368 ;; describe the following rules mentioned in Itanium2
369 ;; microarchitecture: rules mentioned in Itanium2 microarchitecture:
370 ;; o "BBB/MBB: Always splits issue after either of these bundles".
371 ;; o "MIB BBB: Split issue after the first bundle in this pair".
373 "2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb."
374 "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1b.bb,2_1m.bb,\
375 2_1m.ib,2_1m.mb,2_1m.fb,2_1m.lx")
376 (exclusion_set "2_0m.ib,2_0mi.b,2_0mib." "2_1b.bb")
378 ;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
379 ;;; B-slot contains a nop.b or a brp instruction".
380 ;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
381 ;;; nop.b, otherwise it disperses to B2".
383 "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\
384 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx"
385 "2_0mib. 2_ub2, 2_0mfb. 2_ub2, 2_0mmb. 2_ub2")
387 ;; This is necessary to start new processor cycle when we meet stop bit.
388 (define_cpu_unit "2_stop" "two")
390 "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\
391 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\
392 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\
394 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\
395 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\
396 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\
400 ;; The issue logic can reorder M slot insns between different subtypes
401 ;; but cannot reorder insn within the same subtypes. The following
402 ;; constraint is enough to describe this.
403 (final_presence_set "2_um1" "2_um0")
404 (final_presence_set "2_um3" "2_um2")
406 ;; The insn in the 1st I slot of the two bundle issue group will issue
407 ;; to I0. The second I slot insn will issue to I1.
408 (final_presence_set "2_ui1" "2_ui0")
410 ;; For exceptions of I insns:
411 (define_cpu_unit "2_only_ui0" "two")
412 (final_absence_set "2_only_ui0" "2_ui1")
416 (define_reservation "2_M0"
417 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
418 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
419 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
420 +(2_um0|2_um1|2_um2|2_um3)")
422 (define_reservation "2_M1"
423 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
424 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
425 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
426 +(2_um0|2_um1|2_um2|2_um3)")
428 (define_reservation "2_M" "2_M0|2_M1")
430 (define_reservation "2_M0_only_um0"
431 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
432 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
433 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
436 (define_reservation "2_M1_only_um0"
437 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
438 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
439 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
442 (define_reservation "2_M_only_um0" "2_M0_only_um0|2_M1_only_um0")
444 (define_reservation "2_M0_only_um2"
445 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
446 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
447 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
450 (define_reservation "2_M1_only_um2"
451 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
452 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
453 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
456 (define_reservation "2_M_only_um2" "2_M0_only_um2|2_M1_only_um2")
458 (define_reservation "2_M0_only_um23"
459 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
460 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
461 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
464 (define_reservation "2_M1_only_um23"
465 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
466 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
467 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
470 (define_reservation "2_M_only_um23" "2_M0_only_um23|2_M1_only_um23")
472 (define_reservation "2_M0_only_um01"
473 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\
474 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\
475 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\
478 (define_reservation "2_M1_only_um01"
479 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
480 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\
481 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\
484 (define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01")
486 ;; I instruction is dispersed to the lowest numbered I unit
487 ;; not already in use. Remember about possible splitting.
488 (define_reservation "2_I0"
489 "2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\
490 |2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\
491 |(2_1mii.|2_1mmi.|2_1mfi.)+(2_ui0|2_ui1)")
493 (define_reservation "2_I1"
494 "2_0m.ii+(2_um0|2_um1|2_um2|2_um3)+2_0mi.i+2_ui0\
495 |2_0mm.i+(2_um0|2_um1|2_um2|2_um3)+2_0mmi.+2_ui0\
496 |2_0mf.i+2_uf0+2_0mfi.+2_ui0\
497 |2_0m.ib+(2_um0|2_um1|2_um2|2_um3)+2_0mi.b+2_ui0\
498 |(2_1m.ii+2_1mi.i|2_1m.ib+2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)+(2_ui0|2_ui1)\
499 |2_1mm.i+(2_um0|2_um1|2_um2|2_um3)+2_1mmi.+(2_ui0|2_ui1)\
500 |2_1mf.i+2_uf1+2_1mfi.+(2_ui0|2_ui1)")
502 (define_reservation "2_I" "2_I0|2_I1")
504 ;; "An F slot in the 1st bundle disperses to F0".
505 ;; "An F slot in the 2st bundle disperses to F1".
506 (define_reservation "2_F0"
507 "2_0mf.i+2_uf0|2_0mmf.+2_uf0|2_0mf.b+2_uf0\
508 |2_1mf.i+2_uf1|2_1mmf.+2_uf1|2_1mf.b+2_uf1")
510 (define_reservation "2_F1"
511 "(2_0m.fi+2_0mf.i|2_0mm.f+2_0mmf.|2_0m.fb+2_0mf.b)\
512 +(2_um0|2_um1|2_um2|2_um3)+2_uf0\
513 |(2_1m.fi+2_1mf.i|2_1mm.f+2_1mmf.|2_1m.fb+2_1mf.b)\
514 +(2_um0|2_um1|2_um2|2_um3)+2_uf1")
516 (define_reservation "2_F2"
517 "(2_0m.mf+2_0mm.f+2_0mmf.+2_uf0|2_1m.mf+2_1mm.f+2_1mmf.+2_uf1)\
518 +(2_um0|2_um1|2_um2|2_um3)+(2_um0|2_um1|2_um2|2_um3)\
519 |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0\
520 |2_0mmf.+(2_um0|2_um1|2_um2|2_um3)\
521 |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)\
522 +(2_1m.fi+2_1mf.i|2_1m.fb+2_1mf.b)+(2_um0|2_um1|2_um2|2_um3)+2_uf1")
524 (define_reservation "2_F" "2_F0|2_F1|2_F2")
526 ;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
527 ;;; unit. That is, a B slot in 1st position is dispersed to B0. In the
528 ;;; 2nd position it is dispersed to B2".
529 (define_reservation "2_NB"
530 "2_0b.bb+2_unb0|2_0bb.b+2_unb1|2_0bbb.+2_unb2\
531 |2_0mb.b+2_unb1|2_0mbb.+2_unb2|2_0mib.+2_unb0\
532 |2_0mmb.+2_unb0|2_0mfb.+2_unb0\
533 |2_1b.bb+2_unb0|2_1bb.b+2_unb1
534 |2_1bbb.+2_unb2|2_1mb.b+2_unb1|2_1mbb.+2_unb2\
535 |2_1mib.+2_unb0|2_1mmb.+2_unb0|2_1mfb.+2_unb0")
537 (define_reservation "2_B0"
538 "2_0b.bb+2_ub0|2_0bb.b+2_ub1|2_0bbb.+2_ub2\
539 |2_0mb.b+2_ub1|2_0mbb.+2_ub2|2_0mib.+2_ub2\
540 |2_0mfb.+2_ub2|2_1b.bb+2_ub0|2_1bb.b+2_ub1\
541 |2_1bbb.+2_ub2|2_1mb.b+2_ub1\
542 |2_1mib.+2_ub2|2_1mmb.+2_ub2|2_1mfb.+2_ub2")
544 (define_reservation "2_B1"
545 "2_0m.bb+(2_um0|2_um1|2_um2|2_um3)+2_0mb.b+2_ub1\
546 |2_0mi.b+2_ui0+2_0mib.+2_ub2\
547 |2_0mm.b+(2_um0|2_um1|2_um2|2_um3)+2_0mmb.+2_ub2\
548 |2_0mf.b+2_uf0+2_0mfb.+2_ub2\
549 |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0)\
551 |2_1m.bb+(2_um0|2_um1|2_um2|2_um3)+2_1mb.b+2_ub1\
552 |2_1mi.b+(2_ui0|2_ui1)+2_1mib.+2_ub2\
553 |2_1mm.b+(2_um0|2_um1|2_um2|2_um3)+2_1mmb.+2_ub2\
554 |2_1mf.b+2_uf1+2_1mfb.+2_ub2")
556 (define_reservation "2_B" "2_B0|2_B1")
558 ;; MLX bunlde uses ports equivalent to MFI bundles.
560 ;; For the MLI template, the I slot insn is always assigned to port I0
561 ;; if it is in the first bundle or it is assigned to port I1 if it is in
562 ;; the second bundle.
563 (define_reservation "2_L0" "2_0mlx.+2_ui0+2_uf0|2_1mlx.+2_ui1+2_uf1")
565 (define_reservation "2_L1"
566 "2_0m.lx+(2_um0|2_um1|2_um2|2_um3)+2_0mlx.+2_ui0+2_uf0\
567 |2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1")
569 (define_reservation "2_L2"
570 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\
571 |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)
572 +2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1")
574 (define_reservation "2_L" "2_L0|2_L1|2_L2")
576 ;; Should we describe that A insn in I slot can be issued into M
577 ;; ports? I think it is not necessary because of multipass
578 ;; scheduling. For example, the multipass scheduling could use
579 ;; MMI-MMI instead of MII-MII where the two last I slots contain A
580 ;; insns (even if the case is complicated by use-def conflicts).
582 ;; In any case we could describe it as
583 ;; (define_cpu_unit "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" "two")
584 ;; (final_presence_set "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres"
586 ;; (define_reservation "b_A"
588 ;; |(2_1mi.i|2_1mii.|2_1mmi.|2_1mfi.|2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)\
589 ;; +(2_ui1_0pres|2_ui1_1pres|2_ui1_2pres|2_ui1_3pres)")
591 (define_reservation "2_A" "2_M|2_I")
593 ;; We assume that there is no insn issued on the same cycle as the
595 (define_cpu_unit "2_empty" "two")
596 (exclusion_set "2_empty"
597 "2_0m.ii,2_0m.mi,2_0m.fi,2_0m.mf,2_0b.bb,2_0m.bb,2_0m.ib,2_0m.mb,2_0m.fb,\
601 "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs"
604 "2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs"
607 (define_cpu_unit "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont, 2_mb_cont,\
608 2_b_cont, 2_bb_cont" "two")
610 ;; For stop in the middle of the bundles.
611 (define_cpu_unit "2_m_stop, 2_m0_stop, 2_m1_stop, 2_0mmi_cont" "two")
612 (define_cpu_unit "2_mi_stop, 2_mi0_stop, 2_mi1_stop, 2_0mii_cont" "two")
614 (final_presence_set "2_0m_bs"
615 "2_0m.ii, 2_0m.mi, 2_0m.mf, 2_0m.fi, 2_0m.bb,\
616 2_0m.ib, 2_0m.fb, 2_0m.mb, 2_0m.lx")
617 (final_presence_set "2_1m_bs"
618 "2_1m.ii, 2_1m.mi, 2_1m.mf, 2_1m.fi, 2_1m.bb,\
619 2_1m.ib, 2_1m.fb, 2_1m.mb, 2_1m.lx")
620 (final_presence_set "2_0mi_bs" "2_0mi.i, 2_0mi.i")
621 (final_presence_set "2_1mi_bs" "2_1mi.i, 2_1mi.i")
622 (final_presence_set "2_0mm_bs" "2_0mm.i, 2_0mm.f, 2_0mm.b")
623 (final_presence_set "2_1mm_bs" "2_1mm.i, 2_1mm.f, 2_1mm.b")
624 (final_presence_set "2_0mf_bs" "2_0mf.i, 2_0mf.b")
625 (final_presence_set "2_1mf_bs" "2_1mf.i, 2_1mf.b")
626 (final_presence_set "2_0b_bs" "2_0b.bb")
627 (final_presence_set "2_1b_bs" "2_1b.bb")
628 (final_presence_set "2_0bb_bs" "2_0bb.b")
629 (final_presence_set "2_1bb_bs" "2_1bb.b")
630 (final_presence_set "2_0mb_bs" "2_0mb.b")
631 (final_presence_set "2_1mb_bs" "2_1mb.b")
633 (exclusion_set "2_0m_bs"
634 "2_0mi.i, 2_0mm.i, 2_0mm.f, 2_0mf.i, 2_0mb.b,\
635 2_0mi.b, 2_0mf.b, 2_0mm.b, 2_0mlx., 2_m0_stop")
636 (exclusion_set "2_1m_bs"
637 "2_1mi.i, 2_1mm.i, 2_1mm.f, 2_1mf.i, 2_1mb.b,\
638 2_1mi.b, 2_1mf.b, 2_1mm.b, 2_1mlx., 2_m1_stop")
639 (exclusion_set "2_0mi_bs" "2_0mii., 2_0mib., 2_mi0_stop")
640 (exclusion_set "2_1mi_bs" "2_1mii., 2_1mib., 2_mi1_stop")
641 (exclusion_set "2_0mm_bs" "2_0mmi., 2_0mmf., 2_0mmb.")
642 (exclusion_set "2_1mm_bs" "2_1mmi., 2_1mmf., 2_1mmb.")
643 (exclusion_set "2_0mf_bs" "2_0mfi., 2_0mfb.")
644 (exclusion_set "2_1mf_bs" "2_1mfi., 2_1mfb.")
645 (exclusion_set "2_0b_bs" "2_0bb.b")
646 (exclusion_set "2_1b_bs" "2_1bb.b")
647 (exclusion_set "2_0bb_bs" "2_0bbb.")
648 (exclusion_set "2_1bb_bs" "2_1bbb.")
649 (exclusion_set "2_0mb_bs" "2_0mbb.")
650 (exclusion_set "2_1mb_bs" "2_1mbb.")
653 "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs,
654 2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs"
658 "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\
659 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx."
661 (final_presence_set "2_0mii., 2_0mib." "2_mi_cont")
662 (final_presence_set "2_0mmi., 2_0mmf., 2_0mmb." "2_mm_cont")
663 (final_presence_set "2_0mfi., 2_0mfb." "2_mf_cont")
664 (final_presence_set "2_0bb.b" "2_b_cont")
665 (final_presence_set "2_0bbb." "2_bb_cont")
666 (final_presence_set "2_0mbb." "2_mb_cont")
669 "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
670 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx"
671 "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont,\
672 2_mb_cont, 2_b_cont, 2_bb_cont")
674 (exclusion_set "2_empty"
675 "2_m_cont,2_mi_cont,2_mm_cont,2_mf_cont,\
676 2_mb_cont,2_b_cont,2_bb_cont")
679 (final_presence_set "2_m0_stop" "2_0m.mi")
680 (final_presence_set "2_0mm.i" "2_0mmi_cont")
681 (exclusion_set "2_0mmi_cont"
682 "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
683 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
684 (exclusion_set "2_m0_stop" "2_0mm.i")
685 (final_presence_set "2_m1_stop" "2_1m.mi")
686 (exclusion_set "2_m1_stop" "2_1mm.i")
687 (final_presence_set "2_m_stop" "2_m0_stop, 2_m1_stop")
690 (final_presence_set "2_mi0_stop" "2_0mi.i")
691 (final_presence_set "2_0mii." "2_0mii_cont")
692 (exclusion_set "2_0mii_cont"
693 "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\
694 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx")
695 (exclusion_set "2_mi0_stop" "2_0mii.")
696 (final_presence_set "2_mi1_stop" "2_1mi.i")
697 (exclusion_set "2_mi1_stop" "2_1mii.")
698 (final_presence_set "2_mi_stop" "2_mi0_stop, 2_mi1_stop")
701 "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\
702 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\
703 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\
705 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\
706 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\
707 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\
709 "2_m0_stop,2_m1_stop,2_mi0_stop,2_mi1_stop")
711 (define_insn_reservation "2_stop_bit" 0
712 (and (and (eq_attr "cpu" "itanium2")
713 (eq_attr "itanium_class" "stop_bit"))
714 (eq (symbol_ref "bundling_p") (const_int 0)))
715 "2_stop|2_m0_stop|2_m1_stop|2_mi0_stop|2_mi1_stop")
717 (define_insn_reservation "2_br" 0
718 (and (and (eq_attr "cpu" "itanium2")
719 (eq_attr "itanium_class" "br"))
720 (eq (symbol_ref "bundling_p") (const_int 0))) "2_B")
721 (define_insn_reservation "2_scall" 0
722 (and (and (eq_attr "cpu" "itanium2")
723 (eq_attr "itanium_class" "scall"))
724 (eq (symbol_ref "bundling_p") (const_int 0))) "2_B")
725 (define_insn_reservation "2_fcmp" 2
726 (and (and (eq_attr "cpu" "itanium2")
727 (eq_attr "itanium_class" "fcmp"))
728 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
729 (define_insn_reservation "2_fcvtfx" 4
730 (and (and (eq_attr "cpu" "itanium2")
731 (eq_attr "itanium_class" "fcvtfx"))
732 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
733 (define_insn_reservation "2_fld" 6
734 (and (and (and (and (eq_attr "cpu" "itanium2")
735 (eq_attr "itanium_class" "fld"))
736 (eq_attr "data_speculative" "no"))
737 (eq_attr "check_load" "no"))
738 (eq (symbol_ref "bundling_p") (const_int 0)))
740 (define_insn_reservation "2_flda" 6
741 (and (and (and (eq_attr "cpu" "itanium2")
742 (eq_attr "itanium_class" "fld"))
743 (eq_attr "data_speculative" "yes"))
744 (eq (symbol_ref "bundling_p") (const_int 0)))
746 (define_insn_reservation "2_fldc" 0
747 (and (and (and (eq_attr "cpu" "itanium2")
748 (eq_attr "itanium_class" "fld"))
749 (eq_attr "check_load" "yes"))
750 (eq (symbol_ref "bundling_p") (const_int 0)))
753 (define_insn_reservation "2_fldp" 6
754 (and (and (and (eq_attr "cpu" "itanium2")
755 (eq_attr "itanium_class" "fldp"))
756 (eq_attr "check_load" "no"))
757 (eq (symbol_ref "bundling_p") (const_int 0)))
759 (define_insn_reservation "2_fldpc" 0
760 (and (and (and (eq_attr "cpu" "itanium2")
761 (eq_attr "itanium_class" "fldp"))
762 (eq_attr "check_load" "yes"))
763 (eq (symbol_ref "bundling_p") (const_int 0)))
766 (define_insn_reservation "2_fmac" 4
767 (and (and (eq_attr "cpu" "itanium2")
768 (eq_attr "itanium_class" "fmac"))
769 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
770 (define_insn_reservation "2_fmisc" 4
771 (and (and (eq_attr "cpu" "itanium2")
772 (eq_attr "itanium_class" "fmisc"))
773 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
775 ;; There is only one insn `mov = ar.bsp' for frar_i:
777 (define_insn_reservation "2_frar_i" 13
778 (and (and (eq_attr "cpu" "itanium2")
779 (eq_attr "itanium_class" "frar_i"))
780 (eq (symbol_ref "bundling_p") (const_int 0)))
782 ;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m:
784 (define_insn_reservation "2_frar_m" 6
785 (and (and (eq_attr "cpu" "itanium2")
786 (eq_attr "itanium_class" "frar_m"))
787 (eq (symbol_ref "bundling_p") (const_int 0)))
789 (define_insn_reservation "2_frbr" 2
790 (and (and (eq_attr "cpu" "itanium2")
791 (eq_attr "itanium_class" "frbr"))
792 (eq (symbol_ref "bundling_p") (const_int 0)))
794 (define_insn_reservation "2_frfr" 5
795 (and (and (eq_attr "cpu" "itanium2")
796 (eq_attr "itanium_class" "frfr"))
797 (eq (symbol_ref "bundling_p") (const_int 0)))
799 (define_insn_reservation "2_frpr" 2
800 (and (and (eq_attr "cpu" "itanium2")
801 (eq_attr "itanium_class" "frpr"))
802 (eq (symbol_ref "bundling_p") (const_int 0)))
805 (define_insn_reservation "2_ialu" 1
806 (and (and (eq_attr "cpu" "itanium2")
807 (eq_attr "itanium_class" "ialu"))
808 (eq (symbol_ref "bundling_p") (const_int 0)))
810 (define_insn_reservation "2_icmp" 1
811 (and (and (eq_attr "cpu" "itanium2")
812 (eq_attr "itanium_class" "icmp"))
813 (eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
814 (define_insn_reservation "2_ilog" 1
815 (and (and (eq_attr "cpu" "itanium2")
816 (eq_attr "itanium_class" "ilog"))
817 (eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
818 (define_insn_reservation "2_mmalua" 2
819 (and (and (eq_attr "cpu" "itanium2")
820 (eq_attr "itanium_class" "mmalua"))
821 (eq (symbol_ref "bundling_p") (const_int 0))) "2_A")
823 (define_insn_reservation "2_ishf" 1
824 (and (and (eq_attr "cpu" "itanium2")
825 (eq_attr "itanium_class" "ishf"))
826 (eq (symbol_ref "bundling_p") (const_int 0)))
829 (define_insn_reservation "2_ld" 1
830 (and (and (and (eq_attr "cpu" "itanium2")
831 (eq_attr "itanium_class" "ld"))
832 (eq_attr "check_load" "no"))
833 (eq (symbol_ref "bundling_p") (const_int 0)))
835 (define_insn_reservation "2_ldc" 0
836 (and (and (eq_attr "cpu" "itanium2")
837 (eq_attr "check_load" "yes"))
838 (eq (symbol_ref "bundling_p") (const_int 0)))
841 (define_insn_reservation "2_long_i" 1
842 (and (and (eq_attr "cpu" "itanium2")
843 (eq_attr "itanium_class" "long_i"))
844 (eq (symbol_ref "bundling_p") (const_int 0))) "2_L")
846 (define_insn_reservation "2_mmmul" 2
847 (and (and (eq_attr "cpu" "itanium2")
848 (eq_attr "itanium_class" "mmmul"))
849 (eq (symbol_ref "bundling_p") (const_int 0)))
852 (define_insn_reservation "2_mmshf" 2
853 (and (and (eq_attr "cpu" "itanium2")
854 (eq_attr "itanium_class" "mmshf"))
855 (eq (symbol_ref "bundling_p") (const_int 0))) "2_I")
857 (define_insn_reservation "2_mmshfi" 1
858 (and (and (eq_attr "cpu" "itanium2")
859 (eq_attr "itanium_class" "mmshfi"))
860 (eq (symbol_ref "bundling_p") (const_int 0))) "2_I")
862 ;; Now we have only one insn (flushrs) of such class. We assume that flushrs
863 ;; is the 1st syllable of the bundle after stop bit.
864 (define_insn_reservation "2_rse_m" 0
865 (and (and (eq_attr "cpu" "itanium2")
866 (eq_attr "itanium_class" "rse_m"))
867 (eq (symbol_ref "bundling_p") (const_int 0)))
868 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb\
869 |2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx)+2_um0")
870 (define_insn_reservation "2_sem" 0
871 (and (and (eq_attr "cpu" "itanium2")
872 (eq_attr "itanium_class" "sem"))
873 (eq (symbol_ref "bundling_p") (const_int 0)))
876 (define_insn_reservation "2_stf" 1
877 (and (and (eq_attr "cpu" "itanium2")
878 (eq_attr "itanium_class" "stf"))
879 (eq (symbol_ref "bundling_p") (const_int 0)))
881 (define_insn_reservation "2_st" 1
882 (and (and (eq_attr "cpu" "itanium2")
883 (eq_attr "itanium_class" "st"))
884 (eq (symbol_ref "bundling_p") (const_int 0)))
886 (define_insn_reservation "2_syst_m0" 0
887 (and (and (eq_attr "cpu" "itanium2")
888 (eq_attr "itanium_class" "syst_m0"))
889 (eq (symbol_ref "bundling_p") (const_int 0)))
891 (define_insn_reservation "2_syst_m" 0
892 (and (and (eq_attr "cpu" "itanium2")
893 (eq_attr "itanium_class" "syst_m"))
894 (eq (symbol_ref "bundling_p") (const_int 0)))
897 (define_insn_reservation "2_tbit" 1
898 (and (and (eq_attr "cpu" "itanium2")
899 (eq_attr "itanium_class" "tbit"))
900 (eq (symbol_ref "bundling_p") (const_int 0)))
903 ;; There is only ony insn `mov ar.pfs =' for toar_i:
904 (define_insn_reservation "2_toar_i" 0
905 (and (and (eq_attr "cpu" "itanium2")
906 (eq_attr "itanium_class" "toar_i"))
907 (eq (symbol_ref "bundling_p") (const_int 0)))
909 ;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m:
911 (define_insn_reservation "2_toar_m" 5
912 (and (and (eq_attr "cpu" "itanium2")
913 (eq_attr "itanium_class" "toar_m"))
914 (eq (symbol_ref "bundling_p") (const_int 0)))
917 (define_insn_reservation "2_tobr" 1
918 (and (and (eq_attr "cpu" "itanium2")
919 (eq_attr "itanium_class" "tobr"))
920 (eq (symbol_ref "bundling_p") (const_int 0)))
922 (define_insn_reservation "2_tofr" 5
923 (and (and (eq_attr "cpu" "itanium2")
924 (eq_attr "itanium_class" "tofr"))
925 (eq (symbol_ref "bundling_p") (const_int 0)))
928 (define_insn_reservation "2_topr" 1
929 (and (and (eq_attr "cpu" "itanium2")
930 (eq_attr "itanium_class" "topr"))
931 (eq (symbol_ref "bundling_p") (const_int 0)))
934 (define_insn_reservation "2_xmpy" 4
935 (and (and (eq_attr "cpu" "itanium2")
936 (eq_attr "itanium_class" "xmpy"))
937 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F")
939 (define_insn_reservation "2_xtd" 1
940 (and (and (eq_attr "cpu" "itanium2")
941 (eq_attr "itanium_class" "xtd"))
942 (eq (symbol_ref "bundling_p") (const_int 0))) "2_I")
944 (define_insn_reservation "2_chk_s_i" 0
945 (and (and (eq_attr "cpu" "itanium2")
946 (eq_attr "itanium_class" "chk_s_i"))
947 (eq (symbol_ref "bundling_p") (const_int 0)))
949 (define_insn_reservation "2_chk_s_f" 0
950 (and (and (eq_attr "cpu" "itanium2")
951 (eq_attr "itanium_class" "chk_s_f"))
952 (eq (symbol_ref "bundling_p") (const_int 0)))
954 (define_insn_reservation "2_chk_a" 0
955 (and (and (eq_attr "cpu" "itanium2")
956 (eq_attr "itanium_class" "chk_a"))
957 (eq (symbol_ref "bundling_p") (const_int 0)))
960 (define_insn_reservation "2_lfetch" 0
961 (and (and (eq_attr "cpu" "itanium2")
962 (eq_attr "itanium_class" "lfetch"))
963 (eq (symbol_ref "bundling_p") (const_int 0)))
966 (define_insn_reservation "2_nop_m" 0
967 (and (and (eq_attr "cpu" "itanium2")
968 (eq_attr "itanium_class" "nop_m"))
969 (eq (symbol_ref "bundling_p") (const_int 0))) "2_M0")
970 (define_insn_reservation "2_nop_b" 0
971 (and (and (eq_attr "cpu" "itanium2")
972 (eq_attr "itanium_class" "nop_b"))
973 (eq (symbol_ref "bundling_p") (const_int 0))) "2_NB")
974 (define_insn_reservation "2_nop_i" 0
975 (and (and (eq_attr "cpu" "itanium2")
976 (eq_attr "itanium_class" "nop_i"))
977 (eq (symbol_ref "bundling_p") (const_int 0))) "2_I0")
978 (define_insn_reservation "2_nop_f" 0
979 (and (and (eq_attr "cpu" "itanium2")
980 (eq_attr "itanium_class" "nop_f"))
981 (eq (symbol_ref "bundling_p") (const_int 0))) "2_F0")
982 (define_insn_reservation "2_nop_x" 0
983 (and (and (eq_attr "cpu" "itanium2")
984 (eq_attr "itanium_class" "nop_x"))
985 (eq (symbol_ref "bundling_p") (const_int 0))) "2_L0")
987 (define_insn_reservation "2_unknown" 1
988 (and (and (eq_attr "cpu" "itanium2")
989 (eq_attr "itanium_class" "unknown"))
990 (eq (symbol_ref "bundling_p") (const_int 0))) "2_empty")
992 (define_insn_reservation "2_nop" 0
993 (and (and (eq_attr "cpu" "itanium2")
994 (eq_attr "itanium_class" "nop"))
995 (eq (symbol_ref "bundling_p") (const_int 0)))
996 "2_M0|2_NB|2_I0|2_F0")
998 (define_insn_reservation "2_ignore" 0
999 (and (and (eq_attr "cpu" "itanium2")
1000 (eq_attr "itanium_class" "ignore"))
1001 (eq (symbol_ref "bundling_p") (const_int 0))) "nothing")
1003 (define_cpu_unit "2_m_cont_only, 2_b_cont_only" "two")
1004 (define_cpu_unit "2_mi_cont_only, 2_mm_cont_only, 2_mf_cont_only" "two")
1005 (define_cpu_unit "2_mb_cont_only, 2_bb_cont_only" "two")
1007 (final_presence_set "2_m_cont_only" "2_m_cont")
1008 (exclusion_set "2_m_cont_only"
1009 "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\
1010 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.")
1012 (final_presence_set "2_b_cont_only" "2_b_cont")
1013 (exclusion_set "2_b_cont_only" "2_0bb.b")
1015 (final_presence_set "2_mi_cont_only" "2_mi_cont")
1016 (exclusion_set "2_mi_cont_only" "2_0mii., 2_0mib.")
1018 (final_presence_set "2_mm_cont_only" "2_mm_cont")
1019 (exclusion_set "2_mm_cont_only" "2_0mmi., 2_0mmf., 2_0mmb.")
1021 (final_presence_set "2_mf_cont_only" "2_mf_cont")
1022 (exclusion_set "2_mf_cont_only" "2_0mfi., 2_0mfb.")
1024 (final_presence_set "2_mb_cont_only" "2_mb_cont")
1025 (exclusion_set "2_mb_cont_only" "2_0mbb.")
1027 (final_presence_set "2_bb_cont_only" "2_bb_cont")
1028 (exclusion_set "2_bb_cont_only" "2_0bbb.")
1030 (define_insn_reservation "2_pre_cycle" 0
1031 (and (and (eq_attr "cpu" "itanium2")
1032 (eq_attr "itanium_class" "pre_cycle"))
1033 (eq (symbol_ref "bundling_p") (const_int 0)))
1036 ;;(define_insn_reservation "2_pre_cycle" 0
1037 ;; (and (and (eq_attr "cpu" "itanium2")
1038 ;; (eq_attr "itanium_class" "pre_cycle"))
1039 ;; (eq (symbol_ref "bundling_p") (const_int 0)))
1040 ;; "(2_0m_bs, 2_m_cont) \
1041 ;; | (2_0mi_bs, (2_mi_cont|nothing)) \
1042 ;; | (2_0mm_bs, 2_mm_cont) \
1043 ;; | (2_0mf_bs, (2_mf_cont|nothing)) \
1044 ;; | (2_0b_bs, (2_b_cont|nothing)) \
1045 ;; | (2_0bb_bs, (2_bb_cont|nothing)) \
1046 ;; | (2_0mb_bs, (2_mb_cont|nothing)) \
1047 ;; | (2_1m_bs, 2_m_cont) \
1048 ;; | (2_1mi_bs, (2_mi_cont|nothing)) \
1049 ;; | (2_1mm_bs, 2_mm_cont) \
1050 ;; | (2_1mf_bs, (2_mf_cont|nothing)) \
1051 ;; | (2_1b_bs, (2_b_cont|nothing)) \
1052 ;; | (2_1bb_bs, (2_bb_cont|nothing)) \
1053 ;; | (2_1mb_bs, (2_mb_cont|nothing)) \
1054 ;; | (2_m_cont_only, (2_m_cont|nothing)) \
1055 ;; | (2_b_cont_only, (2_b_cont|nothing)) \
1056 ;; | (2_mi_cont_only, (2_mi_cont|nothing)) \
1057 ;; | (2_mm_cont_only, (2_mm_cont|nothing)) \
1058 ;; | (2_mf_cont_only, (2_mf_cont|nothing)) \
1059 ;; | (2_mb_cont_only, (2_mb_cont|nothing)) \
1060 ;; | (2_bb_cont_only, (2_bb_cont|nothing)) \
1061 ;; | (2_m_stop, (2_0mmi_cont|nothing)) \
1062 ;; | (2_mi_stop, (2_0mii_cont|nothing))")
1066 (define_bypass 1 "2_fcmp" "2_br,2_scall")
1067 (define_bypass 0 "2_icmp" "2_br,2_scall")
1068 (define_bypass 0 "2_tbit" "2_br,2_scall")
1069 (define_bypass 2 "2_ld" "2_ld" "ia64_ld_address_bypass_p")
1070 (define_bypass 2 "2_ld" "2_st" "ia64_st_address_bypass_p")
1071 (define_bypass 2 "2_ld,2_ldc" "2_mmalua,2_mmmul,2_mmshf")
1072 (define_bypass 3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf")
1073 (define_bypass 3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf")
1074 (define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld,2_ldc")
1075 (define_bypass 6 "2_tofr" "2_frfr,2_stf")
1076 (define_bypass 7 "2_fmac" "2_frfr,2_stf")
1078 ;; We don't use here fcmp because scall may be predicated.
1079 (define_bypass 0 "2_fcvtfx,2_fld,2_flda,2_fldc,2_fmac,2_fmisc,2_frar_i,2_frar_m,\
1080 2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_ldc,2_long_i,\
1081 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,\
1085 (define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,2_flda,2_fldc,\
1086 2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\
1087 2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_ldc,2_chk_s_i,2_chk_s_f,2_chk_a,2_long_i,\
1088 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\
1089 2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\
1090 2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\
1091 2_topr,2_xmpy,2_xtd,2_lfetch" "2_ignore")
1097 (define_automaton "twob")
1099 ;; Pseudo units for quicker searching for position in two packet window. */
1100 (define_query_cpu_unit "2_1,2_2,2_3,2_4,2_5,2_6" "twob")
1102 ;; All possible combinations of bundles/syllables
1104 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
1105 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" "twob")
1107 "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\
1108 2b_0mi.b, 2b_0mm.b, 2b_0mf.b" "twob")
1109 (define_query_cpu_unit
1110 "2b_0mii., 2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\
1111 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx." "twob")
1114 "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\
1115 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" "twob")
1117 "2b_1mi.i, 2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\
1118 2b_1mi.b, 2b_1mm.b, 2b_1mf.b" "twob")
1119 (define_query_cpu_unit
1120 "2b_1mii., 2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\
1121 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx." "twob")
1124 (exclusion_set "2b_0m.ii"
1125 "2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
1126 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
1127 (exclusion_set "2b_0m.mi"
1128 "2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib,\
1129 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
1130 (exclusion_set "2b_0m.fi"
1131 "2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
1132 (exclusion_set "2b_0m.mf"
1133 "2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
1134 (exclusion_set "2b_0b.bb" "2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
1135 (exclusion_set "2b_0m.bb" "2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
1136 (exclusion_set "2b_0m.ib" "2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
1137 (exclusion_set "2b_0m.mb" "2b_0m.fb, 2b_0m.lx")
1138 (exclusion_set "2b_0m.fb" "2b_0m.lx")
1141 (exclusion_set "2b_0mi.i"
1142 "2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\
1143 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
1144 (exclusion_set "2b_0mm.i"
1145 "2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\
1146 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
1147 (exclusion_set "2b_0mf.i"
1148 "2b_0mm.f, 2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
1149 (exclusion_set "2b_0mm.f"
1150 "2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
1151 (exclusion_set "2b_0bb.b" "2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
1152 (exclusion_set "2b_0mb.b" "2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
1153 (exclusion_set "2b_0mi.b" "2b_0mm.b, 2b_0mf.b, 2b_0mlx.")
1154 (exclusion_set "2b_0mm.b" "2b_0mf.b, 2b_0mlx.")
1155 (exclusion_set "2b_0mf.b" "2b_0mlx.")
1158 (exclusion_set "2b_0mii."
1159 "2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\
1160 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
1161 (exclusion_set "2b_0mmi."
1162 "2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\
1163 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
1164 (exclusion_set "2b_0mfi."
1165 "2b_0mmf., 2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
1166 (exclusion_set "2b_0mmf."
1167 "2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
1168 (exclusion_set "2b_0bbb." "2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
1169 (exclusion_set "2b_0mbb." "2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.")
1170 (exclusion_set "2b_0mib." "2b_0mmb., 2b_0mfb., 2b_0mlx.")
1171 (exclusion_set "2b_0mmb." "2b_0mfb., 2b_0mlx.")
1172 (exclusion_set "2b_0mfb." "2b_0mlx.")
1175 (exclusion_set "2b_1m.ii"
1176 "2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\
1177 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
1178 (exclusion_set "2b_1m.mi"
1179 "2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib,\
1180 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
1181 (exclusion_set "2b_1m.fi"
1182 "2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
1183 (exclusion_set "2b_1m.mf"
1184 "2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
1185 (exclusion_set "2b_1b.bb" "2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
1186 (exclusion_set "2b_1m.bb" "2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
1187 (exclusion_set "2b_1m.ib" "2b_1m.mb, 2b_1m.fb, 2b_1m.lx")
1188 (exclusion_set "2b_1m.mb" "2b_1m.fb, 2b_1m.lx")
1189 (exclusion_set "2b_1m.fb" "2b_1m.lx")
1192 (exclusion_set "2b_1mi.i"
1193 "2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\
1194 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
1195 (exclusion_set "2b_1mm.i"
1196 "2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\
1197 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
1198 (exclusion_set "2b_1mf.i"
1199 "2b_1mm.f, 2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
1200 (exclusion_set "2b_1mm.f"
1201 "2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
1202 (exclusion_set "2b_1bb.b" "2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
1203 (exclusion_set "2b_1mb.b" "2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
1204 (exclusion_set "2b_1mi.b" "2b_1mm.b, 2b_1mf.b, 2b_1mlx.")
1205 (exclusion_set "2b_1mm.b" "2b_1mf.b, 2b_1mlx.")
1206 (exclusion_set "2b_1mf.b" "2b_1mlx.")
1209 (exclusion_set "2b_1mii."
1210 "2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\
1211 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
1212 (exclusion_set "2b_1mmi."
1213 "2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\
1214 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
1215 (exclusion_set "2b_1mfi."
1216 "2b_1mmf., 2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
1217 (exclusion_set "2b_1mmf."
1218 "2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
1219 (exclusion_set "2b_1bbb." "2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
1220 (exclusion_set "2b_1mbb." "2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.")
1221 (exclusion_set "2b_1mib." "2b_1mmb., 2b_1mfb., 2b_1mlx.")
1222 (exclusion_set "2b_1mmb." "2b_1mfb., 2b_1mlx.")
1223 (exclusion_set "2b_1mfb." "2b_1mlx.")
1225 (final_presence_set "2b_0mi.i" "2b_0m.ii")
1226 (final_presence_set "2b_0mii." "2b_0mi.i")
1227 (final_presence_set "2b_1mi.i" "2b_1m.ii")
1228 (final_presence_set "2b_1mii." "2b_1mi.i")
1230 (final_presence_set "2b_0mm.i" "2b_0m.mi")
1231 (final_presence_set "2b_0mmi." "2b_0mm.i")
1232 (final_presence_set "2b_1mm.i" "2b_1m.mi")
1233 (final_presence_set "2b_1mmi." "2b_1mm.i")
1235 (final_presence_set "2b_0mf.i" "2b_0m.fi")
1236 (final_presence_set "2b_0mfi." "2b_0mf.i")
1237 (final_presence_set "2b_1mf.i" "2b_1m.fi")
1238 (final_presence_set "2b_1mfi." "2b_1mf.i")
1240 (final_presence_set "2b_0mm.f" "2b_0m.mf")
1241 (final_presence_set "2b_0mmf." "2b_0mm.f")
1242 (final_presence_set "2b_1mm.f" "2b_1m.mf")
1243 (final_presence_set "2b_1mmf." "2b_1mm.f")
1245 (final_presence_set "2b_0bb.b" "2b_0b.bb")
1246 (final_presence_set "2b_0bbb." "2b_0bb.b")
1247 (final_presence_set "2b_1bb.b" "2b_1b.bb")
1248 (final_presence_set "2b_1bbb." "2b_1bb.b")
1250 (final_presence_set "2b_0mb.b" "2b_0m.bb")
1251 (final_presence_set "2b_0mbb." "2b_0mb.b")
1252 (final_presence_set "2b_1mb.b" "2b_1m.bb")
1253 (final_presence_set "2b_1mbb." "2b_1mb.b")
1255 (final_presence_set "2b_0mi.b" "2b_0m.ib")
1256 (final_presence_set "2b_0mib." "2b_0mi.b")
1257 (final_presence_set "2b_1mi.b" "2b_1m.ib")
1258 (final_presence_set "2b_1mib." "2b_1mi.b")
1260 (final_presence_set "2b_0mm.b" "2b_0m.mb")
1261 (final_presence_set "2b_0mmb." "2b_0mm.b")
1262 (final_presence_set "2b_1mm.b" "2b_1m.mb")
1263 (final_presence_set "2b_1mmb." "2b_1mm.b")
1265 (final_presence_set "2b_0mf.b" "2b_0m.fb")
1266 (final_presence_set "2b_0mfb." "2b_0mf.b")
1267 (final_presence_set "2b_1mf.b" "2b_1m.fb")
1268 (final_presence_set "2b_1mfb." "2b_1mf.b")
1270 (final_presence_set "2b_0mlx." "2b_0m.lx")
1271 (final_presence_set "2b_1mlx." "2b_1m.lx")
1273 ;; See the corresponding comment in non-bundling section above.
1276 "2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.")
1277 (final_presence_set "2b_1b.bb" "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mlx.")
1279 "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1m.bb,2b_1m.ib,2b_1m.mb,2b_1m.fb"
1280 "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.")
1282 ;; Ports/units (nb means nop.b insn issued into given port):
1284 "2b_um0, 2b_um1, 2b_um2, 2b_um3, 2b_ui0, 2b_ui1, 2b_uf0, 2b_uf1,\
1285 2b_ub0, 2b_ub1, 2b_ub2, 2b_unb0, 2b_unb1, 2b_unb2" "twob")
1287 (exclusion_set "2b_ub0" "2b_unb0")
1288 (exclusion_set "2b_ub1" "2b_unb1")
1289 (exclusion_set "2b_ub2" "2b_unb2")
1291 ;; The following rules are used to decrease number of alternatives.
1292 ;; They are consequences of Itanium2 microarchitecture. They also
1293 ;; describe the following rules mentioned in Itanium2
1294 ;; microarchitecture: rules mentioned in Itanium2 microarchitecture:
1295 ;; o "BBB/MBB: Always splits issue after either of these bundles".
1296 ;; o "MIB BBB: Split issue after the first bundle in this pair".
1298 "2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb."
1299 "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1b.bb,2b_1m.bb,\
1300 2b_1m.ib,2b_1m.mb,2b_1m.fb,2b_1m.lx")
1301 (exclusion_set "2b_0m.ib,2b_0mi.b,2b_0mib." "2b_1b.bb")
1303 ;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the
1304 ;;; B-slot contains a nop.b or a brp instruction".
1305 ;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or
1306 ;;; nop.b, otherwise it disperses to B2".
1308 "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\
1309 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx"
1310 "2b_0mib. 2b_ub2, 2b_0mfb. 2b_ub2, 2b_0mmb. 2b_ub2")
1312 ;; This is necessary to start new processor cycle when we meet stop bit.
1313 (define_cpu_unit "2b_stop" "twob")
1315 "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\
1316 2b_0m.fi,2b_0mf.i,2b_0mfi.,\
1317 2b_0m.mf,2b_0mm.f,2b_0mmf.,2b_0b.bb,2b_0bb.b,2b_0bbb.,\
1318 2b_0m.bb,2b_0mb.b,2b_0mbb.,\
1319 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\
1320 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \
1321 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\
1322 2b_1m.fi,2b_1mf.i,2b_1mfi.,\
1323 2b_1m.mf,2b_1mm.f,2b_1mmf.,2b_1b.bb,2b_1bb.b,2b_1bbb.,\
1324 2b_1m.bb,2b_1mb.b,2b_1mbb.,\
1325 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\
1326 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx."
1329 ;; The issue logic can reorder M slot insns between different subtypes
1330 ;; but cannot reorder insn within the same subtypes. The following
1331 ;; constraint is enough to describe this.
1332 (final_presence_set "2b_um1" "2b_um0")
1333 (final_presence_set "2b_um3" "2b_um2")
1335 ;; The insn in the 1st I slot of the two bundle issue group will issue
1336 ;; to I0. The second I slot insn will issue to I1.
1337 (final_presence_set "2b_ui1" "2b_ui0")
1339 ;; For exceptions of I insns:
1340 (define_cpu_unit "2b_only_ui0" "twob")
1341 (final_absence_set "2b_only_ui0" "2b_ui1")
1345 (define_reservation "2b_M"
1346 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
1347 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
1348 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
1349 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
1350 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
1351 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
1352 +(2b_um0|2b_um1|2b_um2|2b_um3)")
1354 (define_reservation "2b_M_only_um0"
1355 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
1356 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
1357 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
1358 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
1359 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
1360 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
1363 (define_reservation "2b_M_only_um2"
1364 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
1365 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
1366 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
1367 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
1368 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
1369 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
1372 (define_reservation "2b_M_only_um01"
1373 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
1374 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
1375 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
1376 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
1377 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
1378 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
1381 (define_reservation "2b_M_only_um23"
1382 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
1383 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\
1384 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\
1385 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\
1386 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\
1387 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\
1390 ;; I instruction is dispersed to the lowest numbered I unit
1391 ;; not already in use. Remember about possible splitting.
1392 (define_reservation "2b_I"
1393 "2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\
1394 |2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\
1395 |(2b_1mi.i+2_5|2b_1mi.b+2_5)+(2b_ui0|2b_ui1)\
1396 |(2b_1mii.|2b_1mmi.|2b_1mfi.)+2_6+(2b_ui0|2b_ui1)")
1398 ;; "An F slot in the 1st bundle disperses to F0".
1399 ;; "An F slot in the 2st bundle disperses to F1".
1400 (define_reservation "2b_F"
1401 "2b_0mf.i+2_2+2b_uf0|2b_0mmf.+2_3+2b_uf0|2b_0mf.b+2_2+2b_uf0\
1402 |2b_1mf.i+2_5+2b_uf1|2b_1mmf.+2_6+2b_uf1|2b_1mf.b+2_5+2b_uf1")
1404 ;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
1405 ;;; unit. That is, a B slot in 1st position is dispersed to B0. In the
1406 ;;; 2nd position it is dispersed to B2".
1407 (define_reservation "2b_NB"
1408 "2b_0b.bb+2_1+2b_unb0|2b_0bb.b+2_2+2b_unb1|2b_0bbb.+2_3+2b_unb2\
1409 |2b_0mb.b+2_2+2b_unb1|2b_0mbb.+2_3+2b_unb2\
1410 |2b_0mib.+2_3+2b_unb0|2b_0mmb.+2_3+2b_unb0|2b_0mfb.+2_3+2b_unb0\
1411 |2b_1b.bb+2_4+2b_unb0|2b_1bb.b+2_5+2b_unb1\
1412 |2b_1bbb.+2_6+2b_unb2|2b_1mb.b+2_5+2b_unb1|2b_1mbb.+2_6+2b_unb2\
1413 |2b_1mib.+2_6+2b_unb0|2b_1mmb.+2_6+2b_unb0|2b_1mfb.+2_6+2b_unb0")
1415 (define_reservation "2b_B"
1416 "2b_0b.bb+2_1+2b_ub0|2b_0bb.b+2_2+2b_ub1|2b_0bbb.+2_3+2b_ub2\
1417 |2b_0mb.b+2_2+2b_ub1|2b_0mbb.+2_3+2b_ub2|2b_0mib.+2_3+2b_ub2\
1418 |2b_0mfb.+2_3+2b_ub2|2b_1b.bb+2_4+2b_ub0|2b_1bb.b+2_5+2b_ub1\
1419 |2b_1bbb.+2_6+2b_ub2|2b_1mb.b+2_5+2b_ub1\
1420 |2b_1mib.+2_6+2b_ub2|2b_1mmb.+2_6+2b_ub2|2b_1mfb.+2_6+2b_ub2")
1422 ;; For the MLI template, the I slot insn is always assigned to port I0
1423 ;; if it is in the first bundle or it is assigned to port I1 if it is in
1424 ;; the second bundle.
1425 (define_reservation "2b_L"
1426 "2b_0mlx.+2_3+2b_ui0+2b_uf0|2b_1mlx.+2_6+2b_ui1+2b_uf1")
1428 ;; Should we describe that A insn in I slot can be issued into M
1429 ;; ports? I think it is not necessary because of multipass
1430 ;; scheduling. For example, the multipass scheduling could use
1431 ;; MMI-MMI instead of MII-MII where the two last I slots contain A
1432 ;; insns (even if the case is complicated by use-def conflicts).
1434 ;; In any case we could describe it as
1435 ;; (define_cpu_unit "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres"
1437 ;; (final_presence_set "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres"
1439 ;; (define_reservation "b_A"
1441 ;; |(2b_1mi.i+2_5|2b_1mii.+2_6|2b_1mmi.+2_6|2b_1mfi.+2_6|2b_1mi.b+2_5)\
1442 ;; +(2b_um0|2b_um1|2b_um2|2b_um3)\
1443 ;; +(2b_ui1_0pres|2b_ui1_1pres|2b_ui1_2pres|2b_ui1_3pres)")
1445 (define_reservation "2b_A" "2b_M|2b_I")
1447 ;; We assume that there is no insn issued on the same cycle as the
1449 (define_cpu_unit "2b_empty" "twob")
1450 (exclusion_set "2b_empty"
1451 "2b_0m.ii,2b_0m.mi,2b_0m.fi,2b_0m.mf,2b_0b.bb,2b_0m.bb,\
1452 2b_0m.ib,2b_0m.mb,2b_0m.fb,2b_0m.lx,2b_0mm.i")
1455 "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs"
1458 "2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs"
1461 (define_cpu_unit "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont, 2b_mb_cont,\
1462 2b_b_cont, 2b_bb_cont" "twob")
1464 ;; For stop in the middle of the bundles.
1465 (define_cpu_unit "2b_m_stop, 2b_m0_stop, 2b_m1_stop, 2b_0mmi_cont" "twob")
1466 (define_cpu_unit "2b_mi_stop, 2b_mi0_stop, 2b_mi1_stop, 2b_0mii_cont" "twob")
1468 (final_presence_set "2b_0m_bs"
1469 "2b_0m.ii, 2b_0m.mi, 2b_0m.mf, 2b_0m.fi, 2b_0m.bb,\
1470 2b_0m.ib, 2b_0m.fb, 2b_0m.mb, 2b_0m.lx")
1471 (final_presence_set "2b_1m_bs"
1472 "2b_1m.ii, 2b_1m.mi, 2b_1m.mf, 2b_1m.fi, 2b_1m.bb,\
1473 2b_1m.ib, 2b_1m.fb, 2b_1m.mb, 2b_1m.lx")
1474 (final_presence_set "2b_0mi_bs" "2b_0mi.i, 2b_0mi.i")
1475 (final_presence_set "2b_1mi_bs" "2b_1mi.i, 2b_1mi.i")
1476 (final_presence_set "2b_0mm_bs" "2b_0mm.i, 2b_0mm.f, 2b_0mm.b")
1477 (final_presence_set "2b_1mm_bs" "2b_1mm.i, 2b_1mm.f, 2b_1mm.b")
1478 (final_presence_set "2b_0mf_bs" "2b_0mf.i, 2b_0mf.b")
1479 (final_presence_set "2b_1mf_bs" "2b_1mf.i, 2b_1mf.b")
1480 (final_presence_set "2b_0b_bs" "2b_0b.bb")
1481 (final_presence_set "2b_1b_bs" "2b_1b.bb")
1482 (final_presence_set "2b_0bb_bs" "2b_0bb.b")
1483 (final_presence_set "2b_1bb_bs" "2b_1bb.b")
1484 (final_presence_set "2b_0mb_bs" "2b_0mb.b")
1485 (final_presence_set "2b_1mb_bs" "2b_1mb.b")
1487 (exclusion_set "2b_0m_bs"
1488 "2b_0mi.i, 2b_0mm.i, 2b_0mm.f, 2b_0mf.i, 2b_0mb.b,\
1489 2b_0mi.b, 2b_0mf.b, 2b_0mm.b, 2b_0mlx., 2b_m0_stop")
1490 (exclusion_set "2b_1m_bs"
1491 "2b_1mi.i, 2b_1mm.i, 2b_1mm.f, 2b_1mf.i, 2b_1mb.b,\
1492 2b_1mi.b, 2b_1mf.b, 2b_1mm.b, 2b_1mlx., 2b_m1_stop")
1493 (exclusion_set "2b_0mi_bs" "2b_0mii., 2b_0mib., 2b_mi0_stop")
1494 (exclusion_set "2b_1mi_bs" "2b_1mii., 2b_1mib., 2b_mi1_stop")
1495 (exclusion_set "2b_0mm_bs" "2b_0mmi., 2b_0mmf., 2b_0mmb.")
1496 (exclusion_set "2b_1mm_bs" "2b_1mmi., 2b_1mmf., 2b_1mmb.")
1497 (exclusion_set "2b_0mf_bs" "2b_0mfi., 2b_0mfb.")
1498 (exclusion_set "2b_1mf_bs" "2b_1mfi., 2b_1mfb.")
1499 (exclusion_set "2b_0b_bs" "2b_0bb.b")
1500 (exclusion_set "2b_1b_bs" "2b_1bb.b")
1501 (exclusion_set "2b_0bb_bs" "2b_0bbb.")
1502 (exclusion_set "2b_1bb_bs" "2b_1bbb.")
1503 (exclusion_set "2b_0mb_bs" "2b_0mbb.")
1504 (exclusion_set "2b_1mb_bs" "2b_1mbb.")
1507 "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs,
1508 2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs"
1512 "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0mb.b,\
1513 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx."
1515 (final_presence_set "2b_0mii., 2b_0mib." "2b_mi_cont")
1516 (final_presence_set "2b_0mmi., 2b_0mmf., 2b_0mmb." "2b_mm_cont")
1517 (final_presence_set "2b_0mfi., 2b_0mfb." "2b_mf_cont")
1518 (final_presence_set "2b_0bb.b" "2b_b_cont")
1519 (final_presence_set "2b_0bbb." "2b_bb_cont")
1520 (final_presence_set "2b_0mbb." "2b_mb_cont")
1523 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
1524 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx"
1525 "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont,\
1526 2b_mb_cont, 2b_b_cont, 2b_bb_cont")
1528 (exclusion_set "2b_empty"
1529 "2b_m_cont,2b_mi_cont,2b_mm_cont,2b_mf_cont,\
1530 2b_mb_cont,2b_b_cont,2b_bb_cont")
1533 (final_presence_set "2b_m0_stop" "2b_0m.mi")
1534 (final_presence_set "2b_0mm.i" "2b_0mmi_cont")
1535 (exclusion_set "2b_0mmi_cont"
1536 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
1537 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
1538 (exclusion_set "2b_m0_stop" "2b_0mm.i")
1539 (final_presence_set "2b_m1_stop" "2b_1m.mi")
1540 (exclusion_set "2b_m1_stop" "2b_1mm.i")
1541 (final_presence_set "2b_m_stop" "2b_m0_stop, 2b_m1_stop")
1544 (final_presence_set "2b_mi0_stop" "2b_0mi.i")
1545 (final_presence_set "2b_0mii." "2b_0mii_cont")
1546 (exclusion_set "2b_0mii_cont"
1547 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\
1548 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx")
1549 (exclusion_set "2b_mi0_stop" "2b_0mii.")
1550 (final_presence_set "2b_mi1_stop" "2b_1mi.i")
1551 (exclusion_set "2b_mi1_stop" "2b_1mii.")
1552 (final_presence_set "2b_mi_stop" "2b_mi0_stop, 2b_mi1_stop")
1555 "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\
1556 2b_0m.fi,2b_0mf.i,2b_0mfi.,2b_0m.mf,2b_0mm.f,2b_0mmf.,\
1557 2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb.,\
1558 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\
1559 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \
1560 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\
1561 2b_1m.fi,2b_1mf.i,2b_1mfi.,2b_1m.mf,2b_1mm.f,2b_1mmf.,\
1562 2b_1b.bb,2b_1bb.b,2b_1bbb.,2b_1m.bb,2b_1mb.b,2b_1mbb.,\
1563 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\
1564 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx."
1565 "2b_m0_stop,2b_m1_stop,2b_mi0_stop,2b_mi1_stop")
1567 (define_insn_reservation "2b_stop_bit" 0
1568 (and (and (eq_attr "cpu" "itanium2")
1569 (eq_attr "itanium_class" "stop_bit"))
1570 (ne (symbol_ref "bundling_p") (const_int 0)))
1571 "2b_stop|2b_m0_stop|2b_m1_stop|2b_mi0_stop|2b_mi1_stop")
1572 (define_insn_reservation "2b_br" 0
1573 (and (and (eq_attr "cpu" "itanium2")
1574 (eq_attr "itanium_class" "br"))
1575 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_B")
1576 (define_insn_reservation "2b_scall" 0
1577 (and (and (eq_attr "cpu" "itanium2")
1578 (eq_attr "itanium_class" "scall"))
1579 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_B")
1580 (define_insn_reservation "2b_fcmp" 2
1581 (and (and (eq_attr "cpu" "itanium2")
1582 (eq_attr "itanium_class" "fcmp"))
1583 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
1584 (define_insn_reservation "2b_fcvtfx" 4
1585 (and (and (eq_attr "cpu" "itanium2")
1586 (eq_attr "itanium_class" "fcvtfx"))
1587 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
1588 (define_insn_reservation "2b_fld" 6
1589 (and (and (and (and (eq_attr "cpu" "itanium2")
1590 (eq_attr "itanium_class" "fld"))
1591 (eq_attr "data_speculative" "no"))
1592 (eq_attr "check_load" "no"))
1593 (ne (symbol_ref "bundling_p") (const_int 0)))
1595 (define_insn_reservation "2b_flda" 6
1596 (and (and (and (eq_attr "cpu" "itanium2")
1597 (eq_attr "itanium_class" "fld"))
1598 (eq_attr "data_speculative" "yes"))
1599 (ne (symbol_ref "bundling_p") (const_int 0)))
1601 (define_insn_reservation "2b_fldc" 0
1602 (and (and (and (eq_attr "cpu" "itanium2")
1603 (eq_attr "itanium_class" "fld"))
1604 (eq_attr "check_load" "yes"))
1605 (ne (symbol_ref "bundling_p") (const_int 0)))
1608 (define_insn_reservation "2b_fldp" 6
1609 (and (and (and (eq_attr "cpu" "itanium2")
1610 (eq_attr "itanium_class" "fldp"))
1611 (eq_attr "check_load" "no"))
1612 (ne (symbol_ref "bundling_p") (const_int 0)))
1614 (define_insn_reservation "2b_fldpc" 0
1615 (and (and (and (eq_attr "cpu" "itanium2")
1616 (eq_attr "itanium_class" "fldp"))
1617 (eq_attr "check_load" "yes"))
1618 (ne (symbol_ref "bundling_p") (const_int 0)))
1621 (define_insn_reservation "2b_fmac" 4
1622 (and (and (eq_attr "cpu" "itanium2")
1623 (eq_attr "itanium_class" "fmac"))
1624 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
1625 (define_insn_reservation "2b_fmisc" 4
1626 (and (and (eq_attr "cpu" "itanium2")
1627 (eq_attr "itanium_class" "fmisc"))
1628 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
1631 (define_insn_reservation "2b_frar_i" 13
1632 (and (and (eq_attr "cpu" "itanium2")
1633 (eq_attr "itanium_class" "frar_i"))
1634 (ne (symbol_ref "bundling_p") (const_int 0)))
1637 (define_insn_reservation "2b_frar_m" 6
1638 (and (and (eq_attr "cpu" "itanium2")
1639 (eq_attr "itanium_class" "frar_m"))
1640 (ne (symbol_ref "bundling_p") (const_int 0)))
1642 (define_insn_reservation "2b_frbr" 2
1643 (and (and (eq_attr "cpu" "itanium2")
1644 (eq_attr "itanium_class" "frbr"))
1645 (ne (symbol_ref "bundling_p") (const_int 0)))
1647 (define_insn_reservation "2b_frfr" 5
1648 (and (and (eq_attr "cpu" "itanium2")
1649 (eq_attr "itanium_class" "frfr"))
1650 (ne (symbol_ref "bundling_p") (const_int 0)))
1652 (define_insn_reservation "2b_frpr" 2
1653 (and (and (eq_attr "cpu" "itanium2")
1654 (eq_attr "itanium_class" "frpr"))
1655 (ne (symbol_ref "bundling_p") (const_int 0)))
1658 (define_insn_reservation "2b_ialu" 1
1659 (and (and (eq_attr "cpu" "itanium2")
1660 (eq_attr "itanium_class" "ialu"))
1661 (ne (symbol_ref "bundling_p") (const_int 0)))
1663 (define_insn_reservation "2b_icmp" 1
1664 (and (and (eq_attr "cpu" "itanium2")
1665 (eq_attr "itanium_class" "icmp"))
1666 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
1667 (define_insn_reservation "2b_ilog" 1
1668 (and (and (eq_attr "cpu" "itanium2")
1669 (eq_attr "itanium_class" "ilog"))
1670 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
1671 (define_insn_reservation "2b_mmalua" 2
1672 (and (and (eq_attr "cpu" "itanium2")
1673 (eq_attr "itanium_class" "mmalua"))
1674 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A")
1676 (define_insn_reservation "2b_ishf" 1
1677 (and (and (eq_attr "cpu" "itanium2")
1678 (eq_attr "itanium_class" "ishf"))
1679 (ne (symbol_ref "bundling_p") (const_int 0)))
1682 (define_insn_reservation "2b_ld" 1
1683 (and (and (and (eq_attr "cpu" "itanium2")
1684 (eq_attr "itanium_class" "ld"))
1685 (eq_attr "check_load" "no"))
1686 (ne (symbol_ref "bundling_p") (const_int 0)))
1688 (define_insn_reservation "2b_ldc" 0
1689 (and (and (and (eq_attr "cpu" "itanium2")
1690 (eq_attr "itanium_class" "ld"))
1691 (eq_attr "check_load" "yes"))
1692 (ne (symbol_ref "bundling_p") (const_int 0)))
1695 (define_insn_reservation "2b_long_i" 1
1696 (and (and (eq_attr "cpu" "itanium2")
1697 (eq_attr "itanium_class" "long_i"))
1698 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_L")
1701 (define_insn_reservation "2b_mmmul" 2
1702 (and (and (eq_attr "cpu" "itanium2")
1703 (eq_attr "itanium_class" "mmmul"))
1704 (ne (symbol_ref "bundling_p") (const_int 0)))
1707 (define_insn_reservation "2b_mmshf" 2
1708 (and (and (eq_attr "cpu" "itanium2")
1709 (eq_attr "itanium_class" "mmshf"))
1710 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I")
1712 (define_insn_reservation "2b_mmshfi" 1
1713 (and (and (eq_attr "cpu" "itanium2")
1714 (eq_attr "itanium_class" "mmshfi"))
1715 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I")
1717 (define_insn_reservation "2b_rse_m" 0
1718 (and (and (eq_attr "cpu" "itanium2")
1719 (eq_attr "itanium_class" "rse_m"))
1720 (ne (symbol_ref "bundling_p") (const_int 0)))
1721 "(2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\
1722 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1+2b_um0")
1723 (define_insn_reservation "2b_sem" 0
1724 (and (and (eq_attr "cpu" "itanium2")
1725 (eq_attr "itanium_class" "sem"))
1726 (ne (symbol_ref "bundling_p") (const_int 0)))
1729 (define_insn_reservation "2b_stf" 1
1730 (and (and (eq_attr "cpu" "itanium2")
1731 (eq_attr "itanium_class" "stf"))
1732 (ne (symbol_ref "bundling_p") (const_int 0)))
1734 (define_insn_reservation "2b_st" 1
1735 (and (and (eq_attr "cpu" "itanium2")
1736 (eq_attr "itanium_class" "st"))
1737 (ne (symbol_ref "bundling_p") (const_int 0)))
1739 (define_insn_reservation "2b_syst_m0" 0
1740 (and (and (eq_attr "cpu" "itanium2")
1741 (eq_attr "itanium_class" "syst_m0"))
1742 (ne (symbol_ref "bundling_p") (const_int 0)))
1744 (define_insn_reservation "2b_syst_m" 0
1745 (and (and (eq_attr "cpu" "itanium2")
1746 (eq_attr "itanium_class" "syst_m"))
1747 (ne (symbol_ref "bundling_p") (const_int 0)))
1750 (define_insn_reservation "2b_tbit" 1
1751 (and (and (eq_attr "cpu" "itanium2")
1752 (eq_attr "itanium_class" "tbit"))
1753 (ne (symbol_ref "bundling_p") (const_int 0)))
1755 (define_insn_reservation "2b_toar_i" 0
1756 (and (and (eq_attr "cpu" "itanium2")
1757 (eq_attr "itanium_class" "toar_i"))
1758 (ne (symbol_ref "bundling_p") (const_int 0)))
1761 (define_insn_reservation "2b_toar_m" 5
1762 (and (and (eq_attr "cpu" "itanium2")
1763 (eq_attr "itanium_class" "toar_m"))
1764 (ne (symbol_ref "bundling_p") (const_int 0)))
1767 (define_insn_reservation "2b_tobr" 1
1768 (and (and (eq_attr "cpu" "itanium2")
1769 (eq_attr "itanium_class" "tobr"))
1770 (ne (symbol_ref "bundling_p") (const_int 0)))
1772 (define_insn_reservation "2b_tofr" 5
1773 (and (and (eq_attr "cpu" "itanium2")
1774 (eq_attr "itanium_class" "tofr"))
1775 (ne (symbol_ref "bundling_p") (const_int 0)))
1778 (define_insn_reservation "2b_topr" 1
1779 (and (and (eq_attr "cpu" "itanium2")
1780 (eq_attr "itanium_class" "topr"))
1781 (ne (symbol_ref "bundling_p") (const_int 0)))
1784 (define_insn_reservation "2b_xmpy" 4
1785 (and (and (eq_attr "cpu" "itanium2")
1786 (eq_attr "itanium_class" "xmpy"))
1787 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
1789 (define_insn_reservation "2b_xtd" 1
1790 (and (and (eq_attr "cpu" "itanium2")
1791 (eq_attr "itanium_class" "xtd"))
1792 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I")
1794 (define_insn_reservation "2b_chk_s_i" 0
1795 (and (and (eq_attr "cpu" "itanium2")
1796 (eq_attr "itanium_class" "chk_s_i"))
1797 (ne (symbol_ref "bundling_p") (const_int 0)))
1798 "2b_I|2b_M_only_um23")
1799 (define_insn_reservation "2b_chk_s_f" 0
1800 (and (and (eq_attr "cpu" "itanium2")
1801 (eq_attr "itanium_class" "chk_s_f"))
1802 (ne (symbol_ref "bundling_p") (const_int 0)))
1804 (define_insn_reservation "2b_chk_a" 0
1805 (and (and (eq_attr "cpu" "itanium2")
1806 (eq_attr "itanium_class" "chk_a"))
1807 (ne (symbol_ref "bundling_p") (const_int 0)))
1810 (define_insn_reservation "2b_lfetch" 0
1811 (and (and (eq_attr "cpu" "itanium2")
1812 (eq_attr "itanium_class" "lfetch"))
1813 (ne (symbol_ref "bundling_p") (const_int 0)))
1815 (define_insn_reservation "2b_nop_m" 0
1816 (and (and (eq_attr "cpu" "itanium2")
1817 (eq_attr "itanium_class" "nop_m"))
1818 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_M")
1819 (define_insn_reservation "2b_nop_b" 0
1820 (and (and (eq_attr "cpu" "itanium2")
1821 (eq_attr "itanium_class" "nop_b"))
1822 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_NB")
1823 (define_insn_reservation "2b_nop_i" 0
1824 (and (and (eq_attr "cpu" "itanium2")
1825 (eq_attr "itanium_class" "nop_i"))
1826 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I")
1827 (define_insn_reservation "2b_nop_f" 0
1828 (and (and (eq_attr "cpu" "itanium2")
1829 (eq_attr "itanium_class" "nop_f"))
1830 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F")
1831 (define_insn_reservation "2b_nop_x" 0
1832 (and (and (eq_attr "cpu" "itanium2")
1833 (eq_attr "itanium_class" "nop_x"))
1834 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_L")
1835 (define_insn_reservation "2b_unknown" 1
1836 (and (and (eq_attr "cpu" "itanium2")
1837 (eq_attr "itanium_class" "unknown"))
1838 (ne (symbol_ref "bundling_p") (const_int 0))) "2b_empty")
1839 (define_insn_reservation "2b_nop" 0
1840 (and (and (eq_attr "cpu" "itanium2")
1841 (eq_attr "itanium_class" "nop"))
1842 (ne (symbol_ref "bundling_p") (const_int 0)))
1843 "2b_M|2b_NB|2b_I|2b_F")
1844 (define_insn_reservation "2b_ignore" 0
1845 (and (and (eq_attr "cpu" "itanium2")
1846 (eq_attr "itanium_class" "ignore"))
1847 (ne (symbol_ref "bundling_p") (const_int 0))) "nothing")
1849 (define_insn_reservation "2b_pre_cycle" 0
1850 (and (and (eq_attr "cpu" "itanium2")
1851 (eq_attr "itanium_class" "pre_cycle"))
1852 (ne (symbol_ref "bundling_p") (const_int 0)))
1853 "(2b_0m_bs, 2b_m_cont) \
1854 | (2b_0mi_bs, 2b_mi_cont) \
1855 | (2b_0mm_bs, 2b_mm_cont) \
1856 | (2b_0mf_bs, 2b_mf_cont) \
1857 | (2b_0b_bs, 2b_b_cont) \
1858 | (2b_0bb_bs, 2b_bb_cont) \
1859 | (2b_0mb_bs, 2b_mb_cont) \
1860 | (2b_1m_bs, 2b_m_cont) \
1861 | (2b_1mi_bs, 2b_mi_cont) \
1862 | (2b_1mm_bs, 2b_mm_cont) \
1863 | (2b_1mf_bs, 2b_mf_cont) \
1864 | (2b_1b_bs, 2b_b_cont) \
1865 | (2b_1bb_bs, 2b_bb_cont) \
1866 | (2b_1mb_bs, 2b_mb_cont) \
1867 | (2b_m_stop, 2b_0mmi_cont) \
1868 | (2b_mi_stop, 2b_0mii_cont)")