1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type {
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
143 MIPS_V2SF_FTYPE_SF_SF,
144 MIPS_INT_FTYPE_V2SF_V2SF,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
146 MIPS_INT_FTYPE_SF_SF,
147 MIPS_INT_FTYPE_DF_DF,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI,
160 MIPS_SI_FTYPE_PTR_SI,
164 MIPS_SI_FTYPE_V2HI_V2HI,
166 MIPS_SI_FTYPE_V4QI_V4QI,
169 MIPS_V2HI_FTYPE_SI_SI,
170 MIPS_V2HI_FTYPE_V2HI,
171 MIPS_V2HI_FTYPE_V2HI_SI,
172 MIPS_V2HI_FTYPE_V2HI_V2HI,
173 MIPS_V2HI_FTYPE_V4QI,
174 MIPS_V2HI_FTYPE_V4QI_V2HI,
176 MIPS_V4QI_FTYPE_V2HI_V2HI,
177 MIPS_V4QI_FTYPE_V4QI_SI,
178 MIPS_V4QI_FTYPE_V4QI_V4QI,
179 MIPS_VOID_FTYPE_SI_SI,
180 MIPS_VOID_FTYPE_V2HI_V2HI,
181 MIPS_VOID_FTYPE_V4QI_V4QI,
187 /* Specifies how a builtin function should be converted into rtl. */
188 enum mips_builtin_type
190 /* The builtin corresponds directly to an .md pattern. The return
191 value is mapped to operand 0 and the arguments are mapped to
192 operands 1 and above. */
195 /* The builtin corresponds directly to an .md pattern. There is no return
196 value and the arguments are mapped to operands 0 and above. */
197 MIPS_BUILTIN_DIRECT_NO_TARGET,
199 /* The builtin corresponds to a comparison instruction followed by
200 a mips_cond_move_tf_ps pattern. The first two arguments are the
201 values to compare and the second two arguments are the vector
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
206 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
207 of this instruction is the result of the comparison, which has mode
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
209 above. The function's return value is an SImode boolean that is
210 true under the following conditions:
212 MIPS_BUILTIN_CMP_ANY: one of the registers is true
213 MIPS_BUILTIN_CMP_ALL: all of the registers are true
214 MIPS_BUILTIN_CMP_LOWER: the first register is true
215 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
216 MIPS_BUILTIN_CMP_ANY,
217 MIPS_BUILTIN_CMP_ALL,
218 MIPS_BUILTIN_CMP_UPPER,
219 MIPS_BUILTIN_CMP_LOWER,
221 /* As above, but the instruction only sets a single $fcc register. */
222 MIPS_BUILTIN_CMP_SINGLE,
224 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
225 MIPS_BUILTIN_BPOSGE32
228 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
229 #define MIPS_FP_CONDITIONS(MACRO) \
247 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
248 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
249 enum mips_fp_condition {
250 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
253 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
254 #define STRINGIFY(X) #X
255 static const char *const mips_fp_conditions[] = {
256 MIPS_FP_CONDITIONS (STRINGIFY)
259 /* A function to save or store a register. The first argument is the
260 register and the second is the stack slot. */
261 typedef void (*mips_save_restore_fn) (rtx, rtx);
263 struct mips16_constant;
264 struct mips_arg_info;
265 struct mips_address_info;
266 struct mips_integer_op;
269 static enum mips_symbol_type mips_classify_symbol (rtx);
270 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
271 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
272 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
273 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
274 static bool mips_classify_address (struct mips_address_info *, rtx,
275 enum machine_mode, int);
276 static bool mips_cannot_force_const_mem (rtx);
277 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
278 static int mips_symbol_insns (enum mips_symbol_type);
279 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
280 static rtx mips_force_temporary (rtx, rtx);
281 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
282 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
283 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
284 static unsigned int mips_build_lower (struct mips_integer_op *,
285 unsigned HOST_WIDE_INT);
286 static unsigned int mips_build_integer (struct mips_integer_op *,
287 unsigned HOST_WIDE_INT);
288 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
289 static int m16_check_op (rtx, int, int, int);
290 static bool mips_rtx_costs (rtx, int, int, int *);
291 static int mips_address_cost (rtx);
292 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
293 static void mips_load_call_address (rtx, rtx, int);
294 static bool mips_function_ok_for_sibcall (tree, tree);
295 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
296 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
297 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
298 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
299 tree, int, struct mips_arg_info *);
300 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
301 static void mips_set_architecture (const struct mips_cpu_info *);
302 static void mips_set_tune (const struct mips_cpu_info *);
303 static bool mips_handle_option (size_t, const char *, int);
304 static struct machine_function *mips_init_machine_status (void);
305 static void print_operand_reloc (FILE *, rtx, const char **);
307 static void irix_output_external_libcall (rtx);
309 static void mips_file_start (void);
310 static void mips_file_end (void);
311 static bool mips_rewrite_small_data_p (rtx);
312 static int mips_small_data_pattern_1 (rtx *, void *);
313 static int mips_rewrite_small_data_1 (rtx *, void *);
314 static bool mips_function_has_gp_insn (void);
315 static unsigned int mips_global_pointer (void);
316 static bool mips_save_reg_p (unsigned int);
317 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
318 mips_save_restore_fn);
319 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
320 static void mips_output_cplocal (void);
321 static void mips_emit_loadgp (void);
322 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
323 static void mips_set_frame_expr (rtx);
324 static rtx mips_frame_set (rtx, rtx);
325 static void mips_save_reg (rtx, rtx);
326 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
327 static void mips_restore_reg (rtx, rtx);
328 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
329 HOST_WIDE_INT, tree);
330 static int symbolic_expression_p (rtx);
331 static section *mips_select_rtx_section (enum machine_mode, rtx,
332 unsigned HOST_WIDE_INT);
333 static section *mips_function_rodata_section (tree);
334 static bool mips_in_small_data_p (tree);
335 static bool mips_use_anchors_for_symbol_p (rtx);
336 static int mips_fpr_return_fields (tree, tree *);
337 static bool mips_return_in_msb (tree);
338 static rtx mips_return_fpr_pair (enum machine_mode mode,
339 enum machine_mode mode1, HOST_WIDE_INT,
340 enum machine_mode mode2, HOST_WIDE_INT);
341 static rtx mips16_gp_pseudo_reg (void);
342 static void mips16_fp_args (FILE *, int, int);
343 static void build_mips16_function_stub (FILE *);
344 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
345 static void dump_constants (struct mips16_constant *, rtx);
346 static int mips16_insn_length (rtx);
347 static int mips16_rewrite_pool_refs (rtx *, void *);
348 static void mips16_lay_out_constants (void);
349 static void mips_sim_reset (struct mips_sim *);
350 static void mips_sim_init (struct mips_sim *, state_t);
351 static void mips_sim_next_cycle (struct mips_sim *);
352 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
353 static int mips_sim_wait_regs_2 (rtx *, void *);
354 static void mips_sim_wait_regs_1 (rtx *, void *);
355 static void mips_sim_wait_regs (struct mips_sim *, rtx);
356 static void mips_sim_wait_units (struct mips_sim *, rtx);
357 static void mips_sim_wait_insn (struct mips_sim *, rtx);
358 static void mips_sim_record_set (rtx, rtx, void *);
359 static void mips_sim_issue_insn (struct mips_sim *, rtx);
360 static void mips_sim_issue_nop (struct mips_sim *);
361 static void mips_sim_finish_insn (struct mips_sim *, rtx);
362 static void vr4130_avoid_branch_rt_conflict (rtx);
363 static void vr4130_align_insns (void);
364 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
365 static void mips_avoid_hazards (void);
366 static void mips_reorg (void);
367 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
368 static bool mips_matching_cpu_name_p (const char *, const char *);
369 static const struct mips_cpu_info *mips_parse_cpu (const char *);
370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
371 static bool mips_return_in_memory (tree, tree);
372 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
373 static void mips_macc_chains_record (rtx);
374 static void mips_macc_chains_reorder (rtx *, int);
375 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
376 static bool vr4130_true_reg_dependence_p (rtx);
377 static bool vr4130_swap_insns_p (rtx, rtx);
378 static void vr4130_reorder (rtx *, int);
379 static void mips_promote_ready (rtx *, int, int);
380 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
381 static int mips_variable_issue (FILE *, int, rtx, int);
382 static int mips_adjust_cost (rtx, rtx, rtx, int);
383 static int mips_issue_rate (void);
384 static int mips_multipass_dfa_lookahead (void);
385 static void mips_init_libfuncs (void);
386 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
388 static tree mips_build_builtin_va_list (void);
389 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
390 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
392 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
394 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
396 static bool mips_valid_pointer_mode (enum machine_mode);
397 static bool mips_vector_mode_supported_p (enum machine_mode);
398 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
399 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
400 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
401 static void mips_init_builtins (void);
402 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
403 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
404 enum insn_code, enum mips_fp_condition,
406 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
407 enum insn_code, enum mips_fp_condition,
409 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
410 static void mips_encode_section_info (tree, rtx, int);
411 static void mips_extra_live_on_entry (bitmap);
412 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
414 /* Structure to be filled in by compute_frame_size with register
415 save masks, and offsets for the current function. */
417 struct mips_frame_info GTY(())
419 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
420 HOST_WIDE_INT var_size; /* # bytes that variables take up */
421 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
422 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
423 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
424 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
425 unsigned int mask; /* mask of saved gp registers */
426 unsigned int fmask; /* mask of saved fp registers */
427 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
428 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
429 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
430 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
431 bool initialized; /* true if frame size already calculated */
432 int num_gp; /* number of gp registers saved */
433 int num_fp; /* number of fp registers saved */
436 struct machine_function GTY(()) {
437 /* Pseudo-reg holding the value of $28 in a mips16 function which
438 refers to GP relative global variables. */
439 rtx mips16_gp_pseudo_rtx;
441 /* The number of extra stack bytes taken up by register varargs.
442 This area is allocated by the callee at the very top of the frame. */
445 /* Current frame information, calculated by compute_frame_size. */
446 struct mips_frame_info frame;
448 /* The register to use as the global pointer within this function. */
449 unsigned int global_pointer;
451 /* True if mips_adjust_insn_length should ignore an instruction's
453 bool ignore_hazard_length_p;
455 /* True if the whole function is suitable for .set noreorder and
457 bool all_noreorder_p;
459 /* True if the function is known to have an instruction that needs $gp. */
463 /* Information about a single argument. */
466 /* True if the argument is passed in a floating-point register, or
467 would have been if we hadn't run out of registers. */
470 /* The number of words passed in registers, rounded up. */
471 unsigned int reg_words;
473 /* For EABI, the offset of the first register from GP_ARG_FIRST or
474 FP_ARG_FIRST. For other ABIs, the offset of the first register from
475 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
476 comment for details).
478 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
480 unsigned int reg_offset;
482 /* The number of words that must be passed on the stack, rounded up. */
483 unsigned int stack_words;
485 /* The offset from the start of the stack overflow area of the argument's
486 first stack word. Only meaningful when STACK_WORDS is nonzero. */
487 unsigned int stack_offset;
491 /* Information about an address described by mips_address_type.
497 REG is the base register and OFFSET is the constant offset.
500 REG is the register that contains the high part of the address,
501 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
502 is the type of OFFSET's symbol.
505 SYMBOL_TYPE is the type of symbol being referenced. */
507 struct mips_address_info
509 enum mips_address_type type;
512 enum mips_symbol_type symbol_type;
516 /* One stage in a constant building sequence. These sequences have
520 A = A CODE[1] VALUE[1]
521 A = A CODE[2] VALUE[2]
524 where A is an accumulator, each CODE[i] is a binary rtl operation
525 and each VALUE[i] is a constant integer. */
526 struct mips_integer_op {
528 unsigned HOST_WIDE_INT value;
532 /* The largest number of operations needed to load an integer constant.
533 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
534 When the lowest bit is clear, we can try, but reject a sequence with
535 an extra SLL at the end. */
536 #define MIPS_MAX_INTEGER_OPS 7
539 /* Global variables for machine-dependent things. */
541 /* Threshold for data being put into the small data/bss area, instead
542 of the normal data area. */
543 int mips_section_threshold = -1;
545 /* Count the number of .file directives, so that .loc is up to date. */
546 int num_source_filenames = 0;
548 /* Count the number of sdb related labels are generated (to find block
549 start and end boundaries). */
550 int sdb_label_count = 0;
552 /* Next label # for each statement for Silicon Graphics IRIS systems. */
555 /* Linked list of all externals that are to be emitted when optimizing
556 for the global pointer if they haven't been declared by the end of
557 the program with an appropriate .comm or initialization. */
559 struct extern_list GTY (())
561 struct extern_list *next; /* next external */
562 const char *name; /* name of the external */
563 int size; /* size in bytes */
566 static GTY (()) struct extern_list *extern_head = 0;
568 /* Name of the file containing the current function. */
569 const char *current_function_file = "";
571 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
577 /* The next branch instruction is a branch likely, not branch normal. */
578 int mips_branch_likely;
580 /* The operands passed to the last cmpMM expander. */
583 /* The target cpu for code generation. */
584 enum processor_type mips_arch;
585 const struct mips_cpu_info *mips_arch_info;
587 /* The target cpu for optimization and scheduling. */
588 enum processor_type mips_tune;
589 const struct mips_cpu_info *mips_tune_info;
591 /* Which instruction set architecture to use. */
594 /* Which ABI to use. */
595 int mips_abi = MIPS_ABI_DEFAULT;
597 /* Cost information to use. */
598 const struct mips_rtx_cost_data *mips_cost;
600 /* Whether we are generating mips16 hard float code. In mips16 mode
601 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
602 -msoft-float was not specified by the user, which means that we
603 should arrange to call mips32 hard floating point code. */
604 int mips16_hard_float;
606 /* The architecture selected by -mipsN. */
607 static const struct mips_cpu_info *mips_isa_info;
609 /* If TRUE, we split addresses into their high and low parts in the RTL. */
610 int mips_split_addresses;
612 /* Mode used for saving/restoring general purpose registers. */
613 static enum machine_mode gpr_mode;
615 /* Array giving truth value on whether or not a given hard register
616 can support a given mode. */
617 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
619 /* List of all MIPS punctuation characters used by print_operand. */
620 char mips_print_operand_punct[256];
622 /* Map GCC register number to debugger register number. */
623 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
625 /* A copy of the original flag_delayed_branch: see override_options. */
626 static int mips_flag_delayed_branch;
628 static GTY (()) int mips_output_filename_first_time = 1;
630 /* mips_split_p[X] is true if symbols of type X can be split by
631 mips_split_symbol(). */
632 bool mips_split_p[NUM_SYMBOL_TYPES];
634 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
635 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
636 if they are matched by a special .md file pattern. */
637 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
639 /* Likewise for HIGHs. */
640 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
642 /* Map hard register number to register class */
643 const enum reg_class mips_regno_to_class[] =
645 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
646 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
647 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
648 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
649 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
650 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
651 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
652 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
658 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
659 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
660 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
661 HI_REG, LO_REG, NO_REGS, ST_REGS,
662 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
663 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
664 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
665 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
666 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
667 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
668 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
669 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
670 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
671 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
672 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
673 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
674 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
675 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
676 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
677 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
678 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
679 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
680 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
681 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
682 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
683 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
684 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
685 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
686 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
687 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
688 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
689 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
690 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
691 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
694 /* Table of machine dependent attributes. */
695 const struct attribute_spec mips_attribute_table[] =
697 { "long_call", 0, 0, false, true, true, NULL },
698 { NULL, 0, 0, false, false, false, NULL }
701 /* A table describing all the processors gcc knows about. Names are
702 matched in the order listed. The first mention of an ISA level is
703 taken as the canonical name for that ISA.
705 To ease comparison, please keep this table in the same order as
706 gas's mips_cpu_info_table[]. */
707 const struct mips_cpu_info mips_cpu_info_table[] = {
708 /* Entries for generic ISAs */
709 { "mips1", PROCESSOR_R3000, 1 },
710 { "mips2", PROCESSOR_R6000, 2 },
711 { "mips3", PROCESSOR_R4000, 3 },
712 { "mips4", PROCESSOR_R8000, 4 },
713 { "mips32", PROCESSOR_4KC, 32 },
714 { "mips32r2", PROCESSOR_M4K, 33 },
715 { "mips64", PROCESSOR_5KC, 64 },
718 { "r3000", PROCESSOR_R3000, 1 },
719 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
720 { "r3900", PROCESSOR_R3900, 1 },
723 { "r6000", PROCESSOR_R6000, 2 },
726 { "r4000", PROCESSOR_R4000, 3 },
727 { "vr4100", PROCESSOR_R4100, 3 },
728 { "vr4111", PROCESSOR_R4111, 3 },
729 { "vr4120", PROCESSOR_R4120, 3 },
730 { "vr4130", PROCESSOR_R4130, 3 },
731 { "vr4300", PROCESSOR_R4300, 3 },
732 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
733 { "r4600", PROCESSOR_R4600, 3 },
734 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
735 { "r4650", PROCESSOR_R4650, 3 },
738 { "r8000", PROCESSOR_R8000, 4 },
739 { "vr5000", PROCESSOR_R5000, 4 },
740 { "vr5400", PROCESSOR_R5400, 4 },
741 { "vr5500", PROCESSOR_R5500, 4 },
742 { "rm7000", PROCESSOR_R7000, 4 },
743 { "rm9000", PROCESSOR_R9000, 4 },
746 { "4kc", PROCESSOR_4KC, 32 },
747 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
748 { "4kp", PROCESSOR_4KP, 32 },
750 /* MIPS32 Release 2 */
751 { "m4k", PROCESSOR_M4K, 33 },
752 { "24k", PROCESSOR_24K, 33 },
753 { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
754 { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
755 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
758 { "5kc", PROCESSOR_5KC, 64 },
759 { "5kf", PROCESSOR_5KF, 64 },
760 { "20kc", PROCESSOR_20KC, 64 },
761 { "sb1", PROCESSOR_SB1, 64 },
762 { "sb1a", PROCESSOR_SB1A, 64 },
763 { "sr71000", PROCESSOR_SR71000, 64 },
769 /* Default costs. If these are used for a processor we should look
770 up the actual costs. */
771 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
772 COSTS_N_INSNS (7), /* fp_mult_sf */ \
773 COSTS_N_INSNS (8), /* fp_mult_df */ \
774 COSTS_N_INSNS (23), /* fp_div_sf */ \
775 COSTS_N_INSNS (36), /* fp_div_df */ \
776 COSTS_N_INSNS (10), /* int_mult_si */ \
777 COSTS_N_INSNS (10), /* int_mult_di */ \
778 COSTS_N_INSNS (69), /* int_div_si */ \
779 COSTS_N_INSNS (69), /* int_div_di */ \
780 2, /* branch_cost */ \
781 4 /* memory_latency */
783 /* Need to replace these with the costs of calling the appropriate
785 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
786 COSTS_N_INSNS (256), /* fp_mult_sf */ \
787 COSTS_N_INSNS (256), /* fp_mult_df */ \
788 COSTS_N_INSNS (256), /* fp_div_sf */ \
789 COSTS_N_INSNS (256) /* fp_div_df */
791 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
794 COSTS_N_INSNS (2), /* fp_add */
795 COSTS_N_INSNS (4), /* fp_mult_sf */
796 COSTS_N_INSNS (5), /* fp_mult_df */
797 COSTS_N_INSNS (12), /* fp_div_sf */
798 COSTS_N_INSNS (19), /* fp_div_df */
799 COSTS_N_INSNS (12), /* int_mult_si */
800 COSTS_N_INSNS (12), /* int_mult_di */
801 COSTS_N_INSNS (35), /* int_div_si */
802 COSTS_N_INSNS (35), /* int_div_di */
804 4 /* memory_latency */
809 COSTS_N_INSNS (6), /* int_mult_si */
810 COSTS_N_INSNS (6), /* int_mult_di */
811 COSTS_N_INSNS (36), /* int_div_si */
812 COSTS_N_INSNS (36), /* int_div_di */
814 4 /* memory_latency */
818 COSTS_N_INSNS (36), /* int_mult_si */
819 COSTS_N_INSNS (36), /* int_mult_di */
820 COSTS_N_INSNS (37), /* int_div_si */
821 COSTS_N_INSNS (37), /* int_div_di */
823 4 /* memory_latency */
827 COSTS_N_INSNS (4), /* int_mult_si */
828 COSTS_N_INSNS (11), /* int_mult_di */
829 COSTS_N_INSNS (36), /* int_div_si */
830 COSTS_N_INSNS (68), /* int_div_di */
832 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* fp_add */
836 COSTS_N_INSNS (4), /* fp_mult_sf */
837 COSTS_N_INSNS (5), /* fp_mult_df */
838 COSTS_N_INSNS (17), /* fp_div_sf */
839 COSTS_N_INSNS (32), /* fp_div_df */
840 COSTS_N_INSNS (4), /* int_mult_si */
841 COSTS_N_INSNS (11), /* int_mult_di */
842 COSTS_N_INSNS (36), /* int_div_si */
843 COSTS_N_INSNS (68), /* int_div_di */
845 4 /* memory_latency */
851 COSTS_N_INSNS (8), /* fp_add */
852 COSTS_N_INSNS (8), /* fp_mult_sf */
853 COSTS_N_INSNS (10), /* fp_mult_df */
854 COSTS_N_INSNS (34), /* fp_div_sf */
855 COSTS_N_INSNS (64), /* fp_div_df */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
864 COSTS_N_INSNS (4), /* fp_add */
865 COSTS_N_INSNS (4), /* fp_mult_sf */
866 COSTS_N_INSNS (5), /* fp_mult_df */
867 COSTS_N_INSNS (17), /* fp_div_sf */
868 COSTS_N_INSNS (32), /* fp_div_df */
869 COSTS_N_INSNS (5), /* int_mult_si */
870 COSTS_N_INSNS (5), /* int_mult_di */
871 COSTS_N_INSNS (41), /* int_div_si */
872 COSTS_N_INSNS (41), /* int_div_di */
874 4 /* memory_latency */
880 COSTS_N_INSNS (2), /* fp_add */
881 COSTS_N_INSNS (4), /* fp_mult_sf */
882 COSTS_N_INSNS (5), /* fp_mult_df */
883 COSTS_N_INSNS (12), /* fp_div_sf */
884 COSTS_N_INSNS (19), /* fp_div_df */
885 COSTS_N_INSNS (2), /* int_mult_si */
886 COSTS_N_INSNS (2), /* int_mult_di */
887 COSTS_N_INSNS (35), /* int_div_si */
888 COSTS_N_INSNS (35), /* int_div_di */
890 4 /* memory_latency */
893 COSTS_N_INSNS (3), /* fp_add */
894 COSTS_N_INSNS (5), /* fp_mult_sf */
895 COSTS_N_INSNS (6), /* fp_mult_df */
896 COSTS_N_INSNS (15), /* fp_div_sf */
897 COSTS_N_INSNS (16), /* fp_div_df */
898 COSTS_N_INSNS (17), /* int_mult_si */
899 COSTS_N_INSNS (17), /* int_mult_di */
900 COSTS_N_INSNS (38), /* int_div_si */
901 COSTS_N_INSNS (38), /* int_div_di */
903 6 /* memory_latency */
906 COSTS_N_INSNS (6), /* fp_add */
907 COSTS_N_INSNS (7), /* fp_mult_sf */
908 COSTS_N_INSNS (8), /* fp_mult_df */
909 COSTS_N_INSNS (23), /* fp_div_sf */
910 COSTS_N_INSNS (36), /* fp_div_df */
911 COSTS_N_INSNS (10), /* int_mult_si */
912 COSTS_N_INSNS (10), /* int_mult_di */
913 COSTS_N_INSNS (69), /* int_div_si */
914 COSTS_N_INSNS (69), /* int_div_di */
916 6 /* memory_latency */
928 /* The only costs that appear to be updated here are
929 integer multiplication. */
931 COSTS_N_INSNS (4), /* int_mult_si */
932 COSTS_N_INSNS (6), /* int_mult_di */
933 COSTS_N_INSNS (69), /* int_div_si */
934 COSTS_N_INSNS (69), /* int_div_di */
936 4 /* memory_latency */
948 COSTS_N_INSNS (6), /* fp_add */
949 COSTS_N_INSNS (4), /* fp_mult_sf */
950 COSTS_N_INSNS (5), /* fp_mult_df */
951 COSTS_N_INSNS (23), /* fp_div_sf */
952 COSTS_N_INSNS (36), /* fp_div_df */
953 COSTS_N_INSNS (5), /* int_mult_si */
954 COSTS_N_INSNS (5), /* int_mult_di */
955 COSTS_N_INSNS (36), /* int_div_si */
956 COSTS_N_INSNS (36), /* int_div_di */
958 4 /* memory_latency */
961 COSTS_N_INSNS (6), /* fp_add */
962 COSTS_N_INSNS (5), /* fp_mult_sf */
963 COSTS_N_INSNS (6), /* fp_mult_df */
964 COSTS_N_INSNS (30), /* fp_div_sf */
965 COSTS_N_INSNS (59), /* fp_div_df */
966 COSTS_N_INSNS (3), /* int_mult_si */
967 COSTS_N_INSNS (4), /* int_mult_di */
968 COSTS_N_INSNS (42), /* int_div_si */
969 COSTS_N_INSNS (74), /* int_div_di */
971 4 /* memory_latency */
974 COSTS_N_INSNS (6), /* fp_add */
975 COSTS_N_INSNS (5), /* fp_mult_sf */
976 COSTS_N_INSNS (6), /* fp_mult_df */
977 COSTS_N_INSNS (30), /* fp_div_sf */
978 COSTS_N_INSNS (59), /* fp_div_df */
979 COSTS_N_INSNS (5), /* int_mult_si */
980 COSTS_N_INSNS (9), /* int_mult_di */
981 COSTS_N_INSNS (42), /* int_div_si */
982 COSTS_N_INSNS (74), /* int_div_di */
984 4 /* memory_latency */
987 /* The only costs that are changed here are
988 integer multiplication. */
989 COSTS_N_INSNS (6), /* fp_add */
990 COSTS_N_INSNS (7), /* fp_mult_sf */
991 COSTS_N_INSNS (8), /* fp_mult_df */
992 COSTS_N_INSNS (23), /* fp_div_sf */
993 COSTS_N_INSNS (36), /* fp_div_df */
994 COSTS_N_INSNS (5), /* int_mult_si */
995 COSTS_N_INSNS (9), /* int_mult_di */
996 COSTS_N_INSNS (69), /* int_div_si */
997 COSTS_N_INSNS (69), /* int_div_di */
999 4 /* memory_latency */
1005 /* The only costs that are changed here are
1006 integer multiplication. */
1007 COSTS_N_INSNS (6), /* fp_add */
1008 COSTS_N_INSNS (7), /* fp_mult_sf */
1009 COSTS_N_INSNS (8), /* fp_mult_df */
1010 COSTS_N_INSNS (23), /* fp_div_sf */
1011 COSTS_N_INSNS (36), /* fp_div_df */
1012 COSTS_N_INSNS (3), /* int_mult_si */
1013 COSTS_N_INSNS (8), /* int_mult_di */
1014 COSTS_N_INSNS (69), /* int_div_si */
1015 COSTS_N_INSNS (69), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1020 /* These costs are the same as the SB-1A below. */
1021 COSTS_N_INSNS (4), /* fp_add */
1022 COSTS_N_INSNS (4), /* fp_mult_sf */
1023 COSTS_N_INSNS (4), /* fp_mult_df */
1024 COSTS_N_INSNS (24), /* fp_div_sf */
1025 COSTS_N_INSNS (32), /* fp_div_df */
1026 COSTS_N_INSNS (3), /* int_mult_si */
1027 COSTS_N_INSNS (4), /* int_mult_di */
1028 COSTS_N_INSNS (36), /* int_div_si */
1029 COSTS_N_INSNS (68), /* int_div_di */
1030 1, /* branch_cost */
1031 4 /* memory_latency */
1034 /* These costs are the same as the SB-1 above. */
1035 COSTS_N_INSNS (4), /* fp_add */
1036 COSTS_N_INSNS (4), /* fp_mult_sf */
1037 COSTS_N_INSNS (4), /* fp_mult_df */
1038 COSTS_N_INSNS (24), /* fp_div_sf */
1039 COSTS_N_INSNS (32), /* fp_div_df */
1040 COSTS_N_INSNS (3), /* int_mult_si */
1041 COSTS_N_INSNS (4), /* int_mult_di */
1042 COSTS_N_INSNS (36), /* int_div_si */
1043 COSTS_N_INSNS (68), /* int_div_di */
1044 1, /* branch_cost */
1045 4 /* memory_latency */
1053 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1054 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1055 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1058 /* Initialize the GCC target structure. */
1059 #undef TARGET_ASM_ALIGNED_HI_OP
1060 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1061 #undef TARGET_ASM_ALIGNED_SI_OP
1062 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1063 #undef TARGET_ASM_ALIGNED_DI_OP
1064 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1066 #undef TARGET_ASM_FUNCTION_PROLOGUE
1067 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1068 #undef TARGET_ASM_FUNCTION_EPILOGUE
1069 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1070 #undef TARGET_ASM_SELECT_RTX_SECTION
1071 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1072 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1073 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1075 #undef TARGET_SCHED_REORDER
1076 #define TARGET_SCHED_REORDER mips_sched_reorder
1077 #undef TARGET_SCHED_VARIABLE_ISSUE
1078 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1079 #undef TARGET_SCHED_ADJUST_COST
1080 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1081 #undef TARGET_SCHED_ISSUE_RATE
1082 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1083 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1084 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1085 mips_multipass_dfa_lookahead
1087 #undef TARGET_DEFAULT_TARGET_FLAGS
1088 #define TARGET_DEFAULT_TARGET_FLAGS \
1090 | TARGET_CPU_DEFAULT \
1091 | TARGET_ENDIAN_DEFAULT \
1092 | TARGET_FP_EXCEPTIONS_DEFAULT \
1093 | MASK_CHECK_ZERO_DIV \
1095 #undef TARGET_HANDLE_OPTION
1096 #define TARGET_HANDLE_OPTION mips_handle_option
1098 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1099 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1101 #undef TARGET_VALID_POINTER_MODE
1102 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1103 #undef TARGET_RTX_COSTS
1104 #define TARGET_RTX_COSTS mips_rtx_costs
1105 #undef TARGET_ADDRESS_COST
1106 #define TARGET_ADDRESS_COST mips_address_cost
1108 #undef TARGET_IN_SMALL_DATA_P
1109 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1111 #undef TARGET_MACHINE_DEPENDENT_REORG
1112 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1114 #undef TARGET_ASM_FILE_START
1115 #undef TARGET_ASM_FILE_END
1116 #define TARGET_ASM_FILE_START mips_file_start
1117 #define TARGET_ASM_FILE_END mips_file_end
1118 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1119 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1121 #undef TARGET_INIT_LIBFUNCS
1122 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1124 #undef TARGET_BUILD_BUILTIN_VA_LIST
1125 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1126 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1127 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1129 #undef TARGET_PROMOTE_FUNCTION_ARGS
1130 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1131 #undef TARGET_PROMOTE_FUNCTION_RETURN
1132 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1133 #undef TARGET_PROMOTE_PROTOTYPES
1134 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1136 #undef TARGET_RETURN_IN_MEMORY
1137 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1138 #undef TARGET_RETURN_IN_MSB
1139 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1141 #undef TARGET_ASM_OUTPUT_MI_THUNK
1142 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1143 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1144 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1146 #undef TARGET_SETUP_INCOMING_VARARGS
1147 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1148 #undef TARGET_STRICT_ARGUMENT_NAMING
1149 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1150 #undef TARGET_MUST_PASS_IN_STACK
1151 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1152 #undef TARGET_PASS_BY_REFERENCE
1153 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1154 #undef TARGET_CALLEE_COPIES
1155 #define TARGET_CALLEE_COPIES mips_callee_copies
1156 #undef TARGET_ARG_PARTIAL_BYTES
1157 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1159 #undef TARGET_MODE_REP_EXTENDED
1160 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1162 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1163 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1165 #undef TARGET_INIT_BUILTINS
1166 #define TARGET_INIT_BUILTINS mips_init_builtins
1167 #undef TARGET_EXPAND_BUILTIN
1168 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1170 #undef TARGET_HAVE_TLS
1171 #define TARGET_HAVE_TLS HAVE_AS_TLS
1173 #undef TARGET_CANNOT_FORCE_CONST_MEM
1174 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1176 #undef TARGET_ENCODE_SECTION_INFO
1177 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1179 #undef TARGET_ATTRIBUTE_TABLE
1180 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1182 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1183 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1185 #undef TARGET_MIN_ANCHOR_OFFSET
1186 #define TARGET_MIN_ANCHOR_OFFSET -32768
1187 #undef TARGET_MAX_ANCHOR_OFFSET
1188 #define TARGET_MAX_ANCHOR_OFFSET 32767
1189 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1190 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1191 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1192 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1194 struct gcc_target targetm = TARGET_INITIALIZER;
1196 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1198 static enum mips_symbol_type
1199 mips_classify_symbol (rtx x)
1201 if (GET_CODE (x) == LABEL_REF)
1204 return SYMBOL_CONSTANT_POOL;
1205 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1206 return SYMBOL_GOT_LOCAL;
1207 return SYMBOL_GENERAL;
1210 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1212 if (SYMBOL_REF_TLS_MODEL (x))
1215 if (CONSTANT_POOL_ADDRESS_P (x))
1218 return SYMBOL_CONSTANT_POOL;
1220 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1221 return SYMBOL_SMALL_DATA;
1224 /* Do not use small-data accesses for weak symbols; they may end up
1226 if (SYMBOL_REF_SMALL_P (x)
1227 && !SYMBOL_REF_WEAK (x))
1228 return SYMBOL_SMALL_DATA;
1230 if (TARGET_ABICALLS)
1232 if (SYMBOL_REF_DECL (x) == 0)
1234 if (!SYMBOL_REF_LOCAL_P (x))
1235 return SYMBOL_GOT_GLOBAL;
1239 /* Don't use GOT accesses for locally-binding symbols if
1240 TARGET_ABSOLUTE_ABICALLS. Otherwise, there are three
1243 - o32 PIC (either with or without explicit relocs)
1244 - n32/n64 PIC without explicit relocs
1245 - n32/n64 PIC with explicit relocs
1247 In the first case, both local and global accesses will use an
1248 R_MIPS_GOT16 relocation. We must correctly predict which of
1249 the two semantics (local or global) the assembler and linker
1250 will apply. The choice doesn't depend on the symbol's
1251 visibility, so we deliberately ignore decl_visibility and
1254 In the second case, the assembler will not use R_MIPS_GOT16
1255 relocations, but it chooses between local and global accesses
1256 in the same way as for o32 PIC.
1258 In the third case we have more freedom since both forms of
1259 access will work for any kind of symbol. However, there seems
1260 little point in doing things differently. */
1261 if (DECL_P (SYMBOL_REF_DECL (x))
1262 && TREE_PUBLIC (SYMBOL_REF_DECL (x))
1263 && !(TARGET_ABSOLUTE_ABICALLS
1264 && targetm.binds_local_p (SYMBOL_REF_DECL (x))))
1265 return SYMBOL_GOT_GLOBAL;
1268 if (!TARGET_ABSOLUTE_ABICALLS)
1269 return SYMBOL_GOT_LOCAL;
1272 return SYMBOL_GENERAL;
1276 /* Split X into a base and a constant offset, storing them in *BASE
1277 and *OFFSET respectively. */
1280 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1284 if (GET_CODE (x) == CONST)
1287 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1289 *offset += INTVAL (XEXP (x, 1));
1297 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1298 to the same object as SYMBOL, or to the same object_block. */
1301 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1303 if (GET_CODE (symbol) != SYMBOL_REF)
1306 if (CONSTANT_POOL_ADDRESS_P (symbol)
1308 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1311 if (SYMBOL_REF_DECL (symbol) != 0
1313 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1316 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)
1317 && SYMBOL_REF_BLOCK (symbol)
1318 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0
1319 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)
1320 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size))
1327 /* Return true if X is a symbolic constant that can be calculated in
1328 the same way as a bare symbol. If it is, store the type of the
1329 symbol in *SYMBOL_TYPE. */
1332 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1334 HOST_WIDE_INT offset;
1336 mips_split_const (x, &x, &offset);
1337 if (UNSPEC_ADDRESS_P (x))
1338 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1339 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1341 *symbol_type = mips_classify_symbol (x);
1342 if (*symbol_type == SYMBOL_TLS)
1351 /* Check whether a nonzero offset is valid for the underlying
1353 switch (*symbol_type)
1355 case SYMBOL_GENERAL:
1356 case SYMBOL_64_HIGH:
1359 /* If the target has 64-bit pointers and the object file only
1360 supports 32-bit symbols, the values of those symbols will be
1361 sign-extended. In this case we can't allow an arbitrary offset
1362 in case the 32-bit value X + OFFSET has a different sign from X. */
1363 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1364 return mips_offset_within_object_p (x, offset);
1366 /* In other cases the relocations can handle any offset. */
1369 case SYMBOL_CONSTANT_POOL:
1370 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1371 In this case, we no longer have access to the underlying constant,
1372 but the original symbol-based access was known to be valid. */
1373 if (GET_CODE (x) == LABEL_REF)
1378 case SYMBOL_SMALL_DATA:
1379 /* Make sure that the offset refers to something within the
1380 underlying object. This should guarantee that the final
1381 PC- or GP-relative offset is within the 16-bit limit. */
1382 return mips_offset_within_object_p (x, offset);
1384 case SYMBOL_GOT_LOCAL:
1385 case SYMBOL_GOTOFF_PAGE:
1386 /* The linker should provide enough local GOT entries for a
1387 16-bit offset. Larger offsets may lead to GOT overflow. */
1388 return SMALL_OPERAND (offset);
1390 case SYMBOL_GOT_GLOBAL:
1391 case SYMBOL_GOTOFF_GLOBAL:
1392 case SYMBOL_GOTOFF_CALL:
1393 case SYMBOL_GOTOFF_LOADGP:
1398 case SYMBOL_GOTTPREL:
1406 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1409 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1411 if (regno >= FIRST_PSEUDO_REGISTER)
1415 regno = reg_renumber[regno];
1418 /* These fake registers will be eliminated to either the stack or
1419 hard frame pointer, both of which are usually valid base registers.
1420 Reload deals with the cases where the eliminated form isn't valid. */
1421 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1424 /* In mips16 mode, the stack pointer can only address word and doubleword
1425 values, nothing smaller. There are two problems here:
1427 (a) Instantiating virtual registers can introduce new uses of the
1428 stack pointer. If these virtual registers are valid addresses,
1429 the stack pointer should be too.
1431 (b) Most uses of the stack pointer are not made explicit until
1432 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1433 We don't know until that stage whether we'll be eliminating to the
1434 stack pointer (which needs the restriction) or the hard frame
1435 pointer (which doesn't).
1437 All in all, it seems more consistent to only enforce this restriction
1438 during and after reload. */
1439 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1440 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1442 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1446 /* Return true if X is a valid base register for the given mode.
1447 Allow only hard registers if STRICT. */
1450 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1452 if (!strict && GET_CODE (x) == SUBREG)
1456 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1460 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1461 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1464 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1465 enum machine_mode mode)
1467 switch (symbol_type)
1469 case SYMBOL_GENERAL:
1470 return !TARGET_MIPS16;
1472 case SYMBOL_SMALL_DATA:
1475 case SYMBOL_CONSTANT_POOL:
1476 /* PC-relative addressing is only available for lw and ld. */
1477 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1479 case SYMBOL_GOT_LOCAL:
1482 case SYMBOL_GOT_GLOBAL:
1483 /* The address will have to be loaded from the GOT first. */
1486 case SYMBOL_GOTOFF_PAGE:
1487 case SYMBOL_GOTOFF_GLOBAL:
1488 case SYMBOL_GOTOFF_CALL:
1489 case SYMBOL_GOTOFF_LOADGP:
1494 case SYMBOL_GOTTPREL:
1496 case SYMBOL_64_HIGH:
1505 /* Return true if X is a valid address for machine mode MODE. If it is,
1506 fill in INFO appropriately. STRICT is true if we should only accept
1507 hard base registers. */
1510 mips_classify_address (struct mips_address_info *info, rtx x,
1511 enum machine_mode mode, int strict)
1513 switch (GET_CODE (x))
1517 info->type = ADDRESS_REG;
1519 info->offset = const0_rtx;
1520 return mips_valid_base_register_p (info->reg, mode, strict);
1523 info->type = ADDRESS_REG;
1524 info->reg = XEXP (x, 0);
1525 info->offset = XEXP (x, 1);
1526 return (mips_valid_base_register_p (info->reg, mode, strict)
1527 && const_arith_operand (info->offset, VOIDmode));
1530 info->type = ADDRESS_LO_SUM;
1531 info->reg = XEXP (x, 0);
1532 info->offset = XEXP (x, 1);
1533 return (mips_valid_base_register_p (info->reg, mode, strict)
1534 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1535 && mips_symbolic_address_p (info->symbol_type, mode)
1536 && mips_lo_relocs[info->symbol_type] != 0);
1539 /* Small-integer addresses don't occur very often, but they
1540 are legitimate if $0 is a valid base register. */
1541 info->type = ADDRESS_CONST_INT;
1542 return !TARGET_MIPS16 && SMALL_INT (x);
1547 info->type = ADDRESS_SYMBOLIC;
1548 return (mips_symbolic_constant_p (x, &info->symbol_type)
1549 && mips_symbolic_address_p (info->symbol_type, mode)
1550 && !mips_split_p[info->symbol_type]);
1557 /* Return true if X is a thread-local symbol. */
1560 mips_tls_operand_p (rtx x)
1562 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1565 /* Return true if X can not be forced into a constant pool. */
1568 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1570 return mips_tls_operand_p (*x);
1573 /* Return true if X can not be forced into a constant pool. */
1576 mips_cannot_force_const_mem (rtx x)
1579 HOST_WIDE_INT offset;
1583 /* As an optimization, reject constants that mips_legitimize_move
1586 Suppose we have a multi-instruction sequence that loads constant C
1587 into register R. If R does not get allocated a hard register, and
1588 R is used in an operand that allows both registers and memory
1589 references, reload will consider forcing C into memory and using
1590 one of the instruction's memory alternatives. Returning false
1591 here will force it to use an input reload instead. */
1592 if (GET_CODE (x) == CONST_INT)
1595 mips_split_const (x, &base, &offset);
1596 if (symbolic_operand (base, VOIDmode) && SMALL_OPERAND (offset))
1600 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1606 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1607 constant pools, but normal-mode code doesn't need to. */
1610 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1611 rtx x ATTRIBUTE_UNUSED)
1613 return !TARGET_MIPS16;
1616 /* Return the number of instructions needed to load a symbol of the
1617 given type into a register. If valid in an address, the same number
1618 of instructions are needed for loads and stores. Treat extended
1619 mips16 instructions as two instructions. */
1622 mips_symbol_insns (enum mips_symbol_type type)
1626 case SYMBOL_GENERAL:
1627 /* In mips16 code, general symbols must be fetched from the
1632 /* When using 64-bit symbols, we need 5 preparatory instructions,
1635 lui $at,%highest(symbol)
1636 daddiu $at,$at,%higher(symbol)
1638 daddiu $at,$at,%hi(symbol)
1641 The final address is then $at + %lo(symbol). With 32-bit
1642 symbols we just need a preparatory lui. */
1643 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1645 case SYMBOL_SMALL_DATA:
1648 case SYMBOL_CONSTANT_POOL:
1649 /* This case is for mips16 only. Assume we'll need an
1650 extended instruction. */
1653 case SYMBOL_GOT_LOCAL:
1654 case SYMBOL_GOT_GLOBAL:
1655 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1656 the local/global classification is accurate. See override_options
1659 The worst cases are:
1661 (1) For local symbols when generating o32 or o64 code. The assembler
1667 ...and the final address will be $at + %lo(symbol).
1669 (2) For global symbols when -mxgot. The assembler will use:
1671 lui $at,%got_hi(symbol)
1674 ...and the final address will be $at + %got_lo(symbol). */
1677 case SYMBOL_GOTOFF_PAGE:
1678 case SYMBOL_GOTOFF_GLOBAL:
1679 case SYMBOL_GOTOFF_CALL:
1680 case SYMBOL_GOTOFF_LOADGP:
1681 case SYMBOL_64_HIGH:
1687 case SYMBOL_GOTTPREL:
1689 /* Check whether the offset is a 16- or 32-bit value. */
1690 return mips_split_p[type] ? 2 : 1;
1693 /* We don't treat a bare TLS symbol as a constant. */
1699 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1702 mips_stack_address_p (rtx x, enum machine_mode mode)
1704 struct mips_address_info addr;
1706 return (mips_classify_address (&addr, x, mode, false)
1707 && addr.type == ADDRESS_REG
1708 && addr.reg == stack_pointer_rtx);
1711 /* Return true if a value at OFFSET bytes from BASE can be accessed
1712 using an unextended mips16 instruction. MODE is the mode of the
1715 Usually the offset in an unextended instruction is a 5-bit field.
1716 The offset is unsigned and shifted left once for HIs, twice
1717 for SIs, and so on. An exception is SImode accesses off the
1718 stack pointer, which have an 8-bit immediate field. */
1721 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1724 && GET_CODE (offset) == CONST_INT
1725 && INTVAL (offset) >= 0
1726 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1728 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1729 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1730 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1736 /* Return the number of instructions needed to load or store a value
1737 of mode MODE at X. Return 0 if X isn't valid for MODE.
1739 For mips16 code, count extended instructions as two instructions. */
1742 mips_address_insns (rtx x, enum machine_mode mode)
1744 struct mips_address_info addr;
1747 if (mode == BLKmode)
1748 /* BLKmode is used for single unaligned loads and stores. */
1751 /* Each word of a multi-word value will be accessed individually. */
1752 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1754 if (mips_classify_address (&addr, x, mode, false))
1759 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1763 case ADDRESS_LO_SUM:
1764 return (TARGET_MIPS16 ? factor * 2 : factor);
1766 case ADDRESS_CONST_INT:
1769 case ADDRESS_SYMBOLIC:
1770 return factor * mips_symbol_insns (addr.symbol_type);
1776 /* Likewise for constant X. */
1779 mips_const_insns (rtx x)
1781 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1782 enum mips_symbol_type symbol_type;
1783 HOST_WIDE_INT offset;
1785 switch (GET_CODE (x))
1789 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1790 || !mips_split_p[symbol_type])
1797 /* Unsigned 8-bit constants can be loaded using an unextended
1798 LI instruction. Unsigned 16-bit constants can be loaded
1799 using an extended LI. Negative constants must be loaded
1800 using LI and then negated. */
1801 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1802 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1803 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1804 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1807 return mips_build_integer (codes, INTVAL (x));
1811 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1817 /* See if we can refer to X directly. */
1818 if (mips_symbolic_constant_p (x, &symbol_type))
1819 return mips_symbol_insns (symbol_type);
1821 /* Otherwise try splitting the constant into a base and offset.
1822 16-bit offsets can be added using an extra addiu. Larger offsets
1823 must be calculated separately and then added to the base. */
1824 mips_split_const (x, &x, &offset);
1827 int n = mips_const_insns (x);
1830 if (SMALL_OPERAND (offset))
1833 return n + 1 + mips_build_integer (codes, offset);
1840 return mips_symbol_insns (mips_classify_symbol (x));
1848 /* Return the number of instructions needed for memory reference X.
1849 Count extended mips16 instructions as two instructions. */
1852 mips_fetch_insns (rtx x)
1854 gcc_assert (MEM_P (x));
1855 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1859 /* Return the number of instructions needed for an integer division. */
1862 mips_idiv_insns (void)
1867 if (TARGET_CHECK_ZERO_DIV)
1869 if (GENERATE_DIVIDE_TRAPS)
1875 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1880 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1881 returns a nonzero value if X is a legitimate address for a memory
1882 operand of the indicated MODE. STRICT is nonzero if this function
1883 is called during reload. */
1886 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1888 struct mips_address_info addr;
1890 return mips_classify_address (&addr, x, mode, strict);
1894 /* Copy VALUE to a register and return that register. If new psuedos
1895 are allowed, copy it into a new register, otherwise use DEST. */
1898 mips_force_temporary (rtx dest, rtx value)
1900 if (!no_new_pseudos)
1901 return force_reg (Pmode, value);
1904 emit_move_insn (copy_rtx (dest), value);
1910 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1911 and is used to load the high part into a register. */
1914 mips_split_symbol (rtx temp, rtx addr)
1919 high = mips16_gp_pseudo_reg ();
1921 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1922 return gen_rtx_LO_SUM (Pmode, high, addr);
1926 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1927 type SYMBOL_TYPE. */
1930 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1933 HOST_WIDE_INT offset;
1935 mips_split_const (address, &base, &offset);
1936 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1937 UNSPEC_ADDRESS_FIRST + symbol_type);
1938 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1942 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1943 high part to BASE and return the result. Just return BASE otherwise.
1944 TEMP is available as a temporary register if needed.
1946 The returned expression can be used as the first operand to a LO_SUM. */
1949 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1950 enum mips_symbol_type symbol_type)
1952 if (mips_split_p[symbol_type])
1954 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1955 addr = mips_force_temporary (temp, addr);
1956 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1962 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1963 mips_force_temporary; it is only needed when OFFSET is not a
1967 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1969 if (!SMALL_OPERAND (offset))
1974 /* Load the full offset into a register so that we can use
1975 an unextended instruction for the address itself. */
1976 high = GEN_INT (offset);
1981 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1982 high = GEN_INT (CONST_HIGH_PART (offset));
1983 offset = CONST_LOW_PART (offset);
1985 high = mips_force_temporary (temp, high);
1986 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1988 return plus_constant (reg, offset);
1991 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1992 referencing, and TYPE is the symbol type to use (either global
1993 dynamic or local dynamic). V0 is an RTX for the return value
1994 location. The entire insn sequence is returned. */
1996 static GTY(()) rtx mips_tls_symbol;
1999 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2001 rtx insn, loc, tga, a0;
2003 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2005 if (!mips_tls_symbol)
2006 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2008 loc = mips_unspec_address (sym, type);
2012 emit_insn (gen_rtx_SET (Pmode, a0,
2013 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2014 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2015 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2016 CONST_OR_PURE_CALL_P (insn) = 1;
2017 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2018 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2019 insn = get_insns ();
2026 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2027 return value will be a valid address and move_operand (either a REG
2031 mips_legitimize_tls_address (rtx loc)
2033 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2034 enum tls_model model;
2036 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2037 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2039 model = SYMBOL_REF_TLS_MODEL (loc);
2040 /* Only TARGET_ABICALLS code can have more than one module; other
2041 code must be be static and should not use a GOT. All TLS models
2042 reduce to local exec in this situation. */
2043 if (!TARGET_ABICALLS)
2044 model = TLS_MODEL_LOCAL_EXEC;
2048 case TLS_MODEL_GLOBAL_DYNAMIC:
2049 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2050 dest = gen_reg_rtx (Pmode);
2051 emit_libcall_block (insn, dest, v0, loc);
2054 case TLS_MODEL_LOCAL_DYNAMIC:
2055 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2056 tmp1 = gen_reg_rtx (Pmode);
2058 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2059 share the LDM result with other LD model accesses. */
2060 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2062 emit_libcall_block (insn, tmp1, v0, eqv);
2064 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2065 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2066 mips_unspec_address (loc, SYMBOL_DTPREL));
2069 case TLS_MODEL_INITIAL_EXEC:
2070 tmp1 = gen_reg_rtx (Pmode);
2071 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2072 if (Pmode == DImode)
2074 emit_insn (gen_tls_get_tp_di (v1));
2075 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2079 emit_insn (gen_tls_get_tp_si (v1));
2080 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2082 dest = gen_reg_rtx (Pmode);
2083 emit_insn (gen_add3_insn (dest, tmp1, v1));
2086 case TLS_MODEL_LOCAL_EXEC:
2087 if (Pmode == DImode)
2088 emit_insn (gen_tls_get_tp_di (v1));
2090 emit_insn (gen_tls_get_tp_si (v1));
2092 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2093 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2094 mips_unspec_address (loc, SYMBOL_TPREL));
2104 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2105 be legitimized in a way that the generic machinery might not expect,
2106 put the new address in *XLOC and return true. MODE is the mode of
2107 the memory being accessed. */
2110 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2112 enum mips_symbol_type symbol_type;
2114 if (mips_tls_operand_p (*xloc))
2116 *xloc = mips_legitimize_tls_address (*xloc);
2120 /* See if the address can split into a high part and a LO_SUM. */
2121 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2122 && mips_symbolic_address_p (symbol_type, mode)
2123 && mips_split_p[symbol_type])
2125 *xloc = mips_split_symbol (0, *xloc);
2129 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2131 /* Handle REG + CONSTANT using mips_add_offset. */
2134 reg = XEXP (*xloc, 0);
2135 if (!mips_valid_base_register_p (reg, mode, 0))
2136 reg = copy_to_mode_reg (Pmode, reg);
2137 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2145 /* Subroutine of mips_build_integer (with the same interface).
2146 Assume that the final action in the sequence should be a left shift. */
2149 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2151 unsigned int i, shift;
2153 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2154 since signed numbers are easier to load than unsigned ones. */
2156 while ((value & 1) == 0)
2157 value /= 2, shift++;
2159 i = mips_build_integer (codes, value);
2160 codes[i].code = ASHIFT;
2161 codes[i].value = shift;
2166 /* As for mips_build_shift, but assume that the final action will be
2167 an IOR or PLUS operation. */
2170 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2172 unsigned HOST_WIDE_INT high;
2175 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2176 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2178 /* The constant is too complex to load with a simple lui/ori pair
2179 so our goal is to clear as many trailing zeros as possible.
2180 In this case, we know bit 16 is set and that the low 16 bits
2181 form a negative number. If we subtract that number from VALUE,
2182 we will clear at least the lowest 17 bits, maybe more. */
2183 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2184 codes[i].code = PLUS;
2185 codes[i].value = CONST_LOW_PART (value);
2189 i = mips_build_integer (codes, high);
2190 codes[i].code = IOR;
2191 codes[i].value = value & 0xffff;
2197 /* Fill CODES with a sequence of rtl operations to load VALUE.
2198 Return the number of operations needed. */
2201 mips_build_integer (struct mips_integer_op *codes,
2202 unsigned HOST_WIDE_INT value)
2204 if (SMALL_OPERAND (value)
2205 || SMALL_OPERAND_UNSIGNED (value)
2206 || LUI_OPERAND (value))
2208 /* The value can be loaded with a single instruction. */
2209 codes[0].code = UNKNOWN;
2210 codes[0].value = value;
2213 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2215 /* Either the constant is a simple LUI/ORI combination or its
2216 lowest bit is set. We don't want to shift in this case. */
2217 return mips_build_lower (codes, value);
2219 else if ((value & 0xffff) == 0)
2221 /* The constant will need at least three actions. The lowest
2222 16 bits are clear, so the final action will be a shift. */
2223 return mips_build_shift (codes, value);
2227 /* The final action could be a shift, add or inclusive OR.
2228 Rather than use a complex condition to select the best
2229 approach, try both mips_build_shift and mips_build_lower
2230 and pick the one that gives the shortest sequence.
2231 Note that this case is only used once per constant. */
2232 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2233 unsigned int cost, alt_cost;
2235 cost = mips_build_shift (codes, value);
2236 alt_cost = mips_build_lower (alt_codes, value);
2237 if (alt_cost < cost)
2239 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2247 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2250 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2252 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2253 enum machine_mode mode;
2254 unsigned int i, cost;
2257 mode = GET_MODE (dest);
2258 cost = mips_build_integer (codes, value);
2260 /* Apply each binary operation to X. Invariant: X is a legitimate
2261 source operand for a SET pattern. */
2262 x = GEN_INT (codes[0].value);
2263 for (i = 1; i < cost; i++)
2267 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2271 x = force_reg (mode, x);
2272 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2275 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2279 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2280 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2284 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2287 HOST_WIDE_INT offset;
2289 /* Split moves of big integers into smaller pieces. */
2290 if (splittable_const_int_operand (src, mode))
2292 mips_move_integer (dest, dest, INTVAL (src));
2296 /* Split moves of symbolic constants into high/low pairs. */
2297 if (splittable_symbolic_operand (src, mode))
2299 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2303 if (mips_tls_operand_p (src))
2305 emit_move_insn (dest, mips_legitimize_tls_address (src));
2309 /* If we have (const (plus symbol offset)), load the symbol first
2310 and then add in the offset. This is usually better than forcing
2311 the constant into memory, at least in non-mips16 code. */
2312 mips_split_const (src, &base, &offset);
2315 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2317 base = mips_force_temporary (dest, base);
2318 emit_move_insn (dest, mips_add_offset (0, base, offset));
2322 src = force_const_mem (mode, src);
2324 /* When using explicit relocs, constant pool references are sometimes
2325 not legitimate addresses. */
2326 if (!memory_operand (src, VOIDmode))
2327 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2328 emit_move_insn (dest, src);
2332 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2333 sequence that is valid. */
2336 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2338 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2340 emit_move_insn (dest, force_reg (mode, src));
2344 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2345 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2346 && REG_P (src) && MD_REG_P (REGNO (src))
2347 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2349 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2350 if (GET_MODE_SIZE (mode) <= 4)
2351 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2352 gen_rtx_REG (SImode, REGNO (src)),
2353 gen_rtx_REG (SImode, other_regno)));
2355 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2356 gen_rtx_REG (DImode, REGNO (src)),
2357 gen_rtx_REG (DImode, other_regno)));
2361 /* We need to deal with constants that would be legitimate
2362 immediate_operands but not legitimate move_operands. */
2363 if (CONSTANT_P (src) && !move_operand (src, mode))
2365 mips_legitimize_const_move (mode, dest, src);
2366 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2372 /* We need a lot of little routines to check constant values on the
2373 mips16. These are used to figure out how long the instruction will
2374 be. It would be much better to do this using constraints, but
2375 there aren't nearly enough letters available. */
2378 m16_check_op (rtx op, int low, int high, int mask)
2380 return (GET_CODE (op) == CONST_INT
2381 && INTVAL (op) >= low
2382 && INTVAL (op) <= high
2383 && (INTVAL (op) & mask) == 0);
2387 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2389 return m16_check_op (op, 0x1, 0x8, 0);
2393 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2395 return m16_check_op (op, - 0x8, 0x7, 0);
2399 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2401 return m16_check_op (op, - 0x7, 0x8, 0);
2405 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2407 return m16_check_op (op, - 0x10, 0xf, 0);
2411 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2413 return m16_check_op (op, - 0xf, 0x10, 0);
2417 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2419 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2423 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2425 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2429 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2431 return m16_check_op (op, - 0x80, 0x7f, 0);
2435 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2437 return m16_check_op (op, - 0x7f, 0x80, 0);
2441 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2443 return m16_check_op (op, 0x0, 0xff, 0);
2447 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2449 return m16_check_op (op, - 0xff, 0x0, 0);
2453 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2455 return m16_check_op (op, - 0x1, 0xfe, 0);
2459 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2461 return m16_check_op (op, 0x0, 0xff << 2, 3);
2465 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2467 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2471 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2473 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2477 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2479 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2483 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2485 enum machine_mode mode = GET_MODE (x);
2486 bool float_mode_p = FLOAT_MODE_P (mode);
2493 /* A number between 1 and 8 inclusive is efficient for a shift.
2494 Otherwise, we will need an extended instruction. */
2495 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2496 || (outer_code) == LSHIFTRT)
2498 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2501 *total = COSTS_N_INSNS (1);
2505 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2506 if ((outer_code) == XOR
2507 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2513 /* We may be able to use slt or sltu for a comparison with a
2514 signed 16 bit value. (The boundary conditions aren't quite
2515 right, but this is just a heuristic anyhow.) */
2516 if (((outer_code) == LT || (outer_code) == LE
2517 || (outer_code) == GE || (outer_code) == GT
2518 || (outer_code) == LTU || (outer_code) == LEU
2519 || (outer_code) == GEU || (outer_code) == GTU)
2520 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2526 /* Equality comparisons with 0 are cheap. */
2527 if (((outer_code) == EQ || (outer_code) == NE)
2534 /* Constants in the range 0...255 can be loaded with an unextended
2535 instruction. They are therefore as cheap as a register move.
2537 Given the choice between "li R1,0...255" and "move R1,R2"
2538 (where R2 is a known constant), it is usually better to use "li",
2539 since we do not want to unnecessarily extend the lifetime
2541 if (outer_code == SET
2543 && INTVAL (x) < 256)
2551 /* These can be used anywhere. */
2556 /* Otherwise fall through to the handling below because
2557 we'll need to construct the constant. */
2563 if (LEGITIMATE_CONSTANT_P (x))
2565 *total = COSTS_N_INSNS (1);
2570 /* The value will need to be fetched from the constant pool. */
2571 *total = CONSTANT_POOL_COST;
2577 /* If the address is legitimate, return the number of
2578 instructions it needs, otherwise use the default handling. */
2579 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2582 *total = COSTS_N_INSNS (n + 1);
2589 *total = COSTS_N_INSNS (6);
2593 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2599 if (mode == DImode && !TARGET_64BIT)
2601 *total = COSTS_N_INSNS (2);
2609 if (mode == DImode && !TARGET_64BIT)
2611 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2619 *total = COSTS_N_INSNS (1);
2621 *total = COSTS_N_INSNS (4);
2625 *total = COSTS_N_INSNS (1);
2632 *total = mips_cost->fp_add;
2636 else if (mode == DImode && !TARGET_64BIT)
2638 *total = COSTS_N_INSNS (4);
2644 if (mode == DImode && !TARGET_64BIT)
2646 *total = COSTS_N_INSNS (4);
2653 *total = mips_cost->fp_mult_sf;
2655 else if (mode == DFmode)
2656 *total = mips_cost->fp_mult_df;
2658 else if (mode == SImode)
2659 *total = mips_cost->int_mult_si;
2662 *total = mips_cost->int_mult_di;
2671 *total = mips_cost->fp_div_sf;
2673 *total = mips_cost->fp_div_df;
2682 *total = mips_cost->int_div_di;
2684 *total = mips_cost->int_div_si;
2689 /* A sign extend from SImode to DImode in 64 bit mode is often
2690 zero instructions, because the result can often be used
2691 directly by another instruction; we'll call it one. */
2692 if (TARGET_64BIT && mode == DImode
2693 && GET_MODE (XEXP (x, 0)) == SImode)
2694 *total = COSTS_N_INSNS (1);
2696 *total = COSTS_N_INSNS (2);
2700 if (TARGET_64BIT && mode == DImode
2701 && GET_MODE (XEXP (x, 0)) == SImode)
2702 *total = COSTS_N_INSNS (2);
2704 *total = COSTS_N_INSNS (1);
2708 case UNSIGNED_FLOAT:
2711 case FLOAT_TRUNCATE:
2713 *total = mips_cost->fp_add;
2721 /* Provide the costs of an addressing mode that contains ADDR.
2722 If ADDR is not a valid address, its cost is irrelevant. */
2725 mips_address_cost (rtx addr)
2727 return mips_address_insns (addr, SImode);
2730 /* Return one word of double-word value OP, taking into account the fixed
2731 endianness of certain registers. HIGH_P is true to select the high part,
2732 false to select the low part. */
2735 mips_subword (rtx op, int high_p)
2738 enum machine_mode mode;
2740 mode = GET_MODE (op);
2741 if (mode == VOIDmode)
2744 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2745 byte = UNITS_PER_WORD;
2751 if (FP_REG_P (REGNO (op)))
2752 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2753 if (ACC_HI_REG_P (REGNO (op)))
2754 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2758 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2760 return simplify_gen_subreg (word_mode, op, mode, byte);
2764 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2767 mips_split_64bit_move_p (rtx dest, rtx src)
2772 /* FP->FP moves can be done in a single instruction. */
2773 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2776 /* Check for floating-point loads and stores. They can be done using
2777 ldc1 and sdc1 on MIPS II and above. */
2780 if (FP_REG_RTX_P (dest) && MEM_P (src))
2782 if (FP_REG_RTX_P (src) && MEM_P (dest))
2789 /* Split a 64-bit move from SRC to DEST assuming that
2790 mips_split_64bit_move_p holds.
2792 Moves into and out of FPRs cause some difficulty here. Such moves
2793 will always be DFmode, since paired FPRs are not allowed to store
2794 DImode values. The most natural representation would be two separate
2795 32-bit moves, such as:
2797 (set (reg:SI $f0) (mem:SI ...))
2798 (set (reg:SI $f1) (mem:SI ...))
2800 However, the second insn is invalid because odd-numbered FPRs are
2801 not allowed to store independent values. Use the patterns load_df_low,
2802 load_df_high and store_df_high instead. */
2805 mips_split_64bit_move (rtx dest, rtx src)
2807 if (FP_REG_RTX_P (dest))
2809 /* Loading an FPR from memory or from GPRs. */
2810 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2811 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2814 else if (FP_REG_RTX_P (src))
2816 /* Storing an FPR into memory or GPRs. */
2817 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2818 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2822 /* The operation can be split into two normal moves. Decide in
2823 which order to do them. */
2826 low_dest = mips_subword (dest, 0);
2827 if (REG_P (low_dest)
2828 && reg_overlap_mentioned_p (low_dest, src))
2830 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2831 emit_move_insn (low_dest, mips_subword (src, 0));
2835 emit_move_insn (low_dest, mips_subword (src, 0));
2836 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2841 /* Return the appropriate instructions to move SRC into DEST. Assume
2842 that SRC is operand 1 and DEST is operand 0. */
2845 mips_output_move (rtx dest, rtx src)
2847 enum rtx_code dest_code, src_code;
2850 dest_code = GET_CODE (dest);
2851 src_code = GET_CODE (src);
2852 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2854 if (dbl_p && mips_split_64bit_move_p (dest, src))
2857 if ((src_code == REG && GP_REG_P (REGNO (src)))
2858 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2860 if (dest_code == REG)
2862 if (GP_REG_P (REGNO (dest)))
2863 return "move\t%0,%z1";
2865 if (MD_REG_P (REGNO (dest)))
2868 if (DSP_ACC_REG_P (REGNO (dest)))
2870 static char retval[] = "mt__\t%z1,%q0";
2871 retval[2] = reg_names[REGNO (dest)][4];
2872 retval[3] = reg_names[REGNO (dest)][5];
2876 if (FP_REG_P (REGNO (dest)))
2877 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2879 if (ALL_COP_REG_P (REGNO (dest)))
2881 static char retval[] = "dmtc_\t%z1,%0";
2883 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2884 return (dbl_p ? retval : retval + 1);
2887 if (dest_code == MEM)
2888 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2890 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2892 if (src_code == REG)
2894 if (DSP_ACC_REG_P (REGNO (src)))
2896 static char retval[] = "mf__\t%0,%q1";
2897 retval[2] = reg_names[REGNO (src)][4];
2898 retval[3] = reg_names[REGNO (src)][5];
2902 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2903 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2905 if (FP_REG_P (REGNO (src)))
2906 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2908 if (ALL_COP_REG_P (REGNO (src)))
2910 static char retval[] = "dmfc_\t%0,%1";
2912 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2913 return (dbl_p ? retval : retval + 1);
2917 if (src_code == MEM)
2918 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2920 if (src_code == CONST_INT)
2922 /* Don't use the X format, because that will give out of
2923 range numbers for 64 bit hosts and 32 bit targets. */
2925 return "li\t%0,%1\t\t\t# %X1";
2927 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2930 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2934 if (src_code == HIGH)
2935 return "lui\t%0,%h1";
2937 if (CONST_GP_P (src))
2938 return "move\t%0,%1";
2940 if (symbolic_operand (src, VOIDmode))
2941 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2943 if (src_code == REG && FP_REG_P (REGNO (src)))
2945 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2947 if (GET_MODE (dest) == V2SFmode)
2948 return "mov.ps\t%0,%1";
2950 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2953 if (dest_code == MEM)
2954 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2956 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2958 if (src_code == MEM)
2959 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2961 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2963 static char retval[] = "l_c_\t%0,%1";
2965 retval[1] = (dbl_p ? 'd' : 'w');
2966 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2969 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2971 static char retval[] = "s_c_\t%1,%0";
2973 retval[1] = (dbl_p ? 'd' : 'w');
2974 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2980 /* Restore $gp from its save slot. Valid only when using o32 or
2984 mips_restore_gp (void)
2988 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2990 address = mips_add_offset (pic_offset_table_rtx,
2991 frame_pointer_needed
2992 ? hard_frame_pointer_rtx
2993 : stack_pointer_rtx,
2994 current_function_outgoing_args_size);
2995 slot = gen_rtx_MEM (Pmode, address);
2997 emit_move_insn (pic_offset_table_rtx, slot);
2998 if (!TARGET_EXPLICIT_RELOCS)
2999 emit_insn (gen_blockage ());
3002 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3005 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3007 emit_insn (gen_rtx_SET (VOIDmode, target,
3008 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3011 /* Return true if CMP1 is a suitable second operand for relational
3012 operator CODE. See also the *sCC patterns in mips.md. */
3015 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3021 return reg_or_0_operand (cmp1, VOIDmode);
3025 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3029 return arith_operand (cmp1, VOIDmode);
3032 return sle_operand (cmp1, VOIDmode);
3035 return sleu_operand (cmp1, VOIDmode);
3042 /* Canonicalize LE or LEU comparisons into LT comparisons when
3043 possible to avoid extra instructions or inverting the
3047 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3048 enum machine_mode mode)
3050 HOST_WIDE_INT original, plus_one;
3052 if (GET_CODE (*cmp1) != CONST_INT)
3055 original = INTVAL (*cmp1);
3056 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3061 if (original < plus_one)
3064 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3073 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3086 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3087 result in TARGET. CMP0 and TARGET are register_operands that have
3088 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3089 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3092 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3093 rtx target, rtx cmp0, rtx cmp1)
3095 /* First see if there is a MIPS instruction that can do this operation
3096 with CMP1 in its current form. If not, try to canonicalize the
3097 comparison to LT. If that fails, try doing the same for the
3098 inverse operation. If that also fails, force CMP1 into a register
3100 if (mips_relational_operand_ok_p (code, cmp1))
3101 mips_emit_binary (code, target, cmp0, cmp1);
3102 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3103 mips_emit_binary (code, target, cmp0, cmp1);
3106 enum rtx_code inv_code = reverse_condition (code);
3107 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3109 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3110 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3112 else if (invert_ptr == 0)
3114 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3115 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3116 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3120 *invert_ptr = !*invert_ptr;
3121 mips_emit_binary (inv_code, target, cmp0, cmp1);
3126 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3127 The register will have the same mode as CMP0. */
3130 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3132 if (cmp1 == const0_rtx)
3135 if (uns_arith_operand (cmp1, VOIDmode))
3136 return expand_binop (GET_MODE (cmp0), xor_optab,
3137 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3139 return expand_binop (GET_MODE (cmp0), sub_optab,
3140 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3143 /* Convert *CODE into a code that can be used in a floating-point
3144 scc instruction (c.<cond>.<fmt>). Return true if the values of
3145 the condition code registers will be inverted, with 0 indicating
3146 that the condition holds. */
3149 mips_reverse_fp_cond_p (enum rtx_code *code)
3156 *code = reverse_condition_maybe_unordered (*code);
3164 /* Convert a comparison into something that can be used in a branch or
3165 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3166 being compared and *CODE is the code used to compare them.
3168 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3169 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3170 otherwise any standard branch condition can be used. The standard branch
3173 - EQ/NE between two registers.
3174 - any comparison between a register and zero. */
3177 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3179 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3181 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3183 *op0 = cmp_operands[0];
3184 *op1 = cmp_operands[1];
3186 else if (*code == EQ || *code == NE)
3190 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3195 *op0 = cmp_operands[0];
3196 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3201 /* The comparison needs a separate scc instruction. Store the
3202 result of the scc in *OP0 and compare it against zero. */
3203 bool invert = false;
3204 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3206 mips_emit_int_relational (*code, &invert, *op0,
3207 cmp_operands[0], cmp_operands[1]);
3208 *code = (invert ? EQ : NE);
3213 enum rtx_code cmp_code;
3215 /* Floating-point tests use a separate c.cond.fmt comparison to
3216 set a condition code register. The branch or conditional move
3217 will then compare that register against zero.
3219 Set CMP_CODE to the code of the comparison instruction and
3220 *CODE to the code that the branch or move should use. */
3222 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3224 ? gen_reg_rtx (CCmode)
3225 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3227 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3231 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3232 Store the result in TARGET and return true if successful.
3234 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3237 mips_emit_scc (enum rtx_code code, rtx target)
3239 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3242 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3243 if (code == EQ || code == NE)
3245 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3246 mips_emit_binary (code, target, zie, const0_rtx);
3249 mips_emit_int_relational (code, 0, target,
3250 cmp_operands[0], cmp_operands[1]);
3254 /* Emit the common code for doing conditional branches.
3255 operand[0] is the label to jump to.
3256 The comparison operands are saved away by cmp{si,di,sf,df}. */
3259 gen_conditional_branch (rtx *operands, enum rtx_code code)
3261 rtx op0, op1, condition;
3263 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3264 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3265 emit_jump_insn (gen_condjump (condition, operands[0]));
3270 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3271 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3274 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3275 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3280 reversed_p = mips_reverse_fp_cond_p (&cond);
3281 cmp_result = gen_reg_rtx (CCV2mode);
3282 emit_insn (gen_scc_ps (cmp_result,
3283 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3285 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3288 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3292 /* Emit the common code for conditional moves. OPERANDS is the array
3293 of operands passed to the conditional move define_expand. */
3296 gen_conditional_move (rtx *operands)
3301 code = GET_CODE (operands[1]);
3302 mips_emit_compare (&code, &op0, &op1, true);
3303 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3304 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3305 gen_rtx_fmt_ee (code,
3308 operands[2], operands[3])));
3311 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3312 the conditional_trap expander. */
3315 mips_gen_conditional_trap (rtx *operands)
3318 enum rtx_code cmp_code = GET_CODE (operands[0]);
3319 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3321 /* MIPS conditional trap machine instructions don't have GT or LE
3322 flavors, so we must invert the comparison and convert to LT and
3323 GE, respectively. */
3326 case GT: cmp_code = LT; break;
3327 case LE: cmp_code = GE; break;
3328 case GTU: cmp_code = LTU; break;
3329 case LEU: cmp_code = GEU; break;
3332 if (cmp_code == GET_CODE (operands[0]))
3334 op0 = cmp_operands[0];
3335 op1 = cmp_operands[1];
3339 op0 = cmp_operands[1];
3340 op1 = cmp_operands[0];
3342 op0 = force_reg (mode, op0);
3343 if (!arith_operand (op1, mode))
3344 op1 = force_reg (mode, op1);
3346 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3347 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3351 /* Load function address ADDR into register DEST. SIBCALL_P is true
3352 if the address is needed for a sibling call. */
3355 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3357 /* If we're generating PIC, and this call is to a global function,
3358 try to allow its address to be resolved lazily. This isn't
3359 possible for NewABI sibcalls since the value of $gp on entry
3360 to the stub would be our caller's gp, not ours. */
3361 if (TARGET_EXPLICIT_RELOCS
3362 && !(sibcall_p && TARGET_NEWABI)
3363 && global_got_operand (addr, VOIDmode))
3365 rtx high, lo_sum_symbol;
3367 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3368 addr, SYMBOL_GOTOFF_CALL);
3369 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3370 if (Pmode == SImode)
3371 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3373 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3376 emit_move_insn (dest, addr);
3380 /* Expand a call or call_value instruction. RESULT is where the
3381 result will go (null for calls), ADDR is the address of the
3382 function, ARGS_SIZE is the size of the arguments and AUX is
3383 the value passed to us by mips_function_arg. SIBCALL_P is true
3384 if we are expanding a sibling call, false if we're expanding
3388 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3390 rtx orig_addr, pattern, insn;
3393 if (!call_insn_operand (addr, VOIDmode))
3395 addr = gen_reg_rtx (Pmode);
3396 mips_load_call_address (addr, orig_addr, sibcall_p);
3400 && mips16_hard_float
3401 && build_mips16_call_stub (result, addr, args_size,
3402 aux == 0 ? 0 : (int) GET_MODE (aux)))
3406 pattern = (sibcall_p
3407 ? gen_sibcall_internal (addr, args_size)
3408 : gen_call_internal (addr, args_size));
3409 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3413 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3414 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3417 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3418 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3421 pattern = (sibcall_p
3422 ? gen_sibcall_value_internal (result, addr, args_size)
3423 : gen_call_value_internal (result, addr, args_size));
3425 insn = emit_call_insn (pattern);
3427 /* Lazy-binding stubs require $gp to be valid on entry. */
3428 if (global_got_operand (orig_addr, VOIDmode))
3429 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3433 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3436 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3437 tree exp ATTRIBUTE_UNUSED)
3439 return TARGET_SIBCALLS;
3442 /* Emit code to move general operand SRC into condition-code
3443 register DEST. SCRATCH is a scratch TFmode float register.
3450 where FP1 and FP2 are single-precision float registers
3451 taken from SCRATCH. */
3454 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3458 /* Change the source to SFmode. */
3460 src = adjust_address (src, SFmode, 0);
3461 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3462 src = gen_rtx_REG (SFmode, true_regnum (src));
3464 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3465 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3467 emit_move_insn (copy_rtx (fp1), src);
3468 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3469 emit_insn (gen_slt_sf (dest, fp2, fp1));
3472 /* Emit code to change the current function's return address to
3473 ADDRESS. SCRATCH is available as a scratch register, if needed.
3474 ADDRESS and SCRATCH are both word-mode GPRs. */
3477 mips_set_return_address (rtx address, rtx scratch)
3481 compute_frame_size (get_frame_size ());
3482 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3483 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3484 cfun->machine->frame.gp_sp_offset);
3486 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3489 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3490 Assume that the areas do not overlap. */
3493 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3495 HOST_WIDE_INT offset, delta;
3496 unsigned HOST_WIDE_INT bits;
3498 enum machine_mode mode;
3501 /* Work out how many bits to move at a time. If both operands have
3502 half-word alignment, it is usually better to move in half words.
3503 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3504 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3505 Otherwise move word-sized chunks. */
3506 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3507 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3508 bits = BITS_PER_WORD / 2;
3510 bits = BITS_PER_WORD;
3512 mode = mode_for_size (bits, MODE_INT, 0);
3513 delta = bits / BITS_PER_UNIT;
3515 /* Allocate a buffer for the temporary registers. */
3516 regs = alloca (sizeof (rtx) * length / delta);
3518 /* Load as many BITS-sized chunks as possible. Use a normal load if
3519 the source has enough alignment, otherwise use left/right pairs. */
3520 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3522 regs[i] = gen_reg_rtx (mode);
3523 if (MEM_ALIGN (src) >= bits)
3524 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3527 rtx part = adjust_address (src, BLKmode, offset);
3528 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3533 /* Copy the chunks to the destination. */
3534 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3535 if (MEM_ALIGN (dest) >= bits)
3536 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3539 rtx part = adjust_address (dest, BLKmode, offset);
3540 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3544 /* Mop up any left-over bytes. */
3545 if (offset < length)
3547 src = adjust_address (src, BLKmode, offset);
3548 dest = adjust_address (dest, BLKmode, offset);
3549 move_by_pieces (dest, src, length - offset,
3550 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3554 #define MAX_MOVE_REGS 4
3555 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3558 /* Helper function for doing a loop-based block operation on memory
3559 reference MEM. Each iteration of the loop will operate on LENGTH
3562 Create a new base register for use within the loop and point it to
3563 the start of MEM. Create a new memory reference that uses this
3564 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3567 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3568 rtx *loop_reg, rtx *loop_mem)
3570 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3572 /* Although the new mem does not refer to a known location,
3573 it does keep up to LENGTH bytes of alignment. */
3574 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3575 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3579 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3580 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3581 memory regions do not overlap. */
3584 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3586 rtx label, src_reg, dest_reg, final_src;
3587 HOST_WIDE_INT leftover;
3589 leftover = length % MAX_MOVE_BYTES;
3592 /* Create registers and memory references for use within the loop. */
3593 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3594 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3596 /* Calculate the value that SRC_REG should have after the last iteration
3598 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3601 /* Emit the start of the loop. */
3602 label = gen_label_rtx ();
3605 /* Emit the loop body. */
3606 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3608 /* Move on to the next block. */
3609 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3610 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3612 /* Emit the loop condition. */
3613 if (Pmode == DImode)
3614 emit_insn (gen_cmpdi (src_reg, final_src));
3616 emit_insn (gen_cmpsi (src_reg, final_src));
3617 emit_jump_insn (gen_bne (label));
3619 /* Mop up any left-over bytes. */
3621 mips_block_move_straight (dest, src, leftover);
3624 /* Expand a movmemsi instruction. */
3627 mips_expand_block_move (rtx dest, rtx src, rtx length)
3629 if (GET_CODE (length) == CONST_INT)
3631 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3633 mips_block_move_straight (dest, src, INTVAL (length));
3638 mips_block_move_loop (dest, src, INTVAL (length));
3645 /* Argument support functions. */
3647 /* Initialize CUMULATIVE_ARGS for a function. */
3650 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3651 rtx libname ATTRIBUTE_UNUSED)
3653 static CUMULATIVE_ARGS zero_cum;
3654 tree param, next_param;
3657 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3659 /* Determine if this function has variable arguments. This is
3660 indicated by the last argument being 'void_type_mode' if there
3661 are no variable arguments. The standard MIPS calling sequence
3662 passes all arguments in the general purpose registers in this case. */
3664 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3665 param != 0; param = next_param)
3667 next_param = TREE_CHAIN (param);
3668 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3669 cum->gp_reg_found = 1;
3674 /* Fill INFO with information about a single argument. CUM is the
3675 cumulative state for earlier arguments. MODE is the mode of this
3676 argument and TYPE is its type (if known). NAMED is true if this
3677 is a named (fixed) argument rather than a variable one. */
3680 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3681 tree type, int named, struct mips_arg_info *info)
3683 bool doubleword_aligned_p;
3684 unsigned int num_bytes, num_words, max_regs;
3686 /* Work out the size of the argument. */
3687 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3688 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3690 /* Decide whether it should go in a floating-point register, assuming
3691 one is free. Later code checks for availability.
3693 The checks against UNITS_PER_FPVALUE handle the soft-float and
3694 single-float cases. */
3698 /* The EABI conventions have traditionally been defined in terms
3699 of TYPE_MODE, regardless of the actual type. */
3700 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3701 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3702 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3707 /* Only leading floating-point scalars are passed in
3708 floating-point registers. We also handle vector floats the same
3709 say, which is OK because they are not covered by the standard ABI. */
3710 info->fpr_p = (!cum->gp_reg_found
3711 && cum->arg_number < 2
3712 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3713 || VECTOR_FLOAT_TYPE_P (type))
3714 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3715 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3716 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3721 /* Scalar and complex floating-point types are passed in
3722 floating-point registers. */
3723 info->fpr_p = (named
3724 && (type == 0 || FLOAT_TYPE_P (type))
3725 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3726 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3727 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3728 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3730 /* ??? According to the ABI documentation, the real and imaginary
3731 parts of complex floats should be passed in individual registers.
3732 The real and imaginary parts of stack arguments are supposed
3733 to be contiguous and there should be an extra word of padding
3736 This has two problems. First, it makes it impossible to use a
3737 single "void *" va_list type, since register and stack arguments
3738 are passed differently. (At the time of writing, MIPSpro cannot
3739 handle complex float varargs correctly.) Second, it's unclear
3740 what should happen when there is only one register free.
3742 For now, we assume that named complex floats should go into FPRs
3743 if there are two FPRs free, otherwise they should be passed in the
3744 same way as a struct containing two floats. */
3746 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3747 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3749 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3750 info->fpr_p = false;
3760 /* See whether the argument has doubleword alignment. */
3761 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3763 /* Set REG_OFFSET to the register count we're interested in.
3764 The EABI allocates the floating-point registers separately,
3765 but the other ABIs allocate them like integer registers. */
3766 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3770 /* Advance to an even register if the argument is doubleword-aligned. */
3771 if (doubleword_aligned_p)
3772 info->reg_offset += info->reg_offset & 1;
3774 /* Work out the offset of a stack argument. */
3775 info->stack_offset = cum->stack_words;
3776 if (doubleword_aligned_p)
3777 info->stack_offset += info->stack_offset & 1;
3779 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3781 /* Partition the argument between registers and stack. */
3782 info->reg_words = MIN (num_words, max_regs);
3783 info->stack_words = num_words - info->reg_words;
3787 /* Implement FUNCTION_ARG_ADVANCE. */
3790 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3791 tree type, int named)
3793 struct mips_arg_info info;
3795 mips_arg_info (cum, mode, type, named, &info);
3798 cum->gp_reg_found = true;
3800 /* See the comment above the cumulative args structure in mips.h
3801 for an explanation of what this code does. It assumes the O32
3802 ABI, which passes at most 2 arguments in float registers. */
3803 if (cum->arg_number < 2 && info.fpr_p)
3804 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3806 if (mips_abi != ABI_EABI || !info.fpr_p)
3807 cum->num_gprs = info.reg_offset + info.reg_words;
3808 else if (info.reg_words > 0)
3809 cum->num_fprs += FP_INC;
3811 if (info.stack_words > 0)
3812 cum->stack_words = info.stack_offset + info.stack_words;
3817 /* Implement FUNCTION_ARG. */
3820 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3821 tree type, int named)
3823 struct mips_arg_info info;
3825 /* We will be called with a mode of VOIDmode after the last argument
3826 has been seen. Whatever we return will be passed to the call
3827 insn. If we need a mips16 fp_code, return a REG with the code
3828 stored as the mode. */
3829 if (mode == VOIDmode)
3831 if (TARGET_MIPS16 && cum->fp_code != 0)
3832 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3838 mips_arg_info (cum, mode, type, named, &info);
3840 /* Return straight away if the whole argument is passed on the stack. */
3841 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3845 && TREE_CODE (type) == RECORD_TYPE
3847 && TYPE_SIZE_UNIT (type)
3848 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3851 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3852 structure contains a double in its entirety, then that 64 bit
3853 chunk is passed in a floating point register. */
3856 /* First check to see if there is any such field. */
3857 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3858 if (TREE_CODE (field) == FIELD_DECL
3859 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3860 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3861 && host_integerp (bit_position (field), 0)
3862 && int_bit_position (field) % BITS_PER_WORD == 0)
3867 /* Now handle the special case by returning a PARALLEL
3868 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3869 chunks are passed in registers. */
3871 HOST_WIDE_INT bitpos;
3874 /* assign_parms checks the mode of ENTRY_PARM, so we must
3875 use the actual mode here. */
3876 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3879 field = TYPE_FIELDS (type);
3880 for (i = 0; i < info.reg_words; i++)
3884 for (; field; field = TREE_CHAIN (field))
3885 if (TREE_CODE (field) == FIELD_DECL
3886 && int_bit_position (field) >= bitpos)
3890 && int_bit_position (field) == bitpos
3891 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3892 && !TARGET_SOFT_FLOAT
3893 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3894 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3896 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3899 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3900 GEN_INT (bitpos / BITS_PER_UNIT));
3902 bitpos += BITS_PER_WORD;
3908 /* Handle the n32/n64 conventions for passing complex floating-point
3909 arguments in FPR pairs. The real part goes in the lower register
3910 and the imaginary part goes in the upper register. */
3913 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3916 enum machine_mode inner;
3919 inner = GET_MODE_INNER (mode);
3920 reg = FP_ARG_FIRST + info.reg_offset;
3921 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
3923 /* Real part in registers, imaginary part on stack. */
3924 gcc_assert (info.stack_words == info.reg_words);
3925 return gen_rtx_REG (inner, reg);
3929 gcc_assert (info.stack_words == 0);
3930 real = gen_rtx_EXPR_LIST (VOIDmode,
3931 gen_rtx_REG (inner, reg),
3933 imag = gen_rtx_EXPR_LIST (VOIDmode,
3935 reg + info.reg_words / 2),
3936 GEN_INT (GET_MODE_SIZE (inner)));
3937 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3942 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3943 else if (info.reg_offset == 1)
3944 /* This code handles the special o32 case in which the second word
3945 of the argument structure is passed in floating-point registers. */
3946 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3948 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3952 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3955 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3956 enum machine_mode mode, tree type, bool named)
3958 struct mips_arg_info info;
3960 mips_arg_info (cum, mode, type, named, &info);
3961 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3965 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3966 PARM_BOUNDARY bits of alignment, but will be given anything up
3967 to STACK_BOUNDARY bits if the type requires it. */
3970 function_arg_boundary (enum machine_mode mode, tree type)
3972 unsigned int alignment;
3974 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3975 if (alignment < PARM_BOUNDARY)
3976 alignment = PARM_BOUNDARY;
3977 if (alignment > STACK_BOUNDARY)
3978 alignment = STACK_BOUNDARY;
3982 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3983 upward rather than downward. In other words, return true if the
3984 first byte of the stack slot has useful data, false if the last
3988 mips_pad_arg_upward (enum machine_mode mode, tree type)
3990 /* On little-endian targets, the first byte of every stack argument
3991 is passed in the first byte of the stack slot. */
3992 if (!BYTES_BIG_ENDIAN)
3995 /* Otherwise, integral types are padded downward: the last byte of a
3996 stack argument is passed in the last byte of the stack slot. */
3998 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3999 : GET_MODE_CLASS (mode) == MODE_INT)
4002 /* Big-endian o64 pads floating-point arguments downward. */
4003 if (mips_abi == ABI_O64)
4004 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4007 /* Other types are padded upward for o32, o64, n32 and n64. */
4008 if (mips_abi != ABI_EABI)
4011 /* Arguments smaller than a stack slot are padded downward. */
4012 if (mode != BLKmode)
4013 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4015 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4019 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4020 if the least significant byte of the register has useful data. Return
4021 the opposite if the most significant byte does. */
4024 mips_pad_reg_upward (enum machine_mode mode, tree type)
4026 /* No shifting is required for floating-point arguments. */
4027 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4028 return !BYTES_BIG_ENDIAN;
4030 /* Otherwise, apply the same padding to register arguments as we do
4031 to stack arguments. */
4032 return mips_pad_arg_upward (mode, type);
4036 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4037 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4040 CUMULATIVE_ARGS local_cum;
4041 int gp_saved, fp_saved;
4043 /* The caller has advanced CUM up to, but not beyond, the last named
4044 argument. Advance a local copy of CUM past the last "real" named
4045 argument, to find out how many registers are left over. */
4048 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4050 /* Found out how many registers we need to save. */
4051 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4052 fp_saved = (EABI_FLOAT_VARARGS_P
4053 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4062 ptr = plus_constant (virtual_incoming_args_rtx,
4063 REG_PARM_STACK_SPACE (cfun->decl)
4064 - gp_saved * UNITS_PER_WORD);
4065 mem = gen_rtx_MEM (BLKmode, ptr);
4066 set_mem_alias_set (mem, get_varargs_alias_set ());
4068 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4073 /* We can't use move_block_from_reg, because it will use
4075 enum machine_mode mode;
4078 /* Set OFF to the offset from virtual_incoming_args_rtx of
4079 the first float register. The FP save area lies below
4080 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4081 off = -gp_saved * UNITS_PER_WORD;
4082 off &= ~(UNITS_PER_FPVALUE - 1);
4083 off -= fp_saved * UNITS_PER_FPREG;
4085 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4087 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4091 ptr = plus_constant (virtual_incoming_args_rtx, off);
4092 mem = gen_rtx_MEM (mode, ptr);
4093 set_mem_alias_set (mem, get_varargs_alias_set ());
4094 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4095 off += UNITS_PER_HWFPVALUE;
4099 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4100 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4101 + fp_saved * UNITS_PER_FPREG);
4104 /* Create the va_list data type.
4105 We keep 3 pointers, and two offsets.
4106 Two pointers are to the overflow area, which starts at the CFA.
4107 One of these is constant, for addressing into the GPR save area below it.
4108 The other is advanced up the stack through the overflow region.
4109 The third pointer is to the GPR save area. Since the FPR save area
4110 is just below it, we can address FPR slots off this pointer.
4111 We also keep two one-byte offsets, which are to be subtracted from the
4112 constant pointers to yield addresses in the GPR and FPR save areas.
4113 These are downcounted as float or non-float arguments are used,
4114 and when they get to zero, the argument must be obtained from the
4116 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4117 pointer is enough. It's started at the GPR save area, and is
4119 Note that the GPR save area is not constant size, due to optimization
4120 in the prologue. Hence, we can't use a design with two pointers
4121 and two offsets, although we could have designed this with two pointers
4122 and three offsets. */
4125 mips_build_builtin_va_list (void)
4127 if (EABI_FLOAT_VARARGS_P)
4129 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4132 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4134 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4136 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4138 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4140 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4141 unsigned_char_type_node);
4142 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4143 unsigned_char_type_node);
4144 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4145 warn on every user file. */
4146 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4147 array = build_array_type (unsigned_char_type_node,
4148 build_index_type (index));
4149 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4151 DECL_FIELD_CONTEXT (f_ovfl) = record;
4152 DECL_FIELD_CONTEXT (f_gtop) = record;
4153 DECL_FIELD_CONTEXT (f_ftop) = record;
4154 DECL_FIELD_CONTEXT (f_goff) = record;
4155 DECL_FIELD_CONTEXT (f_foff) = record;
4156 DECL_FIELD_CONTEXT (f_res) = record;
4158 TYPE_FIELDS (record) = f_ovfl;
4159 TREE_CHAIN (f_ovfl) = f_gtop;
4160 TREE_CHAIN (f_gtop) = f_ftop;
4161 TREE_CHAIN (f_ftop) = f_goff;
4162 TREE_CHAIN (f_goff) = f_foff;
4163 TREE_CHAIN (f_foff) = f_res;
4165 layout_type (record);
4168 else if (TARGET_IRIX && TARGET_IRIX6)
4169 /* On IRIX 6, this type is 'char *'. */
4170 return build_pointer_type (char_type_node);
4172 /* Otherwise, we use 'void *'. */
4173 return ptr_type_node;
4176 /* Implement va_start. */
4179 mips_va_start (tree valist, rtx nextarg)
4181 if (EABI_FLOAT_VARARGS_P)
4183 const CUMULATIVE_ARGS *cum;
4184 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4185 tree ovfl, gtop, ftop, goff, foff;
4187 int gpr_save_area_size;
4188 int fpr_save_area_size;
4191 cum = ¤t_function_args_info;
4193 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4195 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4197 f_ovfl = TYPE_FIELDS (va_list_type_node);
4198 f_gtop = TREE_CHAIN (f_ovfl);
4199 f_ftop = TREE_CHAIN (f_gtop);
4200 f_goff = TREE_CHAIN (f_ftop);
4201 f_foff = TREE_CHAIN (f_goff);
4203 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4205 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4207 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4209 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4211 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4214 /* Emit code to initialize OVFL, which points to the next varargs
4215 stack argument. CUM->STACK_WORDS gives the number of stack
4216 words used by named arguments. */
4217 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4218 if (cum->stack_words > 0)
4219 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4220 build_int_cst (NULL_TREE,
4221 cum->stack_words * UNITS_PER_WORD));
4222 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4223 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4225 /* Emit code to initialize GTOP, the top of the GPR save area. */
4226 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4227 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4228 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4230 /* Emit code to initialize FTOP, the top of the FPR save area.
4231 This address is gpr_save_area_bytes below GTOP, rounded
4232 down to the next fp-aligned boundary. */
4233 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4234 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4235 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4237 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4238 build_int_cst (NULL_TREE, -fpr_offset));
4239 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4240 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4242 /* Emit code to initialize GOFF, the offset from GTOP of the
4243 next GPR argument. */
4244 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
4245 build_int_cst (NULL_TREE, gpr_save_area_size));
4246 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4248 /* Likewise emit code to initialize FOFF, the offset from FTOP
4249 of the next FPR argument. */
4250 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
4251 build_int_cst (NULL_TREE, fpr_save_area_size));
4252 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4256 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4257 std_expand_builtin_va_start (valist, nextarg);
4261 /* Implement va_arg. */
4264 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4266 HOST_WIDE_INT size, rsize;
4270 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4273 type = build_pointer_type (type);
4275 size = int_size_in_bytes (type);
4276 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4278 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4279 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4282 /* Not a simple merged stack. */
4284 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4285 tree ovfl, top, off, align;
4286 HOST_WIDE_INT osize;
4289 f_ovfl = TYPE_FIELDS (va_list_type_node);
4290 f_gtop = TREE_CHAIN (f_ovfl);
4291 f_ftop = TREE_CHAIN (f_gtop);
4292 f_goff = TREE_CHAIN (f_ftop);
4293 f_foff = TREE_CHAIN (f_goff);
4295 /* We maintain separate pointers and offsets for floating-point
4296 and integer arguments, but we need similar code in both cases.
4299 TOP be the top of the register save area;
4300 OFF be the offset from TOP of the next register;
4301 ADDR_RTX be the address of the argument;
4302 RSIZE be the number of bytes used to store the argument
4303 when it's in the register save area;
4304 OSIZE be the number of bytes used to store it when it's
4305 in the stack overflow area; and
4306 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4308 The code we want is:
4310 1: off &= -rsize; // round down
4313 4: addr_rtx = top - off;
4318 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4319 10: addr_rtx = ovfl + PADDING;
4323 [1] and [9] can sometimes be optimized away. */
4325 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4328 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4329 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4331 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4333 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4336 /* When floating-point registers are saved to the stack,
4337 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4338 of the float's precision. */
4339 rsize = UNITS_PER_HWFPVALUE;
4341 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4342 (= PARM_BOUNDARY bits). This can be different from RSIZE
4345 (1) On 32-bit targets when TYPE is a structure such as:
4347 struct s { float f; };
4349 Such structures are passed in paired FPRs, so RSIZE
4350 will be 8 bytes. However, the structure only takes
4351 up 4 bytes of memory, so OSIZE will only be 4.
4353 (2) In combinations such as -mgp64 -msingle-float
4354 -fshort-double. Doubles passed in registers
4355 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4356 but those passed on the stack take up
4357 UNITS_PER_WORD bytes. */
4358 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4362 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4364 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4366 if (rsize > UNITS_PER_WORD)
4368 /* [1] Emit code for: off &= -rsize. */
4369 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4370 build_int_cst (NULL_TREE, -rsize));
4371 t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t);
4372 gimplify_and_add (t, pre_p);
4377 /* [2] Emit code to branch if off == 0. */
4378 t = build2 (NE_EXPR, boolean_type_node, off,
4379 build_int_cst (TREE_TYPE (off), 0));
4380 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4382 /* [5] Emit code for: off -= rsize. We do this as a form of
4383 post-increment not available to C. Also widen for the
4384 coming pointer arithmetic. */
4385 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4386 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4387 t = fold_convert (sizetype, t);
4388 t = fold_convert (TREE_TYPE (top), t);
4390 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4391 the argument has RSIZE - SIZE bytes of leading padding. */
4392 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4393 if (BYTES_BIG_ENDIAN && rsize > size)
4395 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4397 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4399 COND_EXPR_THEN (addr) = t;
4401 if (osize > UNITS_PER_WORD)
4403 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4404 u = fold_convert (TREE_TYPE (ovfl),
4405 build_int_cst (NULL_TREE, osize - 1));
4406 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4407 u = fold_convert (TREE_TYPE (ovfl),
4408 build_int_cst (NULL_TREE, -osize));
4409 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4410 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4415 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4416 post-increment ovfl by osize. On big-endian machines,
4417 the argument has OSIZE - SIZE bytes of leading padding. */
4418 u = fold_convert (TREE_TYPE (ovfl),
4419 build_int_cst (NULL_TREE, osize));
4420 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4421 if (BYTES_BIG_ENDIAN && osize > size)
4423 u = fold_convert (TREE_TYPE (t),
4424 build_int_cst (NULL_TREE, osize - size));
4425 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4428 /* String [9] and [10,11] together. */
4430 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4431 COND_EXPR_ELSE (addr) = t;
4433 addr = fold_convert (build_pointer_type (type), addr);
4434 addr = build_va_arg_indirect_ref (addr);
4438 addr = build_va_arg_indirect_ref (addr);
4443 /* Return true if it is possible to use left/right accesses for a
4444 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4445 returning true, update *OP, *LEFT and *RIGHT as follows:
4447 *OP is a BLKmode reference to the whole field.
4449 *LEFT is a QImode reference to the first byte if big endian or
4450 the last byte if little endian. This address can be used in the
4451 left-side instructions (lwl, swl, ldl, sdl).
4453 *RIGHT is a QImode reference to the opposite end of the field and
4454 can be used in the patterning right-side instruction. */
4457 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4458 rtx *left, rtx *right)
4462 /* Check that the operand really is a MEM. Not all the extv and
4463 extzv predicates are checked. */
4467 /* Check that the size is valid. */
4468 if (width != 32 && (!TARGET_64BIT || width != 64))
4471 /* We can only access byte-aligned values. Since we are always passed
4472 a reference to the first byte of the field, it is not necessary to
4473 do anything with BITPOS after this check. */
4474 if (bitpos % BITS_PER_UNIT != 0)
4477 /* Reject aligned bitfields: we want to use a normal load or store
4478 instead of a left/right pair. */
4479 if (MEM_ALIGN (*op) >= width)
4482 /* Adjust *OP to refer to the whole field. This also has the effect
4483 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4484 *op = adjust_address (*op, BLKmode, 0);
4485 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4487 /* Get references to both ends of the field. We deliberately don't
4488 use the original QImode *OP for FIRST since the new BLKmode one
4489 might have a simpler address. */
4490 first = adjust_address (*op, QImode, 0);
4491 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4493 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4494 be the upper word and RIGHT the lower word. */
4495 if (TARGET_BIG_ENDIAN)
4496 *left = first, *right = last;
4498 *left = last, *right = first;
4504 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4505 Return true on success. We only handle cases where zero_extract is
4506 equivalent to sign_extract. */
4509 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4511 rtx left, right, temp;
4513 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4514 paradoxical word_mode subreg. This is the only case in which
4515 we allow the destination to be larger than the source. */
4516 if (GET_CODE (dest) == SUBREG
4517 && GET_MODE (dest) == DImode
4518 && SUBREG_BYTE (dest) == 0
4519 && GET_MODE (SUBREG_REG (dest)) == SImode)
4520 dest = SUBREG_REG (dest);
4522 /* After the above adjustment, the destination must be the same
4523 width as the source. */
4524 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4527 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4530 temp = gen_reg_rtx (GET_MODE (dest));
4531 if (GET_MODE (dest) == DImode)
4533 emit_insn (gen_mov_ldl (temp, src, left));
4534 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4538 emit_insn (gen_mov_lwl (temp, src, left));
4539 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4545 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4549 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4552 enum machine_mode mode;
4554 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4557 mode = mode_for_size (width, MODE_INT, 0);
4558 src = gen_lowpart (mode, src);
4562 emit_insn (gen_mov_sdl (dest, src, left));
4563 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4567 emit_insn (gen_mov_swl (dest, src, left));
4568 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4573 /* Return true if X is a MEM with the same size as MODE. */
4576 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4583 size = MEM_SIZE (x);
4584 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4587 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4588 source of an "ext" instruction or the destination of an "ins"
4589 instruction. OP must be a register operand and the following
4590 conditions must hold:
4592 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4593 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4594 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4596 Also reject lengths equal to a word as they are better handled
4597 by the move patterns. */
4600 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4602 HOST_WIDE_INT len, pos;
4604 if (!ISA_HAS_EXT_INS
4605 || !register_operand (op, VOIDmode)
4606 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4609 len = INTVAL (size);
4610 pos = INTVAL (position);
4612 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4613 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4619 /* Set up globals to generate code for the ISA or processor
4620 described by INFO. */
4623 mips_set_architecture (const struct mips_cpu_info *info)
4627 mips_arch_info = info;
4628 mips_arch = info->cpu;
4629 mips_isa = info->isa;
4634 /* Likewise for tuning. */
4637 mips_set_tune (const struct mips_cpu_info *info)
4641 mips_tune_info = info;
4642 mips_tune = info->cpu;
4646 /* Implement TARGET_HANDLE_OPTION. */
4649 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4654 if (strcmp (arg, "32") == 0)
4656 else if (strcmp (arg, "o64") == 0)
4658 else if (strcmp (arg, "n32") == 0)
4660 else if (strcmp (arg, "64") == 0)
4662 else if (strcmp (arg, "eabi") == 0)
4663 mips_abi = ABI_EABI;
4670 return mips_parse_cpu (arg) != 0;
4673 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4674 return mips_isa_info != 0;
4676 case OPT_mno_flush_func:
4677 mips_cache_flush_func = NULL;
4685 /* Set up the threshold for data to go into the small data area, instead
4686 of the normal data area, and detect any conflicts in the switches. */
4689 override_options (void)
4691 int i, start, regno;
4692 enum machine_mode mode;
4694 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4696 /* The following code determines the architecture and register size.
4697 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4698 The GAS and GCC code should be kept in sync as much as possible. */
4700 if (mips_arch_string != 0)
4701 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4703 if (mips_isa_info != 0)
4705 if (mips_arch_info == 0)
4706 mips_set_architecture (mips_isa_info);
4707 else if (mips_arch_info->isa != mips_isa_info->isa)
4708 error ("-%s conflicts with the other architecture options, "
4709 "which specify a %s processor",
4710 mips_isa_info->name,
4711 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4714 if (mips_arch_info == 0)
4716 #ifdef MIPS_CPU_STRING_DEFAULT
4717 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4719 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4723 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4724 error ("-march=%s is not compatible with the selected ABI",
4725 mips_arch_info->name);
4727 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4728 if (mips_tune_string != 0)
4729 mips_set_tune (mips_parse_cpu (mips_tune_string));
4731 if (mips_tune_info == 0)
4732 mips_set_tune (mips_arch_info);
4734 /* Set cost structure for the processor. */
4735 mips_cost = &mips_rtx_cost_data[mips_tune];
4737 if ((target_flags_explicit & MASK_64BIT) != 0)
4739 /* The user specified the size of the integer registers. Make sure
4740 it agrees with the ABI and ISA. */
4741 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4742 error ("-mgp64 used with a 32-bit processor");
4743 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4744 error ("-mgp32 used with a 64-bit ABI");
4745 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4746 error ("-mgp64 used with a 32-bit ABI");
4750 /* Infer the integer register size from the ABI and processor.
4751 Restrict ourselves to 32-bit registers if that's all the
4752 processor has, or if the ABI cannot handle 64-bit registers. */
4753 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4754 target_flags &= ~MASK_64BIT;
4756 target_flags |= MASK_64BIT;
4759 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4761 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4762 only one right answer here. */
4763 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4764 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4765 else if (!TARGET_64BIT && TARGET_FLOAT64)
4766 error ("unsupported combination: %s", "-mgp32 -mfp64");
4767 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4768 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4772 /* -msingle-float selects 32-bit float registers. Otherwise the
4773 float registers should be the same size as the integer ones. */
4774 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4775 target_flags |= MASK_FLOAT64;
4777 target_flags &= ~MASK_FLOAT64;
4780 /* End of code shared with GAS. */
4782 if ((target_flags_explicit & MASK_LONG64) == 0)
4784 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4785 target_flags |= MASK_LONG64;
4787 target_flags &= ~MASK_LONG64;
4790 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4791 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4793 /* For some configurations, it is useful to have -march control
4794 the default setting of MASK_SOFT_FLOAT. */
4795 switch ((int) mips_arch)
4797 case PROCESSOR_R4100:
4798 case PROCESSOR_R4111:
4799 case PROCESSOR_R4120:
4800 case PROCESSOR_R4130:
4801 target_flags |= MASK_SOFT_FLOAT;
4805 target_flags &= ~MASK_SOFT_FLOAT;
4811 flag_pcc_struct_return = 0;
4813 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4815 /* If neither -mbranch-likely nor -mno-branch-likely was given
4816 on the command line, set MASK_BRANCHLIKELY based on the target
4819 By default, we enable use of Branch Likely instructions on
4820 all architectures which support them with the following
4821 exceptions: when creating MIPS32 or MIPS64 code, and when
4822 tuning for architectures where their use tends to hurt
4825 The MIPS32 and MIPS64 architecture specifications say "Software
4826 is strongly encouraged to avoid use of Branch Likely
4827 instructions, as they will be removed from a future revision
4828 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4829 issue those instructions unless instructed to do so by
4831 if (ISA_HAS_BRANCHLIKELY
4832 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4833 && !(TUNE_MIPS5500 || TUNE_SB1))
4834 target_flags |= MASK_BRANCHLIKELY;
4836 target_flags &= ~MASK_BRANCHLIKELY;
4838 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4839 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4841 /* The effect of -mabicalls isn't defined for the EABI. */
4842 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4844 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4845 target_flags &= ~MASK_ABICALLS;
4848 if (TARGET_ABICALLS)
4850 /* We need to set flag_pic for executables as well as DSOs
4851 because we may reference symbols that are not defined in
4852 the final executable. (MIPS does not use things like
4853 copy relocs, for example.)
4855 Also, there is a body of code that uses __PIC__ to distinguish
4856 between -mabicalls and -mno-abicalls code. */
4858 if (mips_section_threshold > 0)
4859 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
4862 /* mips_split_addresses is a half-way house between explicit
4863 relocations and the traditional assembler macros. It can
4864 split absolute 32-bit symbolic constants into a high/lo_sum
4865 pair but uses macros for other sorts of access.
4867 Like explicit relocation support for REL targets, it relies
4868 on GNU extensions in the assembler and the linker.
4870 Although this code should work for -O0, it has traditionally
4871 been treated as an optimization. */
4872 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4873 && optimize && !flag_pic
4874 && !ABI_HAS_64BIT_SYMBOLS)
4875 mips_split_addresses = 1;
4877 mips_split_addresses = 0;
4879 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4880 faster code, but at the expense of more nops. Enable it at -O3 and
4882 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4883 target_flags |= MASK_VR4130_ALIGN;
4885 /* When compiling for the mips16, we cannot use floating point. We
4886 record the original hard float value in mips16_hard_float. */
4889 if (TARGET_SOFT_FLOAT)
4890 mips16_hard_float = 0;
4892 mips16_hard_float = 1;
4893 target_flags |= MASK_SOFT_FLOAT;
4895 /* Don't run the scheduler before reload, since it tends to
4896 increase register pressure. */
4897 flag_schedule_insns = 0;
4899 /* Don't do hot/cold partitioning. The constant layout code expects
4900 the whole function to be in a single section. */
4901 flag_reorder_blocks_and_partition = 0;
4903 /* Silently disable -mexplicit-relocs since it doesn't apply
4904 to mips16 code. Even so, it would overly pedantic to warn
4905 about "-mips16 -mexplicit-relocs", especially given that
4906 we use a %gprel() operator. */
4907 target_flags &= ~MASK_EXPLICIT_RELOCS;
4910 /* When using explicit relocs, we call dbr_schedule from within
4912 if (TARGET_EXPLICIT_RELOCS)
4914 mips_flag_delayed_branch = flag_delayed_branch;
4915 flag_delayed_branch = 0;
4918 #ifdef MIPS_TFMODE_FORMAT
4919 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4922 /* Make sure that the user didn't turn off paired single support when
4923 MIPS-3D support is requested. */
4924 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4925 && !TARGET_PAIRED_SINGLE_FLOAT)
4926 error ("-mips3d requires -mpaired-single");
4928 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4930 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4932 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4933 and TARGET_HARD_FLOAT are both true. */
4934 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4935 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4937 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4939 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4940 error ("-mips3d/-mpaired-single must be used with -mips64");
4942 if (TARGET_MIPS16 && TARGET_DSP)
4943 error ("-mips16 and -mdsp cannot be used together");
4945 mips_print_operand_punct['?'] = 1;
4946 mips_print_operand_punct['#'] = 1;
4947 mips_print_operand_punct['/'] = 1;
4948 mips_print_operand_punct['&'] = 1;
4949 mips_print_operand_punct['!'] = 1;
4950 mips_print_operand_punct['*'] = 1;
4951 mips_print_operand_punct['@'] = 1;
4952 mips_print_operand_punct['.'] = 1;
4953 mips_print_operand_punct['('] = 1;
4954 mips_print_operand_punct[')'] = 1;
4955 mips_print_operand_punct['['] = 1;
4956 mips_print_operand_punct[']'] = 1;
4957 mips_print_operand_punct['<'] = 1;
4958 mips_print_operand_punct['>'] = 1;
4959 mips_print_operand_punct['{'] = 1;
4960 mips_print_operand_punct['}'] = 1;
4961 mips_print_operand_punct['^'] = 1;
4962 mips_print_operand_punct['$'] = 1;
4963 mips_print_operand_punct['+'] = 1;
4964 mips_print_operand_punct['~'] = 1;
4966 /* Set up array to map GCC register number to debug register number.
4967 Ignore the special purpose register numbers. */
4969 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4970 mips_dbx_regno[i] = -1;
4972 start = GP_DBX_FIRST - GP_REG_FIRST;
4973 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4974 mips_dbx_regno[i] = i + start;
4976 start = FP_DBX_FIRST - FP_REG_FIRST;
4977 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4978 mips_dbx_regno[i] = i + start;
4980 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4981 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4983 /* Set up array giving whether a given register can hold a given mode. */
4985 for (mode = VOIDmode;
4986 mode != MAX_MACHINE_MODE;
4987 mode = (enum machine_mode) ((int)mode + 1))
4989 register int size = GET_MODE_SIZE (mode);
4990 register enum mode_class class = GET_MODE_CLASS (mode);
4992 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4996 if (mode == CCV2mode)
4999 && (regno - ST_REG_FIRST) % 2 == 0);
5001 else if (mode == CCV4mode)
5004 && (regno - ST_REG_FIRST) % 4 == 0);
5006 else if (mode == CCmode)
5009 temp = (regno == FPSW_REGNUM);
5011 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5012 || FP_REG_P (regno));
5015 else if (GP_REG_P (regno))
5016 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5018 else if (FP_REG_P (regno))
5019 temp = ((regno % FP_INC) == 0)
5020 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5021 || class == MODE_VECTOR_FLOAT)
5022 && size <= UNITS_PER_FPVALUE)
5023 /* Allow integer modes that fit into a single
5024 register. We need to put integers into FPRs
5025 when using instructions like cvt and trunc.
5026 We can't allow sizes smaller than a word,
5027 the FPU has no appropriate load/store
5028 instructions for those. */
5029 || (class == MODE_INT
5030 && size >= MIN_UNITS_PER_WORD
5031 && size <= UNITS_PER_FPREG)
5032 /* Allow TFmode for CCmode reloads. */
5033 || (ISA_HAS_8CC && mode == TFmode));
5035 else if (ACC_REG_P (regno))
5036 temp = (INTEGRAL_MODE_P (mode)
5037 && (size <= UNITS_PER_WORD
5038 || (ACC_HI_REG_P (regno)
5039 && size == 2 * UNITS_PER_WORD)));
5041 else if (ALL_COP_REG_P (regno))
5042 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5046 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5050 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5051 initialized yet, so we can't use that here. */
5052 gpr_mode = TARGET_64BIT ? DImode : SImode;
5054 /* Provide default values for align_* for 64-bit targets. */
5055 if (TARGET_64BIT && !TARGET_MIPS16)
5057 if (align_loops == 0)
5059 if (align_jumps == 0)
5061 if (align_functions == 0)
5062 align_functions = 8;
5065 /* Function to allocate machine-dependent function status. */
5066 init_machine_status = &mips_init_machine_status;
5068 if (ABI_HAS_64BIT_SYMBOLS)
5070 if (TARGET_EXPLICIT_RELOCS)
5072 mips_split_p[SYMBOL_64_HIGH] = true;
5073 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5074 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5076 mips_split_p[SYMBOL_64_MID] = true;
5077 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5078 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5080 mips_split_p[SYMBOL_64_LOW] = true;
5081 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5082 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5084 mips_split_p[SYMBOL_GENERAL] = true;
5085 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5090 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5092 mips_split_p[SYMBOL_GENERAL] = true;
5093 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5094 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5100 /* The high part is provided by a pseudo copy of $gp. */
5101 mips_split_p[SYMBOL_SMALL_DATA] = true;
5102 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5105 if (TARGET_EXPLICIT_RELOCS)
5107 /* Small data constants are kept whole until after reload,
5108 then lowered by mips_rewrite_small_data. */
5109 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5111 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5114 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5115 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5119 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5120 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5125 /* The HIGH and LO_SUM are matched by special .md patterns. */
5126 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5128 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5129 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5130 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5132 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5133 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5134 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5139 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5141 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5142 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5148 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5149 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5150 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5153 /* Thread-local relocation operators. */
5154 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5155 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5156 mips_split_p[SYMBOL_DTPREL] = 1;
5157 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5158 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5159 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5160 mips_split_p[SYMBOL_TPREL] = 1;
5161 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5162 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5164 /* We don't have a thread pointer access instruction on MIPS16, or
5165 appropriate TLS relocations. */
5167 targetm.have_tls = false;
5169 /* Default to working around R4000 errata only if the processor
5170 was selected explicitly. */
5171 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5172 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5173 target_flags |= MASK_FIX_R4000;
5175 /* Default to working around R4400 errata only if the processor
5176 was selected explicitly. */
5177 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5178 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5179 target_flags |= MASK_FIX_R4400;
5182 /* Implement CONDITIONAL_REGISTER_USAGE. */
5185 mips_conditional_register_usage (void)
5191 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5192 fixed_regs[regno] = call_used_regs[regno] = 1;
5194 if (!TARGET_HARD_FLOAT)
5198 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5199 fixed_regs[regno] = call_used_regs[regno] = 1;
5200 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5201 fixed_regs[regno] = call_used_regs[regno] = 1;
5203 else if (! ISA_HAS_8CC)
5207 /* We only have a single condition code register. We
5208 implement this by hiding all the condition code registers,
5209 and generating RTL that refers directly to ST_REG_FIRST. */
5210 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5211 fixed_regs[regno] = call_used_regs[regno] = 1;
5213 /* In mips16 mode, we permit the $t temporary registers to be used
5214 for reload. We prohibit the unused $s registers, since they
5215 are caller saved, and saving them via a mips16 register would
5216 probably waste more time than just reloading the value. */
5219 fixed_regs[18] = call_used_regs[18] = 1;
5220 fixed_regs[19] = call_used_regs[19] = 1;
5221 fixed_regs[20] = call_used_regs[20] = 1;
5222 fixed_regs[21] = call_used_regs[21] = 1;
5223 fixed_regs[22] = call_used_regs[22] = 1;
5224 fixed_regs[23] = call_used_regs[23] = 1;
5225 fixed_regs[26] = call_used_regs[26] = 1;
5226 fixed_regs[27] = call_used_regs[27] = 1;
5227 fixed_regs[30] = call_used_regs[30] = 1;
5229 /* fp20-23 are now caller saved. */
5230 if (mips_abi == ABI_64)
5233 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5234 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5236 /* Odd registers from fp21 to fp31 are now caller saved. */
5237 if (mips_abi == ABI_N32)
5240 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5241 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5245 /* Allocate a chunk of memory for per-function machine-dependent data. */
5246 static struct machine_function *
5247 mips_init_machine_status (void)
5249 return ((struct machine_function *)
5250 ggc_alloc_cleared (sizeof (struct machine_function)));
5253 /* On the mips16, we want to allocate $24 (T_REG) before other
5254 registers for instructions for which it is possible. This helps
5255 avoid shuffling registers around in order to set up for an xor,
5256 encouraging the compiler to use a cmp instead. */
5259 mips_order_regs_for_local_alloc (void)
5263 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5264 reg_alloc_order[i] = i;
5268 /* It really doesn't matter where we put register 0, since it is
5269 a fixed register anyhow. */
5270 reg_alloc_order[0] = 24;
5271 reg_alloc_order[24] = 0;
5276 /* The MIPS debug format wants all automatic variables and arguments
5277 to be in terms of the virtual frame pointer (stack pointer before
5278 any adjustment in the function), while the MIPS 3.0 linker wants
5279 the frame pointer to be the stack pointer after the initial
5280 adjustment. So, we do the adjustment here. The arg pointer (which
5281 is eliminated) points to the virtual frame pointer, while the frame
5282 pointer (which may be eliminated) points to the stack pointer after
5283 the initial adjustments. */
5286 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5288 rtx offset2 = const0_rtx;
5289 rtx reg = eliminate_constant_term (addr, &offset2);
5292 offset = INTVAL (offset2);
5294 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5295 || reg == hard_frame_pointer_rtx)
5297 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5298 ? compute_frame_size (get_frame_size ())
5299 : cfun->machine->frame.total_size;
5301 /* MIPS16 frame is smaller */
5302 if (frame_pointer_needed && TARGET_MIPS16)
5303 frame_size -= cfun->machine->frame.args_size;
5305 offset = offset - frame_size;
5308 /* sdbout_parms does not want this to crash for unrecognized cases. */
5310 else if (reg != arg_pointer_rtx)
5311 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5318 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5320 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5321 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5322 'h' OP is HIGH, prints %hi(X),
5323 'd' output integer constant in decimal,
5324 'z' if the operand is 0, use $0 instead of normal operand.
5325 'D' print second part of double-word register or memory operand.
5326 'L' print low-order register of double-word register operand.
5327 'M' print high-order register of double-word register operand.
5328 'C' print part of opcode for a branch condition.
5329 'F' print part of opcode for a floating-point branch condition.
5330 'N' print part of opcode for a branch condition, inverted.
5331 'W' print part of opcode for a floating-point branch condition, inverted.
5332 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5333 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5334 't' like 'T', but with the EQ/NE cases reversed
5335 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5336 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5337 'R' print the reloc associated with LO_SUM
5338 'q' print DSP accumulator registers
5340 The punctuation characters are:
5342 '(' Turn on .set noreorder
5343 ')' Turn on .set reorder
5344 '[' Turn on .set noat
5346 '<' Turn on .set nomacro
5347 '>' Turn on .set macro
5348 '{' Turn on .set volatile (not GAS)
5349 '}' Turn on .set novolatile (not GAS)
5350 '&' Turn on .set noreorder if filling delay slots
5351 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5352 '!' Turn on .set nomacro if filling delay slots
5353 '#' Print nop if in a .set noreorder section.
5354 '/' Like '#', but does nothing within a delayed branch sequence
5355 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5356 '@' Print the name of the assembler temporary register (at or $1).
5357 '.' Print the name of the register with a hard-wired zero (zero or $0).
5358 '^' Print the name of the pic call-through register (t9 or $25).
5359 '$' Print the name of the stack pointer register (sp or $29).
5360 '+' Print the name of the gp register (usually gp or $28).
5361 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5364 print_operand (FILE *file, rtx op, int letter)
5366 register enum rtx_code code;
5368 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5373 if (mips_branch_likely)
5378 fputs (reg_names [GP_REG_FIRST + 1], file);
5382 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5386 fputs (reg_names [GP_REG_FIRST + 0], file);
5390 fputs (reg_names[STACK_POINTER_REGNUM], file);
5394 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5398 if (final_sequence != 0 && set_noreorder++ == 0)
5399 fputs (".set\tnoreorder\n\t", file);
5403 if (final_sequence != 0)
5405 if (set_noreorder++ == 0)
5406 fputs (".set\tnoreorder\n\t", file);
5408 if (set_nomacro++ == 0)
5409 fputs (".set\tnomacro\n\t", file);
5414 if (final_sequence != 0 && set_nomacro++ == 0)
5415 fputs ("\n\t.set\tnomacro", file);
5419 if (set_noreorder != 0)
5420 fputs ("\n\tnop", file);
5424 /* Print an extra newline so that the delayed insn is separated
5425 from the following ones. This looks neater and is consistent
5426 with non-nop delayed sequences. */
5427 if (set_noreorder != 0 && final_sequence == 0)
5428 fputs ("\n\tnop\n", file);
5432 if (set_noreorder++ == 0)
5433 fputs (".set\tnoreorder\n\t", file);
5437 if (set_noreorder == 0)
5438 error ("internal error: %%) found without a %%( in assembler pattern");
5440 else if (--set_noreorder == 0)
5441 fputs ("\n\t.set\treorder", file);
5446 if (set_noat++ == 0)
5447 fputs (".set\tnoat\n\t", file);
5452 error ("internal error: %%] found without a %%[ in assembler pattern");
5453 else if (--set_noat == 0)
5454 fputs ("\n\t.set\tat", file);
5459 if (set_nomacro++ == 0)
5460 fputs (".set\tnomacro\n\t", file);
5464 if (set_nomacro == 0)
5465 error ("internal error: %%> found without a %%< in assembler pattern");
5466 else if (--set_nomacro == 0)
5467 fputs ("\n\t.set\tmacro", file);
5472 if (set_volatile++ == 0)
5473 fputs ("#.set\tvolatile\n\t", file);
5477 if (set_volatile == 0)
5478 error ("internal error: %%} found without a %%{ in assembler pattern");
5479 else if (--set_volatile == 0)
5480 fputs ("\n\t#.set\tnovolatile", file);
5486 if (align_labels_log > 0)
5487 ASM_OUTPUT_ALIGN (file, align_labels_log);
5492 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5501 error ("PRINT_OPERAND null pointer");
5505 code = GET_CODE (op);
5510 case EQ: fputs ("eq", file); break;
5511 case NE: fputs ("ne", file); break;
5512 case GT: fputs ("gt", file); break;
5513 case GE: fputs ("ge", file); break;
5514 case LT: fputs ("lt", file); break;
5515 case LE: fputs ("le", file); break;
5516 case GTU: fputs ("gtu", file); break;
5517 case GEU: fputs ("geu", file); break;
5518 case LTU: fputs ("ltu", file); break;
5519 case LEU: fputs ("leu", file); break;
5521 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5524 else if (letter == 'N')
5527 case EQ: fputs ("ne", file); break;
5528 case NE: fputs ("eq", file); break;
5529 case GT: fputs ("le", file); break;
5530 case GE: fputs ("lt", file); break;
5531 case LT: fputs ("ge", file); break;
5532 case LE: fputs ("gt", file); break;
5533 case GTU: fputs ("leu", file); break;
5534 case GEU: fputs ("ltu", file); break;
5535 case LTU: fputs ("geu", file); break;
5536 case LEU: fputs ("gtu", file); break;
5538 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5541 else if (letter == 'F')
5544 case EQ: fputs ("c1f", file); break;
5545 case NE: fputs ("c1t", file); break;
5547 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5550 else if (letter == 'W')
5553 case EQ: fputs ("c1t", file); break;
5554 case NE: fputs ("c1f", file); break;
5556 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5559 else if (letter == 'h')
5561 if (GET_CODE (op) == HIGH)
5564 print_operand_reloc (file, op, mips_hi_relocs);
5567 else if (letter == 'R')
5568 print_operand_reloc (file, op, mips_lo_relocs);
5570 else if (letter == 'Y')
5572 if (GET_CODE (op) == CONST_INT
5573 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5574 < ARRAY_SIZE (mips_fp_conditions)))
5575 fputs (mips_fp_conditions[INTVAL (op)], file);
5577 output_operand_lossage ("invalid %%Y value");
5580 else if (letter == 'Z')
5584 print_operand (file, op, 0);
5589 else if (letter == 'q')
5594 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5596 regnum = REGNO (op);
5597 if (MD_REG_P (regnum))
5598 fprintf (file, "$ac0");
5599 else if (DSP_ACC_REG_P (regnum))
5600 fprintf (file, "$ac%c", reg_names[regnum][3]);
5602 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5605 else if (code == REG || code == SUBREG)
5607 register int regnum;
5610 regnum = REGNO (op);
5612 regnum = true_regnum (op);
5614 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5615 || (letter == 'L' && WORDS_BIG_ENDIAN)
5619 fprintf (file, "%s", reg_names[regnum]);
5622 else if (code == MEM)
5625 output_address (plus_constant (XEXP (op, 0), 4));
5627 output_address (XEXP (op, 0));
5630 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5631 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5633 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5634 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5636 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5637 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5639 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5640 fputs (reg_names[GP_REG_FIRST], file);
5642 else if (letter == 'd' || letter == 'x' || letter == 'X')
5643 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5645 else if (letter == 'T' || letter == 't')
5647 int truth = (code == NE) == (letter == 'T');
5648 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5651 else if (CONST_GP_P (op))
5652 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5655 output_addr_const (file, op);
5659 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5660 RELOCS is the array of relocations to use. */
5663 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5665 enum mips_symbol_type symbol_type;
5668 HOST_WIDE_INT offset;
5670 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5671 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5673 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5674 mips_split_const (op, &base, &offset);
5675 if (UNSPEC_ADDRESS_P (base))
5676 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5678 fputs (relocs[symbol_type], file);
5679 output_addr_const (file, op);
5680 for (p = relocs[symbol_type]; *p != 0; p++)
5685 /* Output address operand X to FILE. */
5688 print_operand_address (FILE *file, rtx x)
5690 struct mips_address_info addr;
5692 if (mips_classify_address (&addr, x, word_mode, true))
5696 print_operand (file, addr.offset, 0);
5697 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5700 case ADDRESS_LO_SUM:
5701 print_operand (file, addr.offset, 'R');
5702 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5705 case ADDRESS_CONST_INT:
5706 output_addr_const (file, x);
5707 fprintf (file, "(%s)", reg_names[0]);
5710 case ADDRESS_SYMBOLIC:
5711 output_addr_const (file, x);
5717 /* When using assembler macros, keep track of all of small-data externs
5718 so that mips_file_end can emit the appropriate declarations for them.
5720 In most cases it would be safe (though pointless) to emit .externs
5721 for other symbols too. One exception is when an object is within
5722 the -G limit but declared by the user to be in a section other
5723 than .sbss or .sdata. */
5726 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5728 register struct extern_list *p;
5730 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5732 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5733 p->next = extern_head;
5735 p->size = int_size_in_bytes (TREE_TYPE (decl));
5739 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5741 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5742 p->next = extern_head;
5753 irix_output_external_libcall (rtx fun)
5755 register struct extern_list *p;
5757 if (mips_abi == ABI_32)
5759 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5760 p->next = extern_head;
5761 p->name = XSTR (fun, 0);
5768 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5769 put out a MIPS ECOFF file and a stab. */
5772 mips_output_filename (FILE *stream, const char *name)
5775 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5777 if (write_symbols == DWARF2_DEBUG)
5779 else if (mips_output_filename_first_time)
5781 mips_output_filename_first_time = 0;
5782 num_source_filenames += 1;
5783 current_function_file = name;
5784 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5785 output_quoted_string (stream, name);
5786 putc ('\n', stream);
5789 /* If we are emitting stabs, let dbxout.c handle this (except for
5790 the mips_output_filename_first_time case). */
5791 else if (write_symbols == DBX_DEBUG)
5794 else if (name != current_function_file
5795 && strcmp (name, current_function_file) != 0)
5797 num_source_filenames += 1;
5798 current_function_file = name;
5799 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5800 output_quoted_string (stream, name);
5801 putc ('\n', stream);
5805 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5806 that should be written before the opening quote, such as "\t.ascii\t"
5807 for real string data or "\t# " for a comment. */
5810 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5815 register const unsigned char *string =
5816 (const unsigned char *)string_param;
5818 fprintf (stream, "%s\"", prefix);
5819 for (i = 0; i < len; i++)
5821 register int c = string[i];
5825 if (c == '\\' || c == '\"')
5827 putc ('\\', stream);
5835 fprintf (stream, "\\%03o", c);
5839 if (cur_pos > 72 && i+1 < len)
5842 fprintf (stream, "\"\n%s\"", prefix);
5845 fprintf (stream, "\"\n");
5848 /* Implement TARGET_ASM_FILE_START. */
5851 mips_file_start (void)
5853 default_file_start ();
5857 /* Generate a special section to describe the ABI switches used to
5858 produce the resultant binary. This used to be done by the assembler
5859 setting bits in the ELF header's flags field, but we have run out of
5860 bits. GDB needs this information in order to be able to correctly
5861 debug these binaries. See the function mips_gdbarch_init() in
5862 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5863 causes unnecessary IRIX 6 ld warnings. */
5864 const char * abi_string = NULL;
5868 case ABI_32: abi_string = "abi32"; break;
5869 case ABI_N32: abi_string = "abiN32"; break;
5870 case ABI_64: abi_string = "abi64"; break;
5871 case ABI_O64: abi_string = "abiO64"; break;
5872 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5876 /* Note - we use fprintf directly rather than calling switch_to_section
5877 because in this way we can avoid creating an allocated section. We
5878 do not want this section to take up any space in the running
5880 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5882 /* There is no ELF header flag to distinguish long32 forms of the
5883 EABI from long64 forms. Emit a special section to help tools
5884 such as GDB. Do the same for o64, which is sometimes used with
5886 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
5887 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5888 TARGET_LONG64 ? 64 : 32);
5890 /* Restore the default section. */
5891 fprintf (asm_out_file, "\t.previous\n");
5894 /* Generate the pseudo ops that System V.4 wants. */
5895 if (TARGET_ABICALLS)
5896 fprintf (asm_out_file, "\t.abicalls\n");
5899 fprintf (asm_out_file, "\t.set\tmips16\n");
5901 if (flag_verbose_asm)
5902 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5904 mips_section_threshold, mips_arch_info->name, mips_isa);
5907 #ifdef BSS_SECTION_ASM_OP
5908 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5909 in the use of sbss. */
5912 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5913 unsigned HOST_WIDE_INT size, int align)
5915 extern tree last_assemble_variable_decl;
5917 if (mips_in_small_data_p (decl))
5918 switch_to_section (get_named_section (NULL, ".sbss", 0));
5920 switch_to_section (bss_section);
5921 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5922 last_assemble_variable_decl = decl;
5923 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5924 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5928 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5929 .externs for any small-data variables that turned out to be external. */
5932 mips_file_end (void)
5935 struct extern_list *p;
5939 fputs ("\n", asm_out_file);
5941 for (p = extern_head; p != 0; p = p->next)
5943 name_tree = get_identifier (p->name);
5945 /* Positively ensure only one .extern for any given symbol. */
5946 if (!TREE_ASM_WRITTEN (name_tree)
5947 && TREE_SYMBOL_REFERENCED (name_tree))
5949 TREE_ASM_WRITTEN (name_tree) = 1;
5950 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5951 `.global name .text' directive for every used but
5952 undefined function. If we don't, the linker may perform
5953 an optimization (skipping over the insns that set $gp)
5954 when it is unsafe. */
5955 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5957 fputs ("\t.globl ", asm_out_file);
5958 assemble_name (asm_out_file, p->name);
5959 fputs (" .text\n", asm_out_file);
5963 fputs ("\t.extern\t", asm_out_file);
5964 assemble_name (asm_out_file, p->name);
5965 fprintf (asm_out_file, ", %d\n", p->size);
5972 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5973 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5976 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5977 unsigned HOST_WIDE_INT size,
5980 /* If the target wants uninitialized const declarations in
5981 .rdata then don't put them in .comm. */
5982 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5983 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5984 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5986 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5987 targetm.asm_out.globalize_label (stream, name);
5989 switch_to_section (readonly_data_section);
5990 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5991 mips_declare_object (stream, name, "",
5992 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5996 mips_declare_common_object (stream, name, "\n\t.comm\t",
6000 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6001 NAME is the name of the object and ALIGN is the required alignment
6002 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6003 alignment argument. */
6006 mips_declare_common_object (FILE *stream, const char *name,
6007 const char *init_string,
6008 unsigned HOST_WIDE_INT size,
6009 unsigned int align, bool takes_alignment_p)
6011 if (!takes_alignment_p)
6013 size += (align / BITS_PER_UNIT) - 1;
6014 size -= size % (align / BITS_PER_UNIT);
6015 mips_declare_object (stream, name, init_string,
6016 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6019 mips_declare_object (stream, name, init_string,
6020 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6021 size, align / BITS_PER_UNIT);
6024 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6025 macros, mark the symbol as written so that mips_file_end won't emit an
6026 .extern for it. STREAM is the output file, NAME is the name of the
6027 symbol, INIT_STRING is the string that should be written before the
6028 symbol and FINAL_STRING is the string that should be written after it.
6029 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6032 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6033 const char *final_string, ...)
6037 fputs (init_string, stream);
6038 assemble_name (stream, name);
6039 va_start (ap, final_string);
6040 vfprintf (stream, final_string, ap);
6043 if (!TARGET_EXPLICIT_RELOCS)
6045 tree name_tree = get_identifier (name);
6046 TREE_ASM_WRITTEN (name_tree) = 1;
6050 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6051 extern int size_directive_output;
6053 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6054 definitions except that it uses mips_declare_object() to emit the label. */
6057 mips_declare_object_name (FILE *stream, const char *name,
6058 tree decl ATTRIBUTE_UNUSED)
6060 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6061 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6064 size_directive_output = 0;
6065 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6069 size_directive_output = 1;
6070 size = int_size_in_bytes (TREE_TYPE (decl));
6071 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6074 mips_declare_object (stream, name, "", ":\n");
6077 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6080 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6084 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6085 if (!flag_inhibit_size_directive
6086 && DECL_SIZE (decl) != 0
6087 && !at_end && top_level
6088 && DECL_INITIAL (decl) == error_mark_node
6089 && !size_directive_output)
6093 size_directive_output = 1;
6094 size = int_size_in_bytes (TREE_TYPE (decl));
6095 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6100 /* Return true if X is a small data address that can be rewritten
6104 mips_rewrite_small_data_p (rtx x)
6106 enum mips_symbol_type symbol_type;
6108 return (TARGET_EXPLICIT_RELOCS
6109 && mips_symbolic_constant_p (x, &symbol_type)
6110 && symbol_type == SYMBOL_SMALL_DATA);
6114 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6117 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6119 if (GET_CODE (*loc) == LO_SUM)
6122 return mips_rewrite_small_data_p (*loc);
6125 /* Return true if OP refers to small data symbols directly, not through
6129 mips_small_data_pattern_p (rtx op)
6131 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6134 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6137 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6139 if (mips_rewrite_small_data_p (*loc))
6140 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6142 if (GET_CODE (*loc) == LO_SUM)
6148 /* If possible, rewrite OP so that it refers to small data using
6149 explicit relocations. */
6152 mips_rewrite_small_data (rtx op)
6154 op = copy_insn (op);
6155 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6159 /* Return true if the current function has an insn that implicitly
6163 mips_function_has_gp_insn (void)
6165 /* Don't bother rechecking if we found one last time. */
6166 if (!cfun->machine->has_gp_insn_p)
6170 push_topmost_sequence ();
6171 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6173 && GET_CODE (PATTERN (insn)) != USE
6174 && GET_CODE (PATTERN (insn)) != CLOBBER
6175 && (get_attr_got (insn) != GOT_UNSET
6176 || small_data_pattern (PATTERN (insn), VOIDmode)))
6178 pop_topmost_sequence ();
6180 cfun->machine->has_gp_insn_p = (insn != 0);
6182 return cfun->machine->has_gp_insn_p;
6186 /* Return the register that should be used as the global pointer
6187 within this function. Return 0 if the function doesn't need
6188 a global pointer. */
6191 mips_global_pointer (void)
6195 /* $gp is always available in non-abicalls code. */
6196 if (!TARGET_ABICALLS)
6197 return GLOBAL_POINTER_REGNUM;
6199 /* We must always provide $gp when it is used implicitly. */
6200 if (!TARGET_EXPLICIT_RELOCS)
6201 return GLOBAL_POINTER_REGNUM;
6203 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6205 if (current_function_profile)
6206 return GLOBAL_POINTER_REGNUM;
6208 /* If the function has a nonlocal goto, $gp must hold the correct
6209 global pointer for the target function. */
6210 if (current_function_has_nonlocal_goto)
6211 return GLOBAL_POINTER_REGNUM;
6213 /* If the gp is never referenced, there's no need to initialize it.
6214 Note that reload can sometimes introduce constant pool references
6215 into a function that otherwise didn't need them. For example,
6216 suppose we have an instruction like:
6218 (set (reg:DF R1) (float:DF (reg:SI R2)))
6220 If R2 turns out to be constant such as 1, the instruction may have a
6221 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6222 using this constant if R2 doesn't get allocated to a register.
6224 In cases like these, reload will have added the constant to the pool
6225 but no instruction will yet refer to it. */
6226 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6227 && !current_function_uses_const_pool
6228 && !mips_function_has_gp_insn ())
6231 /* We need a global pointer, but perhaps we can use a call-clobbered
6232 register instead of $gp. */
6233 if (TARGET_NEWABI && current_function_is_leaf)
6234 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6235 if (!regs_ever_live[regno]
6236 && call_used_regs[regno]
6237 && !fixed_regs[regno]
6238 && regno != PIC_FUNCTION_ADDR_REGNUM)
6241 return GLOBAL_POINTER_REGNUM;
6245 /* Return true if the current function must save REGNO. */
6248 mips_save_reg_p (unsigned int regno)
6250 /* We only need to save $gp for NewABI PIC. */
6251 if (regno == GLOBAL_POINTER_REGNUM)
6252 return (TARGET_ABICALLS && TARGET_NEWABI
6253 && cfun->machine->global_pointer == regno);
6255 /* Check call-saved registers. */
6256 if (regs_ever_live[regno] && !call_used_regs[regno])
6259 /* We need to save the old frame pointer before setting up a new one. */
6260 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6263 /* We need to save the incoming return address if it is ever clobbered
6264 within the function. */
6265 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6272 return_type = DECL_RESULT (current_function_decl);
6274 /* $18 is a special case in mips16 code. It may be used to call
6275 a function which returns a floating point value, but it is
6276 marked in call_used_regs. */
6277 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6280 /* $31 is also a special case. It will be used to copy a return
6281 value into the floating point registers if the return value is
6283 if (regno == GP_REG_FIRST + 31
6284 && mips16_hard_float
6285 && !aggregate_value_p (return_type, current_function_decl)
6286 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6287 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6295 /* Return the bytes needed to compute the frame pointer from the current
6296 stack pointer. SIZE is the size (in bytes) of the local variables.
6298 MIPS stack frames look like:
6300 Before call After call
6301 +-----------------------+ +-----------------------+
6304 | caller's temps. | | caller's temps. |
6306 +-----------------------+ +-----------------------+
6308 | arguments on stack. | | arguments on stack. |
6310 +-----------------------+ +-----------------------+
6311 | 4 words to save | | 4 words to save |
6312 | arguments passed | | arguments passed |
6313 | in registers, even | | in registers, even |
6314 SP->| if not passed. | VFP->| if not passed. |
6315 +-----------------------+ +-----------------------+
6317 | fp register save |
6319 +-----------------------+
6321 | gp register save |
6323 +-----------------------+
6327 +-----------------------+
6329 | alloca allocations |
6331 +-----------------------+
6333 | GP save for V.4 abi |
6335 +-----------------------+
6337 | arguments on stack |
6339 +-----------------------+
6341 | arguments passed |
6342 | in registers, even |
6343 low SP->| if not passed. |
6344 memory +-----------------------+
6349 compute_frame_size (HOST_WIDE_INT size)
6352 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6353 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6354 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6355 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6356 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6357 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6358 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6359 unsigned int mask; /* mask of saved gp registers */
6360 unsigned int fmask; /* mask of saved fp registers */
6362 cfun->machine->global_pointer = mips_global_pointer ();
6368 var_size = MIPS_STACK_ALIGN (size);
6369 args_size = current_function_outgoing_args_size;
6370 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6372 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6373 functions. If the function has local variables, we're committed
6374 to allocating it anyway. Otherwise reclaim it here. */
6375 if (var_size == 0 && current_function_is_leaf)
6376 cprestore_size = args_size = 0;
6378 /* The MIPS 3.0 linker does not like functions that dynamically
6379 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6380 looks like we are trying to create a second frame pointer to the
6381 function, so allocate some stack space to make it happy. */
6383 if (args_size == 0 && current_function_calls_alloca)
6384 args_size = 4 * UNITS_PER_WORD;
6386 total_size = var_size + args_size + cprestore_size;
6388 /* Calculate space needed for gp registers. */
6389 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6390 if (mips_save_reg_p (regno))
6392 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6393 mask |= 1 << (regno - GP_REG_FIRST);
6396 /* We need to restore these for the handler. */
6397 if (current_function_calls_eh_return)
6402 regno = EH_RETURN_DATA_REGNO (i);
6403 if (regno == INVALID_REGNUM)
6405 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6406 mask |= 1 << (regno - GP_REG_FIRST);
6410 /* This loop must iterate over the same space as its companion in
6411 save_restore_insns. */
6412 for (regno = (FP_REG_LAST - FP_INC + 1);
6413 regno >= FP_REG_FIRST;
6416 if (mips_save_reg_p (regno))
6418 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6419 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6423 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6424 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6426 /* Add in the space required for saving incoming register arguments. */
6427 total_size += current_function_pretend_args_size;
6428 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6430 /* Save other computed information. */
6431 cfun->machine->frame.total_size = total_size;
6432 cfun->machine->frame.var_size = var_size;
6433 cfun->machine->frame.args_size = args_size;
6434 cfun->machine->frame.cprestore_size = cprestore_size;
6435 cfun->machine->frame.gp_reg_size = gp_reg_size;
6436 cfun->machine->frame.fp_reg_size = fp_reg_size;
6437 cfun->machine->frame.mask = mask;
6438 cfun->machine->frame.fmask = fmask;
6439 cfun->machine->frame.initialized = reload_completed;
6440 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6441 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6445 HOST_WIDE_INT offset;
6447 offset = (args_size + cprestore_size + var_size
6448 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6449 cfun->machine->frame.gp_sp_offset = offset;
6450 cfun->machine->frame.gp_save_offset = offset - total_size;
6454 cfun->machine->frame.gp_sp_offset = 0;
6455 cfun->machine->frame.gp_save_offset = 0;
6460 HOST_WIDE_INT offset;
6462 offset = (args_size + cprestore_size + var_size
6463 + gp_reg_rounded + fp_reg_size
6464 - FP_INC * UNITS_PER_FPREG);
6465 cfun->machine->frame.fp_sp_offset = offset;
6466 cfun->machine->frame.fp_save_offset = offset - total_size;
6470 cfun->machine->frame.fp_sp_offset = 0;
6471 cfun->machine->frame.fp_save_offset = 0;
6474 /* Ok, we're done. */
6478 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6479 pointer or argument pointer. TO is either the stack pointer or
6480 hard frame pointer. */
6483 mips_initial_elimination_offset (int from, int to)
6485 HOST_WIDE_INT offset;
6487 compute_frame_size (get_frame_size ());
6489 /* Set OFFSET to the offset from the stack pointer. */
6492 case FRAME_POINTER_REGNUM:
6496 case ARG_POINTER_REGNUM:
6497 offset = (cfun->machine->frame.total_size
6498 - current_function_pretend_args_size);
6505 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6506 offset -= cfun->machine->frame.args_size;
6511 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6512 back to a previous frame. */
6514 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6519 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6522 /* Use FN to save or restore register REGNO. MODE is the register's
6523 mode and OFFSET is the offset of its save slot from the current
6527 mips_save_restore_reg (enum machine_mode mode, int regno,
6528 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6532 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
6534 fn (gen_rtx_REG (mode, regno), mem);
6538 /* Call FN for each register that is saved by the current function.
6539 SP_OFFSET is the offset of the current stack pointer from the start
6543 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6545 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6547 enum machine_mode fpr_mode;
6548 HOST_WIDE_INT offset;
6551 /* Save registers starting from high to low. The debuggers prefer at least
6552 the return register be stored at func+4, and also it allows us not to
6553 need a nop in the epilog if at least one register is reloaded in
6554 addition to return address. */
6555 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6556 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6557 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6559 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6560 offset -= GET_MODE_SIZE (gpr_mode);
6563 /* This loop must iterate over the same space as its companion in
6564 compute_frame_size. */
6565 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6566 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6567 for (regno = (FP_REG_LAST - FP_INC + 1);
6568 regno >= FP_REG_FIRST;
6570 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6572 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6573 offset -= GET_MODE_SIZE (fpr_mode);
6578 /* If we're generating n32 or n64 abicalls, and the current function
6579 does not use $28 as its global pointer, emit a cplocal directive.
6580 Use pic_offset_table_rtx as the argument to the directive. */
6583 mips_output_cplocal (void)
6585 if (!TARGET_EXPLICIT_RELOCS
6586 && cfun->machine->global_pointer > 0
6587 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6588 output_asm_insn (".cplocal %+", 0);
6591 /* Return the style of GP load sequence that is being used for the
6592 current function. */
6594 enum mips_loadgp_style
6595 mips_current_loadgp_style (void)
6597 if (!TARGET_ABICALLS || cfun->machine->global_pointer == 0)
6600 if (TARGET_ABSOLUTE_ABICALLS)
6601 return LOADGP_ABSOLUTE;
6603 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6606 /* The __gnu_local_gp symbol. */
6608 static GTY(()) rtx mips_gnu_local_gp;
6610 /* If we're generating n32 or n64 abicalls, emit instructions
6611 to set up the global pointer. */
6614 mips_emit_loadgp (void)
6616 rtx addr, offset, incoming_address;
6618 switch (mips_current_loadgp_style ())
6620 case LOADGP_ABSOLUTE:
6621 if (mips_gnu_local_gp == NULL)
6623 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6624 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6626 emit_insn (gen_loadgp_noshared (mips_gnu_local_gp));
6630 addr = XEXP (DECL_RTL (current_function_decl), 0);
6631 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6632 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6633 emit_insn (gen_loadgp (offset, incoming_address));
6634 if (!TARGET_EXPLICIT_RELOCS)
6635 emit_insn (gen_loadgp_blockage ());
6643 /* Set up the stack and frame (if desired) for the function. */
6646 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6649 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6651 #ifdef SDB_DEBUGGING_INFO
6652 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6653 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6656 /* In mips16 mode, we may need to generate a 32 bit to handle
6657 floating point arguments. The linker will arrange for any 32 bit
6658 functions to call this stub, which will then jump to the 16 bit
6660 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6661 && current_function_args_info.fp_code != 0)
6662 build_mips16_function_stub (file);
6664 if (!FUNCTION_NAME_ALREADY_DECLARED)
6666 /* Get the function name the same way that toplev.c does before calling
6667 assemble_start_function. This is needed so that the name used here
6668 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6669 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6671 if (!flag_inhibit_size_directive)
6673 fputs ("\t.ent\t", file);
6674 assemble_name (file, fnname);
6678 assemble_name (file, fnname);
6679 fputs (":\n", file);
6682 /* Stop mips_file_end from treating this function as external. */
6683 if (TARGET_IRIX && mips_abi == ABI_32)
6684 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6686 if (!flag_inhibit_size_directive)
6688 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6690 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6691 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6692 ", args= " HOST_WIDE_INT_PRINT_DEC
6693 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6694 (reg_names[(frame_pointer_needed)
6695 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6696 ((frame_pointer_needed && TARGET_MIPS16)
6697 ? tsize - cfun->machine->frame.args_size
6699 reg_names[GP_REG_FIRST + 31],
6700 cfun->machine->frame.var_size,
6701 cfun->machine->frame.num_gp,
6702 cfun->machine->frame.num_fp,
6703 cfun->machine->frame.args_size,
6704 cfun->machine->frame.cprestore_size);
6706 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6707 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6708 cfun->machine->frame.mask,
6709 cfun->machine->frame.gp_save_offset);
6710 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6711 cfun->machine->frame.fmask,
6712 cfun->machine->frame.fp_save_offset);
6715 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6716 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6719 if (mips_current_loadgp_style () == LOADGP_OLDABI)
6721 /* Handle the initialization of $gp for SVR4 PIC. */
6722 if (!cfun->machine->all_noreorder_p)
6723 output_asm_insn ("%(.cpload\t%^%)", 0);
6725 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6727 else if (cfun->machine->all_noreorder_p)
6728 output_asm_insn ("%(%<", 0);
6730 /* Tell the assembler which register we're using as the global
6731 pointer. This is needed for thunks, since they can use either
6732 explicit relocs or assembler macros. */
6733 mips_output_cplocal ();
6736 /* Make the last instruction frame related and note that it performs
6737 the operation described by FRAME_PATTERN. */
6740 mips_set_frame_expr (rtx frame_pattern)
6744 insn = get_last_insn ();
6745 RTX_FRAME_RELATED_P (insn) = 1;
6746 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6752 /* Return a frame-related rtx that stores REG at MEM.
6753 REG must be a single register. */
6756 mips_frame_set (rtx mem, rtx reg)
6760 /* If we're saving the return address register and the dwarf return
6761 address column differs from the hard register number, adjust the
6762 note reg to refer to the former. */
6763 if (REGNO (reg) == GP_REG_FIRST + 31
6764 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6765 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6767 set = gen_rtx_SET (VOIDmode, mem, reg);
6768 RTX_FRAME_RELATED_P (set) = 1;
6774 /* Save register REG to MEM. Make the instruction frame-related. */
6777 mips_save_reg (rtx reg, rtx mem)
6779 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6783 if (mips_split_64bit_move_p (mem, reg))
6784 mips_split_64bit_move (mem, reg);
6786 emit_move_insn (mem, reg);
6788 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6789 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6790 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6795 && REGNO (reg) != GP_REG_FIRST + 31
6796 && !M16_REG_P (REGNO (reg)))
6798 /* Save a non-mips16 register by moving it through a temporary.
6799 We don't need to do this for $31 since there's a special
6800 instruction for it. */
6801 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6802 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6805 emit_move_insn (mem, reg);
6807 mips_set_frame_expr (mips_frame_set (mem, reg));
6812 /* Expand the prologue into a bunch of separate insns. */
6815 mips_expand_prologue (void)
6819 if (cfun->machine->global_pointer > 0)
6820 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6822 size = compute_frame_size (get_frame_size ());
6824 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6825 bytes beforehand; this is enough to cover the register save area
6826 without going out of range. */
6827 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6829 HOST_WIDE_INT step1;
6831 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6832 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6834 GEN_INT (-step1)))) = 1;
6836 mips_for_each_saved_reg (size, mips_save_reg);
6839 /* Allocate the rest of the frame. */
6842 if (SMALL_OPERAND (-size))
6843 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6845 GEN_INT (-size)))) = 1;
6848 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6851 /* There are no instructions to add or subtract registers
6852 from the stack pointer, so use the frame pointer as a
6853 temporary. We should always be using a frame pointer
6854 in this case anyway. */
6855 gcc_assert (frame_pointer_needed);
6856 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6857 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6858 hard_frame_pointer_rtx,
6859 MIPS_PROLOGUE_TEMP (Pmode)));
6860 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6863 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6865 MIPS_PROLOGUE_TEMP (Pmode)));
6867 /* Describe the combined effect of the previous instructions. */
6869 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6870 plus_constant (stack_pointer_rtx, -size)));
6874 /* Set up the frame pointer, if we're using one. In mips16 code,
6875 we point the frame pointer ahead of the outgoing argument area.
6876 This should allow more variables & incoming arguments to be
6877 accessed with unextended instructions. */
6878 if (frame_pointer_needed)
6880 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6882 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6883 if (SMALL_OPERAND (cfun->machine->frame.args_size))
6885 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6890 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6891 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6892 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6893 hard_frame_pointer_rtx,
6894 MIPS_PROLOGUE_TEMP (Pmode)));
6896 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6897 plus_constant (stack_pointer_rtx,
6898 cfun->machine->frame.args_size)));
6902 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6903 stack_pointer_rtx)) = 1;
6906 mips_emit_loadgp ();
6908 /* If generating o32/o64 abicalls, save $gp on the stack. */
6909 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6910 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6912 /* If we are profiling, make sure no instructions are scheduled before
6913 the call to mcount. */
6915 if (current_function_profile)
6916 emit_insn (gen_blockage ());
6919 /* Do any necessary cleanup after a function to restore stack, frame,
6922 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6925 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6926 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6928 /* Reinstate the normal $gp. */
6929 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6930 mips_output_cplocal ();
6932 if (cfun->machine->all_noreorder_p)
6934 /* Avoid using %>%) since it adds excess whitespace. */
6935 output_asm_insn (".set\tmacro", 0);
6936 output_asm_insn (".set\treorder", 0);
6937 set_noreorder = set_nomacro = 0;
6940 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6944 /* Get the function name the same way that toplev.c does before calling
6945 assemble_start_function. This is needed so that the name used here
6946 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6947 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6948 fputs ("\t.end\t", file);
6949 assemble_name (file, fnname);
6954 /* Emit instructions to restore register REG from slot MEM. */
6957 mips_restore_reg (rtx reg, rtx mem)
6959 /* There's no mips16 instruction to load $31 directly. Load into
6960 $7 instead and adjust the return insn appropriately. */
6961 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6962 reg = gen_rtx_REG (GET_MODE (reg), 7);
6964 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6966 /* Can't restore directly; move through a temporary. */
6967 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6968 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6971 emit_move_insn (reg, mem);
6975 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6976 if this epilogue precedes a sibling call, false if it is for a normal
6977 "epilogue" pattern. */
6980 mips_expand_epilogue (int sibcall_p)
6982 HOST_WIDE_INT step1, step2;
6985 if (!sibcall_p && mips_can_use_return_insn ())
6987 emit_jump_insn (gen_return ());
6991 /* Split the frame into two. STEP1 is the amount of stack we should
6992 deallocate before restoring the registers. STEP2 is the amount we
6993 should deallocate afterwards.
6995 Start off by assuming that no registers need to be restored. */
6996 step1 = cfun->machine->frame.total_size;
6999 /* Work out which register holds the frame address. Account for the
7000 frame pointer offset used by mips16 code. */
7001 if (!frame_pointer_needed)
7002 base = stack_pointer_rtx;
7005 base = hard_frame_pointer_rtx;
7007 step1 -= cfun->machine->frame.args_size;
7010 /* If we need to restore registers, deallocate as much stack as
7011 possible in the second step without going out of range. */
7012 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7014 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7018 /* Set TARGET to BASE + STEP1. */
7024 /* Get an rtx for STEP1 that we can add to BASE. */
7025 adjust = GEN_INT (step1);
7026 if (!SMALL_OPERAND (step1))
7028 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7029 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7032 /* Normal mode code can copy the result straight into $sp. */
7034 target = stack_pointer_rtx;
7036 emit_insn (gen_add3_insn (target, base, adjust));
7039 /* Copy TARGET into the stack pointer. */
7040 if (target != stack_pointer_rtx)
7041 emit_move_insn (stack_pointer_rtx, target);
7043 /* If we're using addressing macros for n32/n64 abicalls, $gp is
7044 implicitly used by all SYMBOL_REFs. We must emit a blockage
7045 insn before restoring it. */
7046 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7047 emit_insn (gen_blockage ());
7049 /* Restore the registers. */
7050 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7053 /* Deallocate the final bit of the frame. */
7055 emit_insn (gen_add3_insn (stack_pointer_rtx,
7059 /* Add in the __builtin_eh_return stack adjustment. We need to
7060 use a temporary in mips16 code. */
7061 if (current_function_calls_eh_return)
7065 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7066 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7067 MIPS_EPILOGUE_TEMP (Pmode),
7068 EH_RETURN_STACKADJ_RTX));
7069 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7072 emit_insn (gen_add3_insn (stack_pointer_rtx,
7074 EH_RETURN_STACKADJ_RTX));
7079 /* The mips16 loads the return address into $7, not $31. */
7080 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7081 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7082 GP_REG_FIRST + 7)));
7084 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7085 GP_REG_FIRST + 31)));
7089 /* Return nonzero if this function is known to have a null epilogue.
7090 This allows the optimizer to omit jumps to jumps if no stack
7094 mips_can_use_return_insn (void)
7098 if (! reload_completed)
7101 if (regs_ever_live[31] || current_function_profile)
7104 return_type = DECL_RESULT (current_function_decl);
7106 /* In mips16 mode, a function which returns a floating point value
7107 needs to arrange to copy the return value into the floating point
7110 && mips16_hard_float
7111 && ! aggregate_value_p (return_type, current_function_decl)
7112 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7113 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7116 if (cfun->machine->frame.initialized)
7117 return cfun->machine->frame.total_size == 0;
7119 return compute_frame_size (get_frame_size ()) == 0;
7122 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7123 in order to avoid duplicating too much logic from elsewhere. */
7126 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7127 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7130 rtx this, temp1, temp2, insn, fnaddr;
7132 /* Pretend to be a post-reload pass while generating rtl. */
7134 reload_completed = 1;
7135 reset_block_changes ();
7137 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7138 for TARGET_NEWABI since the latter is a call-saved register. */
7139 if (TARGET_ABICALLS)
7140 cfun->machine->global_pointer
7141 = REGNO (pic_offset_table_rtx)
7142 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7144 /* Set up the global pointer for n32 or n64 abicalls. */
7145 mips_emit_loadgp ();
7147 /* We need two temporary registers in some cases. */
7148 temp1 = gen_rtx_REG (Pmode, 2);
7149 temp2 = gen_rtx_REG (Pmode, 3);
7151 /* Find out which register contains the "this" pointer. */
7152 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7153 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7155 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7157 /* Add DELTA to THIS. */
7160 rtx offset = GEN_INT (delta);
7161 if (!SMALL_OPERAND (delta))
7163 emit_move_insn (temp1, offset);
7166 emit_insn (gen_add3_insn (this, this, offset));
7169 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7170 if (vcall_offset != 0)
7174 /* Set TEMP1 to *THIS. */
7175 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7177 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7178 addr = mips_add_offset (temp2, temp1, vcall_offset);
7180 /* Load the offset and add it to THIS. */
7181 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7182 emit_insn (gen_add3_insn (this, this, temp1));
7185 /* Jump to the target function. Use a sibcall if direct jumps are
7186 allowed, otherwise load the address into a register first. */
7187 fnaddr = XEXP (DECL_RTL (function), 0);
7188 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7190 /* This is messy. gas treats "la $25,foo" as part of a call
7191 sequence and may allow a global "foo" to be lazily bound.
7192 The general move patterns therefore reject this combination.
7194 In this context, lazy binding would actually be OK for o32 and o64,
7195 but it's still wrong for n32 and n64; see mips_load_call_address.
7196 We must therefore load the address via a temporary register if
7197 mips_dangerous_for_la25_p.
7199 If we jump to the temporary register rather than $25, the assembler
7200 can use the move insn to fill the jump's delay slot. */
7201 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7202 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7203 mips_load_call_address (temp1, fnaddr, true);
7205 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7206 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7207 emit_jump_insn (gen_indirect_jump (temp1));
7211 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7212 SIBLING_CALL_P (insn) = 1;
7215 /* Run just enough of rest_of_compilation. This sequence was
7216 "borrowed" from alpha.c. */
7217 insn = get_insns ();
7218 insn_locators_initialize ();
7219 split_all_insns_noflow ();
7221 mips16_lay_out_constants ();
7222 shorten_branches (insn);
7223 final_start_function (insn, file, 1);
7224 final (insn, file, 1);
7225 final_end_function ();
7227 /* Clean up the vars set above. Note that final_end_function resets
7228 the global pointer for us. */
7229 reload_completed = 0;
7233 /* Returns nonzero if X contains a SYMBOL_REF. */
7236 symbolic_expression_p (rtx x)
7238 if (GET_CODE (x) == SYMBOL_REF)
7241 if (GET_CODE (x) == CONST)
7242 return symbolic_expression_p (XEXP (x, 0));
7245 return symbolic_expression_p (XEXP (x, 0));
7247 if (ARITHMETIC_P (x))
7248 return (symbolic_expression_p (XEXP (x, 0))
7249 || symbolic_expression_p (XEXP (x, 1)));
7254 /* Choose the section to use for the constant rtx expression X that has
7258 mips_select_rtx_section (enum machine_mode mode, rtx x,
7259 unsigned HOST_WIDE_INT align)
7263 /* In mips16 mode, the constant table always goes in the same section
7264 as the function, so that constants can be loaded using PC relative
7266 return function_section (current_function_decl);
7268 else if (TARGET_EMBEDDED_DATA)
7270 /* For embedded applications, always put constants in read-only data,
7271 in order to reduce RAM usage. */
7272 return mergeable_constant_section (mode, align, 0);
7276 /* For hosted applications, always put constants in small data if
7277 possible, as this gives the best performance. */
7278 /* ??? Consider using mergeable small data sections. */
7280 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7281 && mips_section_threshold > 0)
7282 return get_named_section (NULL, ".sdata", 0);
7283 else if (flag_pic && symbolic_expression_p (x))
7284 return get_named_section (NULL, ".data.rel.ro", 3);
7286 return mergeable_constant_section (mode, align, 0);
7290 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7292 The complication here is that, with the combination TARGET_ABICALLS
7293 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7294 therefore not be included in the read-only part of a DSO. Handle such
7295 cases by selecting a normal data section instead of a read-only one.
7296 The logic apes that in default_function_rodata_section. */
7299 mips_function_rodata_section (tree decl)
7301 if (!TARGET_ABICALLS || TARGET_GPWORD)
7302 return default_function_rodata_section (decl);
7304 if (decl && DECL_SECTION_NAME (decl))
7306 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7307 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7309 char *rname = ASTRDUP (name);
7311 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7313 else if (flag_function_sections && flag_data_sections
7314 && strncmp (name, ".text.", 6) == 0)
7316 char *rname = ASTRDUP (name);
7317 memcpy (rname + 1, "data", 4);
7318 return get_section (rname, SECTION_WRITE, decl);
7321 return data_section;
7324 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
7325 locally-defined objects go in a small data section. It also controls
7326 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
7327 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
7330 mips_in_small_data_p (tree decl)
7334 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7337 /* We don't yet generate small-data references for -mabicalls. See related
7338 -G handling in override_options. */
7339 if (TARGET_ABICALLS)
7342 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7346 /* Reject anything that isn't in a known small-data section. */
7347 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7348 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7351 /* If a symbol is defined externally, the assembler will use the
7352 usual -G rules when deciding how to implement macros. */
7353 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7356 else if (TARGET_EMBEDDED_DATA)
7358 /* Don't put constants into the small data section: we want them
7359 to be in ROM rather than RAM. */
7360 if (TREE_CODE (decl) != VAR_DECL)
7363 if (TREE_READONLY (decl)
7364 && !TREE_SIDE_EFFECTS (decl)
7365 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7369 size = int_size_in_bytes (TREE_TYPE (decl));
7370 return (size > 0 && size <= mips_section_threshold);
7373 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7374 anchors for small data: the GP register acts as an anchor in that
7375 case. We also don't want to use them for PC-relative accesses,
7376 where the PC acts as an anchor. */
7379 mips_use_anchors_for_symbol_p (rtx symbol)
7381 switch (mips_classify_symbol (symbol))
7383 case SYMBOL_CONSTANT_POOL:
7384 case SYMBOL_SMALL_DATA:
7392 /* See whether VALTYPE is a record whose fields should be returned in
7393 floating-point registers. If so, return the number of fields and
7394 list them in FIELDS (which should have two elements). Return 0
7397 For n32 & n64, a structure with one or two fields is returned in
7398 floating-point registers as long as every field has a floating-point
7402 mips_fpr_return_fields (tree valtype, tree *fields)
7410 if (TREE_CODE (valtype) != RECORD_TYPE)
7414 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7416 if (TREE_CODE (field) != FIELD_DECL)
7419 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7425 fields[i++] = field;
7431 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7432 a value in the most significant part of $2/$3 if:
7434 - the target is big-endian;
7436 - the value has a structure or union type (we generalize this to
7437 cover aggregates from other languages too); and
7439 - the structure is not returned in floating-point registers. */
7442 mips_return_in_msb (tree valtype)
7446 return (TARGET_NEWABI
7447 && TARGET_BIG_ENDIAN
7448 && AGGREGATE_TYPE_P (valtype)
7449 && mips_fpr_return_fields (valtype, fields) == 0);
7453 /* Return a composite value in a pair of floating-point registers.
7454 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7455 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7458 For n32 & n64, $f0 always holds the first value and $f2 the second.
7459 Otherwise the values are packed together as closely as possible. */
7462 mips_return_fpr_pair (enum machine_mode mode,
7463 enum machine_mode mode1, HOST_WIDE_INT offset1,
7464 enum machine_mode mode2, HOST_WIDE_INT offset2)
7468 inc = (TARGET_NEWABI ? 2 : FP_INC);
7469 return gen_rtx_PARALLEL
7472 gen_rtx_EXPR_LIST (VOIDmode,
7473 gen_rtx_REG (mode1, FP_RETURN),
7475 gen_rtx_EXPR_LIST (VOIDmode,
7476 gen_rtx_REG (mode2, FP_RETURN + inc),
7477 GEN_INT (offset2))));
7482 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7483 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7484 VALTYPE is null and MODE is the mode of the return value. */
7487 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7488 enum machine_mode mode)
7495 mode = TYPE_MODE (valtype);
7496 unsignedp = TYPE_UNSIGNED (valtype);
7498 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7499 true, we must promote the mode just as PROMOTE_MODE does. */
7500 mode = promote_mode (valtype, mode, &unsignedp, 1);
7502 /* Handle structures whose fields are returned in $f0/$f2. */
7503 switch (mips_fpr_return_fields (valtype, fields))
7506 return gen_rtx_REG (mode, FP_RETURN);
7509 return mips_return_fpr_pair (mode,
7510 TYPE_MODE (TREE_TYPE (fields[0])),
7511 int_byte_position (fields[0]),
7512 TYPE_MODE (TREE_TYPE (fields[1])),
7513 int_byte_position (fields[1]));
7516 /* If a value is passed in the most significant part of a register, see
7517 whether we have to round the mode up to a whole number of words. */
7518 if (mips_return_in_msb (valtype))
7520 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7521 if (size % UNITS_PER_WORD != 0)
7523 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7524 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7528 /* For EABI, the class of return register depends entirely on MODE.
7529 For example, "struct { some_type x; }" and "union { some_type x; }"
7530 are returned in the same way as a bare "some_type" would be.
7531 Other ABIs only use FPRs for scalar, complex or vector types. */
7532 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7533 return gen_rtx_REG (mode, GP_RETURN);
7536 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7537 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7538 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7539 return gen_rtx_REG (mode, FP_RETURN);
7541 /* Handle long doubles for n32 & n64. */
7543 return mips_return_fpr_pair (mode,
7545 DImode, GET_MODE_SIZE (mode) / 2);
7547 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7548 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7549 return mips_return_fpr_pair (mode,
7550 GET_MODE_INNER (mode), 0,
7551 GET_MODE_INNER (mode),
7552 GET_MODE_SIZE (mode) / 2);
7554 return gen_rtx_REG (mode, GP_RETURN);
7557 /* Return nonzero when an argument must be passed by reference. */
7560 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7561 enum machine_mode mode, tree type,
7562 bool named ATTRIBUTE_UNUSED)
7564 if (mips_abi == ABI_EABI)
7568 /* ??? How should SCmode be handled? */
7569 if (mode == DImode || mode == DFmode)
7572 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
7573 return size == -1 || size > UNITS_PER_WORD;
7577 /* If we have a variable-sized parameter, we have no choice. */
7578 return targetm.calls.must_pass_in_stack (mode, type);
7583 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7584 enum machine_mode mode ATTRIBUTE_UNUSED,
7585 tree type ATTRIBUTE_UNUSED, bool named)
7587 return mips_abi == ABI_EABI && named;
7590 /* Return true if registers of class CLASS cannot change from mode FROM
7594 mips_cannot_change_mode_class (enum machine_mode from,
7595 enum machine_mode to, enum reg_class class)
7597 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7598 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7600 if (TARGET_BIG_ENDIAN)
7602 /* When a multi-word value is stored in paired floating-point
7603 registers, the first register always holds the low word.
7604 We therefore can't allow FPRs to change between single-word
7605 and multi-word modes. */
7606 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7611 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7612 in LO and HI, the high word always comes first. We therefore
7613 can't allow values stored in HI to change between single-word
7614 and multi-word modes.
7615 This rule applies to both the original HI/LO pair and the new
7616 DSP accumulators. */
7617 if (reg_classes_intersect_p (ACC_REGS, class))
7621 /* Loading a 32-bit value into a 64-bit floating-point register
7622 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7623 We can't allow 64-bit float registers to change from SImode to
7627 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7628 && reg_classes_intersect_p (FP_REGS, class))
7633 /* Return true if X should not be moved directly into register $25.
7634 We need this because many versions of GAS will treat "la $25,foo" as
7635 part of a call sequence and so allow a global "foo" to be lazily bound. */
7638 mips_dangerous_for_la25_p (rtx x)
7640 HOST_WIDE_INT offset;
7642 if (TARGET_EXPLICIT_RELOCS)
7645 mips_split_const (x, &x, &offset);
7646 return global_got_operand (x, VOIDmode);
7649 /* Implement PREFERRED_RELOAD_CLASS. */
7652 mips_preferred_reload_class (rtx x, enum reg_class class)
7654 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7657 if (TARGET_HARD_FLOAT
7658 && FLOAT_MODE_P (GET_MODE (x))
7659 && reg_class_subset_p (FP_REGS, class))
7662 if (reg_class_subset_p (GR_REGS, class))
7665 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7671 /* This function returns the register class required for a secondary
7672 register when copying between one of the registers in CLASS, and X,
7673 using MODE. If IN_P is nonzero, the copy is going from X to the
7674 register, otherwise the register is the source. A return value of
7675 NO_REGS means that no secondary register is required. */
7678 mips_secondary_reload_class (enum reg_class class,
7679 enum machine_mode mode, rtx x, int in_p)
7681 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7685 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7686 regno = true_regnum (x);
7688 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7690 if (mips_dangerous_for_la25_p (x))
7693 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7697 /* Copying from HI or LO to anywhere other than a general register
7698 requires a general register.
7699 This rule applies to both the original HI/LO pair and the new
7700 DSP accumulators. */
7701 if (reg_class_subset_p (class, ACC_REGS))
7703 if (TARGET_MIPS16 && in_p)
7705 /* We can't really copy to HI or LO at all in mips16 mode. */
7708 return gp_reg_p ? NO_REGS : gr_regs;
7710 if (ACC_REG_P (regno))
7712 if (TARGET_MIPS16 && ! in_p)
7714 /* We can't really copy to HI or LO at all in mips16 mode. */
7717 return class == gr_regs ? NO_REGS : gr_regs;
7720 /* We can only copy a value to a condition code register from a
7721 floating point register, and even then we require a scratch
7722 floating point register. We can only copy a value out of a
7723 condition code register into a general register. */
7724 if (class == ST_REGS)
7728 return gp_reg_p ? NO_REGS : gr_regs;
7730 if (ST_REG_P (regno))
7734 return class == gr_regs ? NO_REGS : gr_regs;
7737 if (class == FP_REGS)
7741 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7744 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7746 /* We can use the l.s and l.d macros to load floating-point
7747 constants. ??? For l.s, we could probably get better
7748 code by returning GR_REGS here. */
7751 else if (gp_reg_p || x == CONST0_RTX (mode))
7753 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7756 else if (FP_REG_P (regno))
7758 /* In this case we can use mov.s or mov.d. */
7763 /* Otherwise, we need to reload through an integer register. */
7768 /* In mips16 mode, going between memory and anything but M16_REGS
7769 requires an M16_REG. */
7772 if (class != M16_REGS && class != M16_NA_REGS)
7780 if (class == M16_REGS || class == M16_NA_REGS)
7789 /* Implement CLASS_MAX_NREGS.
7791 Usually all registers are word-sized. The only supported exception
7792 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7793 registers. A word-based calculation is correct even in that case,
7794 since -msingle-float disallows multi-FPR values.
7796 The FP status registers are an exception to this rule. They are always
7797 4 bytes wide as they only hold condition code modes, and CCmode is always
7798 considered to be 4 bytes wide. */
7801 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7802 enum machine_mode mode)
7804 if (class == ST_REGS)
7805 return (GET_MODE_SIZE (mode) + 3) / 4;
7807 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7811 mips_valid_pointer_mode (enum machine_mode mode)
7813 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7816 /* Target hook for vector_mode_supported_p. */
7819 mips_vector_mode_supported_p (enum machine_mode mode)
7824 return TARGET_PAIRED_SINGLE_FLOAT;
7835 /* If we can access small data directly (using gp-relative relocation
7836 operators) return the small data pointer, otherwise return null.
7838 For each mips16 function which refers to GP relative symbols, we
7839 use a pseudo register, initialized at the start of the function, to
7840 hold the $gp value. */
7843 mips16_gp_pseudo_reg (void)
7845 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7850 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7852 /* We want to initialize this to a value which gcc will believe
7855 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7856 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7857 gen_rtx_CONST (Pmode, unspec));
7858 insn = get_insns ();
7861 push_topmost_sequence ();
7862 /* We need to emit the initialization after the FUNCTION_BEG
7863 note, so that it will be integrated. */
7864 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7866 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7868 if (scan == NULL_RTX)
7869 scan = get_insns ();
7870 insn = emit_insn_after (insn, scan);
7871 pop_topmost_sequence ();
7874 return cfun->machine->mips16_gp_pseudo_rtx;
7877 /* Write out code to move floating point arguments in or out of
7878 general registers. Output the instructions to FILE. FP_CODE is
7879 the code describing which arguments are present (see the comment at
7880 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7881 we are copying from the floating point registers. */
7884 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7890 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7891 gcc_assert (TARGET_OLDABI);
7897 gparg = GP_ARG_FIRST;
7898 fparg = FP_ARG_FIRST;
7899 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7903 if ((fparg & 1) != 0)
7905 fprintf (file, "\t%s\t%s,%s\n", s,
7906 reg_names[gparg], reg_names[fparg]);
7908 else if ((f & 3) == 2)
7911 fprintf (file, "\td%s\t%s,%s\n", s,
7912 reg_names[gparg], reg_names[fparg]);
7915 if ((fparg & 1) != 0)
7917 if (TARGET_BIG_ENDIAN)
7918 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7919 reg_names[gparg], reg_names[fparg + 1], s,
7920 reg_names[gparg + 1], reg_names[fparg]);
7922 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7923 reg_names[gparg], reg_names[fparg], s,
7924 reg_names[gparg + 1], reg_names[fparg + 1]);
7937 /* Build a mips16 function stub. This is used for functions which
7938 take arguments in the floating point registers. It is 32 bit code
7939 that moves the floating point args into the general registers, and
7940 then jumps to the 16 bit code. */
7943 build_mips16_function_stub (FILE *file)
7946 char *secname, *stubname;
7947 tree stubid, stubdecl;
7951 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7952 secname = (char *) alloca (strlen (fnname) + 20);
7953 sprintf (secname, ".mips16.fn.%s", fnname);
7954 stubname = (char *) alloca (strlen (fnname) + 20);
7955 sprintf (stubname, "__fn_stub_%s", fnname);
7956 stubid = get_identifier (stubname);
7957 stubdecl = build_decl (FUNCTION_DECL, stubid,
7958 build_function_type (void_type_node, NULL_TREE));
7959 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7961 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7963 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7965 fprintf (file, "%s%s",
7966 need_comma ? ", " : "",
7967 (f & 3) == 1 ? "float" : "double");
7970 fprintf (file, ")\n");
7972 fprintf (file, "\t.set\tnomips16\n");
7973 switch_to_section (function_section (stubdecl));
7974 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7976 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7977 within a .ent, and we cannot emit another .ent. */
7978 if (!FUNCTION_NAME_ALREADY_DECLARED)
7980 fputs ("\t.ent\t", file);
7981 assemble_name (file, stubname);
7985 assemble_name (file, stubname);
7986 fputs (":\n", file);
7988 /* We don't want the assembler to insert any nops here. */
7989 fprintf (file, "\t.set\tnoreorder\n");
7991 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7993 fprintf (asm_out_file, "\t.set\tnoat\n");
7994 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7995 assemble_name (file, fnname);
7996 fprintf (file, "\n");
7997 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7998 fprintf (asm_out_file, "\t.set\tat\n");
8000 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8001 with one of the mfc1 instructions, because the result is not
8002 available for one instruction, so if the very first instruction
8003 in the function refers to the register, it will see the wrong
8005 fprintf (file, "\tnop\n");
8007 fprintf (file, "\t.set\treorder\n");
8009 if (!FUNCTION_NAME_ALREADY_DECLARED)
8011 fputs ("\t.end\t", file);
8012 assemble_name (file, stubname);
8016 fprintf (file, "\t.set\tmips16\n");
8018 switch_to_section (function_section (current_function_decl));
8021 /* We keep a list of functions for which we have already built stubs
8022 in build_mips16_call_stub. */
8026 struct mips16_stub *next;
8031 static struct mips16_stub *mips16_stubs;
8033 /* Build a call stub for a mips16 call. A stub is needed if we are
8034 passing any floating point values which should go into the floating
8035 point registers. If we are, and the call turns out to be to a 32
8036 bit function, the stub will be used to move the values into the
8037 floating point registers before calling the 32 bit function. The
8038 linker will magically adjust the function call to either the 16 bit
8039 function or the 32 bit stub, depending upon where the function call
8040 is actually defined.
8042 Similarly, we need a stub if the return value might come back in a
8043 floating point register.
8045 RETVAL is the location of the return value, or null if this is
8046 a call rather than a call_value. FN is the address of the
8047 function and ARG_SIZE is the size of the arguments. FP_CODE
8048 is the code built by function_arg. This function returns a nonzero
8049 value if it builds the call instruction itself. */
8052 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8056 char *secname, *stubname;
8057 struct mips16_stub *l;
8058 tree stubid, stubdecl;
8062 /* We don't need to do anything if we aren't in mips16 mode, or if
8063 we were invoked with the -msoft-float option. */
8064 if (! TARGET_MIPS16 || ! mips16_hard_float)
8067 /* Figure out whether the value might come back in a floating point
8069 fpret = (retval != 0
8070 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8071 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8073 /* We don't need to do anything if there were no floating point
8074 arguments and the value will not be returned in a floating point
8076 if (fp_code == 0 && ! fpret)
8079 /* We don't need to do anything if this is a call to a special
8080 mips16 support function. */
8081 if (GET_CODE (fn) == SYMBOL_REF
8082 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8085 /* This code will only work for o32 and o64 abis. The other ABI's
8086 require more sophisticated support. */
8087 gcc_assert (TARGET_OLDABI);
8089 /* We can only handle SFmode and DFmode floating point return
8092 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
8094 /* If we're calling via a function pointer, then we must always call
8095 via a stub. There are magic stubs provided in libgcc.a for each
8096 of the required cases. Each of them expects the function address
8097 to arrive in register $2. */
8099 if (GET_CODE (fn) != SYMBOL_REF)
8105 /* ??? If this code is modified to support other ABI's, we need
8106 to handle PARALLEL return values here. */
8108 sprintf (buf, "__mips16_call_stub_%s%d",
8110 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8113 id = get_identifier (buf);
8114 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8116 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8118 if (retval == NULL_RTX)
8119 insn = gen_call_internal (stub_fn, arg_size);
8121 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8122 insn = emit_call_insn (insn);
8124 /* Put the register usage information on the CALL. */
8125 CALL_INSN_FUNCTION_USAGE (insn) =
8126 gen_rtx_EXPR_LIST (VOIDmode,
8127 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8128 CALL_INSN_FUNCTION_USAGE (insn));
8130 /* If we are handling a floating point return value, we need to
8131 save $18 in the function prologue. Putting a note on the
8132 call will mean that regs_ever_live[$18] will be true if the
8133 call is not eliminated, and we can check that in the prologue
8136 CALL_INSN_FUNCTION_USAGE (insn) =
8137 gen_rtx_EXPR_LIST (VOIDmode,
8138 gen_rtx_USE (VOIDmode,
8139 gen_rtx_REG (word_mode, 18)),
8140 CALL_INSN_FUNCTION_USAGE (insn));
8142 /* Return 1 to tell the caller that we've generated the call
8147 /* We know the function we are going to call. If we have already
8148 built a stub, we don't need to do anything further. */
8150 fnname = XSTR (fn, 0);
8151 for (l = mips16_stubs; l != NULL; l = l->next)
8152 if (strcmp (l->name, fnname) == 0)
8157 /* Build a special purpose stub. When the linker sees a
8158 function call in mips16 code, it will check where the target
8159 is defined. If the target is a 32 bit call, the linker will
8160 search for the section defined here. It can tell which
8161 symbol this section is associated with by looking at the
8162 relocation information (the name is unreliable, since this
8163 might be a static function). If such a section is found, the
8164 linker will redirect the call to the start of the magic
8167 If the function does not return a floating point value, the
8168 special stub section is named
8171 If the function does return a floating point value, the stub
8173 .mips16.call.fp.FNNAME
8176 secname = (char *) alloca (strlen (fnname) + 40);
8177 sprintf (secname, ".mips16.call.%s%s",
8180 stubname = (char *) alloca (strlen (fnname) + 20);
8181 sprintf (stubname, "__call_stub_%s%s",
8184 stubid = get_identifier (stubname);
8185 stubdecl = build_decl (FUNCTION_DECL, stubid,
8186 build_function_type (void_type_node, NULL_TREE));
8187 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8189 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8191 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8195 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8197 fprintf (asm_out_file, "%s%s",
8198 need_comma ? ", " : "",
8199 (f & 3) == 1 ? "float" : "double");
8202 fprintf (asm_out_file, ")\n");
8204 fprintf (asm_out_file, "\t.set\tnomips16\n");
8205 assemble_start_function (stubdecl, stubname);
8207 if (!FUNCTION_NAME_ALREADY_DECLARED)
8209 fputs ("\t.ent\t", asm_out_file);
8210 assemble_name (asm_out_file, stubname);
8211 fputs ("\n", asm_out_file);
8213 assemble_name (asm_out_file, stubname);
8214 fputs (":\n", asm_out_file);
8217 /* We build the stub code by hand. That's the only way we can
8218 do it, since we can't generate 32 bit code during a 16 bit
8221 /* We don't want the assembler to insert any nops here. */
8222 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8224 mips16_fp_args (asm_out_file, fp_code, 0);
8228 fprintf (asm_out_file, "\t.set\tnoat\n");
8229 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8231 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8232 fprintf (asm_out_file, "\t.set\tat\n");
8233 /* Unfortunately, we can't fill the jump delay slot. We
8234 can't fill with one of the mtc1 instructions, because the
8235 result is not available for one instruction, so if the
8236 very first instruction in the function refers to the
8237 register, it will see the wrong value. */
8238 fprintf (asm_out_file, "\tnop\n");
8242 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8243 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8244 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8245 /* As above, we can't fill the delay slot. */
8246 fprintf (asm_out_file, "\tnop\n");
8247 if (GET_MODE (retval) == SFmode)
8248 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8249 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8252 if (TARGET_BIG_ENDIAN)
8254 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8255 reg_names[GP_REG_FIRST + 2],
8256 reg_names[FP_REG_FIRST + 1]);
8257 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8258 reg_names[GP_REG_FIRST + 3],
8259 reg_names[FP_REG_FIRST + 0]);
8263 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8264 reg_names[GP_REG_FIRST + 2],
8265 reg_names[FP_REG_FIRST + 0]);
8266 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8267 reg_names[GP_REG_FIRST + 3],
8268 reg_names[FP_REG_FIRST + 1]);
8271 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8272 /* As above, we can't fill the delay slot. */
8273 fprintf (asm_out_file, "\tnop\n");
8276 fprintf (asm_out_file, "\t.set\treorder\n");
8278 #ifdef ASM_DECLARE_FUNCTION_SIZE
8279 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8282 if (!FUNCTION_NAME_ALREADY_DECLARED)
8284 fputs ("\t.end\t", asm_out_file);
8285 assemble_name (asm_out_file, stubname);
8286 fputs ("\n", asm_out_file);
8289 fprintf (asm_out_file, "\t.set\tmips16\n");
8291 /* Record this stub. */
8292 l = (struct mips16_stub *) xmalloc (sizeof *l);
8293 l->name = xstrdup (fnname);
8295 l->next = mips16_stubs;
8299 /* If we expect a floating point return value, but we've built a
8300 stub which does not expect one, then we're in trouble. We can't
8301 use the existing stub, because it won't handle the floating point
8302 value. We can't build a new stub, because the linker won't know
8303 which stub to use for the various calls in this object file.
8304 Fortunately, this case is illegal, since it means that a function
8305 was declared in two different ways in a single compilation. */
8306 if (fpret && ! l->fpret)
8307 error ("cannot handle inconsistent calls to %qs", fnname);
8309 /* If we are calling a stub which handles a floating point return
8310 value, we need to arrange to save $18 in the prologue. We do
8311 this by marking the function call as using the register. The
8312 prologue will later see that it is used, and emit code to save
8319 if (retval == NULL_RTX)
8320 insn = gen_call_internal (fn, arg_size);
8322 insn = gen_call_value_internal (retval, fn, arg_size);
8323 insn = emit_call_insn (insn);
8325 CALL_INSN_FUNCTION_USAGE (insn) =
8326 gen_rtx_EXPR_LIST (VOIDmode,
8327 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8328 CALL_INSN_FUNCTION_USAGE (insn));
8330 /* Return 1 to tell the caller that we've generated the call
8335 /* Return 0 to let the caller generate the call insn. */
8339 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8340 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8342 struct mips16_constant {
8343 struct mips16_constant *next;
8346 enum machine_mode mode;
8349 /* Information about an incomplete mips16 constant pool. FIRST is the
8350 first constant, HIGHEST_ADDRESS is the highest address that the first
8351 byte of the pool can have, and INSN_ADDRESS is the current instruction
8354 struct mips16_constant_pool {
8355 struct mips16_constant *first;
8356 int highest_address;
8360 /* Add constant VALUE to POOL and return its label. MODE is the
8361 value's mode (used for CONST_INTs, etc.). */
8364 add_constant (struct mips16_constant_pool *pool,
8365 rtx value, enum machine_mode mode)
8367 struct mips16_constant **p, *c;
8368 bool first_of_size_p;
8370 /* See whether the constant is already in the pool. If so, return the
8371 existing label, otherwise leave P pointing to the place where the
8372 constant should be added.
8374 Keep the pool sorted in increasing order of mode size so that we can
8375 reduce the number of alignments needed. */
8376 first_of_size_p = true;
8377 for (p = &pool->first; *p != 0; p = &(*p)->next)
8379 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8381 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8383 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8384 first_of_size_p = false;
8387 /* In the worst case, the constant needed by the earliest instruction
8388 will end up at the end of the pool. The entire pool must then be
8389 accessible from that instruction.
8391 When adding the first constant, set the pool's highest address to
8392 the address of the first out-of-range byte. Adjust this address
8393 downwards each time a new constant is added. */
8394 if (pool->first == 0)
8395 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8396 is the address of the instruction with the lowest two bits clear.
8397 The base PC value for ld has the lowest three bits clear. Assume
8398 the worst case here. */
8399 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8400 pool->highest_address -= GET_MODE_SIZE (mode);
8401 if (first_of_size_p)
8402 /* Take into account the worst possible padding due to alignment. */
8403 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8405 /* Create a new entry. */
8406 c = (struct mips16_constant *) xmalloc (sizeof *c);
8409 c->label = gen_label_rtx ();
8416 /* Output constant VALUE after instruction INSN and return the last
8417 instruction emitted. MODE is the mode of the constant. */
8420 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8422 switch (GET_MODE_CLASS (mode))
8426 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8427 return emit_insn_after (gen_consttable_int (value, size), insn);
8431 return emit_insn_after (gen_consttable_float (value), insn);
8433 case MODE_VECTOR_FLOAT:
8434 case MODE_VECTOR_INT:
8437 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8438 insn = dump_constants_1 (GET_MODE_INNER (mode),
8439 CONST_VECTOR_ELT (value, i), insn);
8449 /* Dump out the constants in CONSTANTS after INSN. */
8452 dump_constants (struct mips16_constant *constants, rtx insn)
8454 struct mips16_constant *c, *next;
8458 for (c = constants; c != NULL; c = next)
8460 /* If necessary, increase the alignment of PC. */
8461 if (align < GET_MODE_SIZE (c->mode))
8463 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8464 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8466 align = GET_MODE_SIZE (c->mode);
8468 insn = emit_label_after (c->label, insn);
8469 insn = dump_constants_1 (c->mode, c->value, insn);
8475 emit_barrier_after (insn);
8478 /* Return the length of instruction INSN. */
8481 mips16_insn_length (rtx insn)
8485 rtx body = PATTERN (insn);
8486 if (GET_CODE (body) == ADDR_VEC)
8487 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8488 if (GET_CODE (body) == ADDR_DIFF_VEC)
8489 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8491 return get_attr_length (insn);
8494 /* Rewrite *X so that constant pool references refer to the constant's
8495 label instead. DATA points to the constant pool structure. */
8498 mips16_rewrite_pool_refs (rtx *x, void *data)
8500 struct mips16_constant_pool *pool = data;
8501 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8502 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8503 get_pool_constant (*x),
8504 get_pool_mode (*x)));
8508 /* Build MIPS16 constant pools. */
8511 mips16_lay_out_constants (void)
8513 struct mips16_constant_pool pool;
8517 memset (&pool, 0, sizeof (pool));
8518 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8520 /* Rewrite constant pool references in INSN. */
8522 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8524 pool.insn_address += mips16_insn_length (insn);
8526 if (pool.first != NULL)
8528 /* If there are no natural barriers between the first user of
8529 the pool and the highest acceptable address, we'll need to
8530 create a new instruction to jump around the constant pool.
8531 In the worst case, this instruction will be 4 bytes long.
8533 If it's too late to do this transformation after INSN,
8534 do it immediately before INSN. */
8535 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8539 label = gen_label_rtx ();
8541 jump = emit_jump_insn_before (gen_jump (label), insn);
8542 JUMP_LABEL (jump) = label;
8543 LABEL_NUSES (label) = 1;
8544 barrier = emit_barrier_after (jump);
8546 emit_label_after (label, barrier);
8547 pool.insn_address += 4;
8550 /* See whether the constant pool is now out of range of the first
8551 user. If so, output the constants after the previous barrier.
8552 Note that any instructions between BARRIER and INSN (inclusive)
8553 will use negative offsets to refer to the pool. */
8554 if (pool.insn_address > pool.highest_address)
8556 dump_constants (pool.first, barrier);
8560 else if (BARRIER_P (insn))
8564 dump_constants (pool.first, get_last_insn ());
8567 /* A temporary variable used by for_each_rtx callbacks, etc. */
8568 static rtx mips_sim_insn;
8570 /* A structure representing the state of the processor pipeline.
8571 Used by the mips_sim_* family of functions. */
8573 /* The maximum number of instructions that can be issued in a cycle.
8574 (Caches mips_issue_rate.) */
8575 unsigned int issue_rate;
8577 /* The current simulation time. */
8580 /* How many more instructions can be issued in the current cycle. */
8581 unsigned int insns_left;
8583 /* LAST_SET[X].INSN is the last instruction to set register X.
8584 LAST_SET[X].TIME is the time at which that instruction was issued.
8585 INSN is null if no instruction has yet set register X. */
8589 } last_set[FIRST_PSEUDO_REGISTER];
8591 /* The pipeline's current DFA state. */
8595 /* Reset STATE to the initial simulation state. */
8598 mips_sim_reset (struct mips_sim *state)
8601 state->insns_left = state->issue_rate;
8602 memset (&state->last_set, 0, sizeof (state->last_set));
8603 state_reset (state->dfa_state);
8606 /* Initialize STATE before its first use. DFA_STATE points to an
8607 allocated but uninitialized DFA state. */
8610 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8612 state->issue_rate = mips_issue_rate ();
8613 state->dfa_state = dfa_state;
8614 mips_sim_reset (state);
8617 /* Advance STATE by one clock cycle. */
8620 mips_sim_next_cycle (struct mips_sim *state)
8623 state->insns_left = state->issue_rate;
8624 state_transition (state->dfa_state, 0);
8627 /* Advance simulation state STATE until instruction INSN can read
8631 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8635 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8636 if (state->last_set[REGNO (reg) + i].insn != 0)
8640 t = state->last_set[REGNO (reg) + i].time;
8641 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8642 while (state->time < t)
8643 mips_sim_next_cycle (state);
8647 /* A for_each_rtx callback. If *X is a register, advance simulation state
8648 DATA until mips_sim_insn can read the register's value. */
8651 mips_sim_wait_regs_2 (rtx *x, void *data)
8654 mips_sim_wait_reg (data, mips_sim_insn, *x);
8658 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8661 mips_sim_wait_regs_1 (rtx *x, void *data)
8663 for_each_rtx (x, mips_sim_wait_regs_2, data);
8666 /* Advance simulation state STATE until all of INSN's register
8667 dependencies are satisfied. */
8670 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8672 mips_sim_insn = insn;
8673 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8676 /* Advance simulation state STATE until the units required by
8677 instruction INSN are available. */
8680 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8684 tmp_state = alloca (state_size ());
8685 while (state->insns_left == 0
8686 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8687 state_transition (tmp_state, insn) >= 0))
8688 mips_sim_next_cycle (state);
8691 /* Advance simulation state STATE until INSN is ready to issue. */
8694 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8696 mips_sim_wait_regs (state, insn);
8697 mips_sim_wait_units (state, insn);
8700 /* mips_sim_insn has just set X. Update the LAST_SET array
8701 in simulation state DATA. */
8704 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8706 struct mips_sim *state;
8711 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8713 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8714 state->last_set[REGNO (x) + i].time = state->time;
8718 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8719 can issue immediately (i.e., that mips_sim_wait_insn has already
8723 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8725 state_transition (state->dfa_state, insn);
8726 state->insns_left--;
8728 mips_sim_insn = insn;
8729 note_stores (PATTERN (insn), mips_sim_record_set, state);
8732 /* Simulate issuing a NOP in state STATE. */
8735 mips_sim_issue_nop (struct mips_sim *state)
8737 if (state->insns_left == 0)
8738 mips_sim_next_cycle (state);
8739 state->insns_left--;
8742 /* Update simulation state STATE so that it's ready to accept the instruction
8743 after INSN. INSN should be part of the main rtl chain, not a member of a
8747 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8749 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8751 mips_sim_issue_nop (state);
8753 switch (GET_CODE (SEQ_BEGIN (insn)))
8757 /* We can't predict the processor state after a call or label. */
8758 mips_sim_reset (state);
8762 /* The delay slots of branch likely instructions are only executed
8763 when the branch is taken. Therefore, if the caller has simulated
8764 the delay slot instruction, STATE does not really reflect the state
8765 of the pipeline for the instruction after the delay slot. Also,
8766 branch likely instructions tend to incur a penalty when not taken,
8767 so there will probably be an extra delay between the branch and
8768 the instruction after the delay slot. */
8769 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8770 mips_sim_reset (state);
8778 /* The VR4130 pipeline issues aligned pairs of instructions together,
8779 but it stalls the second instruction if it depends on the first.
8780 In order to cut down the amount of logic required, this dependence
8781 check is not based on a full instruction decode. Instead, any non-SPECIAL
8782 instruction is assumed to modify the register specified by bits 20-16
8783 (which is usually the "rt" field).
8785 In beq, beql, bne and bnel instructions, the rt field is actually an
8786 input, so we can end up with a false dependence between the branch
8787 and its delay slot. If this situation occurs in instruction INSN,
8788 try to avoid it by swapping rs and rt. */
8791 vr4130_avoid_branch_rt_conflict (rtx insn)
8795 first = SEQ_BEGIN (insn);
8796 second = SEQ_END (insn);
8798 && NONJUMP_INSN_P (second)
8799 && GET_CODE (PATTERN (first)) == SET
8800 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8801 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8803 /* Check for the right kind of condition. */
8804 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8805 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8806 && REG_P (XEXP (cond, 0))
8807 && REG_P (XEXP (cond, 1))
8808 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8809 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8811 /* SECOND mentions the rt register but not the rs register. */
8812 rtx tmp = XEXP (cond, 0);
8813 XEXP (cond, 0) = XEXP (cond, 1);
8814 XEXP (cond, 1) = tmp;
8819 /* Implement -mvr4130-align. Go through each basic block and simulate the
8820 processor pipeline. If we find that a pair of instructions could execute
8821 in parallel, and the first of those instruction is not 8-byte aligned,
8822 insert a nop to make it aligned. */
8825 vr4130_align_insns (void)
8827 struct mips_sim state;
8828 rtx insn, subinsn, last, last2, next;
8833 /* LAST is the last instruction before INSN to have a nonzero length.
8834 LAST2 is the last such instruction before LAST. */
8838 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8841 mips_sim_init (&state, alloca (state_size ()));
8842 for (insn = get_insns (); insn != 0; insn = next)
8844 unsigned int length;
8846 next = NEXT_INSN (insn);
8848 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8849 This isn't really related to the alignment pass, but we do it on
8850 the fly to avoid a separate instruction walk. */
8851 vr4130_avoid_branch_rt_conflict (insn);
8853 if (USEFUL_INSN_P (insn))
8854 FOR_EACH_SUBINSN (subinsn, insn)
8856 mips_sim_wait_insn (&state, subinsn);
8858 /* If we want this instruction to issue in parallel with the
8859 previous one, make sure that the previous instruction is
8860 aligned. There are several reasons why this isn't worthwhile
8861 when the second instruction is a call:
8863 - Calls are less likely to be performance critical,
8864 - There's a good chance that the delay slot can execute
8865 in parallel with the call.
8866 - The return address would then be unaligned.
8868 In general, if we're going to insert a nop between instructions
8869 X and Y, it's better to insert it immediately after X. That
8870 way, if the nop makes Y aligned, it will also align any labels
8872 if (state.insns_left != state.issue_rate
8873 && !CALL_P (subinsn))
8875 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8877 /* SUBINSN is the first instruction in INSN and INSN is
8878 aligned. We want to align the previous instruction
8879 instead, so insert a nop between LAST2 and LAST.
8881 Note that LAST could be either a single instruction
8882 or a branch with a delay slot. In the latter case,
8883 LAST, like INSN, is already aligned, but the delay
8884 slot must have some extra delay that stops it from
8885 issuing at the same time as the branch. We therefore
8886 insert a nop before the branch in order to align its
8888 emit_insn_after (gen_nop (), last2);
8891 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8893 /* SUBINSN is the delay slot of INSN, but INSN is
8894 currently unaligned. Insert a nop between
8895 LAST and INSN to align it. */
8896 emit_insn_after (gen_nop (), last);
8900 mips_sim_issue_insn (&state, subinsn);
8902 mips_sim_finish_insn (&state, insn);
8904 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8905 length = get_attr_length (insn);
8908 /* If the instruction is an asm statement or multi-instruction
8909 mips.md patern, the length is only an estimate. Insert an
8910 8 byte alignment after it so that the following instructions
8911 can be handled correctly. */
8912 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8913 && (recog_memoized (insn) < 0 || length >= 8))
8915 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8916 next = NEXT_INSN (next);
8917 mips_sim_next_cycle (&state);
8920 else if (length & 4)
8921 aligned_p = !aligned_p;
8926 /* See whether INSN is an aligned label. */
8927 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8933 /* Subroutine of mips_reorg. If there is a hazard between INSN
8934 and a previous instruction, avoid it by inserting nops after
8937 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8938 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8939 before using the value of that register. *HILO_DELAY counts the
8940 number of instructions since the last hilo hazard (that is,
8941 the number of instructions since the last mflo or mfhi).
8943 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8944 for the next instruction.
8946 LO_REG is an rtx for the LO register, used in dependence checking. */
8949 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8950 rtx *delayed_reg, rtx lo_reg)
8958 pattern = PATTERN (insn);
8960 /* Do not put the whole function in .set noreorder if it contains
8961 an asm statement. We don't know whether there will be hazards
8962 between the asm statement and the gcc-generated code. */
8963 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8964 cfun->machine->all_noreorder_p = false;
8966 /* Ignore zero-length instructions (barriers and the like). */
8967 ninsns = get_attr_length (insn) / 4;
8971 /* Work out how many nops are needed. Note that we only care about
8972 registers that are explicitly mentioned in the instruction's pattern.
8973 It doesn't matter that calls use the argument registers or that they
8974 clobber hi and lo. */
8975 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8976 nops = 2 - *hilo_delay;
8977 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8982 /* Insert the nops between this instruction and the previous one.
8983 Each new nop takes us further from the last hilo hazard. */
8984 *hilo_delay += nops;
8986 emit_insn_after (gen_hazard_nop (), after);
8988 /* Set up the state for the next instruction. */
8989 *hilo_delay += ninsns;
8991 if (INSN_CODE (insn) >= 0)
8992 switch (get_attr_hazard (insn))
9002 set = single_set (insn);
9003 gcc_assert (set != 0);
9004 *delayed_reg = SET_DEST (set);
9010 /* Go through the instruction stream and insert nops where necessary.
9011 See if the whole function can then be put into .set noreorder &
9015 mips_avoid_hazards (void)
9017 rtx insn, last_insn, lo_reg, delayed_reg;
9020 /* Force all instructions to be split into their final form. */
9021 split_all_insns_noflow ();
9023 /* Recalculate instruction lengths without taking nops into account. */
9024 cfun->machine->ignore_hazard_length_p = true;
9025 shorten_branches (get_insns ());
9027 cfun->machine->all_noreorder_p = true;
9029 /* Profiled functions can't be all noreorder because the profiler
9030 support uses assembler macros. */
9031 if (current_function_profile)
9032 cfun->machine->all_noreorder_p = false;
9034 /* Code compiled with -mfix-vr4120 can't be all noreorder because
9035 we rely on the assembler to work around some errata. */
9036 if (TARGET_FIX_VR4120)
9037 cfun->machine->all_noreorder_p = false;
9039 /* The same is true for -mfix-vr4130 if we might generate mflo or
9040 mfhi instructions. Note that we avoid using mflo and mfhi if
9041 the VR4130 macc and dmacc instructions are available instead;
9042 see the *mfhilo_{si,di}_macc patterns. */
9043 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
9044 cfun->machine->all_noreorder_p = false;
9049 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9051 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9054 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9055 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9056 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9057 &hilo_delay, &delayed_reg, lo_reg);
9059 mips_avoid_hazard (last_insn, insn, &hilo_delay,
9060 &delayed_reg, lo_reg);
9067 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9073 mips16_lay_out_constants ();
9074 else if (TARGET_EXPLICIT_RELOCS)
9076 if (mips_flag_delayed_branch)
9077 dbr_schedule (get_insns ());
9078 mips_avoid_hazards ();
9079 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9080 vr4130_align_insns ();
9084 /* This function does three things:
9086 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9087 - Register the mips16 hardware floating point stubs.
9088 - Register the gofast functions if selected using --enable-gofast. */
9090 #include "config/gofast.h"
9093 mips_init_libfuncs (void)
9095 if (TARGET_FIX_VR4120)
9097 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9098 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9101 if (TARGET_MIPS16 && mips16_hard_float)
9103 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9104 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9105 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9106 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9108 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9109 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9110 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9111 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9112 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9113 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9115 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9116 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9118 if (TARGET_DOUBLE_FLOAT)
9120 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9121 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9122 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9123 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9125 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9126 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9127 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9128 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9129 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9130 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9132 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9133 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9135 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9136 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9140 gofast_maybe_init_libfuncs ();
9143 /* Return a number assessing the cost of moving a register in class
9144 FROM to class TO. The classes are expressed using the enumeration
9145 values such as `GENERAL_REGS'. A value of 2 is the default; other
9146 values are interpreted relative to that.
9148 It is not required that the cost always equal 2 when FROM is the
9149 same as TO; on some machines it is expensive to move between
9150 registers if they are not general registers.
9152 If reload sees an insn consisting of a single `set' between two
9153 hard registers, and if `REGISTER_MOVE_COST' applied to their
9154 classes returns a value of 2, reload does not check to ensure that
9155 the constraints of the insn are met. Setting a cost of other than
9156 2 will allow reload to verify that the constraints are met. You
9157 should do this if the `movM' pattern's constraints do not allow
9160 ??? We make the cost of moving from HI/LO into general
9161 registers the same as for one of moving general registers to
9162 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9163 pseudo to HI/LO. This might hurt optimizations though, it
9164 isn't clear if it is wise. And it might not work in all cases. We
9165 could solve the DImode LO reg problem by using a multiply, just
9166 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9167 problem by using divide instructions. divu puts the remainder in
9168 the HI reg, so doing a divide by -1 will move the value in the HI
9169 reg for all values except -1. We could handle that case by using a
9170 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9171 a compare/branch to test the input value to see which instruction
9172 we need to use. This gets pretty messy, but it is feasible. */
9175 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9176 enum reg_class to, enum reg_class from)
9178 if (from == M16_REGS && GR_REG_CLASS_P (to))
9180 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9182 else if (GR_REG_CLASS_P (from))
9186 else if (to == M16_NA_REGS)
9188 else if (GR_REG_CLASS_P (to))
9195 else if (to == FP_REGS)
9197 else if (reg_class_subset_p (to, ACC_REGS))
9204 else if (COP_REG_CLASS_P (to))
9209 else if (from == FP_REGS)
9211 if (GR_REG_CLASS_P (to))
9213 else if (to == FP_REGS)
9215 else if (to == ST_REGS)
9218 else if (reg_class_subset_p (from, ACC_REGS))
9220 if (GR_REG_CLASS_P (to))
9228 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9230 else if (COP_REG_CLASS_P (from))
9236 ??? What cases are these? Shouldn't we return 2 here? */
9241 /* Return the length of INSN. LENGTH is the initial length computed by
9242 attributes in the machine-description file. */
9245 mips_adjust_insn_length (rtx insn, int length)
9247 /* A unconditional jump has an unfilled delay slot if it is not part
9248 of a sequence. A conditional jump normally has a delay slot, but
9249 does not on MIPS16. */
9250 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9253 /* See how many nops might be needed to avoid hardware hazards. */
9254 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9255 switch (get_attr_hazard (insn))
9269 /* All MIPS16 instructions are a measly two bytes. */
9277 /* Return an asm sequence to start a noat block and load the address
9278 of a label into $1. */
9281 mips_output_load_label (void)
9283 if (TARGET_EXPLICIT_RELOCS)
9287 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9290 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9293 if (ISA_HAS_LOAD_DELAY)
9294 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9295 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9299 if (Pmode == DImode)
9300 return "%[dla\t%@,%0";
9302 return "%[la\t%@,%0";
9306 /* Return the assembly code for INSN, which has the operands given by
9307 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9308 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9309 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9310 version of BRANCH_IF_TRUE. */
9313 mips_output_conditional_branch (rtx insn, rtx *operands,
9314 const char *branch_if_true,
9315 const char *branch_if_false)
9317 unsigned int length;
9318 rtx taken, not_taken;
9320 length = get_attr_length (insn);
9323 /* Just a simple conditional branch. */
9324 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9325 return branch_if_true;
9328 /* Generate a reversed branch around a direct jump. This fallback does
9329 not use branch-likely instructions. */
9330 mips_branch_likely = false;
9331 not_taken = gen_label_rtx ();
9332 taken = operands[1];
9334 /* Generate the reversed branch to NOT_TAKEN. */
9335 operands[1] = not_taken;
9336 output_asm_insn (branch_if_false, operands);
9338 /* If INSN has a delay slot, we must provide delay slots for both the
9339 branch to NOT_TAKEN and the conditional jump. We must also ensure
9340 that INSN's delay slot is executed in the appropriate cases. */
9343 /* This first delay slot will always be executed, so use INSN's
9344 delay slot if is not annulled. */
9345 if (!INSN_ANNULLED_BRANCH_P (insn))
9347 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9348 asm_out_file, optimize, 1, NULL);
9349 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9352 output_asm_insn ("nop", 0);
9353 fprintf (asm_out_file, "\n");
9356 /* Output the unconditional branch to TAKEN. */
9358 output_asm_insn ("j\t%0%/", &taken);
9361 output_asm_insn (mips_output_load_label (), &taken);
9362 output_asm_insn ("jr\t%@%]%/", 0);
9365 /* Now deal with its delay slot; see above. */
9368 /* This delay slot will only be executed if the branch is taken.
9369 Use INSN's delay slot if is annulled. */
9370 if (INSN_ANNULLED_BRANCH_P (insn))
9372 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9373 asm_out_file, optimize, 1, NULL);
9374 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9377 output_asm_insn ("nop", 0);
9378 fprintf (asm_out_file, "\n");
9381 /* Output NOT_TAKEN. */
9382 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9383 CODE_LABEL_NUMBER (not_taken));
9387 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9388 if some ordered condition is true. The condition is given by
9389 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9390 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9391 its second is always zero. */
9394 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9396 const char *branch[2];
9398 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9399 Make BRANCH[0] branch on the inverse condition. */
9400 switch (GET_CODE (operands[0]))
9402 /* These cases are equivalent to comparisons against zero. */
9404 inverted_p = !inverted_p;
9407 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9408 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9411 /* These cases are always true or always false. */
9413 inverted_p = !inverted_p;
9416 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9417 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9421 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9422 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9425 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9428 /* Used to output div or ddiv instruction DIVISION, which has the operands
9429 given by OPERANDS. Add in a divide-by-zero check if needed.
9431 When working around R4000 and R4400 errata, we need to make sure that
9432 the division is not immediately followed by a shift[1][2]. We also
9433 need to stop the division from being put into a branch delay slot[3].
9434 The easiest way to avoid both problems is to add a nop after the
9435 division. When a divide-by-zero check is needed, this nop can be
9436 used to fill the branch delay slot.
9438 [1] If a double-word or a variable shift executes immediately
9439 after starting an integer division, the shift may give an
9440 incorrect result. See quotations of errata #16 and #28 from
9441 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9442 in mips.md for details.
9444 [2] A similar bug to [1] exists for all revisions of the
9445 R4000 and the R4400 when run in an MC configuration.
9446 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9448 "19. In this following sequence:
9450 ddiv (or ddivu or div or divu)
9451 dsll32 (or dsrl32, dsra32)
9453 if an MPT stall occurs, while the divide is slipping the cpu
9454 pipeline, then the following double shift would end up with an
9457 Workaround: The compiler needs to avoid generating any
9458 sequence with divide followed by extended double shift."
9460 This erratum is also present in "MIPS R4400MC Errata, Processor
9461 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9462 & 3.0" as errata #10 and #4, respectively.
9464 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9465 (also valid for MIPS R4000MC processors):
9467 "52. R4000SC: This bug does not apply for the R4000PC.
9469 There are two flavors of this bug:
9471 1) If the instruction just after divide takes an RF exception
9472 (tlb-refill, tlb-invalid) and gets an instruction cache
9473 miss (both primary and secondary) and the line which is
9474 currently in secondary cache at this index had the first
9475 data word, where the bits 5..2 are set, then R4000 would
9476 get a wrong result for the div.
9481 ------------------- # end-of page. -tlb-refill
9486 ------------------- # end-of page. -tlb-invalid
9489 2) If the divide is in the taken branch delay slot, where the
9490 target takes RF exception and gets an I-cache miss for the
9491 exception vector or where I-cache miss occurs for the
9492 target address, under the above mentioned scenarios, the
9493 div would get wrong results.
9496 j r2 # to next page mapped or unmapped
9497 div r8,r9 # this bug would be there as long
9498 # as there is an ICache miss and
9499 nop # the "data pattern" is present
9502 beq r0, r0, NextPage # to Next page
9506 This bug is present for div, divu, ddiv, and ddivu
9509 Workaround: For item 1), OS could make sure that the next page
9510 after the divide instruction is also mapped. For item 2), the
9511 compiler could make sure that the divide instruction is not in
9512 the branch delay slot."
9514 These processors have PRId values of 0x00004220 and 0x00004300 for
9515 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9518 mips_output_division (const char *division, rtx *operands)
9523 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9525 output_asm_insn (s, operands);
9528 if (TARGET_CHECK_ZERO_DIV)
9532 output_asm_insn (s, operands);
9533 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9535 else if (GENERATE_DIVIDE_TRAPS)
9537 output_asm_insn (s, operands);
9542 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9543 output_asm_insn (s, operands);
9544 s = "break\t7%)\n1:";
9550 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9551 with a final "000" replaced by "k". Ignore case.
9553 Note: this function is shared between GCC and GAS. */
9556 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9558 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9559 given++, canonical++;
9561 return ((*given == 0 && *canonical == 0)
9562 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9566 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9567 CPU name. We've traditionally allowed a lot of variation here.
9569 Note: this function is shared between GCC and GAS. */
9572 mips_matching_cpu_name_p (const char *canonical, const char *given)
9574 /* First see if the name matches exactly, or with a final "000"
9576 if (mips_strict_matching_cpu_name_p (canonical, given))
9579 /* If not, try comparing based on numerical designation alone.
9580 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9581 if (TOLOWER (*given) == 'r')
9583 if (!ISDIGIT (*given))
9586 /* Skip over some well-known prefixes in the canonical name,
9587 hoping to find a number there too. */
9588 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9590 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9592 else if (TOLOWER (canonical[0]) == 'r')
9595 return mips_strict_matching_cpu_name_p (canonical, given);
9599 /* Return the mips_cpu_info entry for the processor or ISA given
9600 by CPU_STRING. Return null if the string isn't recognized.
9602 A similar function exists in GAS. */
9604 static const struct mips_cpu_info *
9605 mips_parse_cpu (const char *cpu_string)
9607 const struct mips_cpu_info *p;
9610 /* In the past, we allowed upper-case CPU names, but it doesn't
9611 work well with the multilib machinery. */
9612 for (s = cpu_string; *s != 0; s++)
9615 warning (0, "the cpu name must be lower case");
9619 /* 'from-abi' selects the most compatible architecture for the given
9620 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9621 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9622 version. Look first at the -mgp options, if given, otherwise base
9623 the choice on MASK_64BIT in TARGET_DEFAULT. */
9624 if (strcasecmp (cpu_string, "from-abi") == 0)
9625 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9626 : ABI_NEEDS_64BIT_REGS ? 3
9627 : (TARGET_64BIT ? 3 : 1));
9629 /* 'default' has traditionally been a no-op. Probably not very useful. */
9630 if (strcasecmp (cpu_string, "default") == 0)
9633 for (p = mips_cpu_info_table; p->name != 0; p++)
9634 if (mips_matching_cpu_name_p (p->name, cpu_string))
9641 /* Return the processor associated with the given ISA level, or null
9642 if the ISA isn't valid. */
9644 static const struct mips_cpu_info *
9645 mips_cpu_info_from_isa (int isa)
9647 const struct mips_cpu_info *p;
9649 for (p = mips_cpu_info_table; p->name != 0; p++)
9656 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9657 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9658 they only hold condition code modes, and CCmode is always considered to
9659 be 4 bytes wide. All other registers are word sized. */
9662 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9664 if (ST_REG_P (regno))
9665 return ((GET_MODE_SIZE (mode) + 3) / 4);
9666 else if (! FP_REG_P (regno))
9667 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9669 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9672 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9673 all BLKmode objects are returned in memory. Under the new (N32 and
9674 64-bit MIPS ABIs) small structures are returned in a register.
9675 Objects with varying size must still be returned in memory, of
9679 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9682 return (TYPE_MODE (type) == BLKmode);
9684 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9685 || (int_size_in_bytes (type) == -1));
9689 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9691 return !TARGET_OLDABI;
9694 /* Return true if INSN is a multiply-add or multiply-subtract
9695 instruction and PREV assigns to the accumulator operand. */
9698 mips_linked_madd_p (rtx prev, rtx insn)
9702 x = single_set (insn);
9708 if (GET_CODE (x) == PLUS
9709 && GET_CODE (XEXP (x, 0)) == MULT
9710 && reg_set_p (XEXP (x, 1), prev))
9713 if (GET_CODE (x) == MINUS
9714 && GET_CODE (XEXP (x, 1)) == MULT
9715 && reg_set_p (XEXP (x, 0), prev))
9721 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9722 that may clobber hi or lo. */
9724 static rtx mips_macc_chains_last_hilo;
9726 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9727 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9730 mips_macc_chains_record (rtx insn)
9732 if (get_attr_may_clobber_hilo (insn))
9733 mips_macc_chains_last_hilo = insn;
9736 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9737 has NREADY elements, looking for a multiply-add or multiply-subtract
9738 instruction that is cumulative with mips_macc_chains_last_hilo.
9739 If there is one, promote it ahead of anything else that might
9740 clobber hi or lo. */
9743 mips_macc_chains_reorder (rtx *ready, int nready)
9747 if (mips_macc_chains_last_hilo != 0)
9748 for (i = nready - 1; i >= 0; i--)
9749 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9751 for (j = nready - 1; j > i; j--)
9752 if (recog_memoized (ready[j]) >= 0
9753 && get_attr_may_clobber_hilo (ready[j]))
9755 mips_promote_ready (ready, i, j);
9762 /* The last instruction to be scheduled. */
9764 static rtx vr4130_last_insn;
9766 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9767 points to an rtx that is initially an instruction. Nullify the rtx
9768 if the instruction uses the value of register X. */
9771 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9773 rtx *insn_ptr = data;
9776 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9780 /* Return true if there is true register dependence between vr4130_last_insn
9784 vr4130_true_reg_dependence_p (rtx insn)
9786 note_stores (PATTERN (vr4130_last_insn),
9787 vr4130_true_reg_dependence_p_1, &insn);
9791 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9792 the ready queue and that INSN2 is the instruction after it, return
9793 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9794 in which INSN1 and INSN2 can probably issue in parallel, but for
9795 which (INSN2, INSN1) should be less sensitive to instruction
9796 alignment than (INSN1, INSN2). See 4130.md for more details. */
9799 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9803 /* Check for the following case:
9805 1) there is some other instruction X with an anti dependence on INSN1;
9806 2) X has a higher priority than INSN2; and
9807 3) X is an arithmetic instruction (and thus has no unit restrictions).
9809 If INSN1 is the last instruction blocking X, it would better to
9810 choose (INSN1, X) over (INSN2, INSN1). */
9811 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9812 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9813 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9814 && recog_memoized (XEXP (dep, 0)) >= 0
9815 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9818 if (vr4130_last_insn != 0
9819 && recog_memoized (insn1) >= 0
9820 && recog_memoized (insn2) >= 0)
9822 /* See whether INSN1 and INSN2 use different execution units,
9823 or if they are both ALU-type instructions. If so, they can
9824 probably execute in parallel. */
9825 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9826 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9827 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9829 /* If only one of the instructions has a dependence on
9830 vr4130_last_insn, prefer to schedule the other one first. */
9831 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9832 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9836 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9837 is not an ALU-type instruction and if INSN1 uses the same
9838 execution unit. (Note that if this condition holds, we already
9839 know that INSN2 uses a different execution unit.) */
9840 if (class1 != VR4130_CLASS_ALU
9841 && recog_memoized (vr4130_last_insn) >= 0
9842 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9849 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9850 queue with at least two instructions. Swap the first two if
9851 vr4130_swap_insns_p says that it could be worthwhile. */
9854 vr4130_reorder (rtx *ready, int nready)
9856 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9857 mips_promote_ready (ready, nready - 2, nready - 1);
9860 /* Remove the instruction at index LOWER from ready queue READY and
9861 reinsert it in front of the instruction at index HIGHER. LOWER must
9865 mips_promote_ready (rtx *ready, int lower, int higher)
9870 new_head = ready[lower];
9871 for (i = lower; i < higher; i++)
9872 ready[i] = ready[i + 1];
9873 ready[i] = new_head;
9876 /* Implement TARGET_SCHED_REORDER. */
9879 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9880 rtx *ready, int *nreadyp, int cycle)
9882 if (!reload_completed && TUNE_MACC_CHAINS)
9885 mips_macc_chains_last_hilo = 0;
9887 mips_macc_chains_reorder (ready, *nreadyp);
9889 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9892 vr4130_last_insn = 0;
9894 vr4130_reorder (ready, *nreadyp);
9896 return mips_issue_rate ();
9899 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9902 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9905 switch (GET_CODE (PATTERN (insn)))
9909 /* Don't count USEs and CLOBBERs against the issue rate. */
9914 if (!reload_completed && TUNE_MACC_CHAINS)
9915 mips_macc_chains_record (insn);
9916 vr4130_last_insn = insn;
9922 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9923 dependencies have no cost. */
9926 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9927 rtx dep ATTRIBUTE_UNUSED, int cost)
9929 if (REG_NOTE_KIND (link) != 0)
9934 /* Return the number of instructions that can be issued per cycle. */
9937 mips_issue_rate (void)
9941 case PROCESSOR_R4130:
9942 case PROCESSOR_R5400:
9943 case PROCESSOR_R5500:
9944 case PROCESSOR_R7000:
9945 case PROCESSOR_R9000:
9949 case PROCESSOR_SB1A:
9950 /* This is actually 4, but we get better performance if we claim 3.
9951 This is partly because of unwanted speculative code motion with the
9952 larger number, and partly because in most common cases we can't
9953 reach the theoretical max of 4. */
9961 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9962 be as wide as the scheduling freedom in the DFA. */
9965 mips_multipass_dfa_lookahead (void)
9967 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9974 /* Implements a store data bypass check. We need this because the cprestore
9975 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
9976 default routine to abort. We just return false for that case. */
9977 /* ??? Should try to give a better result here than assuming false. */
9980 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9982 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9985 return ! store_data_bypass_p (out_insn, in_insn);
9988 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9989 return the first operand of the associated "pref" or "prefx" insn. */
9992 mips_prefetch_cookie (rtx write, rtx locality)
9994 /* store_streamed / load_streamed. */
9995 if (INTVAL (locality) <= 0)
9996 return GEN_INT (INTVAL (write) + 4);
9999 if (INTVAL (locality) <= 2)
10002 /* store_retained / load_retained. */
10003 return GEN_INT (INTVAL (write) + 6);
10006 /* MIPS builtin function support. */
10008 struct builtin_description
10010 /* The code of the main .md file instruction. See mips_builtin_type
10011 for more information. */
10012 enum insn_code icode;
10014 /* The floating-point comparison code to use with ICODE, if any. */
10015 enum mips_fp_condition cond;
10017 /* The name of the builtin function. */
10020 /* Specifies how the function should be expanded. */
10021 enum mips_builtin_type builtin_type;
10023 /* The function's prototype. */
10024 enum mips_function_type function_type;
10026 /* The target flags required for this function. */
10030 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10031 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
10032 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10033 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10034 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10036 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10038 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10039 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10040 "__builtin_mips_" #INSN "_" #COND "_s", \
10041 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10042 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10043 "__builtin_mips_" #INSN "_" #COND "_d", \
10044 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10046 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10047 The lower and upper forms require TARGET_FLAGS while the any and all
10048 forms require MASK_MIPS3D. */
10049 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10050 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10051 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10052 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10053 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10054 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10055 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10056 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10057 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10058 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10059 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10060 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10061 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10063 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10064 require MASK_MIPS3D. */
10065 #define CMP_4S_BUILTINS(INSN, COND) \
10066 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10067 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10068 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10070 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10071 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10072 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10075 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10076 instruction requires TARGET_FLAGS. */
10077 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10078 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10079 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10080 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10082 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10083 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10084 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10087 /* Define all the builtins related to c.cond.fmt condition COND. */
10088 #define CMP_BUILTINS(COND) \
10089 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10090 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10091 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10092 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10093 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10094 CMP_4S_BUILTINS (c, COND), \
10095 CMP_4S_BUILTINS (cabs, COND)
10097 static const struct builtin_description mips_bdesc[] =
10099 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10100 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10101 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10102 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10103 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10104 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10105 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10106 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10108 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10109 MASK_PAIRED_SINGLE_FLOAT),
10110 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10111 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10112 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10113 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10115 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10116 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10117 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10118 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10119 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10120 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10122 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10123 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10124 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10125 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10126 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10127 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10129 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10132 /* Builtin functions for the SB-1 processor. */
10134 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10136 static const struct builtin_description sb1_bdesc[] =
10138 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10141 /* Builtin functions for DSP ASE. */
10143 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10144 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10145 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10146 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10148 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10149 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10150 builtin_description fields. */
10151 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10152 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10153 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10155 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10156 branch instruction. TARGET_FLAGS is a builtin_description field. */
10157 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10158 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10159 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10161 static const struct builtin_description dsp_bdesc[] =
10163 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10164 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10165 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10166 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10167 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10168 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10169 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10170 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10171 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10172 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10173 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10174 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10175 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10176 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10177 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10178 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10179 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10180 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10181 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10182 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10183 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10184 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10185 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10186 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10187 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10188 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10189 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10190 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10191 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10192 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10193 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10194 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10195 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10196 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10197 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10198 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10199 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10200 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10201 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10202 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10203 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10204 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10205 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10206 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10207 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10208 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10209 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10210 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10211 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10212 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10213 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10214 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10215 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10216 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10217 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10218 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10219 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10220 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10221 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10222 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10223 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10224 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10225 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10226 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10227 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10228 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10229 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10230 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10231 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10232 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10233 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10234 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10235 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10236 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10237 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10238 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10239 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10240 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10241 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10242 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10243 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10244 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10245 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10246 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10247 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10248 BPOSGE_BUILTIN (32, MASK_DSP)
10251 /* This helps provide a mapping from builtin function codes to bdesc
10256 /* The builtin function table that this entry describes. */
10257 const struct builtin_description *bdesc;
10259 /* The number of entries in the builtin function table. */
10262 /* The target processor that supports these builtin functions.
10263 PROCESSOR_MAX means we enable them for all processors. */
10264 enum processor_type proc;
10267 static const struct bdesc_map bdesc_arrays[] =
10269 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10270 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10271 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10274 /* Take the head of argument list *ARGLIST and convert it into a form
10275 suitable for input operand OP of instruction ICODE. Return the value
10276 and point *ARGLIST at the next element of the list. */
10279 mips_prepare_builtin_arg (enum insn_code icode,
10280 unsigned int op, tree *arglist)
10283 enum machine_mode mode;
10285 value = expand_normal (TREE_VALUE (*arglist));
10286 mode = insn_data[icode].operand[op].mode;
10287 if (!insn_data[icode].operand[op].predicate (value, mode))
10289 value = copy_to_mode_reg (mode, value);
10290 /* Check the predicate again. */
10291 if (!insn_data[icode].operand[op].predicate (value, mode))
10293 error ("invalid argument to builtin function");
10298 *arglist = TREE_CHAIN (*arglist);
10302 /* Return an rtx suitable for output operand OP of instruction ICODE.
10303 If TARGET is non-null, try to use it where possible. */
10306 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10308 enum machine_mode mode;
10310 mode = insn_data[icode].operand[op].mode;
10311 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10312 target = gen_reg_rtx (mode);
10317 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10320 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10321 enum machine_mode mode ATTRIBUTE_UNUSED,
10322 int ignore ATTRIBUTE_UNUSED)
10324 enum insn_code icode;
10325 enum mips_builtin_type type;
10326 tree fndecl, arglist;
10327 unsigned int fcode;
10328 const struct builtin_description *bdesc;
10329 const struct bdesc_map *m;
10331 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10332 arglist = TREE_OPERAND (exp, 1);
10333 fcode = DECL_FUNCTION_CODE (fndecl);
10336 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10338 if (fcode < m->size)
10341 icode = bdesc[fcode].icode;
10342 type = bdesc[fcode].builtin_type;
10352 case MIPS_BUILTIN_DIRECT:
10353 return mips_expand_builtin_direct (icode, target, arglist, true);
10355 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10356 return mips_expand_builtin_direct (icode, target, arglist, false);
10358 case MIPS_BUILTIN_MOVT:
10359 case MIPS_BUILTIN_MOVF:
10360 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10363 case MIPS_BUILTIN_CMP_ANY:
10364 case MIPS_BUILTIN_CMP_ALL:
10365 case MIPS_BUILTIN_CMP_UPPER:
10366 case MIPS_BUILTIN_CMP_LOWER:
10367 case MIPS_BUILTIN_CMP_SINGLE:
10368 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10371 case MIPS_BUILTIN_BPOSGE32:
10372 return mips_expand_builtin_bposge (type, target);
10379 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10382 mips_init_builtins (void)
10384 const struct builtin_description *d;
10385 const struct bdesc_map *m;
10386 tree types[(int) MIPS_MAX_FTYPE_MAX];
10387 tree V2SF_type_node;
10388 tree V2HI_type_node;
10389 tree V4QI_type_node;
10390 unsigned int offset;
10392 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10393 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10396 if (TARGET_PAIRED_SINGLE_FLOAT)
10398 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10400 types[MIPS_V2SF_FTYPE_V2SF]
10401 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10403 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10404 = build_function_type_list (V2SF_type_node,
10405 V2SF_type_node, V2SF_type_node, NULL_TREE);
10407 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10408 = build_function_type_list (V2SF_type_node,
10409 V2SF_type_node, V2SF_type_node,
10410 integer_type_node, NULL_TREE);
10412 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10413 = build_function_type_list (V2SF_type_node,
10414 V2SF_type_node, V2SF_type_node,
10415 V2SF_type_node, V2SF_type_node, NULL_TREE);
10417 types[MIPS_V2SF_FTYPE_SF_SF]
10418 = build_function_type_list (V2SF_type_node,
10419 float_type_node, float_type_node, NULL_TREE);
10421 types[MIPS_INT_FTYPE_V2SF_V2SF]
10422 = build_function_type_list (integer_type_node,
10423 V2SF_type_node, V2SF_type_node, NULL_TREE);
10425 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10426 = build_function_type_list (integer_type_node,
10427 V2SF_type_node, V2SF_type_node,
10428 V2SF_type_node, V2SF_type_node, NULL_TREE);
10430 types[MIPS_INT_FTYPE_SF_SF]
10431 = build_function_type_list (integer_type_node,
10432 float_type_node, float_type_node, NULL_TREE);
10434 types[MIPS_INT_FTYPE_DF_DF]
10435 = build_function_type_list (integer_type_node,
10436 double_type_node, double_type_node, NULL_TREE);
10438 types[MIPS_SF_FTYPE_V2SF]
10439 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10441 types[MIPS_SF_FTYPE_SF]
10442 = build_function_type_list (float_type_node,
10443 float_type_node, NULL_TREE);
10445 types[MIPS_SF_FTYPE_SF_SF]
10446 = build_function_type_list (float_type_node,
10447 float_type_node, float_type_node, NULL_TREE);
10449 types[MIPS_DF_FTYPE_DF]
10450 = build_function_type_list (double_type_node,
10451 double_type_node, NULL_TREE);
10453 types[MIPS_DF_FTYPE_DF_DF]
10454 = build_function_type_list (double_type_node,
10455 double_type_node, double_type_node, NULL_TREE);
10460 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10461 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10463 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10464 = build_function_type_list (V2HI_type_node,
10465 V2HI_type_node, V2HI_type_node,
10468 types[MIPS_SI_FTYPE_SI_SI]
10469 = build_function_type_list (intSI_type_node,
10470 intSI_type_node, intSI_type_node,
10473 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10474 = build_function_type_list (V4QI_type_node,
10475 V4QI_type_node, V4QI_type_node,
10478 types[MIPS_SI_FTYPE_V4QI]
10479 = build_function_type_list (intSI_type_node,
10483 types[MIPS_V2HI_FTYPE_V2HI]
10484 = build_function_type_list (V2HI_type_node,
10488 types[MIPS_SI_FTYPE_SI]
10489 = build_function_type_list (intSI_type_node,
10493 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10494 = build_function_type_list (V4QI_type_node,
10495 V2HI_type_node, V2HI_type_node,
10498 types[MIPS_V2HI_FTYPE_SI_SI]
10499 = build_function_type_list (V2HI_type_node,
10500 intSI_type_node, intSI_type_node,
10503 types[MIPS_SI_FTYPE_V2HI]
10504 = build_function_type_list (intSI_type_node,
10508 types[MIPS_V2HI_FTYPE_V4QI]
10509 = build_function_type_list (V2HI_type_node,
10513 types[MIPS_V4QI_FTYPE_V4QI_SI]
10514 = build_function_type_list (V4QI_type_node,
10515 V4QI_type_node, intSI_type_node,
10518 types[MIPS_V2HI_FTYPE_V2HI_SI]
10519 = build_function_type_list (V2HI_type_node,
10520 V2HI_type_node, intSI_type_node,
10523 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10524 = build_function_type_list (V2HI_type_node,
10525 V4QI_type_node, V2HI_type_node,
10528 types[MIPS_SI_FTYPE_V2HI_V2HI]
10529 = build_function_type_list (intSI_type_node,
10530 V2HI_type_node, V2HI_type_node,
10533 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10534 = build_function_type_list (intDI_type_node,
10535 intDI_type_node, V4QI_type_node, V4QI_type_node,
10538 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10539 = build_function_type_list (intDI_type_node,
10540 intDI_type_node, V2HI_type_node, V2HI_type_node,
10543 types[MIPS_DI_FTYPE_DI_SI_SI]
10544 = build_function_type_list (intDI_type_node,
10545 intDI_type_node, intSI_type_node, intSI_type_node,
10548 types[MIPS_V4QI_FTYPE_SI]
10549 = build_function_type_list (V4QI_type_node,
10553 types[MIPS_V2HI_FTYPE_SI]
10554 = build_function_type_list (V2HI_type_node,
10558 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10559 = build_function_type_list (void_type_node,
10560 V4QI_type_node, V4QI_type_node,
10563 types[MIPS_SI_FTYPE_V4QI_V4QI]
10564 = build_function_type_list (intSI_type_node,
10565 V4QI_type_node, V4QI_type_node,
10568 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10569 = build_function_type_list (void_type_node,
10570 V2HI_type_node, V2HI_type_node,
10573 types[MIPS_SI_FTYPE_DI_SI]
10574 = build_function_type_list (intSI_type_node,
10575 intDI_type_node, intSI_type_node,
10578 types[MIPS_DI_FTYPE_DI_SI]
10579 = build_function_type_list (intDI_type_node,
10580 intDI_type_node, intSI_type_node,
10583 types[MIPS_VOID_FTYPE_SI_SI]
10584 = build_function_type_list (void_type_node,
10585 intSI_type_node, intSI_type_node,
10588 types[MIPS_SI_FTYPE_PTR_SI]
10589 = build_function_type_list (intSI_type_node,
10590 ptr_type_node, intSI_type_node,
10593 types[MIPS_SI_FTYPE_VOID]
10594 = build_function_type (intSI_type_node, void_list_node);
10597 /* Iterate through all of the bdesc arrays, initializing all of the
10598 builtin functions. */
10601 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10603 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10604 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10605 if ((d->target_flags & target_flags) == d->target_flags)
10606 lang_hooks.builtin_function (d->name, types[d->function_type],
10607 d - m->bdesc + offset,
10608 BUILT_IN_MD, NULL, NULL);
10613 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10614 .md pattern and ARGLIST is the list of function arguments. TARGET,
10615 if nonnull, suggests a good place to put the result.
10616 HAS_TARGET indicates the function must return something. */
10619 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10622 rtx ops[MAX_RECOG_OPERANDS];
10627 /* We save target to ops[0]. */
10628 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10632 /* We need to test if arglist is not zero. Some instructions have extra
10633 clobber registers. */
10634 for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10635 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10640 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10644 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10648 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10652 gcc_unreachable ();
10657 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10658 function (TYPE says which). ARGLIST is the list of arguments to the
10659 function, ICODE is the instruction that should be used to compare
10660 the first two arguments, and COND is the condition it should test.
10661 TARGET, if nonnull, suggests a good place to put the result. */
10664 mips_expand_builtin_movtf (enum mips_builtin_type type,
10665 enum insn_code icode, enum mips_fp_condition cond,
10666 rtx target, tree arglist)
10668 rtx cmp_result, op0, op1;
10670 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10671 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10672 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10673 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10675 icode = CODE_FOR_mips_cond_move_tf_ps;
10676 target = mips_prepare_builtin_target (icode, 0, target);
10677 if (type == MIPS_BUILTIN_MOVT)
10679 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10680 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10684 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10685 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10687 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10691 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10692 into TARGET otherwise. Return TARGET. */
10695 mips_builtin_branch_and_move (rtx condition, rtx target,
10696 rtx value_if_true, rtx value_if_false)
10698 rtx true_label, done_label;
10700 true_label = gen_label_rtx ();
10701 done_label = gen_label_rtx ();
10703 /* First assume that CONDITION is false. */
10704 emit_move_insn (target, value_if_false);
10706 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10707 emit_jump_insn (gen_condjump (condition, true_label));
10708 emit_jump_insn (gen_jump (done_label));
10711 /* Fix TARGET if CONDITION is true. */
10712 emit_label (true_label);
10713 emit_move_insn (target, value_if_true);
10715 emit_label (done_label);
10719 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10720 of the comparison instruction and COND is the condition it should test.
10721 ARGLIST is the list of function arguments and TARGET, if nonnull,
10722 suggests a good place to put the boolean result. */
10725 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10726 enum insn_code icode, enum mips_fp_condition cond,
10727 rtx target, tree arglist)
10729 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10732 if (target == 0 || GET_MODE (target) != SImode)
10733 target = gen_reg_rtx (SImode);
10735 /* Prepare the operands to the comparison. */
10736 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10737 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10738 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10740 switch (insn_data[icode].n_operands)
10743 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10747 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10748 ops[3], ops[4], GEN_INT (cond)));
10752 gcc_unreachable ();
10755 /* If the comparison sets more than one register, we define the result
10756 to be 0 if all registers are false and -1 if all registers are true.
10757 The value of the complete result is indeterminate otherwise. */
10758 switch (builtin_type)
10760 case MIPS_BUILTIN_CMP_ALL:
10761 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10762 return mips_builtin_branch_and_move (condition, target,
10763 const0_rtx, const1_rtx);
10765 case MIPS_BUILTIN_CMP_UPPER:
10766 case MIPS_BUILTIN_CMP_LOWER:
10767 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10768 condition = gen_single_cc (cmp_result, offset);
10769 return mips_builtin_branch_and_move (condition, target,
10770 const1_rtx, const0_rtx);
10773 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10774 return mips_builtin_branch_and_move (condition, target,
10775 const1_rtx, const0_rtx);
10779 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10780 suggests a good place to put the boolean result. */
10783 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10785 rtx condition, cmp_result;
10788 if (target == 0 || GET_MODE (target) != SImode)
10789 target = gen_reg_rtx (SImode);
10791 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10793 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10798 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10799 return mips_builtin_branch_and_move (condition, target,
10800 const1_rtx, const0_rtx);
10803 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10804 FIRST is true if this is the first time handling this decl. */
10807 mips_encode_section_info (tree decl, rtx rtl, int first)
10809 default_encode_section_info (decl, rtl, first);
10811 if (TREE_CODE (decl) == FUNCTION_DECL
10812 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10814 rtx symbol = XEXP (rtl, 0);
10815 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10819 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. PIC_FUNCTION_ADDR_REGNUM is live
10820 on entry to a function when generating -mshared abicalls code. */
10823 mips_extra_live_on_entry (bitmap regs)
10825 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
10826 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10829 /* SImode values are represented as sign-extended to DImode. */
10832 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10834 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10835 return SIGN_EXTEND;
10840 #include "gt-mips.h"