contrib/gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002, 2003 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the
  19 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
  20 ;; MA 02111-1307, USA.
  21
  22 (define_constants
  23   [(UNSPEC_VSPLTISW     141)
  24    (UNSPEC_VSPLTISH     140)
  25    (UNSPEC_VSPLTISB     139)
  26    ])
  27
  28 ;; Generic LVX load instruction.
  29 (define_insn "altivec_lvx_4si"
  30   [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
  31         (match_operand:V4SI 1 "memory_operand" "m"))]
  32   "TARGET_ALTIVEC"
  33   "lvx %0,%y1"
  34   [(set_attr "type" "vecload")])
  35
  36 (define_insn "altivec_lvx_8hi"
  37   [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
  38         (match_operand:V8HI 1 "memory_operand" "m"))]
  39   "TARGET_ALTIVEC"
  40   "lvx %0,%y1"
  41   [(set_attr "type" "vecload")])
  42
  43 (define_insn "altivec_lvx_16qi"
  44   [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
  45         (match_operand:V16QI 1 "memory_operand" "m"))]
  46   "TARGET_ALTIVEC"
  47   "lvx %0,%y1"
  48   [(set_attr "type" "vecload")])
  49
  50 (define_insn "altivec_lvx_4sf"
  51   [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
  52         (match_operand:V4SF 1 "memory_operand" "m"))]
  53   "TARGET_ALTIVEC"
  54   "lvx %0,%y1"
  55   [(set_attr "type" "vecload")])
  56
  57 ;; Generic STVX store instruction.
  58 (define_insn "altivec_stvx_4si"
  59   [(set (match_operand:V4SI 0 "memory_operand" "=m")
  60         (match_operand:V4SI 1 "altivec_register_operand" "v"))]
  61   "TARGET_ALTIVEC"
  62   "stvx %1,%y0"
  63   [(set_attr "type" "vecstore")])
  64
  65 (define_insn "altivec_stvx_8hi"
  66   [(set (match_operand:V8HI 0 "memory_operand" "=m")
  67         (match_operand:V8HI 1 "altivec_register_operand" "v"))]
  68   "TARGET_ALTIVEC"
  69   "stvx %1,%y0"
  70   [(set_attr "type" "vecstore")])
  71
  72 (define_insn "altivec_stvx_16qi"
  73   [(set (match_operand:V16QI 0 "memory_operand" "=m")
  74         (match_operand:V16QI 1 "altivec_register_operand" "v"))]
  75   "TARGET_ALTIVEC"
  76   "stvx %1,%y0"
  77   [(set_attr "type" "vecstore")])
  78
  79 (define_insn "altivec_stvx_4sf"
  80   [(set (match_operand:V4SF 0 "memory_operand" "=m")
  81         (match_operand:V4SF 1 "altivec_register_operand" "v"))]
  82   "TARGET_ALTIVEC"
  83   "stvx %1,%y0"
  84   [(set_attr "type" "vecstore")])
  85
  86 ;; Vector move instructions.
  87 (define_expand "movv4si"
  88   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
  89         (match_operand:V4SI 1 "any_operand" ""))]
  90   "TARGET_ALTIVEC"
  91   "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
  92
  93 (define_insn "*movv4si_internal"
  94   [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
  95         (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r,W"))]
  96   "TARGET_ALTIVEC
  97    && (register_operand (operands[0], V4SImode)
  98        || register_operand (operands[1], V4SImode))"
  99   "*
 100 {
 101   switch (which_alternative)
 102     {
 103     case 0: return \"stvx %1,%y0\";
 104     case 1: return \"lvx %0,%y1\";
 105     case 2: return \"vor %0,%1,%1\";
 106     case 3: return \"#\";
 107     case 4: return \"#\";
 108     case 5: return \"#\";
 109     case 6: return output_vec_const_move (operands);
 110     default: abort();
 111     }
 112 }"
 113   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 114
 115 (define_split
 116   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
 117         (match_operand:V4SI 1 "input_operand" ""))]
 118   "TARGET_ALTIVEC && reload_completed
 119    && gpr_or_gpr_p (operands[0], operands[1])"
 120   [(pc)]
 121 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 122
 123 (define_split
 124   [(set (match_operand:V4SI 0 "altivec_register_operand" "")
 125         (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
 126   "TARGET_ALTIVEC && reload_completed"
 127   [(set (match_dup 0) (match_dup 3))
 128    (set (match_dup 0)
 129         (plus:V4SI (match_dup 0)
 130                    (match_dup 0)))]
 131   "
 132 {
 133   operands[3] = gen_easy_vector_constant_add_self (operands[1]);
 134 }")
 135
 136 (define_expand "movv8hi"
 137   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 138         (match_operand:V8HI 1 "any_operand" ""))]
 139   "TARGET_ALTIVEC"
 140   "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
 141
 142 (define_insn "*movv8hi_internal1"
 143   [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 144         (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r,W"))]
 145   "TARGET_ALTIVEC
 146    && (register_operand (operands[0], V8HImode)
 147        || register_operand (operands[1], V8HImode))"
 148   "*
 149 {
 150    switch (which_alternative)
 151      {
 152      case 0: return \"stvx %1,%y0\";
 153      case 1: return \"lvx %0,%y1\";
 154      case 2: return \"vor %0,%1,%1\";
 155      case 3: return \"#\";
 156      case 4: return \"#\";
 157      case 5: return \"#\";
 158      case 6: return output_vec_const_move (operands);
 159      default: abort ();
 160      }
 161 }"
 162   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 163
 164 (define_split
 165   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 166         (match_operand:V8HI 1 "input_operand" ""))]
 167   "TARGET_ALTIVEC && reload_completed
 168    && gpr_or_gpr_p (operands[0], operands[1])"
 169   [(pc)]
 170 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 171
 172 (define_split
 173   [(set (match_operand:V8HI 0 "altivec_register_operand" "")
 174         (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
 175   "TARGET_ALTIVEC && reload_completed"
 176   [(set (match_dup 0) (match_dup 3))
 177    (set (match_dup 0)
 178         (plus:V8HI (match_dup 0)
 179                    (match_dup 0)))]
 180   "
 181 {
 182   operands[3] = gen_easy_vector_constant_add_self (operands[1]);
 183 }")
 184
 185 (define_expand "movv16qi"
 186   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 187         (match_operand:V16QI 1 "any_operand" ""))]
 188   "TARGET_ALTIVEC"
 189   "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
 190
 191 (define_insn "*movv16qi_internal1"
 192   [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 193         (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r,W"))]
 194   "TARGET_ALTIVEC
 195    && (register_operand (operands[0], V16QImode)
 196        || register_operand (operands[1], V16QImode))"
 197   "*
 198 {
 199   switch (which_alternative)
 200     {
 201     case 0: return \"stvx %1,%y0\";
 202     case 1: return \"lvx %0,%y1\";
 203     case 2: return \"vor %0,%1,%1\";
 204     case 3: return \"#\";
 205     case 4: return \"#\";
 206     case 5: return \"#\";
 207     case 6: return output_vec_const_move (operands);
 208     default: abort ();
 209     }
 210 }"
 211   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 212
 213 (define_split
 214   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 215         (match_operand:V16QI 1 "input_operand" ""))]
 216   "TARGET_ALTIVEC && reload_completed
 217    && gpr_or_gpr_p (operands[0], operands[1])"
 218   [(pc)]
 219 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 220
 221 (define_split
 222   [(set (match_operand:V16QI 0 "altivec_register_operand" "")
 223         (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
 224   "TARGET_ALTIVEC && reload_completed"
 225   [(set (match_dup 0) (match_dup 3))
 226    (set (match_dup 0)
 227         (plus:V16QI (match_dup 0)
 228                    (match_dup 0)))]
 229   "
 230 {
 231   operands[3] = gen_easy_vector_constant_add_self (operands[1]);
 232 }")
 233
 234 (define_expand "movv4sf"
 235   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 236         (match_operand:V4SF 1 "any_operand" ""))]
 237   "TARGET_ALTIVEC"
 238   "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
 239
 240 (define_insn "*movv4sf_internal1"
 241   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
 242         (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r,W"))]
 243   "TARGET_ALTIVEC
 244    && (register_operand (operands[0], V4SFmode)
 245        || register_operand (operands[1], V4SFmode))"
 246   "*
 247 {
 248   switch (which_alternative)
 249     {
 250     case 0: return \"stvx %1,%y0\";
 251     case 1: return \"lvx %0,%y1\";
 252     case 2: return \"vor %0,%1,%1\";
 253     case 3: return \"#\";
 254     case 4: return \"#\";
 255     case 5: return \"#\";
 256     case 6: return output_vec_const_move (operands);
 257     default: abort ();
 258     }
 259 }"
 260   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 261
 262 (define_split
 263   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 264         (match_operand:V4SF 1 "input_operand" ""))]
 265   "TARGET_ALTIVEC && reload_completed
 266    && gpr_or_gpr_p (operands[0], operands[1])"
 267   [(pc)]
 268 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 269
 270 (define_insn "get_vrsave_internal"
 271   [(set (match_operand:SI 0 "register_operand" "=r")
 272         (unspec:SI [(reg:SI 109)] 214))]
 273   "TARGET_ALTIVEC"
 274   "*
 275 {
 276   if (TARGET_MACHO)
 277      return \"mfspr %0,256\";
 278   else
 279      return \"mfvrsave %0\";
 280 }"
 281   [(set_attr "type" "*")])
 282
 283 (define_insn "*set_vrsave_internal"
 284   [(match_parallel 0 "vrsave_operation"
 285      [(set (reg:SI 109)
 286            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 287                                 (reg:SI 109)] 30))])]
 288   "TARGET_ALTIVEC"
 289   "*
 290 {
 291   if (TARGET_MACHO)
 292     return \"mtspr 256,%1\";
 293   else
 294     return \"mtvrsave %1\";
 295 }"
 296   [(set_attr "type" "*")])
 297
 298 ;; Simple binary operations.
 299
 300 (define_insn "addv16qi3"
 301   [(set (match_operand:V16QI 0 "register_operand" "=v")
 302         (plus:V16QI (match_operand:V16QI 1 "register_operand" "v")
 303                     (match_operand:V16QI 2 "register_operand" "v")))]
 304   "TARGET_ALTIVEC"
 305   "vaddubm %0,%1,%2"
 306   [(set_attr "type" "vecsimple")])
 307
 308 (define_insn "addv8hi3"
 309   [(set (match_operand:V8HI 0 "register_operand" "=v")
 310         (plus:V8HI (match_operand:V8HI 1 "register_operand" "v")
 311                    (match_operand:V8HI 2 "register_operand" "v")))]
 312   "TARGET_ALTIVEC"
 313   "vadduhm %0,%1,%2"
 314   [(set_attr "type" "vecsimple")])
 315
 316 (define_insn "addv4si3"
 317   [(set (match_operand:V4SI 0 "register_operand" "=v")
 318         (plus:V4SI (match_operand:V4SI 1 "register_operand" "v")
 319                    (match_operand:V4SI 2 "register_operand" "v")))]
 320   "TARGET_ALTIVEC"
 321   "vadduwm %0,%1,%2"
 322   [(set_attr "type" "vecsimple")])
 323
 324 (define_insn "addv4sf3"
 325   [(set (match_operand:V4SF 0 "register_operand" "=v")
 326         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 327                    (match_operand:V4SF 2 "register_operand" "v")))]
 328   "TARGET_ALTIVEC"
 329   "vaddfp %0,%1,%2"
 330   [(set_attr "type" "vecfloat")])
 331
 332 (define_insn "altivec_vaddcuw"
 333   [(set (match_operand:V4SI 0 "register_operand" "=v")
 334         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 335                       (match_operand:V4SI 2 "register_operand" "v")] 35))]
 336   "TARGET_ALTIVEC"
 337   "vaddcuw %0,%1,%2"
 338   [(set_attr "type" "vecsimple")])
 339
 340 (define_insn "altivec_vaddubs"
 341   [(set (match_operand:V16QI 0 "register_operand" "=v")
 342         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 343                        (match_operand:V16QI 2 "register_operand" "v")] 36))
 344    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 345   "TARGET_ALTIVEC"
 346   "vaddubs %0,%1,%2"
 347   [(set_attr "type" "vecsimple")])
 348
 349 (define_insn "altivec_vaddsbs"
 350   [(set (match_operand:V16QI 0 "register_operand" "=v")
 351         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 352                        (match_operand:V16QI 2 "register_operand" "v")] 37))
 353    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 354   "TARGET_ALTIVEC"
 355   "vaddsbs %0,%1,%2"
 356   [(set_attr "type" "vecsimple")])
 357
 358 (define_insn "altivec_vadduhs"
 359   [(set (match_operand:V8HI 0 "register_operand" "=v")
 360         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 361                       (match_operand:V8HI 2 "register_operand" "v")] 38))
 362    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 363   "TARGET_ALTIVEC"
 364   "vadduhs %0,%1,%2"
 365   [(set_attr "type" "vecsimple")])
 366
 367 (define_insn "altivec_vaddshs"
 368   [(set (match_operand:V8HI 0 "register_operand" "=v")
 369         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 370                       (match_operand:V8HI 2 "register_operand" "v")] 39))
 371    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 372   "TARGET_ALTIVEC"
 373   "vaddshs %0,%1,%2"
 374   [(set_attr "type" "vecsimple")])
 375
 376 (define_insn "altivec_vadduws"
 377   [(set (match_operand:V4SI 0 "register_operand" "=v")
 378         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 379                       (match_operand:V4SI 2 "register_operand" "v")] 40))
 380    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 381   "TARGET_ALTIVEC"
 382   "vadduws %0,%1,%2"
 383   [(set_attr "type" "vecsimple")])
 384
 385 (define_insn "altivec_vaddsws"
 386   [(set (match_operand:V4SI 0 "register_operand" "=v")
 387         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 388                       (match_operand:V4SI 2 "register_operand" "v")] 41))
 389    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 390   "TARGET_ALTIVEC"
 391   "vaddsws %0,%1,%2"
 392   [(set_attr "type" "vecsimple")])
 393
 394 (define_insn "andv4si3"
 395   [(set (match_operand:V4SI 0 "register_operand" "=v")
 396         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 397                   (match_operand:V4SI 2 "register_operand" "v")))]
 398   "TARGET_ALTIVEC"
 399   "vand %0,%1,%2"
 400   [(set_attr "type" "vecsimple")])
 401
 402 (define_insn "altivec_vandc"
 403   [(set (match_operand:V4SI 0 "register_operand" "=v")
 404         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
 405                   (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))]
 406   "TARGET_ALTIVEC"
 407   "vandc %0,%1,%2"
 408   [(set_attr "type" "vecsimple")])
 409
 410 (define_insn "altivec_vavgub"
 411   [(set (match_operand:V16QI 0 "register_operand" "=v")
 412         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 413                        (match_operand:V16QI 2 "register_operand" "v")] 44))]
 414   "TARGET_ALTIVEC"
 415   "vavgub %0,%1,%2"
 416   [(set_attr "type" "vecsimple")])
 417
 418 (define_insn "altivec_vavgsb"
 419   [(set (match_operand:V16QI 0 "register_operand" "=v")
 420         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 421                        (match_operand:V16QI 2 "register_operand" "v")] 45))]
 422   "TARGET_ALTIVEC"
 423   "vavgsb %0,%1,%2"
 424   [(set_attr "type" "vecsimple")])
 425
 426 (define_insn "altivec_vavguh"
 427   [(set (match_operand:V8HI 0 "register_operand" "=v")
 428         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 429                       (match_operand:V8HI 2 "register_operand" "v")] 46))]
 430   "TARGET_ALTIVEC"
 431   "vavguh %0,%1,%2"
 432   [(set_attr "type" "vecsimple")])
 433
 434 (define_insn "altivec_vavgsh"
 435   [(set (match_operand:V8HI 0 "register_operand" "=v")
 436         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 437                       (match_operand:V8HI 2 "register_operand" "v")] 47))]
 438   "TARGET_ALTIVEC"
 439   "vavgsh %0,%1,%2"
 440   [(set_attr "type" "vecsimple")])
 441
 442 (define_insn "altivec_vavguw"
 443   [(set (match_operand:V4SI 0 "register_operand" "=v")
 444         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 445                       (match_operand:V4SI 2 "register_operand" "v")] 48))]
 446   "TARGET_ALTIVEC"
 447   "vavguw %0,%1,%2"
 448   [(set_attr "type" "vecsimple")])
 449
 450 (define_insn "altivec_vavgsw"
 451   [(set (match_operand:V4SI 0 "register_operand" "=v")
 452         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 453                       (match_operand:V4SI 2 "register_operand" "v")] 49))]
 454   "TARGET_ALTIVEC"
 455   "vavgsw %0,%1,%2"
 456   [(set_attr "type" "vecsimple")])
 457
 458 (define_insn "altivec_vcmpbfp"
 459   [(set (match_operand:V4SI 0 "register_operand" "=v")
 460         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 461                       (match_operand:V4SF 2 "register_operand" "v")] 50))]
 462   "TARGET_ALTIVEC"
 463   "vcmpbfp %0,%1,%2"
 464   [(set_attr "type" "veccmp")])
 465
 466 (define_insn "altivec_vcmpequb"
 467   [(set (match_operand:V16QI 0 "register_operand" "=v")
 468         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 469                        (match_operand:V16QI 2 "register_operand" "v")] 51))]
 470   "TARGET_ALTIVEC"
 471   "vcmpequb %0,%1,%2"
 472   [(set_attr "type" "vecsimple")])
 473
 474 (define_insn "altivec_vcmpequh"
 475   [(set (match_operand:V8HI 0 "register_operand" "=v")
 476         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 477                       (match_operand:V8HI 2 "register_operand" "v")] 52))]
 478   "TARGET_ALTIVEC"
 479   "vcmpequh %0,%1,%2"
 480   [(set_attr "type" "vecsimple")])
 481
 482 (define_insn "altivec_vcmpequw"
 483   [(set (match_operand:V4SI 0 "register_operand" "=v")
 484         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 485                       (match_operand:V4SI 2 "register_operand" "v")] 53))]
 486   "TARGET_ALTIVEC"
 487   "vcmpequw %0,%1,%2"
 488   [(set_attr "type" "vecsimple")])
 489
 490 (define_insn "altivec_vcmpeqfp"
 491   [(set (match_operand:V4SI 0 "register_operand" "=v")
 492         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 493                       (match_operand:V4SF 2 "register_operand" "v")] 54))]
 494   "TARGET_ALTIVEC"
 495   "vcmpeqfp %0,%1,%2"
 496   [(set_attr "type" "veccmp")])
 497
 498 (define_insn "altivec_vcmpgefp"
 499   [(set (match_operand:V4SI 0 "register_operand" "=v")
 500         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 501                       (match_operand:V4SF 2 "register_operand" "v")] 55))]
 502   "TARGET_ALTIVEC"
 503   "vcmpgefp %0,%1,%2"
 504   [(set_attr "type" "veccmp")])
 505
 506 (define_insn "altivec_vcmpgtub"
 507   [(set (match_operand:V16QI 0 "register_operand" "=v")
 508         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 509                        (match_operand:V16QI 2 "register_operand" "v")] 56))]
 510   "TARGET_ALTIVEC"
 511   "vcmpgtub %0,%1,%2"
 512   [(set_attr "type" "vecsimple")])
 513
 514 (define_insn "altivec_vcmpgtsb"
 515   [(set (match_operand:V16QI 0 "register_operand" "=v")
 516         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 517                        (match_operand:V16QI 2 "register_operand" "v")] 57))]
 518   "TARGET_ALTIVEC"
 519   "vcmpgtsb %0,%1,%2"
 520   [(set_attr "type" "vecsimple")])
 521
 522 (define_insn "altivec_vcmpgtuh"
 523   [(set (match_operand:V8HI 0 "register_operand" "=v")
 524         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 525                       (match_operand:V8HI 2 "register_operand" "v")] 58))]
 526   "TARGET_ALTIVEC"
 527   "vcmpgtuh %0,%1,%2"
 528   [(set_attr "type" "vecsimple")])
 529
 530 (define_insn "altivec_vcmpgtsh"
 531   [(set (match_operand:V8HI 0 "register_operand" "=v")
 532         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 533                       (match_operand:V8HI 2 "register_operand" "v")] 59))]
 534   "TARGET_ALTIVEC"
 535   "vcmpgtsh %0,%1,%2"
 536   [(set_attr "type" "vecsimple")])
 537
 538 (define_insn "altivec_vcmpgtuw"
 539   [(set (match_operand:V4SI 0 "register_operand" "=v")
 540         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 541                       (match_operand:V4SI 2 "register_operand" "v")] 60))]
 542   "TARGET_ALTIVEC"
 543   "vcmpgtuw %0,%1,%2"
 544   [(set_attr "type" "vecsimple")])
 545
 546 (define_insn "altivec_vcmpgtsw"
 547   [(set (match_operand:V4SI 0 "register_operand" "=v")
 548         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 549                       (match_operand:V4SI 2 "register_operand" "v")] 61))]
 550   "TARGET_ALTIVEC"
 551   "vcmpgtsw %0,%1,%2"
 552   [(set_attr "type" "vecsimple")])
 553
 554 (define_insn "altivec_vcmpgtfp"
 555   [(set (match_operand:V4SI 0 "register_operand" "=v")
 556         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 557                       (match_operand:V4SF 2 "register_operand" "v")] 62))]
 558   "TARGET_ALTIVEC"
 559   "vcmpgtfp %0,%1,%2"
 560   [(set_attr "type" "veccmp")])
 561
 562 ;; Fused multiply add
 563 (define_insn "altivec_vmaddfp"
 564   [(set (match_operand:V4SF 0 "register_operand" "=v")
 565         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 566                               (match_operand:V4SF 2 "register_operand" "v"))
 567                    (match_operand:V4SF 3 "register_operand" "v")))]
 568   "TARGET_ALTIVEC"
 569   "vmaddfp %0,%1,%2,%3"
 570   [(set_attr "type" "vecfloat")])
 571
 572 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
 573
 574 (define_expand "mulv4sf3"
 575   [(use (match_operand:V4SF 0 "register_operand" ""))
 576    (use (match_operand:V4SF 1 "register_operand" ""))
 577    (use (match_operand:V4SF 2 "register_operand" ""))]
 578   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 579   "
 580 {
 581   rtx neg0;
 582
 583   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
 584   neg0 = gen_reg_rtx (V4SFmode);
 585   emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1)));
 586   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
 587
 588   /* Use the multiply-add.  */
 589   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
 590                                   neg0));
 591   DONE;
 592 }")
 593
 594 ;; Fused multiply subtract
 595 (define_insn "altivec_vnmsubfp"
 596   [(set (match_operand:V4SF 0 "register_operand" "=v")
 597         (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 598                                (match_operand:V4SF 2 "register_operand" "v"))
 599                     (match_operand:V4SF 3 "register_operand" "v"))))]
 600   "TARGET_ALTIVEC"
 601   "vnmsubfp %0,%1,%2,%3"
 602   [(set_attr "type" "vecfloat")])
 603
 604
 605 (define_insn "altivec_vmsumubm"
 606   [(set (match_operand:V4SI 0 "register_operand" "=v")
 607         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 608                       (match_operand:V16QI 2 "register_operand" "v")
 609                       (match_operand:V4SI 3 "register_operand" "v")] 65))]
 610   "TARGET_ALTIVEC"
 611   "vmsumubm %0,%1,%2,%3"
 612   [(set_attr "type" "veccomplex")])
 613
 614 (define_insn "altivec_vmsummbm"
 615   [(set (match_operand:V4SI 0 "register_operand" "=v")
 616         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
 617                       (match_operand:V16QI 2 "register_operand" "v")
 618                       (match_operand:V4SI 3 "register_operand" "v")] 66))]
 619   "TARGET_ALTIVEC"
 620   "vmsummbm %0,%1,%2,%3"
 621   [(set_attr "type" "veccomplex")])
 622
 623 (define_insn "altivec_vmsumuhm"
 624   [(set (match_operand:V4SI 0 "register_operand" "=v")
 625         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 626                       (match_operand:V8HI 2 "register_operand" "v")
 627                       (match_operand:V4SI 3 "register_operand" "v")] 67))]
 628   "TARGET_ALTIVEC"
 629   "vmsumuhm %0,%1,%2,%3"
 630   [(set_attr "type" "veccomplex")])
 631
 632 (define_insn "altivec_vmsumshm"
 633   [(set (match_operand:V4SI 0 "register_operand" "=v")
 634         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 635                       (match_operand:V8HI 2 "register_operand" "v")
 636                       (match_operand:V4SI 3 "register_operand" "v")] 68))]
 637   "TARGET_ALTIVEC"
 638   "vmsumshm %0,%1,%2,%3"
 639   [(set_attr "type" "veccomplex")])
 640
 641 (define_insn "altivec_vmsumuhs"
 642   [(set (match_operand:V4SI 0 "register_operand" "=v")
 643         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 644                       (match_operand:V8HI 2 "register_operand" "v")
 645                       (match_operand:V4SI 3 "register_operand" "v")] 69))
 646    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 647   "TARGET_ALTIVEC"
 648   "vmsumuhs %0,%1,%2,%3"
 649   [(set_attr "type" "veccomplex")])
 650
 651 (define_insn "altivec_vmsumshs"
 652   [(set (match_operand:V4SI 0 "register_operand" "=v")
 653         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 654                       (match_operand:V8HI 2 "register_operand" "v")
 655                       (match_operand:V4SI 3 "register_operand" "v")] 70))
 656    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 657   "TARGET_ALTIVEC"
 658   "vmsumshs %0,%1,%2,%3"
 659   [(set_attr "type" "veccomplex")])
 660
 661 (define_insn "umaxv16qi3"
 662   [(set (match_operand:V16QI 0 "register_operand" "=v")
 663         (umax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 664                     (match_operand:V16QI 2 "register_operand" "v")))]
 665   "TARGET_ALTIVEC"
 666   "vmaxub %0,%1,%2"
 667   [(set_attr "type" "vecsimple")])
 668
 669 (define_insn "smaxv16qi3"
 670   [(set (match_operand:V16QI 0 "register_operand" "=v")
 671         (smax:V16QI (match_operand:V16QI 1 "register_operand" "v")
 672                     (match_operand:V16QI 2 "register_operand" "v")))]
 673   "TARGET_ALTIVEC"
 674   "vmaxsb %0,%1,%2"
 675   [(set_attr "type" "vecsimple")])
 676
 677 (define_insn "umaxv8hi3"
 678   [(set (match_operand:V8HI 0 "register_operand" "=v")
 679         (umax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 680                    (match_operand:V8HI 2 "register_operand" "v")))]
 681   "TARGET_ALTIVEC"
 682   "vmaxuh %0,%1,%2"
 683   [(set_attr "type" "vecsimple")])
 684
 685 (define_insn "smaxv8hi3"
 686   [(set (match_operand:V8HI 0 "register_operand" "=v")
 687         (smax:V8HI (match_operand:V8HI 1 "register_operand" "v")
 688                    (match_operand:V8HI 2 "register_operand" "v")))]
 689   "TARGET_ALTIVEC"
 690   "vmaxsh %0,%1,%2"
 691   [(set_attr "type" "vecsimple")])
 692
 693 (define_insn "umaxv4si3"
 694   [(set (match_operand:V4SI 0 "register_operand" "=v")
 695         (umax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 696                    (match_operand:V4SI 2 "register_operand" "v")))]
 697   "TARGET_ALTIVEC"
 698   "vmaxuw %0,%1,%2"
 699   [(set_attr "type" "vecsimple")])
 700
 701 (define_insn "smaxv4si3"
 702   [(set (match_operand:V4SI 0 "register_operand" "=v")
 703         (smax:V4SI (match_operand:V4SI 1 "register_operand" "v")
 704                    (match_operand:V4SI 2 "register_operand" "v")))]
 705   "TARGET_ALTIVEC"
 706   "vmaxsw %0,%1,%2"
 707   [(set_attr "type" "vecsimple")])
 708
 709 (define_insn "smaxv4sf3"
 710   [(set (match_operand:V4SF 0 "register_operand" "=v")
 711         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 712                    (match_operand:V4SF 2 "register_operand" "v")))]
 713   "TARGET_ALTIVEC"
 714   "vmaxfp %0,%1,%2"
 715   [(set_attr "type" "veccmp")])
 716
 717 (define_insn "altivec_vmhaddshs"
 718   [(set (match_operand:V8HI 0 "register_operand" "=v")
 719         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 720                       (match_operand:V8HI 2 "register_operand" "v")
 721                       (match_operand:V8HI 3 "register_operand" "v")] 71))
 722    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 723   "TARGET_ALTIVEC"
 724   "vmhaddshs %0,%1,%2,%3"
 725   [(set_attr "type" "veccomplex")])
 726 (define_insn "altivec_vmhraddshs"
 727   [(set (match_operand:V8HI 0 "register_operand" "=v")
 728         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 729                       (match_operand:V8HI 2 "register_operand" "v")
 730                       (match_operand:V8HI 3 "register_operand" "v")] 72))
 731    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
 732   "TARGET_ALTIVEC"
 733   "vmhraddshs %0,%1,%2,%3"
 734   [(set_attr "type" "veccomplex")])
 735 (define_insn "altivec_vmladduhm"
 736   [(set (match_operand:V8HI 0 "register_operand" "=v")
 737         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 738                       (match_operand:V8HI 2 "register_operand" "v")
 739                       (match_operand:V8HI 3 "register_operand" "v")] 73))]
 740   "TARGET_ALTIVEC"
 741   "vmladduhm %0,%1,%2,%3"
 742   [(set_attr "type" "veccomplex")])
 743
 744 (define_insn "altivec_vmrghb"
 745   [(set (match_operand:V16QI 0 "register_operand" "=v")
 746         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 747                                            (parallel [(const_int 8)
 748                                                       (const_int 9)
 749                                                       (const_int 10)
 750                                                       (const_int 11)
 751                                                       (const_int 12)
 752                                                       (const_int 13)
 753                                                       (const_int 14)
 754                                                       (const_int 15)
 755                                                       (const_int 0)
 756                                                       (const_int 1)
 757                                                       (const_int 2)
 758                                                       (const_int 3)
 759                                                       (const_int 4)
 760                                                       (const_int 5)
 761                                                       (const_int 6)
 762                                                       (const_int 7)]))
 763                       (match_operand:V16QI 2 "register_operand" "v")
 764                       (const_int 255)))]
 765   "TARGET_ALTIVEC"
 766   "vmrghb %0,%1,%2"
 767   [(set_attr "type" "vecperm")])
 768
 769 (define_insn "altivec_vmrghh"
 770   [(set (match_operand:V8HI 0 "register_operand" "=v")
 771         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 772                                            (parallel [(const_int 4)
 773                                                       (const_int 5)
 774                                                       (const_int 6)
 775                                                       (const_int 7)
 776                                                       (const_int 0)
 777                                                       (const_int 1)
 778                                                       (const_int 2)
 779                                                       (const_int 3)]))
 780                       (match_operand:V8HI 2 "register_operand" "v")
 781                       (const_int 15)))]
 782   "TARGET_ALTIVEC"
 783   "vmrghh %0,%1,%2"
 784   [(set_attr "type" "vecperm")])
 785
 786 (define_insn "altivec_vmrghw"
 787   [(set (match_operand:V4SI 0 "register_operand" "=v")
 788         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 789                                          (parallel [(const_int 2)
 790                                                     (const_int 3)
 791                                                     (const_int 0)
 792                                                     (const_int 1)]))
 793                       (match_operand:V4SI 2 "register_operand" "v")
 794                       (const_int 12)))]
 795   "TARGET_ALTIVEC"
 796   "vmrghw %0,%1,%2"
 797   [(set_attr "type" "vecperm")])
 798
 799 (define_insn "altivec_vmrglb"
 800   [(set (match_operand:V16QI 0 "register_operand" "=v")
 801         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 802                                            (parallel [(const_int 0)
 803                                                       (const_int 1)
 804                                                       (const_int 2)
 805                                                       (const_int 3)
 806                                                       (const_int 4)
 807                                                       (const_int 5)
 808                                                       (const_int 6)
 809                                                       (const_int 7)
 810                                                       (const_int 8)
 811                                                       (const_int 9)
 812                                                       (const_int 10)
 813                                                       (const_int 11)
 814                                                       (const_int 12)
 815                                                       (const_int 13)
 816                                                       (const_int 14)
 817                                                       (const_int 15)]))
 818                       (match_operand:V16QI 1 "register_operand" "v")
 819                       (const_int 255)))]
 820   "TARGET_ALTIVEC"
 821   "vmrglb %0,%1,%2"
 822   [(set_attr "type" "vecperm")])
 823
 824 (define_insn "altivec_vmrglh"
 825   [(set (match_operand:V8HI 0 "register_operand" "=v")
 826         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 827                                            (parallel [(const_int 0)
 828                                                       (const_int 1)
 829                                                       (const_int 2)
 830                                                       (const_int 3)
 831                                                       (const_int 4)
 832                                                       (const_int 5)
 833                                                       (const_int 6)
 834                                                       (const_int 7)]))
 835                       (match_operand:V8HI 1 "register_operand" "v")
 836                       (const_int 15)))]
 837   "TARGET_ALTIVEC"
 838   "vmrglh %0,%1,%2"
 839   [(set_attr "type" "vecperm")])
 840
 841 (define_insn "altivec_vmrglw"
 842   [(set (match_operand:V4SI 0 "register_operand" "=v")
 843         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 844                                          (parallel [(const_int 0)
 845                                                     (const_int 1)
 846                                                     (const_int 2)
 847                                                     (const_int 3)]))
 848                       (match_operand:V4SI 1 "register_operand" "v")
 849                       (const_int 12)))]
 850   "TARGET_ALTIVEC"
 851   "vmrglw %0,%1,%2"
 852   [(set_attr "type" "vecperm")])
 853
 854 (define_insn "uminv16qi3"
 855   [(set (match_operand:V16QI 0 "register_operand" "=v")
 856         (umin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 857                     (match_operand:V16QI 2 "register_operand" "v")))]
 858   "TARGET_ALTIVEC"
 859   "vminub %0,%1,%2"
 860   [(set_attr "type" "vecsimple")])
 861
 862 (define_insn "sminv16qi3"
 863   [(set (match_operand:V16QI 0 "register_operand" "=v")
 864         (smin:V16QI (match_operand:V16QI 1 "register_operand" "v")
 865                     (match_operand:V16QI 2 "register_operand" "v")))]
 866   "TARGET_ALTIVEC"
 867   "vminsb %0,%1,%2"
 868   [(set_attr "type" "vecsimple")])
 869
 870 (define_insn "uminv8hi3"
 871   [(set (match_operand:V8HI 0 "register_operand" "=v")
 872         (umin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 873                    (match_operand:V8HI 2 "register_operand" "v")))]
 874   "TARGET_ALTIVEC"
 875   "vminuh %0,%1,%2"
 876   [(set_attr "type" "vecsimple")])
 877
 878 (define_insn "sminv8hi3"
 879   [(set (match_operand:V8HI 0 "register_operand" "=v")
 880         (smin:V8HI (match_operand:V8HI 1 "register_operand" "v")
 881                    (match_operand:V8HI 2 "register_operand" "v")))]
 882   "TARGET_ALTIVEC"
 883   "vminsh %0,%1,%2"
 884   [(set_attr "type" "vecsimple")])
 885
 886 (define_insn "uminv4si3"
 887   [(set (match_operand:V4SI 0 "register_operand" "=v")
 888         (umin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 889                    (match_operand:V4SI 2 "register_operand" "v")))]
 890   "TARGET_ALTIVEC"
 891   "vminuw %0,%1,%2"
 892   [(set_attr "type" "vecsimple")])
 893
 894 (define_insn "sminv4si3"
 895   [(set (match_operand:V4SI 0 "register_operand" "=v")
 896         (smin:V4SI (match_operand:V4SI 1 "register_operand" "v")
 897                    (match_operand:V4SI 2 "register_operand" "v")))]
 898   "TARGET_ALTIVEC"
 899   "vminsw %0,%1,%2"
 900   [(set_attr "type" "vecsimple")])
 901
 902 (define_insn "sminv4sf3"
 903   [(set (match_operand:V4SF 0 "register_operand" "=v")
 904         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 905                    (match_operand:V4SF 2 "register_operand" "v")))]
 906   "TARGET_ALTIVEC"
 907   "vminfp %0,%1,%2"
 908   [(set_attr "type" "veccmp")])
 909
 910 (define_insn "altivec_vmuleub"
 911   [(set (match_operand:V8HI 0 "register_operand" "=v")
 912         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 913                       (match_operand:V16QI 2 "register_operand" "v")] 83))]
 914   "TARGET_ALTIVEC"
 915   "vmuleub %0,%1,%2"
 916   [(set_attr "type" "veccomplex")])
 917
 918 (define_insn "altivec_vmulesb"
 919   [(set (match_operand:V8HI 0 "register_operand" "=v")
 920         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 921                       (match_operand:V16QI 2 "register_operand" "v")] 84))]
 922   "TARGET_ALTIVEC"
 923   "vmulesb %0,%1,%2"
 924   [(set_attr "type" "veccomplex")])
 925
 926 (define_insn "altivec_vmuleuh"
 927   [(set (match_operand:V4SI 0 "register_operand" "=v")
 928         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 929                       (match_operand:V8HI 2 "register_operand" "v")] 85))]
 930   "TARGET_ALTIVEC"
 931   "vmuleuh %0,%1,%2"
 932   [(set_attr "type" "veccomplex")])
 933
 934 (define_insn "altivec_vmulesh"
 935   [(set (match_operand:V4SI 0 "register_operand" "=v")
 936         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 937                       (match_operand:V8HI 2 "register_operand" "v")] 86))]
 938   "TARGET_ALTIVEC"
 939   "vmulesh %0,%1,%2"
 940   [(set_attr "type" "veccomplex")])
 941
 942 (define_insn "altivec_vmuloub"
 943   [(set (match_operand:V8HI 0 "register_operand" "=v")
 944         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 945                       (match_operand:V16QI 2 "register_operand" "v")] 87))]
 946   "TARGET_ALTIVEC"
 947   "vmuloub %0,%1,%2"
 948   [(set_attr "type" "veccomplex")])
 949
 950 (define_insn "altivec_vmulosb"
 951   [(set (match_operand:V8HI 0 "register_operand" "=v")
 952         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 953                       (match_operand:V16QI 2 "register_operand" "v")] 88))]
 954   "TARGET_ALTIVEC"
 955   "vmulosb %0,%1,%2"
 956   [(set_attr "type" "veccomplex")])
 957
 958 (define_insn "altivec_vmulouh"
 959   [(set (match_operand:V4SI 0 "register_operand" "=v")
 960         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 961                       (match_operand:V8HI 2 "register_operand" "v")] 89))]
 962   "TARGET_ALTIVEC"
 963   "vmulouh %0,%1,%2"
 964   [(set_attr "type" "veccomplex")])
 965
 966 (define_insn "altivec_vmulosh"
 967   [(set (match_operand:V4SI 0 "register_operand" "=v")
 968         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 969                       (match_operand:V8HI 2 "register_operand" "v")] 90))]
 970   "TARGET_ALTIVEC"
 971   "vmulosh %0,%1,%2"
 972   [(set_attr "type" "veccomplex")])
 973
 974 (define_insn "altivec_vnor"
 975   [(set (match_operand:V4SI 0 "register_operand" "=v")
 976         (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 977                             (match_operand:V4SI 2 "register_operand" "v"))))]
 978   "TARGET_ALTIVEC"
 979   "vnor %0,%1,%2"
 980   [(set_attr "type" "vecsimple")])
 981
 982 (define_insn "iorv4si3"
 983   [(set (match_operand:V4SI 0 "register_operand" "=v")
 984         (ior:V4SI (match_operand:V4SI 1 "register_operand" "v")
 985                   (match_operand:V4SI 2 "register_operand" "v")))]
 986   "TARGET_ALTIVEC"
 987   "vor %0,%1,%2"
 988   [(set_attr "type" "vecsimple")])
 989
 990 (define_insn "altivec_vpkuhum"
 991   [(set (match_operand:V16QI 0 "register_operand" "=v")
 992         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
 993                        (match_operand:V8HI 2 "register_operand" "v")] 93))]
 994   "TARGET_ALTIVEC"
 995   "vpkuhum %0,%1,%2"
 996   [(set_attr "type" "vecperm")])
 997
 998 (define_insn "altivec_vpkuwum"
 999   [(set (match_operand:V8HI 0 "register_operand" "=v")
1000         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1001                       (match_operand:V4SI 2 "register_operand" "v")] 94))]
1002   "TARGET_ALTIVEC"
1003   "vpkuwum %0,%1,%2"
1004   [(set_attr "type" "vecperm")])
1005
1006 (define_insn "altivec_vpkpx"
1007   [(set (match_operand:V8HI 0 "register_operand" "=v")
1008         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1009                       (match_operand:V4SI 2 "register_operand" "v")] 95))]
1010   "TARGET_ALTIVEC"
1011   "vpkpx %0,%1,%2"
1012   [(set_attr "type" "vecperm")])
1013
1014 (define_insn "altivec_vpkuhss"
1015   [(set (match_operand:V16QI 0 "register_operand" "=v")
1016         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1017                        (match_operand:V8HI 2 "register_operand" "v")] 96))
1018    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1019   "TARGET_ALTIVEC"
1020   "vpkuhss %0,%1,%2"
1021   [(set_attr "type" "vecperm")])
1022
1023 (define_insn "altivec_vpkshss"
1024   [(set (match_operand:V16QI 0 "register_operand" "=v")
1025         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1026                        (match_operand:V8HI 2 "register_operand" "v")] 97))
1027    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1028   "TARGET_ALTIVEC"
1029   "vpkshss %0,%1,%2"
1030   [(set_attr "type" "vecperm")])
1031
1032 (define_insn "altivec_vpkuwss"
1033   [(set (match_operand:V8HI 0 "register_operand" "=v")
1034         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1035                       (match_operand:V4SI 2 "register_operand" "v")] 98))
1036    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1037   "TARGET_ALTIVEC"
1038   "vpkuwss %0,%1,%2"
1039   [(set_attr "type" "vecperm")])
1040
1041 (define_insn "altivec_vpkswss"
1042   [(set (match_operand:V8HI 0 "register_operand" "=v")
1043         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1044                       (match_operand:V4SI 2 "register_operand" "v")] 99))
1045    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1046   "TARGET_ALTIVEC"
1047   "vpkswss %0,%1,%2"
1048   [(set_attr "type" "vecperm")])
1049
1050 (define_insn "altivec_vpkuhus"
1051   [(set (match_operand:V16QI 0 "register_operand" "=v")
1052         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1053                        (match_operand:V8HI 2 "register_operand" "v")] 100))
1054    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1055   "TARGET_ALTIVEC"
1056   "vpkuhus %0,%1,%2"
1057   [(set_attr "type" "vecperm")])
1058
1059 (define_insn "altivec_vpkshus"
1060   [(set (match_operand:V16QI 0 "register_operand" "=v")
1061         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1062                        (match_operand:V8HI 2 "register_operand" "v")] 101))
1063    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1064   "TARGET_ALTIVEC"
1065   "vpkshus %0,%1,%2"
1066   [(set_attr "type" "vecperm")])
1067
1068 (define_insn "altivec_vpkuwus"
1069   [(set (match_operand:V8HI 0 "register_operand" "=v")
1070         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1071                       (match_operand:V4SI 2 "register_operand" "v")] 102))
1072    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1073   "TARGET_ALTIVEC"
1074   "vpkuwus %0,%1,%2"
1075   [(set_attr "type" "vecperm")])
1076
1077 (define_insn "altivec_vpkswus"
1078   [(set (match_operand:V8HI 0 "register_operand" "=v")
1079         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1080                       (match_operand:V4SI 2 "register_operand" "v")] 103))
1081    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1082   "TARGET_ALTIVEC"
1083   "vpkswus %0,%1,%2"
1084   [(set_attr "type" "vecperm")])
1085
1086 (define_insn "altivec_vrlb"
1087   [(set (match_operand:V16QI 0 "register_operand" "=v")
1088         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1089                        (match_operand:V16QI 2 "register_operand" "v")] 104))]
1090   "TARGET_ALTIVEC"
1091   "vrlb %0,%1,%2"
1092   [(set_attr "type" "vecsimple")])
1093
1094 (define_insn "altivec_vrlh"
1095   [(set (match_operand:V8HI 0 "register_operand" "=v")
1096         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1097                       (match_operand:V8HI 2 "register_operand" "v")] 105))]
1098   "TARGET_ALTIVEC"
1099   "vrlh %0,%1,%2"
1100   [(set_attr "type" "vecsimple")])
1101
1102 (define_insn "altivec_vrlw"
1103   [(set (match_operand:V4SI 0 "register_operand" "=v")
1104         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1105                       (match_operand:V4SI 2 "register_operand" "v")] 106))]
1106   "TARGET_ALTIVEC"
1107   "vrlw %0,%1,%2"
1108   [(set_attr "type" "vecsimple")])
1109
1110 (define_insn "altivec_vslb"
1111   [(set (match_operand:V16QI 0 "register_operand" "=v")
1112         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1113                        (match_operand:V16QI 2 "register_operand" "v")] 107))]
1114   "TARGET_ALTIVEC"
1115   "vslb %0,%1,%2"
1116   [(set_attr "type" "vecsimple")])
1117
1118 (define_insn "altivec_vslh"
1119   [(set (match_operand:V8HI 0 "register_operand" "=v")
1120         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1121                       (match_operand:V8HI 2 "register_operand" "v")] 108))]
1122   "TARGET_ALTIVEC"
1123   "vslh %0,%1,%2"
1124   [(set_attr "type" "vecsimple")])
1125
1126 (define_insn "altivec_vslw"
1127   [(set (match_operand:V4SI 0 "register_operand" "=v")
1128         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1129                       (match_operand:V4SI 2 "register_operand" "v")] 109))]
1130   "TARGET_ALTIVEC"
1131   "vslw %0,%1,%2"
1132   [(set_attr "type" "vecsimple")])
1133
1134 (define_insn "altivec_vslw_v4sf"
1135   [(set (match_operand:V4SF 0 "register_operand" "=v")
1136         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1137                       (match_operand:V4SF 2 "register_operand" "v")] 109))]
1138   "TARGET_ALTIVEC"
1139   "vslw %0,%1,%2"
1140   [(set_attr "type" "vecsimple")])
1141
1142 (define_insn "altivec_vsl"
1143   [(set (match_operand:V4SI 0 "register_operand" "=v")
1144         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1145                       (match_operand:V4SI 2 "register_operand" "v")] 110))]
1146   "TARGET_ALTIVEC"
1147   "vsl %0,%1,%2"
1148   [(set_attr "type" "vecperm")])
1149
1150 (define_insn "altivec_vslo"
1151   [(set (match_operand:V4SI 0 "register_operand" "=v")
1152         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1153                       (match_operand:V4SI 2 "register_operand" "v")] 111))]
1154   "TARGET_ALTIVEC"
1155   "vslo %0,%1,%2"
1156   [(set_attr "type" "vecperm")])
1157
1158 (define_insn "altivec_vsrb"
1159   [(set (match_operand:V16QI 0 "register_operand" "=v")
1160         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1161                        (match_operand:V16QI 2 "register_operand" "v")] 112))]
1162   "TARGET_ALTIVEC"
1163   "vsrb %0,%1,%2"
1164   [(set_attr "type" "vecsimple")])
1165
1166 (define_insn "altivec_vsrh"
1167   [(set (match_operand:V8HI 0 "register_operand" "=v")
1168         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1169                       (match_operand:V8HI 2 "register_operand" "v")] 113))]
1170   "TARGET_ALTIVEC"
1171   "vsrh %0,%1,%2"
1172   [(set_attr "type" "vecsimple")])
1173
1174 (define_insn "altivec_vsrw"
1175   [(set (match_operand:V4SI 0 "register_operand" "=v")
1176         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1177                       (match_operand:V4SI 2 "register_operand" "v")] 114))]
1178   "TARGET_ALTIVEC"
1179   "vsrw %0,%1,%2"
1180   [(set_attr "type" "vecsimple")])
1181
1182 (define_insn "altivec_vsrab"
1183   [(set (match_operand:V16QI 0 "register_operand" "=v")
1184         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1185                        (match_operand:V16QI 2 "register_operand" "v")] 115))]
1186   "TARGET_ALTIVEC"
1187   "vsrab %0,%1,%2"
1188   [(set_attr "type" "vecsimple")])
1189
1190 (define_insn "altivec_vsrah"
1191   [(set (match_operand:V8HI 0 "register_operand" "=v")
1192         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1193                       (match_operand:V8HI 2 "register_operand" "v")] 116))]
1194   "TARGET_ALTIVEC"
1195   "vsrah %0,%1,%2"
1196   [(set_attr "type" "vecsimple")])
1197
1198 (define_insn "altivec_vsraw"
1199   [(set (match_operand:V4SI 0 "register_operand" "=v")
1200         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1201                       (match_operand:V4SI 2 "register_operand" "v")] 117))]
1202   "TARGET_ALTIVEC"
1203   "vsraw %0,%1,%2"
1204   [(set_attr "type" "vecsimple")])
1205
1206 (define_insn "altivec_vsr"
1207   [(set (match_operand:V4SI 0 "register_operand" "=v")
1208         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1209                       (match_operand:V4SI 2 "register_operand" "v")] 118))]
1210   "TARGET_ALTIVEC"
1211   "vsr %0,%1,%2"
1212   [(set_attr "type" "vecperm")])
1213
1214 (define_insn "altivec_vsro"
1215   [(set (match_operand:V4SI 0 "register_operand" "=v")
1216         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1217                       (match_operand:V4SI 2 "register_operand" "v")] 119))]
1218   "TARGET_ALTIVEC"
1219   "vsro %0,%1,%2"
1220   [(set_attr "type" "vecperm")])
1221
1222 (define_insn "subv16qi3"
1223   [(set (match_operand:V16QI 0 "register_operand" "=v")
1224         (minus:V16QI (match_operand:V16QI 1 "register_operand" "v")
1225                      (match_operand:V16QI 2 "register_operand" "v")))]
1226   "TARGET_ALTIVEC"
1227   "vsububm %0,%1,%2"
1228   [(set_attr "type" "vecsimple")])
1229
1230 (define_insn "subv8hi3"
1231   [(set (match_operand:V8HI 0 "register_operand" "=v")
1232         (minus:V8HI (match_operand:V8HI 1 "register_operand" "v")
1233                     (match_operand:V8HI 2 "register_operand" "v")))]
1234   "TARGET_ALTIVEC"
1235   "vsubuhm %0,%1,%2"
1236   [(set_attr "type" "vecsimple")])
1237
1238 (define_insn "subv4si3"
1239   [(set (match_operand:V4SI 0 "register_operand" "=v")
1240         (minus:V4SI (match_operand:V4SI 1 "register_operand" "v")
1241                     (match_operand:V4SI 2 "register_operand" "v")))]
1242   "TARGET_ALTIVEC"
1243   "vsubuwm %0,%1,%2"
1244   [(set_attr "type" "vecsimple")])
1245
1246 (define_insn "subv4sf3"
1247   [(set (match_operand:V4SF 0 "register_operand" "=v")
1248         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
1249                     (match_operand:V4SF 2 "register_operand" "v")))]
1250   "TARGET_ALTIVEC"
1251   "vsubfp %0,%1,%2"
1252   [(set_attr "type" "vecfloat")])
1253
1254 (define_insn "altivec_vsubcuw"
1255   [(set (match_operand:V4SI 0 "register_operand" "=v")
1256         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1257                       (match_operand:V4SI 2 "register_operand" "v")] 124))]
1258   "TARGET_ALTIVEC"
1259   "vsubcuw %0,%1,%2"
1260   [(set_attr "type" "vecsimple")])
1261
1262 (define_insn "altivec_vsububs"
1263   [(set (match_operand:V16QI 0 "register_operand" "=v")
1264         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1265                        (match_operand:V16QI 2 "register_operand" "v")] 125))
1266    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1267   "TARGET_ALTIVEC"
1268   "vsububs %0,%1,%2"
1269   [(set_attr "type" "vecsimple")])
1270
1271 (define_insn "altivec_vsubsbs"
1272   [(set (match_operand:V16QI 0 "register_operand" "=v")
1273         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1274                        (match_operand:V16QI 2 "register_operand" "v")] 126))
1275    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1276   "TARGET_ALTIVEC"
1277   "vsubsbs %0,%1,%2"
1278   [(set_attr "type" "vecsimple")])
1279
1280 (define_insn "altivec_vsubuhs"
1281   [(set (match_operand:V8HI 0 "register_operand" "=v")
1282         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1283                       (match_operand:V8HI 2 "register_operand" "v")] 127))
1284    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1285   "TARGET_ALTIVEC"
1286   "vsubuhs %0,%1,%2"
1287   [(set_attr "type" "vecsimple")])
1288
1289 (define_insn "altivec_vsubshs"
1290   [(set (match_operand:V8HI 0 "register_operand" "=v")
1291         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1292                       (match_operand:V8HI 2 "register_operand" "v")] 128))
1293    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1294   "TARGET_ALTIVEC"
1295   "vsubshs %0,%1,%2"
1296   [(set_attr "type" "vecsimple")])
1297
1298 (define_insn "altivec_vsubuws"
1299   [(set (match_operand:V4SI 0 "register_operand" "=v")
1300         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1301                       (match_operand:V4SI 2 "register_operand" "v")] 129))
1302    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1303   "TARGET_ALTIVEC"
1304   "vsubuws %0,%1,%2"
1305   [(set_attr "type" "vecsimple")])
1306
1307 (define_insn "altivec_vsubsws"
1308   [(set (match_operand:V4SI 0 "register_operand" "=v")
1309         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1310                       (match_operand:V4SI 2 "register_operand" "v")] 130))
1311    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1312   "TARGET_ALTIVEC"
1313   "vsubsws %0,%1,%2"
1314   [(set_attr "type" "vecsimple")])
1315
1316 (define_insn "altivec_vsum4ubs"
1317   [(set (match_operand:V4SI 0 "register_operand" "=v")
1318         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1319                       (match_operand:V4SI 2 "register_operand" "v")] 131))
1320    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1321   "TARGET_ALTIVEC"
1322   "vsum4ubs %0,%1,%2"
1323   [(set_attr "type" "veccomplex")])
1324
1325 (define_insn "altivec_vsum4sbs"
1326   [(set (match_operand:V4SI 0 "register_operand" "=v")
1327         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1328                       (match_operand:V4SI 2 "register_operand" "v")] 132))
1329    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1330   "TARGET_ALTIVEC"
1331   "vsum4sbs %0,%1,%2"
1332   [(set_attr "type" "veccomplex")])
1333
1334 (define_insn "altivec_vsum4shs"
1335   [(set (match_operand:V4SI 0 "register_operand" "=v")
1336         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1337                       (match_operand:V4SI 2 "register_operand" "v")] 133))
1338    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1339   "TARGET_ALTIVEC"
1340   "vsum4shs %0,%1,%2"
1341   [(set_attr "type" "veccomplex")])
1342
1343 (define_insn "altivec_vsum2sws"
1344   [(set (match_operand:V4SI 0 "register_operand" "=v")
1345         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1346                       (match_operand:V4SI 2 "register_operand" "v")] 134))
1347    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1348   "TARGET_ALTIVEC"
1349   "vsum2sws %0,%1,%2"
1350   [(set_attr "type" "veccomplex")])
1351
1352 (define_insn "altivec_vsumsws"
1353   [(set (match_operand:V4SI 0 "register_operand" "=v")
1354         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1355                       (match_operand:V4SI 2 "register_operand" "v")] 135))
1356    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1357   "TARGET_ALTIVEC"
1358   "vsumsws %0,%1,%2"
1359   [(set_attr "type" "veccomplex")])
1360
1361 ;; Vector xor's
1362 (define_insn "xorv4si3"
1363   [(set (match_operand:V4SI 0 "register_operand" "=v")
1364         (xor:V4SI (match_operand:V4SI 1 "register_operand" "v")
1365                   (match_operand:V4SI 2 "register_operand" "v")))]
1366   "TARGET_ALTIVEC"
1367   "vxor %0,%1,%2"
1368   [(set_attr "type" "vecsimple")])
1369
1370 (define_insn "xorv8hi3"
1371   [(set (match_operand:V8HI 0 "register_operand" "=v")
1372         (xor:V8HI (match_operand:V8HI 1 "register_operand" "v")
1373                   (match_operand:V8HI 2 "register_operand" "v")))]
1374   "TARGET_ALTIVEC"
1375   "vxor %0,%1,%2"
1376   [(set_attr "type" "vecsimple")])
1377
1378 (define_insn "xorv16qi3"
1379   [(set (match_operand:V16QI 0 "register_operand" "=v")
1380         (xor:V16QI (match_operand:V16QI 1 "register_operand" "v")
1381                    (match_operand:V16QI 2 "register_operand" "v")))]
1382   "TARGET_ALTIVEC"
1383   "vxor %0,%1,%2"
1384   [(set_attr "type" "vecsimple")])
1385
1386 (define_insn "altivec_vspltb"
1387   [(set (match_operand:V16QI 0 "register_operand" "=v")
1388         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1389                        (match_operand:QI 2 "immediate_operand" "i")] 136))]
1390   "TARGET_ALTIVEC"
1391   "vspltb %0,%1,%2"
1392   [(set_attr "type" "vecperm")])
1393 ;; End of vector xor's
1394
1395 (define_insn "altivec_vsplth"
1396   [(set (match_operand:V8HI 0 "register_operand" "=v")
1397         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1398                       (match_operand:QI 2 "immediate_operand" "i")] 137))]
1399   "TARGET_ALTIVEC"
1400   "vsplth %0,%1,%2"
1401   [(set_attr "type" "vecperm")])
1402
1403 (define_insn "altivec_vspltw"
1404   [(set (match_operand:V4SI 0 "register_operand" "=v")
1405         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1406                       (match_operand:QI 2 "immediate_operand" "i")] 138))]
1407   "TARGET_ALTIVEC"
1408   "vspltw %0,%1,%2"
1409   [(set_attr "type" "vecperm")])
1410
1411 (define_insn "altivec_vspltisb"
1412   [(set (match_operand:V16QI 0 "register_operand" "=v")
1413         (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")]
1414                       UNSPEC_VSPLTISB))]
1415   "TARGET_ALTIVEC"
1416   "vspltisb %0,%1"
1417   [(set_attr "type" "vecperm")])
1418
1419 (define_insn "altivec_vspltish"
1420   [(set (match_operand:V8HI 0 "register_operand" "=v")
1421         (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")]
1422                      UNSPEC_VSPLTISH))]
1423   "TARGET_ALTIVEC"
1424   "vspltish %0,%1"
1425   [(set_attr "type" "vecperm")])
1426
1427 (define_insn "altivec_vspltisw"
1428   [(set (match_operand:V4SI 0 "register_operand" "=v")
1429         (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")]
1430                      UNSPEC_VSPLTISW))]
1431   "TARGET_ALTIVEC"
1432   "vspltisw %0,%1"
1433   [(set_attr "type" "vecperm")])
1434
1435 (define_insn "altivec_vspltisw_v4sf"
1436   [(set (match_operand:V4SF 0 "register_operand" "=v")
1437         (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
1438   "TARGET_ALTIVEC"
1439   "vspltisw %0,%1"
1440   [(set_attr "type" "vecperm")])
1441
1442 (define_insn "ftruncv4sf2"
1443   [(set (match_operand:V4SF 0 "register_operand" "=v")
1444         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1445   "TARGET_ALTIVEC"
1446   "vrfiz %0,%1"
1447   [(set_attr "type" "vecfloat")])
1448
1449 (define_insn "altivec_vperm_4si"
1450   [(set (match_operand:V4SI 0 "register_operand" "=v")
1451         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1452                       (match_operand:V4SI 2 "register_operand" "v")
1453                       (match_operand:V16QI 3 "register_operand" "v")] 144))]
1454   "TARGET_ALTIVEC"
1455   "vperm %0,%1,%2,%3"
1456   [(set_attr "type" "vecperm")])
1457
1458 (define_insn "altivec_vperm_4sf"
1459   [(set (match_operand:V4SF 0 "register_operand" "=v")
1460         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1461                       (match_operand:V4SF 2 "register_operand" "v")
1462                       (match_operand:V16QI 3 "register_operand" "v")] 145))]
1463   "TARGET_ALTIVEC"
1464   "vperm %0,%1,%2,%3"
1465   [(set_attr "type" "vecperm")])
1466
1467 (define_insn "altivec_vperm_8hi"
1468   [(set (match_operand:V8HI 0 "register_operand" "=v")
1469         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1470                       (match_operand:V8HI 2 "register_operand" "v")
1471                       (match_operand:V16QI 3 "register_operand" "v")] 146))]
1472   "TARGET_ALTIVEC"
1473   "vperm %0,%1,%2,%3"
1474   [(set_attr "type" "vecperm")])
1475
1476 (define_insn "altivec_vperm_16qi"
1477   [(set (match_operand:V16QI 0 "register_operand" "=v")
1478         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1479                        (match_operand:V16QI 2 "register_operand" "v")
1480                        (match_operand:V16QI 3 "register_operand" "v")] 147))]
1481   "TARGET_ALTIVEC"
1482   "vperm %0,%1,%2,%3"
1483   [(set_attr "type" "vecperm")])
1484
1485 (define_insn "altivec_vrfip"
1486   [(set (match_operand:V4SF 0 "register_operand" "=v")
1487         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))]
1488   "TARGET_ALTIVEC"
1489   "vrfip %0,%1"
1490   [(set_attr "type" "vecfloat")])
1491
1492 (define_insn "altivec_vrfin"
1493   [(set (match_operand:V4SF 0 "register_operand" "=v")
1494         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))]
1495   "TARGET_ALTIVEC"
1496   "vrfin %0,%1"
1497   [(set_attr "type" "vecfloat")])
1498
1499 (define_insn "altivec_vrfim"
1500   [(set (match_operand:V4SF 0 "register_operand" "=v")
1501         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))]
1502   "TARGET_ALTIVEC"
1503   "vrfim %0,%1"
1504   [(set_attr "type" "vecfloat")])
1505
1506 (define_insn "altivec_vcfux"
1507   [(set (match_operand:V4SF 0 "register_operand" "=v")
1508         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1509                       (match_operand:QI 2 "immediate_operand" "i")] 151))]
1510   "TARGET_ALTIVEC"
1511   "vcfux %0,%1,%2"
1512   [(set_attr "type" "vecfloat")])
1513
1514 (define_insn "altivec_vcfsx"
1515   [(set (match_operand:V4SF 0 "register_operand" "=v")
1516         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1517                       (match_operand:QI 2 "immediate_operand" "i")] 152))]
1518   "TARGET_ALTIVEC"
1519   "vcfsx %0,%1,%2"
1520   [(set_attr "type" "vecfloat")])
1521
1522 (define_insn "altivec_vctuxs"
1523   [(set (match_operand:V4SI 0 "register_operand" "=v")
1524         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1525                       (match_operand:QI 2 "immediate_operand" "i")] 153))
1526    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1527   "TARGET_ALTIVEC"
1528   "vctuxs %0,%1,%2"
1529   [(set_attr "type" "vecfloat")])
1530
1531 (define_insn "altivec_vctsxs"
1532   [(set (match_operand:V4SI 0 "register_operand" "=v")
1533         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1534                       (match_operand:QI 2 "immediate_operand" "i")] 154))
1535    (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
1536   "TARGET_ALTIVEC"
1537   "vctsxs %0,%1,%2"
1538   [(set_attr "type" "vecfloat")])
1539
1540 (define_insn "altivec_vlogefp"
1541   [(set (match_operand:V4SF 0 "register_operand" "=v")
1542         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))]
1543   "TARGET_ALTIVEC"
1544   "vlogefp %0,%1"
1545   [(set_attr "type" "vecfloat")])
1546
1547 (define_insn "altivec_vexptefp"
1548   [(set (match_operand:V4SF 0 "register_operand" "=v")
1549         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))]
1550   "TARGET_ALTIVEC"
1551   "vexptefp %0,%1"
1552   [(set_attr "type" "vecfloat")])
1553
1554 (define_insn "altivec_vrsqrtefp"
1555   [(set (match_operand:V4SF 0 "register_operand" "=v")
1556         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))]
1557   "TARGET_ALTIVEC"
1558   "vrsqrtefp %0,%1"
1559   [(set_attr "type" "vecfloat")])
1560
1561 (define_insn "altivec_vrefp"
1562   [(set (match_operand:V4SF 0 "register_operand" "=v")
1563         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))]
1564   "TARGET_ALTIVEC"
1565   "vrefp %0,%1"
1566   [(set_attr "type" "vecfloat")])
1567
1568 (define_insn "altivec_vsel_4si"
1569   [(set (match_operand:V4SI 0 "register_operand" "=v")
1570         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1571                       (match_operand:V4SI 2 "register_operand" "v")
1572                       (match_operand:V4SI 3 "register_operand" "v")] 159))]
1573   "TARGET_ALTIVEC"
1574   "vsel %0,%1,%2,%3"
1575   [(set_attr "type" "vecperm")])
1576
1577 (define_insn "altivec_vsel_4sf"
1578   [(set (match_operand:V4SF 0 "register_operand" "=v")
1579         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1580                       (match_operand:V4SF 2 "register_operand" "v")
1581                       (match_operand:V4SI 3 "register_operand" "v")] 160))]
1582   "TARGET_ALTIVEC"
1583   "vsel %0,%1,%2,%3"
1584   [(set_attr "type" "vecperm")])
1585
1586 (define_insn "altivec_vsel_8hi"
1587   [(set (match_operand:V8HI 0 "register_operand" "=v")
1588         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1589                       (match_operand:V8HI 2 "register_operand" "v")
1590                       (match_operand:V8HI 3 "register_operand" "v")] 161))]
1591   "TARGET_ALTIVEC"
1592   "vsel %0,%1,%2,%3"
1593   [(set_attr "type" "vecperm")])
1594
1595 (define_insn "altivec_vsel_16qi"
1596   [(set (match_operand:V16QI 0 "register_operand" "=v")
1597         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1598                        (match_operand:V16QI 2 "register_operand" "v")
1599                        (match_operand:V16QI 3 "register_operand" "v")] 162))]
1600   "TARGET_ALTIVEC"
1601   "vsel %0,%1,%2,%3"
1602   [(set_attr "type" "vecperm")])
1603
1604 (define_insn "altivec_vsldoi_4si"
1605   [(set (match_operand:V4SI 0 "register_operand" "=v")
1606         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1607                       (match_operand:V4SI 2 "register_operand" "v")
1608                       (match_operand:QI 3 "immediate_operand" "i")] 163))]
1609   "TARGET_ALTIVEC"
1610   "vsldoi %0,%1,%2,%3"
1611   [(set_attr "type" "vecperm")])
1612
1613 (define_insn "altivec_vsldoi_4sf"
1614   [(set (match_operand:V4SF 0 "register_operand" "=v")
1615         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1616                       (match_operand:V4SF 2 "register_operand" "v")
1617                       (match_operand:QI 3 "immediate_operand" "i")] 164))]
1618   "TARGET_ALTIVEC"
1619   "vsldoi %0,%1,%2,%3"
1620   [(set_attr "type" "vecperm")])
1621
1622 (define_insn "altivec_vsldoi_8hi"
1623   [(set (match_operand:V8HI 0 "register_operand" "=v")
1624         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1625                       (match_operand:V8HI 2 "register_operand" "v")
1626                       (match_operand:QI 3 "immediate_operand" "i")] 165))]
1627   "TARGET_ALTIVEC"
1628   "vsldoi %0,%1,%2,%3"
1629   [(set_attr "type" "vecperm")])
1630
1631 (define_insn "altivec_vsldoi_16qi"
1632   [(set (match_operand:V16QI 0 "register_operand" "=v")
1633         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1634                        (match_operand:V16QI 2 "register_operand" "v")
1635                        (match_operand:QI 3 "immediate_operand" "i")] 166))]
1636   "TARGET_ALTIVEC"
1637   "vsldoi %0,%1,%2,%3"
1638   [(set_attr "type" "vecperm")])
1639
1640 (define_insn "altivec_vupkhsb"
1641   [(set (match_operand:V8HI 0 "register_operand" "=v")
1642         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))]
1643   "TARGET_ALTIVEC"
1644   "vupkhsb %0,%1"
1645   [(set_attr "type" "vecperm")])
1646
1647 (define_insn "altivec_vupkhpx"
1648   [(set (match_operand:V4SI 0 "register_operand" "=v")
1649         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))]
1650   "TARGET_ALTIVEC"
1651   "vupkhpx %0,%1"
1652   [(set_attr "type" "vecperm")])
1653
1654 (define_insn "altivec_vupkhsh"
1655   [(set (match_operand:V4SI 0 "register_operand" "=v")
1656         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))]
1657   "TARGET_ALTIVEC"
1658   "vupkhsh %0,%1"
1659   [(set_attr "type" "vecperm")])
1660
1661 (define_insn "altivec_vupklsb"
1662   [(set (match_operand:V8HI 0 "register_operand" "=v")
1663         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))]
1664   "TARGET_ALTIVEC"
1665   "vupklsb %0,%1"
1666   [(set_attr "type" "vecperm")])
1667
1668 (define_insn "altivec_vupklpx"
1669   [(set (match_operand:V4SI 0 "register_operand" "=v")
1670         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))]
1671   "TARGET_ALTIVEC"
1672   "vupklpx %0,%1"
1673   [(set_attr "type" "vecperm")])
1674
1675 (define_insn "altivec_vupklsh"
1676   [(set (match_operand:V4SI 0 "register_operand" "=v")
1677         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))]
1678   "TARGET_ALTIVEC"
1679   "vupklsh %0,%1"
1680   [(set_attr "type" "vecperm")])
1681
1682 ;; AltiVec predicates.
1683
1684 (define_expand "cr6_test_for_zero"
1685   [(set (match_operand:SI 0 "register_operand" "=r")
1686         (eq:SI (reg:CC 74)
1687                (const_int 0)))]
1688   "TARGET_ALTIVEC"
1689   "")
1690
1691 (define_expand "cr6_test_for_zero_reverse"
1692   [(set (match_operand:SI 0 "register_operand" "=r")
1693         (eq:SI (reg:CC 74)
1694                (const_int 0)))
1695    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1696   "TARGET_ALTIVEC"
1697   "")
1698
1699 (define_expand "cr6_test_for_lt"
1700   [(set (match_operand:SI 0 "register_operand" "=r")
1701         (lt:SI (reg:CC 74)
1702                (const_int 0)))]
1703   "TARGET_ALTIVEC"
1704   "")
1705
1706 (define_expand "cr6_test_for_lt_reverse"
1707   [(set (match_operand:SI 0 "register_operand" "=r")
1708         (lt:SI (reg:CC 74)
1709                (const_int 0)))
1710    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1711   "TARGET_ALTIVEC"
1712   "")
1713
1714 ;; We can get away with generating the opcode on the fly (%3 below)
1715 ;; because all the predicates have the same scheduling parameters.
1716
1717 (define_insn "altivec_predicate_v4si"
1718   [(set (reg:CC 74)
1719         (unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
1720                     (match_operand:V4SI 2 "register_operand" "v")
1721                     (match_operand 3 "any_operand" "")] 173))
1722    (clobber (match_scratch:V4SI 0 "=v"))]
1723   "TARGET_ALTIVEC"
1724   "%3 %0,%1,%2"
1725 [(set_attr "type" "veccmp")])
1726
1727 (define_insn "altivec_predicate_v4sf"
1728   [(set (reg:CC 74)
1729         (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1730                     (match_operand:V4SF 2 "register_operand" "v")
1731                     (match_operand 3 "any_operand" "")] 174))
1732    (clobber (match_scratch:V4SF 0 "=v"))]
1733   "TARGET_ALTIVEC"
1734   "%3 %0,%1,%2"
1735 [(set_attr "type" "veccmp")])
1736
1737 (define_insn "altivec_predicate_v8hi"
1738   [(set (reg:CC 74)
1739         (unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
1740                     (match_operand:V8HI 2 "register_operand" "v")
1741                     (match_operand 3 "any_operand" "")] 175))
1742    (clobber (match_scratch:V8HI 0 "=v"))]
1743   "TARGET_ALTIVEC"
1744   "%3 %0,%1,%2"
1745 [(set_attr "type" "veccmp")])
1746
1747 (define_insn "altivec_predicate_v16qi"
1748   [(set (reg:CC 74)
1749         (unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
1750                     (match_operand:V16QI 2 "register_operand" "v")
1751                     (match_operand 3 "any_operand" "")] 175))
1752    (clobber (match_scratch:V16QI 0 "=v"))]
1753   "TARGET_ALTIVEC"
1754   "%3 %0,%1,%2"
1755 [(set_attr "type" "veccmp")])
1756
1757 (define_insn "altivec_mtvscr"
1758   [(set (reg:SI 110)
1759         (unspec_volatile:SI
1760          [(match_operand:V4SI 0 "register_operand" "v")] 186))]
1761   "TARGET_ALTIVEC"
1762   "mtvscr %0"
1763   [(set_attr "type" "vecsimple")])
1764
1765 (define_insn "altivec_mfvscr"
1766   [(set (match_operand:V8HI 0 "register_operand" "=v")
1767         (unspec_volatile:V8HI [(reg:SI 110)] 187))]
1768   "TARGET_ALTIVEC"
1769   "mfvscr %0"
1770   [(set_attr "type" "vecsimple")])
1771
1772 (define_insn "altivec_dssall"
1773   [(unspec [(const_int 0)] 188)]
1774   "TARGET_ALTIVEC"
1775   "dssall"
1776   [(set_attr "type" "vecsimple")])
1777
1778 (define_insn "altivec_dss"
1779   [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)]
1780   "TARGET_ALTIVEC"
1781   "dss %0"
1782   [(set_attr "type" "vecsimple")])
1783
1784 (define_insn "altivec_dst"
1785   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1786             (match_operand:SI 1 "register_operand" "r")
1787             (match_operand:QI 2 "immediate_operand" "i")] 190)]
1788   "TARGET_ALTIVEC"
1789   "dst %P0,%1,%2"
1790   [(set_attr "type" "vecsimple")])
1791
1792 (define_insn "altivec_dstt"
1793   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1794             (match_operand:SI 1 "register_operand" "r")
1795             (match_operand:QI 2 "immediate_operand" "i")] 191)]
1796   "TARGET_ALTIVEC"
1797   "dstt %P0,%1,%2"
1798   [(set_attr "type" "vecsimple")])
1799
1800 (define_insn "altivec_dstst"
1801   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1802             (match_operand:SI 1 "register_operand" "r")
1803             (match_operand:QI 2 "immediate_operand" "i")] 192)]
1804   "TARGET_ALTIVEC"
1805   "dstst %P0,%1,%2"
1806   [(set_attr "type" "vecsimple")])
1807
1808 (define_insn "altivec_dststt"
1809   [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
1810             (match_operand:SI 1 "register_operand" "r")
1811             (match_operand:QI 2 "immediate_operand" "i")] 193)]
1812   "TARGET_ALTIVEC"
1813   "dststt %P0,%1,%2"
1814   [(set_attr "type" "vecsimple")])
1815
1816 (define_insn "altivec_lvsl"
1817   [(set (match_operand:V16QI 0 "register_operand" "=v")
1818         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 194))]
1819   "TARGET_ALTIVEC"
1820   "lvsl %0,%y1"
1821   [(set_attr "type" "vecload")])
1822
1823 (define_insn "altivec_lvsr"
1824   [(set (match_operand:V16QI 0 "register_operand" "=v")
1825         (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
1826   "TARGET_ALTIVEC"
1827   "lvsr %0,%y1"
1828   [(set_attr "type" "vecload")])
1829
1830 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1831 ;; identical rtl but different instructions-- and gcc gets confused.
1832
1833 (define_insn "altivec_lvebx"
1834   [(parallel
1835     [(set (match_operand:V16QI 0 "register_operand" "=v")
1836           (match_operand:V16QI 1 "memory_operand" "m"))
1837      (unspec [(const_int 0)] 196)])]
1838   "TARGET_ALTIVEC"
1839   "lvebx %0,%y1"
1840   [(set_attr "type" "vecload")])
1841
1842 (define_insn "altivec_lvehx"
1843   [(parallel
1844     [(set (match_operand:V8HI 0 "register_operand" "=v")
1845           (match_operand:V8HI 1 "memory_operand" "m"))
1846      (unspec [(const_int 0)] 197)])]
1847   "TARGET_ALTIVEC"
1848   "lvehx %0,%y1"
1849   [(set_attr "type" "vecload")])
1850
1851 (define_insn "altivec_lvewx"
1852   [(parallel
1853     [(set (match_operand:V4SI 0 "register_operand" "=v")
1854           (match_operand:V4SI 1 "memory_operand" "m"))
1855      (unspec [(const_int 0)] 198)])]
1856   "TARGET_ALTIVEC"
1857   "lvewx %0,%y1"
1858   [(set_attr "type" "vecload")])
1859
1860 (define_insn "altivec_lvxl"
1861   [(parallel
1862     [(set (match_operand:V4SI 0 "register_operand" "=v")
1863           (match_operand:V4SI 1 "memory_operand" "m"))
1864      (unspec [(const_int 0)] 213)])]
1865   "TARGET_ALTIVEC"
1866   "lvxl %0,%y1"
1867   [(set_attr "type" "vecload")])
1868
1869 (define_insn "altivec_lvx"
1870   [(set (match_operand:V4SI 0 "register_operand" "=v")
1871         (match_operand:V4SI 1 "memory_operand" "m"))]
1872   "TARGET_ALTIVEC"
1873   "lvx %0,%y1"
1874   [(set_attr "type" "vecload")])
1875
1876 (define_insn "altivec_stvx"
1877   [(parallel
1878     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1879           (match_operand:V4SI 1 "register_operand" "v"))
1880      (unspec [(const_int 0)] 201)])]
1881   "TARGET_ALTIVEC"
1882   "stvx %1,%y0"
1883   [(set_attr "type" "vecstore")])
1884
1885 (define_insn "altivec_stvxl"
1886   [(parallel
1887     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1888           (match_operand:V4SI 1 "register_operand" "v"))
1889      (unspec [(const_int 0)] 202)])]
1890   "TARGET_ALTIVEC"
1891   "stvxl %1,%y0"
1892   [(set_attr "type" "vecstore")])
1893
1894 (define_insn "altivec_stvebx"
1895   [(parallel
1896     [(set (match_operand:V16QI 0 "memory_operand" "=m")
1897           (match_operand:V16QI 1 "register_operand" "v"))
1898      (unspec [(const_int 0)] 203)])]
1899   "TARGET_ALTIVEC"
1900   "stvebx %1,%y0"
1901   [(set_attr "type" "vecstore")])
1902
1903 (define_insn "altivec_stvehx"
1904   [(parallel
1905     [(set (match_operand:V8HI 0 "memory_operand" "=m")
1906           (match_operand:V8HI 1 "register_operand" "v"))
1907      (unspec [(const_int 0)] 204)])]
1908   "TARGET_ALTIVEC"
1909   "stvehx %1,%y0"
1910   [(set_attr "type" "vecstore")])
1911
1912 (define_insn "altivec_stvewx"
1913   [(parallel
1914     [(set (match_operand:V4SI 0 "memory_operand" "=m")
1915           (match_operand:V4SI 1 "register_operand" "v"))
1916      (unspec [(const_int 0)] 205)])]
1917   "TARGET_ALTIVEC"
1918   "stvewx %1,%y0"
1919   [(set_attr "type" "vecstore")])
1920
1921 (define_insn "absv16qi2"
1922   [(set (match_operand:V16QI 0 "register_operand" "=v")
1923         (abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
1924    (clobber (match_scratch:V16QI 2 "=&v"))
1925    (clobber (match_scratch:V16QI 3 "=&v"))]
1926   "TARGET_ALTIVEC"
1927   "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
1928   [(set_attr "type" "vecsimple")
1929    (set_attr "length" "12")])
1930
1931 (define_insn "absv8hi2"
1932   [(set (match_operand:V8HI 0 "register_operand" "=v")
1933         (abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
1934    (clobber (match_scratch:V8HI 2 "=&v"))
1935    (clobber (match_scratch:V8HI 3 "=&v"))]
1936   "TARGET_ALTIVEC"
1937   "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
1938   [(set_attr "type" "vecsimple")
1939    (set_attr "length" "12")])
1940
1941 (define_insn "absv4si2"
1942   [(set (match_operand:V4SI 0 "register_operand" "=v")
1943         (abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
1944    (clobber (match_scratch:V4SI 2 "=&v"))
1945    (clobber (match_scratch:V4SI 3 "=&v"))]
1946   "TARGET_ALTIVEC"
1947   "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
1948   [(set_attr "type" "vecsimple")
1949    (set_attr "length" "12")])
1950
1951 (define_insn "absv4sf2"
1952   [(set (match_operand:V4SF 0 "register_operand" "=v")
1953         (abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
1954    (clobber (match_scratch:V4SF 2 "=&v"))
1955    (clobber (match_scratch:V4SF 3 "=&v"))]
1956   "TARGET_ALTIVEC"
1957   "vspltisw %2,-1\;vslw %3,%2,%2\;vandc %0,%1,%3"
1958   [(set_attr "type" "vecsimple")
1959    (set_attr "length" "12")])
1960
1961 (define_insn "altivec_abss_v16qi"
1962   [(set (match_operand:V16QI 0 "register_operand" "=v")
1963         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
1964    (clobber (match_scratch:V16QI 2 "=&v"))
1965    (clobber (match_scratch:V16QI 3 "=&v"))]
1966   "TARGET_ALTIVEC"
1967   "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
1968   [(set_attr "type" "vecsimple")
1969    (set_attr "length" "12")])
1970
1971 (define_insn "altivec_abss_v8hi"
1972   [(set (match_operand:V8HI 0 "register_operand" "=v")
1973         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
1974    (clobber (match_scratch:V8HI 2 "=&v"))
1975    (clobber (match_scratch:V8HI 3 "=&v"))]
1976   "TARGET_ALTIVEC"
1977   "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
1978   [(set_attr "type" "vecsimple")
1979    (set_attr "length" "12")])
1980
1981 (define_insn "altivec_abss_v4si"
1982   [(set (match_operand:V4SI 0 "register_operand" "=v")
1983         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
1984    (clobber (match_scratch:V4SI 2 "=&v"))
1985    (clobber (match_scratch:V4SI 3 "=&v"))]
1986   "TARGET_ALTIVEC"
1987   "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
1988   [(set_attr "type" "vecsimple")
1989    (set_attr "length" "12")])