1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit
57 ;; UNSPEC_VOLATILE usage
62 (UNSPECV_EH_RR 9) ; eh_reg_restore
65 ;; Define an insn type attribute. This is used in function unit delay
67 (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
68 (const_string "integer"))
71 ; '(pc)' in the following doesn't include the instruction itself; it is
72 ; calculated as if the instruction had zero size.
73 (define_attr "length" ""
74 (if_then_else (eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
77 (lt (minus (match_dup 0) (pc))
83 ;; Processor type -- this attribute must exactly match the processor_type
84 ;; enumeration in rs6000.h.
86 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
87 (const (symbol_ref "rs6000_cpu_attr")))
89 (automata_option "ndfa")
102 (include "power4.md")
103 (include "power5.md")
106 ;; Start with fixed-point load and store insns. Here we put only the more
107 ;; complex forms. Basic data transfer is done later.
109 (define_expand "zero_extendqidi2"
110 [(set (match_operand:DI 0 "gpc_reg_operand" "")
111 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
116 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
117 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
122 [(set_attr "type" "load,*")])
125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
126 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
128 (clobber (match_scratch:DI 2 "=r,r"))]
133 [(set_attr "type" "compare")
134 (set_attr "length" "4,8")])
137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
138 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
140 (clobber (match_scratch:DI 2 ""))]
141 "TARGET_POWERPC64 && reload_completed"
143 (zero_extend:DI (match_dup 1)))
145 (compare:CC (match_dup 2)
150 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
151 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
153 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
154 (zero_extend:DI (match_dup 1)))]
159 [(set_attr "type" "compare")
160 (set_attr "length" "4,8")])
163 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
164 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
166 (set (match_operand:DI 0 "gpc_reg_operand" "")
167 (zero_extend:DI (match_dup 1)))]
168 "TARGET_POWERPC64 && reload_completed"
170 (zero_extend:DI (match_dup 1)))
172 (compare:CC (match_dup 0)
176 (define_insn "extendqidi2"
177 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
178 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
184 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
186 (clobber (match_scratch:DI 2 "=r,r"))]
191 [(set_attr "type" "compare")
192 (set_attr "length" "4,8")])
195 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
196 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
198 (clobber (match_scratch:DI 2 ""))]
199 "TARGET_POWERPC64 && reload_completed"
201 (sign_extend:DI (match_dup 1)))
203 (compare:CC (match_dup 2)
208 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
209 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
211 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
212 (sign_extend:DI (match_dup 1)))]
217 [(set_attr "type" "compare")
218 (set_attr "length" "4,8")])
221 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
222 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
224 (set (match_operand:DI 0 "gpc_reg_operand" "")
225 (sign_extend:DI (match_dup 1)))]
226 "TARGET_POWERPC64 && reload_completed"
228 (sign_extend:DI (match_dup 1)))
230 (compare:CC (match_dup 0)
234 (define_expand "zero_extendhidi2"
235 [(set (match_operand:DI 0 "gpc_reg_operand" "")
236 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
242 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
247 [(set_attr "type" "load,*")])
250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
251 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
253 (clobber (match_scratch:DI 2 "=r,r"))]
258 [(set_attr "type" "compare")
259 (set_attr "length" "4,8")])
262 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
263 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
265 (clobber (match_scratch:DI 2 ""))]
266 "TARGET_POWERPC64 && reload_completed"
268 (zero_extend:DI (match_dup 1)))
270 (compare:CC (match_dup 2)
275 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
276 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
278 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
279 (zero_extend:DI (match_dup 1)))]
284 [(set_attr "type" "compare")
285 (set_attr "length" "4,8")])
288 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
289 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
291 (set (match_operand:DI 0 "gpc_reg_operand" "")
292 (zero_extend:DI (match_dup 1)))]
293 "TARGET_POWERPC64 && reload_completed"
295 (zero_extend:DI (match_dup 1)))
297 (compare:CC (match_dup 0)
301 (define_expand "extendhidi2"
302 [(set (match_operand:DI 0 "gpc_reg_operand" "")
303 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
308 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
309 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
314 [(set_attr "type" "load_ext,*")])
317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
318 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
320 (clobber (match_scratch:DI 2 "=r,r"))]
325 [(set_attr "type" "compare")
326 (set_attr "length" "4,8")])
329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
330 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
332 (clobber (match_scratch:DI 2 ""))]
333 "TARGET_POWERPC64 && reload_completed"
335 (sign_extend:DI (match_dup 1)))
337 (compare:CC (match_dup 2)
342 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
343 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
345 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
346 (sign_extend:DI (match_dup 1)))]
351 [(set_attr "type" "compare")
352 (set_attr "length" "4,8")])
355 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
356 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
358 (set (match_operand:DI 0 "gpc_reg_operand" "")
359 (sign_extend:DI (match_dup 1)))]
360 "TARGET_POWERPC64 && reload_completed"
362 (sign_extend:DI (match_dup 1)))
364 (compare:CC (match_dup 0)
368 (define_expand "zero_extendsidi2"
369 [(set (match_operand:DI 0 "gpc_reg_operand" "")
370 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
376 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
381 [(set_attr "type" "load,*")])
384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
385 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
387 (clobber (match_scratch:DI 2 "=r,r"))]
392 [(set_attr "type" "compare")
393 (set_attr "length" "4,8")])
396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
397 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
399 (clobber (match_scratch:DI 2 ""))]
400 "TARGET_POWERPC64 && reload_completed"
402 (zero_extend:DI (match_dup 1)))
404 (compare:CC (match_dup 2)
409 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
410 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
412 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
413 (zero_extend:DI (match_dup 1)))]
418 [(set_attr "type" "compare")
419 (set_attr "length" "4,8")])
422 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
423 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
425 (set (match_operand:DI 0 "gpc_reg_operand" "")
426 (zero_extend:DI (match_dup 1)))]
427 "TARGET_POWERPC64 && reload_completed"
429 (zero_extend:DI (match_dup 1)))
431 (compare:CC (match_dup 0)
435 (define_expand "extendsidi2"
436 [(set (match_operand:DI 0 "gpc_reg_operand" "")
437 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
442 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
443 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
448 [(set_attr "type" "load_ext,*")])
451 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
452 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
454 (clobber (match_scratch:DI 2 "=r,r"))]
459 [(set_attr "type" "compare")
460 (set_attr "length" "4,8")])
463 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
464 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
466 (clobber (match_scratch:DI 2 ""))]
467 "TARGET_POWERPC64 && reload_completed"
469 (sign_extend:DI (match_dup 1)))
471 (compare:CC (match_dup 2)
476 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
477 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
479 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
480 (sign_extend:DI (match_dup 1)))]
485 [(set_attr "type" "compare")
486 (set_attr "length" "4,8")])
489 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
490 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
492 (set (match_operand:DI 0 "gpc_reg_operand" "")
493 (sign_extend:DI (match_dup 1)))]
494 "TARGET_POWERPC64 && reload_completed"
496 (sign_extend:DI (match_dup 1)))
498 (compare:CC (match_dup 0)
502 (define_expand "zero_extendqisi2"
503 [(set (match_operand:SI 0 "gpc_reg_operand" "")
504 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
510 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
514 {rlinm|rlwinm} %0,%1,0,0xff"
515 [(set_attr "type" "load,*")])
518 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
519 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
521 (clobber (match_scratch:SI 2 "=r,r"))]
524 {andil.|andi.} %2,%1,0xff
526 [(set_attr "type" "compare")
527 (set_attr "length" "4,8")])
530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
531 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
533 (clobber (match_scratch:SI 2 ""))]
536 (zero_extend:SI (match_dup 1)))
538 (compare:CC (match_dup 2)
543 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
544 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
546 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
547 (zero_extend:SI (match_dup 1)))]
550 {andil.|andi.} %0,%1,0xff
552 [(set_attr "type" "compare")
553 (set_attr "length" "4,8")])
556 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
557 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
559 (set (match_operand:SI 0 "gpc_reg_operand" "")
560 (zero_extend:SI (match_dup 1)))]
563 (zero_extend:SI (match_dup 1)))
565 (compare:CC (match_dup 0)
569 (define_expand "extendqisi2"
570 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
571 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
576 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
577 else if (TARGET_POWER)
578 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
580 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
584 (define_insn "extendqisi2_ppc"
585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
586 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
592 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
594 (clobber (match_scratch:SI 2 "=r,r"))]
599 [(set_attr "type" "compare")
600 (set_attr "length" "4,8")])
603 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
604 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
606 (clobber (match_scratch:SI 2 ""))]
607 "TARGET_POWERPC && reload_completed"
609 (sign_extend:SI (match_dup 1)))
611 (compare:CC (match_dup 2)
616 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
617 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
619 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
620 (sign_extend:SI (match_dup 1)))]
625 [(set_attr "type" "compare")
626 (set_attr "length" "4,8")])
629 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
630 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
632 (set (match_operand:SI 0 "gpc_reg_operand" "")
633 (sign_extend:SI (match_dup 1)))]
634 "TARGET_POWERPC && reload_completed"
636 (sign_extend:SI (match_dup 1)))
638 (compare:CC (match_dup 0)
642 (define_expand "extendqisi2_power"
643 [(parallel [(set (match_dup 2)
644 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
646 (clobber (scratch:SI))])
647 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
648 (ashiftrt:SI (match_dup 2)
650 (clobber (scratch:SI))])]
653 { operands[1] = gen_lowpart (SImode, operands[1]);
654 operands[2] = gen_reg_rtx (SImode); }")
656 (define_expand "extendqisi2_no_power"
658 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
660 (set (match_operand:SI 0 "gpc_reg_operand" "")
661 (ashiftrt:SI (match_dup 2)
663 "! TARGET_POWER && ! TARGET_POWERPC"
665 { operands[1] = gen_lowpart (SImode, operands[1]);
666 operands[2] = gen_reg_rtx (SImode); }")
668 (define_expand "zero_extendqihi2"
669 [(set (match_operand:HI 0 "gpc_reg_operand" "")
670 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
675 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
676 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
680 {rlinm|rlwinm} %0,%1,0,0xff"
681 [(set_attr "type" "load,*")])
684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
685 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
687 (clobber (match_scratch:HI 2 "=r,r"))]
690 {andil.|andi.} %2,%1,0xff
692 [(set_attr "type" "compare")
693 (set_attr "length" "4,8")])
696 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
697 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
699 (clobber (match_scratch:HI 2 ""))]
702 (zero_extend:HI (match_dup 1)))
704 (compare:CC (match_dup 2)
709 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
710 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
712 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
713 (zero_extend:HI (match_dup 1)))]
716 {andil.|andi.} %0,%1,0xff
718 [(set_attr "type" "compare")
719 (set_attr "length" "4,8")])
722 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
723 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
725 (set (match_operand:HI 0 "gpc_reg_operand" "")
726 (zero_extend:HI (match_dup 1)))]
729 (zero_extend:HI (match_dup 1)))
731 (compare:CC (match_dup 0)
735 (define_expand "extendqihi2"
736 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
737 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
742 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
743 else if (TARGET_POWER)
744 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
746 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
750 (define_insn "extendqihi2_ppc"
751 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
752 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
758 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
760 (clobber (match_scratch:HI 2 "=r,r"))]
765 [(set_attr "type" "compare")
766 (set_attr "length" "4,8")])
769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
770 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
772 (clobber (match_scratch:HI 2 ""))]
773 "TARGET_POWERPC && reload_completed"
775 (sign_extend:HI (match_dup 1)))
777 (compare:CC (match_dup 2)
782 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
783 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
785 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
786 (sign_extend:HI (match_dup 1)))]
791 [(set_attr "type" "compare")
792 (set_attr "length" "4,8")])
795 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
796 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
798 (set (match_operand:HI 0 "gpc_reg_operand" "")
799 (sign_extend:HI (match_dup 1)))]
800 "TARGET_POWERPC && reload_completed"
802 (sign_extend:HI (match_dup 1)))
804 (compare:CC (match_dup 0)
808 (define_expand "extendqihi2_power"
809 [(parallel [(set (match_dup 2)
810 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
812 (clobber (scratch:SI))])
813 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
814 (ashiftrt:SI (match_dup 2)
816 (clobber (scratch:SI))])]
819 { operands[0] = gen_lowpart (SImode, operands[0]);
820 operands[1] = gen_lowpart (SImode, operands[1]);
821 operands[2] = gen_reg_rtx (SImode); }")
823 (define_expand "extendqihi2_no_power"
825 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
827 (set (match_operand:HI 0 "gpc_reg_operand" "")
828 (ashiftrt:SI (match_dup 2)
830 "! TARGET_POWER && ! TARGET_POWERPC"
832 { operands[0] = gen_lowpart (SImode, operands[0]);
833 operands[1] = gen_lowpart (SImode, operands[1]);
834 operands[2] = gen_reg_rtx (SImode); }")
836 (define_expand "zero_extendhisi2"
837 [(set (match_operand:SI 0 "gpc_reg_operand" "")
838 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
844 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
848 {rlinm|rlwinm} %0,%1,0,0xffff"
849 [(set_attr "type" "load,*")])
852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
853 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
855 (clobber (match_scratch:SI 2 "=r,r"))]
858 {andil.|andi.} %2,%1,0xffff
860 [(set_attr "type" "compare")
861 (set_attr "length" "4,8")])
864 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
865 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
867 (clobber (match_scratch:SI 2 ""))]
870 (zero_extend:SI (match_dup 1)))
872 (compare:CC (match_dup 2)
877 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
878 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
881 (zero_extend:SI (match_dup 1)))]
884 {andil.|andi.} %0,%1,0xffff
886 [(set_attr "type" "compare")
887 (set_attr "length" "4,8")])
890 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
891 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
893 (set (match_operand:SI 0 "gpc_reg_operand" "")
894 (zero_extend:SI (match_dup 1)))]
897 (zero_extend:SI (match_dup 1)))
899 (compare:CC (match_dup 0)
903 (define_expand "extendhisi2"
904 [(set (match_operand:SI 0 "gpc_reg_operand" "")
905 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
911 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
916 [(set_attr "type" "load_ext,*")])
919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
920 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
922 (clobber (match_scratch:SI 2 "=r,r"))]
927 [(set_attr "type" "compare")
928 (set_attr "length" "4,8")])
931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
932 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
934 (clobber (match_scratch:SI 2 ""))]
937 (sign_extend:SI (match_dup 1)))
939 (compare:CC (match_dup 2)
944 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
945 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
947 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
948 (sign_extend:SI (match_dup 1)))]
953 [(set_attr "type" "compare")
954 (set_attr "length" "4,8")])
957 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
958 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
960 (set (match_operand:SI 0 "gpc_reg_operand" "")
961 (sign_extend:SI (match_dup 1)))]
964 (sign_extend:SI (match_dup 1)))
966 (compare:CC (match_dup 0)
970 ;; Fixed-point arithmetic insns.
972 ;; Discourage ai/addic because of carry but provide it in an alternative
973 ;; allowing register zero as source.
974 (define_expand "addsi3"
975 [(set (match_operand:SI 0 "gpc_reg_operand" "")
976 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
977 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
981 if (GET_CODE (operands[2]) == CONST_INT
982 && ! add_operand (operands[2], SImode))
984 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
985 ? operands[0] : gen_reg_rtx (SImode));
987 HOST_WIDE_INT val = INTVAL (operands[2]);
988 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
989 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
991 /* The ordering here is important for the prolog expander.
992 When space is allocated from the stack, adding 'low' first may
993 produce a temporary deallocation (which would be bad). */
994 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
995 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1000 (define_insn "*addsi3_internal1"
1001 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1002 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1003 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1007 {cal %0,%2(%1)|addi %0,%1,%2}
1009 {cau|addis} %0,%1,%v2"
1010 [(set_attr "length" "4,4,4,4")])
1012 (define_insn "addsi3_high"
1013 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1014 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1015 (high:SI (match_operand 2 "" ""))))]
1016 "TARGET_MACHO && !TARGET_64BIT"
1017 "{cau|addis} %0,%1,ha16(%2)"
1018 [(set_attr "length" "4")])
1020 (define_insn "*addsi3_internal2"
1021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1022 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1023 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1025 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1028 {cax.|add.} %3,%1,%2
1029 {ai.|addic.} %3,%1,%2
1032 [(set_attr "type" "fast_compare,compare,compare,compare")
1033 (set_attr "length" "4,4,8,8")])
1036 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1037 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1038 (match_operand:SI 2 "reg_or_short_operand" ""))
1040 (clobber (match_scratch:SI 3 ""))]
1041 "TARGET_32BIT && reload_completed"
1043 (plus:SI (match_dup 1)
1046 (compare:CC (match_dup 3)
1050 (define_insn "*addsi3_internal3"
1051 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1052 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1053 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1055 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1056 (plus:SI (match_dup 1)
1060 {cax.|add.} %0,%1,%2
1061 {ai.|addic.} %0,%1,%2
1064 [(set_attr "type" "fast_compare,compare,compare,compare")
1065 (set_attr "length" "4,4,8,8")])
1068 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1069 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1070 (match_operand:SI 2 "reg_or_short_operand" ""))
1072 (set (match_operand:SI 0 "gpc_reg_operand" "")
1073 (plus:SI (match_dup 1) (match_dup 2)))]
1074 "TARGET_32BIT && reload_completed"
1076 (plus:SI (match_dup 1)
1079 (compare:CC (match_dup 0)
1083 ;; Split an add that we can't do in one insn into two insns, each of which
1084 ;; does one 16-bit part. This is used by combine. Note that the low-order
1085 ;; add should be last in case the result gets used in an address.
1088 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1089 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1090 (match_operand:SI 2 "non_add_cint_operand" "")))]
1092 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1093 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1096 HOST_WIDE_INT val = INTVAL (operands[2]);
1097 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1098 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1100 operands[3] = GEN_INT (rest);
1101 operands[4] = GEN_INT (low);
1104 (define_insn "one_cmplsi2"
1105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1106 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1111 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1112 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1114 (clobber (match_scratch:SI 2 "=r,r"))]
1119 [(set_attr "type" "compare")
1120 (set_attr "length" "4,8")])
1123 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1124 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1126 (clobber (match_scratch:SI 2 ""))]
1127 "TARGET_32BIT && reload_completed"
1129 (not:SI (match_dup 1)))
1131 (compare:CC (match_dup 2)
1136 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1137 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1139 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1140 (not:SI (match_dup 1)))]
1145 [(set_attr "type" "compare")
1146 (set_attr "length" "4,8")])
1149 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1150 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1152 (set (match_operand:SI 0 "gpc_reg_operand" "")
1153 (not:SI (match_dup 1)))]
1154 "TARGET_32BIT && reload_completed"
1156 (not:SI (match_dup 1)))
1158 (compare:CC (match_dup 0)
1163 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1164 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1165 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1167 "{sf%I1|subf%I1c} %0,%2,%1")
1170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1171 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1172 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1179 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1180 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1181 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1183 (clobber (match_scratch:SI 3 "=r,r"))]
1186 {sf.|subfc.} %3,%2,%1
1188 [(set_attr "type" "compare")
1189 (set_attr "length" "4,8")])
1192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1193 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1194 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1196 (clobber (match_scratch:SI 3 "=r,r"))]
1197 "TARGET_POWERPC && TARGET_32BIT"
1201 [(set_attr "type" "fast_compare")
1202 (set_attr "length" "4,8")])
1205 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1206 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1207 (match_operand:SI 2 "gpc_reg_operand" ""))
1209 (clobber (match_scratch:SI 3 ""))]
1210 "TARGET_32BIT && reload_completed"
1212 (minus:SI (match_dup 1)
1215 (compare:CC (match_dup 3)
1220 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1221 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1222 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1224 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1225 (minus:SI (match_dup 1) (match_dup 2)))]
1228 {sf.|subfc.} %0,%2,%1
1230 [(set_attr "type" "compare")
1231 (set_attr "length" "4,8")])
1234 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1235 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1236 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1238 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1239 (minus:SI (match_dup 1)
1241 "TARGET_POWERPC && TARGET_32BIT"
1245 [(set_attr "type" "fast_compare")
1246 (set_attr "length" "4,8")])
1249 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1250 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1251 (match_operand:SI 2 "gpc_reg_operand" ""))
1253 (set (match_operand:SI 0 "gpc_reg_operand" "")
1254 (minus:SI (match_dup 1)
1256 "TARGET_32BIT && reload_completed"
1258 (minus:SI (match_dup 1)
1261 (compare:CC (match_dup 0)
1265 (define_expand "subsi3"
1266 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1267 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1268 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1272 if (GET_CODE (operands[2]) == CONST_INT)
1274 emit_insn (gen_addsi3 (operands[0], operands[1],
1275 negate_rtx (SImode, operands[2])));
1280 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1281 ;; instruction and some auxiliary computations. Then we just have a single
1282 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1285 (define_expand "sminsi3"
1287 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1288 (match_operand:SI 2 "reg_or_short_operand" ""))
1290 (minus:SI (match_dup 2) (match_dup 1))))
1291 (set (match_operand:SI 0 "gpc_reg_operand" "")
1292 (minus:SI (match_dup 2) (match_dup 3)))]
1293 "TARGET_POWER || TARGET_ISEL"
1298 operands[2] = force_reg (SImode, operands[2]);
1299 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1303 operands[3] = gen_reg_rtx (SImode);
1307 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1308 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1309 (match_operand:SI 2 "reg_or_short_operand" "")))
1310 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1313 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1315 (minus:SI (match_dup 2) (match_dup 1))))
1316 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1319 (define_expand "smaxsi3"
1321 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1322 (match_operand:SI 2 "reg_or_short_operand" ""))
1324 (minus:SI (match_dup 2) (match_dup 1))))
1325 (set (match_operand:SI 0 "gpc_reg_operand" "")
1326 (plus:SI (match_dup 3) (match_dup 1)))]
1327 "TARGET_POWER || TARGET_ISEL"
1332 operands[2] = force_reg (SImode, operands[2]);
1333 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1336 operands[3] = gen_reg_rtx (SImode);
1340 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1341 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1342 (match_operand:SI 2 "reg_or_short_operand" "")))
1343 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1346 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1348 (minus:SI (match_dup 2) (match_dup 1))))
1349 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1352 (define_expand "uminsi3"
1353 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1355 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1357 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1359 (minus:SI (match_dup 4) (match_dup 3))))
1360 (set (match_operand:SI 0 "gpc_reg_operand" "")
1361 (minus:SI (match_dup 2) (match_dup 3)))]
1362 "TARGET_POWER || TARGET_ISEL"
1367 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1370 operands[3] = gen_reg_rtx (SImode);
1371 operands[4] = gen_reg_rtx (SImode);
1372 operands[5] = GEN_INT (-2147483647 - 1);
1375 (define_expand "umaxsi3"
1376 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1378 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1380 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1382 (minus:SI (match_dup 4) (match_dup 3))))
1383 (set (match_operand:SI 0 "gpc_reg_operand" "")
1384 (plus:SI (match_dup 3) (match_dup 1)))]
1385 "TARGET_POWER || TARGET_ISEL"
1390 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1393 operands[3] = gen_reg_rtx (SImode);
1394 operands[4] = gen_reg_rtx (SImode);
1395 operands[5] = GEN_INT (-2147483647 - 1);
1399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1400 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1401 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1403 (minus:SI (match_dup 2) (match_dup 1))))]
1408 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1410 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1411 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1413 (minus:SI (match_dup 2) (match_dup 1)))
1415 (clobber (match_scratch:SI 3 "=r,r"))]
1420 [(set_attr "type" "delayed_compare")
1421 (set_attr "length" "4,8")])
1424 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1426 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1427 (match_operand:SI 2 "reg_or_short_operand" ""))
1429 (minus:SI (match_dup 2) (match_dup 1)))
1431 (clobber (match_scratch:SI 3 ""))]
1432 "TARGET_POWER && reload_completed"
1434 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1436 (minus:SI (match_dup 2) (match_dup 1))))
1438 (compare:CC (match_dup 3)
1443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1445 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1446 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1448 (minus:SI (match_dup 2) (match_dup 1)))
1450 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1451 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1453 (minus:SI (match_dup 2) (match_dup 1))))]
1458 [(set_attr "type" "delayed_compare")
1459 (set_attr "length" "4,8")])
1462 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1464 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1465 (match_operand:SI 2 "reg_or_short_operand" ""))
1467 (minus:SI (match_dup 2) (match_dup 1)))
1469 (set (match_operand:SI 0 "gpc_reg_operand" "")
1470 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1472 (minus:SI (match_dup 2) (match_dup 1))))]
1473 "TARGET_POWER && reload_completed"
1475 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1477 (minus:SI (match_dup 2) (match_dup 1))))
1479 (compare:CC (match_dup 0)
1483 ;; We don't need abs with condition code because such comparisons should
1485 (define_expand "abssi2"
1486 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1487 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1493 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1496 else if (! TARGET_POWER)
1498 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1503 (define_insn "*abssi2_power"
1504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1505 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1509 (define_insn_and_split "abssi2_isel"
1510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1511 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1512 (clobber (match_scratch:SI 2 "=&b"))
1513 (clobber (match_scratch:CC 3 "=y"))]
1516 "&& reload_completed"
1517 [(set (match_dup 2) (neg:SI (match_dup 1)))
1519 (compare:CC (match_dup 1)
1522 (if_then_else:SI (ge (match_dup 3)
1528 (define_insn_and_split "abssi2_nopower"
1529 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1530 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1531 (clobber (match_scratch:SI 2 "=&r,&r"))]
1532 "! TARGET_POWER && ! TARGET_ISEL"
1534 "&& reload_completed"
1535 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1536 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1537 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1540 (define_insn "*nabs_power"
1541 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1542 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1546 (define_insn_and_split "*nabs_nopower"
1547 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1548 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1549 (clobber (match_scratch:SI 2 "=&r,&r"))]
1552 "&& reload_completed"
1553 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1554 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1555 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1558 (define_insn "negsi2"
1559 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1560 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1566 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1568 (clobber (match_scratch:SI 2 "=r,r"))]
1573 [(set_attr "type" "fast_compare")
1574 (set_attr "length" "4,8")])
1577 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1578 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1580 (clobber (match_scratch:SI 2 ""))]
1581 "TARGET_32BIT && reload_completed"
1583 (neg:SI (match_dup 1)))
1585 (compare:CC (match_dup 2)
1590 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1591 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1594 (neg:SI (match_dup 1)))]
1599 [(set_attr "type" "fast_compare")
1600 (set_attr "length" "4,8")])
1603 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1604 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1606 (set (match_operand:SI 0 "gpc_reg_operand" "")
1607 (neg:SI (match_dup 1)))]
1608 "TARGET_32BIT && reload_completed"
1610 (neg:SI (match_dup 1)))
1612 (compare:CC (match_dup 0)
1616 (define_insn "clzsi2"
1617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1618 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1620 "{cntlz|cntlzw} %0,%1")
1622 (define_expand "ctzsi2"
1624 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1625 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1627 (clobber (scratch:CC))])
1628 (set (match_dup 4) (clz:SI (match_dup 3)))
1629 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1630 (minus:SI (const_int 31) (match_dup 4)))]
1633 operands[2] = gen_reg_rtx (SImode);
1634 operands[3] = gen_reg_rtx (SImode);
1635 operands[4] = gen_reg_rtx (SImode);
1638 (define_expand "ffssi2"
1640 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1641 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1643 (clobber (scratch:CC))])
1644 (set (match_dup 4) (clz:SI (match_dup 3)))
1645 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1646 (minus:SI (const_int 32) (match_dup 4)))]
1649 operands[2] = gen_reg_rtx (SImode);
1650 operands[3] = gen_reg_rtx (SImode);
1651 operands[4] = gen_reg_rtx (SImode);
1654 (define_expand "mulsi3"
1655 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1656 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1657 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1662 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1664 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1668 (define_insn "mulsi3_mq"
1669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1670 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1671 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1672 (clobber (match_scratch:SI 3 "=q,q"))]
1675 {muls|mullw} %0,%1,%2
1676 {muli|mulli} %0,%1,%2"
1678 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1679 (const_string "imul3")
1680 (match_operand:SI 2 "short_cint_operand" "")
1681 (const_string "imul2")]
1682 (const_string "imul")))])
1684 (define_insn "mulsi3_no_mq"
1685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1686 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1687 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1690 {muls|mullw} %0,%1,%2
1691 {muli|mulli} %0,%1,%2"
1693 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1694 (const_string "imul3")
1695 (match_operand:SI 2 "short_cint_operand" "")
1696 (const_string "imul2")]
1697 (const_string "imul")))])
1699 (define_insn "*mulsi3_mq_internal1"
1700 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1701 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1702 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1704 (clobber (match_scratch:SI 3 "=r,r"))
1705 (clobber (match_scratch:SI 4 "=q,q"))]
1708 {muls.|mullw.} %3,%1,%2
1710 [(set_attr "type" "imul_compare")
1711 (set_attr "length" "4,8")])
1714 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1715 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1716 (match_operand:SI 2 "gpc_reg_operand" ""))
1718 (clobber (match_scratch:SI 3 ""))
1719 (clobber (match_scratch:SI 4 ""))]
1720 "TARGET_POWER && reload_completed"
1721 [(parallel [(set (match_dup 3)
1722 (mult:SI (match_dup 1) (match_dup 2)))
1723 (clobber (match_dup 4))])
1725 (compare:CC (match_dup 3)
1729 (define_insn "*mulsi3_no_mq_internal1"
1730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1731 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1732 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1734 (clobber (match_scratch:SI 3 "=r,r"))]
1737 {muls.|mullw.} %3,%1,%2
1739 [(set_attr "type" "imul_compare")
1740 (set_attr "length" "4,8")])
1743 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1744 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1745 (match_operand:SI 2 "gpc_reg_operand" ""))
1747 (clobber (match_scratch:SI 3 ""))]
1748 "! TARGET_POWER && reload_completed"
1750 (mult:SI (match_dup 1) (match_dup 2)))
1752 (compare:CC (match_dup 3)
1756 (define_insn "*mulsi3_mq_internal2"
1757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1758 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1759 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1762 (mult:SI (match_dup 1) (match_dup 2)))
1763 (clobber (match_scratch:SI 4 "=q,q"))]
1766 {muls.|mullw.} %0,%1,%2
1768 [(set_attr "type" "imul_compare")
1769 (set_attr "length" "4,8")])
1772 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1773 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1774 (match_operand:SI 2 "gpc_reg_operand" ""))
1776 (set (match_operand:SI 0 "gpc_reg_operand" "")
1777 (mult:SI (match_dup 1) (match_dup 2)))
1778 (clobber (match_scratch:SI 4 ""))]
1779 "TARGET_POWER && reload_completed"
1780 [(parallel [(set (match_dup 0)
1781 (mult:SI (match_dup 1) (match_dup 2)))
1782 (clobber (match_dup 4))])
1784 (compare:CC (match_dup 0)
1788 (define_insn "*mulsi3_no_mq_internal2"
1789 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1790 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1791 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1794 (mult:SI (match_dup 1) (match_dup 2)))]
1797 {muls.|mullw.} %0,%1,%2
1799 [(set_attr "type" "imul_compare")
1800 (set_attr "length" "4,8")])
1803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1804 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1805 (match_operand:SI 2 "gpc_reg_operand" ""))
1807 (set (match_operand:SI 0 "gpc_reg_operand" "")
1808 (mult:SI (match_dup 1) (match_dup 2)))]
1809 "! TARGET_POWER && reload_completed"
1811 (mult:SI (match_dup 1) (match_dup 2)))
1813 (compare:CC (match_dup 0)
1817 ;; Operand 1 is divided by operand 2; quotient goes to operand
1818 ;; 0 and remainder to operand 3.
1819 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1821 (define_expand "divmodsi4"
1822 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1823 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1824 (match_operand:SI 2 "gpc_reg_operand" "")))
1825 (set (match_operand:SI 3 "register_operand" "")
1826 (mod:SI (match_dup 1) (match_dup 2)))])]
1827 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1830 if (! TARGET_POWER && ! TARGET_POWERPC)
1832 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1833 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1834 emit_insn (gen_divss_call ());
1835 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1836 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1841 (define_insn "*divmodsi4_internal"
1842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1843 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1844 (match_operand:SI 2 "gpc_reg_operand" "r")))
1845 (set (match_operand:SI 3 "register_operand" "=q")
1846 (mod:SI (match_dup 1) (match_dup 2)))]
1849 [(set_attr "type" "idiv")])
1851 (define_expand "udivsi3"
1852 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1853 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1854 (match_operand:SI 2 "gpc_reg_operand" "")))]
1855 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1858 if (! TARGET_POWER && ! TARGET_POWERPC)
1860 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1861 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1862 emit_insn (gen_quous_call ());
1863 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1866 else if (TARGET_POWER)
1868 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1873 (define_insn "udivsi3_mq"
1874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1875 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1876 (match_operand:SI 2 "gpc_reg_operand" "r")))
1877 (clobber (match_scratch:SI 3 "=q"))]
1878 "TARGET_POWERPC && TARGET_POWER"
1880 [(set_attr "type" "idiv")])
1882 (define_insn "*udivsi3_no_mq"
1883 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1884 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1885 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1886 "TARGET_POWERPC && ! TARGET_POWER"
1888 [(set_attr "type" "idiv")])
1890 ;; For powers of two we can do srai/aze for divide and then adjust for
1891 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1892 ;; used; for PowerPC, force operands into register and do a normal divide;
1893 ;; for AIX common-mode, use quoss call on register operands.
1894 (define_expand "divsi3"
1895 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1896 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1897 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1901 if (GET_CODE (operands[2]) == CONST_INT
1902 && INTVAL (operands[2]) > 0
1903 && exact_log2 (INTVAL (operands[2])) >= 0)
1905 else if (TARGET_POWERPC)
1907 operands[2] = force_reg (SImode, operands[2]);
1910 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1914 else if (TARGET_POWER)
1918 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1919 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1920 emit_insn (gen_quoss_call ());
1921 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1926 (define_insn "divsi3_mq"
1927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1928 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1929 (match_operand:SI 2 "gpc_reg_operand" "r")))
1930 (clobber (match_scratch:SI 3 "=q"))]
1931 "TARGET_POWERPC && TARGET_POWER"
1933 [(set_attr "type" "idiv")])
1935 (define_insn "*divsi3_no_mq"
1936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1937 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1938 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1939 "TARGET_POWERPC && ! TARGET_POWER"
1941 [(set_attr "type" "idiv")])
1943 (define_expand "modsi3"
1944 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1945 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1946 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1954 if (GET_CODE (operands[2]) != CONST_INT
1955 || INTVAL (operands[2]) <= 0
1956 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1959 temp1 = gen_reg_rtx (SImode);
1960 temp2 = gen_reg_rtx (SImode);
1962 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1963 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1964 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1970 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1971 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1973 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1974 [(set_attr "length" "8")])
1977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1978 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1979 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1981 (clobber (match_scratch:SI 3 "=r,r"))]
1984 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1986 [(set_attr "type" "compare")
1987 (set_attr "length" "8,12")])
1990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1991 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1992 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1994 (clobber (match_scratch:SI 3 ""))]
1997 (div:SI (match_dup 1) (match_dup 2)))
1999 (compare:CC (match_dup 3)
2004 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2005 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2006 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2008 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2009 (div:SI (match_dup 1) (match_dup 2)))]
2012 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2014 [(set_attr "type" "compare")
2015 (set_attr "length" "8,12")])
2018 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2019 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2020 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2022 (set (match_operand:SI 0 "gpc_reg_operand" "")
2023 (div:SI (match_dup 1) (match_dup 2)))]
2026 (div:SI (match_dup 1) (match_dup 2)))
2028 (compare:CC (match_dup 0)
2033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2036 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2038 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2039 (match_operand:SI 3 "gpc_reg_operand" "r")))
2040 (set (match_operand:SI 2 "register_operand" "=*q")
2043 (zero_extend:DI (match_dup 1)) (const_int 32))
2044 (zero_extend:DI (match_dup 4)))
2048 [(set_attr "type" "idiv")])
2050 ;; To do unsigned divide we handle the cases of the divisor looking like a
2051 ;; negative number. If it is a constant that is less than 2**31, we don't
2052 ;; have to worry about the branches. So make a few subroutines here.
2054 ;; First comes the normal case.
2055 (define_expand "udivmodsi4_normal"
2056 [(set (match_dup 4) (const_int 0))
2057 (parallel [(set (match_operand:SI 0 "" "")
2058 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2060 (zero_extend:DI (match_operand:SI 1 "" "")))
2061 (match_operand:SI 2 "" "")))
2062 (set (match_operand:SI 3 "" "")
2063 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2065 (zero_extend:DI (match_dup 1)))
2069 { operands[4] = gen_reg_rtx (SImode); }")
2071 ;; This handles the branches.
2072 (define_expand "udivmodsi4_tests"
2073 [(set (match_operand:SI 0 "" "") (const_int 0))
2074 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2075 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2076 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2077 (label_ref (match_operand:SI 4 "" "")) (pc)))
2078 (set (match_dup 0) (const_int 1))
2079 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2080 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2081 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2082 (label_ref (match_dup 4)) (pc)))]
2085 { operands[5] = gen_reg_rtx (CCUNSmode);
2086 operands[6] = gen_reg_rtx (CCmode);
2089 (define_expand "udivmodsi4"
2090 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2091 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2092 (match_operand:SI 2 "reg_or_cint_operand" "")))
2093 (set (match_operand:SI 3 "gpc_reg_operand" "")
2094 (umod:SI (match_dup 1) (match_dup 2)))])]
2102 if (! TARGET_POWERPC)
2104 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2105 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2106 emit_insn (gen_divus_call ());
2107 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2108 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2115 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2117 operands[2] = force_reg (SImode, operands[2]);
2118 label = gen_label_rtx ();
2119 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2120 operands[3], label));
2123 operands[2] = force_reg (SImode, operands[2]);
2125 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2133 ;; AIX architecture-independent common-mode multiply (DImode),
2134 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2135 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2136 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2137 ;; assumed unused if generating common-mode, so ignore.
2138 (define_insn "mulh_call"
2141 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2142 (sign_extend:DI (reg:SI 4)))
2144 (clobber (match_scratch:SI 0 "=l"))]
2145 "! TARGET_POWER && ! TARGET_POWERPC"
2147 [(set_attr "type" "imul")])
2149 (define_insn "mull_call"
2151 (mult:DI (sign_extend:DI (reg:SI 3))
2152 (sign_extend:DI (reg:SI 4))))
2153 (clobber (match_scratch:SI 0 "=l"))
2154 (clobber (reg:SI 0))]
2155 "! TARGET_POWER && ! TARGET_POWERPC"
2157 [(set_attr "type" "imul")])
2159 (define_insn "divss_call"
2161 (div:SI (reg:SI 3) (reg:SI 4)))
2163 (mod:SI (reg:SI 3) (reg:SI 4)))
2164 (clobber (match_scratch:SI 0 "=l"))
2165 (clobber (reg:SI 0))]
2166 "! TARGET_POWER && ! TARGET_POWERPC"
2168 [(set_attr "type" "idiv")])
2170 (define_insn "divus_call"
2172 (udiv:SI (reg:SI 3) (reg:SI 4)))
2174 (umod:SI (reg:SI 3) (reg:SI 4)))
2175 (clobber (match_scratch:SI 0 "=l"))
2176 (clobber (reg:SI 0))
2177 (clobber (match_scratch:CC 1 "=x"))
2178 (clobber (reg:CC 69))]
2179 "! TARGET_POWER && ! TARGET_POWERPC"
2181 [(set_attr "type" "idiv")])
2183 (define_insn "quoss_call"
2185 (div:SI (reg:SI 3) (reg:SI 4)))
2186 (clobber (match_scratch:SI 0 "=l"))]
2187 "! TARGET_POWER && ! TARGET_POWERPC"
2189 [(set_attr "type" "idiv")])
2191 (define_insn "quous_call"
2193 (udiv:SI (reg:SI 3) (reg:SI 4)))
2194 (clobber (match_scratch:SI 0 "=l"))
2195 (clobber (reg:SI 0))
2196 (clobber (match_scratch:CC 1 "=x"))
2197 (clobber (reg:CC 69))]
2198 "! TARGET_POWER && ! TARGET_POWERPC"
2200 [(set_attr "type" "idiv")])
2202 ;; Logical instructions
2203 ;; The logical instructions are mostly combined by using match_operator,
2204 ;; but the plain AND insns are somewhat different because there is no
2205 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2206 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2208 (define_insn "andsi3"
2209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2210 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2211 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2212 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2216 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2217 {andil.|andi.} %0,%1,%b2
2218 {andiu.|andis.} %0,%1,%u2")
2220 ;; Note to set cr's other than cr0 we do the and immediate and then
2221 ;; the test again -- this avoids a mfcr which on the higher end
2222 ;; machines causes an execution serialization
2224 (define_insn "*andsi3_internal2"
2225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2226 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2227 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2229 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2230 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2234 {andil.|andi.} %3,%1,%b2
2235 {andiu.|andis.} %3,%1,%u2
2236 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2241 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2242 (set_attr "length" "4,4,4,4,8,8,8,8")])
2244 (define_insn "*andsi3_internal3"
2245 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2246 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2247 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2249 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2250 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2254 {andil.|andi.} %3,%1,%b2
2255 {andiu.|andis.} %3,%1,%u2
2256 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2261 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2262 (set_attr "length" "8,4,4,4,8,8,8,8")])
2265 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2266 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2267 (match_operand:SI 2 "and_operand" ""))
2269 (clobber (match_scratch:SI 3 ""))
2270 (clobber (match_scratch:CC 4 ""))]
2272 [(parallel [(set (match_dup 3)
2273 (and:SI (match_dup 1)
2275 (clobber (match_dup 4))])
2277 (compare:CC (match_dup 3)
2281 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2282 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2285 [(set (match_operand:CC 0 "cc_reg_operand" "")
2286 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2287 (match_operand:SI 2 "gpc_reg_operand" ""))
2289 (clobber (match_scratch:SI 3 ""))
2290 (clobber (match_scratch:CC 4 ""))]
2291 "TARGET_POWERPC64 && reload_completed"
2292 [(parallel [(set (match_dup 3)
2293 (and:SI (match_dup 1)
2295 (clobber (match_dup 4))])
2297 (compare:CC (match_dup 3)
2301 (define_insn "*andsi3_internal4"
2302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2303 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2304 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2307 (and:SI (match_dup 1)
2309 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2313 {andil.|andi.} %0,%1,%b2
2314 {andiu.|andis.} %0,%1,%u2
2315 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2320 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2321 (set_attr "length" "4,4,4,4,8,8,8,8")])
2323 (define_insn "*andsi3_internal5"
2324 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2326 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2328 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2329 (and:SI (match_dup 1)
2331 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2335 {andil.|andi.} %0,%1,%b2
2336 {andiu.|andis.} %0,%1,%u2
2337 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2342 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2343 (set_attr "length" "8,4,4,4,8,8,8,8")])
2346 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2347 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2348 (match_operand:SI 2 "and_operand" ""))
2350 (set (match_operand:SI 0 "gpc_reg_operand" "")
2351 (and:SI (match_dup 1)
2353 (clobber (match_scratch:CC 4 ""))]
2355 [(parallel [(set (match_dup 0)
2356 (and:SI (match_dup 1)
2358 (clobber (match_dup 4))])
2360 (compare:CC (match_dup 0)
2365 [(set (match_operand:CC 3 "cc_reg_operand" "")
2366 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2367 (match_operand:SI 2 "gpc_reg_operand" ""))
2369 (set (match_operand:SI 0 "gpc_reg_operand" "")
2370 (and:SI (match_dup 1)
2372 (clobber (match_scratch:CC 4 ""))]
2373 "TARGET_POWERPC64 && reload_completed"
2374 [(parallel [(set (match_dup 0)
2375 (and:SI (match_dup 1)
2377 (clobber (match_dup 4))])
2379 (compare:CC (match_dup 0)
2383 ;; Handle the PowerPC64 rlwinm corner case
2385 (define_insn_and_split "*andsi3_internal6"
2386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2387 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2388 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2393 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2396 (rotate:SI (match_dup 0) (match_dup 5)))]
2399 int mb = extract_MB (operands[2]);
2400 int me = extract_ME (operands[2]);
2401 operands[3] = GEN_INT (me + 1);
2402 operands[5] = GEN_INT (32 - (me + 1));
2403 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2405 [(set_attr "length" "8")])
2407 (define_expand "iorsi3"
2408 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2409 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2410 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2414 if (GET_CODE (operands[2]) == CONST_INT
2415 && ! logical_operand (operands[2], SImode))
2417 HOST_WIDE_INT value = INTVAL (operands[2]);
2418 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2419 ? operands[0] : gen_reg_rtx (SImode));
2421 emit_insn (gen_iorsi3 (tmp, operands[1],
2422 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2423 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2428 (define_expand "xorsi3"
2429 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2430 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2431 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2435 if (GET_CODE (operands[2]) == CONST_INT
2436 && ! logical_operand (operands[2], SImode))
2438 HOST_WIDE_INT value = INTVAL (operands[2]);
2439 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2440 ? operands[0] : gen_reg_rtx (SImode));
2442 emit_insn (gen_xorsi3 (tmp, operands[1],
2443 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2444 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2449 (define_insn "*boolsi3_internal1"
2450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2451 (match_operator:SI 3 "boolean_or_operator"
2452 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2453 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2457 {%q3il|%q3i} %0,%1,%b2
2458 {%q3iu|%q3is} %0,%1,%u2")
2460 (define_insn "*boolsi3_internal2"
2461 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2462 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2463 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2464 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2466 (clobber (match_scratch:SI 3 "=r,r"))]
2471 [(set_attr "type" "compare")
2472 (set_attr "length" "4,8")])
2475 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2476 (compare:CC (match_operator:SI 4 "boolean_operator"
2477 [(match_operand:SI 1 "gpc_reg_operand" "")
2478 (match_operand:SI 2 "gpc_reg_operand" "")])
2480 (clobber (match_scratch:SI 3 ""))]
2481 "TARGET_32BIT && reload_completed"
2482 [(set (match_dup 3) (match_dup 4))
2484 (compare:CC (match_dup 3)
2488 (define_insn "*boolsi3_internal3"
2489 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2490 (compare:CC (match_operator:SI 4 "boolean_operator"
2491 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2492 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2494 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2500 [(set_attr "type" "compare")
2501 (set_attr "length" "4,8")])
2504 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2505 (compare:CC (match_operator:SI 4 "boolean_operator"
2506 [(match_operand:SI 1 "gpc_reg_operand" "")
2507 (match_operand:SI 2 "gpc_reg_operand" "")])
2509 (set (match_operand:SI 0 "gpc_reg_operand" "")
2511 "TARGET_32BIT && reload_completed"
2512 [(set (match_dup 0) (match_dup 4))
2514 (compare:CC (match_dup 0)
2518 ;; Split a logical operation that we can't do in one insn into two insns,
2519 ;; each of which does one 16-bit part. This is used by combine.
2522 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2523 (match_operator:SI 3 "boolean_or_operator"
2524 [(match_operand:SI 1 "gpc_reg_operand" "")
2525 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2527 [(set (match_dup 0) (match_dup 4))
2528 (set (match_dup 0) (match_dup 5))]
2532 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2533 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2535 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2536 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2540 (define_insn "*boolcsi3_internal1"
2541 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2542 (match_operator:SI 3 "boolean_operator"
2543 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2544 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2548 (define_insn "*boolcsi3_internal2"
2549 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2550 (compare:CC (match_operator:SI 4 "boolean_operator"
2551 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2552 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2554 (clobber (match_scratch:SI 3 "=r,r"))]
2559 [(set_attr "type" "compare")
2560 (set_attr "length" "4,8")])
2563 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2564 (compare:CC (match_operator:SI 4 "boolean_operator"
2565 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2566 (match_operand:SI 2 "gpc_reg_operand" "")])
2568 (clobber (match_scratch:SI 3 ""))]
2569 "TARGET_32BIT && reload_completed"
2570 [(set (match_dup 3) (match_dup 4))
2572 (compare:CC (match_dup 3)
2576 (define_insn "*boolcsi3_internal3"
2577 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2578 (compare:CC (match_operator:SI 4 "boolean_operator"
2579 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2580 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2582 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2588 [(set_attr "type" "compare")
2589 (set_attr "length" "4,8")])
2592 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2593 (compare:CC (match_operator:SI 4 "boolean_operator"
2594 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2595 (match_operand:SI 2 "gpc_reg_operand" "")])
2597 (set (match_operand:SI 0 "gpc_reg_operand" "")
2599 "TARGET_32BIT && reload_completed"
2600 [(set (match_dup 0) (match_dup 4))
2602 (compare:CC (match_dup 0)
2606 (define_insn "*boolccsi3_internal1"
2607 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2608 (match_operator:SI 3 "boolean_operator"
2609 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2610 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2614 (define_insn "*boolccsi3_internal2"
2615 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2616 (compare:CC (match_operator:SI 4 "boolean_operator"
2617 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2618 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2620 (clobber (match_scratch:SI 3 "=r,r"))]
2625 [(set_attr "type" "compare")
2626 (set_attr "length" "4,8")])
2629 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2630 (compare:CC (match_operator:SI 4 "boolean_operator"
2631 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2632 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2634 (clobber (match_scratch:SI 3 ""))]
2635 "TARGET_32BIT && reload_completed"
2636 [(set (match_dup 3) (match_dup 4))
2638 (compare:CC (match_dup 3)
2642 (define_insn "*boolccsi3_internal3"
2643 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2644 (compare:CC (match_operator:SI 4 "boolean_operator"
2645 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2646 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2648 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2654 [(set_attr "type" "compare")
2655 (set_attr "length" "4,8")])
2658 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2659 (compare:CC (match_operator:SI 4 "boolean_operator"
2660 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2661 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2663 (set (match_operand:SI 0 "gpc_reg_operand" "")
2665 "TARGET_32BIT && reload_completed"
2666 [(set (match_dup 0) (match_dup 4))
2668 (compare:CC (match_dup 0)
2672 ;; maskir insn. We need four forms because things might be in arbitrary
2673 ;; orders. Don't define forms that only set CR fields because these
2674 ;; would modify an input register.
2676 (define_insn "*maskir_internal1"
2677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2678 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2679 (match_operand:SI 1 "gpc_reg_operand" "0"))
2680 (and:SI (match_dup 2)
2681 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2685 (define_insn "*maskir_internal2"
2686 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2687 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2688 (match_operand:SI 1 "gpc_reg_operand" "0"))
2689 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2694 (define_insn "*maskir_internal3"
2695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2696 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2697 (match_operand:SI 3 "gpc_reg_operand" "r"))
2698 (and:SI (not:SI (match_dup 2))
2699 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2703 (define_insn "*maskir_internal4"
2704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2705 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2706 (match_operand:SI 2 "gpc_reg_operand" "r"))
2707 (and:SI (not:SI (match_dup 2))
2708 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2712 (define_insn "*maskir_internal5"
2713 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2715 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2716 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2717 (and:SI (match_dup 2)
2718 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2720 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2721 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2722 (and:SI (match_dup 2) (match_dup 3))))]
2727 [(set_attr "type" "compare")
2728 (set_attr "length" "4,8")])
2731 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2733 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2734 (match_operand:SI 1 "gpc_reg_operand" ""))
2735 (and:SI (match_dup 2)
2736 (match_operand:SI 3 "gpc_reg_operand" "")))
2738 (set (match_operand:SI 0 "gpc_reg_operand" "")
2739 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2740 (and:SI (match_dup 2) (match_dup 3))))]
2741 "TARGET_POWER && reload_completed"
2743 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2744 (and:SI (match_dup 2) (match_dup 3))))
2746 (compare:CC (match_dup 0)
2750 (define_insn "*maskir_internal6"
2751 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2753 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2754 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2755 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2758 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2759 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2760 (and:SI (match_dup 3) (match_dup 2))))]
2765 [(set_attr "type" "compare")
2766 (set_attr "length" "4,8")])
2769 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2771 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2772 (match_operand:SI 1 "gpc_reg_operand" ""))
2773 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2776 (set (match_operand:SI 0 "gpc_reg_operand" "")
2777 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2778 (and:SI (match_dup 3) (match_dup 2))))]
2779 "TARGET_POWER && reload_completed"
2781 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2782 (and:SI (match_dup 3) (match_dup 2))))
2784 (compare:CC (match_dup 0)
2788 (define_insn "*maskir_internal7"
2789 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2791 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2792 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2793 (and:SI (not:SI (match_dup 2))
2794 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2796 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2797 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2798 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2803 [(set_attr "type" "compare")
2804 (set_attr "length" "4,8")])
2807 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2809 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2810 (match_operand:SI 3 "gpc_reg_operand" ""))
2811 (and:SI (not:SI (match_dup 2))
2812 (match_operand:SI 1 "gpc_reg_operand" "")))
2814 (set (match_operand:SI 0 "gpc_reg_operand" "")
2815 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2816 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2817 "TARGET_POWER && reload_completed"
2819 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2820 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2822 (compare:CC (match_dup 0)
2826 (define_insn "*maskir_internal8"
2827 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2829 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2830 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2831 (and:SI (not:SI (match_dup 2))
2832 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2835 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2836 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2841 [(set_attr "type" "compare")
2842 (set_attr "length" "4,8")])
2845 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2847 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2848 (match_operand:SI 2 "gpc_reg_operand" ""))
2849 (and:SI (not:SI (match_dup 2))
2850 (match_operand:SI 1 "gpc_reg_operand" "")))
2852 (set (match_operand:SI 0 "gpc_reg_operand" "")
2853 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2854 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2855 "TARGET_POWER && reload_completed"
2857 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2858 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2860 (compare:CC (match_dup 0)
2864 ;; Rotate and shift insns, in all their variants. These support shifts,
2865 ;; field inserts and extracts, and various combinations thereof.
2866 (define_expand "insv"
2867 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2868 (match_operand:SI 1 "const_int_operand" "")
2869 (match_operand:SI 2 "const_int_operand" ""))
2870 (match_operand 3 "gpc_reg_operand" ""))]
2874 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2875 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2876 compiler if the address of the structure is taken later. */
2877 if (GET_CODE (operands[0]) == SUBREG
2878 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2881 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2882 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2884 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2888 (define_insn "insvsi"
2889 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2890 (match_operand:SI 1 "const_int_operand" "i")
2891 (match_operand:SI 2 "const_int_operand" "i"))
2892 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2896 int start = INTVAL (operands[2]) & 31;
2897 int size = INTVAL (operands[1]) & 31;
2899 operands[4] = GEN_INT (32 - start - size);
2900 operands[1] = GEN_INT (start + size - 1);
2901 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2903 [(set_attr "type" "insert_word")])
2905 (define_insn "*insvsi_internal1"
2906 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2907 (match_operand:SI 1 "const_int_operand" "i")
2908 (match_operand:SI 2 "const_int_operand" "i"))
2909 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2910 (match_operand:SI 4 "const_int_operand" "i")))]
2911 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2914 int shift = INTVAL (operands[4]) & 31;
2915 int start = INTVAL (operands[2]) & 31;
2916 int size = INTVAL (operands[1]) & 31;
2918 operands[4] = GEN_INT (shift - start - size);
2919 operands[1] = GEN_INT (start + size - 1);
2920 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2922 [(set_attr "type" "insert_word")])
2924 (define_insn "*insvsi_internal2"
2925 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2926 (match_operand:SI 1 "const_int_operand" "i")
2927 (match_operand:SI 2 "const_int_operand" "i"))
2928 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2929 (match_operand:SI 4 "const_int_operand" "i")))]
2930 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2933 int shift = INTVAL (operands[4]) & 31;
2934 int start = INTVAL (operands[2]) & 31;
2935 int size = INTVAL (operands[1]) & 31;
2937 operands[4] = GEN_INT (32 - shift - start - size);
2938 operands[1] = GEN_INT (start + size - 1);
2939 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2941 [(set_attr "type" "insert_word")])
2943 (define_insn "*insvsi_internal3"
2944 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2945 (match_operand:SI 1 "const_int_operand" "i")
2946 (match_operand:SI 2 "const_int_operand" "i"))
2947 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2948 (match_operand:SI 4 "const_int_operand" "i")))]
2949 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2952 int shift = INTVAL (operands[4]) & 31;
2953 int start = INTVAL (operands[2]) & 31;
2954 int size = INTVAL (operands[1]) & 31;
2956 operands[4] = GEN_INT (32 - shift - start - size);
2957 operands[1] = GEN_INT (start + size - 1);
2958 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2960 [(set_attr "type" "insert_word")])
2962 (define_insn "*insvsi_internal4"
2963 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2964 (match_operand:SI 1 "const_int_operand" "i")
2965 (match_operand:SI 2 "const_int_operand" "i"))
2966 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2967 (match_operand:SI 4 "const_int_operand" "i")
2968 (match_operand:SI 5 "const_int_operand" "i")))]
2969 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2972 int extract_start = INTVAL (operands[5]) & 31;
2973 int extract_size = INTVAL (operands[4]) & 31;
2974 int insert_start = INTVAL (operands[2]) & 31;
2975 int insert_size = INTVAL (operands[1]) & 31;
2977 /* Align extract field with insert field */
2978 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
2979 operands[1] = GEN_INT (insert_start + insert_size - 1);
2980 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
2982 [(set_attr "type" "insert_word")])
2984 (define_insn "insvdi"
2985 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
2986 (match_operand:SI 1 "const_int_operand" "i")
2987 (match_operand:SI 2 "const_int_operand" "i"))
2988 (match_operand:DI 3 "gpc_reg_operand" "r"))]
2992 int start = INTVAL (operands[2]) & 63;
2993 int size = INTVAL (operands[1]) & 63;
2995 operands[1] = GEN_INT (64 - start - size);
2996 return \"rldimi %0,%3,%H1,%H2\";
2999 (define_expand "extzv"
3000 [(set (match_operand 0 "gpc_reg_operand" "")
3001 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3002 (match_operand:SI 2 "const_int_operand" "")
3003 (match_operand:SI 3 "const_int_operand" "")))]
3007 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3008 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3009 compiler if the address of the structure is taken later. */
3010 if (GET_CODE (operands[0]) == SUBREG
3011 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3014 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3015 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3017 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3021 (define_insn "extzvsi"
3022 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3023 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3024 (match_operand:SI 2 "const_int_operand" "i")
3025 (match_operand:SI 3 "const_int_operand" "i")))]
3029 int start = INTVAL (operands[3]) & 31;
3030 int size = INTVAL (operands[2]) & 31;
3032 if (start + size >= 32)
3033 operands[3] = const0_rtx;
3035 operands[3] = GEN_INT (start + size);
3036 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3039 (define_insn "*extzvsi_internal1"
3040 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3041 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3042 (match_operand:SI 2 "const_int_operand" "i,i")
3043 (match_operand:SI 3 "const_int_operand" "i,i"))
3045 (clobber (match_scratch:SI 4 "=r,r"))]
3049 int start = INTVAL (operands[3]) & 31;
3050 int size = INTVAL (operands[2]) & 31;
3052 /* Force split for non-cc0 compare. */
3053 if (which_alternative == 1)
3056 /* If the bit-field being tested fits in the upper or lower half of a
3057 word, it is possible to use andiu. or andil. to test it. This is
3058 useful because the condition register set-use delay is smaller for
3059 andi[ul]. than for rlinm. This doesn't work when the starting bit
3060 position is 0 because the LT and GT bits may be set wrong. */
3062 if ((start > 0 && start + size <= 16) || start >= 16)
3064 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3065 - (1 << (16 - (start & 15) - size))));
3067 return \"{andiu.|andis.} %4,%1,%3\";
3069 return \"{andil.|andi.} %4,%1,%3\";
3072 if (start + size >= 32)
3073 operands[3] = const0_rtx;
3075 operands[3] = GEN_INT (start + size);
3076 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3078 [(set_attr "type" "compare")
3079 (set_attr "length" "4,8")])
3082 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3083 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3084 (match_operand:SI 2 "const_int_operand" "")
3085 (match_operand:SI 3 "const_int_operand" ""))
3087 (clobber (match_scratch:SI 4 ""))]
3090 (zero_extract:SI (match_dup 1) (match_dup 2)
3093 (compare:CC (match_dup 4)
3097 (define_insn "*extzvsi_internal2"
3098 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3099 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3100 (match_operand:SI 2 "const_int_operand" "i,i")
3101 (match_operand:SI 3 "const_int_operand" "i,i"))
3103 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3104 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3108 int start = INTVAL (operands[3]) & 31;
3109 int size = INTVAL (operands[2]) & 31;
3111 /* Force split for non-cc0 compare. */
3112 if (which_alternative == 1)
3115 /* Since we are using the output value, we can't ignore any need for
3116 a shift. The bit-field must end at the LSB. */
3117 if (start >= 16 && start + size == 32)
3119 operands[3] = GEN_INT ((1 << size) - 1);
3120 return \"{andil.|andi.} %0,%1,%3\";
3123 if (start + size >= 32)
3124 operands[3] = const0_rtx;
3126 operands[3] = GEN_INT (start + size);
3127 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3129 [(set_attr "type" "compare")
3130 (set_attr "length" "4,8")])
3133 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3134 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3135 (match_operand:SI 2 "const_int_operand" "")
3136 (match_operand:SI 3 "const_int_operand" ""))
3138 (set (match_operand:SI 0 "gpc_reg_operand" "")
3139 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3142 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3144 (compare:CC (match_dup 0)
3148 (define_insn "extzvdi"
3149 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3150 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3151 (match_operand:SI 2 "const_int_operand" "i")
3152 (match_operand:SI 3 "const_int_operand" "i")))]
3156 int start = INTVAL (operands[3]) & 63;
3157 int size = INTVAL (operands[2]) & 63;
3159 if (start + size >= 64)
3160 operands[3] = const0_rtx;
3162 operands[3] = GEN_INT (start + size);
3163 operands[2] = GEN_INT (64 - size);
3164 return \"rldicl %0,%1,%3,%2\";
3167 (define_insn "*extzvdi_internal1"
3168 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3169 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3170 (match_operand:SI 2 "const_int_operand" "i")
3171 (match_operand:SI 3 "const_int_operand" "i"))
3173 (clobber (match_scratch:DI 4 "=r"))]
3177 int start = INTVAL (operands[3]) & 63;
3178 int size = INTVAL (operands[2]) & 63;
3180 if (start + size >= 64)
3181 operands[3] = const0_rtx;
3183 operands[3] = GEN_INT (start + size);
3184 operands[2] = GEN_INT (64 - size);
3185 return \"rldicl. %4,%1,%3,%2\";
3188 (define_insn "*extzvdi_internal2"
3189 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3190 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3191 (match_operand:SI 2 "const_int_operand" "i")
3192 (match_operand:SI 3 "const_int_operand" "i"))
3194 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3195 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3199 int start = INTVAL (operands[3]) & 63;
3200 int size = INTVAL (operands[2]) & 63;
3202 if (start + size >= 64)
3203 operands[3] = const0_rtx;
3205 operands[3] = GEN_INT (start + size);
3206 operands[2] = GEN_INT (64 - size);
3207 return \"rldicl. %0,%1,%3,%2\";
3210 (define_insn "rotlsi3"
3211 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3212 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3213 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3215 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3217 (define_insn "*rotlsi3_internal2"
3218 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3219 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3220 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3222 (clobber (match_scratch:SI 3 "=r,r"))]
3225 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3227 [(set_attr "type" "delayed_compare")
3228 (set_attr "length" "4,8")])
3231 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3232 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3233 (match_operand:SI 2 "reg_or_cint_operand" ""))
3235 (clobber (match_scratch:SI 3 ""))]
3238 (rotate:SI (match_dup 1) (match_dup 2)))
3240 (compare:CC (match_dup 3)
3244 (define_insn "*rotlsi3_internal3"
3245 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3246 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3247 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3249 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3250 (rotate:SI (match_dup 1) (match_dup 2)))]
3253 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3255 [(set_attr "type" "delayed_compare")
3256 (set_attr "length" "4,8")])
3259 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3260 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3261 (match_operand:SI 2 "reg_or_cint_operand" ""))
3263 (set (match_operand:SI 0 "gpc_reg_operand" "")
3264 (rotate:SI (match_dup 1) (match_dup 2)))]
3267 (rotate:SI (match_dup 1) (match_dup 2)))
3269 (compare:CC (match_dup 0)
3273 (define_insn "*rotlsi3_internal4"
3274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3275 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3276 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3277 (match_operand:SI 3 "mask_operand" "n")))]
3279 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3281 (define_insn "*rotlsi3_internal5"
3282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3284 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3285 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3286 (match_operand:SI 3 "mask_operand" "n,n"))
3288 (clobber (match_scratch:SI 4 "=r,r"))]
3291 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3293 [(set_attr "type" "delayed_compare")
3294 (set_attr "length" "4,8")])
3297 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3299 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3300 (match_operand:SI 2 "reg_or_cint_operand" ""))
3301 (match_operand:SI 3 "mask_operand" ""))
3303 (clobber (match_scratch:SI 4 ""))]
3306 (and:SI (rotate:SI (match_dup 1)
3310 (compare:CC (match_dup 4)
3314 (define_insn "*rotlsi3_internal6"
3315 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3317 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3318 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3319 (match_operand:SI 3 "mask_operand" "n,n"))
3321 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3322 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3325 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3327 [(set_attr "type" "delayed_compare")
3328 (set_attr "length" "4,8")])
3331 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3333 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3334 (match_operand:SI 2 "reg_or_cint_operand" ""))
3335 (match_operand:SI 3 "mask_operand" ""))
3337 (set (match_operand:SI 0 "gpc_reg_operand" "")
3338 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3341 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3343 (compare:CC (match_dup 0)
3347 (define_insn "*rotlsi3_internal7"
3348 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3351 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3352 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3354 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3356 (define_insn "*rotlsi3_internal8"
3357 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3358 (compare:CC (zero_extend:SI
3360 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3361 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3363 (clobber (match_scratch:SI 3 "=r,r"))]
3366 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3368 [(set_attr "type" "delayed_compare")
3369 (set_attr "length" "4,8")])
3372 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3373 (compare:CC (zero_extend:SI
3375 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3376 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3378 (clobber (match_scratch:SI 3 ""))]
3381 (zero_extend:SI (subreg:QI
3382 (rotate:SI (match_dup 1)
3385 (compare:CC (match_dup 3)
3389 (define_insn "*rotlsi3_internal9"
3390 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3391 (compare:CC (zero_extend:SI
3393 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3394 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3396 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3397 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3400 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3402 [(set_attr "type" "delayed_compare")
3403 (set_attr "length" "4,8")])
3406 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3407 (compare:CC (zero_extend:SI
3409 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3410 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3412 (set (match_operand:SI 0 "gpc_reg_operand" "")
3413 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3416 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3418 (compare:CC (match_dup 0)
3422 (define_insn "*rotlsi3_internal10"
3423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3426 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3427 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3429 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3431 (define_insn "*rotlsi3_internal11"
3432 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3433 (compare:CC (zero_extend:SI
3435 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3436 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3438 (clobber (match_scratch:SI 3 "=r,r"))]
3441 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3443 [(set_attr "type" "delayed_compare")
3444 (set_attr "length" "4,8")])
3447 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3448 (compare:CC (zero_extend:SI
3450 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3451 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3453 (clobber (match_scratch:SI 3 ""))]
3456 (zero_extend:SI (subreg:HI
3457 (rotate:SI (match_dup 1)
3460 (compare:CC (match_dup 3)
3464 (define_insn "*rotlsi3_internal12"
3465 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3466 (compare:CC (zero_extend:SI
3468 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3469 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3471 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3472 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3475 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3477 [(set_attr "type" "delayed_compare")
3478 (set_attr "length" "4,8")])
3481 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3482 (compare:CC (zero_extend:SI
3484 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3485 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3487 (set (match_operand:SI 0 "gpc_reg_operand" "")
3488 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3491 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3493 (compare:CC (match_dup 0)
3497 ;; Note that we use "sle." instead of "sl." so that we can set
3498 ;; SHIFT_COUNT_TRUNCATED.
3500 (define_expand "ashlsi3"
3501 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3502 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3503 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3508 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3510 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3514 (define_insn "ashlsi3_power"
3515 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3516 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3517 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3518 (clobber (match_scratch:SI 3 "=q,X"))]
3522 {sli|slwi} %0,%1,%h2")
3524 (define_insn "ashlsi3_no_power"
3525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3526 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3527 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3529 "{sl|slw}%I2 %0,%1,%h2")
3532 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3533 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3534 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3536 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3537 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3541 {sli.|slwi.} %3,%1,%h2
3544 [(set_attr "type" "delayed_compare")
3545 (set_attr "length" "4,4,8,8")])
3548 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3549 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3550 (match_operand:SI 2 "reg_or_cint_operand" ""))
3552 (clobber (match_scratch:SI 3 ""))
3553 (clobber (match_scratch:SI 4 ""))]
3554 "TARGET_POWER && reload_completed"
3555 [(parallel [(set (match_dup 3)
3556 (ashift:SI (match_dup 1) (match_dup 2)))
3557 (clobber (match_dup 4))])
3559 (compare:CC (match_dup 3)
3564 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3565 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3566 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3568 (clobber (match_scratch:SI 3 "=r,r"))]
3569 "! TARGET_POWER && TARGET_32BIT"
3571 {sl|slw}%I2. %3,%1,%h2
3573 [(set_attr "type" "delayed_compare")
3574 (set_attr "length" "4,8")])
3577 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3578 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3579 (match_operand:SI 2 "reg_or_cint_operand" ""))
3581 (clobber (match_scratch:SI 3 ""))]
3582 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3584 (ashift:SI (match_dup 1) (match_dup 2)))
3586 (compare:CC (match_dup 3)
3591 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3592 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3593 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3596 (ashift:SI (match_dup 1) (match_dup 2)))
3597 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3601 {sli.|slwi.} %0,%1,%h2
3604 [(set_attr "type" "delayed_compare")
3605 (set_attr "length" "4,4,8,8")])
3608 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3609 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3610 (match_operand:SI 2 "reg_or_cint_operand" ""))
3612 (set (match_operand:SI 0 "gpc_reg_operand" "")
3613 (ashift:SI (match_dup 1) (match_dup 2)))
3614 (clobber (match_scratch:SI 4 ""))]
3615 "TARGET_POWER && reload_completed"
3616 [(parallel [(set (match_dup 0)
3617 (ashift:SI (match_dup 1) (match_dup 2)))
3618 (clobber (match_dup 4))])
3620 (compare:CC (match_dup 0)
3625 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3626 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3627 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3629 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3630 (ashift:SI (match_dup 1) (match_dup 2)))]
3631 "! TARGET_POWER && TARGET_32BIT"
3633 {sl|slw}%I2. %0,%1,%h2
3635 [(set_attr "type" "delayed_compare")
3636 (set_attr "length" "4,8")])
3639 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3640 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3641 (match_operand:SI 2 "reg_or_cint_operand" ""))
3643 (set (match_operand:SI 0 "gpc_reg_operand" "")
3644 (ashift:SI (match_dup 1) (match_dup 2)))]
3645 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3647 (ashift:SI (match_dup 1) (match_dup 2)))
3649 (compare:CC (match_dup 0)
3654 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3655 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3656 (match_operand:SI 2 "const_int_operand" "i"))
3657 (match_operand:SI 3 "mask_operand" "n")))]
3658 "includes_lshift_p (operands[2], operands[3])"
3659 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3662 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3664 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3665 (match_operand:SI 2 "const_int_operand" "i,i"))
3666 (match_operand:SI 3 "mask_operand" "n,n"))
3668 (clobber (match_scratch:SI 4 "=r,r"))]
3669 "includes_lshift_p (operands[2], operands[3])"
3671 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3673 [(set_attr "type" "delayed_compare")
3674 (set_attr "length" "4,8")])
3677 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3679 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3680 (match_operand:SI 2 "const_int_operand" ""))
3681 (match_operand:SI 3 "mask_operand" ""))
3683 (clobber (match_scratch:SI 4 ""))]
3684 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3686 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3689 (compare:CC (match_dup 4)
3694 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3696 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3697 (match_operand:SI 2 "const_int_operand" "i,i"))
3698 (match_operand:SI 3 "mask_operand" "n,n"))
3700 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3701 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3702 "includes_lshift_p (operands[2], operands[3])"
3704 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3706 [(set_attr "type" "delayed_compare")
3707 (set_attr "length" "4,8")])
3710 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3712 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3713 (match_operand:SI 2 "const_int_operand" ""))
3714 (match_operand:SI 3 "mask_operand" ""))
3716 (set (match_operand:SI 0 "gpc_reg_operand" "")
3717 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3718 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3720 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3722 (compare:CC (match_dup 0)
3726 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3728 (define_expand "lshrsi3"
3729 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3730 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3731 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3736 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3738 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3742 (define_insn "lshrsi3_power"
3743 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3744 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3745 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3746 (clobber (match_scratch:SI 3 "=q,X,X"))]
3751 {s%A2i|s%A2wi} %0,%1,%h2")
3753 (define_insn "lshrsi3_no_power"
3754 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3755 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3756 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3760 {sr|srw}%I2 %0,%1,%h2")
3763 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3764 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3765 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3767 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3768 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3773 {s%A2i.|s%A2wi.} %3,%1,%h2
3777 [(set_attr "type" "delayed_compare")
3778 (set_attr "length" "4,4,4,8,8,8")])
3781 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3782 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3783 (match_operand:SI 2 "reg_or_cint_operand" ""))
3785 (clobber (match_scratch:SI 3 ""))
3786 (clobber (match_scratch:SI 4 ""))]
3787 "TARGET_POWER && reload_completed"
3788 [(parallel [(set (match_dup 3)
3789 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3790 (clobber (match_dup 4))])
3792 (compare:CC (match_dup 3)
3797 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3798 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3799 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3801 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3802 "! TARGET_POWER && TARGET_32BIT"
3805 {sr|srw}%I2. %3,%1,%h2
3808 [(set_attr "type" "delayed_compare")
3809 (set_attr "length" "4,4,8,8")])
3812 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3813 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3814 (match_operand:SI 2 "reg_or_cint_operand" ""))
3816 (clobber (match_scratch:SI 3 ""))]
3817 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3819 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3821 (compare:CC (match_dup 3)
3826 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3827 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3828 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3830 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3831 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3832 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3837 {s%A2i.|s%A2wi.} %0,%1,%h2
3841 [(set_attr "type" "delayed_compare")
3842 (set_attr "length" "4,4,4,8,8,8")])
3845 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3846 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3847 (match_operand:SI 2 "reg_or_cint_operand" ""))
3849 (set (match_operand:SI 0 "gpc_reg_operand" "")
3850 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3851 (clobber (match_scratch:SI 4 ""))]
3852 "TARGET_POWER && reload_completed"
3853 [(parallel [(set (match_dup 0)
3854 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3855 (clobber (match_dup 4))])
3857 (compare:CC (match_dup 0)
3862 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3863 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3864 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3866 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3867 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3868 "! TARGET_POWER && TARGET_32BIT"
3871 {sr|srw}%I2. %0,%1,%h2
3874 [(set_attr "type" "delayed_compare")
3875 (set_attr "length" "4,4,8,8")])
3878 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3879 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3880 (match_operand:SI 2 "reg_or_cint_operand" ""))
3882 (set (match_operand:SI 0 "gpc_reg_operand" "")
3883 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3884 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3886 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3888 (compare:CC (match_dup 0)
3893 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3894 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3895 (match_operand:SI 2 "const_int_operand" "i"))
3896 (match_operand:SI 3 "mask_operand" "n")))]
3897 "includes_rshift_p (operands[2], operands[3])"
3898 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3903 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3904 (match_operand:SI 2 "const_int_operand" "i,i"))
3905 (match_operand:SI 3 "mask_operand" "n,n"))
3907 (clobber (match_scratch:SI 4 "=r,r"))]
3908 "includes_rshift_p (operands[2], operands[3])"
3910 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3912 [(set_attr "type" "delayed_compare")
3913 (set_attr "length" "4,8")])
3916 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3918 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3919 (match_operand:SI 2 "const_int_operand" ""))
3920 (match_operand:SI 3 "mask_operand" ""))
3922 (clobber (match_scratch:SI 4 ""))]
3923 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3925 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3928 (compare:CC (match_dup 4)
3933 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3935 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3936 (match_operand:SI 2 "const_int_operand" "i,i"))
3937 (match_operand:SI 3 "mask_operand" "n,n"))
3939 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3940 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3941 "includes_rshift_p (operands[2], operands[3])"
3943 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
3945 [(set_attr "type" "delayed_compare")
3946 (set_attr "length" "4,8")])
3949 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3951 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3952 (match_operand:SI 2 "const_int_operand" ""))
3953 (match_operand:SI 3 "mask_operand" ""))
3955 (set (match_operand:SI 0 "gpc_reg_operand" "")
3956 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3957 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3959 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3961 (compare:CC (match_dup 0)
3966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3969 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3970 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
3971 "includes_rshift_p (operands[2], GEN_INT (255))"
3972 "{rlinm|rlwinm} %0,%1,%s2,0xff")
3975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3979 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3980 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
3982 (clobber (match_scratch:SI 3 "=r,r"))]
3983 "includes_rshift_p (operands[2], GEN_INT (255))"
3985 {rlinm.|rlwinm.} %3,%1,%s2,0xff
3987 [(set_attr "type" "delayed_compare")
3988 (set_attr "length" "4,8")])
3991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3995 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3996 (match_operand:SI 2 "const_int_operand" "")) 0))
3998 (clobber (match_scratch:SI 3 ""))]
3999 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4001 (zero_extend:SI (subreg:QI
4002 (lshiftrt:SI (match_dup 1)
4005 (compare:CC (match_dup 3)
4010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4014 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4015 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4018 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4019 "includes_rshift_p (operands[2], GEN_INT (255))"
4021 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4023 [(set_attr "type" "delayed_compare")
4024 (set_attr "length" "4,8")])
4027 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4031 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4032 (match_operand:SI 2 "const_int_operand" "")) 0))
4034 (set (match_operand:SI 0 "gpc_reg_operand" "")
4035 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4036 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4038 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4040 (compare:CC (match_dup 0)
4045 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4048 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4049 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4050 "includes_rshift_p (operands[2], GEN_INT (65535))"
4051 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4054 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4058 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4059 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4061 (clobber (match_scratch:SI 3 "=r,r"))]
4062 "includes_rshift_p (operands[2], GEN_INT (65535))"
4064 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4066 [(set_attr "type" "delayed_compare")
4067 (set_attr "length" "4,8")])
4070 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4074 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4075 (match_operand:SI 2 "const_int_operand" "")) 0))
4077 (clobber (match_scratch:SI 3 ""))]
4078 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4080 (zero_extend:SI (subreg:HI
4081 (lshiftrt:SI (match_dup 1)
4084 (compare:CC (match_dup 3)
4089 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4093 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4094 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4096 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4097 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4098 "includes_rshift_p (operands[2], GEN_INT (65535))"
4100 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4102 [(set_attr "type" "delayed_compare")
4103 (set_attr "length" "4,8")])
4106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4110 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4111 (match_operand:SI 2 "const_int_operand" "")) 0))
4113 (set (match_operand:SI 0 "gpc_reg_operand" "")
4114 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4115 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4117 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4119 (compare:CC (match_dup 0)
4124 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4126 (match_operand:SI 1 "gpc_reg_operand" "r"))
4127 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4133 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4135 (match_operand:SI 1 "gpc_reg_operand" "r"))
4136 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4142 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4144 (match_operand:SI 1 "gpc_reg_operand" "r"))
4145 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4151 (define_expand "ashrsi3"
4152 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4153 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4154 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4159 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4161 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4165 (define_insn "ashrsi3_power"
4166 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4167 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4168 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4169 (clobber (match_scratch:SI 3 "=q,X"))]
4173 {srai|srawi} %0,%1,%h2")
4175 (define_insn "ashrsi3_no_power"
4176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4177 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4178 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4180 "{sra|sraw}%I2 %0,%1,%h2")
4183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4184 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4185 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4187 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4188 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4192 {srai.|srawi.} %3,%1,%h2
4195 [(set_attr "type" "delayed_compare")
4196 (set_attr "length" "4,4,8,8")])
4199 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4200 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4201 (match_operand:SI 2 "reg_or_cint_operand" ""))
4203 (clobber (match_scratch:SI 3 ""))
4204 (clobber (match_scratch:SI 4 ""))]
4205 "TARGET_POWER && reload_completed"
4206 [(parallel [(set (match_dup 3)
4207 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4208 (clobber (match_dup 4))])
4210 (compare:CC (match_dup 3)
4215 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4216 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4217 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4219 (clobber (match_scratch:SI 3 "=r,r"))]
4222 {sra|sraw}%I2. %3,%1,%h2
4224 [(set_attr "type" "delayed_compare")
4225 (set_attr "length" "4,8")])
4228 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4229 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4230 (match_operand:SI 2 "reg_or_cint_operand" ""))
4232 (clobber (match_scratch:SI 3 ""))]
4233 "! TARGET_POWER && reload_completed"
4235 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4237 (compare:CC (match_dup 3)
4242 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4243 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4244 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4246 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4247 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4248 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4252 {srai.|srawi.} %0,%1,%h2
4255 [(set_attr "type" "delayed_compare")
4256 (set_attr "length" "4,4,8,8")])
4259 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4260 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4261 (match_operand:SI 2 "reg_or_cint_operand" ""))
4263 (set (match_operand:SI 0 "gpc_reg_operand" "")
4264 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4265 (clobber (match_scratch:SI 4 ""))]
4266 "TARGET_POWER && reload_completed"
4267 [(parallel [(set (match_dup 0)
4268 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4269 (clobber (match_dup 4))])
4271 (compare:CC (match_dup 0)
4276 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4277 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4278 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4280 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4281 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4284 {sra|sraw}%I2. %0,%1,%h2
4286 [(set_attr "type" "delayed_compare")
4287 (set_attr "length" "4,8")])
4290 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4291 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4292 (match_operand:SI 2 "reg_or_cint_operand" ""))
4294 (set (match_operand:SI 0 "gpc_reg_operand" "")
4295 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4296 "! TARGET_POWER && reload_completed"
4298 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4300 (compare:CC (match_dup 0)
4304 ;; Floating-point insns, excluding normal data motion.
4306 ;; PowerPC has a full set of single-precision floating point instructions.
4308 ;; For the POWER architecture, we pretend that we have both SFmode and
4309 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4310 ;; The only conversions we will do will be when storing to memory. In that
4311 ;; case, we will use the "frsp" instruction before storing.
4313 ;; Note that when we store into a single-precision memory location, we need to
4314 ;; use the frsp insn first. If the register being stored isn't dead, we
4315 ;; need a scratch register for the frsp. But this is difficult when the store
4316 ;; is done by reload. It is not incorrect to do the frsp on the register in
4317 ;; this case, we just lose precision that we would have otherwise gotten but
4318 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4320 (define_insn "extendsfdf2"
4321 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4322 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4323 "TARGET_HARD_FLOAT && TARGET_FPRS"
4326 if (REGNO (operands[0]) == REGNO (operands[1]))
4329 return \"fmr %0,%1\";
4331 [(set_attr "type" "fp")])
4333 (define_insn "truncdfsf2"
4334 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4335 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4336 "TARGET_HARD_FLOAT && TARGET_FPRS"
4338 [(set_attr "type" "fp")])
4340 (define_insn "aux_truncdfsf2"
4341 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4342 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4343 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4345 [(set_attr "type" "fp")])
4347 (define_expand "negsf2"
4348 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4349 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4353 (define_insn "*negsf2"
4354 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4355 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4356 "TARGET_HARD_FLOAT && TARGET_FPRS"
4358 [(set_attr "type" "fp")])
4360 (define_expand "abssf2"
4361 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4362 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4366 (define_insn "*abssf2"
4367 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4368 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4369 "TARGET_HARD_FLOAT && TARGET_FPRS"
4371 [(set_attr "type" "fp")])
4374 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4375 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4376 "TARGET_HARD_FLOAT && TARGET_FPRS"
4378 [(set_attr "type" "fp")])
4380 (define_expand "addsf3"
4381 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4382 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4383 (match_operand:SF 2 "gpc_reg_operand" "")))]
4388 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4389 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4390 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4391 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4393 [(set_attr "type" "fp")])
4396 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4397 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4398 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4399 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4400 "{fa|fadd} %0,%1,%2"
4401 [(set_attr "type" "fp")])
4403 (define_expand "subsf3"
4404 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4405 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4406 (match_operand:SF 2 "gpc_reg_operand" "")))]
4411 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4412 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4413 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4414 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4416 [(set_attr "type" "fp")])
4419 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4420 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4421 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4422 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4423 "{fs|fsub} %0,%1,%2"
4424 [(set_attr "type" "fp")])
4426 (define_expand "mulsf3"
4427 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4428 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4429 (match_operand:SF 2 "gpc_reg_operand" "")))]
4434 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4435 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4436 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4437 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4439 [(set_attr "type" "fp")])
4442 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4443 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4444 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4445 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4446 "{fm|fmul} %0,%1,%2"
4447 [(set_attr "type" "dmul")])
4449 (define_expand "divsf3"
4450 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4451 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4452 (match_operand:SF 2 "gpc_reg_operand" "")))]
4457 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4458 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4459 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4460 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4462 [(set_attr "type" "sdiv")])
4465 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4466 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4467 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4468 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4469 "{fd|fdiv} %0,%1,%2"
4470 [(set_attr "type" "ddiv")])
4473 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4474 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4475 (match_operand:SF 2 "gpc_reg_operand" "f"))
4476 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4477 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4478 "fmadds %0,%1,%2,%3"
4479 [(set_attr "type" "fp")])
4482 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4483 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4484 (match_operand:SF 2 "gpc_reg_operand" "f"))
4485 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4486 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4487 "{fma|fmadd} %0,%1,%2,%3"
4488 [(set_attr "type" "dmul")])
4491 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4492 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4493 (match_operand:SF 2 "gpc_reg_operand" "f"))
4494 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4495 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4496 "fmsubs %0,%1,%2,%3"
4497 [(set_attr "type" "fp")])
4500 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4501 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4502 (match_operand:SF 2 "gpc_reg_operand" "f"))
4503 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4504 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4505 "{fms|fmsub} %0,%1,%2,%3"
4506 [(set_attr "type" "dmul")])
4509 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4510 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4511 (match_operand:SF 2 "gpc_reg_operand" "f"))
4512 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4513 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4514 && HONOR_SIGNED_ZEROS (SFmode)"
4515 "fnmadds %0,%1,%2,%3"
4516 [(set_attr "type" "fp")])
4519 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4520 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4521 (match_operand:SF 2 "gpc_reg_operand" "f"))
4522 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4523 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4524 && ! HONOR_SIGNED_ZEROS (SFmode)"
4525 "fnmadds %0,%1,%2,%3"
4526 [(set_attr "type" "fp")])
4529 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4530 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4531 (match_operand:SF 2 "gpc_reg_operand" "f"))
4532 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4533 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4534 "{fnma|fnmadd} %0,%1,%2,%3"
4535 [(set_attr "type" "dmul")])
4538 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4539 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4540 (match_operand:SF 2 "gpc_reg_operand" "f"))
4541 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4542 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4543 && ! HONOR_SIGNED_ZEROS (SFmode)"
4544 "{fnma|fnmadd} %0,%1,%2,%3"
4545 [(set_attr "type" "dmul")])
4548 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4549 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4550 (match_operand:SF 2 "gpc_reg_operand" "f"))
4551 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4552 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4553 && HONOR_SIGNED_ZEROS (SFmode)"
4554 "fnmsubs %0,%1,%2,%3"
4555 [(set_attr "type" "fp")])
4558 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4559 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4560 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4561 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4562 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4563 && ! HONOR_SIGNED_ZEROS (SFmode)"
4564 "fnmsubs %0,%1,%2,%3"
4565 [(set_attr "type" "fp")])
4568 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4569 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4570 (match_operand:SF 2 "gpc_reg_operand" "f"))
4571 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4572 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4573 "{fnms|fnmsub} %0,%1,%2,%3"
4574 [(set_attr "type" "dmul")])
4577 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4578 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4579 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4580 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4581 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4582 && ! HONOR_SIGNED_ZEROS (SFmode)"
4583 "{fnms|fnmsub} %0,%1,%2,%3"
4584 [(set_attr "type" "fp")])
4586 (define_expand "sqrtsf2"
4587 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4588 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4589 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4593 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4594 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4595 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4597 [(set_attr "type" "ssqrt")])
4600 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4601 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4602 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4604 [(set_attr "type" "dsqrt")])
4606 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4607 ;; fsel instruction and some auxiliary computations. Then we just have a
4608 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4610 (define_expand "maxsf3"
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4612 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4613 (match_operand:SF 2 "gpc_reg_operand" ""))
4616 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4617 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4619 (define_expand "minsf3"
4620 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4621 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4622 (match_operand:SF 2 "gpc_reg_operand" ""))
4625 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4626 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4629 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4630 (match_operator:SF 3 "min_max_operator"
4631 [(match_operand:SF 1 "gpc_reg_operand" "")
4632 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4633 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4636 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4637 operands[1], operands[2]);
4641 (define_expand "movsicc"
4642 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4643 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4644 (match_operand:SI 2 "gpc_reg_operand" "")
4645 (match_operand:SI 3 "gpc_reg_operand" "")))]
4649 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4655 ;; We use the BASE_REGS for the isel input operands because, if rA is
4656 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4657 ;; because we may switch the operands and rB may end up being rA.
4659 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4660 ;; leave out the mode in operand 4 and use one pattern, but reload can
4661 ;; change the mode underneath our feet and then gets confused trying
4662 ;; to reload the value.
4663 (define_insn "isel_signed"
4664 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4666 (match_operator 1 "comparison_operator"
4667 [(match_operand:CC 4 "cc_reg_operand" "y")
4669 (match_operand:SI 2 "gpc_reg_operand" "b")
4670 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4673 { return output_isel (operands); }"
4674 [(set_attr "length" "4")])
4676 (define_insn "isel_unsigned"
4677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4679 (match_operator 1 "comparison_operator"
4680 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4682 (match_operand:SI 2 "gpc_reg_operand" "b")
4683 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4686 { return output_isel (operands); }"
4687 [(set_attr "length" "4")])
4689 (define_expand "movsfcc"
4690 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4691 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4692 (match_operand:SF 2 "gpc_reg_operand" "")
4693 (match_operand:SF 3 "gpc_reg_operand" "")))]
4694 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4697 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4703 (define_insn "*fselsfsf4"
4704 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4705 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4706 (match_operand:SF 4 "zero_fp_constant" "F"))
4707 (match_operand:SF 2 "gpc_reg_operand" "f")
4708 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4709 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4711 [(set_attr "type" "fp")])
4713 (define_insn "*fseldfsf4"
4714 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4715 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4716 (match_operand:DF 4 "zero_fp_constant" "F"))
4717 (match_operand:SF 2 "gpc_reg_operand" "f")
4718 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4719 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4721 [(set_attr "type" "fp")])
4723 (define_insn "negdf2"
4724 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4725 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4726 "TARGET_HARD_FLOAT && TARGET_FPRS"
4728 [(set_attr "type" "fp")])
4730 (define_insn "absdf2"
4731 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4732 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4733 "TARGET_HARD_FLOAT && TARGET_FPRS"
4735 [(set_attr "type" "fp")])
4738 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4739 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4740 "TARGET_HARD_FLOAT && TARGET_FPRS"
4742 [(set_attr "type" "fp")])
4744 (define_insn "adddf3"
4745 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4746 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4747 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4748 "TARGET_HARD_FLOAT && TARGET_FPRS"
4749 "{fa|fadd} %0,%1,%2"
4750 [(set_attr "type" "fp")])
4752 (define_insn "subdf3"
4753 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4754 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4755 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4756 "TARGET_HARD_FLOAT && TARGET_FPRS"
4757 "{fs|fsub} %0,%1,%2"
4758 [(set_attr "type" "fp")])
4760 (define_insn "muldf3"
4761 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4762 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4763 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4764 "TARGET_HARD_FLOAT && TARGET_FPRS"
4765 "{fm|fmul} %0,%1,%2"
4766 [(set_attr "type" "dmul")])
4768 (define_insn "divdf3"
4769 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4770 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4771 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4772 "TARGET_HARD_FLOAT && TARGET_FPRS"
4773 "{fd|fdiv} %0,%1,%2"
4774 [(set_attr "type" "ddiv")])
4777 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4778 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4779 (match_operand:DF 2 "gpc_reg_operand" "f"))
4780 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4781 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4782 "{fma|fmadd} %0,%1,%2,%3"
4783 [(set_attr "type" "dmul")])
4786 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4787 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4788 (match_operand:DF 2 "gpc_reg_operand" "f"))
4789 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4790 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4791 "{fms|fmsub} %0,%1,%2,%3"
4792 [(set_attr "type" "dmul")])
4795 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4796 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4797 (match_operand:DF 2 "gpc_reg_operand" "f"))
4798 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4799 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4800 && HONOR_SIGNED_ZEROS (DFmode)"
4801 "{fnma|fnmadd} %0,%1,%2,%3"
4802 [(set_attr "type" "dmul")])
4805 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4806 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4807 (match_operand:DF 2 "gpc_reg_operand" "f"))
4808 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4809 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4810 && ! HONOR_SIGNED_ZEROS (DFmode)"
4811 "{fnma|fnmadd} %0,%1,%2,%3"
4812 [(set_attr "type" "dmul")])
4815 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4816 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4817 (match_operand:DF 2 "gpc_reg_operand" "f"))
4818 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4819 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4820 && HONOR_SIGNED_ZEROS (DFmode)"
4821 "{fnms|fnmsub} %0,%1,%2,%3"
4822 [(set_attr "type" "dmul")])
4825 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4826 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4827 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4828 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4829 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4830 && ! HONOR_SIGNED_ZEROS (DFmode)"
4831 "{fnms|fnmsub} %0,%1,%2,%3"
4832 [(set_attr "type" "dmul")])
4834 (define_insn "sqrtdf2"
4835 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4836 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4837 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4839 [(set_attr "type" "dsqrt")])
4841 ;; The conditional move instructions allow us to perform max and min
4842 ;; operations even when
4844 (define_expand "maxdf3"
4845 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4846 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4847 (match_operand:DF 2 "gpc_reg_operand" ""))
4850 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4851 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4853 (define_expand "mindf3"
4854 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4855 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4856 (match_operand:DF 2 "gpc_reg_operand" ""))
4859 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4860 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4863 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4864 (match_operator:DF 3 "min_max_operator"
4865 [(match_operand:DF 1 "gpc_reg_operand" "")
4866 (match_operand:DF 2 "gpc_reg_operand" "")]))]
4867 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4870 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4871 operands[1], operands[2]);
4875 (define_expand "movdfcc"
4876 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4877 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4878 (match_operand:DF 2 "gpc_reg_operand" "")
4879 (match_operand:DF 3 "gpc_reg_operand" "")))]
4880 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4883 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4889 (define_insn "*fseldfdf4"
4890 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4891 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4892 (match_operand:DF 4 "zero_fp_constant" "F"))
4893 (match_operand:DF 2 "gpc_reg_operand" "f")
4894 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4895 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4897 [(set_attr "type" "fp")])
4899 (define_insn "*fselsfdf4"
4900 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4901 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4902 (match_operand:SF 4 "zero_fp_constant" "F"))
4903 (match_operand:DF 2 "gpc_reg_operand" "f")
4904 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4907 [(set_attr "type" "fp")])
4909 ;; Conversions to and from floating-point.
4911 (define_expand "fixuns_truncsfsi2"
4912 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4913 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4914 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4917 (define_expand "fix_truncsfsi2"
4918 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4919 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4920 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4923 ; For each of these conversions, there is a define_expand, a define_insn
4924 ; with a '#' template, and a define_split (with C code). The idea is
4925 ; to allow constant folding with the template of the define_insn,
4926 ; then to have the insns split later (between sched1 and final).
4928 (define_expand "floatsidf2"
4929 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4930 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4933 (clobber (match_dup 4))
4934 (clobber (match_dup 5))
4935 (clobber (match_dup 6))])]
4936 "TARGET_HARD_FLOAT && TARGET_FPRS"
4939 if (TARGET_POWERPC64)
4941 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4942 rtx t1 = gen_reg_rtx (DImode);
4943 rtx t2 = gen_reg_rtx (DImode);
4944 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
4948 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
4949 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
4950 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
4951 operands[5] = gen_reg_rtx (DFmode);
4952 operands[6] = gen_reg_rtx (SImode);
4955 (define_insn "*floatsidf2_internal"
4956 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
4957 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
4958 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
4959 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
4960 (clobber (match_operand:DF 4 "memory_operand" "=o"))
4961 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
4962 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
4963 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
4965 [(set_attr "length" "24")])
4968 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4969 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4970 (use (match_operand:SI 2 "gpc_reg_operand" ""))
4971 (use (match_operand:DF 3 "gpc_reg_operand" ""))
4972 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
4973 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
4974 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
4975 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
4976 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4977 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4978 (use (match_operand:SI 2 "gpc_reg_operand" ""))
4979 (use (match_operand:DF 3 "gpc_reg_operand" ""))
4980 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
4981 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
4982 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
4985 rtx lowword, highword;
4986 if (GET_CODE (operands[4]) != MEM)
4988 highword = XEXP (operands[4], 0);
4989 lowword = plus_constant (highword, 4);
4990 if (! WORDS_BIG_ENDIAN)
4993 tmp = highword; highword = lowword; lowword = tmp;
4996 emit_insn (gen_xorsi3 (operands[6], operands[1],
4997 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
4998 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
4999 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5000 emit_move_insn (operands[5], operands[4]);
5001 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5005 (define_expand "floatunssisf2"
5006 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5007 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5008 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5011 (define_expand "floatunssidf2"
5012 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5013 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5016 (clobber (match_dup 4))
5017 (clobber (match_dup 5))])]
5018 "TARGET_HARD_FLOAT && TARGET_FPRS"
5021 if (TARGET_POWERPC64)
5023 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5024 rtx t1 = gen_reg_rtx (DImode);
5025 rtx t2 = gen_reg_rtx (DImode);
5026 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5031 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5032 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5033 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5034 operands[5] = gen_reg_rtx (DFmode);
5037 (define_insn "*floatunssidf2_internal"
5038 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5039 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5040 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5041 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5042 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5043 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5044 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5046 [(set_attr "length" "20")])
5049 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5050 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5051 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5052 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5053 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5054 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5055 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5056 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5057 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5058 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5059 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5060 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5061 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5064 rtx lowword, highword;
5065 if (GET_CODE (operands[4]) != MEM)
5067 highword = XEXP (operands[4], 0);
5068 lowword = plus_constant (highword, 4);
5069 if (! WORDS_BIG_ENDIAN)
5072 tmp = highword; highword = lowword; lowword = tmp;
5075 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5076 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5077 emit_move_insn (operands[5], operands[4]);
5078 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5082 (define_expand "fix_truncdfsi2"
5083 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5084 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5085 (clobber (match_dup 2))
5086 (clobber (match_dup 3))])]
5087 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5090 operands[2] = gen_reg_rtx (DImode);
5091 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5094 (define_insn "*fix_truncdfsi2_internal"
5095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5096 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5097 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5098 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5099 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5101 [(set_attr "length" "16")])
5104 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5105 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5106 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5107 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5108 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5109 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5110 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5111 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5112 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5116 if (GET_CODE (operands[3]) != MEM)
5118 lowword = XEXP (operands[3], 0);
5119 if (WORDS_BIG_ENDIAN)
5120 lowword = plus_constant (lowword, 4);
5122 emit_insn (gen_fctiwz (operands[2], operands[1]));
5123 emit_move_insn (operands[3], operands[2]);
5124 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5128 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5129 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5130 ; because the first makes it clear that operand 0 is not live
5131 ; before the instruction.
5132 (define_insn "fctiwz"
5133 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5134 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5136 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5137 "{fcirz|fctiwz} %0,%1"
5138 [(set_attr "type" "fp")])
5140 (define_expand "floatsisf2"
5141 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5142 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5143 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5146 (define_insn "floatdidf2"
5147 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5148 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5149 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5151 [(set_attr "type" "fp")])
5153 (define_insn_and_split "floatsidf_ppc64"
5154 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5155 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5156 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5157 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5158 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5159 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5162 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5163 (set (match_dup 2) (match_dup 3))
5164 (set (match_dup 4) (match_dup 2))
5165 (set (match_dup 0) (float:DF (match_dup 4)))]
5168 (define_insn_and_split "floatunssidf_ppc64"
5169 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5170 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5171 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5172 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5173 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5174 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5177 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5178 (set (match_dup 2) (match_dup 3))
5179 (set (match_dup 4) (match_dup 2))
5180 (set (match_dup 0) (float:DF (match_dup 4)))]
5183 (define_insn "fix_truncdfdi2"
5184 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5185 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5186 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5188 [(set_attr "type" "fp")])
5190 (define_expand "floatdisf2"
5191 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5192 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5193 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5196 rtx val = operands[1];
5197 if (!flag_unsafe_math_optimizations)
5199 rtx label = gen_label_rtx ();
5200 val = gen_reg_rtx (DImode);
5201 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5204 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5208 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5209 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5210 ;; from double rounding.
5211 (define_insn_and_split "floatdisf2_internal1"
5212 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5213 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5214 (clobber (match_scratch:DF 2 "=f"))]
5215 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5217 "&& reload_completed"
5219 (float:DF (match_dup 1)))
5221 (float_truncate:SF (match_dup 2)))]
5224 ;; Twiddles bits to avoid double rounding.
5225 ;; Bits that might be truncated when converting to DFmode are replaced
5226 ;; by a bit that won't be lost at that stage, but is below the SFmode
5227 ;; rounding position.
5228 (define_expand "floatdisf2_internal2"
5229 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5231 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5233 (clobber (scratch:CC))])
5234 (set (match_dup 3) (plus:DI (match_dup 3)
5236 (set (match_dup 0) (plus:DI (match_dup 0)
5238 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5240 (set (match_dup 0) (ior:DI (match_dup 0)
5242 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
5244 (clobber (scratch:CC))])
5245 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5246 (label_ref (match_operand:DI 2 "" ""))
5248 (set (match_dup 0) (match_dup 1))]
5249 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5252 operands[3] = gen_reg_rtx (DImode);
5253 operands[4] = gen_reg_rtx (CCUNSmode);
5256 ;; Define the DImode operations that can be done in a small number
5257 ;; of instructions. The & constraints are to prevent the register
5258 ;; allocator from allocating registers that overlap with the inputs
5259 ;; (for example, having an input in 7,8 and an output in 6,7). We
5260 ;; also allow for the output being the same as one of the inputs.
5262 (define_insn "*adddi3_noppc64"
5263 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5264 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5265 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5266 "! TARGET_POWERPC64"
5269 if (WORDS_BIG_ENDIAN)
5270 return (GET_CODE (operands[2])) != CONST_INT
5271 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5272 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5274 return (GET_CODE (operands[2])) != CONST_INT
5275 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5276 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5278 [(set_attr "length" "8")])
5280 (define_insn "*subdi3_noppc64"
5281 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5282 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5283 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5284 "! TARGET_POWERPC64"
5287 if (WORDS_BIG_ENDIAN)
5288 return (GET_CODE (operands[1]) != CONST_INT)
5289 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5290 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5292 return (GET_CODE (operands[1]) != CONST_INT)
5293 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5294 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5296 [(set_attr "length" "8")])
5298 (define_insn "*negdi2_noppc64"
5299 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5300 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5301 "! TARGET_POWERPC64"
5304 return (WORDS_BIG_ENDIAN)
5305 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5306 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5308 [(set_attr "length" "8")])
5310 (define_expand "mulsidi3"
5311 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5312 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5313 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5314 "! TARGET_POWERPC64"
5317 if (! TARGET_POWER && ! TARGET_POWERPC)
5319 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5320 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5321 emit_insn (gen_mull_call ());
5322 if (WORDS_BIG_ENDIAN)
5323 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5326 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5327 gen_rtx_REG (SImode, 3));
5328 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5329 gen_rtx_REG (SImode, 4));
5333 else if (TARGET_POWER)
5335 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5340 (define_insn "mulsidi3_mq"
5341 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5342 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5343 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5344 (clobber (match_scratch:SI 3 "=q"))]
5346 "mul %0,%1,%2\;mfmq %L0"
5347 [(set_attr "type" "imul")
5348 (set_attr "length" "8")])
5350 (define_insn "*mulsidi3_no_mq"
5351 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5352 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5353 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5354 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5357 return (WORDS_BIG_ENDIAN)
5358 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5359 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5361 [(set_attr "type" "imul")
5362 (set_attr "length" "8")])
5365 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5366 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5367 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5368 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5371 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5372 (sign_extend:DI (match_dup 2)))
5375 (mult:SI (match_dup 1)
5379 int endian = (WORDS_BIG_ENDIAN == 0);
5380 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5381 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5384 (define_expand "umulsidi3"
5385 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5386 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5387 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5388 "TARGET_POWERPC && ! TARGET_POWERPC64"
5393 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5398 (define_insn "umulsidi3_mq"
5399 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5400 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5401 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5402 (clobber (match_scratch:SI 3 "=q"))]
5403 "TARGET_POWERPC && TARGET_POWER"
5406 return (WORDS_BIG_ENDIAN)
5407 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5408 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5410 [(set_attr "type" "imul")
5411 (set_attr "length" "8")])
5413 (define_insn "*umulsidi3_no_mq"
5414 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5415 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5416 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5417 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5420 return (WORDS_BIG_ENDIAN)
5421 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5422 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5424 [(set_attr "type" "imul")
5425 (set_attr "length" "8")])
5428 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5429 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5430 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5431 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5434 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5435 (zero_extend:DI (match_dup 2)))
5438 (mult:SI (match_dup 1)
5442 int endian = (WORDS_BIG_ENDIAN == 0);
5443 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5444 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5447 (define_expand "smulsi3_highpart"
5448 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5450 (lshiftrt:DI (mult:DI (sign_extend:DI
5451 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5453 (match_operand:SI 2 "gpc_reg_operand" "r")))
5458 if (! TARGET_POWER && ! TARGET_POWERPC)
5460 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5461 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5462 emit_insn (gen_mulh_call ());
5463 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5466 else if (TARGET_POWER)
5468 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5473 (define_insn "smulsi3_highpart_mq"
5474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5476 (lshiftrt:DI (mult:DI (sign_extend:DI
5477 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5479 (match_operand:SI 2 "gpc_reg_operand" "r")))
5481 (clobber (match_scratch:SI 3 "=q"))]
5484 [(set_attr "type" "imul")])
5486 (define_insn "*smulsi3_highpart_no_mq"
5487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5489 (lshiftrt:DI (mult:DI (sign_extend:DI
5490 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5492 (match_operand:SI 2 "gpc_reg_operand" "r")))
5494 "TARGET_POWERPC && ! TARGET_POWER"
5496 [(set_attr "type" "imul")])
5498 (define_expand "umulsi3_highpart"
5499 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5501 (lshiftrt:DI (mult:DI (zero_extend:DI
5502 (match_operand:SI 1 "gpc_reg_operand" ""))
5504 (match_operand:SI 2 "gpc_reg_operand" "")))
5511 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5516 (define_insn "umulsi3_highpart_mq"
5517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5519 (lshiftrt:DI (mult:DI (zero_extend:DI
5520 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5522 (match_operand:SI 2 "gpc_reg_operand" "r")))
5524 (clobber (match_scratch:SI 3 "=q"))]
5525 "TARGET_POWERPC && TARGET_POWER"
5527 [(set_attr "type" "imul")])
5529 (define_insn "*umulsi3_highpart_no_mq"
5530 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5532 (lshiftrt:DI (mult:DI (zero_extend:DI
5533 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5535 (match_operand:SI 2 "gpc_reg_operand" "r")))
5537 "TARGET_POWERPC && ! TARGET_POWER"
5539 [(set_attr "type" "imul")])
5541 ;; If operands 0 and 2 are in the same register, we have a problem. But
5542 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5543 ;; why we have the strange constraints below.
5544 (define_insn "ashldi3_power"
5545 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5546 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5547 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5548 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5551 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5552 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5553 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5554 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5555 [(set_attr "length" "8")])
5557 (define_insn "lshrdi3_power"
5558 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5559 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5560 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5561 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5564 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5565 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5566 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5567 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5568 [(set_attr "length" "8")])
5570 ;; Shift by a variable amount is too complex to be worth open-coding. We
5571 ;; just handle shifts by constants.
5572 (define_insn "ashrdi3_power"
5573 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5574 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5575 (match_operand:SI 2 "const_int_operand" "M,i")))
5576 (clobber (match_scratch:SI 3 "=X,q"))]
5579 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5580 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5581 [(set_attr "length" "8")])
5583 (define_insn "ashrdi3_no_power"
5584 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5585 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5586 (match_operand:SI 2 "const_int_operand" "M,i")))]
5587 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5589 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5590 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5591 [(set_attr "length" "8,12")])
5593 (define_insn "*ashrdisi3_noppc64"
5594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5595 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5596 (const_int 32)) 4))]
5597 "TARGET_32BIT && !TARGET_POWERPC64"
5600 if (REGNO (operands[0]) == REGNO (operands[1]))
5603 return \"mr %0,%1\";
5605 [(set_attr "length" "4")])
5608 ;; PowerPC64 DImode operations.
5610 (define_expand "adddi3"
5611 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5612 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5613 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5617 if (! TARGET_POWERPC64)
5619 if (non_short_cint_operand (operands[2], DImode))
5623 if (GET_CODE (operands[2]) == CONST_INT
5624 && ! add_operand (operands[2], DImode))
5626 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5627 ? operands[0] : gen_reg_rtx (DImode));
5629 HOST_WIDE_INT val = INTVAL (operands[2]);
5630 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5631 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5633 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5636 /* The ordering here is important for the prolog expander.
5637 When space is allocated from the stack, adding 'low' first may
5638 produce a temporary deallocation (which would be bad). */
5639 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5640 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5645 ;; Discourage ai/addic because of carry but provide it in an alternative
5646 ;; allowing register zero as source.
5648 (define_insn "*adddi3_internal1"
5649 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5650 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5651 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5659 (define_insn "*adddi3_internal2"
5660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5661 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5662 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5664 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5671 [(set_attr "type" "fast_compare,compare,compare,compare")
5672 (set_attr "length" "4,4,8,8")])
5675 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5676 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5677 (match_operand:DI 2 "reg_or_short_operand" ""))
5679 (clobber (match_scratch:DI 3 ""))]
5680 "TARGET_POWERPC64 && reload_completed"
5682 (plus:DI (match_dup 1) (match_dup 2)))
5684 (compare:CC (match_dup 3)
5688 (define_insn "*adddi3_internal3"
5689 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5690 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5691 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5693 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5694 (plus:DI (match_dup 1) (match_dup 2)))]
5701 [(set_attr "type" "fast_compare,compare,compare,compare")
5702 (set_attr "length" "4,4,8,8")])
5705 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5706 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5707 (match_operand:DI 2 "reg_or_short_operand" ""))
5709 (set (match_operand:DI 0 "gpc_reg_operand" "")
5710 (plus:DI (match_dup 1) (match_dup 2)))]
5711 "TARGET_POWERPC64 && reload_completed"
5713 (plus:DI (match_dup 1) (match_dup 2)))
5715 (compare:CC (match_dup 0)
5719 ;; Split an add that we can't do in one insn into two insns, each of which
5720 ;; does one 16-bit part. This is used by combine. Note that the low-order
5721 ;; add should be last in case the result gets used in an address.
5724 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5725 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5726 (match_operand:DI 2 "non_add_cint_operand" "")))]
5728 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5729 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5732 HOST_WIDE_INT val = INTVAL (operands[2]);
5733 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5734 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5736 operands[4] = GEN_INT (low);
5737 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5738 operands[3] = GEN_INT (rest);
5739 else if (! no_new_pseudos)
5741 operands[3] = gen_reg_rtx (DImode);
5742 emit_move_insn (operands[3], operands[2]);
5743 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5750 (define_insn "one_cmpldi2"
5751 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5752 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5758 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5760 (clobber (match_scratch:DI 2 "=r,r"))]
5765 [(set_attr "type" "compare")
5766 (set_attr "length" "4,8")])
5769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5770 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5772 (clobber (match_scratch:DI 2 ""))]
5773 "TARGET_POWERPC64 && reload_completed"
5775 (not:DI (match_dup 1)))
5777 (compare:CC (match_dup 2)
5782 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5783 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5785 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5786 (not:DI (match_dup 1)))]
5791 [(set_attr "type" "compare")
5792 (set_attr "length" "4,8")])
5795 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5796 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5798 (set (match_operand:DI 0 "gpc_reg_operand" "")
5799 (not:DI (match_dup 1)))]
5800 "TARGET_POWERPC64 && reload_completed"
5802 (not:DI (match_dup 1)))
5804 (compare:CC (match_dup 0)
5809 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5810 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5811 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5819 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5820 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5822 (clobber (match_scratch:DI 3 "=r,r"))]
5827 [(set_attr "type" "fast_compare")
5828 (set_attr "length" "4,8")])
5831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5832 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5833 (match_operand:DI 2 "gpc_reg_operand" ""))
5835 (clobber (match_scratch:DI 3 ""))]
5836 "TARGET_POWERPC64 && reload_completed"
5838 (minus:DI (match_dup 1) (match_dup 2)))
5840 (compare:CC (match_dup 3)
5845 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5846 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5847 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5849 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5850 (minus:DI (match_dup 1) (match_dup 2)))]
5855 [(set_attr "type" "fast_compare")
5856 (set_attr "length" "4,8")])
5859 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5860 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5861 (match_operand:DI 2 "gpc_reg_operand" ""))
5863 (set (match_operand:DI 0 "gpc_reg_operand" "")
5864 (minus:DI (match_dup 1) (match_dup 2)))]
5865 "TARGET_POWERPC64 && reload_completed"
5867 (minus:DI (match_dup 1) (match_dup 2)))
5869 (compare:CC (match_dup 0)
5873 (define_expand "subdi3"
5874 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5875 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5876 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
5880 if (GET_CODE (operands[2]) == CONST_INT)
5882 emit_insn (gen_adddi3 (operands[0], operands[1],
5883 negate_rtx (DImode, operands[2])));
5888 (define_insn_and_split "absdi2"
5889 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5890 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5891 (clobber (match_scratch:DI 2 "=&r,&r"))]
5894 "&& reload_completed"
5895 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5896 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5897 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5900 (define_insn_and_split "*nabsdi2"
5901 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5902 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5903 (clobber (match_scratch:DI 2 "=&r,&r"))]
5906 "&& reload_completed"
5907 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5908 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5909 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5912 (define_expand "negdi2"
5913 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5914 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5919 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5920 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5926 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5928 (clobber (match_scratch:DI 2 "=r,r"))]
5933 [(set_attr "type" "fast_compare")
5934 (set_attr "length" "4,8")])
5937 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5938 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5940 (clobber (match_scratch:DI 2 ""))]
5941 "TARGET_POWERPC64 && reload_completed"
5943 (neg:DI (match_dup 1)))
5945 (compare:CC (match_dup 2)
5950 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5951 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5953 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5954 (neg:DI (match_dup 1)))]
5959 [(set_attr "type" "fast_compare")
5960 (set_attr "length" "4,8")])
5963 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5964 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5966 (set (match_operand:DI 0 "gpc_reg_operand" "")
5967 (neg:DI (match_dup 1)))]
5968 "TARGET_POWERPC64 && reload_completed"
5970 (neg:DI (match_dup 1)))
5972 (compare:CC (match_dup 0)
5976 (define_insn "clzdi2"
5977 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5978 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5982 (define_expand "ctzdi2"
5984 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
5985 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
5987 (clobber (scratch:CC))])
5988 (set (match_dup 4) (clz:DI (match_dup 3)))
5989 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
5990 (minus:DI (const_int 63) (match_dup 4)))]
5993 operands[2] = gen_reg_rtx (DImode);
5994 operands[3] = gen_reg_rtx (DImode);
5995 operands[4] = gen_reg_rtx (DImode);
5998 (define_expand "ffsdi2"
6000 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6001 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6003 (clobber (scratch:CC))])
6004 (set (match_dup 4) (clz:DI (match_dup 3)))
6005 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6006 (minus:DI (const_int 64) (match_dup 4)))]
6009 operands[2] = gen_reg_rtx (DImode);
6010 operands[3] = gen_reg_rtx (DImode);
6011 operands[4] = gen_reg_rtx (DImode);
6014 (define_insn "muldi3"
6015 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6016 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6017 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6020 [(set_attr "type" "lmul")])
6022 (define_insn "*muldi3_internal1"
6023 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6024 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6025 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6027 (clobber (match_scratch:DI 3 "=r,r"))]
6032 [(set_attr "type" "lmul_compare")
6033 (set_attr "length" "4,8")])
6036 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6037 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6038 (match_operand:DI 2 "gpc_reg_operand" ""))
6040 (clobber (match_scratch:DI 3 ""))]
6041 "TARGET_POWERPC64 && reload_completed"
6043 (mult:DI (match_dup 1) (match_dup 2)))
6045 (compare:CC (match_dup 3)
6049 (define_insn "*muldi3_internal2"
6050 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6051 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6052 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6054 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6055 (mult:DI (match_dup 1) (match_dup 2)))]
6060 [(set_attr "type" "lmul_compare")
6061 (set_attr "length" "4,8")])
6064 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6065 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6066 (match_operand:DI 2 "gpc_reg_operand" ""))
6068 (set (match_operand:DI 0 "gpc_reg_operand" "")
6069 (mult:DI (match_dup 1) (match_dup 2)))]
6070 "TARGET_POWERPC64 && reload_completed"
6072 (mult:DI (match_dup 1) (match_dup 2)))
6074 (compare:CC (match_dup 0)
6078 (define_insn "smuldi3_highpart"
6079 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6081 (lshiftrt:TI (mult:TI (sign_extend:TI
6082 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6084 (match_operand:DI 2 "gpc_reg_operand" "r")))
6088 [(set_attr "type" "lmul")])
6090 (define_insn "umuldi3_highpart"
6091 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6093 (lshiftrt:TI (mult:TI (zero_extend:TI
6094 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6096 (match_operand:DI 2 "gpc_reg_operand" "r")))
6100 [(set_attr "type" "lmul")])
6102 (define_expand "divdi3"
6103 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6104 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6105 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6109 if (GET_CODE (operands[2]) == CONST_INT
6110 && INTVAL (operands[2]) > 0
6111 && exact_log2 (INTVAL (operands[2])) >= 0)
6114 operands[2] = force_reg (DImode, operands[2]);
6117 (define_expand "moddi3"
6118 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6119 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6120 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6128 if (GET_CODE (operands[2]) != CONST_INT
6129 || INTVAL (operands[2]) <= 0
6130 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6133 temp1 = gen_reg_rtx (DImode);
6134 temp2 = gen_reg_rtx (DImode);
6136 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6137 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6138 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6143 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6144 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6145 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6147 "sradi %0,%1,%p2\;addze %0,%0"
6148 [(set_attr "length" "8")])
6151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6152 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6153 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6155 (clobber (match_scratch:DI 3 "=r,r"))]
6158 sradi %3,%1,%p2\;addze. %3,%3
6160 [(set_attr "type" "compare")
6161 (set_attr "length" "8,12")])
6164 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6165 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6166 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6168 (clobber (match_scratch:DI 3 ""))]
6169 "TARGET_POWERPC64 && reload_completed"
6171 (div:DI (match_dup 1) (match_dup 2)))
6173 (compare:CC (match_dup 3)
6178 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6179 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6180 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6182 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6183 (div:DI (match_dup 1) (match_dup 2)))]
6186 sradi %0,%1,%p2\;addze. %0,%0
6188 [(set_attr "type" "compare")
6189 (set_attr "length" "8,12")])
6192 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6193 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6194 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6196 (set (match_operand:DI 0 "gpc_reg_operand" "")
6197 (div:DI (match_dup 1) (match_dup 2)))]
6198 "TARGET_POWERPC64 && reload_completed"
6200 (div:DI (match_dup 1) (match_dup 2)))
6202 (compare:CC (match_dup 0)
6207 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6208 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6209 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6212 [(set_attr "type" "ldiv")])
6214 (define_insn "udivdi3"
6215 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6216 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6217 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6220 [(set_attr "type" "ldiv")])
6222 (define_insn "rotldi3"
6223 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6224 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6225 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6227 "rld%I2cl %0,%1,%H2,0")
6229 (define_insn "*rotldi3_internal2"
6230 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6231 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6232 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6234 (clobber (match_scratch:DI 3 "=r,r"))]
6237 rld%I2cl. %3,%1,%H2,0
6239 [(set_attr "type" "delayed_compare")
6240 (set_attr "length" "4,8")])
6243 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6244 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6245 (match_operand:DI 2 "reg_or_cint_operand" ""))
6247 (clobber (match_scratch:DI 3 ""))]
6248 "TARGET_POWERPC64 && reload_completed"
6250 (rotate:DI (match_dup 1) (match_dup 2)))
6252 (compare:CC (match_dup 3)
6256 (define_insn "*rotldi3_internal3"
6257 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6258 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6259 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6261 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6262 (rotate:DI (match_dup 1) (match_dup 2)))]
6265 rld%I2cl. %0,%1,%H2,0
6267 [(set_attr "type" "delayed_compare")
6268 (set_attr "length" "4,8")])
6271 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6272 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6273 (match_operand:DI 2 "reg_or_cint_operand" ""))
6275 (set (match_operand:DI 0 "gpc_reg_operand" "")
6276 (rotate:DI (match_dup 1) (match_dup 2)))]
6277 "TARGET_POWERPC64 && reload_completed"
6279 (rotate:DI (match_dup 1) (match_dup 2)))
6281 (compare:CC (match_dup 0)
6285 (define_insn "*rotldi3_internal4"
6286 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6287 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6288 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6289 (match_operand:DI 3 "mask64_operand" "n")))]
6291 "rld%I2c%B3 %0,%1,%H2,%S3")
6293 (define_insn "*rotldi3_internal5"
6294 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6296 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6297 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6298 (match_operand:DI 3 "mask64_operand" "n,n"))
6300 (clobber (match_scratch:DI 4 "=r,r"))]
6303 rld%I2c%B3. %4,%1,%H2,%S3
6305 [(set_attr "type" "delayed_compare")
6306 (set_attr "length" "4,8")])
6309 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6311 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6312 (match_operand:DI 2 "reg_or_cint_operand" ""))
6313 (match_operand:DI 3 "mask64_operand" ""))
6315 (clobber (match_scratch:DI 4 ""))]
6316 "TARGET_POWERPC64 && reload_completed"
6318 (and:DI (rotate:DI (match_dup 1)
6322 (compare:CC (match_dup 4)
6326 (define_insn "*rotldi3_internal6"
6327 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6329 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6330 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6331 (match_operand:DI 3 "mask64_operand" "n,n"))
6333 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6334 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6337 rld%I2c%B3. %0,%1,%H2,%S3
6339 [(set_attr "type" "delayed_compare")
6340 (set_attr "length" "4,8")])
6343 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6345 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6346 (match_operand:DI 2 "reg_or_cint_operand" ""))
6347 (match_operand:DI 3 "mask64_operand" ""))
6349 (set (match_operand:DI 0 "gpc_reg_operand" "")
6350 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6351 "TARGET_POWERPC64 && reload_completed"
6353 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6355 (compare:CC (match_dup 0)
6359 (define_insn "*rotldi3_internal7"
6360 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6363 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6364 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6366 "rld%I2cl %0,%1,%H2,56")
6368 (define_insn "*rotldi3_internal8"
6369 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6370 (compare:CC (zero_extend:DI
6372 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6373 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6375 (clobber (match_scratch:DI 3 "=r,r"))]
6378 rld%I2cl. %3,%1,%H2,56
6380 [(set_attr "type" "delayed_compare")
6381 (set_attr "length" "4,8")])
6384 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6385 (compare:CC (zero_extend:DI
6387 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6388 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6390 (clobber (match_scratch:DI 3 ""))]
6391 "TARGET_POWERPC64 && reload_completed"
6393 (zero_extend:DI (subreg:QI
6394 (rotate:DI (match_dup 1)
6397 (compare:CC (match_dup 3)
6401 (define_insn "*rotldi3_internal9"
6402 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6403 (compare:CC (zero_extend:DI
6405 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6406 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6408 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6409 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6412 rld%I2cl. %0,%1,%H2,56
6414 [(set_attr "type" "delayed_compare")
6415 (set_attr "length" "4,8")])
6418 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6419 (compare:CC (zero_extend:DI
6421 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6422 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6424 (set (match_operand:DI 0 "gpc_reg_operand" "")
6425 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6426 "TARGET_POWERPC64 && reload_completed"
6428 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6430 (compare:CC (match_dup 0)
6434 (define_insn "*rotldi3_internal10"
6435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6438 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6439 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6441 "rld%I2cl %0,%1,%H2,48")
6443 (define_insn "*rotldi3_internal11"
6444 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6445 (compare:CC (zero_extend:DI
6447 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6448 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6450 (clobber (match_scratch:DI 3 "=r,r"))]
6453 rld%I2cl. %3,%1,%H2,48
6455 [(set_attr "type" "delayed_compare")
6456 (set_attr "length" "4,8")])
6459 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6460 (compare:CC (zero_extend:DI
6462 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6463 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6465 (clobber (match_scratch:DI 3 ""))]
6466 "TARGET_POWERPC64 && reload_completed"
6468 (zero_extend:DI (subreg:HI
6469 (rotate:DI (match_dup 1)
6472 (compare:CC (match_dup 3)
6476 (define_insn "*rotldi3_internal12"
6477 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6478 (compare:CC (zero_extend:DI
6480 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6481 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6483 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6484 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6487 rld%I2cl. %0,%1,%H2,48
6489 [(set_attr "type" "delayed_compare")
6490 (set_attr "length" "4,8")])
6493 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6494 (compare:CC (zero_extend:DI
6496 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6497 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6499 (set (match_operand:DI 0 "gpc_reg_operand" "")
6500 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6501 "TARGET_POWERPC64 && reload_completed"
6503 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6505 (compare:CC (match_dup 0)
6509 (define_insn "*rotldi3_internal13"
6510 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6513 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6514 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6516 "rld%I2cl %0,%1,%H2,32")
6518 (define_insn "*rotldi3_internal14"
6519 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6520 (compare:CC (zero_extend:DI
6522 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6523 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6525 (clobber (match_scratch:DI 3 "=r,r"))]
6528 rld%I2cl. %3,%1,%H2,32
6530 [(set_attr "type" "delayed_compare")
6531 (set_attr "length" "4,8")])
6534 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6535 (compare:CC (zero_extend:DI
6537 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6538 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6540 (clobber (match_scratch:DI 3 ""))]
6541 "TARGET_POWERPC64 && reload_completed"
6543 (zero_extend:DI (subreg:SI
6544 (rotate:DI (match_dup 1)
6547 (compare:CC (match_dup 3)
6551 (define_insn "*rotldi3_internal15"
6552 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6553 (compare:CC (zero_extend:DI
6555 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6556 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6558 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6559 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6562 rld%I2cl. %0,%1,%H2,32
6564 [(set_attr "type" "delayed_compare")
6565 (set_attr "length" "4,8")])
6568 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6569 (compare:CC (zero_extend:DI
6571 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6572 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6574 (set (match_operand:DI 0 "gpc_reg_operand" "")
6575 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6576 "TARGET_POWERPC64 && reload_completed"
6578 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6580 (compare:CC (match_dup 0)
6584 (define_expand "ashldi3"
6585 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6586 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6587 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6588 "TARGET_POWERPC64 || TARGET_POWER"
6591 if (TARGET_POWERPC64)
6593 else if (TARGET_POWER)
6595 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6602 (define_insn "*ashldi3_internal1"
6603 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6604 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6605 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6608 [(set_attr "length" "8")])
6610 (define_insn "*ashldi3_internal2"
6611 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6612 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6613 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6615 (clobber (match_scratch:DI 3 "=r,r"))]
6620 [(set_attr "type" "delayed_compare")
6621 (set_attr "length" "4,8")])
6624 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6625 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6626 (match_operand:SI 2 "reg_or_cint_operand" ""))
6628 (clobber (match_scratch:DI 3 ""))]
6629 "TARGET_POWERPC64 && reload_completed"
6631 (ashift:DI (match_dup 1) (match_dup 2)))
6633 (compare:CC (match_dup 3)
6637 (define_insn "*ashldi3_internal3"
6638 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6639 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6640 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6642 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6643 (ashift:DI (match_dup 1) (match_dup 2)))]
6648 [(set_attr "type" "delayed_compare")
6649 (set_attr "length" "4,8")])
6652 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6653 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6654 (match_operand:SI 2 "reg_or_cint_operand" ""))
6656 (set (match_operand:DI 0 "gpc_reg_operand" "")
6657 (ashift:DI (match_dup 1) (match_dup 2)))]
6658 "TARGET_POWERPC64 && reload_completed"
6660 (ashift:DI (match_dup 1) (match_dup 2)))
6662 (compare:CC (match_dup 0)
6666 (define_insn "*ashldi3_internal4"
6667 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6668 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6669 (match_operand:SI 2 "const_int_operand" "i"))
6670 (match_operand:DI 3 "const_int_operand" "n")))]
6671 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6672 "rldic %0,%1,%H2,%W3")
6674 (define_insn "ashldi3_internal5"
6675 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6677 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6678 (match_operand:SI 2 "const_int_operand" "i,i"))
6679 (match_operand:DI 3 "const_int_operand" "n,n"))
6681 (clobber (match_scratch:DI 4 "=r,r"))]
6682 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6684 rldic. %4,%1,%H2,%W3
6686 [(set_attr "type" "delayed_compare")
6687 (set_attr "length" "4,8")])
6690 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6692 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6693 (match_operand:SI 2 "const_int_operand" ""))
6694 (match_operand:DI 3 "const_int_operand" ""))
6696 (clobber (match_scratch:DI 4 ""))]
6697 "TARGET_POWERPC64 && reload_completed
6698 && includes_rldic_lshift_p (operands[2], operands[3])"
6700 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6703 (compare:CC (match_dup 4)
6707 (define_insn "*ashldi3_internal6"
6708 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6710 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6711 (match_operand:SI 2 "const_int_operand" "i,i"))
6712 (match_operand:DI 3 "const_int_operand" "n,n"))
6714 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6715 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6716 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6718 rldic. %0,%1,%H2,%W3
6720 [(set_attr "type" "delayed_compare")
6721 (set_attr "length" "4,8")])
6724 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6726 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6727 (match_operand:SI 2 "const_int_operand" ""))
6728 (match_operand:DI 3 "const_int_operand" ""))
6730 (set (match_operand:DI 0 "gpc_reg_operand" "")
6731 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6732 "TARGET_POWERPC64 && reload_completed
6733 && includes_rldic_lshift_p (operands[2], operands[3])"
6735 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6738 (compare:CC (match_dup 0)
6742 (define_insn "*ashldi3_internal7"
6743 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6744 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6745 (match_operand:SI 2 "const_int_operand" "i"))
6746 (match_operand:DI 3 "mask64_operand" "n")))]
6747 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6748 "rldicr %0,%1,%H2,%S3")
6750 (define_insn "ashldi3_internal8"
6751 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6753 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6754 (match_operand:SI 2 "const_int_operand" "i,i"))
6755 (match_operand:DI 3 "mask64_operand" "n,n"))
6757 (clobber (match_scratch:DI 4 "=r,r"))]
6758 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6760 rldicr. %4,%1,%H2,%S3
6762 [(set_attr "type" "delayed_compare")
6763 (set_attr "length" "4,8")])
6766 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6768 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6769 (match_operand:SI 2 "const_int_operand" ""))
6770 (match_operand:DI 3 "mask64_operand" ""))
6772 (clobber (match_scratch:DI 4 ""))]
6773 "TARGET_POWERPC64 && reload_completed
6774 && includes_rldicr_lshift_p (operands[2], operands[3])"
6776 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6779 (compare:CC (match_dup 4)
6783 (define_insn "*ashldi3_internal9"
6784 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6786 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6787 (match_operand:SI 2 "const_int_operand" "i,i"))
6788 (match_operand:DI 3 "mask64_operand" "n,n"))
6790 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6791 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6792 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6794 rldicr. %0,%1,%H2,%S3
6796 [(set_attr "type" "delayed_compare")
6797 (set_attr "length" "4,8")])
6800 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6802 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6803 (match_operand:SI 2 "const_int_operand" ""))
6804 (match_operand:DI 3 "mask64_operand" ""))
6806 (set (match_operand:DI 0 "gpc_reg_operand" "")
6807 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6808 "TARGET_POWERPC64 && reload_completed
6809 && includes_rldicr_lshift_p (operands[2], operands[3])"
6811 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6814 (compare:CC (match_dup 0)
6818 (define_expand "lshrdi3"
6819 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6820 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6821 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6822 "TARGET_POWERPC64 || TARGET_POWER"
6825 if (TARGET_POWERPC64)
6827 else if (TARGET_POWER)
6829 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6836 (define_insn "*lshrdi3_internal1"
6837 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6838 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6839 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6843 (define_insn "*lshrdi3_internal2"
6844 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6845 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6846 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6848 (clobber (match_scratch:DI 3 "=r,r"))]
6853 [(set_attr "type" "delayed_compare")
6854 (set_attr "length" "4,8")])
6857 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6858 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6859 (match_operand:SI 2 "reg_or_cint_operand" ""))
6861 (clobber (match_scratch:DI 3 ""))]
6862 "TARGET_POWERPC64 && reload_completed"
6864 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6866 (compare:CC (match_dup 3)
6870 (define_insn "*lshrdi3_internal3"
6871 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6872 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6873 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6875 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6876 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6881 [(set_attr "type" "delayed_compare")
6882 (set_attr "length" "4,8")])
6885 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6886 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6887 (match_operand:SI 2 "reg_or_cint_operand" ""))
6889 (set (match_operand:DI 0 "gpc_reg_operand" "")
6890 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6891 "TARGET_POWERPC64 && reload_completed"
6893 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6895 (compare:CC (match_dup 0)
6899 (define_expand "ashrdi3"
6900 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6901 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6902 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6906 if (TARGET_POWERPC64)
6908 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6910 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6913 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6914 && WORDS_BIG_ENDIAN)
6916 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6923 (define_insn "*ashrdi3_internal1"
6924 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6925 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6926 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6928 "srad%I2 %0,%1,%H2")
6930 (define_insn "*ashrdi3_internal2"
6931 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6932 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6933 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6935 (clobber (match_scratch:DI 3 "=r,r"))]
6940 [(set_attr "type" "delayed_compare")
6941 (set_attr "length" "4,8")])
6944 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6945 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6946 (match_operand:SI 2 "reg_or_cint_operand" ""))
6948 (clobber (match_scratch:DI 3 ""))]
6949 "TARGET_POWERPC64 && reload_completed"
6951 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6953 (compare:CC (match_dup 3)
6957 (define_insn "*ashrdi3_internal3"
6958 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6959 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6960 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6962 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6963 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6968 [(set_attr "type" "delayed_compare")
6969 (set_attr "length" "4,8")])
6972 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6973 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6974 (match_operand:SI 2 "reg_or_cint_operand" ""))
6976 (set (match_operand:DI 0 "gpc_reg_operand" "")
6977 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6978 "TARGET_POWERPC64 && reload_completed"
6980 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6982 (compare:CC (match_dup 0)
6986 (define_insn "anddi3"
6987 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
6988 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
6989 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
6990 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
6994 rldic%B2 %0,%1,0,%S2
6998 [(set_attr "length" "4,4,4,4,8")])
7001 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7002 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7003 (match_operand:DI 2 "mask64_2_operand" "")))
7004 (clobber (match_scratch:CC 3 ""))]
7006 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7007 && !mask64_operand (operands[2], DImode)"
7009 (and:DI (rotate:DI (match_dup 1)
7013 (and:DI (rotate:DI (match_dup 0)
7018 build_mask64_2_operands (operands[2], &operands[4]);
7021 (define_insn "*anddi3_internal2"
7022 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7023 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7024 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7026 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7027 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7031 rldic%B2. %3,%1,0,%S2
7040 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7041 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7045 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7046 (match_operand:DI 2 "and64_operand" ""))
7048 (clobber (match_scratch:DI 3 ""))
7049 (clobber (match_scratch:CC 4 ""))]
7050 "TARGET_POWERPC64 && reload_completed"
7051 [(parallel [(set (match_dup 3)
7052 (and:DI (match_dup 1)
7054 (clobber (match_dup 4))])
7056 (compare:CC (match_dup 3)
7061 [(set (match_operand:CC 0 "cc_reg_operand" "")
7062 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7063 (match_operand:DI 2 "mask64_2_operand" ""))
7065 (clobber (match_scratch:DI 3 ""))
7066 (clobber (match_scratch:CC 4 ""))]
7067 "TARGET_POWERPC64 && reload_completed
7068 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7069 && !mask64_operand (operands[2], DImode)"
7071 (and:DI (rotate:DI (match_dup 1)
7074 (parallel [(set (match_dup 0)
7075 (compare:CC (and:DI (rotate:DI (match_dup 3)
7079 (clobber (match_dup 3))])]
7082 build_mask64_2_operands (operands[2], &operands[5]);
7085 (define_insn "*anddi3_internal3"
7086 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7087 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7088 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7090 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7091 (and:DI (match_dup 1) (match_dup 2)))
7092 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7096 rldic%B2. %0,%1,0,%S2
7105 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7106 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7109 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7110 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7111 (match_operand:DI 2 "and64_operand" ""))
7113 (set (match_operand:DI 0 "gpc_reg_operand" "")
7114 (and:DI (match_dup 1) (match_dup 2)))
7115 (clobber (match_scratch:CC 4 ""))]
7116 "TARGET_POWERPC64 && reload_completed"
7117 [(parallel [(set (match_dup 0)
7118 (and:DI (match_dup 1) (match_dup 2)))
7119 (clobber (match_dup 4))])
7121 (compare:CC (match_dup 0)
7126 [(set (match_operand:CC 3 "cc_reg_operand" "")
7127 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7128 (match_operand:DI 2 "mask64_2_operand" ""))
7130 (set (match_operand:DI 0 "gpc_reg_operand" "")
7131 (and:DI (match_dup 1) (match_dup 2)))
7132 (clobber (match_scratch:CC 4 ""))]
7133 "TARGET_POWERPC64 && reload_completed
7134 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7135 && !mask64_operand (operands[2], DImode)"
7137 (and:DI (rotate:DI (match_dup 1)
7140 (parallel [(set (match_dup 3)
7141 (compare:CC (and:DI (rotate:DI (match_dup 0)
7146 (and:DI (rotate:DI (match_dup 0)
7151 build_mask64_2_operands (operands[2], &operands[5]);
7154 (define_expand "iordi3"
7155 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7156 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7157 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7161 if (non_logical_cint_operand (operands[2], DImode))
7163 HOST_WIDE_INT value;
7164 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7165 ? operands[0] : gen_reg_rtx (DImode));
7167 if (GET_CODE (operands[2]) == CONST_INT)
7169 value = INTVAL (operands[2]);
7170 emit_insn (gen_iordi3 (tmp, operands[1],
7171 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7175 value = CONST_DOUBLE_LOW (operands[2]);
7176 emit_insn (gen_iordi3 (tmp, operands[1],
7177 immed_double_const (value
7178 & (~ (HOST_WIDE_INT) 0xffff),
7182 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7187 (define_expand "xordi3"
7188 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7189 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7190 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7194 if (non_logical_cint_operand (operands[2], DImode))
7196 HOST_WIDE_INT value;
7197 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7198 ? operands[0] : gen_reg_rtx (DImode));
7200 if (GET_CODE (operands[2]) == CONST_INT)
7202 value = INTVAL (operands[2]);
7203 emit_insn (gen_xordi3 (tmp, operands[1],
7204 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7208 value = CONST_DOUBLE_LOW (operands[2]);
7209 emit_insn (gen_xordi3 (tmp, operands[1],
7210 immed_double_const (value
7211 & (~ (HOST_WIDE_INT) 0xffff),
7215 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7220 (define_insn "*booldi3_internal1"
7221 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7222 (match_operator:DI 3 "boolean_or_operator"
7223 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7224 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7231 (define_insn "*booldi3_internal2"
7232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7233 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7234 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7235 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7237 (clobber (match_scratch:DI 3 "=r,r"))]
7242 [(set_attr "type" "compare")
7243 (set_attr "length" "4,8")])
7246 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7247 (compare:CC (match_operator:DI 4 "boolean_operator"
7248 [(match_operand:DI 1 "gpc_reg_operand" "")
7249 (match_operand:DI 2 "gpc_reg_operand" "")])
7251 (clobber (match_scratch:DI 3 ""))]
7252 "TARGET_POWERPC64 && reload_completed"
7253 [(set (match_dup 3) (match_dup 4))
7255 (compare:CC (match_dup 3)
7259 (define_insn "*booldi3_internal3"
7260 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7261 (compare:CC (match_operator:DI 4 "boolean_operator"
7262 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7263 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7265 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7271 [(set_attr "type" "compare")
7272 (set_attr "length" "4,8")])
7275 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7276 (compare:CC (match_operator:DI 4 "boolean_operator"
7277 [(match_operand:DI 1 "gpc_reg_operand" "")
7278 (match_operand:DI 2 "gpc_reg_operand" "")])
7280 (set (match_operand:DI 0 "gpc_reg_operand" "")
7282 "TARGET_POWERPC64 && reload_completed"
7283 [(set (match_dup 0) (match_dup 4))
7285 (compare:CC (match_dup 0)
7289 ;; Split a logical operation that we can't do in one insn into two insns,
7290 ;; each of which does one 16-bit part. This is used by combine.
7293 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7294 (match_operator:DI 3 "boolean_or_operator"
7295 [(match_operand:DI 1 "gpc_reg_operand" "")
7296 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7298 [(set (match_dup 0) (match_dup 4))
7299 (set (match_dup 0) (match_dup 5))]
7304 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7306 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7307 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7309 i4 = GEN_INT (value & 0xffff);
7313 i3 = GEN_INT (INTVAL (operands[2])
7314 & (~ (HOST_WIDE_INT) 0xffff));
7315 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7317 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7319 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7323 (define_insn "*boolcdi3_internal1"
7324 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7325 (match_operator:DI 3 "boolean_operator"
7326 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7327 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7331 (define_insn "*boolcdi3_internal2"
7332 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7333 (compare:CC (match_operator:DI 4 "boolean_operator"
7334 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7335 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7337 (clobber (match_scratch:DI 3 "=r,r"))]
7342 [(set_attr "type" "compare")
7343 (set_attr "length" "4,8")])
7346 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7347 (compare:CC (match_operator:DI 4 "boolean_operator"
7348 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7349 (match_operand:DI 2 "gpc_reg_operand" "")])
7351 (clobber (match_scratch:DI 3 ""))]
7352 "TARGET_POWERPC64 && reload_completed"
7353 [(set (match_dup 3) (match_dup 4))
7355 (compare:CC (match_dup 3)
7359 (define_insn "*boolcdi3_internal3"
7360 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7361 (compare:CC (match_operator:DI 4 "boolean_operator"
7362 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7363 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7365 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7371 [(set_attr "type" "compare")
7372 (set_attr "length" "4,8")])
7375 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7376 (compare:CC (match_operator:DI 4 "boolean_operator"
7377 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7378 (match_operand:DI 2 "gpc_reg_operand" "")])
7380 (set (match_operand:DI 0 "gpc_reg_operand" "")
7382 "TARGET_POWERPC64 && reload_completed"
7383 [(set (match_dup 0) (match_dup 4))
7385 (compare:CC (match_dup 0)
7389 (define_insn "*boolccdi3_internal1"
7390 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7391 (match_operator:DI 3 "boolean_operator"
7392 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7393 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7397 (define_insn "*boolccdi3_internal2"
7398 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7399 (compare:CC (match_operator:DI 4 "boolean_operator"
7400 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7401 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7403 (clobber (match_scratch:DI 3 "=r,r"))]
7408 [(set_attr "type" "compare")
7409 (set_attr "length" "4,8")])
7412 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7413 (compare:CC (match_operator:DI 4 "boolean_operator"
7414 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7415 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7417 (clobber (match_scratch:DI 3 ""))]
7418 "TARGET_POWERPC64 && reload_completed"
7419 [(set (match_dup 3) (match_dup 4))
7421 (compare:CC (match_dup 3)
7425 (define_insn "*boolccdi3_internal3"
7426 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7427 (compare:CC (match_operator:DI 4 "boolean_operator"
7428 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7429 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7431 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7437 [(set_attr "type" "compare")
7438 (set_attr "length" "4,8")])
7441 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7442 (compare:CC (match_operator:DI 4 "boolean_operator"
7443 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7444 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7446 (set (match_operand:DI 0 "gpc_reg_operand" "")
7448 "TARGET_POWERPC64 && reload_completed"
7449 [(set (match_dup 0) (match_dup 4))
7451 (compare:CC (match_dup 0)
7455 ;; Now define ways of moving data around.
7457 ;; Elf specific ways of loading addresses for non-PIC code.
7458 ;; The output of this could be r0, but we make a very strong
7459 ;; preference for a base register because it will usually
7461 (define_insn "elf_high"
7462 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7463 (high:SI (match_operand 1 "" "")))]
7464 "TARGET_ELF && ! TARGET_64BIT"
7465 "{liu|lis} %0,%1@ha")
7467 (define_insn "elf_low"
7468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7469 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7470 (match_operand 2 "" "")))]
7471 "TARGET_ELF && ! TARGET_64BIT"
7473 {cal|la} %0,%2@l(%1)
7474 {ai|addic} %0,%1,%K2")
7476 ;; Mach-O PIC trickery.
7477 (define_insn "macho_high"
7478 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7479 (high:SI (match_operand 1 "" "")))]
7480 "TARGET_MACHO && ! TARGET_64BIT"
7481 "{liu|lis} %0,ha16(%1)")
7483 (define_insn "macho_low"
7484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7485 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7486 (match_operand 2 "" "")))]
7487 "TARGET_MACHO && ! TARGET_64BIT"
7489 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7490 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7492 ;; Set up a register with a value from the GOT table
7494 (define_expand "movsi_got"
7495 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7496 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7497 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7498 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7501 if (GET_CODE (operands[1]) == CONST)
7503 rtx offset = const0_rtx;
7504 HOST_WIDE_INT value;
7506 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7507 value = INTVAL (offset);
7510 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7511 emit_insn (gen_movsi_got (tmp, operands[1]));
7512 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7517 operands[2] = rs6000_got_register (operands[1]);
7520 (define_insn "*movsi_got_internal"
7521 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7522 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7523 (match_operand:SI 2 "gpc_reg_operand" "b")]
7525 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7526 "{l|lwz} %0,%a1@got(%2)"
7527 [(set_attr "type" "load")])
7529 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7530 ;; didn't get allocated to a hard register.
7532 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7533 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7534 (match_operand:SI 2 "memory_operand" "")]
7536 "DEFAULT_ABI == ABI_V4
7538 && (reload_in_progress || reload_completed)"
7539 [(set (match_dup 0) (match_dup 2))
7540 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7544 ;; For SI, we special-case integers that can't be loaded in one insn. We
7545 ;; do the load 16-bits at a time. We could do this by loading from memory,
7546 ;; and this is even supposed to be faster, but it is simpler not to get
7547 ;; integers in the TOC.
7548 (define_expand "movsi"
7549 [(set (match_operand:SI 0 "general_operand" "")
7550 (match_operand:SI 1 "any_operand" ""))]
7552 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7554 (define_insn "movsi_low"
7555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7556 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7557 (match_operand 2 "" ""))))]
7558 "TARGET_MACHO && ! TARGET_64BIT"
7559 "{l|lwz} %0,lo16(%2)(%1)"
7560 [(set_attr "type" "load")
7561 (set_attr "length" "4")])
7563 (define_insn "movsi_low_st"
7564 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7565 (match_operand 2 "" "")))
7566 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7567 "TARGET_MACHO && ! TARGET_64BIT"
7568 "{st|stw} %0,lo16(%2)(%1)"
7569 [(set_attr "type" "store")
7570 (set_attr "length" "4")])
7572 (define_insn "movdf_low"
7573 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
7574 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7575 (match_operand 2 "" ""))))]
7576 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7579 switch (which_alternative)
7582 return \"lfd %0,lo16(%2)(%1)\";
7586 operands2[0] = operands[0];
7587 operands2[1] = operands[1];
7588 operands2[2] = operands[2];
7589 if (TARGET_POWERPC64 && TARGET_32BIT)
7590 /* Note, old assemblers didn't support relocation here. */
7591 return \"ld %0,lo16(%2)(%1)\";
7594 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7595 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7597 if (MACHO_DYNAMIC_NO_PIC_P)
7598 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
7600 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7601 although in practice it almost always is. */
7602 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7604 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7611 [(set_attr "type" "load")
7612 (set_attr "length" "4,12")])
7614 (define_insn "movdf_low_st"
7615 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7616 (match_operand 2 "" "")))
7617 (match_operand:DF 0 "gpc_reg_operand" "f"))]
7618 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7619 "stfd %0,lo16(%2)(%1)"
7620 [(set_attr "type" "store")
7621 (set_attr "length" "4")])
7623 (define_insn "movsf_low"
7624 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
7625 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7626 (match_operand 2 "" ""))))]
7627 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7630 {l|lwz} %0,lo16(%2)(%1)"
7631 [(set_attr "type" "load")
7632 (set_attr "length" "4")])
7634 (define_insn "movsf_low_st"
7635 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7636 (match_operand 2 "" "")))
7637 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
7638 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7640 stfs %0,lo16(%2)(%1)
7641 {st|stw} %0,lo16(%2)(%1)"
7642 [(set_attr "type" "store")
7643 (set_attr "length" "4")])
7645 (define_insn "*movsi_internal1"
7646 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7647 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7648 "gpc_reg_operand (operands[0], SImode)
7649 || gpc_reg_operand (operands[1], SImode)"
7653 {l%U1%X1|lwz%U1%X1} %0,%1
7654 {st%U0%X0|stw%U0%X0} %1,%0
7664 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7665 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7667 ;; Split a load of a large constant into the appropriate two-insn
7671 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7672 (match_operand:SI 1 "const_int_operand" ""))]
7673 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7674 && (INTVAL (operands[1]) & 0xffff) != 0"
7678 (ior:SI (match_dup 0)
7681 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7683 if (tem == operands[0])
7689 (define_insn "*movsi_internal2"
7690 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7691 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7693 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7696 {cmpi|cmpwi} %2,%0,0
7699 [(set_attr "type" "cmp,compare,cmp")
7700 (set_attr "length" "4,4,8")])
7703 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7704 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7706 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7707 "TARGET_32BIT && reload_completed"
7708 [(set (match_dup 0) (match_dup 1))
7710 (compare:CC (match_dup 0)
7714 (define_expand "movhi"
7715 [(set (match_operand:HI 0 "general_operand" "")
7716 (match_operand:HI 1 "any_operand" ""))]
7718 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7720 (define_insn "*movhi_internal"
7721 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7722 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7723 "gpc_reg_operand (operands[0], HImode)
7724 || gpc_reg_operand (operands[1], HImode)"
7734 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7736 (define_expand "movqi"
7737 [(set (match_operand:QI 0 "general_operand" "")
7738 (match_operand:QI 1 "any_operand" ""))]
7740 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7742 (define_insn "*movqi_internal"
7743 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7744 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7745 "gpc_reg_operand (operands[0], QImode)
7746 || gpc_reg_operand (operands[1], QImode)"
7756 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7758 ;; Here is how to move condition codes around. When we store CC data in
7759 ;; an integer register or memory, we store just the high-order 4 bits.
7760 ;; This lets us not shift in the most common case of CR0.
7761 (define_expand "movcc"
7762 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7763 (match_operand:CC 1 "nonimmediate_operand" ""))]
7767 (define_insn "*movcc_internal1"
7768 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7769 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7770 "register_operand (operands[0], CCmode)
7771 || register_operand (operands[1], CCmode)"
7775 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7777 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7782 {l%U1%X1|lwz%U1%X1} %0,%1
7783 {st%U0%U1|stw%U0%U1} %1,%0"
7785 (cond [(eq_attr "alternative" "0")
7786 (const_string "cr_logical")
7787 (eq_attr "alternative" "1,2")
7788 (const_string "mtcr")
7789 (eq_attr "alternative" "5,7")
7790 (const_string "integer")
7791 (eq_attr "alternative" "6")
7792 (const_string "mfjmpr")
7793 (eq_attr "alternative" "8")
7794 (const_string "mtjmpr")
7795 (eq_attr "alternative" "9")
7796 (const_string "load")
7797 (eq_attr "alternative" "10")
7798 (const_string "store")
7799 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7800 (const_string "mfcrf")
7802 (const_string "mfcr")))
7803 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7805 ;; For floating-point, we normally deal with the floating-point registers
7806 ;; unless -msoft-float is used. The sole exception is that parameter passing
7807 ;; can produce floating-point values in fixed-point registers. Unless the
7808 ;; value is a simple constant or already in memory, we deal with this by
7809 ;; allocating memory and copying the value explicitly via that memory location.
7810 (define_expand "movsf"
7811 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7812 (match_operand:SF 1 "any_operand" ""))]
7814 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7817 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7818 (match_operand:SF 1 "const_double_operand" ""))]
7820 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7821 || (GET_CODE (operands[0]) == SUBREG
7822 && GET_CODE (SUBREG_REG (operands[0])) == REG
7823 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7824 [(set (match_dup 2) (match_dup 3))]
7830 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7831 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7833 if (! TARGET_POWERPC64)
7834 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7836 operands[2] = gen_lowpart (SImode, operands[0]);
7838 operands[3] = gen_int_mode (l, SImode);
7841 (define_insn "*movsf_hardfloat"
7842 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
7843 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
7844 "(gpc_reg_operand (operands[0], SFmode)
7845 || gpc_reg_operand (operands[1], SFmode))
7846 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7849 {l%U1%X1|lwz%U1%X1} %0,%1
7850 {st%U0%X0|stw%U0%X0} %1,%0
7860 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
7861 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
7863 (define_insn "*movsf_softfloat"
7864 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7865 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7866 "(gpc_reg_operand (operands[0], SFmode)
7867 || gpc_reg_operand (operands[1], SFmode))
7868 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7874 {l%U1%X1|lwz%U1%X1} %0,%1
7875 {st%U0%X0|stw%U0%X0} %1,%0
7882 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7883 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7886 (define_expand "movdf"
7887 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7888 (match_operand:DF 1 "any_operand" ""))]
7890 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7893 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7894 (match_operand:DF 1 "const_int_operand" ""))]
7895 "! TARGET_POWERPC64 && reload_completed
7896 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7897 || (GET_CODE (operands[0]) == SUBREG
7898 && GET_CODE (SUBREG_REG (operands[0])) == REG
7899 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7900 [(set (match_dup 2) (match_dup 4))
7901 (set (match_dup 3) (match_dup 1))]
7904 int endian = (WORDS_BIG_ENDIAN == 0);
7905 HOST_WIDE_INT value = INTVAL (operands[1]);
7907 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7908 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7909 #if HOST_BITS_PER_WIDE_INT == 32
7910 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7912 operands[4] = GEN_INT (value >> 32);
7913 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7918 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7919 (match_operand:DF 1 "const_double_operand" ""))]
7920 "! TARGET_POWERPC64 && reload_completed
7921 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7922 || (GET_CODE (operands[0]) == SUBREG
7923 && GET_CODE (SUBREG_REG (operands[0])) == REG
7924 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7925 [(set (match_dup 2) (match_dup 4))
7926 (set (match_dup 3) (match_dup 5))]
7929 int endian = (WORDS_BIG_ENDIAN == 0);
7933 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7934 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7936 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7937 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7938 operands[4] = gen_int_mode (l[endian], SImode);
7939 operands[5] = gen_int_mode (l[1 - endian], SImode);
7943 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7944 (match_operand:DF 1 "easy_fp_constant" ""))]
7945 "TARGET_POWERPC64 && reload_completed
7946 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7947 || (GET_CODE (operands[0]) == SUBREG
7948 && GET_CODE (SUBREG_REG (operands[0])) == REG
7949 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7950 [(set (match_dup 2) (match_dup 3))]
7953 int endian = (WORDS_BIG_ENDIAN == 0);
7956 #if HOST_BITS_PER_WIDE_INT >= 64
7960 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7961 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7963 operands[2] = gen_lowpart (DImode, operands[0]);
7964 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7965 #if HOST_BITS_PER_WIDE_INT >= 64
7966 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7967 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
7969 operands[3] = gen_int_mode (val, DImode);
7971 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7975 ;; Don't have reload use general registers to load a constant. First,
7976 ;; it might not work if the output operand is the equivalent of
7977 ;; a non-offsettable memref, but also it is less efficient than loading
7978 ;; the constant into an FP register, since it will probably be used there.
7979 ;; The "??" is a kludge until we can figure out a more reasonable way
7980 ;; of handling these non-offsettable values.
7981 (define_insn "*movdf_hardfloat32"
7982 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7983 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
7984 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
7985 && (gpc_reg_operand (operands[0], DFmode)
7986 || gpc_reg_operand (operands[1], DFmode))"
7989 switch (which_alternative)
7994 /* We normally copy the low-numbered register first. However, if
7995 the first register operand 0 is the same as the second register
7996 of operand 1, we must copy in the opposite order. */
7997 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7998 return \"mr %L0,%L1\;mr %0,%1\";
8000 return \"mr %0,%1\;mr %L0,%L1\";
8002 if (offsettable_memref_p (operands[1])
8003 || (GET_CODE (operands[1]) == MEM
8004 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8005 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8006 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8008 /* If the low-address word is used in the address, we must load
8009 it last. Otherwise, load it first. Note that we cannot have
8010 auto-increment in that case since the address register is
8011 known to be dead. */
8012 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8014 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8016 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8022 addreg = find_addr_reg (XEXP (operands[1], 0));
8023 if (refers_to_regno_p (REGNO (operands[0]),
8024 REGNO (operands[0]) + 1,
8027 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8028 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8029 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8030 return \"{lx|lwzx} %0,%1\";
8034 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8035 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8036 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8037 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8042 if (offsettable_memref_p (operands[0])
8043 || (GET_CODE (operands[0]) == MEM
8044 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8045 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8046 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8047 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8052 addreg = find_addr_reg (XEXP (operands[0], 0));
8053 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8054 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8055 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8056 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8060 return \"fmr %0,%1\";
8062 return \"lfd%U1%X1 %0,%1\";
8064 return \"stfd%U0%X0 %1,%0\";
8071 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
8072 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8074 (define_insn "*movdf_softfloat32"
8075 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8076 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8077 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8078 && (gpc_reg_operand (operands[0], DFmode)
8079 || gpc_reg_operand (operands[1], DFmode))"
8082 switch (which_alternative)
8087 /* We normally copy the low-numbered register first. However, if
8088 the first register operand 0 is the same as the second register of
8089 operand 1, we must copy in the opposite order. */
8090 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8091 return \"mr %L0,%L1\;mr %0,%1\";
8093 return \"mr %0,%1\;mr %L0,%L1\";
8095 /* If the low-address word is used in the address, we must load
8096 it last. Otherwise, load it first. Note that we cannot have
8097 auto-increment in that case since the address register is
8098 known to be dead. */
8099 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8101 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8103 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8105 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8112 [(set_attr "type" "*,load,store,*,*,*")
8113 (set_attr "length" "8,8,8,8,12,16")])
8115 ; ld/std require word-aligned displacements -> 'Y' constraint.
8116 ; List Y->r and r->Y before r->r for reload.
8117 (define_insn "*movdf_hardfloat64"
8118 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
8119 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8120 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8121 && (gpc_reg_operand (operands[0], DFmode)
8122 || gpc_reg_operand (operands[1], DFmode))"
8136 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
8137 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8139 (define_insn "*movdf_softfloat64"
8140 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8141 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8142 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8143 && (gpc_reg_operand (operands[0], DFmode)
8144 || gpc_reg_operand (operands[1], DFmode))"
8155 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8156 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8158 (define_expand "movtf"
8159 [(set (match_operand:TF 0 "general_operand" "")
8160 (match_operand:TF 1 "any_operand" ""))]
8161 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8162 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8163 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8165 ; It's important to list the o->f and f->o moves before f->f because
8166 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8167 ; which doesn't make progress.
8168 (define_insn_and_split "*movtf_internal"
8169 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r")
8170 (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))]
8171 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8172 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8173 && (gpc_reg_operand (operands[0], TFmode)
8174 || gpc_reg_operand (operands[1], TFmode))"
8176 "&& reload_completed"
8178 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8179 [(set_attr "length" "8,8,8,20,20")])
8181 (define_expand "extenddftf2"
8182 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8183 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8184 (use (match_dup 2))])]
8185 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8186 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8188 operands[2] = CONST0_RTX (DFmode);
8191 (define_insn_and_split "*extenddftf2_internal"
8192 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8193 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8194 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
8195 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8196 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8198 "&& reload_completed"
8201 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8202 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8203 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8205 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8210 (define_expand "extendsftf2"
8211 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8212 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8213 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8214 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8216 rtx tmp = gen_reg_rtx (DFmode);
8217 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8218 emit_insn (gen_extenddftf2 (operands[0], tmp));
8222 (define_expand "trunctfdf2"
8223 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8224 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8225 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8226 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8229 (define_insn_and_split "trunctfdf2_internal1"
8230 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8231 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8232 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
8233 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8237 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8240 emit_note (NOTE_INSN_DELETED);
8243 [(set_attr "type" "fp")])
8245 (define_insn "trunctfdf2_internal2"
8246 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8247 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8248 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
8249 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8251 [(set_attr "type" "fp")])
8253 (define_insn_and_split "trunctfsf2"
8254 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8255 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8256 (clobber (match_scratch:DF 2 "=f"))]
8257 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8258 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8260 "&& reload_completed"
8262 (float_truncate:DF (match_dup 1)))
8264 (float_truncate:SF (match_dup 2)))]
8267 (define_expand "floatsitf2"
8268 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8269 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8270 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8271 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8273 rtx tmp = gen_reg_rtx (DFmode);
8274 expand_float (tmp, operands[1], false);
8275 emit_insn (gen_extenddftf2 (operands[0], tmp));
8279 ; fadd, but rounding towards zero.
8280 ; This is probably not the optimal code sequence.
8281 (define_insn "fix_trunc_helper"
8282 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8283 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8284 UNSPEC_FIX_TRUNC_TF))
8285 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8286 "TARGET_HARD_FLOAT && TARGET_FPRS"
8287 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8288 [(set_attr "type" "fp")
8289 (set_attr "length" "20")])
8291 (define_expand "fix_trunctfsi2"
8292 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8293 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8294 (clobber (match_dup 2))
8295 (clobber (match_dup 3))
8296 (clobber (match_dup 4))
8297 (clobber (match_dup 5))])]
8298 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8299 && (TARGET_POWER2 || TARGET_POWERPC)
8300 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8302 operands[2] = gen_reg_rtx (DFmode);
8303 operands[3] = gen_reg_rtx (DFmode);
8304 operands[4] = gen_reg_rtx (DImode);
8305 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8308 (define_insn_and_split "*fix_trunctfsi2_internal"
8309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8310 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8311 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8312 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8313 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8314 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8315 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8316 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8318 "&& reload_completed"
8322 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8324 if (GET_CODE (operands[5]) != MEM)
8326 lowword = XEXP (operands[5], 0);
8327 if (WORDS_BIG_ENDIAN)
8328 lowword = plus_constant (lowword, 4);
8330 emit_insn (gen_fctiwz (operands[4], operands[2]));
8331 emit_move_insn (operands[5], operands[4]);
8332 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8336 (define_insn "negtf2"
8337 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8338 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8339 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8340 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8343 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8344 return \"fneg %L0,%L1\;fneg %0,%1\";
8346 return \"fneg %0,%1\;fneg %L0,%L1\";
8348 [(set_attr "type" "fp")
8349 (set_attr "length" "8")])
8351 (define_expand "abstf2"
8352 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8353 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8354 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8355 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8358 rtx label = gen_label_rtx ();
8359 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8364 (define_expand "abstf2_internal"
8365 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8366 (match_operand:TF 1 "gpc_reg_operand" "f"))
8367 (set (match_dup 3) (match_dup 5))
8368 (set (match_dup 5) (abs:DF (match_dup 5)))
8369 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8370 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8371 (label_ref (match_operand 2 "" ""))
8373 (set (match_dup 6) (neg:DF (match_dup 6)))]
8374 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8375 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8378 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8379 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8380 operands[3] = gen_reg_rtx (DFmode);
8381 operands[4] = gen_reg_rtx (CCFPmode);
8382 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8383 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8386 ;; Next come the multi-word integer load and store and the load and store
8388 (define_expand "movdi"
8389 [(set (match_operand:DI 0 "general_operand" "")
8390 (match_operand:DI 1 "any_operand" ""))]
8392 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8394 (define_insn "*movdi_internal32"
8395 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8396 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8398 && (gpc_reg_operand (operands[0], DImode)
8399 || gpc_reg_operand (operands[1], DImode))"
8402 switch (which_alternative)
8411 return \"fmr %0,%1\";
8413 return \"lfd%U1%X1 %0,%1\";
8415 return \"stfd%U0%X0 %1,%0\";
8424 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")])
8427 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8428 (match_operand:DI 1 "const_int_operand" ""))]
8429 "! TARGET_POWERPC64 && reload_completed"
8430 [(set (match_dup 2) (match_dup 4))
8431 (set (match_dup 3) (match_dup 1))]
8434 HOST_WIDE_INT value = INTVAL (operands[1]);
8435 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8437 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8439 #if HOST_BITS_PER_WIDE_INT == 32
8440 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8442 operands[4] = GEN_INT (value >> 32);
8443 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8448 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8449 (match_operand:DI 1 "input_operand" ""))]
8450 "reload_completed && !TARGET_POWERPC64
8451 && gpr_or_gpr_p (operands[0], operands[1])"
8453 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8456 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8457 (match_operand:TI 1 "const_double_operand" ""))]
8459 [(set (match_dup 2) (match_dup 4))
8460 (set (match_dup 3) (match_dup 5))]
8463 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8465 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8467 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8469 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8470 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8472 else if (GET_CODE (operands[1]) == CONST_INT)
8474 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8475 operands[5] = operands[1];
8481 (define_insn "*movdi_internal64"
8482 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,r,??f,f,m,r,*h,*h")
8483 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,R,f,m,f,*h,r,0"))]
8485 && (gpc_reg_operand (operands[0], DImode)
8486 || gpc_reg_operand (operands[1], DImode))"
8501 [(set_attr "type" "store,load,*,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8502 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8504 ;; immediate value valid for a single instruction hiding in a const_double
8506 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8507 (match_operand:DI 1 "const_double_operand" "F"))]
8508 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8509 && GET_CODE (operands[1]) == CONST_DOUBLE
8510 && num_insns_constant (operands[1], DImode) == 1"
8513 return ((unsigned HOST_WIDE_INT)
8514 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8515 ? \"li %0,%1\" : \"lis %0,%v1\";
8518 ;; Generate all one-bits and clear left or right.
8519 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8521 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8522 (match_operand:DI 1 "mask64_operand" ""))]
8523 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8524 [(set (match_dup 0) (const_int -1))
8526 (and:DI (rotate:DI (match_dup 0)
8531 ;; Split a load of a large constant into the appropriate five-instruction
8532 ;; sequence. Handle anything in a constant number of insns.
8533 ;; When non-easy constants can go in the TOC, this should use
8534 ;; easy_fp_constant predicate.
8536 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8537 (match_operand:DI 1 "const_int_operand" ""))]
8538 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8539 [(set (match_dup 0) (match_dup 2))
8540 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8542 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8544 if (tem == operands[0])
8551 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8552 (match_operand:DI 1 "const_double_operand" ""))]
8553 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8554 [(set (match_dup 0) (match_dup 2))
8555 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8557 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8559 if (tem == operands[0])
8565 (define_insn "*movdi_internal2"
8566 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8567 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8569 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8575 [(set_attr "type" "cmp,compare,cmp")
8576 (set_attr "length" "4,4,8")])
8579 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8580 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8582 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8583 "TARGET_POWERPC64 && reload_completed"
8584 [(set (match_dup 0) (match_dup 1))
8586 (compare:CC (match_dup 0)
8590 ;; TImode is similar, except that we usually want to compute the address into
8591 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8592 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8593 (define_expand "movti"
8594 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8595 (match_operand:TI 1 "general_operand" ""))
8596 (clobber (scratch:SI))])]
8598 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8600 ;; We say that MQ is clobbered in the last alternative because the first
8601 ;; alternative would never get used otherwise since it would need a reload
8602 ;; while the 2nd alternative would not. We put memory cases first so they
8603 ;; are preferred. Otherwise, we'd try to reload the output instead of
8604 ;; giving the SCRATCH mq.
8606 (define_insn "*movti_power"
8607 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8608 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8609 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8610 "TARGET_POWER && ! TARGET_POWERPC64
8611 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8614 switch (which_alternative)
8621 return \"{stsi|stswi} %1,%P0,16\";
8626 /* If the address is not used in the output, we can use lsi. Otherwise,
8627 fall through to generating four loads. */
8629 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8630 return \"{lsi|lswi} %0,%P1,16\";
8631 /* ... fall through ... */
8636 [(set_attr "type" "store,store,*,load,load")])
8638 (define_insn "*movti_string"
8639 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8640 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
8641 "! TARGET_POWER && ! TARGET_POWERPC64
8642 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8645 switch (which_alternative)
8651 return \"{stsi|stswi} %1,%P0,16\";
8656 /* If the address is not used in the output, we can use lsi. Otherwise,
8657 fall through to generating four loads. */
8659 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8660 return \"{lsi|lswi} %0,%P1,16\";
8661 /* ... fall through ... */
8666 [(set_attr "type" "store,store,*,load,load")])
8668 (define_insn "*movti_ppc64"
8669 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r")
8670 (match_operand:TI 1 "input_operand" "r,r,o"))]
8671 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8672 || gpc_reg_operand (operands[1], TImode))"
8677 [(set_attr "type" "*,load,store")])
8680 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8681 (match_operand:TI 1 "input_operand" ""))]
8683 && gpr_or_gpr_p (operands[0], operands[1])"
8685 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8687 (define_expand "load_multiple"
8688 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8689 (match_operand:SI 1 "" ""))
8690 (use (match_operand:SI 2 "" ""))])]
8691 "TARGET_STRING && !TARGET_POWERPC64"
8699 /* Support only loading a constant number of fixed-point registers from
8700 memory and only bother with this if more than two; the machine
8701 doesn't support more than eight. */
8702 if (GET_CODE (operands[2]) != CONST_INT
8703 || INTVAL (operands[2]) <= 2
8704 || INTVAL (operands[2]) > 8
8705 || GET_CODE (operands[1]) != MEM
8706 || GET_CODE (operands[0]) != REG
8707 || REGNO (operands[0]) >= 32)
8710 count = INTVAL (operands[2]);
8711 regno = REGNO (operands[0]);
8713 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8714 op1 = replace_equiv_address (operands[1],
8715 force_reg (SImode, XEXP (operands[1], 0)));
8717 for (i = 0; i < count; i++)
8718 XVECEXP (operands[3], 0, i)
8719 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8720 adjust_address_nv (op1, SImode, i * 4));
8723 (define_insn "*ldmsi8"
8724 [(match_parallel 0 "load_multiple_operation"
8725 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8726 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8727 (set (match_operand:SI 3 "gpc_reg_operand" "")
8728 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8729 (set (match_operand:SI 4 "gpc_reg_operand" "")
8730 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8731 (set (match_operand:SI 5 "gpc_reg_operand" "")
8732 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8733 (set (match_operand:SI 6 "gpc_reg_operand" "")
8734 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8735 (set (match_operand:SI 7 "gpc_reg_operand" "")
8736 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8737 (set (match_operand:SI 8 "gpc_reg_operand" "")
8738 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8739 (set (match_operand:SI 9 "gpc_reg_operand" "")
8740 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8741 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8743 { return rs6000_output_load_multiple (operands); }"
8744 [(set_attr "type" "load")
8745 (set_attr "length" "32")])
8747 (define_insn "*ldmsi7"
8748 [(match_parallel 0 "load_multiple_operation"
8749 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8750 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8751 (set (match_operand:SI 3 "gpc_reg_operand" "")
8752 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8753 (set (match_operand:SI 4 "gpc_reg_operand" "")
8754 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8755 (set (match_operand:SI 5 "gpc_reg_operand" "")
8756 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8757 (set (match_operand:SI 6 "gpc_reg_operand" "")
8758 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8759 (set (match_operand:SI 7 "gpc_reg_operand" "")
8760 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8761 (set (match_operand:SI 8 "gpc_reg_operand" "")
8762 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8763 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8765 { return rs6000_output_load_multiple (operands); }"
8766 [(set_attr "type" "load")
8767 (set_attr "length" "32")])
8769 (define_insn "*ldmsi6"
8770 [(match_parallel 0 "load_multiple_operation"
8771 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8772 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8773 (set (match_operand:SI 3 "gpc_reg_operand" "")
8774 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8775 (set (match_operand:SI 4 "gpc_reg_operand" "")
8776 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8777 (set (match_operand:SI 5 "gpc_reg_operand" "")
8778 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8779 (set (match_operand:SI 6 "gpc_reg_operand" "")
8780 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8781 (set (match_operand:SI 7 "gpc_reg_operand" "")
8782 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8783 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8785 { return rs6000_output_load_multiple (operands); }"
8786 [(set_attr "type" "load")
8787 (set_attr "length" "32")])
8789 (define_insn "*ldmsi5"
8790 [(match_parallel 0 "load_multiple_operation"
8791 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8792 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8793 (set (match_operand:SI 3 "gpc_reg_operand" "")
8794 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8795 (set (match_operand:SI 4 "gpc_reg_operand" "")
8796 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8797 (set (match_operand:SI 5 "gpc_reg_operand" "")
8798 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8799 (set (match_operand:SI 6 "gpc_reg_operand" "")
8800 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8801 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8803 { return rs6000_output_load_multiple (operands); }"
8804 [(set_attr "type" "load")
8805 (set_attr "length" "32")])
8807 (define_insn "*ldmsi4"
8808 [(match_parallel 0 "load_multiple_operation"
8809 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8810 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8811 (set (match_operand:SI 3 "gpc_reg_operand" "")
8812 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8813 (set (match_operand:SI 4 "gpc_reg_operand" "")
8814 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8815 (set (match_operand:SI 5 "gpc_reg_operand" "")
8816 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8817 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8819 { return rs6000_output_load_multiple (operands); }"
8820 [(set_attr "type" "load")
8821 (set_attr "length" "32")])
8823 (define_insn "*ldmsi3"
8824 [(match_parallel 0 "load_multiple_operation"
8825 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8826 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8827 (set (match_operand:SI 3 "gpc_reg_operand" "")
8828 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8829 (set (match_operand:SI 4 "gpc_reg_operand" "")
8830 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8831 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8833 { return rs6000_output_load_multiple (operands); }"
8834 [(set_attr "type" "load")
8835 (set_attr "length" "32")])
8837 (define_expand "store_multiple"
8838 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8839 (match_operand:SI 1 "" ""))
8840 (clobber (scratch:SI))
8841 (use (match_operand:SI 2 "" ""))])]
8842 "TARGET_STRING && !TARGET_POWERPC64"
8851 /* Support only storing a constant number of fixed-point registers to
8852 memory and only bother with this if more than two; the machine
8853 doesn't support more than eight. */
8854 if (GET_CODE (operands[2]) != CONST_INT
8855 || INTVAL (operands[2]) <= 2
8856 || INTVAL (operands[2]) > 8
8857 || GET_CODE (operands[0]) != MEM
8858 || GET_CODE (operands[1]) != REG
8859 || REGNO (operands[1]) >= 32)
8862 count = INTVAL (operands[2]);
8863 regno = REGNO (operands[1]);
8865 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8866 to = force_reg (SImode, XEXP (operands[0], 0));
8867 op0 = replace_equiv_address (operands[0], to);
8869 XVECEXP (operands[3], 0, 0)
8870 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8871 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8872 gen_rtx_SCRATCH (SImode));
8874 for (i = 1; i < count; i++)
8875 XVECEXP (operands[3], 0, i + 1)
8876 = gen_rtx_SET (VOIDmode,
8877 adjust_address_nv (op0, SImode, i * 4),
8878 gen_rtx_REG (SImode, regno + i));
8881 (define_insn "*store_multiple_power"
8882 [(match_parallel 0 "store_multiple_operation"
8883 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8884 (match_operand:SI 2 "gpc_reg_operand" "r"))
8885 (clobber (match_scratch:SI 3 "=q"))])]
8886 "TARGET_STRING && TARGET_POWER"
8887 "{stsi|stswi} %2,%P1,%O0"
8888 [(set_attr "type" "store")])
8890 (define_insn "*stmsi8"
8891 [(match_parallel 0 "store_multiple_operation"
8892 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8893 (match_operand:SI 2 "gpc_reg_operand" "r"))
8894 (clobber (match_scratch:SI 3 "X"))
8895 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8896 (match_operand:SI 4 "gpc_reg_operand" "r"))
8897 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8898 (match_operand:SI 5 "gpc_reg_operand" "r"))
8899 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8900 (match_operand:SI 6 "gpc_reg_operand" "r"))
8901 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8902 (match_operand:SI 7 "gpc_reg_operand" "r"))
8903 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8904 (match_operand:SI 8 "gpc_reg_operand" "r"))
8905 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8906 (match_operand:SI 9 "gpc_reg_operand" "r"))
8907 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8908 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8909 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8910 "{stsi|stswi} %2,%1,%O0"
8911 [(set_attr "type" "store")])
8913 (define_insn "*stmsi7"
8914 [(match_parallel 0 "store_multiple_operation"
8915 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8916 (match_operand:SI 2 "gpc_reg_operand" "r"))
8917 (clobber (match_scratch:SI 3 "X"))
8918 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8919 (match_operand:SI 4 "gpc_reg_operand" "r"))
8920 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8921 (match_operand:SI 5 "gpc_reg_operand" "r"))
8922 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8923 (match_operand:SI 6 "gpc_reg_operand" "r"))
8924 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8925 (match_operand:SI 7 "gpc_reg_operand" "r"))
8926 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8927 (match_operand:SI 8 "gpc_reg_operand" "r"))
8928 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8929 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8930 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8931 "{stsi|stswi} %2,%1,%O0"
8932 [(set_attr "type" "store")])
8934 (define_insn "*stmsi6"
8935 [(match_parallel 0 "store_multiple_operation"
8936 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8937 (match_operand:SI 2 "gpc_reg_operand" "r"))
8938 (clobber (match_scratch:SI 3 "X"))
8939 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8940 (match_operand:SI 4 "gpc_reg_operand" "r"))
8941 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8942 (match_operand:SI 5 "gpc_reg_operand" "r"))
8943 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8944 (match_operand:SI 6 "gpc_reg_operand" "r"))
8945 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8946 (match_operand:SI 7 "gpc_reg_operand" "r"))
8947 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8948 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8949 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8950 "{stsi|stswi} %2,%1,%O0"
8951 [(set_attr "type" "store")])
8953 (define_insn "*stmsi5"
8954 [(match_parallel 0 "store_multiple_operation"
8955 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8956 (match_operand:SI 2 "gpc_reg_operand" "r"))
8957 (clobber (match_scratch:SI 3 "X"))
8958 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8959 (match_operand:SI 4 "gpc_reg_operand" "r"))
8960 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8961 (match_operand:SI 5 "gpc_reg_operand" "r"))
8962 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8963 (match_operand:SI 6 "gpc_reg_operand" "r"))
8964 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8965 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8966 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8967 "{stsi|stswi} %2,%1,%O0"
8968 [(set_attr "type" "store")])
8970 (define_insn "*stmsi4"
8971 [(match_parallel 0 "store_multiple_operation"
8972 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8973 (match_operand:SI 2 "gpc_reg_operand" "r"))
8974 (clobber (match_scratch:SI 3 "X"))
8975 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8976 (match_operand:SI 4 "gpc_reg_operand" "r"))
8977 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8978 (match_operand:SI 5 "gpc_reg_operand" "r"))
8979 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8980 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8981 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
8982 "{stsi|stswi} %2,%1,%O0"
8983 [(set_attr "type" "store")])
8985 (define_insn "*stmsi3"
8986 [(match_parallel 0 "store_multiple_operation"
8987 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8988 (match_operand:SI 2 "gpc_reg_operand" "r"))
8989 (clobber (match_scratch:SI 3 "X"))
8990 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8991 (match_operand:SI 4 "gpc_reg_operand" "r"))
8992 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8993 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8994 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
8995 "{stsi|stswi} %2,%1,%O0"
8996 [(set_attr "type" "store")])
8998 ;; String/block move insn.
8999 ;; Argument 0 is the destination
9000 ;; Argument 1 is the source
9001 ;; Argument 2 is the length
9002 ;; Argument 3 is the alignment
9004 (define_expand "movstrsi"
9005 [(parallel [(set (match_operand:BLK 0 "" "")
9006 (match_operand:BLK 1 "" ""))
9007 (use (match_operand:SI 2 "" ""))
9008 (use (match_operand:SI 3 "" ""))])]
9012 if (expand_block_move (operands))
9018 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9019 ;; register allocator doesn't have a clue about allocating 8 word registers.
9020 ;; rD/rS = r5 is preferred, efficient form.
9021 (define_expand "movstrsi_8reg"
9022 [(parallel [(set (match_operand 0 "" "")
9023 (match_operand 1 "" ""))
9024 (use (match_operand 2 "" ""))
9025 (use (match_operand 3 "" ""))
9026 (clobber (reg:SI 5))
9027 (clobber (reg:SI 6))
9028 (clobber (reg:SI 7))
9029 (clobber (reg:SI 8))
9030 (clobber (reg:SI 9))
9031 (clobber (reg:SI 10))
9032 (clobber (reg:SI 11))
9033 (clobber (reg:SI 12))
9034 (clobber (match_scratch:SI 4 ""))])]
9039 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9040 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9041 (use (match_operand:SI 2 "immediate_operand" "i"))
9042 (use (match_operand:SI 3 "immediate_operand" "i"))
9043 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9044 (clobber (reg:SI 6))
9045 (clobber (reg:SI 7))
9046 (clobber (reg:SI 8))
9047 (clobber (reg:SI 9))
9048 (clobber (reg:SI 10))
9049 (clobber (reg:SI 11))
9050 (clobber (reg:SI 12))
9051 (clobber (match_scratch:SI 5 "=q"))]
9052 "TARGET_STRING && TARGET_POWER
9053 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9054 || INTVAL (operands[2]) == 0)
9055 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9056 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9057 && REGNO (operands[4]) == 5"
9058 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9059 [(set_attr "type" "load")
9060 (set_attr "length" "8")])
9063 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9064 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9065 (use (match_operand:SI 2 "immediate_operand" "i"))
9066 (use (match_operand:SI 3 "immediate_operand" "i"))
9067 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9068 (clobber (reg:SI 6))
9069 (clobber (reg:SI 7))
9070 (clobber (reg:SI 8))
9071 (clobber (reg:SI 9))
9072 (clobber (reg:SI 10))
9073 (clobber (reg:SI 11))
9074 (clobber (reg:SI 12))
9075 (clobber (match_scratch:SI 5 "X"))]
9076 "TARGET_STRING && ! TARGET_POWER
9077 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9078 || INTVAL (operands[2]) == 0)
9079 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9080 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9081 && REGNO (operands[4]) == 5"
9082 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9083 [(set_attr "type" "load")
9084 (set_attr "length" "8")])
9087 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9088 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9089 (use (match_operand:SI 2 "immediate_operand" "i"))
9090 (use (match_operand:SI 3 "immediate_operand" "i"))
9091 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9092 (clobber (reg:SI 6))
9093 (clobber (reg:SI 7))
9094 (clobber (reg:SI 8))
9095 (clobber (reg:SI 9))
9096 (clobber (reg:SI 10))
9097 (clobber (reg:SI 11))
9098 (clobber (reg:SI 12))
9099 (clobber (match_scratch:SI 5 "X"))]
9100 "TARGET_STRING && TARGET_POWERPC64
9101 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9102 || INTVAL (operands[2]) == 0)
9103 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9104 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9105 && REGNO (operands[4]) == 5"
9106 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9107 [(set_attr "type" "load")
9108 (set_attr "length" "8")])
9110 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9111 ;; register allocator doesn't have a clue about allocating 6 word registers.
9112 ;; rD/rS = r5 is preferred, efficient form.
9113 (define_expand "movstrsi_6reg"
9114 [(parallel [(set (match_operand 0 "" "")
9115 (match_operand 1 "" ""))
9116 (use (match_operand 2 "" ""))
9117 (use (match_operand 3 "" ""))
9118 (clobber (reg:SI 5))
9119 (clobber (reg:SI 6))
9120 (clobber (reg:SI 7))
9121 (clobber (reg:SI 8))
9122 (clobber (reg:SI 9))
9123 (clobber (reg:SI 10))
9124 (clobber (match_scratch:SI 4 ""))])]
9129 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9130 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9131 (use (match_operand:SI 2 "immediate_operand" "i"))
9132 (use (match_operand:SI 3 "immediate_operand" "i"))
9133 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9134 (clobber (reg:SI 6))
9135 (clobber (reg:SI 7))
9136 (clobber (reg:SI 8))
9137 (clobber (reg:SI 9))
9138 (clobber (reg:SI 10))
9139 (clobber (match_scratch:SI 5 "=q"))]
9140 "TARGET_STRING && TARGET_POWER
9141 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9142 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9143 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9144 && REGNO (operands[4]) == 5"
9145 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9146 [(set_attr "type" "load")
9147 (set_attr "length" "8")])
9150 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9151 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9152 (use (match_operand:SI 2 "immediate_operand" "i"))
9153 (use (match_operand:SI 3 "immediate_operand" "i"))
9154 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9155 (clobber (reg:SI 6))
9156 (clobber (reg:SI 7))
9157 (clobber (reg:SI 8))
9158 (clobber (reg:SI 9))
9159 (clobber (reg:SI 10))
9160 (clobber (match_scratch:SI 5 "X"))]
9161 "TARGET_STRING && ! TARGET_POWER
9162 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9163 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9164 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9165 && REGNO (operands[4]) == 5"
9166 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9167 [(set_attr "type" "load")
9168 (set_attr "length" "8")])
9171 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9172 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9173 (use (match_operand:SI 2 "immediate_operand" "i"))
9174 (use (match_operand:SI 3 "immediate_operand" "i"))
9175 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9176 (clobber (reg:SI 6))
9177 (clobber (reg:SI 7))
9178 (clobber (reg:SI 8))
9179 (clobber (reg:SI 9))
9180 (clobber (reg:SI 10))
9181 (clobber (match_scratch:SI 5 "X"))]
9182 "TARGET_STRING && TARGET_POWERPC64
9183 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9184 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9185 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9186 && REGNO (operands[4]) == 5"
9187 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9188 [(set_attr "type" "load")
9189 (set_attr "length" "8")])
9191 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9192 ;; problems with TImode.
9193 ;; rD/rS = r5 is preferred, efficient form.
9194 (define_expand "movstrsi_4reg"
9195 [(parallel [(set (match_operand 0 "" "")
9196 (match_operand 1 "" ""))
9197 (use (match_operand 2 "" ""))
9198 (use (match_operand 3 "" ""))
9199 (clobber (reg:SI 5))
9200 (clobber (reg:SI 6))
9201 (clobber (reg:SI 7))
9202 (clobber (reg:SI 8))
9203 (clobber (match_scratch:SI 4 ""))])]
9208 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9209 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9210 (use (match_operand:SI 2 "immediate_operand" "i"))
9211 (use (match_operand:SI 3 "immediate_operand" "i"))
9212 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9213 (clobber (reg:SI 6))
9214 (clobber (reg:SI 7))
9215 (clobber (reg:SI 8))
9216 (clobber (match_scratch:SI 5 "=q"))]
9217 "TARGET_STRING && TARGET_POWER
9218 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9219 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9220 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9221 && REGNO (operands[4]) == 5"
9222 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9223 [(set_attr "type" "load")
9224 (set_attr "length" "8")])
9227 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9228 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9229 (use (match_operand:SI 2 "immediate_operand" "i"))
9230 (use (match_operand:SI 3 "immediate_operand" "i"))
9231 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9232 (clobber (reg:SI 6))
9233 (clobber (reg:SI 7))
9234 (clobber (reg:SI 8))
9235 (clobber (match_scratch:SI 5 "X"))]
9236 "TARGET_STRING && ! TARGET_POWER
9237 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9238 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9239 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9240 && REGNO (operands[4]) == 5"
9241 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9242 [(set_attr "type" "load")
9243 (set_attr "length" "8")])
9246 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9247 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9248 (use (match_operand:SI 2 "immediate_operand" "i"))
9249 (use (match_operand:SI 3 "immediate_operand" "i"))
9250 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9251 (clobber (reg:SI 6))
9252 (clobber (reg:SI 7))
9253 (clobber (reg:SI 8))
9254 (clobber (match_scratch:SI 5 "X"))]
9255 "TARGET_STRING && TARGET_POWERPC64
9256 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9257 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9258 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9259 && REGNO (operands[4]) == 5"
9260 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9261 [(set_attr "type" "load")
9262 (set_attr "length" "8")])
9264 ;; Move up to 8 bytes at a time.
9265 (define_expand "movstrsi_2reg"
9266 [(parallel [(set (match_operand 0 "" "")
9267 (match_operand 1 "" ""))
9268 (use (match_operand 2 "" ""))
9269 (use (match_operand 3 "" ""))
9270 (clobber (match_scratch:DI 4 ""))
9271 (clobber (match_scratch:SI 5 ""))])]
9272 "TARGET_STRING && ! TARGET_POWERPC64"
9276 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9277 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9278 (use (match_operand:SI 2 "immediate_operand" "i"))
9279 (use (match_operand:SI 3 "immediate_operand" "i"))
9280 (clobber (match_scratch:DI 4 "=&r"))
9281 (clobber (match_scratch:SI 5 "=q"))]
9282 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9283 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9284 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9285 [(set_attr "type" "load")
9286 (set_attr "length" "8")])
9289 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9290 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9291 (use (match_operand:SI 2 "immediate_operand" "i"))
9292 (use (match_operand:SI 3 "immediate_operand" "i"))
9293 (clobber (match_scratch:DI 4 "=&r"))
9294 (clobber (match_scratch:SI 5 "X"))]
9295 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9296 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9297 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9298 [(set_attr "type" "load")
9299 (set_attr "length" "8")])
9301 ;; Move up to 4 bytes at a time.
9302 (define_expand "movstrsi_1reg"
9303 [(parallel [(set (match_operand 0 "" "")
9304 (match_operand 1 "" ""))
9305 (use (match_operand 2 "" ""))
9306 (use (match_operand 3 "" ""))
9307 (clobber (match_scratch:SI 4 ""))
9308 (clobber (match_scratch:SI 5 ""))])]
9313 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9314 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9315 (use (match_operand:SI 2 "immediate_operand" "i"))
9316 (use (match_operand:SI 3 "immediate_operand" "i"))
9317 (clobber (match_scratch:SI 4 "=&r"))
9318 (clobber (match_scratch:SI 5 "=q"))]
9319 "TARGET_STRING && TARGET_POWER
9320 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9321 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9322 [(set_attr "type" "load")
9323 (set_attr "length" "8")])
9326 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9327 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9328 (use (match_operand:SI 2 "immediate_operand" "i"))
9329 (use (match_operand:SI 3 "immediate_operand" "i"))
9330 (clobber (match_scratch:SI 4 "=&r"))
9331 (clobber (match_scratch:SI 5 "X"))]
9332 "TARGET_STRING && ! TARGET_POWER
9333 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9334 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9335 [(set_attr "type" "load")
9336 (set_attr "length" "8")])
9339 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9340 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9341 (use (match_operand:SI 2 "immediate_operand" "i"))
9342 (use (match_operand:SI 3 "immediate_operand" "i"))
9343 (clobber (match_scratch:SI 4 "=&r"))
9344 (clobber (match_scratch:SI 5 "X"))]
9345 "TARGET_STRING && TARGET_POWERPC64
9346 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9347 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9348 [(set_attr "type" "load")
9349 (set_attr "length" "8")])
9352 ;; Define insns that do load or store with update. Some of these we can
9353 ;; get by using pre-decrement or pre-increment, but the hardware can also
9354 ;; do cases where the increment is not the size of the object.
9356 ;; In all these cases, we use operands 0 and 1 for the register being
9357 ;; incremented because those are the operands that local-alloc will
9358 ;; tie and these are the pair most likely to be tieable (and the ones
9359 ;; that will benefit the most).
9361 (define_insn "*movdi_update1"
9362 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9363 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9364 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9365 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9366 (plus:DI (match_dup 1) (match_dup 2)))]
9367 "TARGET_POWERPC64 && TARGET_UPDATE"
9371 [(set_attr "type" "load_ux,load_u")])
9373 (define_insn "movdi_update"
9374 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9375 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
9376 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9377 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9378 (plus:DI (match_dup 1) (match_dup 2)))]
9379 "TARGET_POWERPC64 && TARGET_UPDATE"
9383 [(set_attr "type" "store_ux,store_u")])
9385 (define_insn "*movsi_update1"
9386 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9387 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9388 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9389 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9390 (plus:SI (match_dup 1) (match_dup 2)))]
9393 {lux|lwzux} %3,%0,%2
9394 {lu|lwzu} %3,%2(%0)"
9395 [(set_attr "type" "load_ux,load_u")])
9397 (define_insn "*movsi_update2"
9398 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9400 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9401 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9402 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9403 (plus:DI (match_dup 1) (match_dup 2)))]
9406 [(set_attr "type" "load_ext_ux")])
9408 (define_insn "movsi_update"
9409 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9410 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9411 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9412 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9413 (plus:SI (match_dup 1) (match_dup 2)))]
9416 {stux|stwux} %3,%0,%2
9417 {stu|stwu} %3,%2(%0)"
9418 [(set_attr "type" "store_ux,store_u")])
9420 (define_insn "*movhi_update1"
9421 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9422 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9423 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9424 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9425 (plus:SI (match_dup 1) (match_dup 2)))]
9430 [(set_attr "type" "load_ux,load_u")])
9432 (define_insn "*movhi_update2"
9433 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9435 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9436 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9437 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9438 (plus:SI (match_dup 1) (match_dup 2)))]
9443 [(set_attr "type" "load_ux,load_u")])
9445 (define_insn "*movhi_update3"
9446 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9448 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9449 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9450 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9451 (plus:SI (match_dup 1) (match_dup 2)))]
9456 [(set_attr "type" "load_ext_ux,load_ext_u")])
9458 (define_insn "*movhi_update4"
9459 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9460 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9461 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9462 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9463 (plus:SI (match_dup 1) (match_dup 2)))]
9468 [(set_attr "type" "store_ux,store_u")])
9470 (define_insn "*movqi_update1"
9471 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9472 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9473 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9474 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9475 (plus:SI (match_dup 1) (match_dup 2)))]
9480 [(set_attr "type" "load_ux,load_u")])
9482 (define_insn "*movqi_update2"
9483 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9485 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9486 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9487 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9488 (plus:SI (match_dup 1) (match_dup 2)))]
9493 [(set_attr "type" "load_ux,load_u")])
9495 (define_insn "*movqi_update3"
9496 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9497 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9498 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9499 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9500 (plus:SI (match_dup 1) (match_dup 2)))]
9505 [(set_attr "type" "store_ux,store_u")])
9507 (define_insn "*movsf_update1"
9508 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9509 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9510 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9511 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9512 (plus:SI (match_dup 1) (match_dup 2)))]
9513 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9517 [(set_attr "type" "fpload_ux,fpload_u")])
9519 (define_insn "*movsf_update2"
9520 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9521 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9522 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9523 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9524 (plus:SI (match_dup 1) (match_dup 2)))]
9525 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9529 [(set_attr "type" "fpstore_ux,fpstore_u")])
9531 (define_insn "*movsf_update3"
9532 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9533 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9534 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9535 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9536 (plus:SI (match_dup 1) (match_dup 2)))]
9537 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9539 {lux|lwzux} %3,%0,%2
9540 {lu|lwzu} %3,%2(%0)"
9541 [(set_attr "type" "load_ux,load_u")])
9543 (define_insn "*movsf_update4"
9544 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9545 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9546 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9547 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9548 (plus:SI (match_dup 1) (match_dup 2)))]
9549 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9551 {stux|stwux} %3,%0,%2
9552 {stu|stwu} %3,%2(%0)"
9553 [(set_attr "type" "store_ux,store_u")])
9555 (define_insn "*movdf_update1"
9556 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9557 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9558 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9559 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9560 (plus:SI (match_dup 1) (match_dup 2)))]
9561 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9565 [(set_attr "type" "fpload_ux,fpload_u")])
9567 (define_insn "*movdf_update2"
9568 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9569 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9570 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9571 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9572 (plus:SI (match_dup 1) (match_dup 2)))]
9573 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9577 [(set_attr "type" "fpstore_ux,fpstore_u")])
9579 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9582 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9583 (match_operand:DF 1 "memory_operand" ""))
9584 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9585 (match_operand:DF 3 "memory_operand" ""))]
9587 && TARGET_HARD_FLOAT && TARGET_FPRS
9588 && registers_ok_for_quad_peep (operands[0], operands[2])
9589 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9590 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9594 [(set (match_operand:DF 0 "memory_operand" "")
9595 (match_operand:DF 1 "gpc_reg_operand" "f"))
9596 (set (match_operand:DF 2 "memory_operand" "")
9597 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9599 && TARGET_HARD_FLOAT && TARGET_FPRS
9600 && registers_ok_for_quad_peep (operands[1], operands[3])
9601 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9602 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9607 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9608 (define_insn "tls_gd_32"
9609 [(set (match_operand:SI 0 "register_operand" "=b")
9610 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9611 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9613 "HAVE_AS_TLS && !TARGET_64BIT"
9614 "addi %0,%1,%2@got@tlsgd")
9616 (define_insn "tls_gd_64"
9617 [(set (match_operand:DI 0 "register_operand" "=b")
9618 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9619 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9621 "HAVE_AS_TLS && TARGET_64BIT"
9622 "addi %0,%1,%2@got@tlsgd")
9624 (define_insn "tls_ld_32"
9625 [(set (match_operand:SI 0 "register_operand" "=b")
9626 (unspec:SI [(match_operand:SI 1 "register_operand" "b")]
9628 "HAVE_AS_TLS && !TARGET_64BIT"
9629 "addi %0,%1,%&@got@tlsld")
9631 (define_insn "tls_ld_64"
9632 [(set (match_operand:DI 0 "register_operand" "=b")
9633 (unspec:DI [(match_operand:DI 1 "register_operand" "b")]
9635 "HAVE_AS_TLS && TARGET_64BIT"
9636 "addi %0,%1,%&@got@tlsld")
9638 (define_insn "tls_dtprel_32"
9639 [(set (match_operand:SI 0 "register_operand" "=r")
9640 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9641 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9643 "HAVE_AS_TLS && !TARGET_64BIT"
9644 "addi %0,%1,%2@dtprel")
9646 (define_insn "tls_dtprel_64"
9647 [(set (match_operand:DI 0 "register_operand" "=r")
9648 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9649 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9651 "HAVE_AS_TLS && TARGET_64BIT"
9652 "addi %0,%1,%2@dtprel")
9654 (define_insn "tls_dtprel_ha_32"
9655 [(set (match_operand:SI 0 "register_operand" "=r")
9656 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9657 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9658 UNSPEC_TLSDTPRELHA))]
9659 "HAVE_AS_TLS && !TARGET_64BIT"
9660 "addis %0,%1,%2@dtprel@ha")
9662 (define_insn "tls_dtprel_ha_64"
9663 [(set (match_operand:DI 0 "register_operand" "=r")
9664 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9665 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9666 UNSPEC_TLSDTPRELHA))]
9667 "HAVE_AS_TLS && TARGET_64BIT"
9668 "addis %0,%1,%2@dtprel@ha")
9670 (define_insn "tls_dtprel_lo_32"
9671 [(set (match_operand:SI 0 "register_operand" "=r")
9672 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9673 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9674 UNSPEC_TLSDTPRELLO))]
9675 "HAVE_AS_TLS && !TARGET_64BIT"
9676 "addi %0,%1,%2@dtprel@l")
9678 (define_insn "tls_dtprel_lo_64"
9679 [(set (match_operand:DI 0 "register_operand" "=r")
9680 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9681 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9682 UNSPEC_TLSDTPRELLO))]
9683 "HAVE_AS_TLS && TARGET_64BIT"
9684 "addi %0,%1,%2@dtprel@l")
9686 (define_insn "tls_got_dtprel_32"
9687 [(set (match_operand:SI 0 "register_operand" "=r")
9688 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9689 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9690 UNSPEC_TLSGOTDTPREL))]
9691 "HAVE_AS_TLS && !TARGET_64BIT"
9692 "lwz %0,%2@got@dtprel(%1)")
9694 (define_insn "tls_got_dtprel_64"
9695 [(set (match_operand:DI 0 "register_operand" "=r")
9696 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9697 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9698 UNSPEC_TLSGOTDTPREL))]
9699 "HAVE_AS_TLS && TARGET_64BIT"
9700 "ld %0,%2@got@dtprel(%1)")
9702 (define_insn "tls_tprel_32"
9703 [(set (match_operand:SI 0 "register_operand" "=r")
9704 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9705 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9707 "HAVE_AS_TLS && !TARGET_64BIT"
9708 "addi %0,%1,%2@tprel")
9710 (define_insn "tls_tprel_64"
9711 [(set (match_operand:DI 0 "register_operand" "=r")
9712 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9713 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9715 "HAVE_AS_TLS && TARGET_64BIT"
9716 "addi %0,%1,%2@tprel")
9718 (define_insn "tls_tprel_ha_32"
9719 [(set (match_operand:SI 0 "register_operand" "=r")
9720 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9721 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9722 UNSPEC_TLSTPRELHA))]
9723 "HAVE_AS_TLS && !TARGET_64BIT"
9724 "addis %0,%1,%2@tprel@ha")
9726 (define_insn "tls_tprel_ha_64"
9727 [(set (match_operand:DI 0 "register_operand" "=r")
9728 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9729 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9730 UNSPEC_TLSTPRELHA))]
9731 "HAVE_AS_TLS && TARGET_64BIT"
9732 "addis %0,%1,%2@tprel@ha")
9734 (define_insn "tls_tprel_lo_32"
9735 [(set (match_operand:SI 0 "register_operand" "=r")
9736 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9737 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9738 UNSPEC_TLSTPRELLO))]
9739 "HAVE_AS_TLS && !TARGET_64BIT"
9740 "addi %0,%1,%2@tprel@l")
9742 (define_insn "tls_tprel_lo_64"
9743 [(set (match_operand:DI 0 "register_operand" "=r")
9744 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9745 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9746 UNSPEC_TLSTPRELLO))]
9747 "HAVE_AS_TLS && TARGET_64BIT"
9748 "addi %0,%1,%2@tprel@l")
9750 ;; "b" output constraint here and on tls_tls input to support linker tls
9751 ;; optimization. The linker may edit the instructions emitted by a
9752 ;; tls_got_tprel/tls_tls pair to addis,addi.
9753 (define_insn "tls_got_tprel_32"
9754 [(set (match_operand:SI 0 "register_operand" "=b")
9755 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9756 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9757 UNSPEC_TLSGOTTPREL))]
9758 "HAVE_AS_TLS && !TARGET_64BIT"
9759 "lwz %0,%2@got@tprel(%1)")
9761 (define_insn "tls_got_tprel_64"
9762 [(set (match_operand:DI 0 "register_operand" "=b")
9763 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9764 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9765 UNSPEC_TLSGOTTPREL))]
9766 "HAVE_AS_TLS && TARGET_64BIT"
9767 "ld %0,%2@got@tprel(%1)")
9769 (define_insn "tls_tls_32"
9770 [(set (match_operand:SI 0 "register_operand" "=r")
9771 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9772 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9774 "HAVE_AS_TLS && !TARGET_64BIT"
9777 (define_insn "tls_tls_64"
9778 [(set (match_operand:DI 0 "register_operand" "=r")
9779 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9780 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9782 "HAVE_AS_TLS && TARGET_64BIT"
9785 ;; Next come insns related to the calling sequence.
9787 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9788 ;; We move the back-chain and decrement the stack pointer.
9790 (define_expand "allocate_stack"
9791 [(set (match_operand 0 "gpc_reg_operand" "=r")
9792 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9794 (minus (reg 1) (match_dup 1)))]
9797 { rtx chain = gen_reg_rtx (Pmode);
9798 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9801 emit_move_insn (chain, stack_bot);
9803 /* Check stack bounds if necessary. */
9804 if (current_function_limit_stack)
9807 available = expand_binop (Pmode, sub_optab,
9808 stack_pointer_rtx, stack_limit_rtx,
9809 NULL_RTX, 1, OPTAB_WIDEN);
9810 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9813 if (GET_CODE (operands[1]) != CONST_INT
9814 || INTVAL (operands[1]) < -32767
9815 || INTVAL (operands[1]) > 32768)
9817 neg_op0 = gen_reg_rtx (Pmode);
9819 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9821 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9824 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9827 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9828 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9832 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9833 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9834 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9837 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9841 ;; These patterns say how to save and restore the stack pointer. We need not
9842 ;; save the stack pointer at function level since we are careful to
9843 ;; preserve the backchain. At block level, we have to restore the backchain
9844 ;; when we restore the stack pointer.
9846 ;; For nonlocal gotos, we must save both the stack pointer and its
9847 ;; backchain and restore both. Note that in the nonlocal case, the
9848 ;; save area is a memory location.
9850 (define_expand "save_stack_function"
9851 [(match_operand 0 "any_operand" "")
9852 (match_operand 1 "any_operand" "")]
9856 (define_expand "restore_stack_function"
9857 [(match_operand 0 "any_operand" "")
9858 (match_operand 1 "any_operand" "")]
9862 (define_expand "restore_stack_block"
9863 [(use (match_operand 0 "register_operand" ""))
9864 (set (match_dup 2) (match_dup 3))
9865 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9866 (set (match_dup 3) (match_dup 2))]
9870 operands[2] = gen_reg_rtx (Pmode);
9871 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9874 (define_expand "save_stack_nonlocal"
9875 [(match_operand 0 "memory_operand" "")
9876 (match_operand 1 "register_operand" "")]
9880 rtx temp = gen_reg_rtx (Pmode);
9882 /* Copy the backchain to the first word, sp to the second. */
9883 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9884 emit_move_insn (operand_subword (operands[0], 0, 0,
9885 (TARGET_32BIT ? DImode : TImode)),
9887 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
9892 (define_expand "restore_stack_nonlocal"
9893 [(match_operand 0 "register_operand" "")
9894 (match_operand 1 "memory_operand" "")]
9898 rtx temp = gen_reg_rtx (Pmode);
9900 /* Restore the backchain from the first word, sp from the second. */
9901 emit_move_insn (temp,
9902 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
9903 emit_move_insn (operands[0],
9904 operand_subword (operands[1], 1, 0,
9905 (TARGET_32BIT ? DImode : TImode)));
9906 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9910 ;; TOC register handling.
9912 ;; Code to initialize the TOC register...
9914 (define_insn "load_toc_aix_si"
9915 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9916 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9918 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9922 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9923 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9924 operands[2] = gen_rtx_REG (Pmode, 2);
9925 return \"{l|lwz} %0,%1(%2)\";
9927 [(set_attr "type" "load")])
9929 (define_insn "load_toc_aix_di"
9930 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9931 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9933 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9937 #ifdef TARGET_RELOCATABLE
9938 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9939 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9941 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9944 strcat (buf, \"@toc\");
9945 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9946 operands[2] = gen_rtx_REG (Pmode, 2);
9947 return \"ld %0,%1(%2)\";
9949 [(set_attr "type" "load")])
9951 (define_insn "load_toc_v4_pic_si"
9952 [(set (match_operand:SI 0 "register_operand" "=l")
9953 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9954 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9955 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9956 [(set_attr "type" "branch")
9957 (set_attr "length" "4")])
9959 (define_insn "load_toc_v4_PIC_1"
9960 [(set (match_operand:SI 0 "register_operand" "=l")
9961 (match_operand:SI 1 "immediate_operand" "s"))
9962 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
9963 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9964 "bcl 20,31,%1\\n%1:"
9965 [(set_attr "type" "branch")
9966 (set_attr "length" "4")])
9968 (define_insn "load_toc_v4_PIC_1b"
9969 [(set (match_operand:SI 0 "register_operand" "=l")
9970 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9972 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9973 "bcl 20,31,$+8\\n\\t.long %1-$"
9974 [(set_attr "type" "branch")
9975 (set_attr "length" "8")])
9977 (define_insn "load_toc_v4_PIC_2"
9978 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9979 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9980 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9981 (match_operand:SI 3 "immediate_operand" "s")))))]
9982 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9983 "{l|lwz} %0,%2-%3(%1)"
9984 [(set_attr "type" "load")])
9986 (define_insn "load_macho_picbase"
9987 [(set (match_operand:SI 0 "register_operand" "=l")
9988 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
9990 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
9991 "bcl 20,31,%1\\n%1:"
9992 [(set_attr "type" "branch")
9993 (set_attr "length" "4")])
9995 (define_insn "macho_correct_pic"
9996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9997 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
9998 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
9999 (match_operand:SI 3 "immediate_operand" "s")]
10000 UNSPEC_MPIC_CORRECT)))]
10001 "DEFAULT_ABI == ABI_DARWIN"
10002 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
10003 [(set_attr "length" "8")])
10005 ;; If the TOC is shared over a translation unit, as happens with all
10006 ;; the kinds of PIC that we support, we need to restore the TOC
10007 ;; pointer only when jumping over units of translation.
10008 ;; On Darwin, we need to reload the picbase.
10010 (define_expand "builtin_setjmp_receiver"
10011 [(use (label_ref (match_operand 0 "" "")))]
10012 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10013 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10014 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10018 if (DEFAULT_ABI == ABI_DARWIN)
10020 const char *picbase = machopic_function_base_name ();
10021 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10022 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10026 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10027 CODE_LABEL_NUMBER (operands[0]));
10028 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10030 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10031 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10035 rs6000_emit_load_toc_table (FALSE);
10039 ;; A function pointer under AIX is a pointer to a data area whose first word
10040 ;; contains the actual address of the function, whose second word contains a
10041 ;; pointer to its TOC, and whose third word contains a value to place in the
10042 ;; static chain register (r11). Note that if we load the static chain, our
10043 ;; "trampoline" need not have any executable code.
10045 (define_expand "call_indirect_aix32"
10046 [(set (match_dup 2)
10047 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10048 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10051 (mem:SI (plus:SI (match_dup 0)
10054 (mem:SI (plus:SI (match_dup 0)
10056 (parallel [(call (mem:SI (match_dup 2))
10057 (match_operand 1 "" ""))
10061 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10062 (clobber (scratch:SI))])]
10065 { operands[2] = gen_reg_rtx (SImode); }")
10067 (define_expand "call_indirect_aix64"
10068 [(set (match_dup 2)
10069 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10070 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10073 (mem:DI (plus:DI (match_dup 0)
10076 (mem:DI (plus:DI (match_dup 0)
10078 (parallel [(call (mem:SI (match_dup 2))
10079 (match_operand 1 "" ""))
10083 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10084 (clobber (scratch:SI))])]
10087 { operands[2] = gen_reg_rtx (DImode); }")
10089 (define_expand "call_value_indirect_aix32"
10090 [(set (match_dup 3)
10091 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10092 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10095 (mem:SI (plus:SI (match_dup 1)
10098 (mem:SI (plus:SI (match_dup 1)
10100 (parallel [(set (match_operand 0 "" "")
10101 (call (mem:SI (match_dup 3))
10102 (match_operand 2 "" "")))
10106 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10107 (clobber (scratch:SI))])]
10110 { operands[3] = gen_reg_rtx (SImode); }")
10112 (define_expand "call_value_indirect_aix64"
10113 [(set (match_dup 3)
10114 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10115 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10118 (mem:DI (plus:DI (match_dup 1)
10121 (mem:DI (plus:DI (match_dup 1)
10123 (parallel [(set (match_operand 0 "" "")
10124 (call (mem:SI (match_dup 3))
10125 (match_operand 2 "" "")))
10129 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10130 (clobber (scratch:SI))])]
10133 { operands[3] = gen_reg_rtx (DImode); }")
10135 ;; Now the definitions for the call and call_value insns
10136 (define_expand "call"
10137 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10138 (match_operand 1 "" ""))
10139 (use (match_operand 2 "" ""))
10140 (clobber (scratch:SI))])]
10145 if (MACHOPIC_INDIRECT)
10146 operands[0] = machopic_indirect_call_target (operands[0]);
10149 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10152 operands[0] = XEXP (operands[0], 0);
10154 if (GET_CODE (operands[0]) != SYMBOL_REF
10155 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10156 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10158 if (INTVAL (operands[2]) & CALL_LONG)
10159 operands[0] = rs6000_longcall_ref (operands[0]);
10161 if (DEFAULT_ABI == ABI_V4
10162 || DEFAULT_ABI == ABI_DARWIN)
10163 operands[0] = force_reg (Pmode, operands[0]);
10165 else if (DEFAULT_ABI == ABI_AIX)
10167 /* AIX function pointers are really pointers to a three word
10169 emit_call_insn (TARGET_32BIT
10170 ? gen_call_indirect_aix32 (force_reg (SImode,
10173 : gen_call_indirect_aix64 (force_reg (DImode,
10183 (define_expand "call_value"
10184 [(parallel [(set (match_operand 0 "" "")
10185 (call (mem:SI (match_operand 1 "address_operand" ""))
10186 (match_operand 2 "" "")))
10187 (use (match_operand 3 "" ""))
10188 (clobber (scratch:SI))])]
10193 if (MACHOPIC_INDIRECT)
10194 operands[1] = machopic_indirect_call_target (operands[1]);
10197 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10200 operands[1] = XEXP (operands[1], 0);
10202 if (GET_CODE (operands[1]) != SYMBOL_REF
10203 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10204 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10206 if (INTVAL (operands[3]) & CALL_LONG)
10207 operands[1] = rs6000_longcall_ref (operands[1]);
10209 if (DEFAULT_ABI == ABI_V4
10210 || DEFAULT_ABI == ABI_DARWIN)
10211 operands[1] = force_reg (Pmode, operands[1]);
10213 else if (DEFAULT_ABI == ABI_AIX)
10215 /* AIX function pointers are really pointers to a three word
10217 emit_call_insn (TARGET_32BIT
10218 ? gen_call_value_indirect_aix32 (operands[0],
10222 : gen_call_value_indirect_aix64 (operands[0],
10233 ;; Call to function in current module. No TOC pointer reload needed.
10234 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10235 ;; either the function was not prototyped, or it was prototyped as a
10236 ;; variable argument function. It is > 0 if FP registers were passed
10237 ;; and < 0 if they were not.
10239 (define_insn "*call_local32"
10240 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10241 (match_operand 1 "" "g,g"))
10242 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10243 (clobber (match_scratch:SI 3 "=l,l"))]
10244 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10247 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10248 output_asm_insn (\"crxor 6,6,6\", operands);
10250 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10251 output_asm_insn (\"creqv 6,6,6\", operands);
10253 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10255 [(set_attr "type" "branch")
10256 (set_attr "length" "4,8")])
10258 (define_insn "*call_local64"
10259 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10260 (match_operand 1 "" "g,g"))
10261 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10262 (clobber (match_scratch:SI 3 "=l,l"))]
10263 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10266 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10267 output_asm_insn (\"crxor 6,6,6\", operands);
10269 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10270 output_asm_insn (\"creqv 6,6,6\", operands);
10272 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10274 [(set_attr "type" "branch")
10275 (set_attr "length" "4,8")])
10277 (define_insn "*call_value_local32"
10278 [(set (match_operand 0 "" "")
10279 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10280 (match_operand 2 "" "g,g")))
10281 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10282 (clobber (match_scratch:SI 4 "=l,l"))]
10283 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10286 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10287 output_asm_insn (\"crxor 6,6,6\", operands);
10289 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10290 output_asm_insn (\"creqv 6,6,6\", operands);
10292 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10294 [(set_attr "type" "branch")
10295 (set_attr "length" "4,8")])
10298 (define_insn "*call_value_local64"
10299 [(set (match_operand 0 "" "")
10300 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10301 (match_operand 2 "" "g,g")))
10302 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10303 (clobber (match_scratch:SI 4 "=l,l"))]
10304 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10307 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10308 output_asm_insn (\"crxor 6,6,6\", operands);
10310 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10311 output_asm_insn (\"creqv 6,6,6\", operands);
10313 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10315 [(set_attr "type" "branch")
10316 (set_attr "length" "4,8")])
10318 ;; Call to function which may be in another module. Restore the TOC
10319 ;; pointer (r2) after the call unless this is System V.
10320 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10321 ;; either the function was not prototyped, or it was prototyped as a
10322 ;; variable argument function. It is > 0 if FP registers were passed
10323 ;; and < 0 if they were not.
10325 (define_insn "*call_indirect_nonlocal_aix32"
10326 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10327 (match_operand 1 "" "g"))
10331 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10332 (clobber (match_scratch:SI 2 "=l"))]
10333 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10334 "b%T0l\;{l|lwz} 2,20(1)"
10335 [(set_attr "type" "jmpreg")
10336 (set_attr "length" "8")])
10338 (define_insn "*call_nonlocal_aix32"
10339 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10340 (match_operand 1 "" "g"))
10341 (use (match_operand:SI 2 "immediate_operand" "O"))
10342 (clobber (match_scratch:SI 3 "=l"))]
10344 && DEFAULT_ABI == ABI_AIX
10345 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10347 [(set_attr "type" "branch")
10348 (set_attr "length" "8")])
10350 (define_insn "*call_indirect_nonlocal_aix64"
10351 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10352 (match_operand 1 "" "g"))
10356 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10357 (clobber (match_scratch:SI 2 "=l"))]
10358 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10359 "b%T0l\;ld 2,40(1)"
10360 [(set_attr "type" "jmpreg")
10361 (set_attr "length" "8")])
10363 (define_insn "*call_nonlocal_aix64"
10364 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10365 (match_operand 1 "" "g"))
10366 (use (match_operand:SI 2 "immediate_operand" "O"))
10367 (clobber (match_scratch:SI 3 "=l"))]
10369 && DEFAULT_ABI == ABI_AIX
10370 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10372 [(set_attr "type" "branch")
10373 (set_attr "length" "8")])
10375 (define_insn "*call_value_indirect_nonlocal_aix32"
10376 [(set (match_operand 0 "" "")
10377 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10378 (match_operand 2 "" "g")))
10382 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10383 (clobber (match_scratch:SI 3 "=l"))]
10384 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10385 "b%T1l\;{l|lwz} 2,20(1)"
10386 [(set_attr "type" "jmpreg")
10387 (set_attr "length" "8")])
10389 (define_insn "*call_value_nonlocal_aix32"
10390 [(set (match_operand 0 "" "")
10391 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10392 (match_operand 2 "" "g")))
10393 (use (match_operand:SI 3 "immediate_operand" "O"))
10394 (clobber (match_scratch:SI 4 "=l"))]
10396 && DEFAULT_ABI == ABI_AIX
10397 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10399 [(set_attr "type" "branch")
10400 (set_attr "length" "8")])
10402 (define_insn "*call_value_indirect_nonlocal_aix64"
10403 [(set (match_operand 0 "" "")
10404 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10405 (match_operand 2 "" "g")))
10409 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10410 (clobber (match_scratch:SI 3 "=l"))]
10411 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10412 "b%T1l\;ld 2,40(1)"
10413 [(set_attr "type" "jmpreg")
10414 (set_attr "length" "8")])
10416 (define_insn "*call_value_nonlocal_aix64"
10417 [(set (match_operand 0 "" "")
10418 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10419 (match_operand 2 "" "g")))
10420 (use (match_operand:SI 3 "immediate_operand" "O"))
10421 (clobber (match_scratch:SI 4 "=l"))]
10423 && DEFAULT_ABI == ABI_AIX
10424 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10426 [(set_attr "type" "branch")
10427 (set_attr "length" "8")])
10429 ;; A function pointer under System V is just a normal pointer
10430 ;; operands[0] is the function pointer
10431 ;; operands[1] is the stack size to clean up
10432 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10433 ;; which indicates how to set cr1
10435 (define_insn "*call_indirect_nonlocal_sysv"
10436 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10437 (match_operand 1 "" "g,g"))
10438 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10439 (clobber (match_scratch:SI 3 "=l,l"))]
10440 "DEFAULT_ABI == ABI_V4
10441 || DEFAULT_ABI == ABI_DARWIN"
10443 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10444 output_asm_insn ("crxor 6,6,6", operands);
10446 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10447 output_asm_insn ("creqv 6,6,6", operands);
10451 [(set_attr "type" "jmpreg,jmpreg")
10452 (set_attr "length" "4,8")])
10454 (define_insn "*call_nonlocal_sysv"
10455 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10456 (match_operand 1 "" "g,g"))
10457 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10458 (clobber (match_scratch:SI 3 "=l,l"))]
10459 "(DEFAULT_ABI == ABI_DARWIN
10460 || (DEFAULT_ABI == ABI_V4
10461 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10463 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10464 output_asm_insn ("crxor 6,6,6", operands);
10466 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10467 output_asm_insn ("creqv 6,6,6", operands);
10470 return output_call(insn, operands, 0, 2);
10472 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10475 [(set_attr "type" "branch,branch")
10476 (set_attr "length" "4,8")])
10478 (define_insn "*call_value_indirect_nonlocal_sysv"
10479 [(set (match_operand 0 "" "")
10480 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10481 (match_operand 2 "" "g,g")))
10482 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10483 (clobber (match_scratch:SI 4 "=l,l"))]
10484 "DEFAULT_ABI == ABI_V4
10485 || DEFAULT_ABI == ABI_DARWIN"
10487 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10488 output_asm_insn ("crxor 6,6,6", operands);
10490 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10491 output_asm_insn ("creqv 6,6,6", operands);
10495 [(set_attr "type" "jmpreg,jmpreg")
10496 (set_attr "length" "4,8")])
10498 (define_insn "*call_value_nonlocal_sysv"
10499 [(set (match_operand 0 "" "")
10500 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10501 (match_operand 2 "" "g,g")))
10502 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10503 (clobber (match_scratch:SI 4 "=l,l"))]
10504 "(DEFAULT_ABI == ABI_DARWIN
10505 || (DEFAULT_ABI == ABI_V4
10506 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10508 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10509 output_asm_insn ("crxor 6,6,6", operands);
10511 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10512 output_asm_insn ("creqv 6,6,6", operands);
10515 return output_call(insn, operands, 1, 3);
10517 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10520 [(set_attr "type" "branch,branch")
10521 (set_attr "length" "4,8")])
10523 ;; Call subroutine returning any type.
10524 (define_expand "untyped_call"
10525 [(parallel [(call (match_operand 0 "" "")
10527 (match_operand 1 "" "")
10528 (match_operand 2 "" "")])]
10534 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10536 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10538 rtx set = XVECEXP (operands[2], 0, i);
10539 emit_move_insn (SET_DEST (set), SET_SRC (set));
10542 /* The optimizer does not know that the call sets the function value
10543 registers we stored in the result block. We avoid problems by
10544 claiming that all hard registers are used and clobbered at this
10546 emit_insn (gen_blockage ());
10551 ;; sibling call patterns
10552 (define_expand "sibcall"
10553 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10554 (match_operand 1 "" ""))
10555 (use (match_operand 2 "" ""))
10556 (use (match_operand 3 "" ""))
10562 if (MACHOPIC_INDIRECT)
10563 operands[0] = machopic_indirect_call_target (operands[0]);
10566 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10569 operands[0] = XEXP (operands[0], 0);
10570 operands[3] = gen_reg_rtx (SImode);
10574 ;; this and similar patterns must be marked as using LR, otherwise
10575 ;; dataflow will try to delete the store into it. This is true
10576 ;; even when the actual reg to jump to is in CTR, when LR was
10577 ;; saved and restored around the PIC-setting BCL.
10578 (define_insn "*sibcall_local32"
10579 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10580 (match_operand 1 "" "g,g"))
10581 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10582 (use (match_operand:SI 3 "register_operand" "l,l"))
10584 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10587 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10588 output_asm_insn (\"crxor 6,6,6\", operands);
10590 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10591 output_asm_insn (\"creqv 6,6,6\", operands);
10593 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10595 [(set_attr "type" "branch")
10596 (set_attr "length" "4,8")])
10598 (define_insn "*sibcall_local64"
10599 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10600 (match_operand 1 "" "g,g"))
10601 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10602 (use (match_operand:SI 3 "register_operand" "l,l"))
10604 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10607 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10608 output_asm_insn (\"crxor 6,6,6\", operands);
10610 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10611 output_asm_insn (\"creqv 6,6,6\", operands);
10613 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10615 [(set_attr "type" "branch")
10616 (set_attr "length" "4,8")])
10618 (define_insn "*sibcall_value_local32"
10619 [(set (match_operand 0 "" "")
10620 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10621 (match_operand 2 "" "g,g")))
10622 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10623 (use (match_operand:SI 4 "register_operand" "l,l"))
10625 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10628 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10629 output_asm_insn (\"crxor 6,6,6\", operands);
10631 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10632 output_asm_insn (\"creqv 6,6,6\", operands);
10634 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10636 [(set_attr "type" "branch")
10637 (set_attr "length" "4,8")])
10640 (define_insn "*sibcall_value_local64"
10641 [(set (match_operand 0 "" "")
10642 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10643 (match_operand 2 "" "g,g")))
10644 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10645 (use (match_operand:SI 4 "register_operand" "l,l"))
10647 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10650 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10651 output_asm_insn (\"crxor 6,6,6\", operands);
10653 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10654 output_asm_insn (\"creqv 6,6,6\", operands);
10656 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10658 [(set_attr "type" "branch")
10659 (set_attr "length" "4,8")])
10661 (define_insn "*sibcall_nonlocal_aix32"
10662 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10663 (match_operand 1 "" "g"))
10664 (use (match_operand:SI 2 "immediate_operand" "O"))
10665 (use (match_operand:SI 3 "register_operand" "l"))
10668 && DEFAULT_ABI == ABI_AIX
10669 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10671 [(set_attr "type" "branch")
10672 (set_attr "length" "4")])
10674 (define_insn "*sibcall_nonlocal_aix64"
10675 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10676 (match_operand 1 "" "g"))
10677 (use (match_operand:SI 2 "immediate_operand" "O"))
10678 (use (match_operand:SI 3 "register_operand" "l"))
10681 && DEFAULT_ABI == ABI_AIX
10682 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10684 [(set_attr "type" "branch")
10685 (set_attr "length" "4")])
10687 (define_insn "*sibcall_value_nonlocal_aix32"
10688 [(set (match_operand 0 "" "")
10689 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10690 (match_operand 2 "" "g")))
10691 (use (match_operand:SI 3 "immediate_operand" "O"))
10692 (use (match_operand:SI 4 "register_operand" "l"))
10695 && DEFAULT_ABI == ABI_AIX
10696 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10698 [(set_attr "type" "branch")
10699 (set_attr "length" "4")])
10701 (define_insn "*sibcall_value_nonlocal_aix64"
10702 [(set (match_operand 0 "" "")
10703 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10704 (match_operand 2 "" "g")))
10705 (use (match_operand:SI 3 "immediate_operand" "O"))
10706 (use (match_operand:SI 4 "register_operand" "l"))
10709 && DEFAULT_ABI == ABI_AIX
10710 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10712 [(set_attr "type" "branch")
10713 (set_attr "length" "4")])
10715 (define_insn "*sibcall_nonlocal_sysv"
10716 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10717 (match_operand 1 "" ""))
10718 (use (match_operand 2 "immediate_operand" "O,n"))
10719 (use (match_operand:SI 3 "register_operand" "l,l"))
10721 "(DEFAULT_ABI == ABI_DARWIN
10722 || DEFAULT_ABI == ABI_V4)
10723 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10726 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10727 output_asm_insn (\"crxor 6,6,6\", operands);
10729 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10730 output_asm_insn (\"creqv 6,6,6\", operands);
10732 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10734 [(set_attr "type" "branch,branch")
10735 (set_attr "length" "4,8")])
10737 (define_expand "sibcall_value"
10738 [(parallel [(set (match_operand 0 "register_operand" "")
10739 (call (mem:SI (match_operand 1 "address_operand" ""))
10740 (match_operand 2 "" "")))
10741 (use (match_operand 3 "" ""))
10742 (use (match_operand 4 "" ""))
10748 if (MACHOPIC_INDIRECT)
10749 operands[1] = machopic_indirect_call_target (operands[1]);
10752 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10755 operands[1] = XEXP (operands[1], 0);
10756 operands[4] = gen_reg_rtx (SImode);
10760 (define_insn "*sibcall_value_nonlocal_sysv"
10761 [(set (match_operand 0 "" "")
10762 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10763 (match_operand 2 "" "")))
10764 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10765 (use (match_operand:SI 4 "register_operand" "l,l"))
10767 "(DEFAULT_ABI == ABI_DARWIN
10768 || DEFAULT_ABI == ABI_V4)
10769 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10772 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10773 output_asm_insn (\"crxor 6,6,6\", operands);
10775 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10776 output_asm_insn (\"creqv 6,6,6\", operands);
10778 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10780 [(set_attr "type" "branch,branch")
10781 (set_attr "length" "4,8")])
10783 (define_expand "sibcall_epilogue"
10784 [(use (const_int 0))]
10785 "TARGET_SCHED_PROLOG"
10788 rs6000_emit_epilogue (TRUE);
10792 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10793 ;; all of memory. This blocks insns from being moved across this point.
10795 (define_insn "blockage"
10796 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10800 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10801 ;; signed & unsigned, and one type of branch.
10803 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10804 ;; insns, and branches. We store the operands of compares until we see
10806 (define_expand "cmpsi"
10808 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10809 (match_operand:SI 1 "reg_or_short_operand" "")))]
10813 /* Take care of the possibility that operands[1] might be negative but
10814 this might be a logical operation. That insn doesn't exist. */
10815 if (GET_CODE (operands[1]) == CONST_INT
10816 && INTVAL (operands[1]) < 0)
10817 operands[1] = force_reg (SImode, operands[1]);
10819 rs6000_compare_op0 = operands[0];
10820 rs6000_compare_op1 = operands[1];
10821 rs6000_compare_fp_p = 0;
10825 (define_expand "cmpdi"
10827 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10828 (match_operand:DI 1 "reg_or_short_operand" "")))]
10832 /* Take care of the possibility that operands[1] might be negative but
10833 this might be a logical operation. That insn doesn't exist. */
10834 if (GET_CODE (operands[1]) == CONST_INT
10835 && INTVAL (operands[1]) < 0)
10836 operands[1] = force_reg (DImode, operands[1]);
10838 rs6000_compare_op0 = operands[0];
10839 rs6000_compare_op1 = operands[1];
10840 rs6000_compare_fp_p = 0;
10844 (define_expand "cmpsf"
10845 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10846 (match_operand:SF 1 "gpc_reg_operand" "")))]
10847 "TARGET_HARD_FLOAT"
10850 rs6000_compare_op0 = operands[0];
10851 rs6000_compare_op1 = operands[1];
10852 rs6000_compare_fp_p = 1;
10856 (define_expand "cmpdf"
10857 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10858 (match_operand:DF 1 "gpc_reg_operand" "")))]
10859 "TARGET_HARD_FLOAT && TARGET_FPRS"
10862 rs6000_compare_op0 = operands[0];
10863 rs6000_compare_op1 = operands[1];
10864 rs6000_compare_fp_p = 1;
10868 (define_expand "cmptf"
10869 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10870 (match_operand:TF 1 "gpc_reg_operand" "")))]
10871 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10872 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10875 rs6000_compare_op0 = operands[0];
10876 rs6000_compare_op1 = operands[1];
10877 rs6000_compare_fp_p = 1;
10881 (define_expand "beq"
10882 [(use (match_operand 0 "" ""))]
10884 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
10886 (define_expand "bne"
10887 [(use (match_operand 0 "" ""))]
10889 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
10891 (define_expand "bge"
10892 [(use (match_operand 0 "" ""))]
10894 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
10896 (define_expand "bgt"
10897 [(use (match_operand 0 "" ""))]
10899 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
10901 (define_expand "ble"
10902 [(use (match_operand 0 "" ""))]
10904 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
10906 (define_expand "blt"
10907 [(use (match_operand 0 "" ""))]
10909 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
10911 (define_expand "bgeu"
10912 [(use (match_operand 0 "" ""))]
10914 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
10916 (define_expand "bgtu"
10917 [(use (match_operand 0 "" ""))]
10919 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
10921 (define_expand "bleu"
10922 [(use (match_operand 0 "" ""))]
10924 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
10926 (define_expand "bltu"
10927 [(use (match_operand 0 "" ""))]
10929 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
10931 (define_expand "bunordered"
10932 [(use (match_operand 0 "" ""))]
10934 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
10936 (define_expand "bordered"
10937 [(use (match_operand 0 "" ""))]
10939 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
10941 (define_expand "buneq"
10942 [(use (match_operand 0 "" ""))]
10944 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
10946 (define_expand "bunge"
10947 [(use (match_operand 0 "" ""))]
10949 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
10951 (define_expand "bungt"
10952 [(use (match_operand 0 "" ""))]
10954 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
10956 (define_expand "bunle"
10957 [(use (match_operand 0 "" ""))]
10959 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
10961 (define_expand "bunlt"
10962 [(use (match_operand 0 "" ""))]
10964 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
10966 (define_expand "bltgt"
10967 [(use (match_operand 0 "" ""))]
10969 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
10971 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10972 ;; For SEQ, likewise, except that comparisons with zero should be done
10973 ;; with an scc insns. However, due to the order that combine see the
10974 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10975 ;; the cases we don't want to handle.
10976 (define_expand "seq"
10977 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10979 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
10981 (define_expand "sne"
10982 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10986 if (! rs6000_compare_fp_p)
10989 rs6000_emit_sCOND (NE, operands[0]);
10993 ;; A >= 0 is best done the portable way for A an integer.
10994 (define_expand "sge"
10995 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10999 if (! rs6000_compare_fp_p
11000 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11003 rs6000_emit_sCOND (GE, operands[0]);
11007 ;; A > 0 is best done using the portable sequence, so fail in that case.
11008 (define_expand "sgt"
11009 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11013 if (! rs6000_compare_fp_p
11014 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11017 rs6000_emit_sCOND (GT, operands[0]);
11021 ;; A <= 0 is best done the portable way for A an integer.
11022 (define_expand "sle"
11023 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11027 if (! rs6000_compare_fp_p
11028 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11031 rs6000_emit_sCOND (LE, operands[0]);
11035 ;; A < 0 is best done in the portable way for A an integer.
11036 (define_expand "slt"
11037 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11041 if (! rs6000_compare_fp_p
11042 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11045 rs6000_emit_sCOND (LT, operands[0]);
11049 (define_expand "sgeu"
11050 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11052 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11054 (define_expand "sgtu"
11055 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11057 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11059 (define_expand "sleu"
11060 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11062 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11064 (define_expand "sltu"
11065 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11067 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11069 (define_expand "sunordered"
11070 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11072 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11074 (define_expand "sordered"
11075 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11077 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11079 (define_expand "suneq"
11080 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11082 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11084 (define_expand "sunge"
11085 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11087 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11089 (define_expand "sungt"
11090 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11092 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11094 (define_expand "sunle"
11095 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11097 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11099 (define_expand "sunlt"
11100 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11102 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11104 (define_expand "sltgt"
11105 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11107 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11110 ;; Here are the actual compare insns.
11111 (define_insn "*cmpsi_internal1"
11112 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11113 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11114 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11116 "{cmp%I2|cmpw%I2} %0,%1,%2"
11117 [(set_attr "type" "cmp")])
11119 (define_insn "*cmpdi_internal1"
11120 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11121 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11122 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11125 [(set_attr "type" "cmp")])
11127 ;; If we are comparing a register for equality with a large constant,
11128 ;; we can do this with an XOR followed by a compare. But we need a scratch
11129 ;; register for the result of the XOR.
11132 [(set (match_operand:CC 0 "cc_reg_operand" "")
11133 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11134 (match_operand:SI 2 "non_short_cint_operand" "")))
11135 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11136 "find_single_use (operands[0], insn, 0)
11137 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11138 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11139 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11140 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11143 /* Get the constant we are comparing against, C, and see what it looks like
11144 sign-extended to 16 bits. Then see what constant could be XOR'ed
11145 with C to get the sign-extended value. */
11147 HOST_WIDE_INT c = INTVAL (operands[2]);
11148 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11149 HOST_WIDE_INT xorv = c ^ sextc;
11151 operands[4] = GEN_INT (xorv);
11152 operands[5] = GEN_INT (sextc);
11155 (define_insn "*cmpsi_internal2"
11156 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11157 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11158 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11160 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11161 [(set_attr "type" "cmp")])
11163 (define_insn "*cmpdi_internal2"
11164 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11165 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11166 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11168 "cmpld%I2 %0,%1,%b2"
11169 [(set_attr "type" "cmp")])
11171 ;; The following two insns don't exist as single insns, but if we provide
11172 ;; them, we can swap an add and compare, which will enable us to overlap more
11173 ;; of the required delay between a compare and branch. We generate code for
11174 ;; them by splitting.
11177 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11178 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11179 (match_operand:SI 2 "short_cint_operand" "i")))
11180 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11181 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11184 [(set_attr "length" "8")])
11187 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11188 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11189 (match_operand:SI 2 "u_short_cint_operand" "i")))
11190 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11191 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11194 [(set_attr "length" "8")])
11197 [(set (match_operand:CC 3 "cc_reg_operand" "")
11198 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11199 (match_operand:SI 2 "short_cint_operand" "")))
11200 (set (match_operand:SI 0 "gpc_reg_operand" "")
11201 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11203 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11204 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11207 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11208 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11209 (match_operand:SI 2 "u_short_cint_operand" "")))
11210 (set (match_operand:SI 0 "gpc_reg_operand" "")
11211 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11213 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11214 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11216 (define_insn "*cmpsf_internal1"
11217 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11218 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11219 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11220 "TARGET_HARD_FLOAT && TARGET_FPRS"
11222 [(set_attr "type" "fpcompare")])
11224 (define_insn "*cmpdf_internal1"
11225 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11226 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11227 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11228 "TARGET_HARD_FLOAT && TARGET_FPRS"
11230 [(set_attr "type" "fpcompare")])
11232 ;; Only need to compare second words if first words equal
11233 (define_insn "*cmptf_internal1"
11234 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11235 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11236 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11237 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
11238 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11239 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11240 [(set_attr "type" "fpcompare")
11241 (set_attr "length" "12")])
11243 (define_insn_and_split "*cmptf_internal2"
11244 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11245 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11246 (match_operand:TF 2 "gpc_reg_operand" "f")))
11247 (clobber (match_scratch:DF 3 "=f"))
11248 (clobber (match_scratch:DF 4 "=f"))
11249 (clobber (match_scratch:DF 5 "=f"))
11250 (clobber (match_scratch:DF 6 "=f"))
11251 (clobber (match_scratch:DF 7 "=f"))
11252 (clobber (match_scratch:DF 8 "=f"))
11253 (clobber (match_scratch:DF 9 "=f"))
11254 (clobber (match_scratch:DF 10 "=f"))]
11255 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
11256 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11258 "&& reload_completed"
11259 [(set (match_dup 3) (match_dup 13))
11260 (set (match_dup 4) (match_dup 14))
11261 (set (match_dup 9) (abs:DF (match_dup 5)))
11262 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11263 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11264 (label_ref (match_dup 11))
11266 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11267 (set (pc) (label_ref (match_dup 12)))
11269 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11270 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11271 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11272 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11275 REAL_VALUE_TYPE rv;
11276 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11277 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11279 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11280 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11281 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11282 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11283 operands[11] = gen_label_rtx ();
11284 operands[12] = gen_label_rtx ();
11286 operands[13] = force_const_mem (DFmode,
11287 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11288 operands[14] = force_const_mem (DFmode,
11289 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11293 operands[13] = gen_rtx_MEM (DFmode,
11294 create_TOC_reference (XEXP (operands[13], 0)));
11295 operands[14] = gen_rtx_MEM (DFmode,
11296 create_TOC_reference (XEXP (operands[14], 0)));
11297 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11298 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11299 RTX_UNCHANGING_P (operands[13]) = 1;
11300 RTX_UNCHANGING_P (operands[14]) = 1;
11304 ;; Now we have the scc insns. We can do some combinations because of the
11305 ;; way the machine works.
11307 ;; Note that this is probably faster if we can put an insn between the
11308 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11309 ;; cases the insns below which don't use an intermediate CR field will
11310 ;; be used instead.
11312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11313 (match_operator:SI 1 "scc_comparison_operator"
11314 [(match_operand 2 "cc_reg_operand" "y")
11317 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11318 [(set (attr "type")
11319 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11320 (const_string "mfcrf")
11322 (const_string "mfcr")))
11323 (set_attr "length" "12")])
11325 ;; Same as above, but get the EQ bit.
11326 (define_insn "move_from_CR_eq_bit"
11327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11328 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))]
11330 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
11331 [(set_attr "type" "mfcr")
11332 (set_attr "length" "12")])
11334 ;; Same as above, but get the OV/ORDERED bit.
11335 (define_insn "move_from_CR_ov_bit"
11336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11337 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11339 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11340 [(set_attr "type" "mfcr")
11341 (set_attr "length" "12")])
11344 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11345 (match_operator:DI 1 "scc_comparison_operator"
11346 [(match_operand 2 "cc_reg_operand" "y")
11349 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11350 [(set (attr "type")
11351 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11352 (const_string "mfcrf")
11354 (const_string "mfcr")))
11355 (set_attr "length" "12")])
11358 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11359 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11360 [(match_operand 2 "cc_reg_operand" "y,y")
11363 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11364 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11367 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11369 [(set_attr "type" "delayed_compare")
11370 (set_attr "length" "12,16")])
11373 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11374 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11375 [(match_operand 2 "cc_reg_operand" "")
11378 (set (match_operand:SI 3 "gpc_reg_operand" "")
11379 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11380 "TARGET_32BIT && reload_completed"
11381 [(set (match_dup 3)
11382 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11384 (compare:CC (match_dup 3)
11389 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11390 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11391 [(match_operand 2 "cc_reg_operand" "y")
11393 (match_operand:SI 3 "const_int_operand" "n")))]
11397 int is_bit = ccr_bit (operands[1], 1);
11398 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11401 if (is_bit >= put_bit)
11402 count = is_bit - put_bit;
11404 count = 32 - (put_bit - is_bit);
11406 operands[4] = GEN_INT (count);
11407 operands[5] = GEN_INT (put_bit);
11409 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11411 [(set (attr "type")
11412 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11413 (const_string "mfcrf")
11415 (const_string "mfcr")))
11416 (set_attr "length" "12")])
11419 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11421 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11422 [(match_operand 2 "cc_reg_operand" "y,y")
11424 (match_operand:SI 3 "const_int_operand" "n,n"))
11426 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11427 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11432 int is_bit = ccr_bit (operands[1], 1);
11433 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11436 /* Force split for non-cc0 compare. */
11437 if (which_alternative == 1)
11440 if (is_bit >= put_bit)
11441 count = is_bit - put_bit;
11443 count = 32 - (put_bit - is_bit);
11445 operands[5] = GEN_INT (count);
11446 operands[6] = GEN_INT (put_bit);
11448 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11450 [(set_attr "type" "delayed_compare")
11451 (set_attr "length" "12,16")])
11454 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11456 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11457 [(match_operand 2 "cc_reg_operand" "")
11459 (match_operand:SI 3 "const_int_operand" ""))
11461 (set (match_operand:SI 4 "gpc_reg_operand" "")
11462 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11465 [(set (match_dup 4)
11466 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11469 (compare:CC (match_dup 4)
11473 ;; There is a 3 cycle delay between consecutive mfcr instructions
11474 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11478 (match_operator:SI 1 "scc_comparison_operator"
11479 [(match_operand 2 "cc_reg_operand" "y")
11481 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11482 (match_operator:SI 4 "scc_comparison_operator"
11483 [(match_operand 5 "cc_reg_operand" "y")
11485 "REGNO (operands[2]) != REGNO (operands[5])"
11486 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11487 [(set_attr "type" "mfcr")
11488 (set_attr "length" "20")])
11491 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11492 (match_operator:DI 1 "scc_comparison_operator"
11493 [(match_operand 2 "cc_reg_operand" "y")
11495 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11496 (match_operator:DI 4 "scc_comparison_operator"
11497 [(match_operand 5 "cc_reg_operand" "y")
11499 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11500 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11501 [(set_attr "type" "mfcr")
11502 (set_attr "length" "20")])
11504 ;; There are some scc insns that can be done directly, without a compare.
11505 ;; These are faster because they don't involve the communications between
11506 ;; the FXU and branch units. In fact, we will be replacing all of the
11507 ;; integer scc insns here or in the portable methods in emit_store_flag.
11509 ;; Also support (neg (scc ..)) since that construct is used to replace
11510 ;; branches, (plus (scc ..) ..) since that construct is common and
11511 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11512 ;; cases where it is no more expensive than (neg (scc ..)).
11514 ;; Have reload force a constant into a register for the simple insns that
11515 ;; otherwise won't accept constants. We do this because it is faster than
11516 ;; the cmp/mfcr sequence we would otherwise generate.
11519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11520 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11521 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11522 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11525 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11526 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11527 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11528 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11529 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11530 [(set_attr "length" "12,8,12,12,12")])
11533 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11534 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11535 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11536 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11539 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11540 subfic %3,%1,0\;adde %0,%3,%1
11541 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11542 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11543 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11544 [(set_attr "length" "12,8,12,12,12")])
11547 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11549 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11550 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11552 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11553 (eq:SI (match_dup 1) (match_dup 2)))
11554 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11557 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11558 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11559 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11560 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11561 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11567 [(set_attr "type" "compare")
11568 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11571 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11573 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11574 (match_operand:SI 2 "reg_or_cint_operand" ""))
11576 (set (match_operand:SI 0 "gpc_reg_operand" "")
11577 (eq:SI (match_dup 1) (match_dup 2)))
11578 (clobber (match_scratch:SI 3 ""))]
11579 "TARGET_32BIT && reload_completed"
11580 [(parallel [(set (match_dup 0)
11581 (eq:SI (match_dup 1) (match_dup 2)))
11582 (clobber (match_dup 3))])
11584 (compare:CC (match_dup 0)
11589 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11591 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11592 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11594 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11595 (eq:DI (match_dup 1) (match_dup 2)))
11596 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11599 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11600 subfic %3,%1,0\;adde. %0,%3,%1
11601 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11602 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11603 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11609 [(set_attr "type" "compare")
11610 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11613 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11615 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11616 (match_operand:DI 2 "reg_or_cint_operand" ""))
11618 (set (match_operand:DI 0 "gpc_reg_operand" "")
11619 (eq:DI (match_dup 1) (match_dup 2)))
11620 (clobber (match_scratch:DI 3 ""))]
11621 "TARGET_64BIT && reload_completed"
11622 [(parallel [(set (match_dup 0)
11623 (eq:DI (match_dup 1) (match_dup 2)))
11624 (clobber (match_dup 3))])
11626 (compare:CC (match_dup 0)
11630 ;; We have insns of the form shown by the first define_insn below. If
11631 ;; there is something inside the comparison operation, we must split it.
11633 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11634 (plus:SI (match_operator 1 "comparison_operator"
11635 [(match_operand:SI 2 "" "")
11636 (match_operand:SI 3
11637 "reg_or_cint_operand" "")])
11638 (match_operand:SI 4 "gpc_reg_operand" "")))
11639 (clobber (match_operand:SI 5 "register_operand" ""))]
11640 "! gpc_reg_operand (operands[2], SImode)"
11641 [(set (match_dup 5) (match_dup 2))
11642 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11646 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11647 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11648 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11649 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11652 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11653 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11654 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11655 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11656 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11657 [(set_attr "length" "12,8,12,12,12")])
11660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11663 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11664 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11665 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11667 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11670 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11671 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11672 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11673 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11674 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11680 [(set_attr "type" "compare")
11681 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11684 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11687 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11688 (match_operand:SI 2 "reg_or_cint_operand" ""))
11689 (match_operand:SI 3 "gpc_reg_operand" ""))
11691 (clobber (match_scratch:SI 4 ""))]
11692 "TARGET_32BIT && reload_completed"
11693 [(set (match_dup 4)
11694 (plus:SI (eq:SI (match_dup 1)
11698 (compare:CC (match_dup 4)
11703 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11706 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11707 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11708 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11710 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11711 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11714 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11715 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11716 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11717 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11718 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11724 [(set_attr "type" "compare")
11725 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11728 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11731 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11732 (match_operand:SI 2 "reg_or_cint_operand" ""))
11733 (match_operand:SI 3 "gpc_reg_operand" ""))
11735 (set (match_operand:SI 0 "gpc_reg_operand" "")
11736 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11737 "TARGET_32BIT && reload_completed"
11738 [(set (match_dup 0)
11739 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11741 (compare:CC (match_dup 0)
11746 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11747 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11748 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11751 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11752 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11753 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11754 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11755 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11756 [(set_attr "length" "12,8,12,12,12")])
11758 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11759 ;; since it nabs/sr is just as fast.
11760 (define_insn "*ne0"
11761 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11762 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11764 (clobber (match_scratch:SI 2 "=&r"))]
11765 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11766 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11767 [(set_attr "length" "8")])
11770 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11771 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11773 (clobber (match_scratch:DI 2 "=&r"))]
11775 "addic %2,%1,-1\;subfe %0,%2,%1"
11776 [(set_attr "length" "8")])
11778 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11780 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11781 (plus:SI (lshiftrt:SI
11782 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11784 (match_operand:SI 2 "gpc_reg_operand" "r")))
11785 (clobber (match_scratch:SI 3 "=&r"))]
11787 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11788 [(set_attr "length" "8")])
11791 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11792 (plus:DI (lshiftrt:DI
11793 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11795 (match_operand:DI 2 "gpc_reg_operand" "r")))
11796 (clobber (match_scratch:DI 3 "=&r"))]
11798 "addic %3,%1,-1\;addze %0,%2"
11799 [(set_attr "length" "8")])
11802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11804 (plus:SI (lshiftrt:SI
11805 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11807 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11809 (clobber (match_scratch:SI 3 "=&r,&r"))
11810 (clobber (match_scratch:SI 4 "=X,&r"))]
11813 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11815 [(set_attr "type" "compare")
11816 (set_attr "length" "8,12")])
11819 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11821 (plus:SI (lshiftrt:SI
11822 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11824 (match_operand:SI 2 "gpc_reg_operand" ""))
11826 (clobber (match_scratch:SI 3 ""))
11827 (clobber (match_scratch:SI 4 ""))]
11828 "TARGET_32BIT && reload_completed"
11829 [(parallel [(set (match_dup 3)
11830 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11833 (clobber (match_dup 4))])
11835 (compare:CC (match_dup 3)
11840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11842 (plus:DI (lshiftrt:DI
11843 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11845 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11847 (clobber (match_scratch:DI 3 "=&r,&r"))]
11850 addic %3,%1,-1\;addze. %3,%2
11852 [(set_attr "type" "compare")
11853 (set_attr "length" "8,12")])
11856 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11858 (plus:DI (lshiftrt:DI
11859 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11861 (match_operand:DI 2 "gpc_reg_operand" ""))
11863 (clobber (match_scratch:DI 3 ""))]
11864 "TARGET_64BIT && reload_completed"
11865 [(set (match_dup 3)
11866 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11870 (compare:CC (match_dup 3)
11875 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11877 (plus:SI (lshiftrt:SI
11878 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11880 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11882 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11883 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11885 (clobber (match_scratch:SI 3 "=&r,&r"))]
11888 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11890 [(set_attr "type" "compare")
11891 (set_attr "length" "8,12")])
11894 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11896 (plus:SI (lshiftrt:SI
11897 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11899 (match_operand:SI 2 "gpc_reg_operand" ""))
11901 (set (match_operand:SI 0 "gpc_reg_operand" "")
11902 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11904 (clobber (match_scratch:SI 3 ""))]
11905 "TARGET_32BIT && reload_completed"
11906 [(parallel [(set (match_dup 0)
11907 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11909 (clobber (match_dup 3))])
11911 (compare:CC (match_dup 0)
11916 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11918 (plus:DI (lshiftrt:DI
11919 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11921 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11923 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11924 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11926 (clobber (match_scratch:DI 3 "=&r,&r"))]
11929 addic %3,%1,-1\;addze. %0,%2
11931 [(set_attr "type" "compare")
11932 (set_attr "length" "8,12")])
11935 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11937 (plus:DI (lshiftrt:DI
11938 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11940 (match_operand:DI 2 "gpc_reg_operand" ""))
11942 (set (match_operand:DI 0 "gpc_reg_operand" "")
11943 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11945 (clobber (match_scratch:DI 3 ""))]
11946 "TARGET_64BIT && reload_completed"
11947 [(parallel [(set (match_dup 0)
11948 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11950 (clobber (match_dup 3))])
11952 (compare:CC (match_dup 0)
11957 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11958 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11959 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11960 (clobber (match_scratch:SI 3 "=r,X"))]
11963 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11964 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11965 [(set_attr "length" "12")])
11968 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11970 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11971 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11973 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11974 (le:SI (match_dup 1) (match_dup 2)))
11975 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11978 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11979 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11982 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11983 (set_attr "length" "12,12,16,16")])
11986 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11988 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11989 (match_operand:SI 2 "reg_or_short_operand" ""))
11991 (set (match_operand:SI 0 "gpc_reg_operand" "")
11992 (le:SI (match_dup 1) (match_dup 2)))
11993 (clobber (match_scratch:SI 3 ""))]
11994 "TARGET_POWER && reload_completed"
11995 [(parallel [(set (match_dup 0)
11996 (le:SI (match_dup 1) (match_dup 2)))
11997 (clobber (match_dup 3))])
11999 (compare:CC (match_dup 0)
12004 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12005 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12006 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12007 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12010 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12011 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12012 [(set_attr "length" "12")])
12015 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12017 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12018 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12019 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12021 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12024 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12025 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12028 [(set_attr "type" "compare")
12029 (set_attr "length" "12,12,16,16")])
12032 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12034 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12035 (match_operand:SI 2 "reg_or_short_operand" ""))
12036 (match_operand:SI 3 "gpc_reg_operand" ""))
12038 (clobber (match_scratch:SI 4 ""))]
12039 "TARGET_POWER && reload_completed"
12040 [(set (match_dup 4)
12041 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12044 (compare:CC (match_dup 4)
12049 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12051 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12052 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12053 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12055 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12056 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12059 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12060 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12063 [(set_attr "type" "compare")
12064 (set_attr "length" "12,12,16,16")])
12067 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12069 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12070 (match_operand:SI 2 "reg_or_short_operand" ""))
12071 (match_operand:SI 3 "gpc_reg_operand" ""))
12073 (set (match_operand:SI 0 "gpc_reg_operand" "")
12074 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12075 "TARGET_POWER && reload_completed"
12076 [(set (match_dup 0)
12077 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12079 (compare:CC (match_dup 0)
12084 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12085 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12086 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12089 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12090 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12091 [(set_attr "length" "12")])
12094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12095 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12096 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12098 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12099 [(set_attr "length" "12")])
12102 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12103 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12104 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12106 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12107 [(set_attr "length" "12")])
12110 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12112 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12113 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12115 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12116 (leu:DI (match_dup 1) (match_dup 2)))]
12119 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12121 [(set_attr "type" "compare")
12122 (set_attr "length" "12,16")])
12125 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12127 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12128 (match_operand:DI 2 "reg_or_short_operand" ""))
12130 (set (match_operand:DI 0 "gpc_reg_operand" "")
12131 (leu:DI (match_dup 1) (match_dup 2)))]
12132 "TARGET_64BIT && reload_completed"
12133 [(set (match_dup 0)
12134 (leu:DI (match_dup 1) (match_dup 2)))
12136 (compare:CC (match_dup 0)
12141 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12143 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12144 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12146 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12147 (leu:SI (match_dup 1) (match_dup 2)))]
12150 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12152 [(set_attr "type" "compare")
12153 (set_attr "length" "12,16")])
12156 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12158 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12159 (match_operand:SI 2 "reg_or_short_operand" ""))
12161 (set (match_operand:SI 0 "gpc_reg_operand" "")
12162 (leu:SI (match_dup 1) (match_dup 2)))]
12163 "TARGET_32BIT && reload_completed"
12164 [(set (match_dup 0)
12165 (leu:SI (match_dup 1) (match_dup 2)))
12167 (compare:CC (match_dup 0)
12172 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12173 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12174 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12175 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12177 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12178 [(set_attr "length" "8")])
12181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12183 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12184 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12185 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12187 (clobber (match_scratch:SI 4 "=&r,&r"))]
12190 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12192 [(set_attr "type" "compare")
12193 (set_attr "length" "8,12")])
12196 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12198 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12199 (match_operand:SI 2 "reg_or_short_operand" ""))
12200 (match_operand:SI 3 "gpc_reg_operand" ""))
12202 (clobber (match_scratch:SI 4 ""))]
12203 "TARGET_32BIT && reload_completed"
12204 [(set (match_dup 4)
12205 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12208 (compare:CC (match_dup 4)
12213 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12215 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12216 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12217 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12219 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12220 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12223 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12225 [(set_attr "type" "compare")
12226 (set_attr "length" "8,12")])
12229 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12231 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12232 (match_operand:SI 2 "reg_or_short_operand" ""))
12233 (match_operand:SI 3 "gpc_reg_operand" ""))
12235 (set (match_operand:SI 0 "gpc_reg_operand" "")
12236 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12237 "TARGET_32BIT && reload_completed"
12238 [(set (match_dup 0)
12239 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12241 (compare:CC (match_dup 0)
12246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12247 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12248 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12250 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12251 [(set_attr "length" "12")])
12254 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12256 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12257 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12258 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12260 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12261 [(set_attr "length" "12")])
12264 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12267 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12268 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12269 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12271 (clobber (match_scratch:SI 4 "=&r,&r"))]
12274 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12276 [(set_attr "type" "compare")
12277 (set_attr "length" "12,16")])
12280 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12283 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12284 (match_operand:SI 2 "reg_or_short_operand" "")))
12285 (match_operand:SI 3 "gpc_reg_operand" ""))
12287 (clobber (match_scratch:SI 4 ""))]
12288 "TARGET_32BIT && reload_completed"
12289 [(set (match_dup 4)
12290 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12293 (compare:CC (match_dup 4)
12298 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12301 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12302 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12303 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12305 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12306 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12309 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12311 [(set_attr "type" "compare")
12312 (set_attr "length" "12,16")])
12315 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12318 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12319 (match_operand:SI 2 "reg_or_short_operand" "")))
12320 (match_operand:SI 3 "gpc_reg_operand" ""))
12322 (set (match_operand:SI 0 "gpc_reg_operand" "")
12323 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12324 "TARGET_32BIT && reload_completed"
12325 [(set (match_dup 0)
12326 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12329 (compare:CC (match_dup 0)
12334 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12335 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12336 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12338 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12339 [(set_attr "length" "12")])
12342 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12344 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12345 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12347 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12348 (lt:SI (match_dup 1) (match_dup 2)))]
12351 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12353 [(set_attr "type" "delayed_compare")
12354 (set_attr "length" "12,16")])
12357 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12359 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12360 (match_operand:SI 2 "reg_or_short_operand" ""))
12362 (set (match_operand:SI 0 "gpc_reg_operand" "")
12363 (lt:SI (match_dup 1) (match_dup 2)))]
12364 "TARGET_POWER && reload_completed"
12365 [(set (match_dup 0)
12366 (lt:SI (match_dup 1) (match_dup 2)))
12368 (compare:CC (match_dup 0)
12373 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12374 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12375 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12376 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12378 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12379 [(set_attr "length" "12")])
12382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12384 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12385 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12386 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12388 (clobber (match_scratch:SI 4 "=&r,&r"))]
12391 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12393 [(set_attr "type" "compare")
12394 (set_attr "length" "12,16")])
12397 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12399 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12400 (match_operand:SI 2 "reg_or_short_operand" ""))
12401 (match_operand:SI 3 "gpc_reg_operand" ""))
12403 (clobber (match_scratch:SI 4 ""))]
12404 "TARGET_POWER && reload_completed"
12405 [(set (match_dup 4)
12406 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12409 (compare:CC (match_dup 4)
12414 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12416 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12417 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12418 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12420 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12421 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12424 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12426 [(set_attr "type" "compare")
12427 (set_attr "length" "12,16")])
12430 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12432 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12433 (match_operand:SI 2 "reg_or_short_operand" ""))
12434 (match_operand:SI 3 "gpc_reg_operand" ""))
12436 (set (match_operand:SI 0 "gpc_reg_operand" "")
12437 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12438 "TARGET_POWER && reload_completed"
12439 [(set (match_dup 0)
12440 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12442 (compare:CC (match_dup 0)
12447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12448 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12449 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12451 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12452 [(set_attr "length" "12")])
12455 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12456 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12457 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12460 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12461 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12462 [(set_attr "length" "12")])
12465 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12467 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12468 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12470 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12471 (ltu:SI (match_dup 1) (match_dup 2)))]
12474 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12475 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12478 [(set_attr "type" "compare")
12479 (set_attr "length" "12,12,16,16")])
12482 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12484 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12485 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12487 (set (match_operand:SI 0 "gpc_reg_operand" "")
12488 (ltu:SI (match_dup 1) (match_dup 2)))]
12489 "TARGET_32BIT && reload_completed"
12490 [(set (match_dup 0)
12491 (ltu:SI (match_dup 1) (match_dup 2)))
12493 (compare:CC (match_dup 0)
12498 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12499 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12500 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12501 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12504 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12505 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12506 [(set_attr "length" "12")])
12509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12511 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12512 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12513 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12515 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12518 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12519 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12522 [(set_attr "type" "compare")
12523 (set_attr "length" "12,12,16,16")])
12526 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12528 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12529 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12530 (match_operand:SI 3 "gpc_reg_operand" ""))
12532 (clobber (match_scratch:SI 4 ""))]
12533 "TARGET_32BIT && reload_completed"
12534 [(set (match_dup 4)
12535 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12538 (compare:CC (match_dup 4)
12543 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12545 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12546 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12547 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12549 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12550 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12553 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12554 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12557 [(set_attr "type" "compare")
12558 (set_attr "length" "12,12,16,16")])
12561 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12563 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12564 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12565 (match_operand:SI 3 "gpc_reg_operand" ""))
12567 (set (match_operand:SI 0 "gpc_reg_operand" "")
12568 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12569 "TARGET_32BIT && reload_completed"
12570 [(set (match_dup 0)
12571 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12573 (compare:CC (match_dup 0)
12578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12579 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12580 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12583 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12584 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12585 [(set_attr "length" "8")])
12588 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12589 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12590 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12591 (clobber (match_scratch:SI 3 "=r"))]
12593 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12594 [(set_attr "length" "12")])
12597 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12599 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12600 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12602 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12603 (ge:SI (match_dup 1) (match_dup 2)))
12604 (clobber (match_scratch:SI 3 "=r,r"))]
12607 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12609 [(set_attr "type" "compare")
12610 (set_attr "length" "12,16")])
12613 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12615 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12616 (match_operand:SI 2 "reg_or_short_operand" ""))
12618 (set (match_operand:SI 0 "gpc_reg_operand" "")
12619 (ge:SI (match_dup 1) (match_dup 2)))
12620 (clobber (match_scratch:SI 3 ""))]
12621 "TARGET_POWER && reload_completed"
12622 [(parallel [(set (match_dup 0)
12623 (ge:SI (match_dup 1) (match_dup 2)))
12624 (clobber (match_dup 3))])
12626 (compare:CC (match_dup 0)
12631 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12632 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12633 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12634 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12636 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12637 [(set_attr "length" "12")])
12640 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12642 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12643 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12644 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12646 (clobber (match_scratch:SI 4 "=&r,&r"))]
12649 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12651 [(set_attr "type" "compare")
12652 (set_attr "length" "12,16")])
12655 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12657 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12658 (match_operand:SI 2 "reg_or_short_operand" ""))
12659 (match_operand:SI 3 "gpc_reg_operand" ""))
12661 (clobber (match_scratch:SI 4 ""))]
12662 "TARGET_POWER && reload_completed"
12663 [(set (match_dup 4)
12664 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12667 (compare:CC (match_dup 4)
12672 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12674 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12675 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12676 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12678 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12679 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12682 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12684 [(set_attr "type" "compare")
12685 (set_attr "length" "12,16")])
12688 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12690 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12691 (match_operand:SI 2 "reg_or_short_operand" ""))
12692 (match_operand:SI 3 "gpc_reg_operand" ""))
12694 (set (match_operand:SI 0 "gpc_reg_operand" "")
12695 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12696 "TARGET_POWER && reload_completed"
12697 [(set (match_dup 0)
12698 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12700 (compare:CC (match_dup 0)
12705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12706 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12707 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12709 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12710 [(set_attr "length" "12")])
12713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12714 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12715 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12718 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12719 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12720 [(set_attr "length" "12")])
12723 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12724 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12725 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12728 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12729 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12730 [(set_attr "length" "12")])
12733 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12735 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12736 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12738 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12739 (geu:SI (match_dup 1) (match_dup 2)))]
12742 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12743 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12746 [(set_attr "type" "compare")
12747 (set_attr "length" "12,12,16,16")])
12750 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12752 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12753 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12755 (set (match_operand:SI 0 "gpc_reg_operand" "")
12756 (geu:SI (match_dup 1) (match_dup 2)))]
12757 "TARGET_32BIT && reload_completed"
12758 [(set (match_dup 0)
12759 (geu:SI (match_dup 1) (match_dup 2)))
12761 (compare:CC (match_dup 0)
12766 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12768 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12769 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12771 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12772 (geu:DI (match_dup 1) (match_dup 2)))]
12775 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12776 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12779 [(set_attr "type" "compare")
12780 (set_attr "length" "12,12,16,16")])
12783 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12785 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12786 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12788 (set (match_operand:DI 0 "gpc_reg_operand" "")
12789 (geu:DI (match_dup 1) (match_dup 2)))]
12790 "TARGET_64BIT && reload_completed"
12791 [(set (match_dup 0)
12792 (geu:DI (match_dup 1) (match_dup 2)))
12794 (compare:CC (match_dup 0)
12799 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12800 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12801 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12802 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12805 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12806 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12807 [(set_attr "length" "8")])
12810 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12812 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12813 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12814 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12816 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12819 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12820 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12823 [(set_attr "type" "compare")
12824 (set_attr "length" "8,8,12,12")])
12827 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12829 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12830 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12831 (match_operand:SI 3 "gpc_reg_operand" ""))
12833 (clobber (match_scratch:SI 4 ""))]
12834 "TARGET_32BIT && reload_completed"
12835 [(set (match_dup 4)
12836 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12839 (compare:CC (match_dup 4)
12844 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12846 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12847 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12848 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12850 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12851 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12854 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12855 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12858 [(set_attr "type" "compare")
12859 (set_attr "length" "8,8,12,12")])
12862 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12864 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12865 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12866 (match_operand:SI 3 "gpc_reg_operand" ""))
12868 (set (match_operand:SI 0 "gpc_reg_operand" "")
12869 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12870 "TARGET_32BIT && reload_completed"
12871 [(set (match_dup 0)
12872 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12874 (compare:CC (match_dup 0)
12879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12880 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12881 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12884 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12885 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12886 [(set_attr "length" "12")])
12889 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12891 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12892 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12893 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12896 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12897 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12898 [(set_attr "length" "12")])
12901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12904 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12905 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12906 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12908 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12911 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12912 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12915 [(set_attr "type" "compare")
12916 (set_attr "length" "12,12,16,16")])
12919 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12922 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12923 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12924 (match_operand:SI 3 "gpc_reg_operand" ""))
12926 (clobber (match_scratch:SI 4 ""))]
12927 "TARGET_32BIT && reload_completed"
12928 [(set (match_dup 4)
12929 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12932 (compare:CC (match_dup 4)
12937 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12940 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12941 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12942 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12944 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12945 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12948 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12949 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12952 [(set_attr "type" "compare")
12953 (set_attr "length" "12,12,16,16")])
12956 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12959 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12960 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12961 (match_operand:SI 3 "gpc_reg_operand" ""))
12963 (set (match_operand:SI 0 "gpc_reg_operand" "")
12964 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12965 "TARGET_32BIT && reload_completed"
12966 [(set (match_dup 0)
12967 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12969 (compare:CC (match_dup 0)
12974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12975 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12978 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12979 [(set_attr "length" "12")])
12982 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12983 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12986 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12987 [(set_attr "length" "12")])
12990 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12992 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12995 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12996 (gt:SI (match_dup 1) (const_int 0)))]
12999 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13001 [(set_attr "type" "delayed_compare")
13002 (set_attr "length" "12,16")])
13005 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13007 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13010 (set (match_operand:SI 0 "gpc_reg_operand" "")
13011 (gt:SI (match_dup 1) (const_int 0)))]
13012 "TARGET_32BIT && reload_completed"
13013 [(set (match_dup 0)
13014 (gt:SI (match_dup 1) (const_int 0)))
13016 (compare:CC (match_dup 0)
13021 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13023 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13026 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13027 (gt:DI (match_dup 1) (const_int 0)))]
13030 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13032 [(set_attr "type" "delayed_compare")
13033 (set_attr "length" "12,16")])
13036 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13038 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13041 (set (match_operand:DI 0 "gpc_reg_operand" "")
13042 (gt:DI (match_dup 1) (const_int 0)))]
13043 "TARGET_64BIT && reload_completed"
13044 [(set (match_dup 0)
13045 (gt:DI (match_dup 1) (const_int 0)))
13047 (compare:CC (match_dup 0)
13052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13053 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13054 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13056 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13057 [(set_attr "length" "12")])
13060 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13062 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13063 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13065 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13066 (gt:SI (match_dup 1) (match_dup 2)))]
13069 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13071 [(set_attr "type" "delayed_compare")
13072 (set_attr "length" "12,16")])
13075 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13077 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13078 (match_operand:SI 2 "reg_or_short_operand" ""))
13080 (set (match_operand:SI 0 "gpc_reg_operand" "")
13081 (gt:SI (match_dup 1) (match_dup 2)))]
13082 "TARGET_POWER && reload_completed"
13083 [(set (match_dup 0)
13084 (gt:SI (match_dup 1) (match_dup 2)))
13086 (compare:CC (match_dup 0)
13091 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13092 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13094 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13096 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13097 [(set_attr "length" "12")])
13100 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13101 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13103 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13105 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13106 [(set_attr "length" "12")])
13109 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13111 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13113 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13115 (clobber (match_scratch:SI 3 "=&r,&r"))]
13118 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13120 [(set_attr "type" "compare")
13121 (set_attr "length" "12,16")])
13124 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13126 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13128 (match_operand:SI 2 "gpc_reg_operand" ""))
13130 (clobber (match_scratch:SI 3 ""))]
13131 "TARGET_32BIT && reload_completed"
13132 [(set (match_dup 3)
13133 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13136 (compare:CC (match_dup 3)
13141 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13143 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13145 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13147 (clobber (match_scratch:DI 3 "=&r,&r"))]
13150 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13152 [(set_attr "type" "compare")
13153 (set_attr "length" "12,16")])
13156 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13158 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13160 (match_operand:DI 2 "gpc_reg_operand" ""))
13162 (clobber (match_scratch:DI 3 ""))]
13163 "TARGET_64BIT && reload_completed"
13164 [(set (match_dup 3)
13165 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13168 (compare:CC (match_dup 3)
13173 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13175 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13177 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13179 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13180 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13183 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13185 [(set_attr "type" "compare")
13186 (set_attr "length" "12,16")])
13189 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13191 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13193 (match_operand:SI 2 "gpc_reg_operand" ""))
13195 (set (match_operand:SI 0 "gpc_reg_operand" "")
13196 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13197 "TARGET_32BIT && reload_completed"
13198 [(set (match_dup 0)
13199 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13201 (compare:CC (match_dup 0)
13206 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13208 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13210 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13212 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13213 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13216 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13218 [(set_attr "type" "compare")
13219 (set_attr "length" "12,16")])
13222 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13224 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13226 (match_operand:DI 2 "gpc_reg_operand" ""))
13228 (set (match_operand:DI 0 "gpc_reg_operand" "")
13229 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13230 "TARGET_64BIT && reload_completed"
13231 [(set (match_dup 0)
13232 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13234 (compare:CC (match_dup 0)
13239 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13240 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13241 (match_operand:SI 2 "reg_or_short_operand" "r"))
13242 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13244 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13245 [(set_attr "length" "12")])
13248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13250 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13251 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13252 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13254 (clobber (match_scratch:SI 4 "=&r,&r"))]
13257 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13259 [(set_attr "type" "compare")
13260 (set_attr "length" "12,16")])
13263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13265 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13266 (match_operand:SI 2 "reg_or_short_operand" ""))
13267 (match_operand:SI 3 "gpc_reg_operand" ""))
13269 (clobber (match_scratch:SI 4 ""))]
13270 "TARGET_POWER && reload_completed"
13271 [(set (match_dup 4)
13272 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13274 (compare:CC (match_dup 4)
13279 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13281 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13282 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13283 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13285 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13286 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13289 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13291 [(set_attr "type" "compare")
13292 (set_attr "length" "12,16")])
13295 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13297 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13298 (match_operand:SI 2 "reg_or_short_operand" ""))
13299 (match_operand:SI 3 "gpc_reg_operand" ""))
13301 (set (match_operand:SI 0 "gpc_reg_operand" "")
13302 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13303 "TARGET_POWER && reload_completed"
13304 [(set (match_dup 0)
13305 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13307 (compare:CC (match_dup 0)
13312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13313 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13316 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13317 [(set_attr "length" "12")])
13320 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13321 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13324 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13325 [(set_attr "length" "12")])
13328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13329 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13330 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13332 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13333 [(set_attr "length" "12")])
13336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13337 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13338 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13340 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
13341 [(set_attr "length" "12")])
13344 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13345 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13346 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13348 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13349 [(set_attr "length" "12")])
13352 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13354 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13355 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13357 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13358 (gtu:SI (match_dup 1) (match_dup 2)))]
13361 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13363 [(set_attr "type" "compare")
13364 (set_attr "length" "12,16")])
13367 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13369 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13370 (match_operand:SI 2 "reg_or_short_operand" ""))
13372 (set (match_operand:SI 0 "gpc_reg_operand" "")
13373 (gtu:SI (match_dup 1) (match_dup 2)))]
13374 "TARGET_32BIT && reload_completed"
13375 [(set (match_dup 0)
13376 (gtu:SI (match_dup 1) (match_dup 2)))
13378 (compare:CC (match_dup 0)
13383 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13385 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13386 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13388 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13389 (gtu:DI (match_dup 1) (match_dup 2)))]
13392 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13394 [(set_attr "type" "compare")
13395 (set_attr "length" "12,16")])
13398 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13400 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13401 (match_operand:DI 2 "reg_or_short_operand" ""))
13403 (set (match_operand:DI 0 "gpc_reg_operand" "")
13404 (gtu:DI (match_dup 1) (match_dup 2)))]
13405 "TARGET_64BIT && reload_completed"
13406 [(set (match_dup 0)
13407 (gtu:DI (match_dup 1) (match_dup 2)))
13409 (compare:CC (match_dup 0)
13414 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13415 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13416 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
13417 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
13420 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13421 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
13422 [(set_attr "length" "8,12")])
13425 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13426 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13427 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
13428 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
13431 addic %0,%1,%k2\;addze %0,%3
13432 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
13433 [(set_attr "length" "8,12")])
13436 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13438 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13439 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13440 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13442 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13445 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13446 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13449 [(set_attr "type" "compare")
13450 (set_attr "length" "8,12,12,16")])
13453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13455 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13456 (match_operand:SI 2 "reg_or_short_operand" ""))
13457 (match_operand:SI 3 "gpc_reg_operand" ""))
13459 (clobber (match_scratch:SI 4 ""))]
13460 "TARGET_32BIT && reload_completed"
13461 [(set (match_dup 4)
13462 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13465 (compare:CC (match_dup 4)
13470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13472 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13473 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13474 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13476 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13479 addic %4,%1,%k2\;addze. %4,%3
13480 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13483 [(set_attr "type" "compare")
13484 (set_attr "length" "8,12,12,16")])
13487 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13489 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13490 (match_operand:DI 2 "reg_or_short_operand" ""))
13491 (match_operand:DI 3 "gpc_reg_operand" ""))
13493 (clobber (match_scratch:DI 4 ""))]
13494 "TARGET_64BIT && reload_completed"
13495 [(set (match_dup 4)
13496 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13499 (compare:CC (match_dup 4)
13504 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13506 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13507 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13508 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13510 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13511 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13514 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13515 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
13518 [(set_attr "type" "compare")
13519 (set_attr "length" "8,12,12,16")])
13522 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13524 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13525 (match_operand:SI 2 "reg_or_short_operand" ""))
13526 (match_operand:SI 3 "gpc_reg_operand" ""))
13528 (set (match_operand:SI 0 "gpc_reg_operand" "")
13529 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13530 "TARGET_32BIT && reload_completed"
13531 [(set (match_dup 0)
13532 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13534 (compare:CC (match_dup 0)
13539 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13541 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13542 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13543 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13545 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13546 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13549 addic %0,%1,%k2\;addze. %0,%3
13550 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
13553 [(set_attr "type" "compare")
13554 (set_attr "length" "8,12,12,16")])
13557 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13559 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13560 (match_operand:DI 2 "reg_or_short_operand" ""))
13561 (match_operand:DI 3 "gpc_reg_operand" ""))
13563 (set (match_operand:DI 0 "gpc_reg_operand" "")
13564 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13565 "TARGET_64BIT && reload_completed"
13566 [(set (match_dup 0)
13567 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13569 (compare:CC (match_dup 0)
13574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13575 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13576 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13578 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13579 [(set_attr "length" "8")])
13582 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13583 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13584 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13586 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13587 [(set_attr "length" "8")])
13589 ;; Define both directions of branch and return. If we need a reload
13590 ;; register, we'd rather use CR0 since it is much easier to copy a
13591 ;; register CC value to there.
13595 (if_then_else (match_operator 1 "branch_comparison_operator"
13597 "cc_reg_operand" "y")
13599 (label_ref (match_operand 0 "" ""))
13604 return output_cbranch (operands[1], \"%l0\", 0, insn);
13606 [(set_attr "type" "branch")])
13610 (if_then_else (match_operator 0 "branch_comparison_operator"
13612 "cc_reg_operand" "y")
13619 return output_cbranch (operands[0], NULL, 0, insn);
13621 [(set_attr "type" "branch")
13622 (set_attr "length" "4")])
13626 (if_then_else (match_operator 1 "branch_comparison_operator"
13628 "cc_reg_operand" "y")
13631 (label_ref (match_operand 0 "" ""))))]
13635 return output_cbranch (operands[1], \"%l0\", 1, insn);
13637 [(set_attr "type" "branch")])
13641 (if_then_else (match_operator 0 "branch_comparison_operator"
13643 "cc_reg_operand" "y")
13650 return output_cbranch (operands[0], NULL, 1, insn);
13652 [(set_attr "type" "branch")
13653 (set_attr "length" "4")])
13655 ;; Logic on condition register values.
13657 ; This pattern matches things like
13658 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13659 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13661 ; which are generated by the branch logic.
13662 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13664 (define_insn "*cceq_ior_compare"
13665 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13666 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13667 [(match_operator:SI 2
13668 "branch_positive_comparison_operator"
13670 "cc_reg_operand" "y,y")
13672 (match_operator:SI 4
13673 "branch_positive_comparison_operator"
13675 "cc_reg_operand" "0,y")
13679 "cr%q1 %E0,%j2,%j4"
13680 [(set_attr "type" "cr_logical,delayed_cr")])
13682 ; Why is the constant -1 here, but 1 in the previous pattern?
13683 ; Because ~1 has all but the low bit set.
13685 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13686 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13687 [(not:SI (match_operator:SI 2
13688 "branch_positive_comparison_operator"
13690 "cc_reg_operand" "y,y")
13692 (match_operator:SI 4
13693 "branch_positive_comparison_operator"
13695 "cc_reg_operand" "0,y")
13699 "cr%q1 %E0,%j2,%j4"
13700 [(set_attr "type" "cr_logical,delayed_cr")])
13702 (define_insn "*cceq_rev_compare"
13703 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13704 (compare:CCEQ (match_operator:SI 1
13705 "branch_positive_comparison_operator"
13707 "cc_reg_operand" "0,y")
13711 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13712 [(set_attr "type" "cr_logical,delayed_cr")])
13714 ;; If we are comparing the result of two comparisons, this can be done
13715 ;; using creqv or crxor.
13717 (define_insn_and_split ""
13718 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13719 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13720 [(match_operand 2 "cc_reg_operand" "y")
13722 (match_operator 3 "branch_comparison_operator"
13723 [(match_operand 4 "cc_reg_operand" "y")
13728 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13732 int positive_1, positive_2;
13734 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13735 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13738 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
13739 GET_CODE (operands[1])),
13741 operands[2], const0_rtx);
13742 else if (GET_MODE (operands[1]) != SImode)
13743 operands[1] = gen_rtx (GET_CODE (operands[1]),
13745 operands[2], const0_rtx);
13748 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
13749 GET_CODE (operands[3])),
13751 operands[4], const0_rtx);
13752 else if (GET_MODE (operands[3]) != SImode)
13753 operands[3] = gen_rtx (GET_CODE (operands[3]),
13755 operands[4], const0_rtx);
13757 if (positive_1 == positive_2)
13759 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13760 operands[5] = constm1_rtx;
13764 operands[5] = const1_rtx;
13768 ;; Unconditional branch and return.
13770 (define_insn "jump"
13772 (label_ref (match_operand 0 "" "")))]
13775 [(set_attr "type" "branch")])
13777 (define_insn "return"
13781 [(set_attr "type" "jmpreg")])
13783 (define_expand "indirect_jump"
13784 [(set (pc) (match_operand 0 "register_operand" ""))]
13789 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13791 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13795 (define_insn "indirect_jumpsi"
13796 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13801 [(set_attr "type" "jmpreg")])
13803 (define_insn "indirect_jumpdi"
13804 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13809 [(set_attr "type" "jmpreg")])
13811 ;; Table jump for switch statements:
13812 (define_expand "tablejump"
13813 [(use (match_operand 0 "" ""))
13814 (use (label_ref (match_operand 1 "" "")))]
13819 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13821 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13825 (define_expand "tablejumpsi"
13826 [(set (match_dup 3)
13827 (plus:SI (match_operand:SI 0 "" "")
13829 (parallel [(set (pc) (match_dup 3))
13830 (use (label_ref (match_operand 1 "" "")))])]
13833 { operands[0] = force_reg (SImode, operands[0]);
13834 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13835 operands[3] = gen_reg_rtx (SImode);
13838 (define_expand "tablejumpdi"
13839 [(set (match_dup 4)
13840 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13842 (plus:DI (match_dup 4)
13844 (parallel [(set (pc) (match_dup 3))
13845 (use (label_ref (match_operand 1 "" "")))])]
13848 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13849 operands[3] = gen_reg_rtx (DImode);
13850 operands[4] = gen_reg_rtx (DImode);
13855 (match_operand:SI 0 "register_operand" "c,*l"))
13856 (use (label_ref (match_operand 1 "" "")))]
13861 [(set_attr "type" "jmpreg")])
13865 (match_operand:DI 0 "register_operand" "c,*l"))
13866 (use (label_ref (match_operand 1 "" "")))]
13871 [(set_attr "type" "jmpreg")])
13876 "{cror 0,0,0|nop}")
13878 ;; Define the subtract-one-and-jump insns, starting with the template
13879 ;; so loop.c knows what to generate.
13881 (define_expand "doloop_end"
13882 [(use (match_operand 0 "" "")) ; loop pseudo
13883 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13884 (use (match_operand 2 "" "")) ; max iterations
13885 (use (match_operand 3 "" "")) ; loop level
13886 (use (match_operand 4 "" ""))] ; label
13890 /* Only use this on innermost loops. */
13891 if (INTVAL (operands[3]) > 1)
13895 if (GET_MODE (operands[0]) != DImode)
13897 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13901 if (GET_MODE (operands[0]) != SImode)
13903 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13908 (define_expand "ctrsi"
13909 [(parallel [(set (pc)
13910 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13912 (label_ref (match_operand 1 "" ""))
13915 (plus:SI (match_dup 0)
13917 (clobber (match_scratch:CC 2 ""))
13918 (clobber (match_scratch:SI 3 ""))])]
13922 (define_expand "ctrdi"
13923 [(parallel [(set (pc)
13924 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13926 (label_ref (match_operand 1 "" ""))
13929 (plus:DI (match_dup 0)
13931 (clobber (match_scratch:CC 2 ""))
13932 (clobber (match_scratch:DI 3 ""))])]
13936 ;; We need to be able to do this for any operand, including MEM, or we
13937 ;; will cause reload to blow up since we don't allow output reloads on
13939 ;; For the length attribute to be calculated correctly, the
13940 ;; label MUST be operand 0.
13942 (define_insn "*ctrsi_internal1"
13944 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13946 (label_ref (match_operand 0 "" ""))
13948 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
13949 (plus:SI (match_dup 1)
13951 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13952 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13956 if (which_alternative != 0)
13958 else if (get_attr_length (insn) == 4)
13959 return \"{bdn|bdnz} %l0\";
13961 return \"bdz $+8\;b %l0\";
13963 [(set_attr "type" "branch")
13964 (set_attr "length" "*,12,16,16")])
13966 (define_insn "*ctrsi_internal2"
13968 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
13971 (label_ref (match_operand 0 "" ""))))
13972 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
13973 (plus:SI (match_dup 1)
13975 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13976 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
13980 if (which_alternative != 0)
13982 else if (get_attr_length (insn) == 4)
13983 return \"bdz %l0\";
13985 return \"{bdn|bdnz} $+8\;b %l0\";
13987 [(set_attr "type" "branch")
13988 (set_attr "length" "*,12,16,16")])
13990 (define_insn "*ctrdi_internal1"
13992 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
13994 (label_ref (match_operand 0 "" ""))
13996 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
13997 (plus:DI (match_dup 1)
13999 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14000 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14004 if (which_alternative != 0)
14006 else if (get_attr_length (insn) == 4)
14007 return \"{bdn|bdnz} %l0\";
14009 return \"bdz $+8\;b %l0\";
14011 [(set_attr "type" "branch")
14012 (set_attr "length" "*,12,16,16")])
14014 (define_insn "*ctrdi_internal2"
14016 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14019 (label_ref (match_operand 0 "" ""))))
14020 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14021 (plus:DI (match_dup 1)
14023 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14024 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14028 if (which_alternative != 0)
14030 else if (get_attr_length (insn) == 4)
14031 return \"bdz %l0\";
14033 return \"{bdn|bdnz} $+8\;b %l0\";
14035 [(set_attr "type" "branch")
14036 (set_attr "length" "*,12,16,16")])
14038 ;; Similar, but we can use GE since we have a REG_NONNEG.
14040 (define_insn "*ctrsi_internal3"
14042 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14044 (label_ref (match_operand 0 "" ""))
14046 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14047 (plus:SI (match_dup 1)
14049 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14050 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14051 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14054 if (which_alternative != 0)
14056 else if (get_attr_length (insn) == 4)
14057 return \"{bdn|bdnz} %l0\";
14059 return \"bdz $+8\;b %l0\";
14061 [(set_attr "type" "branch")
14062 (set_attr "length" "*,12,16,16")])
14064 (define_insn "*ctrsi_internal4"
14066 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14069 (label_ref (match_operand 0 "" ""))))
14070 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14071 (plus:SI (match_dup 1)
14073 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14074 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14075 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14078 if (which_alternative != 0)
14080 else if (get_attr_length (insn) == 4)
14081 return \"bdz %l0\";
14083 return \"{bdn|bdnz} $+8\;b %l0\";
14085 [(set_attr "type" "branch")
14086 (set_attr "length" "*,12,16,16")])
14088 (define_insn "*ctrdi_internal3"
14090 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14092 (label_ref (match_operand 0 "" ""))
14094 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14095 (plus:DI (match_dup 1)
14097 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14098 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14099 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14102 if (which_alternative != 0)
14104 else if (get_attr_length (insn) == 4)
14105 return \"{bdn|bdnz} %l0\";
14107 return \"bdz $+8\;b %l0\";
14109 [(set_attr "type" "branch")
14110 (set_attr "length" "*,12,16,16")])
14112 (define_insn "*ctrdi_internal4"
14114 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14117 (label_ref (match_operand 0 "" ""))))
14118 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14119 (plus:DI (match_dup 1)
14121 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14122 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14123 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14126 if (which_alternative != 0)
14128 else if (get_attr_length (insn) == 4)
14129 return \"bdz %l0\";
14131 return \"{bdn|bdnz} $+8\;b %l0\";
14133 [(set_attr "type" "branch")
14134 (set_attr "length" "*,12,16,16")])
14136 ;; Similar but use EQ
14138 (define_insn "*ctrsi_internal5"
14140 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14142 (label_ref (match_operand 0 "" ""))
14144 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14145 (plus:SI (match_dup 1)
14147 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14148 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14152 if (which_alternative != 0)
14154 else if (get_attr_length (insn) == 4)
14155 return \"bdz %l0\";
14157 return \"{bdn|bdnz} $+8\;b %l0\";
14159 [(set_attr "type" "branch")
14160 (set_attr "length" "*,12,16,16")])
14162 (define_insn "*ctrsi_internal6"
14164 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14167 (label_ref (match_operand 0 "" ""))))
14168 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14169 (plus:SI (match_dup 1)
14171 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14172 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14176 if (which_alternative != 0)
14178 else if (get_attr_length (insn) == 4)
14179 return \"{bdn|bdnz} %l0\";
14181 return \"bdz $+8\;b %l0\";
14183 [(set_attr "type" "branch")
14184 (set_attr "length" "*,12,16,16")])
14186 (define_insn "*ctrdi_internal5"
14188 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14190 (label_ref (match_operand 0 "" ""))
14192 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14193 (plus:DI (match_dup 1)
14195 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14196 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14200 if (which_alternative != 0)
14202 else if (get_attr_length (insn) == 4)
14203 return \"bdz %l0\";
14205 return \"{bdn|bdnz} $+8\;b %l0\";
14207 [(set_attr "type" "branch")
14208 (set_attr "length" "*,12,16,16")])
14210 (define_insn "*ctrdi_internal6"
14212 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14215 (label_ref (match_operand 0 "" ""))))
14216 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14217 (plus:DI (match_dup 1)
14219 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14220 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14224 if (which_alternative != 0)
14226 else if (get_attr_length (insn) == 4)
14227 return \"{bdn|bdnz} %l0\";
14229 return \"bdz $+8\;b %l0\";
14231 [(set_attr "type" "branch")
14232 (set_attr "length" "*,12,16,16")])
14234 ;; Now the splitters if we could not allocate the CTR register
14238 (if_then_else (match_operator 2 "comparison_operator"
14239 [(match_operand:SI 1 "gpc_reg_operand" "")
14241 (match_operand 5 "" "")
14242 (match_operand 6 "" "")))
14243 (set (match_operand:SI 0 "gpc_reg_operand" "")
14244 (plus:SI (match_dup 1)
14246 (clobber (match_scratch:CC 3 ""))
14247 (clobber (match_scratch:SI 4 ""))]
14248 "TARGET_32BIT && reload_completed"
14249 [(parallel [(set (match_dup 3)
14250 (compare:CC (plus:SI (match_dup 1)
14254 (plus:SI (match_dup 1)
14256 (set (pc) (if_then_else (match_dup 7)
14260 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14265 (if_then_else (match_operator 2 "comparison_operator"
14266 [(match_operand:SI 1 "gpc_reg_operand" "")
14268 (match_operand 5 "" "")
14269 (match_operand 6 "" "")))
14270 (set (match_operand:SI 0 "nonimmediate_operand" "")
14271 (plus:SI (match_dup 1) (const_int -1)))
14272 (clobber (match_scratch:CC 3 ""))
14273 (clobber (match_scratch:SI 4 ""))]
14274 "TARGET_32BIT && reload_completed
14275 && ! gpc_reg_operand (operands[0], SImode)"
14276 [(parallel [(set (match_dup 3)
14277 (compare:CC (plus:SI (match_dup 1)
14281 (plus:SI (match_dup 1)
14285 (set (pc) (if_then_else (match_dup 7)
14289 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14293 (if_then_else (match_operator 2 "comparison_operator"
14294 [(match_operand:DI 1 "gpc_reg_operand" "")
14296 (match_operand 5 "" "")
14297 (match_operand 6 "" "")))
14298 (set (match_operand:DI 0 "gpc_reg_operand" "")
14299 (plus:DI (match_dup 1)
14301 (clobber (match_scratch:CC 3 ""))
14302 (clobber (match_scratch:DI 4 ""))]
14303 "TARGET_64BIT && reload_completed"
14304 [(parallel [(set (match_dup 3)
14305 (compare:CC (plus:DI (match_dup 1)
14309 (plus:DI (match_dup 1)
14311 (set (pc) (if_then_else (match_dup 7)
14315 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14320 (if_then_else (match_operator 2 "comparison_operator"
14321 [(match_operand:DI 1 "gpc_reg_operand" "")
14323 (match_operand 5 "" "")
14324 (match_operand 6 "" "")))
14325 (set (match_operand:DI 0 "nonimmediate_operand" "")
14326 (plus:DI (match_dup 1) (const_int -1)))
14327 (clobber (match_scratch:CC 3 ""))
14328 (clobber (match_scratch:DI 4 ""))]
14329 "TARGET_64BIT && reload_completed
14330 && ! gpc_reg_operand (operands[0], DImode)"
14331 [(parallel [(set (match_dup 3)
14332 (compare:CC (plus:DI (match_dup 1)
14336 (plus:DI (match_dup 1)
14340 (set (pc) (if_then_else (match_dup 7)
14344 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14347 (define_insn "trap"
14348 [(trap_if (const_int 1) (const_int 0))]
14352 (define_expand "conditional_trap"
14353 [(trap_if (match_operator 0 "trap_comparison_operator"
14354 [(match_dup 2) (match_dup 3)])
14355 (match_operand 1 "const_int_operand" ""))]
14357 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14358 operands[2] = rs6000_compare_op0;
14359 operands[3] = rs6000_compare_op1;")
14362 [(trap_if (match_operator 0 "trap_comparison_operator"
14363 [(match_operand:SI 1 "register_operand" "r")
14364 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14367 "{t|tw}%V0%I2 %1,%2")
14370 [(trap_if (match_operator 0 "trap_comparison_operator"
14371 [(match_operand:DI 1 "register_operand" "r")
14372 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14377 ;; Insns related to generating the function prologue and epilogue.
14379 (define_expand "prologue"
14380 [(use (const_int 0))]
14381 "TARGET_SCHED_PROLOG"
14384 rs6000_emit_prologue ();
14388 (define_insn "*movesi_from_cr_one"
14389 [(match_parallel 0 "mfcr_operation"
14390 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14391 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14392 (match_operand 3 "immediate_operand" "n")]
14393 UNSPEC_MOVESI_FROM_CR))])]
14399 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14401 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14402 operands[4] = GEN_INT (mask);
14403 output_asm_insn (\"mfcr %1,%4\", operands);
14407 [(set_attr "type" "mfcrf")])
14409 (define_insn "movesi_from_cr"
14410 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14411 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14412 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14413 UNSPEC_MOVESI_FROM_CR))]
14416 [(set_attr "type" "mfcr")])
14418 (define_insn "*stmw"
14419 [(match_parallel 0 "stmw_operation"
14420 [(set (match_operand:SI 1 "memory_operand" "=m")
14421 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14423 "{stm|stmw} %2,%1")
14425 (define_insn "*save_fpregs_si"
14426 [(match_parallel 0 "any_operand"
14427 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14428 (use (match_operand:SI 2 "call_operand" "s"))
14429 (set (match_operand:DF 3 "memory_operand" "=m")
14430 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14433 [(set_attr "type" "branch")
14434 (set_attr "length" "4")])
14436 (define_insn "*save_fpregs_di"
14437 [(match_parallel 0 "any_operand"
14438 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14439 (use (match_operand:DI 2 "call_operand" "s"))
14440 (set (match_operand:DF 3 "memory_operand" "=m")
14441 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14444 [(set_attr "type" "branch")
14445 (set_attr "length" "4")])
14447 ; These are to explain that changes to the stack pointer should
14448 ; not be moved over stores to stack memory.
14449 (define_insn "stack_tie"
14450 [(set (match_operand:BLK 0 "memory_operand" "+m")
14451 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14454 [(set_attr "length" "0")])
14457 (define_expand "epilogue"
14458 [(use (const_int 0))]
14459 "TARGET_SCHED_PROLOG"
14462 rs6000_emit_epilogue (FALSE);
14466 ; On some processors, doing the mtcrf one CC register at a time is
14467 ; faster (like on the 604e). On others, doing them all at once is
14468 ; faster; for instance, on the 601 and 750.
14470 (define_expand "movsi_to_cr_one"
14471 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14472 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14473 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14475 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14477 (define_insn "*movsi_to_cr"
14478 [(match_parallel 0 "mtcrf_operation"
14479 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14480 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14481 (match_operand 3 "immediate_operand" "n")]
14482 UNSPEC_MOVESI_TO_CR))])]
14488 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14489 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14490 operands[4] = GEN_INT (mask);
14491 return \"mtcrf %4,%2\";
14493 [(set_attr "type" "mtcr")])
14495 (define_insn "*mtcrfsi"
14496 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14497 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14498 (match_operand 2 "immediate_operand" "n")]
14499 UNSPEC_MOVESI_TO_CR))]
14500 "GET_CODE (operands[0]) == REG
14501 && CR_REGNO_P (REGNO (operands[0]))
14502 && GET_CODE (operands[2]) == CONST_INT
14503 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14505 [(set_attr "type" "mtcr")])
14507 ; The load-multiple instructions have similar properties.
14508 ; Note that "load_multiple" is a name known to the machine-independent
14509 ; code that actually corresponds to the powerpc load-string.
14511 (define_insn "*lmw"
14512 [(match_parallel 0 "lmw_operation"
14513 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14514 (match_operand:SI 2 "memory_operand" "m"))])]
14518 (define_insn "*return_internal_si"
14520 (use (match_operand:SI 0 "register_operand" "lc"))]
14523 [(set_attr "type" "jmpreg")])
14525 (define_insn "*return_internal_di"
14527 (use (match_operand:DI 0 "register_operand" "lc"))]
14530 [(set_attr "type" "jmpreg")])
14532 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14533 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14535 (define_insn "*return_and_restore_fpregs_si"
14536 [(match_parallel 0 "any_operand"
14538 (use (match_operand:SI 1 "register_operand" "l"))
14539 (use (match_operand:SI 2 "call_operand" "s"))
14540 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14541 (match_operand:DF 4 "memory_operand" "m"))])]
14545 (define_insn "*return_and_restore_fpregs_di"
14546 [(match_parallel 0 "any_operand"
14548 (use (match_operand:DI 1 "register_operand" "l"))
14549 (use (match_operand:DI 2 "call_operand" "s"))
14550 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14551 (match_operand:DF 4 "memory_operand" "m"))])]
14555 ; This is used in compiling the unwind routines.
14556 (define_expand "eh_return"
14557 [(use (match_operand 0 "general_operand" ""))]
14562 emit_insn (gen_eh_set_lr_si (operands[0]));
14564 emit_insn (gen_eh_set_lr_di (operands[0]));
14568 ; We can't expand this before we know where the link register is stored.
14569 (define_insn "eh_set_lr_si"
14570 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14572 (clobber (match_scratch:SI 1 "=&b"))]
14576 (define_insn "eh_set_lr_di"
14577 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14579 (clobber (match_scratch:DI 1 "=&b"))]
14584 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14585 (clobber (match_scratch 1 ""))]
14590 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14594 (define_insn "prefetch"
14595 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14596 (match_operand:SI 1 "const_int_operand" "n")
14597 (match_operand:SI 2 "const_int_operand" "n"))]
14601 if (GET_CODE (operands[0]) == REG)
14602 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14603 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14605 [(set_attr "type" "load")])
14607 (include "altivec.md")