1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the
20 ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 ;; MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
53 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
57 ;; UNSPEC_VOLATILE usage
62 (UNSPECV_EH_RR 9) ; eh_reg_restore
65 ;; Define an insn type attribute. This is used in function unit delay
67 (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
68 (const_string "integer"))
71 ; '(pc)' in the following doesn't include the instruction itself; it is
72 ; calculated as if the instruction had zero size.
73 (define_attr "length" ""
74 (if_then_else (eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
77 (lt (minus (match_dup 0) (pc))
83 ;; Processor type -- this attribute must exactly match the processor_type
84 ;; enumeration in rs6000.h.
86 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
87 (const (symbol_ref "rs6000_cpu_attr")))
89 (automata_option "ndfa")
102 (include "power4.md")
103 (include "power5.md")
106 ;; Start with fixed-point load and store insns. Here we put only the more
107 ;; complex forms. Basic data transfer is done later.
109 (define_expand "zero_extendqidi2"
110 [(set (match_operand:DI 0 "gpc_reg_operand" "")
111 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
116 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
117 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
122 [(set_attr "type" "load,*")])
125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
126 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
128 (clobber (match_scratch:DI 2 "=r,r"))]
133 [(set_attr "type" "compare")
134 (set_attr "length" "4,8")])
137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
138 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
140 (clobber (match_scratch:DI 2 ""))]
141 "TARGET_POWERPC64 && reload_completed"
143 (zero_extend:DI (match_dup 1)))
145 (compare:CC (match_dup 2)
150 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
151 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
153 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
154 (zero_extend:DI (match_dup 1)))]
159 [(set_attr "type" "compare")
160 (set_attr "length" "4,8")])
163 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
164 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
166 (set (match_operand:DI 0 "gpc_reg_operand" "")
167 (zero_extend:DI (match_dup 1)))]
168 "TARGET_POWERPC64 && reload_completed"
170 (zero_extend:DI (match_dup 1)))
172 (compare:CC (match_dup 0)
176 (define_insn "extendqidi2"
177 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
178 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
184 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
186 (clobber (match_scratch:DI 2 "=r,r"))]
191 [(set_attr "type" "compare")
192 (set_attr "length" "4,8")])
195 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
196 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
198 (clobber (match_scratch:DI 2 ""))]
199 "TARGET_POWERPC64 && reload_completed"
201 (sign_extend:DI (match_dup 1)))
203 (compare:CC (match_dup 2)
208 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
209 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
211 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
212 (sign_extend:DI (match_dup 1)))]
217 [(set_attr "type" "compare")
218 (set_attr "length" "4,8")])
221 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
222 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
224 (set (match_operand:DI 0 "gpc_reg_operand" "")
225 (sign_extend:DI (match_dup 1)))]
226 "TARGET_POWERPC64 && reload_completed"
228 (sign_extend:DI (match_dup 1)))
230 (compare:CC (match_dup 0)
234 (define_expand "zero_extendhidi2"
235 [(set (match_operand:DI 0 "gpc_reg_operand" "")
236 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
242 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
247 [(set_attr "type" "load,*")])
250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
251 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
253 (clobber (match_scratch:DI 2 "=r,r"))]
258 [(set_attr "type" "compare")
259 (set_attr "length" "4,8")])
262 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
263 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
265 (clobber (match_scratch:DI 2 ""))]
266 "TARGET_POWERPC64 && reload_completed"
268 (zero_extend:DI (match_dup 1)))
270 (compare:CC (match_dup 2)
275 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
276 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
278 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
279 (zero_extend:DI (match_dup 1)))]
284 [(set_attr "type" "compare")
285 (set_attr "length" "4,8")])
288 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
289 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
291 (set (match_operand:DI 0 "gpc_reg_operand" "")
292 (zero_extend:DI (match_dup 1)))]
293 "TARGET_POWERPC64 && reload_completed"
295 (zero_extend:DI (match_dup 1)))
297 (compare:CC (match_dup 0)
301 (define_expand "extendhidi2"
302 [(set (match_operand:DI 0 "gpc_reg_operand" "")
303 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
308 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
309 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
314 [(set_attr "type" "load_ext,*")])
317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
318 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
320 (clobber (match_scratch:DI 2 "=r,r"))]
325 [(set_attr "type" "compare")
326 (set_attr "length" "4,8")])
329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
330 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
332 (clobber (match_scratch:DI 2 ""))]
333 "TARGET_POWERPC64 && reload_completed"
335 (sign_extend:DI (match_dup 1)))
337 (compare:CC (match_dup 2)
342 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
343 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
345 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
346 (sign_extend:DI (match_dup 1)))]
351 [(set_attr "type" "compare")
352 (set_attr "length" "4,8")])
355 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
356 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
358 (set (match_operand:DI 0 "gpc_reg_operand" "")
359 (sign_extend:DI (match_dup 1)))]
360 "TARGET_POWERPC64 && reload_completed"
362 (sign_extend:DI (match_dup 1)))
364 (compare:CC (match_dup 0)
368 (define_expand "zero_extendsidi2"
369 [(set (match_operand:DI 0 "gpc_reg_operand" "")
370 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
376 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
381 [(set_attr "type" "load,*")])
384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
385 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
387 (clobber (match_scratch:DI 2 "=r,r"))]
392 [(set_attr "type" "compare")
393 (set_attr "length" "4,8")])
396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
397 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
399 (clobber (match_scratch:DI 2 ""))]
400 "TARGET_POWERPC64 && reload_completed"
402 (zero_extend:DI (match_dup 1)))
404 (compare:CC (match_dup 2)
409 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
410 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
412 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
413 (zero_extend:DI (match_dup 1)))]
418 [(set_attr "type" "compare")
419 (set_attr "length" "4,8")])
422 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
423 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
425 (set (match_operand:DI 0 "gpc_reg_operand" "")
426 (zero_extend:DI (match_dup 1)))]
427 "TARGET_POWERPC64 && reload_completed"
429 (zero_extend:DI (match_dup 1)))
431 (compare:CC (match_dup 0)
435 (define_expand "extendsidi2"
436 [(set (match_operand:DI 0 "gpc_reg_operand" "")
437 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
442 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
443 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
448 [(set_attr "type" "load_ext,*")])
451 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
452 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
454 (clobber (match_scratch:DI 2 "=r,r"))]
459 [(set_attr "type" "compare")
460 (set_attr "length" "4,8")])
463 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
464 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
466 (clobber (match_scratch:DI 2 ""))]
467 "TARGET_POWERPC64 && reload_completed"
469 (sign_extend:DI (match_dup 1)))
471 (compare:CC (match_dup 2)
476 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
477 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
479 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
480 (sign_extend:DI (match_dup 1)))]
485 [(set_attr "type" "compare")
486 (set_attr "length" "4,8")])
489 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
490 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
492 (set (match_operand:DI 0 "gpc_reg_operand" "")
493 (sign_extend:DI (match_dup 1)))]
494 "TARGET_POWERPC64 && reload_completed"
496 (sign_extend:DI (match_dup 1)))
498 (compare:CC (match_dup 0)
502 (define_expand "zero_extendqisi2"
503 [(set (match_operand:SI 0 "gpc_reg_operand" "")
504 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
510 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
514 {rlinm|rlwinm} %0,%1,0,0xff"
515 [(set_attr "type" "load,*")])
518 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
519 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
521 (clobber (match_scratch:SI 2 "=r,r"))]
524 {andil.|andi.} %2,%1,0xff
526 [(set_attr "type" "compare")
527 (set_attr "length" "4,8")])
530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
531 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
533 (clobber (match_scratch:SI 2 ""))]
536 (zero_extend:SI (match_dup 1)))
538 (compare:CC (match_dup 2)
543 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
544 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
546 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
547 (zero_extend:SI (match_dup 1)))]
550 {andil.|andi.} %0,%1,0xff
552 [(set_attr "type" "compare")
553 (set_attr "length" "4,8")])
556 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
557 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
559 (set (match_operand:SI 0 "gpc_reg_operand" "")
560 (zero_extend:SI (match_dup 1)))]
563 (zero_extend:SI (match_dup 1)))
565 (compare:CC (match_dup 0)
569 (define_expand "extendqisi2"
570 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
571 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
576 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
577 else if (TARGET_POWER)
578 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
580 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
584 (define_insn "extendqisi2_ppc"
585 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
586 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
592 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
594 (clobber (match_scratch:SI 2 "=r,r"))]
599 [(set_attr "type" "compare")
600 (set_attr "length" "4,8")])
603 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
604 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
606 (clobber (match_scratch:SI 2 ""))]
607 "TARGET_POWERPC && reload_completed"
609 (sign_extend:SI (match_dup 1)))
611 (compare:CC (match_dup 2)
616 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
617 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
619 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
620 (sign_extend:SI (match_dup 1)))]
625 [(set_attr "type" "compare")
626 (set_attr "length" "4,8")])
629 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
630 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
632 (set (match_operand:SI 0 "gpc_reg_operand" "")
633 (sign_extend:SI (match_dup 1)))]
634 "TARGET_POWERPC && reload_completed"
636 (sign_extend:SI (match_dup 1)))
638 (compare:CC (match_dup 0)
642 (define_expand "extendqisi2_power"
643 [(parallel [(set (match_dup 2)
644 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
646 (clobber (scratch:SI))])
647 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
648 (ashiftrt:SI (match_dup 2)
650 (clobber (scratch:SI))])]
653 { operands[1] = gen_lowpart (SImode, operands[1]);
654 operands[2] = gen_reg_rtx (SImode); }")
656 (define_expand "extendqisi2_no_power"
658 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
660 (set (match_operand:SI 0 "gpc_reg_operand" "")
661 (ashiftrt:SI (match_dup 2)
663 "! TARGET_POWER && ! TARGET_POWERPC"
665 { operands[1] = gen_lowpart (SImode, operands[1]);
666 operands[2] = gen_reg_rtx (SImode); }")
668 (define_expand "zero_extendqihi2"
669 [(set (match_operand:HI 0 "gpc_reg_operand" "")
670 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
675 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
676 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
680 {rlinm|rlwinm} %0,%1,0,0xff"
681 [(set_attr "type" "load,*")])
684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
685 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
687 (clobber (match_scratch:HI 2 "=r,r"))]
690 {andil.|andi.} %2,%1,0xff
692 [(set_attr "type" "compare")
693 (set_attr "length" "4,8")])
696 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
697 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
699 (clobber (match_scratch:HI 2 ""))]
702 (zero_extend:HI (match_dup 1)))
704 (compare:CC (match_dup 2)
709 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
710 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
712 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
713 (zero_extend:HI (match_dup 1)))]
716 {andil.|andi.} %0,%1,0xff
718 [(set_attr "type" "compare")
719 (set_attr "length" "4,8")])
722 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
723 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
725 (set (match_operand:HI 0 "gpc_reg_operand" "")
726 (zero_extend:HI (match_dup 1)))]
729 (zero_extend:HI (match_dup 1)))
731 (compare:CC (match_dup 0)
735 (define_expand "extendqihi2"
736 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
737 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
742 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
743 else if (TARGET_POWER)
744 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
746 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
750 (define_insn "extendqihi2_ppc"
751 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
752 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
758 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
760 (clobber (match_scratch:HI 2 "=r,r"))]
765 [(set_attr "type" "compare")
766 (set_attr "length" "4,8")])
769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
770 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
772 (clobber (match_scratch:HI 2 ""))]
773 "TARGET_POWERPC && reload_completed"
775 (sign_extend:HI (match_dup 1)))
777 (compare:CC (match_dup 2)
782 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
783 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
785 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
786 (sign_extend:HI (match_dup 1)))]
791 [(set_attr "type" "compare")
792 (set_attr "length" "4,8")])
795 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
796 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
798 (set (match_operand:HI 0 "gpc_reg_operand" "")
799 (sign_extend:HI (match_dup 1)))]
800 "TARGET_POWERPC && reload_completed"
802 (sign_extend:HI (match_dup 1)))
804 (compare:CC (match_dup 0)
808 (define_expand "extendqihi2_power"
809 [(parallel [(set (match_dup 2)
810 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
812 (clobber (scratch:SI))])
813 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
814 (ashiftrt:SI (match_dup 2)
816 (clobber (scratch:SI))])]
819 { operands[0] = gen_lowpart (SImode, operands[0]);
820 operands[1] = gen_lowpart (SImode, operands[1]);
821 operands[2] = gen_reg_rtx (SImode); }")
823 (define_expand "extendqihi2_no_power"
825 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
827 (set (match_operand:HI 0 "gpc_reg_operand" "")
828 (ashiftrt:SI (match_dup 2)
830 "! TARGET_POWER && ! TARGET_POWERPC"
832 { operands[0] = gen_lowpart (SImode, operands[0]);
833 operands[1] = gen_lowpart (SImode, operands[1]);
834 operands[2] = gen_reg_rtx (SImode); }")
836 (define_expand "zero_extendhisi2"
837 [(set (match_operand:SI 0 "gpc_reg_operand" "")
838 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
844 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
848 {rlinm|rlwinm} %0,%1,0,0xffff"
849 [(set_attr "type" "load,*")])
852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
853 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
855 (clobber (match_scratch:SI 2 "=r,r"))]
858 {andil.|andi.} %2,%1,0xffff
860 [(set_attr "type" "compare")
861 (set_attr "length" "4,8")])
864 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
865 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
867 (clobber (match_scratch:SI 2 ""))]
870 (zero_extend:SI (match_dup 1)))
872 (compare:CC (match_dup 2)
877 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
878 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
880 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
881 (zero_extend:SI (match_dup 1)))]
884 {andil.|andi.} %0,%1,0xffff
886 [(set_attr "type" "compare")
887 (set_attr "length" "4,8")])
890 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
891 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
893 (set (match_operand:SI 0 "gpc_reg_operand" "")
894 (zero_extend:SI (match_dup 1)))]
897 (zero_extend:SI (match_dup 1)))
899 (compare:CC (match_dup 0)
903 (define_expand "extendhisi2"
904 [(set (match_operand:SI 0 "gpc_reg_operand" "")
905 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
910 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
911 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
916 [(set_attr "type" "load_ext,*")])
919 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
920 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
922 (clobber (match_scratch:SI 2 "=r,r"))]
927 [(set_attr "type" "compare")
928 (set_attr "length" "4,8")])
931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
932 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
934 (clobber (match_scratch:SI 2 ""))]
937 (sign_extend:SI (match_dup 1)))
939 (compare:CC (match_dup 2)
944 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
945 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
947 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
948 (sign_extend:SI (match_dup 1)))]
953 [(set_attr "type" "compare")
954 (set_attr "length" "4,8")])
957 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
958 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
960 (set (match_operand:SI 0 "gpc_reg_operand" "")
961 (sign_extend:SI (match_dup 1)))]
964 (sign_extend:SI (match_dup 1)))
966 (compare:CC (match_dup 0)
970 ;; Fixed-point arithmetic insns.
972 ;; Discourage ai/addic because of carry but provide it in an alternative
973 ;; allowing register zero as source.
974 (define_expand "addsi3"
975 [(set (match_operand:SI 0 "gpc_reg_operand" "")
976 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
977 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
981 if (GET_CODE (operands[2]) == CONST_INT
982 && ! add_operand (operands[2], SImode))
984 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
985 ? operands[0] : gen_reg_rtx (SImode));
987 HOST_WIDE_INT val = INTVAL (operands[2]);
988 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
989 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
991 /* The ordering here is important for the prolog expander.
992 When space is allocated from the stack, adding 'low' first may
993 produce a temporary deallocation (which would be bad). */
994 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
995 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1000 (define_insn "*addsi3_internal1"
1001 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1002 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1003 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1007 {cal %0,%2(%1)|addi %0,%1,%2}
1009 {cau|addis} %0,%1,%v2"
1010 [(set_attr "length" "4,4,4,4")])
1012 (define_insn "addsi3_high"
1013 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1014 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1015 (high:SI (match_operand 2 "" ""))))]
1016 "TARGET_MACHO && !TARGET_64BIT"
1017 "{cau|addis} %0,%1,ha16(%2)"
1018 [(set_attr "length" "4")])
1020 (define_insn "*addsi3_internal2"
1021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1022 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1023 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1025 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1028 {cax.|add.} %3,%1,%2
1029 {ai.|addic.} %3,%1,%2
1032 [(set_attr "type" "fast_compare,compare,compare,compare")
1033 (set_attr "length" "4,4,8,8")])
1036 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1037 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1038 (match_operand:SI 2 "reg_or_short_operand" ""))
1040 (clobber (match_scratch:SI 3 ""))]
1041 "TARGET_32BIT && reload_completed"
1043 (plus:SI (match_dup 1)
1046 (compare:CC (match_dup 3)
1050 (define_insn "*addsi3_internal3"
1051 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1052 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1053 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1055 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1056 (plus:SI (match_dup 1)
1060 {cax.|add.} %0,%1,%2
1061 {ai.|addic.} %0,%1,%2
1064 [(set_attr "type" "fast_compare,compare,compare,compare")
1065 (set_attr "length" "4,4,8,8")])
1068 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1069 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1070 (match_operand:SI 2 "reg_or_short_operand" ""))
1072 (set (match_operand:SI 0 "gpc_reg_operand" "")
1073 (plus:SI (match_dup 1) (match_dup 2)))]
1074 "TARGET_32BIT && reload_completed"
1076 (plus:SI (match_dup 1)
1079 (compare:CC (match_dup 0)
1083 ;; Split an add that we can't do in one insn into two insns, each of which
1084 ;; does one 16-bit part. This is used by combine. Note that the low-order
1085 ;; add should be last in case the result gets used in an address.
1088 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1089 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1090 (match_operand:SI 2 "non_add_cint_operand" "")))]
1092 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1093 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1096 HOST_WIDE_INT val = INTVAL (operands[2]);
1097 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1098 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1100 operands[3] = GEN_INT (rest);
1101 operands[4] = GEN_INT (low);
1104 (define_insn "one_cmplsi2"
1105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1106 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1111 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1112 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1114 (clobber (match_scratch:SI 2 "=r,r"))]
1119 [(set_attr "type" "compare")
1120 (set_attr "length" "4,8")])
1123 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1124 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1126 (clobber (match_scratch:SI 2 ""))]
1127 "TARGET_32BIT && reload_completed"
1129 (not:SI (match_dup 1)))
1131 (compare:CC (match_dup 2)
1136 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1137 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1139 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1140 (not:SI (match_dup 1)))]
1145 [(set_attr "type" "compare")
1146 (set_attr "length" "4,8")])
1149 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1150 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1152 (set (match_operand:SI 0 "gpc_reg_operand" "")
1153 (not:SI (match_dup 1)))]
1154 "TARGET_32BIT && reload_completed"
1156 (not:SI (match_dup 1)))
1158 (compare:CC (match_dup 0)
1163 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1164 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1165 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1167 "{sf%I1|subf%I1c} %0,%2,%1")
1170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1171 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1172 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1179 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1180 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1181 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1183 (clobber (match_scratch:SI 3 "=r,r"))]
1186 {sf.|subfc.} %3,%2,%1
1188 [(set_attr "type" "compare")
1189 (set_attr "length" "4,8")])
1192 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1193 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1194 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1196 (clobber (match_scratch:SI 3 "=r,r"))]
1197 "TARGET_POWERPC && TARGET_32BIT"
1201 [(set_attr "type" "fast_compare")
1202 (set_attr "length" "4,8")])
1205 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1206 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1207 (match_operand:SI 2 "gpc_reg_operand" ""))
1209 (clobber (match_scratch:SI 3 ""))]
1210 "TARGET_32BIT && reload_completed"
1212 (minus:SI (match_dup 1)
1215 (compare:CC (match_dup 3)
1220 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1221 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1222 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1224 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1225 (minus:SI (match_dup 1) (match_dup 2)))]
1228 {sf.|subfc.} %0,%2,%1
1230 [(set_attr "type" "compare")
1231 (set_attr "length" "4,8")])
1234 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1235 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1236 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1238 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1239 (minus:SI (match_dup 1)
1241 "TARGET_POWERPC && TARGET_32BIT"
1245 [(set_attr "type" "fast_compare")
1246 (set_attr "length" "4,8")])
1249 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1250 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1251 (match_operand:SI 2 "gpc_reg_operand" ""))
1253 (set (match_operand:SI 0 "gpc_reg_operand" "")
1254 (minus:SI (match_dup 1)
1256 "TARGET_32BIT && reload_completed"
1258 (minus:SI (match_dup 1)
1261 (compare:CC (match_dup 0)
1265 (define_expand "subsi3"
1266 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1267 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1268 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1272 if (GET_CODE (operands[2]) == CONST_INT)
1274 emit_insn (gen_addsi3 (operands[0], operands[1],
1275 negate_rtx (SImode, operands[2])));
1280 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1281 ;; instruction and some auxiliary computations. Then we just have a single
1282 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1285 (define_expand "sminsi3"
1287 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1288 (match_operand:SI 2 "reg_or_short_operand" ""))
1290 (minus:SI (match_dup 2) (match_dup 1))))
1291 (set (match_operand:SI 0 "gpc_reg_operand" "")
1292 (minus:SI (match_dup 2) (match_dup 3)))]
1293 "TARGET_POWER || TARGET_ISEL"
1298 operands[2] = force_reg (SImode, operands[2]);
1299 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1303 operands[3] = gen_reg_rtx (SImode);
1307 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1308 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1309 (match_operand:SI 2 "reg_or_short_operand" "")))
1310 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1313 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1315 (minus:SI (match_dup 2) (match_dup 1))))
1316 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1319 (define_expand "smaxsi3"
1321 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1322 (match_operand:SI 2 "reg_or_short_operand" ""))
1324 (minus:SI (match_dup 2) (match_dup 1))))
1325 (set (match_operand:SI 0 "gpc_reg_operand" "")
1326 (plus:SI (match_dup 3) (match_dup 1)))]
1327 "TARGET_POWER || TARGET_ISEL"
1332 operands[2] = force_reg (SImode, operands[2]);
1333 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1336 operands[3] = gen_reg_rtx (SImode);
1340 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1341 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1342 (match_operand:SI 2 "reg_or_short_operand" "")))
1343 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1346 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1348 (minus:SI (match_dup 2) (match_dup 1))))
1349 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1352 (define_expand "uminsi3"
1353 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1355 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1357 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1359 (minus:SI (match_dup 4) (match_dup 3))))
1360 (set (match_operand:SI 0 "gpc_reg_operand" "")
1361 (minus:SI (match_dup 2) (match_dup 3)))]
1362 "TARGET_POWER || TARGET_ISEL"
1367 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1370 operands[3] = gen_reg_rtx (SImode);
1371 operands[4] = gen_reg_rtx (SImode);
1372 operands[5] = GEN_INT (-2147483647 - 1);
1375 (define_expand "umaxsi3"
1376 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1378 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1380 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1382 (minus:SI (match_dup 4) (match_dup 3))))
1383 (set (match_operand:SI 0 "gpc_reg_operand" "")
1384 (plus:SI (match_dup 3) (match_dup 1)))]
1385 "TARGET_POWER || TARGET_ISEL"
1390 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1393 operands[3] = gen_reg_rtx (SImode);
1394 operands[4] = gen_reg_rtx (SImode);
1395 operands[5] = GEN_INT (-2147483647 - 1);
1399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1400 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1401 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1403 (minus:SI (match_dup 2) (match_dup 1))))]
1408 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1410 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1411 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1413 (minus:SI (match_dup 2) (match_dup 1)))
1415 (clobber (match_scratch:SI 3 "=r,r"))]
1420 [(set_attr "type" "delayed_compare")
1421 (set_attr "length" "4,8")])
1424 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1426 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1427 (match_operand:SI 2 "reg_or_short_operand" ""))
1429 (minus:SI (match_dup 2) (match_dup 1)))
1431 (clobber (match_scratch:SI 3 ""))]
1432 "TARGET_POWER && reload_completed"
1434 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1436 (minus:SI (match_dup 2) (match_dup 1))))
1438 (compare:CC (match_dup 3)
1443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1445 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1446 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1448 (minus:SI (match_dup 2) (match_dup 1)))
1450 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1451 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1453 (minus:SI (match_dup 2) (match_dup 1))))]
1458 [(set_attr "type" "delayed_compare")
1459 (set_attr "length" "4,8")])
1462 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1464 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1465 (match_operand:SI 2 "reg_or_short_operand" ""))
1467 (minus:SI (match_dup 2) (match_dup 1)))
1469 (set (match_operand:SI 0 "gpc_reg_operand" "")
1470 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1472 (minus:SI (match_dup 2) (match_dup 1))))]
1473 "TARGET_POWER && reload_completed"
1475 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1477 (minus:SI (match_dup 2) (match_dup 1))))
1479 (compare:CC (match_dup 0)
1483 ;; We don't need abs with condition code because such comparisons should
1485 (define_expand "abssi2"
1486 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1487 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1493 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1496 else if (! TARGET_POWER)
1498 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1503 (define_insn "*abssi2_power"
1504 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1505 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1509 (define_insn_and_split "abssi2_isel"
1510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1511 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1512 (clobber (match_scratch:SI 2 "=&b"))
1513 (clobber (match_scratch:CC 3 "=y"))]
1516 "&& reload_completed"
1517 [(set (match_dup 2) (neg:SI (match_dup 1)))
1519 (compare:CC (match_dup 1)
1522 (if_then_else:SI (ge (match_dup 3)
1528 (define_insn_and_split "abssi2_nopower"
1529 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1530 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1531 (clobber (match_scratch:SI 2 "=&r,&r"))]
1532 "! TARGET_POWER && ! TARGET_ISEL"
1534 "&& reload_completed"
1535 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1536 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1537 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1540 (define_insn "*nabs_power"
1541 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1542 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1546 (define_insn_and_split "*nabs_nopower"
1547 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1548 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1549 (clobber (match_scratch:SI 2 "=&r,&r"))]
1552 "&& reload_completed"
1553 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1554 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1555 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1558 (define_insn "negsi2"
1559 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1560 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1566 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1568 (clobber (match_scratch:SI 2 "=r,r"))]
1573 [(set_attr "type" "fast_compare")
1574 (set_attr "length" "4,8")])
1577 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1578 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1580 (clobber (match_scratch:SI 2 ""))]
1581 "TARGET_32BIT && reload_completed"
1583 (neg:SI (match_dup 1)))
1585 (compare:CC (match_dup 2)
1590 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1591 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1594 (neg:SI (match_dup 1)))]
1599 [(set_attr "type" "fast_compare")
1600 (set_attr "length" "4,8")])
1603 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1604 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1606 (set (match_operand:SI 0 "gpc_reg_operand" "")
1607 (neg:SI (match_dup 1)))]
1608 "TARGET_32BIT && reload_completed"
1610 (neg:SI (match_dup 1)))
1612 (compare:CC (match_dup 0)
1616 (define_insn "clzsi2"
1617 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1618 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1620 "{cntlz|cntlzw} %0,%1")
1622 (define_expand "ctzsi2"
1624 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1625 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1627 (clobber (scratch:CC))])
1628 (set (match_dup 4) (clz:SI (match_dup 3)))
1629 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1630 (minus:SI (const_int 31) (match_dup 4)))]
1633 operands[2] = gen_reg_rtx (SImode);
1634 operands[3] = gen_reg_rtx (SImode);
1635 operands[4] = gen_reg_rtx (SImode);
1638 (define_expand "ffssi2"
1640 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1641 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1643 (clobber (scratch:CC))])
1644 (set (match_dup 4) (clz:SI (match_dup 3)))
1645 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1646 (minus:SI (const_int 32) (match_dup 4)))]
1649 operands[2] = gen_reg_rtx (SImode);
1650 operands[3] = gen_reg_rtx (SImode);
1651 operands[4] = gen_reg_rtx (SImode);
1654 (define_expand "mulsi3"
1655 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1656 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1657 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1662 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1664 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1668 (define_insn "mulsi3_mq"
1669 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1670 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1671 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1672 (clobber (match_scratch:SI 3 "=q,q"))]
1675 {muls|mullw} %0,%1,%2
1676 {muli|mulli} %0,%1,%2"
1678 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1679 (const_string "imul3")
1680 (match_operand:SI 2 "short_cint_operand" "")
1681 (const_string "imul2")]
1682 (const_string "imul")))])
1684 (define_insn "mulsi3_no_mq"
1685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1686 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1687 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1690 {muls|mullw} %0,%1,%2
1691 {muli|mulli} %0,%1,%2"
1693 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1694 (const_string "imul3")
1695 (match_operand:SI 2 "short_cint_operand" "")
1696 (const_string "imul2")]
1697 (const_string "imul")))])
1699 (define_insn "*mulsi3_mq_internal1"
1700 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1701 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1702 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1704 (clobber (match_scratch:SI 3 "=r,r"))
1705 (clobber (match_scratch:SI 4 "=q,q"))]
1708 {muls.|mullw.} %3,%1,%2
1710 [(set_attr "type" "imul_compare")
1711 (set_attr "length" "4,8")])
1714 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1715 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1716 (match_operand:SI 2 "gpc_reg_operand" ""))
1718 (clobber (match_scratch:SI 3 ""))
1719 (clobber (match_scratch:SI 4 ""))]
1720 "TARGET_POWER && reload_completed"
1721 [(parallel [(set (match_dup 3)
1722 (mult:SI (match_dup 1) (match_dup 2)))
1723 (clobber (match_dup 4))])
1725 (compare:CC (match_dup 3)
1729 (define_insn "*mulsi3_no_mq_internal1"
1730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1731 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1732 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1734 (clobber (match_scratch:SI 3 "=r,r"))]
1737 {muls.|mullw.} %3,%1,%2
1739 [(set_attr "type" "imul_compare")
1740 (set_attr "length" "4,8")])
1743 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1744 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1745 (match_operand:SI 2 "gpc_reg_operand" ""))
1747 (clobber (match_scratch:SI 3 ""))]
1748 "! TARGET_POWER && reload_completed"
1750 (mult:SI (match_dup 1) (match_dup 2)))
1752 (compare:CC (match_dup 3)
1756 (define_insn "*mulsi3_mq_internal2"
1757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1758 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1759 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1762 (mult:SI (match_dup 1) (match_dup 2)))
1763 (clobber (match_scratch:SI 4 "=q,q"))]
1766 {muls.|mullw.} %0,%1,%2
1768 [(set_attr "type" "imul_compare")
1769 (set_attr "length" "4,8")])
1772 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1773 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1774 (match_operand:SI 2 "gpc_reg_operand" ""))
1776 (set (match_operand:SI 0 "gpc_reg_operand" "")
1777 (mult:SI (match_dup 1) (match_dup 2)))
1778 (clobber (match_scratch:SI 4 ""))]
1779 "TARGET_POWER && reload_completed"
1780 [(parallel [(set (match_dup 0)
1781 (mult:SI (match_dup 1) (match_dup 2)))
1782 (clobber (match_dup 4))])
1784 (compare:CC (match_dup 0)
1788 (define_insn "*mulsi3_no_mq_internal2"
1789 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1790 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1791 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1794 (mult:SI (match_dup 1) (match_dup 2)))]
1797 {muls.|mullw.} %0,%1,%2
1799 [(set_attr "type" "imul_compare")
1800 (set_attr "length" "4,8")])
1803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1804 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1805 (match_operand:SI 2 "gpc_reg_operand" ""))
1807 (set (match_operand:SI 0 "gpc_reg_operand" "")
1808 (mult:SI (match_dup 1) (match_dup 2)))]
1809 "! TARGET_POWER && reload_completed"
1811 (mult:SI (match_dup 1) (match_dup 2)))
1813 (compare:CC (match_dup 0)
1817 ;; Operand 1 is divided by operand 2; quotient goes to operand
1818 ;; 0 and remainder to operand 3.
1819 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1821 (define_expand "divmodsi4"
1822 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1823 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1824 (match_operand:SI 2 "gpc_reg_operand" "")))
1825 (set (match_operand:SI 3 "register_operand" "")
1826 (mod:SI (match_dup 1) (match_dup 2)))])]
1827 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1830 if (! TARGET_POWER && ! TARGET_POWERPC)
1832 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1833 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1834 emit_insn (gen_divss_call ());
1835 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1836 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
1841 (define_insn "*divmodsi4_internal"
1842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1843 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1844 (match_operand:SI 2 "gpc_reg_operand" "r")))
1845 (set (match_operand:SI 3 "register_operand" "=q")
1846 (mod:SI (match_dup 1) (match_dup 2)))]
1849 [(set_attr "type" "idiv")])
1851 (define_expand "udivsi3"
1852 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1853 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1854 (match_operand:SI 2 "gpc_reg_operand" "")))]
1855 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1858 if (! TARGET_POWER && ! TARGET_POWERPC)
1860 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1861 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1862 emit_insn (gen_quous_call ());
1863 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1866 else if (TARGET_POWER)
1868 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1873 (define_insn "udivsi3_mq"
1874 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1875 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1876 (match_operand:SI 2 "gpc_reg_operand" "r")))
1877 (clobber (match_scratch:SI 3 "=q"))]
1878 "TARGET_POWERPC && TARGET_POWER"
1880 [(set_attr "type" "idiv")])
1882 (define_insn "*udivsi3_no_mq"
1883 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1884 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1885 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1886 "TARGET_POWERPC && ! TARGET_POWER"
1888 [(set_attr "type" "idiv")])
1890 ;; For powers of two we can do srai/aze for divide and then adjust for
1891 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1892 ;; used; for PowerPC, force operands into register and do a normal divide;
1893 ;; for AIX common-mode, use quoss call on register operands.
1894 (define_expand "divsi3"
1895 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1896 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1897 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1901 if (GET_CODE (operands[2]) == CONST_INT
1902 && INTVAL (operands[2]) > 0
1903 && exact_log2 (INTVAL (operands[2])) >= 0)
1905 else if (TARGET_POWERPC)
1907 operands[2] = force_reg (SImode, operands[2]);
1910 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1914 else if (TARGET_POWER)
1918 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1919 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
1920 emit_insn (gen_quoss_call ());
1921 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1926 (define_insn "divsi3_mq"
1927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1928 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1929 (match_operand:SI 2 "gpc_reg_operand" "r")))
1930 (clobber (match_scratch:SI 3 "=q"))]
1931 "TARGET_POWERPC && TARGET_POWER"
1933 [(set_attr "type" "idiv")])
1935 (define_insn "*divsi3_no_mq"
1936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1937 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1938 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1939 "TARGET_POWERPC && ! TARGET_POWER"
1941 [(set_attr "type" "idiv")])
1943 (define_expand "modsi3"
1944 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1945 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1946 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1954 if (GET_CODE (operands[2]) != CONST_INT
1955 || INTVAL (operands[2]) <= 0
1956 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
1959 temp1 = gen_reg_rtx (SImode);
1960 temp2 = gen_reg_rtx (SImode);
1962 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1963 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1964 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1970 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1971 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1973 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1974 [(set_attr "length" "8")])
1977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1978 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1979 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
1981 (clobber (match_scratch:SI 3 "=r,r"))]
1984 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1986 [(set_attr "type" "compare")
1987 (set_attr "length" "8,12")])
1990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1991 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1992 (match_operand:SI 2 "exact_log2_cint_operand" ""))
1994 (clobber (match_scratch:SI 3 ""))]
1997 (div:SI (match_dup 1) (match_dup 2)))
1999 (compare:CC (match_dup 3)
2004 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2005 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2006 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2008 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2009 (div:SI (match_dup 1) (match_dup 2)))]
2012 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2014 [(set_attr "type" "compare")
2015 (set_attr "length" "8,12")])
2018 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2019 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2020 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2022 (set (match_operand:SI 0 "gpc_reg_operand" "")
2023 (div:SI (match_dup 1) (match_dup 2)))]
2026 (div:SI (match_dup 1) (match_dup 2)))
2028 (compare:CC (match_dup 0)
2033 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2036 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2038 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2039 (match_operand:SI 3 "gpc_reg_operand" "r")))
2040 (set (match_operand:SI 2 "register_operand" "=*q")
2043 (zero_extend:DI (match_dup 1)) (const_int 32))
2044 (zero_extend:DI (match_dup 4)))
2048 [(set_attr "type" "idiv")])
2050 ;; To do unsigned divide we handle the cases of the divisor looking like a
2051 ;; negative number. If it is a constant that is less than 2**31, we don't
2052 ;; have to worry about the branches. So make a few subroutines here.
2054 ;; First comes the normal case.
2055 (define_expand "udivmodsi4_normal"
2056 [(set (match_dup 4) (const_int 0))
2057 (parallel [(set (match_operand:SI 0 "" "")
2058 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2060 (zero_extend:DI (match_operand:SI 1 "" "")))
2061 (match_operand:SI 2 "" "")))
2062 (set (match_operand:SI 3 "" "")
2063 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2065 (zero_extend:DI (match_dup 1)))
2069 { operands[4] = gen_reg_rtx (SImode); }")
2071 ;; This handles the branches.
2072 (define_expand "udivmodsi4_tests"
2073 [(set (match_operand:SI 0 "" "") (const_int 0))
2074 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2075 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2076 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2077 (label_ref (match_operand:SI 4 "" "")) (pc)))
2078 (set (match_dup 0) (const_int 1))
2079 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2080 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2081 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2082 (label_ref (match_dup 4)) (pc)))]
2085 { operands[5] = gen_reg_rtx (CCUNSmode);
2086 operands[6] = gen_reg_rtx (CCmode);
2089 (define_expand "udivmodsi4"
2090 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2091 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2092 (match_operand:SI 2 "reg_or_cint_operand" "")))
2093 (set (match_operand:SI 3 "gpc_reg_operand" "")
2094 (umod:SI (match_dup 1) (match_dup 2)))])]
2102 if (! TARGET_POWERPC)
2104 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2105 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2106 emit_insn (gen_divus_call ());
2107 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2108 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2115 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2117 operands[2] = force_reg (SImode, operands[2]);
2118 label = gen_label_rtx ();
2119 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2120 operands[3], label));
2123 operands[2] = force_reg (SImode, operands[2]);
2125 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2133 ;; AIX architecture-independent common-mode multiply (DImode),
2134 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2135 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2136 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2137 ;; assumed unused if generating common-mode, so ignore.
2138 (define_insn "mulh_call"
2141 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2142 (sign_extend:DI (reg:SI 4)))
2144 (clobber (match_scratch:SI 0 "=l"))]
2145 "! TARGET_POWER && ! TARGET_POWERPC"
2147 [(set_attr "type" "imul")])
2149 (define_insn "mull_call"
2151 (mult:DI (sign_extend:DI (reg:SI 3))
2152 (sign_extend:DI (reg:SI 4))))
2153 (clobber (match_scratch:SI 0 "=l"))
2154 (clobber (reg:SI 0))]
2155 "! TARGET_POWER && ! TARGET_POWERPC"
2157 [(set_attr "type" "imul")])
2159 (define_insn "divss_call"
2161 (div:SI (reg:SI 3) (reg:SI 4)))
2163 (mod:SI (reg:SI 3) (reg:SI 4)))
2164 (clobber (match_scratch:SI 0 "=l"))
2165 (clobber (reg:SI 0))]
2166 "! TARGET_POWER && ! TARGET_POWERPC"
2168 [(set_attr "type" "idiv")])
2170 (define_insn "divus_call"
2172 (udiv:SI (reg:SI 3) (reg:SI 4)))
2174 (umod:SI (reg:SI 3) (reg:SI 4)))
2175 (clobber (match_scratch:SI 0 "=l"))
2176 (clobber (reg:SI 0))
2177 (clobber (match_scratch:CC 1 "=x"))
2178 (clobber (reg:CC 69))]
2179 "! TARGET_POWER && ! TARGET_POWERPC"
2181 [(set_attr "type" "idiv")])
2183 (define_insn "quoss_call"
2185 (div:SI (reg:SI 3) (reg:SI 4)))
2186 (clobber (match_scratch:SI 0 "=l"))]
2187 "! TARGET_POWER && ! TARGET_POWERPC"
2189 [(set_attr "type" "idiv")])
2191 (define_insn "quous_call"
2193 (udiv:SI (reg:SI 3) (reg:SI 4)))
2194 (clobber (match_scratch:SI 0 "=l"))
2195 (clobber (reg:SI 0))
2196 (clobber (match_scratch:CC 1 "=x"))
2197 (clobber (reg:CC 69))]
2198 "! TARGET_POWER && ! TARGET_POWERPC"
2200 [(set_attr "type" "idiv")])
2202 ;; Logical instructions
2203 ;; The logical instructions are mostly combined by using match_operator,
2204 ;; but the plain AND insns are somewhat different because there is no
2205 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2206 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2208 (define_insn "andsi3"
2209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2210 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2211 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2212 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2216 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2217 {andil.|andi.} %0,%1,%b2
2218 {andiu.|andis.} %0,%1,%u2")
2220 ;; Note to set cr's other than cr0 we do the and immediate and then
2221 ;; the test again -- this avoids a mfcr which on the higher end
2222 ;; machines causes an execution serialization
2224 (define_insn "*andsi3_internal2"
2225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2226 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2227 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2229 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2230 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2234 {andil.|andi.} %3,%1,%b2
2235 {andiu.|andis.} %3,%1,%u2
2236 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2241 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2242 (set_attr "length" "4,4,4,4,8,8,8,8")])
2244 (define_insn "*andsi3_internal3"
2245 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2246 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2247 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2249 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2250 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2254 {andil.|andi.} %3,%1,%b2
2255 {andiu.|andis.} %3,%1,%u2
2256 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2261 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2262 (set_attr "length" "8,4,4,4,8,8,8,8")])
2265 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2266 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2267 (match_operand:SI 2 "and_operand" ""))
2269 (clobber (match_scratch:SI 3 ""))
2270 (clobber (match_scratch:CC 4 ""))]
2272 [(parallel [(set (match_dup 3)
2273 (and:SI (match_dup 1)
2275 (clobber (match_dup 4))])
2277 (compare:CC (match_dup 3)
2281 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2282 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2285 [(set (match_operand:CC 0 "cc_reg_operand" "")
2286 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2287 (match_operand:SI 2 "gpc_reg_operand" ""))
2289 (clobber (match_scratch:SI 3 ""))
2290 (clobber (match_scratch:CC 4 ""))]
2291 "TARGET_POWERPC64 && reload_completed"
2292 [(parallel [(set (match_dup 3)
2293 (and:SI (match_dup 1)
2295 (clobber (match_dup 4))])
2297 (compare:CC (match_dup 3)
2301 (define_insn "*andsi3_internal4"
2302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2303 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2304 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2307 (and:SI (match_dup 1)
2309 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2313 {andil.|andi.} %0,%1,%b2
2314 {andiu.|andis.} %0,%1,%u2
2315 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2320 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2321 (set_attr "length" "4,4,4,4,8,8,8,8")])
2323 (define_insn "*andsi3_internal5"
2324 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2325 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2326 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2328 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2329 (and:SI (match_dup 1)
2331 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2335 {andil.|andi.} %0,%1,%b2
2336 {andiu.|andis.} %0,%1,%u2
2337 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2342 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2343 (set_attr "length" "8,4,4,4,8,8,8,8")])
2346 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2347 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2348 (match_operand:SI 2 "and_operand" ""))
2350 (set (match_operand:SI 0 "gpc_reg_operand" "")
2351 (and:SI (match_dup 1)
2353 (clobber (match_scratch:CC 4 ""))]
2355 [(parallel [(set (match_dup 0)
2356 (and:SI (match_dup 1)
2358 (clobber (match_dup 4))])
2360 (compare:CC (match_dup 0)
2365 [(set (match_operand:CC 3 "cc_reg_operand" "")
2366 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2367 (match_operand:SI 2 "gpc_reg_operand" ""))
2369 (set (match_operand:SI 0 "gpc_reg_operand" "")
2370 (and:SI (match_dup 1)
2372 (clobber (match_scratch:CC 4 ""))]
2373 "TARGET_POWERPC64 && reload_completed"
2374 [(parallel [(set (match_dup 0)
2375 (and:SI (match_dup 1)
2377 (clobber (match_dup 4))])
2379 (compare:CC (match_dup 0)
2383 ;; Handle the PowerPC64 rlwinm corner case
2385 (define_insn_and_split "*andsi3_internal6"
2386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2387 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2388 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2393 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2396 (rotate:SI (match_dup 0) (match_dup 5)))]
2399 int mb = extract_MB (operands[2]);
2400 int me = extract_ME (operands[2]);
2401 operands[3] = GEN_INT (me + 1);
2402 operands[5] = GEN_INT (32 - (me + 1));
2403 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2405 [(set_attr "length" "8")])
2407 (define_insn_and_split "*andsi3_internal7"
2408 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2409 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2410 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2412 (clobber (match_scratch:SI 3 "=r,r"))]
2416 [(parallel [(set (match_dup 2)
2417 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2420 (clobber (match_dup 3))])]
2423 int mb = extract_MB (operands[1]);
2424 int me = extract_ME (operands[1]);
2425 operands[4] = GEN_INT (me + 1);
2426 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2428 [(set_attr "type" "delayed_compare,compare")
2429 (set_attr "length" "4,8")])
2431 (define_insn_and_split "*andsi3_internal8"
2432 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2433 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2434 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2436 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2437 (and:SI (match_dup 1)
2442 [(parallel [(set (match_dup 3)
2443 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2447 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2450 (rotate:SI (match_dup 0) (match_dup 6)))]
2453 int mb = extract_MB (operands[2]);
2454 int me = extract_ME (operands[2]);
2455 operands[4] = GEN_INT (me + 1);
2456 operands[6] = GEN_INT (32 - (me + 1));
2457 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2459 [(set_attr "type" "delayed_compare,compare")
2460 (set_attr "length" "8,12")])
2462 (define_expand "iorsi3"
2463 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2464 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2465 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2469 if (GET_CODE (operands[2]) == CONST_INT
2470 && ! logical_operand (operands[2], SImode))
2472 HOST_WIDE_INT value = INTVAL (operands[2]);
2473 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2474 ? operands[0] : gen_reg_rtx (SImode));
2476 emit_insn (gen_iorsi3 (tmp, operands[1],
2477 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2478 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2483 (define_expand "xorsi3"
2484 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2485 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2486 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2490 if (GET_CODE (operands[2]) == CONST_INT
2491 && ! logical_operand (operands[2], SImode))
2493 HOST_WIDE_INT value = INTVAL (operands[2]);
2494 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2495 ? operands[0] : gen_reg_rtx (SImode));
2497 emit_insn (gen_xorsi3 (tmp, operands[1],
2498 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2499 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2504 (define_insn "*boolsi3_internal1"
2505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2506 (match_operator:SI 3 "boolean_or_operator"
2507 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2508 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2512 {%q3il|%q3i} %0,%1,%b2
2513 {%q3iu|%q3is} %0,%1,%u2")
2515 (define_insn "*boolsi3_internal2"
2516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2517 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2518 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2519 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2521 (clobber (match_scratch:SI 3 "=r,r"))]
2526 [(set_attr "type" "compare")
2527 (set_attr "length" "4,8")])
2530 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2531 (compare:CC (match_operator:SI 4 "boolean_operator"
2532 [(match_operand:SI 1 "gpc_reg_operand" "")
2533 (match_operand:SI 2 "gpc_reg_operand" "")])
2535 (clobber (match_scratch:SI 3 ""))]
2536 "TARGET_32BIT && reload_completed"
2537 [(set (match_dup 3) (match_dup 4))
2539 (compare:CC (match_dup 3)
2543 (define_insn "*boolsi3_internal3"
2544 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2545 (compare:CC (match_operator:SI 4 "boolean_operator"
2546 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2547 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2549 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2555 [(set_attr "type" "compare")
2556 (set_attr "length" "4,8")])
2559 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2560 (compare:CC (match_operator:SI 4 "boolean_operator"
2561 [(match_operand:SI 1 "gpc_reg_operand" "")
2562 (match_operand:SI 2 "gpc_reg_operand" "")])
2564 (set (match_operand:SI 0 "gpc_reg_operand" "")
2566 "TARGET_32BIT && reload_completed"
2567 [(set (match_dup 0) (match_dup 4))
2569 (compare:CC (match_dup 0)
2573 ;; Split a logical operation that we can't do in one insn into two insns,
2574 ;; each of which does one 16-bit part. This is used by combine.
2577 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2578 (match_operator:SI 3 "boolean_or_operator"
2579 [(match_operand:SI 1 "gpc_reg_operand" "")
2580 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2582 [(set (match_dup 0) (match_dup 4))
2583 (set (match_dup 0) (match_dup 5))]
2587 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2588 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2590 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2591 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2595 (define_insn "*boolcsi3_internal1"
2596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2597 (match_operator:SI 3 "boolean_operator"
2598 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2599 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2603 (define_insn "*boolcsi3_internal2"
2604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2605 (compare:CC (match_operator:SI 4 "boolean_operator"
2606 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2607 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2609 (clobber (match_scratch:SI 3 "=r,r"))]
2614 [(set_attr "type" "compare")
2615 (set_attr "length" "4,8")])
2618 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2619 (compare:CC (match_operator:SI 4 "boolean_operator"
2620 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2621 (match_operand:SI 2 "gpc_reg_operand" "")])
2623 (clobber (match_scratch:SI 3 ""))]
2624 "TARGET_32BIT && reload_completed"
2625 [(set (match_dup 3) (match_dup 4))
2627 (compare:CC (match_dup 3)
2631 (define_insn "*boolcsi3_internal3"
2632 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2633 (compare:CC (match_operator:SI 4 "boolean_operator"
2634 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2635 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2637 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2643 [(set_attr "type" "compare")
2644 (set_attr "length" "4,8")])
2647 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2648 (compare:CC (match_operator:SI 4 "boolean_operator"
2649 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2650 (match_operand:SI 2 "gpc_reg_operand" "")])
2652 (set (match_operand:SI 0 "gpc_reg_operand" "")
2654 "TARGET_32BIT && reload_completed"
2655 [(set (match_dup 0) (match_dup 4))
2657 (compare:CC (match_dup 0)
2661 (define_insn "*boolccsi3_internal1"
2662 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2663 (match_operator:SI 3 "boolean_operator"
2664 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2665 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2669 (define_insn "*boolccsi3_internal2"
2670 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2671 (compare:CC (match_operator:SI 4 "boolean_operator"
2672 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2673 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2675 (clobber (match_scratch:SI 3 "=r,r"))]
2680 [(set_attr "type" "compare")
2681 (set_attr "length" "4,8")])
2684 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2685 (compare:CC (match_operator:SI 4 "boolean_operator"
2686 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2687 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2689 (clobber (match_scratch:SI 3 ""))]
2690 "TARGET_32BIT && reload_completed"
2691 [(set (match_dup 3) (match_dup 4))
2693 (compare:CC (match_dup 3)
2697 (define_insn "*boolccsi3_internal3"
2698 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2699 (compare:CC (match_operator:SI 4 "boolean_operator"
2700 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2701 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2703 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2709 [(set_attr "type" "compare")
2710 (set_attr "length" "4,8")])
2713 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2714 (compare:CC (match_operator:SI 4 "boolean_operator"
2715 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2716 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2718 (set (match_operand:SI 0 "gpc_reg_operand" "")
2720 "TARGET_32BIT && reload_completed"
2721 [(set (match_dup 0) (match_dup 4))
2723 (compare:CC (match_dup 0)
2727 ;; maskir insn. We need four forms because things might be in arbitrary
2728 ;; orders. Don't define forms that only set CR fields because these
2729 ;; would modify an input register.
2731 (define_insn "*maskir_internal1"
2732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2733 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2734 (match_operand:SI 1 "gpc_reg_operand" "0"))
2735 (and:SI (match_dup 2)
2736 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2740 (define_insn "*maskir_internal2"
2741 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2742 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2743 (match_operand:SI 1 "gpc_reg_operand" "0"))
2744 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2749 (define_insn "*maskir_internal3"
2750 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2751 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2752 (match_operand:SI 3 "gpc_reg_operand" "r"))
2753 (and:SI (not:SI (match_dup 2))
2754 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2758 (define_insn "*maskir_internal4"
2759 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2760 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2761 (match_operand:SI 2 "gpc_reg_operand" "r"))
2762 (and:SI (not:SI (match_dup 2))
2763 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2767 (define_insn "*maskir_internal5"
2768 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2770 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2771 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2772 (and:SI (match_dup 2)
2773 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2775 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2776 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2777 (and:SI (match_dup 2) (match_dup 3))))]
2782 [(set_attr "type" "compare")
2783 (set_attr "length" "4,8")])
2786 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2788 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2789 (match_operand:SI 1 "gpc_reg_operand" ""))
2790 (and:SI (match_dup 2)
2791 (match_operand:SI 3 "gpc_reg_operand" "")))
2793 (set (match_operand:SI 0 "gpc_reg_operand" "")
2794 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2795 (and:SI (match_dup 2) (match_dup 3))))]
2796 "TARGET_POWER && reload_completed"
2798 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2799 (and:SI (match_dup 2) (match_dup 3))))
2801 (compare:CC (match_dup 0)
2805 (define_insn "*maskir_internal6"
2806 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2808 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2809 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2810 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2813 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2814 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2815 (and:SI (match_dup 3) (match_dup 2))))]
2820 [(set_attr "type" "compare")
2821 (set_attr "length" "4,8")])
2824 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2826 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2827 (match_operand:SI 1 "gpc_reg_operand" ""))
2828 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2831 (set (match_operand:SI 0 "gpc_reg_operand" "")
2832 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2833 (and:SI (match_dup 3) (match_dup 2))))]
2834 "TARGET_POWER && reload_completed"
2836 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2837 (and:SI (match_dup 3) (match_dup 2))))
2839 (compare:CC (match_dup 0)
2843 (define_insn "*maskir_internal7"
2844 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2846 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2847 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
2848 (and:SI (not:SI (match_dup 2))
2849 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2851 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2852 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2853 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2858 [(set_attr "type" "compare")
2859 (set_attr "length" "4,8")])
2862 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2864 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2865 (match_operand:SI 3 "gpc_reg_operand" ""))
2866 (and:SI (not:SI (match_dup 2))
2867 (match_operand:SI 1 "gpc_reg_operand" "")))
2869 (set (match_operand:SI 0 "gpc_reg_operand" "")
2870 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2871 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2872 "TARGET_POWER && reload_completed"
2874 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2875 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2877 (compare:CC (match_dup 0)
2881 (define_insn "*maskir_internal8"
2882 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2884 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2885 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2886 (and:SI (not:SI (match_dup 2))
2887 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
2889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2890 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2891 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2896 [(set_attr "type" "compare")
2897 (set_attr "length" "4,8")])
2900 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2902 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2903 (match_operand:SI 2 "gpc_reg_operand" ""))
2904 (and:SI (not:SI (match_dup 2))
2905 (match_operand:SI 1 "gpc_reg_operand" "")))
2907 (set (match_operand:SI 0 "gpc_reg_operand" "")
2908 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2909 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2910 "TARGET_POWER && reload_completed"
2912 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2913 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2915 (compare:CC (match_dup 0)
2919 ;; Rotate and shift insns, in all their variants. These support shifts,
2920 ;; field inserts and extracts, and various combinations thereof.
2921 (define_expand "insv"
2922 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2923 (match_operand:SI 1 "const_int_operand" "")
2924 (match_operand:SI 2 "const_int_operand" ""))
2925 (match_operand 3 "gpc_reg_operand" ""))]
2929 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2930 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2931 compiler if the address of the structure is taken later. */
2932 if (GET_CODE (operands[0]) == SUBREG
2933 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2936 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2937 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2939 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2943 (define_insn "insvsi"
2944 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2945 (match_operand:SI 1 "const_int_operand" "i")
2946 (match_operand:SI 2 "const_int_operand" "i"))
2947 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2951 int start = INTVAL (operands[2]) & 31;
2952 int size = INTVAL (operands[1]) & 31;
2954 operands[4] = GEN_INT (32 - start - size);
2955 operands[1] = GEN_INT (start + size - 1);
2956 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2958 [(set_attr "type" "insert_word")])
2960 (define_insn "*insvsi_internal1"
2961 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2962 (match_operand:SI 1 "const_int_operand" "i")
2963 (match_operand:SI 2 "const_int_operand" "i"))
2964 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2965 (match_operand:SI 4 "const_int_operand" "i")))]
2966 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2969 int shift = INTVAL (operands[4]) & 31;
2970 int start = INTVAL (operands[2]) & 31;
2971 int size = INTVAL (operands[1]) & 31;
2973 operands[4] = GEN_INT (shift - start - size);
2974 operands[1] = GEN_INT (start + size - 1);
2975 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2977 [(set_attr "type" "insert_word")])
2979 (define_insn "*insvsi_internal2"
2980 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2981 (match_operand:SI 1 "const_int_operand" "i")
2982 (match_operand:SI 2 "const_int_operand" "i"))
2983 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2984 (match_operand:SI 4 "const_int_operand" "i")))]
2985 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
2988 int shift = INTVAL (operands[4]) & 31;
2989 int start = INTVAL (operands[2]) & 31;
2990 int size = INTVAL (operands[1]) & 31;
2992 operands[4] = GEN_INT (32 - shift - start - size);
2993 operands[1] = GEN_INT (start + size - 1);
2994 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
2996 [(set_attr "type" "insert_word")])
2998 (define_insn "*insvsi_internal3"
2999 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3000 (match_operand:SI 1 "const_int_operand" "i")
3001 (match_operand:SI 2 "const_int_operand" "i"))
3002 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3003 (match_operand:SI 4 "const_int_operand" "i")))]
3004 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3007 int shift = INTVAL (operands[4]) & 31;
3008 int start = INTVAL (operands[2]) & 31;
3009 int size = INTVAL (operands[1]) & 31;
3011 operands[4] = GEN_INT (32 - shift - start - size);
3012 operands[1] = GEN_INT (start + size - 1);
3013 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3015 [(set_attr "type" "insert_word")])
3017 (define_insn "*insvsi_internal4"
3018 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3019 (match_operand:SI 1 "const_int_operand" "i")
3020 (match_operand:SI 2 "const_int_operand" "i"))
3021 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3022 (match_operand:SI 4 "const_int_operand" "i")
3023 (match_operand:SI 5 "const_int_operand" "i")))]
3024 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3027 int extract_start = INTVAL (operands[5]) & 31;
3028 int extract_size = INTVAL (operands[4]) & 31;
3029 int insert_start = INTVAL (operands[2]) & 31;
3030 int insert_size = INTVAL (operands[1]) & 31;
3032 /* Align extract field with insert field */
3033 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3034 operands[1] = GEN_INT (insert_start + insert_size - 1);
3035 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3037 [(set_attr "type" "insert_word")])
3039 (define_insn "insvdi"
3040 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3041 (match_operand:SI 1 "const_int_operand" "i")
3042 (match_operand:SI 2 "const_int_operand" "i"))
3043 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3047 int start = INTVAL (operands[2]) & 63;
3048 int size = INTVAL (operands[1]) & 63;
3050 operands[1] = GEN_INT (64 - start - size);
3051 return \"rldimi %0,%3,%H1,%H2\";
3054 (define_expand "extzv"
3055 [(set (match_operand 0 "gpc_reg_operand" "")
3056 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3057 (match_operand:SI 2 "const_int_operand" "")
3058 (match_operand:SI 3 "const_int_operand" "")))]
3062 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3063 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3064 compiler if the address of the structure is taken later. */
3065 if (GET_CODE (operands[0]) == SUBREG
3066 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3069 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3070 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3072 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3076 (define_insn "extzvsi"
3077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3078 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3079 (match_operand:SI 2 "const_int_operand" "i")
3080 (match_operand:SI 3 "const_int_operand" "i")))]
3084 int start = INTVAL (operands[3]) & 31;
3085 int size = INTVAL (operands[2]) & 31;
3087 if (start + size >= 32)
3088 operands[3] = const0_rtx;
3090 operands[3] = GEN_INT (start + size);
3091 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3094 (define_insn "*extzvsi_internal1"
3095 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3096 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3097 (match_operand:SI 2 "const_int_operand" "i,i")
3098 (match_operand:SI 3 "const_int_operand" "i,i"))
3100 (clobber (match_scratch:SI 4 "=r,r"))]
3104 int start = INTVAL (operands[3]) & 31;
3105 int size = INTVAL (operands[2]) & 31;
3107 /* Force split for non-cc0 compare. */
3108 if (which_alternative == 1)
3111 /* If the bit-field being tested fits in the upper or lower half of a
3112 word, it is possible to use andiu. or andil. to test it. This is
3113 useful because the condition register set-use delay is smaller for
3114 andi[ul]. than for rlinm. This doesn't work when the starting bit
3115 position is 0 because the LT and GT bits may be set wrong. */
3117 if ((start > 0 && start + size <= 16) || start >= 16)
3119 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3120 - (1 << (16 - (start & 15) - size))));
3122 return \"{andiu.|andis.} %4,%1,%3\";
3124 return \"{andil.|andi.} %4,%1,%3\";
3127 if (start + size >= 32)
3128 operands[3] = const0_rtx;
3130 operands[3] = GEN_INT (start + size);
3131 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3133 [(set_attr "type" "compare")
3134 (set_attr "length" "4,8")])
3137 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3138 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3139 (match_operand:SI 2 "const_int_operand" "")
3140 (match_operand:SI 3 "const_int_operand" ""))
3142 (clobber (match_scratch:SI 4 ""))]
3145 (zero_extract:SI (match_dup 1) (match_dup 2)
3148 (compare:CC (match_dup 4)
3152 (define_insn "*extzvsi_internal2"
3153 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3154 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3155 (match_operand:SI 2 "const_int_operand" "i,i")
3156 (match_operand:SI 3 "const_int_operand" "i,i"))
3158 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3159 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3163 int start = INTVAL (operands[3]) & 31;
3164 int size = INTVAL (operands[2]) & 31;
3166 /* Force split for non-cc0 compare. */
3167 if (which_alternative == 1)
3170 /* Since we are using the output value, we can't ignore any need for
3171 a shift. The bit-field must end at the LSB. */
3172 if (start >= 16 && start + size == 32)
3174 operands[3] = GEN_INT ((1 << size) - 1);
3175 return \"{andil.|andi.} %0,%1,%3\";
3178 if (start + size >= 32)
3179 operands[3] = const0_rtx;
3181 operands[3] = GEN_INT (start + size);
3182 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3184 [(set_attr "type" "compare")
3185 (set_attr "length" "4,8")])
3188 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3189 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3190 (match_operand:SI 2 "const_int_operand" "")
3191 (match_operand:SI 3 "const_int_operand" ""))
3193 (set (match_operand:SI 0 "gpc_reg_operand" "")
3194 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3197 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3199 (compare:CC (match_dup 0)
3203 (define_insn "extzvdi"
3204 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3205 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3206 (match_operand:SI 2 "const_int_operand" "i")
3207 (match_operand:SI 3 "const_int_operand" "i")))]
3211 int start = INTVAL (operands[3]) & 63;
3212 int size = INTVAL (operands[2]) & 63;
3214 if (start + size >= 64)
3215 operands[3] = const0_rtx;
3217 operands[3] = GEN_INT (start + size);
3218 operands[2] = GEN_INT (64 - size);
3219 return \"rldicl %0,%1,%3,%2\";
3222 (define_insn "*extzvdi_internal1"
3223 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3224 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3225 (match_operand:SI 2 "const_int_operand" "i")
3226 (match_operand:SI 3 "const_int_operand" "i"))
3228 (clobber (match_scratch:DI 4 "=r"))]
3232 int start = INTVAL (operands[3]) & 63;
3233 int size = INTVAL (operands[2]) & 63;
3235 if (start + size >= 64)
3236 operands[3] = const0_rtx;
3238 operands[3] = GEN_INT (start + size);
3239 operands[2] = GEN_INT (64 - size);
3240 return \"rldicl. %4,%1,%3,%2\";
3243 (define_insn "*extzvdi_internal2"
3244 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3245 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3246 (match_operand:SI 2 "const_int_operand" "i")
3247 (match_operand:SI 3 "const_int_operand" "i"))
3249 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3250 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3254 int start = INTVAL (operands[3]) & 63;
3255 int size = INTVAL (operands[2]) & 63;
3257 if (start + size >= 64)
3258 operands[3] = const0_rtx;
3260 operands[3] = GEN_INT (start + size);
3261 operands[2] = GEN_INT (64 - size);
3262 return \"rldicl. %0,%1,%3,%2\";
3265 (define_insn "rotlsi3"
3266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3267 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3268 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3270 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3272 (define_insn "*rotlsi3_internal2"
3273 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3274 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3275 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3277 (clobber (match_scratch:SI 3 "=r,r"))]
3280 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3282 [(set_attr "type" "delayed_compare")
3283 (set_attr "length" "4,8")])
3286 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3287 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3288 (match_operand:SI 2 "reg_or_cint_operand" ""))
3290 (clobber (match_scratch:SI 3 ""))]
3293 (rotate:SI (match_dup 1) (match_dup 2)))
3295 (compare:CC (match_dup 3)
3299 (define_insn "*rotlsi3_internal3"
3300 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3301 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3302 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3304 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3305 (rotate:SI (match_dup 1) (match_dup 2)))]
3308 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3310 [(set_attr "type" "delayed_compare")
3311 (set_attr "length" "4,8")])
3314 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3315 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3316 (match_operand:SI 2 "reg_or_cint_operand" ""))
3318 (set (match_operand:SI 0 "gpc_reg_operand" "")
3319 (rotate:SI (match_dup 1) (match_dup 2)))]
3322 (rotate:SI (match_dup 1) (match_dup 2)))
3324 (compare:CC (match_dup 0)
3328 (define_insn "*rotlsi3_internal4"
3329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3330 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3331 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3332 (match_operand:SI 3 "mask_operand" "n")))]
3334 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3336 (define_insn "*rotlsi3_internal5"
3337 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3339 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3340 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3341 (match_operand:SI 3 "mask_operand" "n,n"))
3343 (clobber (match_scratch:SI 4 "=r,r"))]
3346 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3348 [(set_attr "type" "delayed_compare")
3349 (set_attr "length" "4,8")])
3352 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3354 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3355 (match_operand:SI 2 "reg_or_cint_operand" ""))
3356 (match_operand:SI 3 "mask_operand" ""))
3358 (clobber (match_scratch:SI 4 ""))]
3361 (and:SI (rotate:SI (match_dup 1)
3365 (compare:CC (match_dup 4)
3369 (define_insn "*rotlsi3_internal6"
3370 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3372 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3373 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3374 (match_operand:SI 3 "mask_operand" "n,n"))
3376 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3377 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3380 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3382 [(set_attr "type" "delayed_compare")
3383 (set_attr "length" "4,8")])
3386 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3388 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3389 (match_operand:SI 2 "reg_or_cint_operand" ""))
3390 (match_operand:SI 3 "mask_operand" ""))
3392 (set (match_operand:SI 0 "gpc_reg_operand" "")
3393 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3396 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3398 (compare:CC (match_dup 0)
3402 (define_insn "*rotlsi3_internal7"
3403 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3406 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3407 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3409 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3411 (define_insn "*rotlsi3_internal8"
3412 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3413 (compare:CC (zero_extend:SI
3415 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3416 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3418 (clobber (match_scratch:SI 3 "=r,r"))]
3421 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3423 [(set_attr "type" "delayed_compare")
3424 (set_attr "length" "4,8")])
3427 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3428 (compare:CC (zero_extend:SI
3430 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3431 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3433 (clobber (match_scratch:SI 3 ""))]
3436 (zero_extend:SI (subreg:QI
3437 (rotate:SI (match_dup 1)
3440 (compare:CC (match_dup 3)
3444 (define_insn "*rotlsi3_internal9"
3445 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3446 (compare:CC (zero_extend:SI
3448 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3449 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3451 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3452 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3455 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3457 [(set_attr "type" "delayed_compare")
3458 (set_attr "length" "4,8")])
3461 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3462 (compare:CC (zero_extend:SI
3464 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3465 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3467 (set (match_operand:SI 0 "gpc_reg_operand" "")
3468 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3471 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3473 (compare:CC (match_dup 0)
3477 (define_insn "*rotlsi3_internal10"
3478 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3481 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3482 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3484 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3486 (define_insn "*rotlsi3_internal11"
3487 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3488 (compare:CC (zero_extend:SI
3490 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3491 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3493 (clobber (match_scratch:SI 3 "=r,r"))]
3496 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3498 [(set_attr "type" "delayed_compare")
3499 (set_attr "length" "4,8")])
3502 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3503 (compare:CC (zero_extend:SI
3505 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3506 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3508 (clobber (match_scratch:SI 3 ""))]
3511 (zero_extend:SI (subreg:HI
3512 (rotate:SI (match_dup 1)
3515 (compare:CC (match_dup 3)
3519 (define_insn "*rotlsi3_internal12"
3520 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3521 (compare:CC (zero_extend:SI
3523 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3524 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3526 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3527 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3530 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3532 [(set_attr "type" "delayed_compare")
3533 (set_attr "length" "4,8")])
3536 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3537 (compare:CC (zero_extend:SI
3539 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3540 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3542 (set (match_operand:SI 0 "gpc_reg_operand" "")
3543 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3546 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3548 (compare:CC (match_dup 0)
3552 ;; Note that we use "sle." instead of "sl." so that we can set
3553 ;; SHIFT_COUNT_TRUNCATED.
3555 (define_expand "ashlsi3"
3556 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3557 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3558 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3563 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3565 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3569 (define_insn "ashlsi3_power"
3570 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3571 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3572 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3573 (clobber (match_scratch:SI 3 "=q,X"))]
3577 {sli|slwi} %0,%1,%h2")
3579 (define_insn "ashlsi3_no_power"
3580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3581 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3582 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3584 "{sl|slw}%I2 %0,%1,%h2")
3587 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3588 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3589 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3591 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3592 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3596 {sli.|slwi.} %3,%1,%h2
3599 [(set_attr "type" "delayed_compare")
3600 (set_attr "length" "4,4,8,8")])
3603 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3604 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3605 (match_operand:SI 2 "reg_or_cint_operand" ""))
3607 (clobber (match_scratch:SI 3 ""))
3608 (clobber (match_scratch:SI 4 ""))]
3609 "TARGET_POWER && reload_completed"
3610 [(parallel [(set (match_dup 3)
3611 (ashift:SI (match_dup 1) (match_dup 2)))
3612 (clobber (match_dup 4))])
3614 (compare:CC (match_dup 3)
3619 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3620 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3621 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3623 (clobber (match_scratch:SI 3 "=r,r"))]
3624 "! TARGET_POWER && TARGET_32BIT"
3626 {sl|slw}%I2. %3,%1,%h2
3628 [(set_attr "type" "delayed_compare")
3629 (set_attr "length" "4,8")])
3632 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3633 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3634 (match_operand:SI 2 "reg_or_cint_operand" ""))
3636 (clobber (match_scratch:SI 3 ""))]
3637 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3639 (ashift:SI (match_dup 1) (match_dup 2)))
3641 (compare:CC (match_dup 3)
3646 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3647 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3648 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3650 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3651 (ashift:SI (match_dup 1) (match_dup 2)))
3652 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3656 {sli.|slwi.} %0,%1,%h2
3659 [(set_attr "type" "delayed_compare")
3660 (set_attr "length" "4,4,8,8")])
3663 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3664 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3665 (match_operand:SI 2 "reg_or_cint_operand" ""))
3667 (set (match_operand:SI 0 "gpc_reg_operand" "")
3668 (ashift:SI (match_dup 1) (match_dup 2)))
3669 (clobber (match_scratch:SI 4 ""))]
3670 "TARGET_POWER && reload_completed"
3671 [(parallel [(set (match_dup 0)
3672 (ashift:SI (match_dup 1) (match_dup 2)))
3673 (clobber (match_dup 4))])
3675 (compare:CC (match_dup 0)
3680 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3681 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3682 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3684 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3685 (ashift:SI (match_dup 1) (match_dup 2)))]
3686 "! TARGET_POWER && TARGET_32BIT"
3688 {sl|slw}%I2. %0,%1,%h2
3690 [(set_attr "type" "delayed_compare")
3691 (set_attr "length" "4,8")])
3694 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3695 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3696 (match_operand:SI 2 "reg_or_cint_operand" ""))
3698 (set (match_operand:SI 0 "gpc_reg_operand" "")
3699 (ashift:SI (match_dup 1) (match_dup 2)))]
3700 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3702 (ashift:SI (match_dup 1) (match_dup 2)))
3704 (compare:CC (match_dup 0)
3709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3710 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3711 (match_operand:SI 2 "const_int_operand" "i"))
3712 (match_operand:SI 3 "mask_operand" "n")))]
3713 "includes_lshift_p (operands[2], operands[3])"
3714 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3717 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3719 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3720 (match_operand:SI 2 "const_int_operand" "i,i"))
3721 (match_operand:SI 3 "mask_operand" "n,n"))
3723 (clobber (match_scratch:SI 4 "=r,r"))]
3724 "includes_lshift_p (operands[2], operands[3])"
3726 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3728 [(set_attr "type" "delayed_compare")
3729 (set_attr "length" "4,8")])
3732 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3734 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3735 (match_operand:SI 2 "const_int_operand" ""))
3736 (match_operand:SI 3 "mask_operand" ""))
3738 (clobber (match_scratch:SI 4 ""))]
3739 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3741 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3744 (compare:CC (match_dup 4)
3749 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3751 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3752 (match_operand:SI 2 "const_int_operand" "i,i"))
3753 (match_operand:SI 3 "mask_operand" "n,n"))
3755 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3756 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3757 "includes_lshift_p (operands[2], operands[3])"
3759 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3761 [(set_attr "type" "delayed_compare")
3762 (set_attr "length" "4,8")])
3765 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3767 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3768 (match_operand:SI 2 "const_int_operand" ""))
3769 (match_operand:SI 3 "mask_operand" ""))
3771 (set (match_operand:SI 0 "gpc_reg_operand" "")
3772 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3773 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3775 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3777 (compare:CC (match_dup 0)
3781 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3783 (define_expand "lshrsi3"
3784 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3785 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3786 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3791 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3793 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3797 (define_insn "lshrsi3_power"
3798 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3799 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3800 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3801 (clobber (match_scratch:SI 3 "=q,X,X"))]
3806 {s%A2i|s%A2wi} %0,%1,%h2")
3808 (define_insn "lshrsi3_no_power"
3809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3810 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3811 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
3815 {sr|srw}%I2 %0,%1,%h2")
3818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3819 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3820 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3822 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3823 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3828 {s%A2i.|s%A2wi.} %3,%1,%h2
3832 [(set_attr "type" "delayed_compare")
3833 (set_attr "length" "4,4,4,8,8,8")])
3836 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3837 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3838 (match_operand:SI 2 "reg_or_cint_operand" ""))
3840 (clobber (match_scratch:SI 3 ""))
3841 (clobber (match_scratch:SI 4 ""))]
3842 "TARGET_POWER && reload_completed"
3843 [(parallel [(set (match_dup 3)
3844 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3845 (clobber (match_dup 4))])
3847 (compare:CC (match_dup 3)
3852 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3853 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3854 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3856 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
3857 "! TARGET_POWER && TARGET_32BIT"
3860 {sr|srw}%I2. %3,%1,%h2
3863 [(set_attr "type" "delayed_compare")
3864 (set_attr "length" "4,4,8,8")])
3867 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3868 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3869 (match_operand:SI 2 "reg_or_cint_operand" ""))
3871 (clobber (match_scratch:SI 3 ""))]
3872 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3874 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3876 (compare:CC (match_dup 3)
3881 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3882 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3883 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
3885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
3886 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3887 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
3892 {s%A2i.|s%A2wi.} %0,%1,%h2
3896 [(set_attr "type" "delayed_compare")
3897 (set_attr "length" "4,4,4,8,8,8")])
3900 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3901 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3902 (match_operand:SI 2 "reg_or_cint_operand" ""))
3904 (set (match_operand:SI 0 "gpc_reg_operand" "")
3905 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3906 (clobber (match_scratch:SI 4 ""))]
3907 "TARGET_POWER && reload_completed"
3908 [(parallel [(set (match_dup 0)
3909 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3910 (clobber (match_dup 4))])
3912 (compare:CC (match_dup 0)
3917 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3918 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3919 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
3921 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3922 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3923 "! TARGET_POWER && TARGET_32BIT"
3926 {sr|srw}%I2. %0,%1,%h2
3929 [(set_attr "type" "delayed_compare")
3930 (set_attr "length" "4,4,8,8")])
3933 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3934 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3935 (match_operand:SI 2 "reg_or_cint_operand" ""))
3937 (set (match_operand:SI 0 "gpc_reg_operand" "")
3938 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3939 "! TARGET_POWER && TARGET_32BIT && reload_completed"
3941 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3943 (compare:CC (match_dup 0)
3948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3949 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3950 (match_operand:SI 2 "const_int_operand" "i"))
3951 (match_operand:SI 3 "mask_operand" "n")))]
3952 "includes_rshift_p (operands[2], operands[3])"
3953 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
3956 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3958 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3959 (match_operand:SI 2 "const_int_operand" "i,i"))
3960 (match_operand:SI 3 "mask_operand" "n,n"))
3962 (clobber (match_scratch:SI 4 "=r,r"))]
3963 "includes_rshift_p (operands[2], operands[3])"
3965 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3967 [(set_attr "type" "delayed_compare")
3968 (set_attr "length" "4,8")])
3971 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3973 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3974 (match_operand:SI 2 "const_int_operand" ""))
3975 (match_operand:SI 3 "mask_operand" ""))
3977 (clobber (match_scratch:SI 4 ""))]
3978 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
3980 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3983 (compare:CC (match_dup 4)
3988 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3990 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3991 (match_operand:SI 2 "const_int_operand" "i,i"))
3992 (match_operand:SI 3 "mask_operand" "n,n"))
3994 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3995 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3996 "includes_rshift_p (operands[2], operands[3])"
3998 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4000 [(set_attr "type" "delayed_compare")
4001 (set_attr "length" "4,8")])
4004 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4006 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4007 (match_operand:SI 2 "const_int_operand" ""))
4008 (match_operand:SI 3 "mask_operand" ""))
4010 (set (match_operand:SI 0 "gpc_reg_operand" "")
4011 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4012 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4014 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4016 (compare:CC (match_dup 0)
4021 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4024 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4025 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4026 "includes_rshift_p (operands[2], GEN_INT (255))"
4027 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4034 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4035 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4037 (clobber (match_scratch:SI 3 "=r,r"))]
4038 "includes_rshift_p (operands[2], GEN_INT (255))"
4040 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4042 [(set_attr "type" "delayed_compare")
4043 (set_attr "length" "4,8")])
4046 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4050 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4051 (match_operand:SI 2 "const_int_operand" "")) 0))
4053 (clobber (match_scratch:SI 3 ""))]
4054 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4056 (zero_extend:SI (subreg:QI
4057 (lshiftrt:SI (match_dup 1)
4060 (compare:CC (match_dup 3)
4065 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4069 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4070 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4072 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4073 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4074 "includes_rshift_p (operands[2], GEN_INT (255))"
4076 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4078 [(set_attr "type" "delayed_compare")
4079 (set_attr "length" "4,8")])
4082 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4086 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4087 (match_operand:SI 2 "const_int_operand" "")) 0))
4089 (set (match_operand:SI 0 "gpc_reg_operand" "")
4090 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4091 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4093 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4095 (compare:CC (match_dup 0)
4100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4103 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4104 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4105 "includes_rshift_p (operands[2], GEN_INT (65535))"
4106 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4109 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4113 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4114 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4116 (clobber (match_scratch:SI 3 "=r,r"))]
4117 "includes_rshift_p (operands[2], GEN_INT (65535))"
4119 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4121 [(set_attr "type" "delayed_compare")
4122 (set_attr "length" "4,8")])
4125 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4129 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4130 (match_operand:SI 2 "const_int_operand" "")) 0))
4132 (clobber (match_scratch:SI 3 ""))]
4133 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4135 (zero_extend:SI (subreg:HI
4136 (lshiftrt:SI (match_dup 1)
4139 (compare:CC (match_dup 3)
4144 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4148 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4149 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4151 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4152 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4153 "includes_rshift_p (operands[2], GEN_INT (65535))"
4155 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4157 [(set_attr "type" "delayed_compare")
4158 (set_attr "length" "4,8")])
4161 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4165 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4166 (match_operand:SI 2 "const_int_operand" "")) 0))
4168 (set (match_operand:SI 0 "gpc_reg_operand" "")
4169 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4170 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4172 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4174 (compare:CC (match_dup 0)
4179 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4181 (match_operand:SI 1 "gpc_reg_operand" "r"))
4182 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4188 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4190 (match_operand:SI 1 "gpc_reg_operand" "r"))
4191 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4197 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4199 (match_operand:SI 1 "gpc_reg_operand" "r"))
4200 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4206 (define_expand "ashrsi3"
4207 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4208 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4209 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4214 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4216 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4220 (define_insn "ashrsi3_power"
4221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4222 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4223 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4224 (clobber (match_scratch:SI 3 "=q,X"))]
4228 {srai|srawi} %0,%1,%h2")
4230 (define_insn "ashrsi3_no_power"
4231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4232 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4233 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4235 "{sra|sraw}%I2 %0,%1,%h2")
4238 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4239 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4240 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4242 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4243 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4247 {srai.|srawi.} %3,%1,%h2
4250 [(set_attr "type" "delayed_compare")
4251 (set_attr "length" "4,4,8,8")])
4254 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4255 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4256 (match_operand:SI 2 "reg_or_cint_operand" ""))
4258 (clobber (match_scratch:SI 3 ""))
4259 (clobber (match_scratch:SI 4 ""))]
4260 "TARGET_POWER && reload_completed"
4261 [(parallel [(set (match_dup 3)
4262 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4263 (clobber (match_dup 4))])
4265 (compare:CC (match_dup 3)
4270 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4271 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4272 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4274 (clobber (match_scratch:SI 3 "=r,r"))]
4277 {sra|sraw}%I2. %3,%1,%h2
4279 [(set_attr "type" "delayed_compare")
4280 (set_attr "length" "4,8")])
4283 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4284 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4285 (match_operand:SI 2 "reg_or_cint_operand" ""))
4287 (clobber (match_scratch:SI 3 ""))]
4288 "! TARGET_POWER && reload_completed"
4290 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4292 (compare:CC (match_dup 3)
4297 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4298 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4299 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4301 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4302 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4303 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4307 {srai.|srawi.} %0,%1,%h2
4310 [(set_attr "type" "delayed_compare")
4311 (set_attr "length" "4,4,8,8")])
4314 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4315 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4316 (match_operand:SI 2 "reg_or_cint_operand" ""))
4318 (set (match_operand:SI 0 "gpc_reg_operand" "")
4319 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4320 (clobber (match_scratch:SI 4 ""))]
4321 "TARGET_POWER && reload_completed"
4322 [(parallel [(set (match_dup 0)
4323 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4324 (clobber (match_dup 4))])
4326 (compare:CC (match_dup 0)
4331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4332 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4333 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4335 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4336 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4339 {sra|sraw}%I2. %0,%1,%h2
4341 [(set_attr "type" "delayed_compare")
4342 (set_attr "length" "4,8")])
4345 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4346 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4347 (match_operand:SI 2 "reg_or_cint_operand" ""))
4349 (set (match_operand:SI 0 "gpc_reg_operand" "")
4350 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4351 "! TARGET_POWER && reload_completed"
4353 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4355 (compare:CC (match_dup 0)
4359 ;; Floating-point insns, excluding normal data motion.
4361 ;; PowerPC has a full set of single-precision floating point instructions.
4363 ;; For the POWER architecture, we pretend that we have both SFmode and
4364 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4365 ;; The only conversions we will do will be when storing to memory. In that
4366 ;; case, we will use the "frsp" instruction before storing.
4368 ;; Note that when we store into a single-precision memory location, we need to
4369 ;; use the frsp insn first. If the register being stored isn't dead, we
4370 ;; need a scratch register for the frsp. But this is difficult when the store
4371 ;; is done by reload. It is not incorrect to do the frsp on the register in
4372 ;; this case, we just lose precision that we would have otherwise gotten but
4373 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4375 (define_insn "extendsfdf2"
4376 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4377 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4378 "TARGET_HARD_FLOAT && TARGET_FPRS"
4381 if (REGNO (operands[0]) == REGNO (operands[1]))
4384 return \"fmr %0,%1\";
4386 [(set_attr "type" "fp")])
4388 (define_insn "truncdfsf2"
4389 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4390 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4391 "TARGET_HARD_FLOAT && TARGET_FPRS"
4393 [(set_attr "type" "fp")])
4395 (define_insn "aux_truncdfsf2"
4396 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4397 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4398 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4400 [(set_attr "type" "fp")])
4402 (define_expand "negsf2"
4403 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4404 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4408 (define_insn "*negsf2"
4409 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4410 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4411 "TARGET_HARD_FLOAT && TARGET_FPRS"
4413 [(set_attr "type" "fp")])
4415 (define_expand "abssf2"
4416 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4417 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4421 (define_insn "*abssf2"
4422 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4423 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4424 "TARGET_HARD_FLOAT && TARGET_FPRS"
4426 [(set_attr "type" "fp")])
4429 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4430 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4431 "TARGET_HARD_FLOAT && TARGET_FPRS"
4433 [(set_attr "type" "fp")])
4435 (define_expand "addsf3"
4436 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4437 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4438 (match_operand:SF 2 "gpc_reg_operand" "")))]
4443 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4444 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4445 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4446 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4448 [(set_attr "type" "fp")])
4451 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4452 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4453 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4454 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4455 "{fa|fadd} %0,%1,%2"
4456 [(set_attr "type" "fp")])
4458 (define_expand "subsf3"
4459 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4460 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4461 (match_operand:SF 2 "gpc_reg_operand" "")))]
4466 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4467 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4468 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4469 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4471 [(set_attr "type" "fp")])
4474 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4475 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4476 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4477 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4478 "{fs|fsub} %0,%1,%2"
4479 [(set_attr "type" "fp")])
4481 (define_expand "mulsf3"
4482 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4483 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4484 (match_operand:SF 2 "gpc_reg_operand" "")))]
4489 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4490 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4491 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4492 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4494 [(set_attr "type" "fp")])
4497 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4498 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4499 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4500 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4501 "{fm|fmul} %0,%1,%2"
4502 [(set_attr "type" "dmul")])
4504 (define_expand "divsf3"
4505 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4506 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4507 (match_operand:SF 2 "gpc_reg_operand" "")))]
4512 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4513 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4514 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4515 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4517 [(set_attr "type" "sdiv")])
4520 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4521 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4522 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4523 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4524 "{fd|fdiv} %0,%1,%2"
4525 [(set_attr "type" "ddiv")])
4528 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4529 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4530 (match_operand:SF 2 "gpc_reg_operand" "f"))
4531 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4532 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4533 "fmadds %0,%1,%2,%3"
4534 [(set_attr "type" "fp")])
4537 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4538 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4539 (match_operand:SF 2 "gpc_reg_operand" "f"))
4540 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4541 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4542 "{fma|fmadd} %0,%1,%2,%3"
4543 [(set_attr "type" "dmul")])
4546 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4547 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4548 (match_operand:SF 2 "gpc_reg_operand" "f"))
4549 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4550 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4551 "fmsubs %0,%1,%2,%3"
4552 [(set_attr "type" "fp")])
4555 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4556 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4557 (match_operand:SF 2 "gpc_reg_operand" "f"))
4558 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4559 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4560 "{fms|fmsub} %0,%1,%2,%3"
4561 [(set_attr "type" "dmul")])
4564 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4565 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4566 (match_operand:SF 2 "gpc_reg_operand" "f"))
4567 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4568 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4569 && HONOR_SIGNED_ZEROS (SFmode)"
4570 "fnmadds %0,%1,%2,%3"
4571 [(set_attr "type" "fp")])
4574 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4575 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4576 (match_operand:SF 2 "gpc_reg_operand" "f"))
4577 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4578 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4579 && ! HONOR_SIGNED_ZEROS (SFmode)"
4580 "fnmadds %0,%1,%2,%3"
4581 [(set_attr "type" "fp")])
4584 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4585 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4586 (match_operand:SF 2 "gpc_reg_operand" "f"))
4587 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4588 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4589 "{fnma|fnmadd} %0,%1,%2,%3"
4590 [(set_attr "type" "dmul")])
4593 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4594 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4595 (match_operand:SF 2 "gpc_reg_operand" "f"))
4596 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4597 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4598 && ! HONOR_SIGNED_ZEROS (SFmode)"
4599 "{fnma|fnmadd} %0,%1,%2,%3"
4600 [(set_attr "type" "dmul")])
4603 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4604 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4605 (match_operand:SF 2 "gpc_reg_operand" "f"))
4606 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4607 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4608 && HONOR_SIGNED_ZEROS (SFmode)"
4609 "fnmsubs %0,%1,%2,%3"
4610 [(set_attr "type" "fp")])
4613 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4614 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4615 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4616 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4617 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4618 && ! HONOR_SIGNED_ZEROS (SFmode)"
4619 "fnmsubs %0,%1,%2,%3"
4620 [(set_attr "type" "fp")])
4623 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4624 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4625 (match_operand:SF 2 "gpc_reg_operand" "f"))
4626 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4627 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4628 "{fnms|fnmsub} %0,%1,%2,%3"
4629 [(set_attr "type" "dmul")])
4632 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4633 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4634 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4635 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4636 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4637 && ! HONOR_SIGNED_ZEROS (SFmode)"
4638 "{fnms|fnmsub} %0,%1,%2,%3"
4639 [(set_attr "type" "fp")])
4641 (define_expand "sqrtsf2"
4642 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4643 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4644 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4648 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4649 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4650 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4652 [(set_attr "type" "ssqrt")])
4655 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4656 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4657 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
4659 [(set_attr "type" "dsqrt")])
4661 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4662 ;; fsel instruction and some auxiliary computations. Then we just have a
4663 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4665 (define_expand "maxsf3"
4666 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4667 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4668 (match_operand:SF 2 "gpc_reg_operand" ""))
4671 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4672 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4674 (define_expand "minsf3"
4675 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4676 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4677 (match_operand:SF 2 "gpc_reg_operand" ""))
4680 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4681 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4684 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4685 (match_operator:SF 3 "min_max_operator"
4686 [(match_operand:SF 1 "gpc_reg_operand" "")
4687 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4688 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4691 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4692 operands[1], operands[2]);
4696 (define_expand "movsicc"
4697 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4698 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4699 (match_operand:SI 2 "gpc_reg_operand" "")
4700 (match_operand:SI 3 "gpc_reg_operand" "")))]
4704 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4710 ;; We use the BASE_REGS for the isel input operands because, if rA is
4711 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4712 ;; because we may switch the operands and rB may end up being rA.
4714 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4715 ;; leave out the mode in operand 4 and use one pattern, but reload can
4716 ;; change the mode underneath our feet and then gets confused trying
4717 ;; to reload the value.
4718 (define_insn "isel_signed"
4719 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4721 (match_operator 1 "comparison_operator"
4722 [(match_operand:CC 4 "cc_reg_operand" "y")
4724 (match_operand:SI 2 "gpc_reg_operand" "b")
4725 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4728 { return output_isel (operands); }"
4729 [(set_attr "length" "4")])
4731 (define_insn "isel_unsigned"
4732 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4734 (match_operator 1 "comparison_operator"
4735 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4737 (match_operand:SI 2 "gpc_reg_operand" "b")
4738 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4741 { return output_isel (operands); }"
4742 [(set_attr "length" "4")])
4744 (define_expand "movsfcc"
4745 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4746 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4747 (match_operand:SF 2 "gpc_reg_operand" "")
4748 (match_operand:SF 3 "gpc_reg_operand" "")))]
4749 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4752 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4758 (define_insn "*fselsfsf4"
4759 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4760 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4761 (match_operand:SF 4 "zero_fp_constant" "F"))
4762 (match_operand:SF 2 "gpc_reg_operand" "f")
4763 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4764 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4766 [(set_attr "type" "fp")])
4768 (define_insn "*fseldfsf4"
4769 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4770 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4771 (match_operand:DF 4 "zero_fp_constant" "F"))
4772 (match_operand:SF 2 "gpc_reg_operand" "f")
4773 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4774 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4776 [(set_attr "type" "fp")])
4778 (define_insn "negdf2"
4779 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4780 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4781 "TARGET_HARD_FLOAT && TARGET_FPRS"
4783 [(set_attr "type" "fp")])
4785 (define_insn "absdf2"
4786 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4787 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4788 "TARGET_HARD_FLOAT && TARGET_FPRS"
4790 [(set_attr "type" "fp")])
4793 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4794 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4795 "TARGET_HARD_FLOAT && TARGET_FPRS"
4797 [(set_attr "type" "fp")])
4799 (define_insn "adddf3"
4800 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4801 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4802 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4803 "TARGET_HARD_FLOAT && TARGET_FPRS"
4804 "{fa|fadd} %0,%1,%2"
4805 [(set_attr "type" "fp")])
4807 (define_insn "subdf3"
4808 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4809 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4810 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4811 "TARGET_HARD_FLOAT && TARGET_FPRS"
4812 "{fs|fsub} %0,%1,%2"
4813 [(set_attr "type" "fp")])
4815 (define_insn "muldf3"
4816 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4817 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4818 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4819 "TARGET_HARD_FLOAT && TARGET_FPRS"
4820 "{fm|fmul} %0,%1,%2"
4821 [(set_attr "type" "dmul")])
4823 (define_insn "divdf3"
4824 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4825 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4826 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4827 "TARGET_HARD_FLOAT && TARGET_FPRS"
4828 "{fd|fdiv} %0,%1,%2"
4829 [(set_attr "type" "ddiv")])
4832 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4833 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4834 (match_operand:DF 2 "gpc_reg_operand" "f"))
4835 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4836 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4837 "{fma|fmadd} %0,%1,%2,%3"
4838 [(set_attr "type" "dmul")])
4841 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4842 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4843 (match_operand:DF 2 "gpc_reg_operand" "f"))
4844 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4845 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
4846 "{fms|fmsub} %0,%1,%2,%3"
4847 [(set_attr "type" "dmul")])
4850 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4851 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4852 (match_operand:DF 2 "gpc_reg_operand" "f"))
4853 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4854 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4855 && HONOR_SIGNED_ZEROS (DFmode)"
4856 "{fnma|fnmadd} %0,%1,%2,%3"
4857 [(set_attr "type" "dmul")])
4860 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4861 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4862 (match_operand:DF 2 "gpc_reg_operand" "f"))
4863 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4864 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4865 && ! HONOR_SIGNED_ZEROS (DFmode)"
4866 "{fnma|fnmadd} %0,%1,%2,%3"
4867 [(set_attr "type" "dmul")])
4870 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4871 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4872 (match_operand:DF 2 "gpc_reg_operand" "f"))
4873 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
4874 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4875 && HONOR_SIGNED_ZEROS (DFmode)"
4876 "{fnms|fnmsub} %0,%1,%2,%3"
4877 [(set_attr "type" "dmul")])
4880 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4881 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4882 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4883 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4884 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4885 && ! HONOR_SIGNED_ZEROS (DFmode)"
4886 "{fnms|fnmsub} %0,%1,%2,%3"
4887 [(set_attr "type" "dmul")])
4889 (define_insn "sqrtdf2"
4890 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4891 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4892 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
4894 [(set_attr "type" "dsqrt")])
4896 ;; The conditional move instructions allow us to perform max and min
4897 ;; operations even when
4899 (define_expand "maxdf3"
4900 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4901 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4902 (match_operand:DF 2 "gpc_reg_operand" ""))
4905 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4906 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4908 (define_expand "mindf3"
4909 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4910 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4911 (match_operand:DF 2 "gpc_reg_operand" ""))
4914 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4915 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4918 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4919 (match_operator:DF 3 "min_max_operator"
4920 [(match_operand:DF 1 "gpc_reg_operand" "")
4921 (match_operand:DF 2 "gpc_reg_operand" "")]))]
4922 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4925 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4926 operands[1], operands[2]);
4930 (define_expand "movdfcc"
4931 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4932 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4933 (match_operand:DF 2 "gpc_reg_operand" "")
4934 (match_operand:DF 3 "gpc_reg_operand" "")))]
4935 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4938 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4944 (define_insn "*fseldfdf4"
4945 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4946 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4947 (match_operand:DF 4 "zero_fp_constant" "F"))
4948 (match_operand:DF 2 "gpc_reg_operand" "f")
4949 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4950 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
4952 [(set_attr "type" "fp")])
4954 (define_insn "*fselsfdf4"
4955 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4956 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4957 (match_operand:SF 4 "zero_fp_constant" "F"))
4958 (match_operand:DF 2 "gpc_reg_operand" "f")
4959 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4962 [(set_attr "type" "fp")])
4964 ;; Conversions to and from floating-point.
4966 (define_expand "fixuns_truncsfsi2"
4967 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4968 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4969 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4972 (define_expand "fix_truncsfsi2"
4973 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4974 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4975 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4978 ; For each of these conversions, there is a define_expand, a define_insn
4979 ; with a '#' template, and a define_split (with C code). The idea is
4980 ; to allow constant folding with the template of the define_insn,
4981 ; then to have the insns split later (between sched1 and final).
4983 (define_expand "floatsidf2"
4984 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4985 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4988 (clobber (match_dup 4))
4989 (clobber (match_dup 5))
4990 (clobber (match_dup 6))])]
4991 "TARGET_HARD_FLOAT && TARGET_FPRS"
4994 if (TARGET_POWERPC64)
4996 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4997 rtx t1 = gen_reg_rtx (DImode);
4998 rtx t2 = gen_reg_rtx (DImode);
4999 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5003 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5004 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5005 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5006 operands[5] = gen_reg_rtx (DFmode);
5007 operands[6] = gen_reg_rtx (SImode);
5010 (define_insn "*floatsidf2_internal"
5011 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5012 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5013 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5014 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5015 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5016 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5017 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5018 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5020 [(set_attr "length" "24")])
5023 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5024 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5025 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5026 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5027 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5028 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5029 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5030 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5031 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5032 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5033 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5034 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5035 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5036 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5037 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5040 rtx lowword, highword;
5041 if (GET_CODE (operands[4]) != MEM)
5043 highword = XEXP (operands[4], 0);
5044 lowword = plus_constant (highword, 4);
5045 if (! WORDS_BIG_ENDIAN)
5048 tmp = highword; highword = lowword; lowword = tmp;
5051 emit_insn (gen_xorsi3 (operands[6], operands[1],
5052 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5053 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5054 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5055 emit_move_insn (operands[5], operands[4]);
5056 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5060 (define_expand "floatunssisf2"
5061 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5062 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5063 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5066 (define_expand "floatunssidf2"
5067 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5068 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5071 (clobber (match_dup 4))
5072 (clobber (match_dup 5))])]
5073 "TARGET_HARD_FLOAT && TARGET_FPRS"
5076 if (TARGET_POWERPC64)
5078 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5079 rtx t1 = gen_reg_rtx (DImode);
5080 rtx t2 = gen_reg_rtx (DImode);
5081 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5086 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5087 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5088 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5089 operands[5] = gen_reg_rtx (DFmode);
5092 (define_insn "*floatunssidf2_internal"
5093 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5094 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5095 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5096 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5097 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5098 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5099 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5101 [(set_attr "length" "20")])
5104 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5105 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5106 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5107 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5108 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5109 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5110 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5111 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5112 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5113 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5114 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5115 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5116 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5119 rtx lowword, highword;
5120 if (GET_CODE (operands[4]) != MEM)
5122 highword = XEXP (operands[4], 0);
5123 lowword = plus_constant (highword, 4);
5124 if (! WORDS_BIG_ENDIAN)
5127 tmp = highword; highword = lowword; lowword = tmp;
5130 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5131 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5132 emit_move_insn (operands[5], operands[4]);
5133 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5137 (define_expand "fix_truncdfsi2"
5138 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5139 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5140 (clobber (match_dup 2))
5141 (clobber (match_dup 3))])]
5142 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5145 operands[2] = gen_reg_rtx (DImode);
5146 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5149 (define_insn "*fix_truncdfsi2_internal"
5150 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5151 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5152 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5153 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5154 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5156 [(set_attr "length" "16")])
5159 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5160 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5161 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5162 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5163 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5164 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5165 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5166 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5167 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5171 if (GET_CODE (operands[3]) != MEM)
5173 lowword = XEXP (operands[3], 0);
5174 if (WORDS_BIG_ENDIAN)
5175 lowword = plus_constant (lowword, 4);
5177 emit_insn (gen_fctiwz (operands[2], operands[1]));
5178 emit_move_insn (operands[3], operands[2]);
5179 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5183 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5184 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5185 ; because the first makes it clear that operand 0 is not live
5186 ; before the instruction.
5187 (define_insn "fctiwz"
5188 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5189 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5191 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5192 "{fcirz|fctiwz} %0,%1"
5193 [(set_attr "type" "fp")])
5195 (define_expand "floatsisf2"
5196 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5197 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5198 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5201 (define_insn "floatdidf2"
5202 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5203 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5204 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5206 [(set_attr "type" "fp")])
5208 (define_insn_and_split "floatsidf_ppc64"
5209 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5210 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5211 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5212 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5213 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5214 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5217 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5218 (set (match_dup 2) (match_dup 3))
5219 (set (match_dup 4) (match_dup 2))
5220 (set (match_dup 0) (float:DF (match_dup 4)))]
5223 (define_insn_and_split "floatunssidf_ppc64"
5224 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5225 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5226 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5227 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5228 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5229 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5232 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5233 (set (match_dup 2) (match_dup 3))
5234 (set (match_dup 4) (match_dup 2))
5235 (set (match_dup 0) (float:DF (match_dup 4)))]
5238 (define_insn "fix_truncdfdi2"
5239 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5240 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5241 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5243 [(set_attr "type" "fp")])
5245 (define_expand "floatdisf2"
5246 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5247 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5248 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5251 if (!flag_unsafe_math_optimizations)
5253 rtx label = gen_label_rtx ();
5254 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5257 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5261 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5262 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5263 ;; from double rounding.
5264 (define_insn_and_split "floatdisf2_internal1"
5265 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5266 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5267 (clobber (match_scratch:DF 2 "=f"))]
5268 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5270 "&& reload_completed"
5272 (float:DF (match_dup 1)))
5274 (float_truncate:SF (match_dup 2)))]
5277 ;; Twiddles bits to avoid double rounding.
5278 ;; Bits that might be truncated when converting to DFmode are replaced
5279 ;; by a bit that won't be lost at that stage, but is below the SFmode
5280 ;; rounding position.
5281 (define_expand "floatdisf2_internal2"
5282 [(parallel [(set (match_dup 4)
5283 (compare:CC (and:DI (match_operand:DI 0 "" "")
5286 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5287 (clobber (match_scratch:CC 7 ""))])
5288 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5289 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5290 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5291 (label_ref (match_operand:DI 1 "" ""))
5293 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5294 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5295 (label_ref (match_dup 1))
5297 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5298 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
5299 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
5302 operands[2] = gen_reg_rtx (DImode);
5303 operands[3] = gen_reg_rtx (DImode);
5304 operands[4] = gen_reg_rtx (CCmode);
5305 operands[5] = gen_reg_rtx (CCUNSmode);
5308 ;; Define the DImode operations that can be done in a small number
5309 ;; of instructions. The & constraints are to prevent the register
5310 ;; allocator from allocating registers that overlap with the inputs
5311 ;; (for example, having an input in 7,8 and an output in 6,7). We
5312 ;; also allow for the output being the same as one of the inputs.
5314 (define_insn "*adddi3_noppc64"
5315 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5316 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5317 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5318 "! TARGET_POWERPC64"
5321 if (WORDS_BIG_ENDIAN)
5322 return (GET_CODE (operands[2])) != CONST_INT
5323 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5324 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5326 return (GET_CODE (operands[2])) != CONST_INT
5327 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5328 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5330 [(set_attr "length" "8")])
5332 (define_insn "*subdi3_noppc64"
5333 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5334 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5335 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5336 "! TARGET_POWERPC64"
5339 if (WORDS_BIG_ENDIAN)
5340 return (GET_CODE (operands[1]) != CONST_INT)
5341 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5342 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5344 return (GET_CODE (operands[1]) != CONST_INT)
5345 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5346 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5348 [(set_attr "length" "8")])
5350 (define_insn "*negdi2_noppc64"
5351 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5352 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5353 "! TARGET_POWERPC64"
5356 return (WORDS_BIG_ENDIAN)
5357 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5358 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5360 [(set_attr "length" "8")])
5362 (define_expand "mulsidi3"
5363 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5364 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5365 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5366 "! TARGET_POWERPC64"
5369 if (! TARGET_POWER && ! TARGET_POWERPC)
5371 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5372 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5373 emit_insn (gen_mull_call ());
5374 if (WORDS_BIG_ENDIAN)
5375 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5378 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5379 gen_rtx_REG (SImode, 3));
5380 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5381 gen_rtx_REG (SImode, 4));
5385 else if (TARGET_POWER)
5387 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5392 (define_insn "mulsidi3_mq"
5393 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5394 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5395 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5396 (clobber (match_scratch:SI 3 "=q"))]
5398 "mul %0,%1,%2\;mfmq %L0"
5399 [(set_attr "type" "imul")
5400 (set_attr "length" "8")])
5402 (define_insn "*mulsidi3_no_mq"
5403 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5404 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5405 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5406 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5409 return (WORDS_BIG_ENDIAN)
5410 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5411 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5413 [(set_attr "type" "imul")
5414 (set_attr "length" "8")])
5417 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5418 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5419 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5420 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5423 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5424 (sign_extend:DI (match_dup 2)))
5427 (mult:SI (match_dup 1)
5431 int endian = (WORDS_BIG_ENDIAN == 0);
5432 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5433 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5436 (define_expand "umulsidi3"
5437 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5438 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5439 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5440 "TARGET_POWERPC && ! TARGET_POWERPC64"
5445 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5450 (define_insn "umulsidi3_mq"
5451 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5452 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5453 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5454 (clobber (match_scratch:SI 3 "=q"))]
5455 "TARGET_POWERPC && TARGET_POWER"
5458 return (WORDS_BIG_ENDIAN)
5459 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5460 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5462 [(set_attr "type" "imul")
5463 (set_attr "length" "8")])
5465 (define_insn "*umulsidi3_no_mq"
5466 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5467 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5468 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5469 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5472 return (WORDS_BIG_ENDIAN)
5473 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5474 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5476 [(set_attr "type" "imul")
5477 (set_attr "length" "8")])
5480 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5481 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5482 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5483 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5486 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5487 (zero_extend:DI (match_dup 2)))
5490 (mult:SI (match_dup 1)
5494 int endian = (WORDS_BIG_ENDIAN == 0);
5495 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5496 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5499 (define_expand "smulsi3_highpart"
5500 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5502 (lshiftrt:DI (mult:DI (sign_extend:DI
5503 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5505 (match_operand:SI 2 "gpc_reg_operand" "r")))
5510 if (! TARGET_POWER && ! TARGET_POWERPC)
5512 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5513 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5514 emit_insn (gen_mulh_call ());
5515 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5518 else if (TARGET_POWER)
5520 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5525 (define_insn "smulsi3_highpart_mq"
5526 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5528 (lshiftrt:DI (mult:DI (sign_extend:DI
5529 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5531 (match_operand:SI 2 "gpc_reg_operand" "r")))
5533 (clobber (match_scratch:SI 3 "=q"))]
5536 [(set_attr "type" "imul")])
5538 (define_insn "*smulsi3_highpart_no_mq"
5539 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5541 (lshiftrt:DI (mult:DI (sign_extend:DI
5542 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5544 (match_operand:SI 2 "gpc_reg_operand" "r")))
5546 "TARGET_POWERPC && ! TARGET_POWER"
5548 [(set_attr "type" "imul")])
5550 (define_expand "umulsi3_highpart"
5551 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5553 (lshiftrt:DI (mult:DI (zero_extend:DI
5554 (match_operand:SI 1 "gpc_reg_operand" ""))
5556 (match_operand:SI 2 "gpc_reg_operand" "")))
5563 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5568 (define_insn "umulsi3_highpart_mq"
5569 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5571 (lshiftrt:DI (mult:DI (zero_extend:DI
5572 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5574 (match_operand:SI 2 "gpc_reg_operand" "r")))
5576 (clobber (match_scratch:SI 3 "=q"))]
5577 "TARGET_POWERPC && TARGET_POWER"
5579 [(set_attr "type" "imul")])
5581 (define_insn "*umulsi3_highpart_no_mq"
5582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5584 (lshiftrt:DI (mult:DI (zero_extend:DI
5585 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5587 (match_operand:SI 2 "gpc_reg_operand" "r")))
5589 "TARGET_POWERPC && ! TARGET_POWER"
5591 [(set_attr "type" "imul")])
5593 ;; If operands 0 and 2 are in the same register, we have a problem. But
5594 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5595 ;; why we have the strange constraints below.
5596 (define_insn "ashldi3_power"
5597 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5598 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5599 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5600 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5603 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5604 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5605 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5606 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5607 [(set_attr "length" "8")])
5609 (define_insn "lshrdi3_power"
5610 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5611 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5612 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5613 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5616 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5617 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5618 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5619 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5620 [(set_attr "length" "8")])
5622 ;; Shift by a variable amount is too complex to be worth open-coding. We
5623 ;; just handle shifts by constants.
5624 (define_insn "ashrdi3_power"
5625 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5626 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5627 (match_operand:SI 2 "const_int_operand" "M,i")))
5628 (clobber (match_scratch:SI 3 "=X,q"))]
5631 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5632 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5633 [(set_attr "length" "8")])
5635 (define_insn "ashrdi3_no_power"
5636 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5637 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5638 (match_operand:SI 2 "const_int_operand" "M,i")))]
5639 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
5641 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5642 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5643 [(set_attr "length" "8,12")])
5645 (define_insn "*ashrdisi3_noppc64"
5646 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5647 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5648 (const_int 32)) 4))]
5649 "TARGET_32BIT && !TARGET_POWERPC64"
5652 if (REGNO (operands[0]) == REGNO (operands[1]))
5655 return \"mr %0,%1\";
5657 [(set_attr "length" "4")])
5660 ;; PowerPC64 DImode operations.
5662 (define_expand "adddi3"
5663 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5664 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5665 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5669 if (! TARGET_POWERPC64)
5671 if (non_short_cint_operand (operands[2], DImode))
5675 if (GET_CODE (operands[2]) == CONST_INT
5676 && ! add_operand (operands[2], DImode))
5678 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5679 ? operands[0] : gen_reg_rtx (DImode));
5681 HOST_WIDE_INT val = INTVAL (operands[2]);
5682 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5683 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5685 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5688 /* The ordering here is important for the prolog expander.
5689 When space is allocated from the stack, adding 'low' first may
5690 produce a temporary deallocation (which would be bad). */
5691 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5692 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5697 ;; Discourage ai/addic because of carry but provide it in an alternative
5698 ;; allowing register zero as source.
5700 (define_insn "*adddi3_internal1"
5701 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5702 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5703 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5711 (define_insn "*adddi3_internal2"
5712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5713 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5714 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5716 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5723 [(set_attr "type" "fast_compare,compare,compare,compare")
5724 (set_attr "length" "4,4,8,8")])
5727 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5728 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5729 (match_operand:DI 2 "reg_or_short_operand" ""))
5731 (clobber (match_scratch:DI 3 ""))]
5732 "TARGET_POWERPC64 && reload_completed"
5734 (plus:DI (match_dup 1) (match_dup 2)))
5736 (compare:CC (match_dup 3)
5740 (define_insn "*adddi3_internal3"
5741 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5742 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5743 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5745 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5746 (plus:DI (match_dup 1) (match_dup 2)))]
5753 [(set_attr "type" "fast_compare,compare,compare,compare")
5754 (set_attr "length" "4,4,8,8")])
5757 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5758 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5759 (match_operand:DI 2 "reg_or_short_operand" ""))
5761 (set (match_operand:DI 0 "gpc_reg_operand" "")
5762 (plus:DI (match_dup 1) (match_dup 2)))]
5763 "TARGET_POWERPC64 && reload_completed"
5765 (plus:DI (match_dup 1) (match_dup 2)))
5767 (compare:CC (match_dup 0)
5771 ;; Split an add that we can't do in one insn into two insns, each of which
5772 ;; does one 16-bit part. This is used by combine. Note that the low-order
5773 ;; add should be last in case the result gets used in an address.
5776 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5777 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5778 (match_operand:DI 2 "non_add_cint_operand" "")))]
5780 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5781 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5784 HOST_WIDE_INT val = INTVAL (operands[2]);
5785 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
5786 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5788 operands[4] = GEN_INT (low);
5789 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5790 operands[3] = GEN_INT (rest);
5791 else if (! no_new_pseudos)
5793 operands[3] = gen_reg_rtx (DImode);
5794 emit_move_insn (operands[3], operands[2]);
5795 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5802 (define_insn "one_cmpldi2"
5803 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5804 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5809 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5810 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5812 (clobber (match_scratch:DI 2 "=r,r"))]
5817 [(set_attr "type" "compare")
5818 (set_attr "length" "4,8")])
5821 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5822 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5824 (clobber (match_scratch:DI 2 ""))]
5825 "TARGET_POWERPC64 && reload_completed"
5827 (not:DI (match_dup 1)))
5829 (compare:CC (match_dup 2)
5834 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5835 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5837 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5838 (not:DI (match_dup 1)))]
5843 [(set_attr "type" "compare")
5844 (set_attr "length" "4,8")])
5847 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5848 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5850 (set (match_operand:DI 0 "gpc_reg_operand" "")
5851 (not:DI (match_dup 1)))]
5852 "TARGET_POWERPC64 && reload_completed"
5854 (not:DI (match_dup 1)))
5856 (compare:CC (match_dup 0)
5861 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5862 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5863 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5870 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5871 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5872 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5874 (clobber (match_scratch:DI 3 "=r,r"))]
5879 [(set_attr "type" "fast_compare")
5880 (set_attr "length" "4,8")])
5883 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5884 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5885 (match_operand:DI 2 "gpc_reg_operand" ""))
5887 (clobber (match_scratch:DI 3 ""))]
5888 "TARGET_POWERPC64 && reload_completed"
5890 (minus:DI (match_dup 1) (match_dup 2)))
5892 (compare:CC (match_dup 3)
5897 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5898 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5899 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5901 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5902 (minus:DI (match_dup 1) (match_dup 2)))]
5907 [(set_attr "type" "fast_compare")
5908 (set_attr "length" "4,8")])
5911 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5912 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5913 (match_operand:DI 2 "gpc_reg_operand" ""))
5915 (set (match_operand:DI 0 "gpc_reg_operand" "")
5916 (minus:DI (match_dup 1) (match_dup 2)))]
5917 "TARGET_POWERPC64 && reload_completed"
5919 (minus:DI (match_dup 1) (match_dup 2)))
5921 (compare:CC (match_dup 0)
5925 (define_expand "subdi3"
5926 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5927 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5928 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
5932 if (GET_CODE (operands[2]) == CONST_INT)
5934 emit_insn (gen_adddi3 (operands[0], operands[1],
5935 negate_rtx (DImode, operands[2])));
5940 (define_insn_and_split "absdi2"
5941 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5942 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5943 (clobber (match_scratch:DI 2 "=&r,&r"))]
5946 "&& reload_completed"
5947 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5948 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5949 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5952 (define_insn_and_split "*nabsdi2"
5953 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5954 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5955 (clobber (match_scratch:DI 2 "=&r,&r"))]
5958 "&& reload_completed"
5959 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5960 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5961 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5964 (define_expand "negdi2"
5965 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5966 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5971 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5972 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5978 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5980 (clobber (match_scratch:DI 2 "=r,r"))]
5985 [(set_attr "type" "fast_compare")
5986 (set_attr "length" "4,8")])
5989 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5990 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5992 (clobber (match_scratch:DI 2 ""))]
5993 "TARGET_POWERPC64 && reload_completed"
5995 (neg:DI (match_dup 1)))
5997 (compare:CC (match_dup 2)
6002 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6003 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6005 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6006 (neg:DI (match_dup 1)))]
6011 [(set_attr "type" "fast_compare")
6012 (set_attr "length" "4,8")])
6015 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6016 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6018 (set (match_operand:DI 0 "gpc_reg_operand" "")
6019 (neg:DI (match_dup 1)))]
6020 "TARGET_POWERPC64 && reload_completed"
6022 (neg:DI (match_dup 1)))
6024 (compare:CC (match_dup 0)
6028 (define_insn "clzdi2"
6029 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6030 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6034 (define_expand "ctzdi2"
6036 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6037 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6039 (clobber (scratch:CC))])
6040 (set (match_dup 4) (clz:DI (match_dup 3)))
6041 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6042 (minus:DI (const_int 63) (match_dup 4)))]
6045 operands[2] = gen_reg_rtx (DImode);
6046 operands[3] = gen_reg_rtx (DImode);
6047 operands[4] = gen_reg_rtx (DImode);
6050 (define_expand "ffsdi2"
6052 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6053 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6055 (clobber (scratch:CC))])
6056 (set (match_dup 4) (clz:DI (match_dup 3)))
6057 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6058 (minus:DI (const_int 64) (match_dup 4)))]
6061 operands[2] = gen_reg_rtx (DImode);
6062 operands[3] = gen_reg_rtx (DImode);
6063 operands[4] = gen_reg_rtx (DImode);
6066 (define_insn "muldi3"
6067 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6068 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6069 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6072 [(set_attr "type" "lmul")])
6074 (define_insn "*muldi3_internal1"
6075 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6076 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6077 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6079 (clobber (match_scratch:DI 3 "=r,r"))]
6084 [(set_attr "type" "lmul_compare")
6085 (set_attr "length" "4,8")])
6088 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6089 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6090 (match_operand:DI 2 "gpc_reg_operand" ""))
6092 (clobber (match_scratch:DI 3 ""))]
6093 "TARGET_POWERPC64 && reload_completed"
6095 (mult:DI (match_dup 1) (match_dup 2)))
6097 (compare:CC (match_dup 3)
6101 (define_insn "*muldi3_internal2"
6102 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6103 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6104 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6106 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6107 (mult:DI (match_dup 1) (match_dup 2)))]
6112 [(set_attr "type" "lmul_compare")
6113 (set_attr "length" "4,8")])
6116 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6117 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6118 (match_operand:DI 2 "gpc_reg_operand" ""))
6120 (set (match_operand:DI 0 "gpc_reg_operand" "")
6121 (mult:DI (match_dup 1) (match_dup 2)))]
6122 "TARGET_POWERPC64 && reload_completed"
6124 (mult:DI (match_dup 1) (match_dup 2)))
6126 (compare:CC (match_dup 0)
6130 (define_insn "smuldi3_highpart"
6131 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6133 (lshiftrt:TI (mult:TI (sign_extend:TI
6134 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6136 (match_operand:DI 2 "gpc_reg_operand" "r")))
6140 [(set_attr "type" "lmul")])
6142 (define_insn "umuldi3_highpart"
6143 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6145 (lshiftrt:TI (mult:TI (zero_extend:TI
6146 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6148 (match_operand:DI 2 "gpc_reg_operand" "r")))
6152 [(set_attr "type" "lmul")])
6154 (define_expand "divdi3"
6155 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6156 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6157 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6161 if (GET_CODE (operands[2]) == CONST_INT
6162 && INTVAL (operands[2]) > 0
6163 && exact_log2 (INTVAL (operands[2])) >= 0)
6166 operands[2] = force_reg (DImode, operands[2]);
6169 (define_expand "moddi3"
6170 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6171 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6172 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6180 if (GET_CODE (operands[2]) != CONST_INT
6181 || INTVAL (operands[2]) <= 0
6182 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6185 temp1 = gen_reg_rtx (DImode);
6186 temp2 = gen_reg_rtx (DImode);
6188 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6189 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6190 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6195 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6196 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6197 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6199 "sradi %0,%1,%p2\;addze %0,%0"
6200 [(set_attr "length" "8")])
6203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6204 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6205 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6207 (clobber (match_scratch:DI 3 "=r,r"))]
6210 sradi %3,%1,%p2\;addze. %3,%3
6212 [(set_attr "type" "compare")
6213 (set_attr "length" "8,12")])
6216 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6217 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6218 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6220 (clobber (match_scratch:DI 3 ""))]
6221 "TARGET_POWERPC64 && reload_completed"
6223 (div:DI (match_dup 1) (match_dup 2)))
6225 (compare:CC (match_dup 3)
6230 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6231 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6232 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6234 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6235 (div:DI (match_dup 1) (match_dup 2)))]
6238 sradi %0,%1,%p2\;addze. %0,%0
6240 [(set_attr "type" "compare")
6241 (set_attr "length" "8,12")])
6244 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6245 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6246 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6248 (set (match_operand:DI 0 "gpc_reg_operand" "")
6249 (div:DI (match_dup 1) (match_dup 2)))]
6250 "TARGET_POWERPC64 && reload_completed"
6252 (div:DI (match_dup 1) (match_dup 2)))
6254 (compare:CC (match_dup 0)
6259 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6260 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6261 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6264 [(set_attr "type" "ldiv")])
6266 (define_insn "udivdi3"
6267 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6268 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6269 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6272 [(set_attr "type" "ldiv")])
6274 (define_insn "rotldi3"
6275 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6276 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6277 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6279 "rld%I2cl %0,%1,%H2,0")
6281 (define_insn "*rotldi3_internal2"
6282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6283 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6284 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6286 (clobber (match_scratch:DI 3 "=r,r"))]
6289 rld%I2cl. %3,%1,%H2,0
6291 [(set_attr "type" "delayed_compare")
6292 (set_attr "length" "4,8")])
6295 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6296 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6297 (match_operand:DI 2 "reg_or_cint_operand" ""))
6299 (clobber (match_scratch:DI 3 ""))]
6300 "TARGET_POWERPC64 && reload_completed"
6302 (rotate:DI (match_dup 1) (match_dup 2)))
6304 (compare:CC (match_dup 3)
6308 (define_insn "*rotldi3_internal3"
6309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6310 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6311 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6313 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6314 (rotate:DI (match_dup 1) (match_dup 2)))]
6317 rld%I2cl. %0,%1,%H2,0
6319 [(set_attr "type" "delayed_compare")
6320 (set_attr "length" "4,8")])
6323 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6324 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6325 (match_operand:DI 2 "reg_or_cint_operand" ""))
6327 (set (match_operand:DI 0 "gpc_reg_operand" "")
6328 (rotate:DI (match_dup 1) (match_dup 2)))]
6329 "TARGET_POWERPC64 && reload_completed"
6331 (rotate:DI (match_dup 1) (match_dup 2)))
6333 (compare:CC (match_dup 0)
6337 (define_insn "*rotldi3_internal4"
6338 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6339 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6340 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6341 (match_operand:DI 3 "mask64_operand" "n")))]
6343 "rld%I2c%B3 %0,%1,%H2,%S3")
6345 (define_insn "*rotldi3_internal5"
6346 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6348 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6349 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6350 (match_operand:DI 3 "mask64_operand" "n,n"))
6352 (clobber (match_scratch:DI 4 "=r,r"))]
6355 rld%I2c%B3. %4,%1,%H2,%S3
6357 [(set_attr "type" "delayed_compare")
6358 (set_attr "length" "4,8")])
6361 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6363 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6364 (match_operand:DI 2 "reg_or_cint_operand" ""))
6365 (match_operand:DI 3 "mask64_operand" ""))
6367 (clobber (match_scratch:DI 4 ""))]
6368 "TARGET_POWERPC64 && reload_completed"
6370 (and:DI (rotate:DI (match_dup 1)
6374 (compare:CC (match_dup 4)
6378 (define_insn "*rotldi3_internal6"
6379 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6381 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6382 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6383 (match_operand:DI 3 "mask64_operand" "n,n"))
6385 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6386 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6389 rld%I2c%B3. %0,%1,%H2,%S3
6391 [(set_attr "type" "delayed_compare")
6392 (set_attr "length" "4,8")])
6395 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6397 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6398 (match_operand:DI 2 "reg_or_cint_operand" ""))
6399 (match_operand:DI 3 "mask64_operand" ""))
6401 (set (match_operand:DI 0 "gpc_reg_operand" "")
6402 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6403 "TARGET_POWERPC64 && reload_completed"
6405 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6407 (compare:CC (match_dup 0)
6411 (define_insn "*rotldi3_internal7"
6412 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6415 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6416 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6418 "rld%I2cl %0,%1,%H2,56")
6420 (define_insn "*rotldi3_internal8"
6421 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6422 (compare:CC (zero_extend:DI
6424 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6425 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6427 (clobber (match_scratch:DI 3 "=r,r"))]
6430 rld%I2cl. %3,%1,%H2,56
6432 [(set_attr "type" "delayed_compare")
6433 (set_attr "length" "4,8")])
6436 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6437 (compare:CC (zero_extend:DI
6439 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6440 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6442 (clobber (match_scratch:DI 3 ""))]
6443 "TARGET_POWERPC64 && reload_completed"
6445 (zero_extend:DI (subreg:QI
6446 (rotate:DI (match_dup 1)
6449 (compare:CC (match_dup 3)
6453 (define_insn "*rotldi3_internal9"
6454 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6455 (compare:CC (zero_extend:DI
6457 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6458 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6460 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6461 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6464 rld%I2cl. %0,%1,%H2,56
6466 [(set_attr "type" "delayed_compare")
6467 (set_attr "length" "4,8")])
6470 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6471 (compare:CC (zero_extend:DI
6473 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6474 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6476 (set (match_operand:DI 0 "gpc_reg_operand" "")
6477 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6478 "TARGET_POWERPC64 && reload_completed"
6480 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6482 (compare:CC (match_dup 0)
6486 (define_insn "*rotldi3_internal10"
6487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6490 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6491 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6493 "rld%I2cl %0,%1,%H2,48")
6495 (define_insn "*rotldi3_internal11"
6496 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6497 (compare:CC (zero_extend:DI
6499 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6500 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6502 (clobber (match_scratch:DI 3 "=r,r"))]
6505 rld%I2cl. %3,%1,%H2,48
6507 [(set_attr "type" "delayed_compare")
6508 (set_attr "length" "4,8")])
6511 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6512 (compare:CC (zero_extend:DI
6514 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6515 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6517 (clobber (match_scratch:DI 3 ""))]
6518 "TARGET_POWERPC64 && reload_completed"
6520 (zero_extend:DI (subreg:HI
6521 (rotate:DI (match_dup 1)
6524 (compare:CC (match_dup 3)
6528 (define_insn "*rotldi3_internal12"
6529 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6530 (compare:CC (zero_extend:DI
6532 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6533 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6535 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6536 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6539 rld%I2cl. %0,%1,%H2,48
6541 [(set_attr "type" "delayed_compare")
6542 (set_attr "length" "4,8")])
6545 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6546 (compare:CC (zero_extend:DI
6548 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6549 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6551 (set (match_operand:DI 0 "gpc_reg_operand" "")
6552 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6553 "TARGET_POWERPC64 && reload_completed"
6555 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6557 (compare:CC (match_dup 0)
6561 (define_insn "*rotldi3_internal13"
6562 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6565 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6566 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6568 "rld%I2cl %0,%1,%H2,32")
6570 (define_insn "*rotldi3_internal14"
6571 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6572 (compare:CC (zero_extend:DI
6574 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6575 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6577 (clobber (match_scratch:DI 3 "=r,r"))]
6580 rld%I2cl. %3,%1,%H2,32
6582 [(set_attr "type" "delayed_compare")
6583 (set_attr "length" "4,8")])
6586 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6587 (compare:CC (zero_extend:DI
6589 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6590 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6592 (clobber (match_scratch:DI 3 ""))]
6593 "TARGET_POWERPC64 && reload_completed"
6595 (zero_extend:DI (subreg:SI
6596 (rotate:DI (match_dup 1)
6599 (compare:CC (match_dup 3)
6603 (define_insn "*rotldi3_internal15"
6604 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6605 (compare:CC (zero_extend:DI
6607 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6608 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6610 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6611 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6614 rld%I2cl. %0,%1,%H2,32
6616 [(set_attr "type" "delayed_compare")
6617 (set_attr "length" "4,8")])
6620 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6621 (compare:CC (zero_extend:DI
6623 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6624 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6626 (set (match_operand:DI 0 "gpc_reg_operand" "")
6627 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6628 "TARGET_POWERPC64 && reload_completed"
6630 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6632 (compare:CC (match_dup 0)
6636 (define_expand "ashldi3"
6637 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6638 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6639 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6640 "TARGET_POWERPC64 || TARGET_POWER"
6643 if (TARGET_POWERPC64)
6645 else if (TARGET_POWER)
6647 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6654 (define_insn "*ashldi3_internal1"
6655 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6656 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6657 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6660 [(set_attr "length" "8")])
6662 (define_insn "*ashldi3_internal2"
6663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6664 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6665 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6667 (clobber (match_scratch:DI 3 "=r,r"))]
6672 [(set_attr "type" "delayed_compare")
6673 (set_attr "length" "4,8")])
6676 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6677 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6678 (match_operand:SI 2 "reg_or_cint_operand" ""))
6680 (clobber (match_scratch:DI 3 ""))]
6681 "TARGET_POWERPC64 && reload_completed"
6683 (ashift:DI (match_dup 1) (match_dup 2)))
6685 (compare:CC (match_dup 3)
6689 (define_insn "*ashldi3_internal3"
6690 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6691 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6692 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6694 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6695 (ashift:DI (match_dup 1) (match_dup 2)))]
6700 [(set_attr "type" "delayed_compare")
6701 (set_attr "length" "4,8")])
6704 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6705 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6706 (match_operand:SI 2 "reg_or_cint_operand" ""))
6708 (set (match_operand:DI 0 "gpc_reg_operand" "")
6709 (ashift:DI (match_dup 1) (match_dup 2)))]
6710 "TARGET_POWERPC64 && reload_completed"
6712 (ashift:DI (match_dup 1) (match_dup 2)))
6714 (compare:CC (match_dup 0)
6718 (define_insn "*ashldi3_internal4"
6719 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6720 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6721 (match_operand:SI 2 "const_int_operand" "i"))
6722 (match_operand:DI 3 "const_int_operand" "n")))]
6723 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6724 "rldic %0,%1,%H2,%W3")
6726 (define_insn "ashldi3_internal5"
6727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6729 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6730 (match_operand:SI 2 "const_int_operand" "i,i"))
6731 (match_operand:DI 3 "const_int_operand" "n,n"))
6733 (clobber (match_scratch:DI 4 "=r,r"))]
6734 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6736 rldic. %4,%1,%H2,%W3
6738 [(set_attr "type" "delayed_compare")
6739 (set_attr "length" "4,8")])
6742 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6744 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6745 (match_operand:SI 2 "const_int_operand" ""))
6746 (match_operand:DI 3 "const_int_operand" ""))
6748 (clobber (match_scratch:DI 4 ""))]
6749 "TARGET_POWERPC64 && reload_completed
6750 && includes_rldic_lshift_p (operands[2], operands[3])"
6752 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6755 (compare:CC (match_dup 4)
6759 (define_insn "*ashldi3_internal6"
6760 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6762 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6763 (match_operand:SI 2 "const_int_operand" "i,i"))
6764 (match_operand:DI 3 "const_int_operand" "n,n"))
6766 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6767 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6768 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6770 rldic. %0,%1,%H2,%W3
6772 [(set_attr "type" "delayed_compare")
6773 (set_attr "length" "4,8")])
6776 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6778 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6779 (match_operand:SI 2 "const_int_operand" ""))
6780 (match_operand:DI 3 "const_int_operand" ""))
6782 (set (match_operand:DI 0 "gpc_reg_operand" "")
6783 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6784 "TARGET_POWERPC64 && reload_completed
6785 && includes_rldic_lshift_p (operands[2], operands[3])"
6787 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6790 (compare:CC (match_dup 0)
6794 (define_insn "*ashldi3_internal7"
6795 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6796 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6797 (match_operand:SI 2 "const_int_operand" "i"))
6798 (match_operand:DI 3 "mask64_operand" "n")))]
6799 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6800 "rldicr %0,%1,%H2,%S3")
6802 (define_insn "ashldi3_internal8"
6803 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6805 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6806 (match_operand:SI 2 "const_int_operand" "i,i"))
6807 (match_operand:DI 3 "mask64_operand" "n,n"))
6809 (clobber (match_scratch:DI 4 "=r,r"))]
6810 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6812 rldicr. %4,%1,%H2,%S3
6814 [(set_attr "type" "delayed_compare")
6815 (set_attr "length" "4,8")])
6818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6820 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6821 (match_operand:SI 2 "const_int_operand" ""))
6822 (match_operand:DI 3 "mask64_operand" ""))
6824 (clobber (match_scratch:DI 4 ""))]
6825 "TARGET_POWERPC64 && reload_completed
6826 && includes_rldicr_lshift_p (operands[2], operands[3])"
6828 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6831 (compare:CC (match_dup 4)
6835 (define_insn "*ashldi3_internal9"
6836 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6838 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6839 (match_operand:SI 2 "const_int_operand" "i,i"))
6840 (match_operand:DI 3 "mask64_operand" "n,n"))
6842 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6843 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6844 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6846 rldicr. %0,%1,%H2,%S3
6848 [(set_attr "type" "delayed_compare")
6849 (set_attr "length" "4,8")])
6852 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6854 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6855 (match_operand:SI 2 "const_int_operand" ""))
6856 (match_operand:DI 3 "mask64_operand" ""))
6858 (set (match_operand:DI 0 "gpc_reg_operand" "")
6859 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6860 "TARGET_POWERPC64 && reload_completed
6861 && includes_rldicr_lshift_p (operands[2], operands[3])"
6863 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6866 (compare:CC (match_dup 0)
6870 (define_expand "lshrdi3"
6871 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6872 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6873 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6874 "TARGET_POWERPC64 || TARGET_POWER"
6877 if (TARGET_POWERPC64)
6879 else if (TARGET_POWER)
6881 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6888 (define_insn "*lshrdi3_internal1"
6889 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6890 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6891 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6895 (define_insn "*lshrdi3_internal2"
6896 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6897 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6898 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6900 (clobber (match_scratch:DI 3 "=r,r"))]
6905 [(set_attr "type" "delayed_compare")
6906 (set_attr "length" "4,8")])
6909 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6910 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6911 (match_operand:SI 2 "reg_or_cint_operand" ""))
6913 (clobber (match_scratch:DI 3 ""))]
6914 "TARGET_POWERPC64 && reload_completed"
6916 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6918 (compare:CC (match_dup 3)
6922 (define_insn "*lshrdi3_internal3"
6923 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6924 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6925 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6927 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6928 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6933 [(set_attr "type" "delayed_compare")
6934 (set_attr "length" "4,8")])
6937 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6938 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6939 (match_operand:SI 2 "reg_or_cint_operand" ""))
6941 (set (match_operand:DI 0 "gpc_reg_operand" "")
6942 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6943 "TARGET_POWERPC64 && reload_completed"
6945 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6947 (compare:CC (match_dup 0)
6951 (define_expand "ashrdi3"
6952 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6953 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6954 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6958 if (TARGET_POWERPC64)
6960 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6962 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6965 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
6966 && WORDS_BIG_ENDIAN)
6968 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6975 (define_insn "*ashrdi3_internal1"
6976 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6977 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6978 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6980 "srad%I2 %0,%1,%H2")
6982 (define_insn "*ashrdi3_internal2"
6983 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6984 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6985 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6987 (clobber (match_scratch:DI 3 "=r,r"))]
6992 [(set_attr "type" "delayed_compare")
6993 (set_attr "length" "4,8")])
6996 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6997 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6998 (match_operand:SI 2 "reg_or_cint_operand" ""))
7000 (clobber (match_scratch:DI 3 ""))]
7001 "TARGET_POWERPC64 && reload_completed"
7003 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7005 (compare:CC (match_dup 3)
7009 (define_insn "*ashrdi3_internal3"
7010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7011 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7012 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7014 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7015 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7020 [(set_attr "type" "delayed_compare")
7021 (set_attr "length" "4,8")])
7024 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7025 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7026 (match_operand:SI 2 "reg_or_cint_operand" ""))
7028 (set (match_operand:DI 0 "gpc_reg_operand" "")
7029 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7030 "TARGET_POWERPC64 && reload_completed"
7032 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7034 (compare:CC (match_dup 0)
7038 (define_insn "anddi3"
7039 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
7040 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
7041 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
7042 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
7046 rldic%B2 %0,%1,0,%S2
7050 [(set_attr "length" "4,4,4,4,8")])
7053 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7054 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7055 (match_operand:DI 2 "mask64_2_operand" "")))
7056 (clobber (match_scratch:CC 3 ""))]
7058 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7059 && !mask64_operand (operands[2], DImode)"
7061 (and:DI (rotate:DI (match_dup 1)
7065 (and:DI (rotate:DI (match_dup 0)
7070 build_mask64_2_operands (operands[2], &operands[4]);
7073 (define_insn "*anddi3_internal2"
7074 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7075 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7076 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7078 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7079 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7083 rldic%B2. %3,%1,0,%S2
7092 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7093 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7096 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7097 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7098 (match_operand:DI 2 "and64_operand" ""))
7100 (clobber (match_scratch:DI 3 ""))
7101 (clobber (match_scratch:CC 4 ""))]
7102 "TARGET_POWERPC64 && reload_completed"
7103 [(parallel [(set (match_dup 3)
7104 (and:DI (match_dup 1)
7106 (clobber (match_dup 4))])
7108 (compare:CC (match_dup 3)
7113 [(set (match_operand:CC 0 "cc_reg_operand" "")
7114 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7115 (match_operand:DI 2 "mask64_2_operand" ""))
7117 (clobber (match_scratch:DI 3 ""))
7118 (clobber (match_scratch:CC 4 ""))]
7119 "TARGET_POWERPC64 && reload_completed
7120 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7121 && !mask64_operand (operands[2], DImode)"
7123 (and:DI (rotate:DI (match_dup 1)
7126 (parallel [(set (match_dup 0)
7127 (compare:CC (and:DI (rotate:DI (match_dup 3)
7131 (clobber (match_dup 3))])]
7134 build_mask64_2_operands (operands[2], &operands[5]);
7137 (define_insn "*anddi3_internal3"
7138 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7139 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7140 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7142 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7143 (and:DI (match_dup 1) (match_dup 2)))
7144 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7148 rldic%B2. %0,%1,0,%S2
7157 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7158 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7161 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7162 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7163 (match_operand:DI 2 "and64_operand" ""))
7165 (set (match_operand:DI 0 "gpc_reg_operand" "")
7166 (and:DI (match_dup 1) (match_dup 2)))
7167 (clobber (match_scratch:CC 4 ""))]
7168 "TARGET_POWERPC64 && reload_completed"
7169 [(parallel [(set (match_dup 0)
7170 (and:DI (match_dup 1) (match_dup 2)))
7171 (clobber (match_dup 4))])
7173 (compare:CC (match_dup 0)
7178 [(set (match_operand:CC 3 "cc_reg_operand" "")
7179 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7180 (match_operand:DI 2 "mask64_2_operand" ""))
7182 (set (match_operand:DI 0 "gpc_reg_operand" "")
7183 (and:DI (match_dup 1) (match_dup 2)))
7184 (clobber (match_scratch:CC 4 ""))]
7185 "TARGET_POWERPC64 && reload_completed
7186 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7187 && !mask64_operand (operands[2], DImode)"
7189 (and:DI (rotate:DI (match_dup 1)
7192 (parallel [(set (match_dup 3)
7193 (compare:CC (and:DI (rotate:DI (match_dup 0)
7198 (and:DI (rotate:DI (match_dup 0)
7203 build_mask64_2_operands (operands[2], &operands[5]);
7206 (define_expand "iordi3"
7207 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7208 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7209 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7213 if (non_logical_cint_operand (operands[2], DImode))
7215 HOST_WIDE_INT value;
7216 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7217 ? operands[0] : gen_reg_rtx (DImode));
7219 if (GET_CODE (operands[2]) == CONST_INT)
7221 value = INTVAL (operands[2]);
7222 emit_insn (gen_iordi3 (tmp, operands[1],
7223 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7227 value = CONST_DOUBLE_LOW (operands[2]);
7228 emit_insn (gen_iordi3 (tmp, operands[1],
7229 immed_double_const (value
7230 & (~ (HOST_WIDE_INT) 0xffff),
7234 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7239 (define_expand "xordi3"
7240 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7241 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7242 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7246 if (non_logical_cint_operand (operands[2], DImode))
7248 HOST_WIDE_INT value;
7249 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7250 ? operands[0] : gen_reg_rtx (DImode));
7252 if (GET_CODE (operands[2]) == CONST_INT)
7254 value = INTVAL (operands[2]);
7255 emit_insn (gen_xordi3 (tmp, operands[1],
7256 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7260 value = CONST_DOUBLE_LOW (operands[2]);
7261 emit_insn (gen_xordi3 (tmp, operands[1],
7262 immed_double_const (value
7263 & (~ (HOST_WIDE_INT) 0xffff),
7267 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7272 (define_insn "*booldi3_internal1"
7273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7274 (match_operator:DI 3 "boolean_or_operator"
7275 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7276 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7283 (define_insn "*booldi3_internal2"
7284 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7285 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7286 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7287 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7289 (clobber (match_scratch:DI 3 "=r,r"))]
7294 [(set_attr "type" "compare")
7295 (set_attr "length" "4,8")])
7298 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7299 (compare:CC (match_operator:DI 4 "boolean_operator"
7300 [(match_operand:DI 1 "gpc_reg_operand" "")
7301 (match_operand:DI 2 "gpc_reg_operand" "")])
7303 (clobber (match_scratch:DI 3 ""))]
7304 "TARGET_POWERPC64 && reload_completed"
7305 [(set (match_dup 3) (match_dup 4))
7307 (compare:CC (match_dup 3)
7311 (define_insn "*booldi3_internal3"
7312 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7313 (compare:CC (match_operator:DI 4 "boolean_operator"
7314 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7315 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7317 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7323 [(set_attr "type" "compare")
7324 (set_attr "length" "4,8")])
7327 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7328 (compare:CC (match_operator:DI 4 "boolean_operator"
7329 [(match_operand:DI 1 "gpc_reg_operand" "")
7330 (match_operand:DI 2 "gpc_reg_operand" "")])
7332 (set (match_operand:DI 0 "gpc_reg_operand" "")
7334 "TARGET_POWERPC64 && reload_completed"
7335 [(set (match_dup 0) (match_dup 4))
7337 (compare:CC (match_dup 0)
7341 ;; Split a logical operation that we can't do in one insn into two insns,
7342 ;; each of which does one 16-bit part. This is used by combine.
7345 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7346 (match_operator:DI 3 "boolean_or_operator"
7347 [(match_operand:DI 1 "gpc_reg_operand" "")
7348 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7350 [(set (match_dup 0) (match_dup 4))
7351 (set (match_dup 0) (match_dup 5))]
7356 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7358 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7359 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7361 i4 = GEN_INT (value & 0xffff);
7365 i3 = GEN_INT (INTVAL (operands[2])
7366 & (~ (HOST_WIDE_INT) 0xffff));
7367 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7369 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7371 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7375 (define_insn "*boolcdi3_internal1"
7376 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7377 (match_operator:DI 3 "boolean_operator"
7378 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7379 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7383 (define_insn "*boolcdi3_internal2"
7384 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7385 (compare:CC (match_operator:DI 4 "boolean_operator"
7386 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7387 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7389 (clobber (match_scratch:DI 3 "=r,r"))]
7394 [(set_attr "type" "compare")
7395 (set_attr "length" "4,8")])
7398 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7399 (compare:CC (match_operator:DI 4 "boolean_operator"
7400 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7401 (match_operand:DI 2 "gpc_reg_operand" "")])
7403 (clobber (match_scratch:DI 3 ""))]
7404 "TARGET_POWERPC64 && reload_completed"
7405 [(set (match_dup 3) (match_dup 4))
7407 (compare:CC (match_dup 3)
7411 (define_insn "*boolcdi3_internal3"
7412 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7413 (compare:CC (match_operator:DI 4 "boolean_operator"
7414 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7415 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7417 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7423 [(set_attr "type" "compare")
7424 (set_attr "length" "4,8")])
7427 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7428 (compare:CC (match_operator:DI 4 "boolean_operator"
7429 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7430 (match_operand:DI 2 "gpc_reg_operand" "")])
7432 (set (match_operand:DI 0 "gpc_reg_operand" "")
7434 "TARGET_POWERPC64 && reload_completed"
7435 [(set (match_dup 0) (match_dup 4))
7437 (compare:CC (match_dup 0)
7441 (define_insn "*boolccdi3_internal1"
7442 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7443 (match_operator:DI 3 "boolean_operator"
7444 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7445 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7449 (define_insn "*boolccdi3_internal2"
7450 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7451 (compare:CC (match_operator:DI 4 "boolean_operator"
7452 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7453 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7455 (clobber (match_scratch:DI 3 "=r,r"))]
7460 [(set_attr "type" "compare")
7461 (set_attr "length" "4,8")])
7464 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7465 (compare:CC (match_operator:DI 4 "boolean_operator"
7466 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7467 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7469 (clobber (match_scratch:DI 3 ""))]
7470 "TARGET_POWERPC64 && reload_completed"
7471 [(set (match_dup 3) (match_dup 4))
7473 (compare:CC (match_dup 3)
7477 (define_insn "*boolccdi3_internal3"
7478 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7479 (compare:CC (match_operator:DI 4 "boolean_operator"
7480 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7481 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7483 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7489 [(set_attr "type" "compare")
7490 (set_attr "length" "4,8")])
7493 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7494 (compare:CC (match_operator:DI 4 "boolean_operator"
7495 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7496 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7498 (set (match_operand:DI 0 "gpc_reg_operand" "")
7500 "TARGET_POWERPC64 && reload_completed"
7501 [(set (match_dup 0) (match_dup 4))
7503 (compare:CC (match_dup 0)
7507 ;; Now define ways of moving data around.
7509 ;; Elf specific ways of loading addresses for non-PIC code.
7510 ;; The output of this could be r0, but we make a very strong
7511 ;; preference for a base register because it will usually
7513 (define_insn "elf_high"
7514 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7515 (high:SI (match_operand 1 "" "")))]
7516 "TARGET_ELF && ! TARGET_64BIT"
7517 "{liu|lis} %0,%1@ha")
7519 (define_insn "elf_low"
7520 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7521 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7522 (match_operand 2 "" "")))]
7523 "TARGET_ELF && ! TARGET_64BIT"
7525 {cal|la} %0,%2@l(%1)
7526 {ai|addic} %0,%1,%K2")
7528 ;; Mach-O PIC trickery.
7529 (define_insn "macho_high"
7530 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7531 (high:SI (match_operand 1 "" "")))]
7532 "TARGET_MACHO && ! TARGET_64BIT"
7533 "{liu|lis} %0,ha16(%1)")
7535 (define_insn "macho_low"
7536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7537 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7538 (match_operand 2 "" "")))]
7539 "TARGET_MACHO && ! TARGET_64BIT"
7541 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7542 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7544 ;; Set up a register with a value from the GOT table
7546 (define_expand "movsi_got"
7547 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7548 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7549 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7550 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7553 if (GET_CODE (operands[1]) == CONST)
7555 rtx offset = const0_rtx;
7556 HOST_WIDE_INT value;
7558 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7559 value = INTVAL (offset);
7562 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7563 emit_insn (gen_movsi_got (tmp, operands[1]));
7564 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7569 operands[2] = rs6000_got_register (operands[1]);
7572 (define_insn "*movsi_got_internal"
7573 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7574 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7575 (match_operand:SI 2 "gpc_reg_operand" "b")]
7577 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7578 "{l|lwz} %0,%a1@got(%2)"
7579 [(set_attr "type" "load")])
7581 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7582 ;; didn't get allocated to a hard register.
7584 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7585 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7586 (match_operand:SI 2 "memory_operand" "")]
7588 "DEFAULT_ABI == ABI_V4
7590 && (reload_in_progress || reload_completed)"
7591 [(set (match_dup 0) (match_dup 2))
7592 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7596 ;; For SI, we special-case integers that can't be loaded in one insn. We
7597 ;; do the load 16-bits at a time. We could do this by loading from memory,
7598 ;; and this is even supposed to be faster, but it is simpler not to get
7599 ;; integers in the TOC.
7600 (define_expand "movsi"
7601 [(set (match_operand:SI 0 "general_operand" "")
7602 (match_operand:SI 1 "any_operand" ""))]
7604 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7606 (define_insn "movsi_low"
7607 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7608 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7609 (match_operand 2 "" ""))))]
7610 "TARGET_MACHO && ! TARGET_64BIT"
7611 "{l|lwz} %0,lo16(%2)(%1)"
7612 [(set_attr "type" "load")
7613 (set_attr "length" "4")])
7615 (define_insn "movsi_low_st"
7616 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7617 (match_operand 2 "" "")))
7618 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7619 "TARGET_MACHO && ! TARGET_64BIT"
7620 "{st|stw} %0,lo16(%2)(%1)"
7621 [(set_attr "type" "store")
7622 (set_attr "length" "4")])
7624 (define_insn "movdf_low"
7625 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
7626 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7627 (match_operand 2 "" ""))))]
7628 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7631 switch (which_alternative)
7634 return \"lfd %0,lo16(%2)(%1)\";
7638 operands2[0] = operands[0];
7639 operands2[1] = operands[1];
7640 operands2[2] = operands[2];
7641 if (TARGET_POWERPC64 && TARGET_32BIT)
7642 /* Note, old assemblers didn't support relocation here. */
7643 return \"ld %0,lo16(%2)(%1)\";
7646 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7647 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7649 if (MACHO_DYNAMIC_NO_PIC_P)
7650 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
7652 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7653 although in practice it almost always is. */
7654 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7656 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7663 [(set_attr "type" "load")
7664 (set_attr "length" "4,12")])
7666 (define_insn "movdf_low_st"
7667 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7668 (match_operand 2 "" "")))
7669 (match_operand:DF 0 "gpc_reg_operand" "f"))]
7670 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7671 "stfd %0,lo16(%2)(%1)"
7672 [(set_attr "type" "store")
7673 (set_attr "length" "4")])
7675 (define_insn "movsf_low"
7676 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
7677 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7678 (match_operand 2 "" ""))))]
7679 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7682 {l|lwz} %0,lo16(%2)(%1)"
7683 [(set_attr "type" "load")
7684 (set_attr "length" "4")])
7686 (define_insn "movsf_low_st"
7687 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
7688 (match_operand 2 "" "")))
7689 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
7690 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
7692 stfs %0,lo16(%2)(%1)
7693 {st|stw} %0,lo16(%2)(%1)"
7694 [(set_attr "type" "store")
7695 (set_attr "length" "4")])
7697 (define_insn "*movsi_internal1"
7698 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7699 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7700 "gpc_reg_operand (operands[0], SImode)
7701 || gpc_reg_operand (operands[1], SImode)"
7705 {l%U1%X1|lwz%U1%X1} %0,%1
7706 {st%U0%X0|stw%U0%X0} %1,%0
7716 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7717 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7719 ;; Split a load of a large constant into the appropriate two-insn
7723 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7724 (match_operand:SI 1 "const_int_operand" ""))]
7725 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7726 && (INTVAL (operands[1]) & 0xffff) != 0"
7730 (ior:SI (match_dup 0)
7733 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7735 if (tem == operands[0])
7741 (define_insn "*movsi_internal2"
7742 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7743 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
7745 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7748 {cmpi|cmpwi} %2,%0,0
7751 [(set_attr "type" "cmp,compare,cmp")
7752 (set_attr "length" "4,4,8")])
7755 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7756 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7758 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7759 "TARGET_32BIT && reload_completed"
7760 [(set (match_dup 0) (match_dup 1))
7762 (compare:CC (match_dup 0)
7766 (define_expand "movhi"
7767 [(set (match_operand:HI 0 "general_operand" "")
7768 (match_operand:HI 1 "any_operand" ""))]
7770 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7772 (define_insn "*movhi_internal"
7773 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7774 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7775 "gpc_reg_operand (operands[0], HImode)
7776 || gpc_reg_operand (operands[1], HImode)"
7786 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7788 (define_expand "movqi"
7789 [(set (match_operand:QI 0 "general_operand" "")
7790 (match_operand:QI 1 "any_operand" ""))]
7792 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7794 (define_insn "*movqi_internal"
7795 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7796 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7797 "gpc_reg_operand (operands[0], QImode)
7798 || gpc_reg_operand (operands[1], QImode)"
7808 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7810 ;; Here is how to move condition codes around. When we store CC data in
7811 ;; an integer register or memory, we store just the high-order 4 bits.
7812 ;; This lets us not shift in the most common case of CR0.
7813 (define_expand "movcc"
7814 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7815 (match_operand:CC 1 "nonimmediate_operand" ""))]
7819 (define_insn "*movcc_internal1"
7820 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7821 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7822 "register_operand (operands[0], CCmode)
7823 || register_operand (operands[1], CCmode)"
7827 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7829 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7834 {l%U1%X1|lwz%U1%X1} %0,%1
7835 {st%U0%U1|stw%U0%U1} %1,%0"
7837 (cond [(eq_attr "alternative" "0")
7838 (const_string "cr_logical")
7839 (eq_attr "alternative" "1,2")
7840 (const_string "mtcr")
7841 (eq_attr "alternative" "5,7")
7842 (const_string "integer")
7843 (eq_attr "alternative" "6")
7844 (const_string "mfjmpr")
7845 (eq_attr "alternative" "8")
7846 (const_string "mtjmpr")
7847 (eq_attr "alternative" "9")
7848 (const_string "load")
7849 (eq_attr "alternative" "10")
7850 (const_string "store")
7851 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7852 (const_string "mfcrf")
7854 (const_string "mfcr")))
7855 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7857 ;; For floating-point, we normally deal with the floating-point registers
7858 ;; unless -msoft-float is used. The sole exception is that parameter passing
7859 ;; can produce floating-point values in fixed-point registers. Unless the
7860 ;; value is a simple constant or already in memory, we deal with this by
7861 ;; allocating memory and copying the value explicitly via that memory location.
7862 (define_expand "movsf"
7863 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7864 (match_operand:SF 1 "any_operand" ""))]
7866 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7869 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7870 (match_operand:SF 1 "const_double_operand" ""))]
7872 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7873 || (GET_CODE (operands[0]) == SUBREG
7874 && GET_CODE (SUBREG_REG (operands[0])) == REG
7875 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7876 [(set (match_dup 2) (match_dup 3))]
7882 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7883 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7885 if (! TARGET_POWERPC64)
7886 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7888 operands[2] = gen_lowpart (SImode, operands[0]);
7890 operands[3] = gen_int_mode (l, SImode);
7893 (define_insn "*movsf_hardfloat"
7894 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
7895 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
7896 "(gpc_reg_operand (operands[0], SFmode)
7897 || gpc_reg_operand (operands[1], SFmode))
7898 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
7901 {l%U1%X1|lwz%U1%X1} %0,%1
7902 {st%U0%X0|stw%U0%X0} %1,%0
7911 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
7912 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7914 (define_insn "*movsf_softfloat"
7915 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7916 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
7917 "(gpc_reg_operand (operands[0], SFmode)
7918 || gpc_reg_operand (operands[1], SFmode))
7919 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7925 {l%U1%X1|lwz%U1%X1} %0,%1
7926 {st%U0%X0|stw%U0%X0} %1,%0
7933 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7934 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
7937 (define_expand "movdf"
7938 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7939 (match_operand:DF 1 "any_operand" ""))]
7941 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7944 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7945 (match_operand:DF 1 "const_int_operand" ""))]
7946 "! TARGET_POWERPC64 && reload_completed
7947 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7948 || (GET_CODE (operands[0]) == SUBREG
7949 && GET_CODE (SUBREG_REG (operands[0])) == REG
7950 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7951 [(set (match_dup 2) (match_dup 4))
7952 (set (match_dup 3) (match_dup 1))]
7955 int endian = (WORDS_BIG_ENDIAN == 0);
7956 HOST_WIDE_INT value = INTVAL (operands[1]);
7958 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7959 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7960 #if HOST_BITS_PER_WIDE_INT == 32
7961 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7963 operands[4] = GEN_INT (value >> 32);
7964 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7969 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7970 (match_operand:DF 1 "const_double_operand" ""))]
7971 "! TARGET_POWERPC64 && reload_completed
7972 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7973 || (GET_CODE (operands[0]) == SUBREG
7974 && GET_CODE (SUBREG_REG (operands[0])) == REG
7975 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7976 [(set (match_dup 2) (match_dup 4))
7977 (set (match_dup 3) (match_dup 5))]
7980 int endian = (WORDS_BIG_ENDIAN == 0);
7984 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7985 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7987 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7988 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7989 operands[4] = gen_int_mode (l[endian], SImode);
7990 operands[5] = gen_int_mode (l[1 - endian], SImode);
7994 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7995 (match_operand:DF 1 "easy_fp_constant" ""))]
7996 "TARGET_POWERPC64 && reload_completed
7997 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7998 || (GET_CODE (operands[0]) == SUBREG
7999 && GET_CODE (SUBREG_REG (operands[0])) == REG
8000 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8001 [(set (match_dup 2) (match_dup 3))]
8004 int endian = (WORDS_BIG_ENDIAN == 0);
8007 #if HOST_BITS_PER_WIDE_INT >= 64
8011 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8012 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8014 operands[2] = gen_lowpart (DImode, operands[0]);
8015 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8016 #if HOST_BITS_PER_WIDE_INT >= 64
8017 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8018 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8020 operands[3] = gen_int_mode (val, DImode);
8022 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8026 ;; Don't have reload use general registers to load a constant. First,
8027 ;; it might not work if the output operand is the equivalent of
8028 ;; a non-offsettable memref, but also it is less efficient than loading
8029 ;; the constant into an FP register, since it will probably be used there.
8030 ;; The "??" is a kludge until we can figure out a more reasonable way
8031 ;; of handling these non-offsettable values.
8032 (define_insn "*movdf_hardfloat32"
8033 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8034 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8035 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8036 && (gpc_reg_operand (operands[0], DFmode)
8037 || gpc_reg_operand (operands[1], DFmode))"
8040 switch (which_alternative)
8045 /* We normally copy the low-numbered register first. However, if
8046 the first register operand 0 is the same as the second register
8047 of operand 1, we must copy in the opposite order. */
8048 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8049 return \"mr %L0,%L1\;mr %0,%1\";
8051 return \"mr %0,%1\;mr %L0,%L1\";
8053 if (offsettable_memref_p (operands[1])
8054 || (GET_CODE (operands[1]) == MEM
8055 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8056 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8057 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8059 /* If the low-address word is used in the address, we must load
8060 it last. Otherwise, load it first. Note that we cannot have
8061 auto-increment in that case since the address register is
8062 known to be dead. */
8063 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8065 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8067 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8073 addreg = find_addr_reg (XEXP (operands[1], 0));
8074 if (refers_to_regno_p (REGNO (operands[0]),
8075 REGNO (operands[0]) + 1,
8078 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8079 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8080 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8081 return \"{lx|lwzx} %0,%1\";
8085 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8086 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8087 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8088 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8093 if (offsettable_memref_p (operands[0])
8094 || (GET_CODE (operands[0]) == MEM
8095 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8096 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8097 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8098 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8103 addreg = find_addr_reg (XEXP (operands[0], 0));
8104 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8105 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8106 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8107 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8111 return \"fmr %0,%1\";
8113 return \"lfd%U1%X1 %0,%1\";
8115 return \"stfd%U0%X0 %1,%0\";
8122 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
8123 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8125 (define_insn "*movdf_softfloat32"
8126 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8127 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8128 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8129 && (gpc_reg_operand (operands[0], DFmode)
8130 || gpc_reg_operand (operands[1], DFmode))"
8133 switch (which_alternative)
8138 /* We normally copy the low-numbered register first. However, if
8139 the first register operand 0 is the same as the second register of
8140 operand 1, we must copy in the opposite order. */
8141 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8142 return \"mr %L0,%L1\;mr %0,%1\";
8144 return \"mr %0,%1\;mr %L0,%L1\";
8146 /* If the low-address word is used in the address, we must load
8147 it last. Otherwise, load it first. Note that we cannot have
8148 auto-increment in that case since the address register is
8149 known to be dead. */
8150 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8152 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8154 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8156 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8163 [(set_attr "type" "*,load,store,*,*,*")
8164 (set_attr "length" "8,8,8,8,12,16")])
8166 ; ld/std require word-aligned displacements -> 'Y' constraint.
8167 ; List Y->r and r->Y before r->r for reload.
8168 (define_insn "*movdf_hardfloat64"
8169 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,b,!r,f,f,m,!cl,!r,!r,!r,!r")
8170 (match_operand:DF 1 "input_operand" "r,Y,m,r,f,m,f,r,h,G,H,F"))]
8171 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8172 && (gpc_reg_operand (operands[0], DFmode)
8173 || gpc_reg_operand (operands[1], DFmode))"
8187 [(set_attr "type" "store,load,load,*,fp,fpload,fpstore,mtjmpr,*,*,*,*")
8188 (set_attr "length" "4,4,8,4,4,4,4,4,4,8,12,16")])
8191 [(set (match_operand:DF 0 "base_reg_operand" "")
8192 (match_operand:DF 1 "invalid_gpr_mem" ""))]
8193 "TARGET_POWERPC64 && no_new_pseudos"
8194 [(set (match_dup 2) (match_dup 3))
8195 (set (match_dup 0) (match_dup 4))]
8198 operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
8199 operands[3] = XEXP (operands[1], 0);
8200 operands[4] = replace_equiv_address (operands[1], operands[2]);
8203 (define_expand "reload_outdf"
8204 [(parallel [(match_operand:DF 0 "invalid_gpr_mem" "")
8205 (match_operand:DF 1 "register_operand" "")
8206 (match_operand:DI 2 "register_operand" "=&b")])]
8210 operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
8211 emit_move_insn (operands[2], XEXP (operands[0], 0));
8212 operands[0] = replace_equiv_address (operands[0], operands[2]);
8213 emit_move_insn (operands[0], operands[1]);
8217 (define_expand "reload_indf"
8218 [(parallel [(match_operand:DF 0 "register_operand" "")
8219 (match_operand:DF 1 "invalid_gpr_mem" "")
8220 (match_operand:DI 2 "register_operand" "=&b")])]
8224 operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
8225 emit_move_insn (operands[2], XEXP (operands[1], 0));
8226 operands[1] = replace_equiv_address (operands[1], operands[2]);
8227 emit_move_insn (operands[0], operands[1]);
8231 (define_insn "*movdf_softfloat64"
8232 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8233 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8234 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8235 && (gpc_reg_operand (operands[0], DFmode)
8236 || gpc_reg_operand (operands[1], DFmode))"
8247 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
8248 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8250 (define_expand "movtf"
8251 [(set (match_operand:TF 0 "general_operand" "")
8252 (match_operand:TF 1 "any_operand" ""))]
8253 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8254 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8255 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8257 ; It's important to list the o->f and f->o moves before f->f because
8258 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8259 ; which doesn't make progress.
8260 (define_insn_and_split "*movtf_internal"
8261 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r")
8262 (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))]
8263 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8264 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8265 && (gpc_reg_operand (operands[0], TFmode)
8266 || gpc_reg_operand (operands[1], TFmode))"
8268 "&& reload_completed"
8270 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8271 [(set_attr "length" "8,8,8,20,20")])
8273 (define_expand "extenddftf2"
8274 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8275 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8276 (use (match_dup 2))])]
8277 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8278 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8280 operands[2] = CONST0_RTX (DFmode);
8283 (define_insn_and_split "*extenddftf2_internal"
8284 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8285 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8286 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
8287 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8288 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8290 "&& reload_completed"
8293 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8294 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8295 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8297 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8302 (define_expand "extendsftf2"
8303 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8304 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8305 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8306 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8308 rtx tmp = gen_reg_rtx (DFmode);
8309 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8310 emit_insn (gen_extenddftf2 (operands[0], tmp));
8314 (define_insn "trunctfdf2"
8315 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8316 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8317 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8318 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8320 [(set_attr "type" "fp")
8321 (set_attr "length" "4")])
8323 (define_insn_and_split "trunctfsf2"
8324 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8325 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8326 (clobber (match_scratch:DF 2 "=f"))]
8327 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8328 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8330 "&& reload_completed"
8332 (float_truncate:DF (match_dup 1)))
8334 (float_truncate:SF (match_dup 2)))]
8337 (define_expand "floatsitf2"
8338 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8339 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8340 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8341 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8343 rtx tmp = gen_reg_rtx (DFmode);
8344 expand_float (tmp, operands[1], false);
8345 emit_insn (gen_extenddftf2 (operands[0], tmp));
8349 ; fadd, but rounding towards zero.
8350 ; This is probably not the optimal code sequence.
8351 (define_insn "fix_trunc_helper"
8352 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8353 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8354 UNSPEC_FIX_TRUNC_TF))
8355 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8356 "TARGET_HARD_FLOAT && TARGET_FPRS"
8357 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8358 [(set_attr "type" "fp")
8359 (set_attr "length" "20")])
8361 (define_expand "fix_trunctfsi2"
8362 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8363 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8364 (clobber (match_dup 2))
8365 (clobber (match_dup 3))
8366 (clobber (match_dup 4))
8367 (clobber (match_dup 5))])]
8368 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8369 && (TARGET_POWER2 || TARGET_POWERPC)
8370 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8372 operands[2] = gen_reg_rtx (DFmode);
8373 operands[3] = gen_reg_rtx (DFmode);
8374 operands[4] = gen_reg_rtx (DImode);
8375 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8378 (define_insn_and_split "*fix_trunctfsi2_internal"
8379 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8380 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8381 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8382 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8383 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8384 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8385 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8386 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8388 "&& reload_completed"
8392 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8394 if (GET_CODE (operands[5]) != MEM)
8396 lowword = XEXP (operands[5], 0);
8397 if (WORDS_BIG_ENDIAN)
8398 lowword = plus_constant (lowword, 4);
8400 emit_insn (gen_fctiwz (operands[4], operands[2]));
8401 emit_move_insn (operands[5], operands[4]);
8402 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
8406 (define_insn "negtf2"
8407 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8408 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8409 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8410 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8413 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8414 return \"fneg %L0,%L1\;fneg %0,%1\";
8416 return \"fneg %0,%1\;fneg %L0,%L1\";
8418 [(set_attr "type" "fp")
8419 (set_attr "length" "8")])
8421 (define_expand "abstf2"
8422 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8423 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8424 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8425 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8428 rtx label = gen_label_rtx ();
8429 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8434 (define_expand "abstf2_internal"
8435 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8436 (match_operand:TF 1 "gpc_reg_operand" "f"))
8437 (set (match_dup 3) (match_dup 5))
8438 (set (match_dup 5) (abs:DF (match_dup 5)))
8439 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8440 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8441 (label_ref (match_operand 2 "" ""))
8443 (set (match_dup 6) (neg:DF (match_dup 6)))]
8444 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8445 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8448 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8449 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8450 operands[3] = gen_reg_rtx (DFmode);
8451 operands[4] = gen_reg_rtx (CCFPmode);
8452 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8453 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8456 ;; Next come the multi-word integer load and store and the load and store
8458 (define_expand "movdi"
8459 [(set (match_operand:DI 0 "general_operand" "")
8460 (match_operand:DI 1 "any_operand" ""))]
8462 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
8464 (define_insn "*movdi_internal32"
8465 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8466 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8468 && (gpc_reg_operand (operands[0], DImode)
8469 || gpc_reg_operand (operands[1], DImode))"
8472 switch (which_alternative)
8481 return \"fmr %0,%1\";
8483 return \"lfd%U1%X1 %0,%1\";
8485 return \"stfd%U0%X0 %1,%0\";
8494 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")])
8497 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8498 (match_operand:DI 1 "const_int_operand" ""))]
8499 "! TARGET_POWERPC64 && reload_completed"
8500 [(set (match_dup 2) (match_dup 4))
8501 (set (match_dup 3) (match_dup 1))]
8504 HOST_WIDE_INT value = INTVAL (operands[1]);
8505 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8507 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8509 #if HOST_BITS_PER_WIDE_INT == 32
8510 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8512 operands[4] = GEN_INT (value >> 32);
8513 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8518 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8519 (match_operand:DI 1 "input_operand" ""))]
8520 "reload_completed && !TARGET_POWERPC64
8521 && gpr_or_gpr_p (operands[0], operands[1])"
8523 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8526 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8527 (match_operand:TI 1 "const_double_operand" ""))]
8529 [(set (match_dup 2) (match_dup 4))
8530 (set (match_dup 3) (match_dup 5))]
8533 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8535 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8537 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8539 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8540 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8542 else if (GET_CODE (operands[1]) == CONST_INT)
8544 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8545 operands[5] = operands[1];
8551 (define_insn "*movdi_internal64"
8552 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,b,r,r,r,r,r,??f,f,m,r,*h,*h")
8553 (match_operand:DI 1 "input_operand" "r,Y,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8555 && (gpc_reg_operand (operands[0], DImode)
8556 || gpc_reg_operand (operands[1], DImode))"
8572 [(set_attr "type" "store,load,load,*,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8573 (set_attr "length" "4,4,8,4,4,4,20,4,4,4,4,4,4,4")])
8576 [(set (match_operand:DI 0 "base_reg_operand" "")
8577 (match_operand:DI 1 "invalid_gpr_mem" ""))]
8578 "TARGET_POWERPC64 && no_new_pseudos"
8579 [(set (match_dup 2) (match_dup 3))
8580 (set (match_dup 0) (match_dup 4))]
8583 operands[2] = operands[0];
8585 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
8586 operands[3] = XEXP (operands[1], 0);
8587 operands[4] = replace_equiv_address (operands[1], operands[2]);
8590 (define_expand "reload_outdi"
8591 [(parallel [(match_operand:DI 0 "invalid_gpr_mem" "")
8592 (match_operand:DI 1 "register_operand" "")
8593 (match_operand:DI 2 "register_operand" "=&b")])]
8597 operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
8598 emit_move_insn (operands[2], XEXP (operands[0], 0));
8599 operands[0] = replace_equiv_address (operands[0], operands[2]);
8600 emit_move_insn (operands[0], operands[1]);
8604 (define_expand "reload_indi"
8605 [(parallel [(match_operand:DI 0 "register_operand" "")
8606 (match_operand:DI 1 "invalid_gpr_mem" "")
8607 (match_operand:DI 2 "register_operand" "=&b")])]
8611 operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
8612 emit_move_insn (operands[2], XEXP (operands[1], 0));
8613 operands[1] = replace_equiv_address (operands[1], operands[2]);
8614 emit_move_insn (operands[0], operands[1]);
8618 ;; immediate value valid for a single instruction hiding in a const_double
8620 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8621 (match_operand:DI 1 "const_double_operand" "F"))]
8622 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8623 && GET_CODE (operands[1]) == CONST_DOUBLE
8624 && num_insns_constant (operands[1], DImode) == 1"
8627 return ((unsigned HOST_WIDE_INT)
8628 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8629 ? \"li %0,%1\" : \"lis %0,%v1\";
8632 ;; Generate all one-bits and clear left or right.
8633 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8635 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8636 (match_operand:DI 1 "mask64_operand" ""))]
8637 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8638 [(set (match_dup 0) (const_int -1))
8640 (and:DI (rotate:DI (match_dup 0)
8645 ;; Split a load of a large constant into the appropriate five-instruction
8646 ;; sequence. Handle anything in a constant number of insns.
8647 ;; When non-easy constants can go in the TOC, this should use
8648 ;; easy_fp_constant predicate.
8650 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8651 (match_operand:DI 1 "const_int_operand" ""))]
8652 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8653 [(set (match_dup 0) (match_dup 2))
8654 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8656 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8658 if (tem == operands[0])
8665 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8666 (match_operand:DI 1 "const_double_operand" ""))]
8667 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8668 [(set (match_dup 0) (match_dup 2))
8669 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8671 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8673 if (tem == operands[0])
8679 (define_insn "*movdi_internal2"
8680 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8681 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
8683 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8689 [(set_attr "type" "cmp,compare,cmp")
8690 (set_attr "length" "4,4,8")])
8693 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8694 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8696 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8697 "TARGET_POWERPC64 && reload_completed"
8698 [(set (match_dup 0) (match_dup 1))
8700 (compare:CC (match_dup 0)
8704 ;; TImode is similar, except that we usually want to compute the address into
8705 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8706 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8707 (define_expand "movti"
8708 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8709 (match_operand:TI 1 "general_operand" ""))
8710 (clobber (scratch:SI))])]
8712 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8714 ;; We say that MQ is clobbered in the last alternative because the first
8715 ;; alternative would never get used otherwise since it would need a reload
8716 ;; while the 2nd alternative would not. We put memory cases first so they
8717 ;; are preferred. Otherwise, we'd try to reload the output instead of
8718 ;; giving the SCRATCH mq.
8720 (define_insn "*movti_power"
8721 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8722 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8723 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8724 "TARGET_POWER && ! TARGET_POWERPC64
8725 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8728 switch (which_alternative)
8735 return \"{stsi|stswi} %1,%P0,16\";
8740 /* If the address is not used in the output, we can use lsi. Otherwise,
8741 fall through to generating four loads. */
8743 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8744 return \"{lsi|lswi} %0,%P1,16\";
8745 /* ... fall through ... */
8750 [(set_attr "type" "store,store,*,load,load")])
8752 (define_insn "*movti_string"
8753 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8754 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
8755 "! TARGET_POWER && ! TARGET_POWERPC64
8756 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8759 switch (which_alternative)
8765 return \"{stsi|stswi} %1,%P0,16\";
8770 /* If the address is not used in the output, we can use lsi. Otherwise,
8771 fall through to generating four loads. */
8773 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8774 return \"{lsi|lswi} %0,%P1,16\";
8775 /* ... fall through ... */
8780 [(set_attr "type" "store,store,*,load,load")])
8782 (define_insn "*movti_ppc64"
8783 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r")
8784 (match_operand:TI 1 "input_operand" "r,r,o"))]
8785 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8786 || gpc_reg_operand (operands[1], TImode))"
8791 [(set_attr "type" "*,load,store")])
8794 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8795 (match_operand:TI 1 "input_operand" ""))]
8797 && gpr_or_gpr_p (operands[0], operands[1])"
8799 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8801 (define_expand "load_multiple"
8802 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8803 (match_operand:SI 1 "" ""))
8804 (use (match_operand:SI 2 "" ""))])]
8805 "TARGET_STRING && !TARGET_POWERPC64"
8813 /* Support only loading a constant number of fixed-point registers from
8814 memory and only bother with this if more than two; the machine
8815 doesn't support more than eight. */
8816 if (GET_CODE (operands[2]) != CONST_INT
8817 || INTVAL (operands[2]) <= 2
8818 || INTVAL (operands[2]) > 8
8819 || GET_CODE (operands[1]) != MEM
8820 || GET_CODE (operands[0]) != REG
8821 || REGNO (operands[0]) >= 32)
8824 count = INTVAL (operands[2]);
8825 regno = REGNO (operands[0]);
8827 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8828 op1 = replace_equiv_address (operands[1],
8829 force_reg (SImode, XEXP (operands[1], 0)));
8831 for (i = 0; i < count; i++)
8832 XVECEXP (operands[3], 0, i)
8833 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8834 adjust_address_nv (op1, SImode, i * 4));
8837 (define_insn "*ldmsi8"
8838 [(match_parallel 0 "load_multiple_operation"
8839 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8840 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8841 (set (match_operand:SI 3 "gpc_reg_operand" "")
8842 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8843 (set (match_operand:SI 4 "gpc_reg_operand" "")
8844 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8845 (set (match_operand:SI 5 "gpc_reg_operand" "")
8846 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8847 (set (match_operand:SI 6 "gpc_reg_operand" "")
8848 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8849 (set (match_operand:SI 7 "gpc_reg_operand" "")
8850 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8851 (set (match_operand:SI 8 "gpc_reg_operand" "")
8852 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8853 (set (match_operand:SI 9 "gpc_reg_operand" "")
8854 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8855 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8857 { return rs6000_output_load_multiple (operands); }"
8858 [(set_attr "type" "load")
8859 (set_attr "length" "32")])
8861 (define_insn "*ldmsi7"
8862 [(match_parallel 0 "load_multiple_operation"
8863 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8864 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8865 (set (match_operand:SI 3 "gpc_reg_operand" "")
8866 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8867 (set (match_operand:SI 4 "gpc_reg_operand" "")
8868 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8869 (set (match_operand:SI 5 "gpc_reg_operand" "")
8870 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8871 (set (match_operand:SI 6 "gpc_reg_operand" "")
8872 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8873 (set (match_operand:SI 7 "gpc_reg_operand" "")
8874 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8875 (set (match_operand:SI 8 "gpc_reg_operand" "")
8876 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8877 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8879 { return rs6000_output_load_multiple (operands); }"
8880 [(set_attr "type" "load")
8881 (set_attr "length" "32")])
8883 (define_insn "*ldmsi6"
8884 [(match_parallel 0 "load_multiple_operation"
8885 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8886 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8887 (set (match_operand:SI 3 "gpc_reg_operand" "")
8888 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8889 (set (match_operand:SI 4 "gpc_reg_operand" "")
8890 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8891 (set (match_operand:SI 5 "gpc_reg_operand" "")
8892 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8893 (set (match_operand:SI 6 "gpc_reg_operand" "")
8894 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8895 (set (match_operand:SI 7 "gpc_reg_operand" "")
8896 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8897 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8899 { return rs6000_output_load_multiple (operands); }"
8900 [(set_attr "type" "load")
8901 (set_attr "length" "32")])
8903 (define_insn "*ldmsi5"
8904 [(match_parallel 0 "load_multiple_operation"
8905 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8906 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8907 (set (match_operand:SI 3 "gpc_reg_operand" "")
8908 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8909 (set (match_operand:SI 4 "gpc_reg_operand" "")
8910 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8911 (set (match_operand:SI 5 "gpc_reg_operand" "")
8912 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8913 (set (match_operand:SI 6 "gpc_reg_operand" "")
8914 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8915 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8917 { return rs6000_output_load_multiple (operands); }"
8918 [(set_attr "type" "load")
8919 (set_attr "length" "32")])
8921 (define_insn "*ldmsi4"
8922 [(match_parallel 0 "load_multiple_operation"
8923 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8924 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8925 (set (match_operand:SI 3 "gpc_reg_operand" "")
8926 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8927 (set (match_operand:SI 4 "gpc_reg_operand" "")
8928 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8929 (set (match_operand:SI 5 "gpc_reg_operand" "")
8930 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8931 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8933 { return rs6000_output_load_multiple (operands); }"
8934 [(set_attr "type" "load")
8935 (set_attr "length" "32")])
8937 (define_insn "*ldmsi3"
8938 [(match_parallel 0 "load_multiple_operation"
8939 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8940 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8941 (set (match_operand:SI 3 "gpc_reg_operand" "")
8942 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8943 (set (match_operand:SI 4 "gpc_reg_operand" "")
8944 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8945 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8947 { return rs6000_output_load_multiple (operands); }"
8948 [(set_attr "type" "load")
8949 (set_attr "length" "32")])
8951 (define_expand "store_multiple"
8952 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8953 (match_operand:SI 1 "" ""))
8954 (clobber (scratch:SI))
8955 (use (match_operand:SI 2 "" ""))])]
8956 "TARGET_STRING && !TARGET_POWERPC64"
8965 /* Support only storing a constant number of fixed-point registers to
8966 memory and only bother with this if more than two; the machine
8967 doesn't support more than eight. */
8968 if (GET_CODE (operands[2]) != CONST_INT
8969 || INTVAL (operands[2]) <= 2
8970 || INTVAL (operands[2]) > 8
8971 || GET_CODE (operands[0]) != MEM
8972 || GET_CODE (operands[1]) != REG
8973 || REGNO (operands[1]) >= 32)
8976 count = INTVAL (operands[2]);
8977 regno = REGNO (operands[1]);
8979 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8980 to = force_reg (SImode, XEXP (operands[0], 0));
8981 op0 = replace_equiv_address (operands[0], to);
8983 XVECEXP (operands[3], 0, 0)
8984 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8985 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8986 gen_rtx_SCRATCH (SImode));
8988 for (i = 1; i < count; i++)
8989 XVECEXP (operands[3], 0, i + 1)
8990 = gen_rtx_SET (VOIDmode,
8991 adjust_address_nv (op0, SImode, i * 4),
8992 gen_rtx_REG (SImode, regno + i));
8995 (define_insn "*store_multiple_power"
8996 [(match_parallel 0 "store_multiple_operation"
8997 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8998 (match_operand:SI 2 "gpc_reg_operand" "r"))
8999 (clobber (match_scratch:SI 3 "=q"))])]
9000 "TARGET_STRING && TARGET_POWER"
9001 "{stsi|stswi} %2,%P1,%O0"
9002 [(set_attr "type" "store")])
9004 (define_insn "*stmsi8"
9005 [(match_parallel 0 "store_multiple_operation"
9006 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9007 (match_operand:SI 2 "gpc_reg_operand" "r"))
9008 (clobber (match_scratch:SI 3 "X"))
9009 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9010 (match_operand:SI 4 "gpc_reg_operand" "r"))
9011 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9012 (match_operand:SI 5 "gpc_reg_operand" "r"))
9013 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9014 (match_operand:SI 6 "gpc_reg_operand" "r"))
9015 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9016 (match_operand:SI 7 "gpc_reg_operand" "r"))
9017 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9018 (match_operand:SI 8 "gpc_reg_operand" "r"))
9019 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9020 (match_operand:SI 9 "gpc_reg_operand" "r"))
9021 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9022 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9023 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9024 "{stsi|stswi} %2,%1,%O0"
9025 [(set_attr "type" "store")])
9027 (define_insn "*stmsi7"
9028 [(match_parallel 0 "store_multiple_operation"
9029 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9030 (match_operand:SI 2 "gpc_reg_operand" "r"))
9031 (clobber (match_scratch:SI 3 "X"))
9032 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9033 (match_operand:SI 4 "gpc_reg_operand" "r"))
9034 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9035 (match_operand:SI 5 "gpc_reg_operand" "r"))
9036 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9037 (match_operand:SI 6 "gpc_reg_operand" "r"))
9038 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9039 (match_operand:SI 7 "gpc_reg_operand" "r"))
9040 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9041 (match_operand:SI 8 "gpc_reg_operand" "r"))
9042 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9043 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9044 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9045 "{stsi|stswi} %2,%1,%O0"
9046 [(set_attr "type" "store")])
9048 (define_insn "*stmsi6"
9049 [(match_parallel 0 "store_multiple_operation"
9050 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9051 (match_operand:SI 2 "gpc_reg_operand" "r"))
9052 (clobber (match_scratch:SI 3 "X"))
9053 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9054 (match_operand:SI 4 "gpc_reg_operand" "r"))
9055 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9056 (match_operand:SI 5 "gpc_reg_operand" "r"))
9057 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9058 (match_operand:SI 6 "gpc_reg_operand" "r"))
9059 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9060 (match_operand:SI 7 "gpc_reg_operand" "r"))
9061 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9062 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9063 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9064 "{stsi|stswi} %2,%1,%O0"
9065 [(set_attr "type" "store")])
9067 (define_insn "*stmsi5"
9068 [(match_parallel 0 "store_multiple_operation"
9069 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9070 (match_operand:SI 2 "gpc_reg_operand" "r"))
9071 (clobber (match_scratch:SI 3 "X"))
9072 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9073 (match_operand:SI 4 "gpc_reg_operand" "r"))
9074 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9075 (match_operand:SI 5 "gpc_reg_operand" "r"))
9076 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9077 (match_operand:SI 6 "gpc_reg_operand" "r"))
9078 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9079 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9080 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9081 "{stsi|stswi} %2,%1,%O0"
9082 [(set_attr "type" "store")])
9084 (define_insn "*stmsi4"
9085 [(match_parallel 0 "store_multiple_operation"
9086 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9087 (match_operand:SI 2 "gpc_reg_operand" "r"))
9088 (clobber (match_scratch:SI 3 "X"))
9089 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9090 (match_operand:SI 4 "gpc_reg_operand" "r"))
9091 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9092 (match_operand:SI 5 "gpc_reg_operand" "r"))
9093 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9094 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9095 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9096 "{stsi|stswi} %2,%1,%O0"
9097 [(set_attr "type" "store")])
9099 (define_insn "*stmsi3"
9100 [(match_parallel 0 "store_multiple_operation"
9101 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9102 (match_operand:SI 2 "gpc_reg_operand" "r"))
9103 (clobber (match_scratch:SI 3 "X"))
9104 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9105 (match_operand:SI 4 "gpc_reg_operand" "r"))
9106 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9107 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9108 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9109 "{stsi|stswi} %2,%1,%O0"
9110 [(set_attr "type" "store")])
9112 ;; String/block move insn.
9113 ;; Argument 0 is the destination
9114 ;; Argument 1 is the source
9115 ;; Argument 2 is the length
9116 ;; Argument 3 is the alignment
9118 (define_expand "movstrsi"
9119 [(parallel [(set (match_operand:BLK 0 "" "")
9120 (match_operand:BLK 1 "" ""))
9121 (use (match_operand:SI 2 "" ""))
9122 (use (match_operand:SI 3 "" ""))])]
9126 if (expand_block_move (operands))
9132 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9133 ;; register allocator doesn't have a clue about allocating 8 word registers.
9134 ;; rD/rS = r5 is preferred, efficient form.
9135 (define_expand "movstrsi_8reg"
9136 [(parallel [(set (match_operand 0 "" "")
9137 (match_operand 1 "" ""))
9138 (use (match_operand 2 "" ""))
9139 (use (match_operand 3 "" ""))
9140 (clobber (reg:SI 5))
9141 (clobber (reg:SI 6))
9142 (clobber (reg:SI 7))
9143 (clobber (reg:SI 8))
9144 (clobber (reg:SI 9))
9145 (clobber (reg:SI 10))
9146 (clobber (reg:SI 11))
9147 (clobber (reg:SI 12))
9148 (clobber (match_scratch:SI 4 ""))])]
9153 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9154 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9155 (use (match_operand:SI 2 "immediate_operand" "i"))
9156 (use (match_operand:SI 3 "immediate_operand" "i"))
9157 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9158 (clobber (reg:SI 6))
9159 (clobber (reg:SI 7))
9160 (clobber (reg:SI 8))
9161 (clobber (reg:SI 9))
9162 (clobber (reg:SI 10))
9163 (clobber (reg:SI 11))
9164 (clobber (reg:SI 12))
9165 (clobber (match_scratch:SI 5 "=q"))]
9166 "TARGET_STRING && TARGET_POWER
9167 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9168 || INTVAL (operands[2]) == 0)
9169 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9170 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9171 && REGNO (operands[4]) == 5"
9172 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9173 [(set_attr "type" "load")
9174 (set_attr "length" "8")])
9177 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9178 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9179 (use (match_operand:SI 2 "immediate_operand" "i"))
9180 (use (match_operand:SI 3 "immediate_operand" "i"))
9181 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9182 (clobber (reg:SI 6))
9183 (clobber (reg:SI 7))
9184 (clobber (reg:SI 8))
9185 (clobber (reg:SI 9))
9186 (clobber (reg:SI 10))
9187 (clobber (reg:SI 11))
9188 (clobber (reg:SI 12))
9189 (clobber (match_scratch:SI 5 "X"))]
9190 "TARGET_STRING && ! TARGET_POWER
9191 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9192 || INTVAL (operands[2]) == 0)
9193 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9194 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9195 && REGNO (operands[4]) == 5"
9196 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9197 [(set_attr "type" "load")
9198 (set_attr "length" "8")])
9201 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9202 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9203 (use (match_operand:SI 2 "immediate_operand" "i"))
9204 (use (match_operand:SI 3 "immediate_operand" "i"))
9205 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9206 (clobber (reg:SI 6))
9207 (clobber (reg:SI 7))
9208 (clobber (reg:SI 8))
9209 (clobber (reg:SI 9))
9210 (clobber (reg:SI 10))
9211 (clobber (reg:SI 11))
9212 (clobber (reg:SI 12))
9213 (clobber (match_scratch:SI 5 "X"))]
9214 "TARGET_STRING && TARGET_POWERPC64
9215 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9216 || INTVAL (operands[2]) == 0)
9217 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9218 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9219 && REGNO (operands[4]) == 5"
9220 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9221 [(set_attr "type" "load")
9222 (set_attr "length" "8")])
9224 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9225 ;; register allocator doesn't have a clue about allocating 6 word registers.
9226 ;; rD/rS = r5 is preferred, efficient form.
9227 (define_expand "movstrsi_6reg"
9228 [(parallel [(set (match_operand 0 "" "")
9229 (match_operand 1 "" ""))
9230 (use (match_operand 2 "" ""))
9231 (use (match_operand 3 "" ""))
9232 (clobber (reg:SI 5))
9233 (clobber (reg:SI 6))
9234 (clobber (reg:SI 7))
9235 (clobber (reg:SI 8))
9236 (clobber (reg:SI 9))
9237 (clobber (reg:SI 10))
9238 (clobber (match_scratch:SI 4 ""))])]
9243 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9244 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9245 (use (match_operand:SI 2 "immediate_operand" "i"))
9246 (use (match_operand:SI 3 "immediate_operand" "i"))
9247 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9248 (clobber (reg:SI 6))
9249 (clobber (reg:SI 7))
9250 (clobber (reg:SI 8))
9251 (clobber (reg:SI 9))
9252 (clobber (reg:SI 10))
9253 (clobber (match_scratch:SI 5 "=q"))]
9254 "TARGET_STRING && TARGET_POWER
9255 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9256 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9257 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9258 && REGNO (operands[4]) == 5"
9259 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9260 [(set_attr "type" "load")
9261 (set_attr "length" "8")])
9264 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9265 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9266 (use (match_operand:SI 2 "immediate_operand" "i"))
9267 (use (match_operand:SI 3 "immediate_operand" "i"))
9268 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9269 (clobber (reg:SI 6))
9270 (clobber (reg:SI 7))
9271 (clobber (reg:SI 8))
9272 (clobber (reg:SI 9))
9273 (clobber (reg:SI 10))
9274 (clobber (match_scratch:SI 5 "X"))]
9275 "TARGET_STRING && ! TARGET_POWER
9276 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9277 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9278 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9279 && REGNO (operands[4]) == 5"
9280 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9281 [(set_attr "type" "load")
9282 (set_attr "length" "8")])
9285 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9286 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9287 (use (match_operand:SI 2 "immediate_operand" "i"))
9288 (use (match_operand:SI 3 "immediate_operand" "i"))
9289 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9290 (clobber (reg:SI 6))
9291 (clobber (reg:SI 7))
9292 (clobber (reg:SI 8))
9293 (clobber (reg:SI 9))
9294 (clobber (reg:SI 10))
9295 (clobber (match_scratch:SI 5 "X"))]
9296 "TARGET_STRING && TARGET_POWERPC64
9297 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9298 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9299 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9300 && REGNO (operands[4]) == 5"
9301 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9302 [(set_attr "type" "load")
9303 (set_attr "length" "8")])
9305 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9306 ;; problems with TImode.
9307 ;; rD/rS = r5 is preferred, efficient form.
9308 (define_expand "movstrsi_4reg"
9309 [(parallel [(set (match_operand 0 "" "")
9310 (match_operand 1 "" ""))
9311 (use (match_operand 2 "" ""))
9312 (use (match_operand 3 "" ""))
9313 (clobber (reg:SI 5))
9314 (clobber (reg:SI 6))
9315 (clobber (reg:SI 7))
9316 (clobber (reg:SI 8))
9317 (clobber (match_scratch:SI 4 ""))])]
9322 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9323 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9324 (use (match_operand:SI 2 "immediate_operand" "i"))
9325 (use (match_operand:SI 3 "immediate_operand" "i"))
9326 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9327 (clobber (reg:SI 6))
9328 (clobber (reg:SI 7))
9329 (clobber (reg:SI 8))
9330 (clobber (match_scratch:SI 5 "=q"))]
9331 "TARGET_STRING && TARGET_POWER
9332 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9333 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9334 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9335 && REGNO (operands[4]) == 5"
9336 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9337 [(set_attr "type" "load")
9338 (set_attr "length" "8")])
9341 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9342 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9343 (use (match_operand:SI 2 "immediate_operand" "i"))
9344 (use (match_operand:SI 3 "immediate_operand" "i"))
9345 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9346 (clobber (reg:SI 6))
9347 (clobber (reg:SI 7))
9348 (clobber (reg:SI 8))
9349 (clobber (match_scratch:SI 5 "X"))]
9350 "TARGET_STRING && ! TARGET_POWER
9351 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9352 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9353 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9354 && REGNO (operands[4]) == 5"
9355 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9356 [(set_attr "type" "load")
9357 (set_attr "length" "8")])
9360 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9361 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9362 (use (match_operand:SI 2 "immediate_operand" "i"))
9363 (use (match_operand:SI 3 "immediate_operand" "i"))
9364 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9365 (clobber (reg:SI 6))
9366 (clobber (reg:SI 7))
9367 (clobber (reg:SI 8))
9368 (clobber (match_scratch:SI 5 "X"))]
9369 "TARGET_STRING && TARGET_POWERPC64
9370 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9371 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9372 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9373 && REGNO (operands[4]) == 5"
9374 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9375 [(set_attr "type" "load")
9376 (set_attr "length" "8")])
9378 ;; Move up to 8 bytes at a time.
9379 (define_expand "movstrsi_2reg"
9380 [(parallel [(set (match_operand 0 "" "")
9381 (match_operand 1 "" ""))
9382 (use (match_operand 2 "" ""))
9383 (use (match_operand 3 "" ""))
9384 (clobber (match_scratch:DI 4 ""))
9385 (clobber (match_scratch:SI 5 ""))])]
9386 "TARGET_STRING && ! TARGET_POWERPC64"
9390 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9391 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9392 (use (match_operand:SI 2 "immediate_operand" "i"))
9393 (use (match_operand:SI 3 "immediate_operand" "i"))
9394 (clobber (match_scratch:DI 4 "=&r"))
9395 (clobber (match_scratch:SI 5 "=q"))]
9396 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9397 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9398 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9399 [(set_attr "type" "load")
9400 (set_attr "length" "8")])
9403 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9404 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9405 (use (match_operand:SI 2 "immediate_operand" "i"))
9406 (use (match_operand:SI 3 "immediate_operand" "i"))
9407 (clobber (match_scratch:DI 4 "=&r"))
9408 (clobber (match_scratch:SI 5 "X"))]
9409 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9410 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9411 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9412 [(set_attr "type" "load")
9413 (set_attr "length" "8")])
9415 ;; Move up to 4 bytes at a time.
9416 (define_expand "movstrsi_1reg"
9417 [(parallel [(set (match_operand 0 "" "")
9418 (match_operand 1 "" ""))
9419 (use (match_operand 2 "" ""))
9420 (use (match_operand 3 "" ""))
9421 (clobber (match_scratch:SI 4 ""))
9422 (clobber (match_scratch:SI 5 ""))])]
9427 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9428 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9429 (use (match_operand:SI 2 "immediate_operand" "i"))
9430 (use (match_operand:SI 3 "immediate_operand" "i"))
9431 (clobber (match_scratch:SI 4 "=&r"))
9432 (clobber (match_scratch:SI 5 "=q"))]
9433 "TARGET_STRING && TARGET_POWER
9434 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9435 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9436 [(set_attr "type" "load")
9437 (set_attr "length" "8")])
9440 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9441 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9442 (use (match_operand:SI 2 "immediate_operand" "i"))
9443 (use (match_operand:SI 3 "immediate_operand" "i"))
9444 (clobber (match_scratch:SI 4 "=&r"))
9445 (clobber (match_scratch:SI 5 "X"))]
9446 "TARGET_STRING && ! TARGET_POWER
9447 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9448 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9449 [(set_attr "type" "load")
9450 (set_attr "length" "8")])
9453 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9454 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9455 (use (match_operand:SI 2 "immediate_operand" "i"))
9456 (use (match_operand:SI 3 "immediate_operand" "i"))
9457 (clobber (match_scratch:SI 4 "=&r"))
9458 (clobber (match_scratch:SI 5 "X"))]
9459 "TARGET_STRING && TARGET_POWERPC64
9460 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9461 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9462 [(set_attr "type" "load")
9463 (set_attr "length" "8")])
9466 ;; Define insns that do load or store with update. Some of these we can
9467 ;; get by using pre-decrement or pre-increment, but the hardware can also
9468 ;; do cases where the increment is not the size of the object.
9470 ;; In all these cases, we use operands 0 and 1 for the register being
9471 ;; incremented because those are the operands that local-alloc will
9472 ;; tie and these are the pair most likely to be tieable (and the ones
9473 ;; that will benefit the most).
9475 (define_insn "*movdi_update1"
9476 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9477 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9478 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9479 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9480 (plus:DI (match_dup 1) (match_dup 2)))]
9481 "TARGET_POWERPC64 && TARGET_UPDATE"
9485 [(set_attr "type" "load_ux,load_u")])
9487 (define_insn "movdi_update"
9488 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9489 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
9490 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9491 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9492 (plus:DI (match_dup 1) (match_dup 2)))]
9493 "TARGET_POWERPC64 && TARGET_UPDATE"
9497 [(set_attr "type" "store_ux,store_u")])
9499 (define_insn "*movsi_update1"
9500 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9501 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9502 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9503 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9504 (plus:SI (match_dup 1) (match_dup 2)))]
9507 {lux|lwzux} %3,%0,%2
9508 {lu|lwzu} %3,%2(%0)"
9509 [(set_attr "type" "load_ux,load_u")])
9511 (define_insn "*movsi_update2"
9512 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9514 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9515 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9516 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9517 (plus:DI (match_dup 1) (match_dup 2)))]
9520 [(set_attr "type" "load_ext_ux")])
9522 (define_insn "movsi_update"
9523 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9524 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9525 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9526 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9527 (plus:SI (match_dup 1) (match_dup 2)))]
9530 {stux|stwux} %3,%0,%2
9531 {stu|stwu} %3,%2(%0)"
9532 [(set_attr "type" "store_ux,store_u")])
9534 (define_insn "*movhi_update1"
9535 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9536 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9537 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9538 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9539 (plus:SI (match_dup 1) (match_dup 2)))]
9544 [(set_attr "type" "load_ux,load_u")])
9546 (define_insn "*movhi_update2"
9547 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9549 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9550 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9551 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9552 (plus:SI (match_dup 1) (match_dup 2)))]
9557 [(set_attr "type" "load_ux,load_u")])
9559 (define_insn "*movhi_update3"
9560 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9562 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9563 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9564 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9565 (plus:SI (match_dup 1) (match_dup 2)))]
9570 [(set_attr "type" "load_ext_ux,load_ext_u")])
9572 (define_insn "*movhi_update4"
9573 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9574 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9575 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9576 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9577 (plus:SI (match_dup 1) (match_dup 2)))]
9582 [(set_attr "type" "store_ux,store_u")])
9584 (define_insn "*movqi_update1"
9585 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9586 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9587 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9588 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9589 (plus:SI (match_dup 1) (match_dup 2)))]
9594 [(set_attr "type" "load_ux,load_u")])
9596 (define_insn "*movqi_update2"
9597 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9599 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9600 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9601 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9602 (plus:SI (match_dup 1) (match_dup 2)))]
9607 [(set_attr "type" "load_ux,load_u")])
9609 (define_insn "*movqi_update3"
9610 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9611 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9612 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9613 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9614 (plus:SI (match_dup 1) (match_dup 2)))]
9619 [(set_attr "type" "store_ux,store_u")])
9621 (define_insn "*movsf_update1"
9622 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9623 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9624 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9625 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9626 (plus:SI (match_dup 1) (match_dup 2)))]
9627 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9631 [(set_attr "type" "fpload_ux,fpload_u")])
9633 (define_insn "*movsf_update2"
9634 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9635 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9636 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9637 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9638 (plus:SI (match_dup 1) (match_dup 2)))]
9639 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9643 [(set_attr "type" "fpstore_ux,fpstore_u")])
9645 (define_insn "*movsf_update3"
9646 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9647 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9648 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9649 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9650 (plus:SI (match_dup 1) (match_dup 2)))]
9651 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9653 {lux|lwzux} %3,%0,%2
9654 {lu|lwzu} %3,%2(%0)"
9655 [(set_attr "type" "load_ux,load_u")])
9657 (define_insn "*movsf_update4"
9658 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9659 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9660 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9661 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9662 (plus:SI (match_dup 1) (match_dup 2)))]
9663 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9665 {stux|stwux} %3,%0,%2
9666 {stu|stwu} %3,%2(%0)"
9667 [(set_attr "type" "store_ux,store_u")])
9669 (define_insn "*movdf_update1"
9670 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9671 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9672 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9673 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9674 (plus:SI (match_dup 1) (match_dup 2)))]
9675 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9679 [(set_attr "type" "fpload_ux,fpload_u")])
9681 (define_insn "*movdf_update2"
9682 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9683 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9684 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9685 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9686 (plus:SI (match_dup 1) (match_dup 2)))]
9687 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9691 [(set_attr "type" "fpstore_ux,fpstore_u")])
9693 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9696 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9697 (match_operand:DF 1 "memory_operand" ""))
9698 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9699 (match_operand:DF 3 "memory_operand" ""))]
9701 && TARGET_HARD_FLOAT && TARGET_FPRS
9702 && registers_ok_for_quad_peep (operands[0], operands[2])
9703 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9704 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9708 [(set (match_operand:DF 0 "memory_operand" "")
9709 (match_operand:DF 1 "gpc_reg_operand" "f"))
9710 (set (match_operand:DF 2 "memory_operand" "")
9711 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9713 && TARGET_HARD_FLOAT && TARGET_FPRS
9714 && registers_ok_for_quad_peep (operands[1], operands[3])
9715 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9716 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9721 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9722 (define_insn "tls_gd_32"
9723 [(set (match_operand:SI 0 "register_operand" "=b")
9724 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9725 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9727 "HAVE_AS_TLS && !TARGET_64BIT"
9728 "addi %0,%1,%2@got@tlsgd")
9730 (define_insn "tls_gd_64"
9731 [(set (match_operand:DI 0 "register_operand" "=b")
9732 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9733 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9735 "HAVE_AS_TLS && TARGET_64BIT"
9736 "addi %0,%1,%2@got@tlsgd")
9738 (define_insn "tls_ld_32"
9739 [(set (match_operand:SI 0 "register_operand" "=b")
9740 (unspec:SI [(match_operand:SI 1 "register_operand" "b")]
9742 "HAVE_AS_TLS && !TARGET_64BIT"
9743 "addi %0,%1,%&@got@tlsld")
9745 (define_insn "tls_ld_64"
9746 [(set (match_operand:DI 0 "register_operand" "=b")
9747 (unspec:DI [(match_operand:DI 1 "register_operand" "b")]
9749 "HAVE_AS_TLS && TARGET_64BIT"
9750 "addi %0,%1,%&@got@tlsld")
9752 (define_insn "tls_dtprel_32"
9753 [(set (match_operand:SI 0 "register_operand" "=r")
9754 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9755 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9757 "HAVE_AS_TLS && !TARGET_64BIT"
9758 "addi %0,%1,%2@dtprel")
9760 (define_insn "tls_dtprel_64"
9761 [(set (match_operand:DI 0 "register_operand" "=r")
9762 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9763 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9765 "HAVE_AS_TLS && TARGET_64BIT"
9766 "addi %0,%1,%2@dtprel")
9768 (define_insn "tls_dtprel_ha_32"
9769 [(set (match_operand:SI 0 "register_operand" "=r")
9770 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9771 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9772 UNSPEC_TLSDTPRELHA))]
9773 "HAVE_AS_TLS && !TARGET_64BIT"
9774 "addis %0,%1,%2@dtprel@ha")
9776 (define_insn "tls_dtprel_ha_64"
9777 [(set (match_operand:DI 0 "register_operand" "=r")
9778 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9779 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9780 UNSPEC_TLSDTPRELHA))]
9781 "HAVE_AS_TLS && TARGET_64BIT"
9782 "addis %0,%1,%2@dtprel@ha")
9784 (define_insn "tls_dtprel_lo_32"
9785 [(set (match_operand:SI 0 "register_operand" "=r")
9786 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9787 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9788 UNSPEC_TLSDTPRELLO))]
9789 "HAVE_AS_TLS && !TARGET_64BIT"
9790 "addi %0,%1,%2@dtprel@l")
9792 (define_insn "tls_dtprel_lo_64"
9793 [(set (match_operand:DI 0 "register_operand" "=r")
9794 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9795 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9796 UNSPEC_TLSDTPRELLO))]
9797 "HAVE_AS_TLS && TARGET_64BIT"
9798 "addi %0,%1,%2@dtprel@l")
9800 (define_insn "tls_got_dtprel_32"
9801 [(set (match_operand:SI 0 "register_operand" "=r")
9802 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9803 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9804 UNSPEC_TLSGOTDTPREL))]
9805 "HAVE_AS_TLS && !TARGET_64BIT"
9806 "lwz %0,%2@got@dtprel(%1)")
9808 (define_insn "tls_got_dtprel_64"
9809 [(set (match_operand:DI 0 "register_operand" "=r")
9810 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9811 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9812 UNSPEC_TLSGOTDTPREL))]
9813 "HAVE_AS_TLS && TARGET_64BIT"
9814 "ld %0,%2@got@dtprel(%1)")
9816 (define_insn "tls_tprel_32"
9817 [(set (match_operand:SI 0 "register_operand" "=r")
9818 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9819 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9821 "HAVE_AS_TLS && !TARGET_64BIT"
9822 "addi %0,%1,%2@tprel")
9824 (define_insn "tls_tprel_64"
9825 [(set (match_operand:DI 0 "register_operand" "=r")
9826 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9827 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9829 "HAVE_AS_TLS && TARGET_64BIT"
9830 "addi %0,%1,%2@tprel")
9832 (define_insn "tls_tprel_ha_32"
9833 [(set (match_operand:SI 0 "register_operand" "=r")
9834 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9835 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9836 UNSPEC_TLSTPRELHA))]
9837 "HAVE_AS_TLS && !TARGET_64BIT"
9838 "addis %0,%1,%2@tprel@ha")
9840 (define_insn "tls_tprel_ha_64"
9841 [(set (match_operand:DI 0 "register_operand" "=r")
9842 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9843 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9844 UNSPEC_TLSTPRELHA))]
9845 "HAVE_AS_TLS && TARGET_64BIT"
9846 "addis %0,%1,%2@tprel@ha")
9848 (define_insn "tls_tprel_lo_32"
9849 [(set (match_operand:SI 0 "register_operand" "=r")
9850 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9851 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9852 UNSPEC_TLSTPRELLO))]
9853 "HAVE_AS_TLS && !TARGET_64BIT"
9854 "addi %0,%1,%2@tprel@l")
9856 (define_insn "tls_tprel_lo_64"
9857 [(set (match_operand:DI 0 "register_operand" "=r")
9858 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9859 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9860 UNSPEC_TLSTPRELLO))]
9861 "HAVE_AS_TLS && TARGET_64BIT"
9862 "addi %0,%1,%2@tprel@l")
9864 ;; "b" output constraint here and on tls_tls input to support linker tls
9865 ;; optimization. The linker may edit the instructions emitted by a
9866 ;; tls_got_tprel/tls_tls pair to addis,addi.
9867 (define_insn "tls_got_tprel_32"
9868 [(set (match_operand:SI 0 "register_operand" "=b")
9869 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9870 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9871 UNSPEC_TLSGOTTPREL))]
9872 "HAVE_AS_TLS && !TARGET_64BIT"
9873 "lwz %0,%2@got@tprel(%1)")
9875 (define_insn "tls_got_tprel_64"
9876 [(set (match_operand:DI 0 "register_operand" "=b")
9877 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9878 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9879 UNSPEC_TLSGOTTPREL))]
9880 "HAVE_AS_TLS && TARGET_64BIT"
9881 "ld %0,%2@got@tprel(%1)")
9883 (define_insn "tls_tls_32"
9884 [(set (match_operand:SI 0 "register_operand" "=r")
9885 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9886 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9888 "HAVE_AS_TLS && !TARGET_64BIT"
9891 (define_insn "tls_tls_64"
9892 [(set (match_operand:DI 0 "register_operand" "=r")
9893 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9894 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9896 "HAVE_AS_TLS && TARGET_64BIT"
9899 ;; Next come insns related to the calling sequence.
9901 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9902 ;; We move the back-chain and decrement the stack pointer.
9904 (define_expand "allocate_stack"
9905 [(set (match_operand 0 "gpc_reg_operand" "=r")
9906 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9908 (minus (reg 1) (match_dup 1)))]
9911 { rtx chain = gen_reg_rtx (Pmode);
9912 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9915 emit_move_insn (chain, stack_bot);
9917 /* Check stack bounds if necessary. */
9918 if (current_function_limit_stack)
9921 available = expand_binop (Pmode, sub_optab,
9922 stack_pointer_rtx, stack_limit_rtx,
9923 NULL_RTX, 1, OPTAB_WIDEN);
9924 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9927 if (GET_CODE (operands[1]) != CONST_INT
9928 || INTVAL (operands[1]) < -32767
9929 || INTVAL (operands[1]) > 32768)
9931 neg_op0 = gen_reg_rtx (Pmode);
9933 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9935 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9938 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9941 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9942 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9946 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9947 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9948 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9951 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9955 ;; These patterns say how to save and restore the stack pointer. We need not
9956 ;; save the stack pointer at function level since we are careful to
9957 ;; preserve the backchain. At block level, we have to restore the backchain
9958 ;; when we restore the stack pointer.
9960 ;; For nonlocal gotos, we must save both the stack pointer and its
9961 ;; backchain and restore both. Note that in the nonlocal case, the
9962 ;; save area is a memory location.
9964 (define_expand "save_stack_function"
9965 [(match_operand 0 "any_operand" "")
9966 (match_operand 1 "any_operand" "")]
9970 (define_expand "restore_stack_function"
9971 [(match_operand 0 "any_operand" "")
9972 (match_operand 1 "any_operand" "")]
9976 (define_expand "restore_stack_block"
9977 [(use (match_operand 0 "register_operand" ""))
9978 (set (match_dup 2) (match_dup 3))
9979 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9980 (set (match_dup 3) (match_dup 2))]
9984 operands[2] = gen_reg_rtx (Pmode);
9985 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9988 (define_expand "save_stack_nonlocal"
9989 [(match_operand 0 "memory_operand" "")
9990 (match_operand 1 "register_operand" "")]
9994 rtx temp = gen_reg_rtx (Pmode);
9996 /* Copy the backchain to the first word, sp to the second. */
9997 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9998 emit_move_insn (operand_subword (operands[0], 0, 0,
9999 (TARGET_32BIT ? DImode : TImode)),
10001 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
10006 (define_expand "restore_stack_nonlocal"
10007 [(match_operand 0 "register_operand" "")
10008 (match_operand 1 "memory_operand" "")]
10012 rtx temp = gen_reg_rtx (Pmode);
10014 /* Restore the backchain from the first word, sp from the second. */
10015 emit_move_insn (temp,
10016 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
10017 emit_move_insn (operands[0],
10018 operand_subword (operands[1], 1, 0,
10019 (TARGET_32BIT ? DImode : TImode)));
10020 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
10024 ;; TOC register handling.
10026 ;; Code to initialize the TOC register...
10028 (define_insn "load_toc_aix_si"
10029 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10030 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10031 (use (reg:SI 2))])]
10032 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10036 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10037 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10038 operands[2] = gen_rtx_REG (Pmode, 2);
10039 return \"{l|lwz} %0,%1(%2)\";
10041 [(set_attr "type" "load")])
10043 (define_insn "load_toc_aix_di"
10044 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10045 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10046 (use (reg:DI 2))])]
10047 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10051 #ifdef TARGET_RELOCATABLE
10052 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10053 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10055 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10058 strcat (buf, \"@toc\");
10059 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10060 operands[2] = gen_rtx_REG (Pmode, 2);
10061 return \"ld %0,%1(%2)\";
10063 [(set_attr "type" "load")])
10065 (define_insn "load_toc_v4_pic_si"
10066 [(set (match_operand:SI 0 "register_operand" "=l")
10067 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10068 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10069 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10070 [(set_attr "type" "branch")
10071 (set_attr "length" "4")])
10073 (define_insn "load_toc_v4_PIC_1"
10074 [(set (match_operand:SI 0 "register_operand" "=l")
10075 (match_operand:SI 1 "immediate_operand" "s"))
10076 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10077 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10078 "bcl 20,31,%1\\n%1:"
10079 [(set_attr "type" "branch")
10080 (set_attr "length" "4")])
10082 (define_insn "load_toc_v4_PIC_1b"
10083 [(set (match_operand:SI 0 "register_operand" "=l")
10084 (match_operand:SI 1 "immediate_operand" "s"))
10085 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
10087 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10088 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
10089 [(set_attr "type" "branch")
10090 (set_attr "length" "8")])
10092 (define_insn "load_toc_v4_PIC_2"
10093 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10094 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10095 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10096 (match_operand:SI 3 "immediate_operand" "s")))))]
10097 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10098 "{l|lwz} %0,%2-%3(%1)"
10099 [(set_attr "type" "load")])
10101 (define_insn "load_macho_picbase"
10102 [(set (match_operand:SI 0 "register_operand" "=l")
10103 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10105 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
10106 "bcl 20,31,%1\\n%1:"
10107 [(set_attr "type" "branch")
10108 (set_attr "length" "4")])
10110 (define_insn "macho_correct_pic"
10111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10112 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10113 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
10114 (match_operand:SI 3 "immediate_operand" "s")]
10115 UNSPEC_MPIC_CORRECT)))]
10116 "DEFAULT_ABI == ABI_DARWIN"
10117 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
10118 [(set_attr "length" "8")])
10120 ;; If the TOC is shared over a translation unit, as happens with all
10121 ;; the kinds of PIC that we support, we need to restore the TOC
10122 ;; pointer only when jumping over units of translation.
10123 ;; On Darwin, we need to reload the picbase.
10125 (define_expand "builtin_setjmp_receiver"
10126 [(use (label_ref (match_operand 0 "" "")))]
10127 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10128 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10129 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10133 if (DEFAULT_ABI == ABI_DARWIN)
10135 const char *picbase = machopic_function_base_name ();
10136 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10137 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10141 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10142 CODE_LABEL_NUMBER (operands[0]));
10143 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10145 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10146 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10150 rs6000_emit_load_toc_table (FALSE);
10154 ;; A function pointer under AIX is a pointer to a data area whose first word
10155 ;; contains the actual address of the function, whose second word contains a
10156 ;; pointer to its TOC, and whose third word contains a value to place in the
10157 ;; static chain register (r11). Note that if we load the static chain, our
10158 ;; "trampoline" need not have any executable code.
10160 (define_expand "call_indirect_aix32"
10161 [(set (match_dup 2)
10162 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10163 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10166 (mem:SI (plus:SI (match_dup 0)
10169 (mem:SI (plus:SI (match_dup 0)
10171 (parallel [(call (mem:SI (match_dup 2))
10172 (match_operand 1 "" ""))
10176 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10177 (clobber (scratch:SI))])]
10180 { operands[2] = gen_reg_rtx (SImode); }")
10182 (define_expand "call_indirect_aix64"
10183 [(set (match_dup 2)
10184 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10185 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10188 (mem:DI (plus:DI (match_dup 0)
10191 (mem:DI (plus:DI (match_dup 0)
10193 (parallel [(call (mem:SI (match_dup 2))
10194 (match_operand 1 "" ""))
10198 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10199 (clobber (scratch:SI))])]
10202 { operands[2] = gen_reg_rtx (DImode); }")
10204 (define_expand "call_value_indirect_aix32"
10205 [(set (match_dup 3)
10206 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10207 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10210 (mem:SI (plus:SI (match_dup 1)
10213 (mem:SI (plus:SI (match_dup 1)
10215 (parallel [(set (match_operand 0 "" "")
10216 (call (mem:SI (match_dup 3))
10217 (match_operand 2 "" "")))
10221 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10222 (clobber (scratch:SI))])]
10225 { operands[3] = gen_reg_rtx (SImode); }")
10227 (define_expand "call_value_indirect_aix64"
10228 [(set (match_dup 3)
10229 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10230 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10233 (mem:DI (plus:DI (match_dup 1)
10236 (mem:DI (plus:DI (match_dup 1)
10238 (parallel [(set (match_operand 0 "" "")
10239 (call (mem:SI (match_dup 3))
10240 (match_operand 2 "" "")))
10244 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10245 (clobber (scratch:SI))])]
10248 { operands[3] = gen_reg_rtx (DImode); }")
10250 ;; Now the definitions for the call and call_value insns
10251 (define_expand "call"
10252 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10253 (match_operand 1 "" ""))
10254 (use (match_operand 2 "" ""))
10255 (clobber (scratch:SI))])]
10260 if (MACHOPIC_INDIRECT)
10261 operands[0] = machopic_indirect_call_target (operands[0]);
10264 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10267 operands[0] = XEXP (operands[0], 0);
10269 if (GET_CODE (operands[0]) != SYMBOL_REF
10270 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10271 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10273 if (INTVAL (operands[2]) & CALL_LONG)
10274 operands[0] = rs6000_longcall_ref (operands[0]);
10276 if (DEFAULT_ABI == ABI_V4
10277 || DEFAULT_ABI == ABI_DARWIN)
10278 operands[0] = force_reg (Pmode, operands[0]);
10280 else if (DEFAULT_ABI == ABI_AIX)
10282 /* AIX function pointers are really pointers to a three word
10284 emit_call_insn (TARGET_32BIT
10285 ? gen_call_indirect_aix32 (force_reg (SImode,
10288 : gen_call_indirect_aix64 (force_reg (DImode,
10298 (define_expand "call_value"
10299 [(parallel [(set (match_operand 0 "" "")
10300 (call (mem:SI (match_operand 1 "address_operand" ""))
10301 (match_operand 2 "" "")))
10302 (use (match_operand 3 "" ""))
10303 (clobber (scratch:SI))])]
10308 if (MACHOPIC_INDIRECT)
10309 operands[1] = machopic_indirect_call_target (operands[1]);
10312 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10315 operands[1] = XEXP (operands[1], 0);
10317 if (GET_CODE (operands[1]) != SYMBOL_REF
10318 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10319 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10321 if (INTVAL (operands[3]) & CALL_LONG)
10322 operands[1] = rs6000_longcall_ref (operands[1]);
10324 if (DEFAULT_ABI == ABI_V4
10325 || DEFAULT_ABI == ABI_DARWIN)
10326 operands[1] = force_reg (Pmode, operands[1]);
10328 else if (DEFAULT_ABI == ABI_AIX)
10330 /* AIX function pointers are really pointers to a three word
10332 emit_call_insn (TARGET_32BIT
10333 ? gen_call_value_indirect_aix32 (operands[0],
10337 : gen_call_value_indirect_aix64 (operands[0],
10348 ;; Call to function in current module. No TOC pointer reload needed.
10349 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10350 ;; either the function was not prototyped, or it was prototyped as a
10351 ;; variable argument function. It is > 0 if FP registers were passed
10352 ;; and < 0 if they were not.
10354 (define_insn "*call_local32"
10355 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10356 (match_operand 1 "" "g,g"))
10357 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10358 (clobber (match_scratch:SI 3 "=l,l"))]
10359 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10362 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10363 output_asm_insn (\"crxor 6,6,6\", operands);
10365 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10366 output_asm_insn (\"creqv 6,6,6\", operands);
10368 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10370 [(set_attr "type" "branch")
10371 (set_attr "length" "4,8")])
10373 (define_insn "*call_local64"
10374 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10375 (match_operand 1 "" "g,g"))
10376 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10377 (clobber (match_scratch:SI 3 "=l,l"))]
10378 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10381 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10382 output_asm_insn (\"crxor 6,6,6\", operands);
10384 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10385 output_asm_insn (\"creqv 6,6,6\", operands);
10387 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10389 [(set_attr "type" "branch")
10390 (set_attr "length" "4,8")])
10392 (define_insn "*call_value_local32"
10393 [(set (match_operand 0 "" "")
10394 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10395 (match_operand 2 "" "g,g")))
10396 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10397 (clobber (match_scratch:SI 4 "=l,l"))]
10398 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10401 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10402 output_asm_insn (\"crxor 6,6,6\", operands);
10404 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10405 output_asm_insn (\"creqv 6,6,6\", operands);
10407 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10409 [(set_attr "type" "branch")
10410 (set_attr "length" "4,8")])
10413 (define_insn "*call_value_local64"
10414 [(set (match_operand 0 "" "")
10415 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10416 (match_operand 2 "" "g,g")))
10417 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10418 (clobber (match_scratch:SI 4 "=l,l"))]
10419 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10422 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10423 output_asm_insn (\"crxor 6,6,6\", operands);
10425 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10426 output_asm_insn (\"creqv 6,6,6\", operands);
10428 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10430 [(set_attr "type" "branch")
10431 (set_attr "length" "4,8")])
10433 ;; Call to function which may be in another module. Restore the TOC
10434 ;; pointer (r2) after the call unless this is System V.
10435 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10436 ;; either the function was not prototyped, or it was prototyped as a
10437 ;; variable argument function. It is > 0 if FP registers were passed
10438 ;; and < 0 if they were not.
10440 (define_insn "*call_indirect_nonlocal_aix32"
10441 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10442 (match_operand 1 "" "g"))
10446 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10447 (clobber (match_scratch:SI 2 "=l"))]
10448 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10449 "b%T0l\;{l|lwz} 2,20(1)"
10450 [(set_attr "type" "jmpreg")
10451 (set_attr "length" "8")])
10453 (define_insn "*call_nonlocal_aix32"
10454 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10455 (match_operand 1 "" "g"))
10456 (use (match_operand:SI 2 "immediate_operand" "O"))
10457 (clobber (match_scratch:SI 3 "=l"))]
10459 && DEFAULT_ABI == ABI_AIX
10460 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10462 [(set_attr "type" "branch")
10463 (set_attr "length" "8")])
10465 (define_insn "*call_indirect_nonlocal_aix64"
10466 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10467 (match_operand 1 "" "g"))
10471 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10472 (clobber (match_scratch:SI 2 "=l"))]
10473 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10474 "b%T0l\;ld 2,40(1)"
10475 [(set_attr "type" "jmpreg")
10476 (set_attr "length" "8")])
10478 (define_insn "*call_nonlocal_aix64"
10479 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10480 (match_operand 1 "" "g"))
10481 (use (match_operand:SI 2 "immediate_operand" "O"))
10482 (clobber (match_scratch:SI 3 "=l"))]
10484 && DEFAULT_ABI == ABI_AIX
10485 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10487 [(set_attr "type" "branch")
10488 (set_attr "length" "8")])
10490 (define_insn "*call_value_indirect_nonlocal_aix32"
10491 [(set (match_operand 0 "" "")
10492 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10493 (match_operand 2 "" "g")))
10497 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10498 (clobber (match_scratch:SI 3 "=l"))]
10499 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10500 "b%T1l\;{l|lwz} 2,20(1)"
10501 [(set_attr "type" "jmpreg")
10502 (set_attr "length" "8")])
10504 (define_insn "*call_value_nonlocal_aix32"
10505 [(set (match_operand 0 "" "")
10506 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10507 (match_operand 2 "" "g")))
10508 (use (match_operand:SI 3 "immediate_operand" "O"))
10509 (clobber (match_scratch:SI 4 "=l"))]
10511 && DEFAULT_ABI == ABI_AIX
10512 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10514 [(set_attr "type" "branch")
10515 (set_attr "length" "8")])
10517 (define_insn "*call_value_indirect_nonlocal_aix64"
10518 [(set (match_operand 0 "" "")
10519 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10520 (match_operand 2 "" "g")))
10524 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10525 (clobber (match_scratch:SI 3 "=l"))]
10526 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10527 "b%T1l\;ld 2,40(1)"
10528 [(set_attr "type" "jmpreg")
10529 (set_attr "length" "8")])
10531 (define_insn "*call_value_nonlocal_aix64"
10532 [(set (match_operand 0 "" "")
10533 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10534 (match_operand 2 "" "g")))
10535 (use (match_operand:SI 3 "immediate_operand" "O"))
10536 (clobber (match_scratch:SI 4 "=l"))]
10538 && DEFAULT_ABI == ABI_AIX
10539 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10541 [(set_attr "type" "branch")
10542 (set_attr "length" "8")])
10544 ;; A function pointer under System V is just a normal pointer
10545 ;; operands[0] is the function pointer
10546 ;; operands[1] is the stack size to clean up
10547 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10548 ;; which indicates how to set cr1
10550 (define_insn "*call_indirect_nonlocal_sysv"
10551 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10552 (match_operand 1 "" "g,g"))
10553 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10554 (clobber (match_scratch:SI 3 "=l,l"))]
10555 "DEFAULT_ABI == ABI_V4
10556 || DEFAULT_ABI == ABI_DARWIN"
10558 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10559 output_asm_insn ("crxor 6,6,6", operands);
10561 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10562 output_asm_insn ("creqv 6,6,6", operands);
10566 [(set_attr "type" "jmpreg,jmpreg")
10567 (set_attr "length" "4,8")])
10569 (define_insn "*call_nonlocal_sysv"
10570 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10571 (match_operand 1 "" "g,g"))
10572 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10573 (clobber (match_scratch:SI 3 "=l,l"))]
10574 "(DEFAULT_ABI == ABI_DARWIN
10575 || (DEFAULT_ABI == ABI_V4
10576 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10578 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10579 output_asm_insn ("crxor 6,6,6", operands);
10581 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10582 output_asm_insn ("creqv 6,6,6", operands);
10585 return output_call(insn, operands, 0, 2);
10587 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10590 [(set_attr "type" "branch,branch")
10591 (set_attr "length" "4,8")])
10593 (define_insn "*call_value_indirect_nonlocal_sysv"
10594 [(set (match_operand 0 "" "")
10595 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10596 (match_operand 2 "" "g,g")))
10597 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10598 (clobber (match_scratch:SI 4 "=l,l"))]
10599 "DEFAULT_ABI == ABI_V4
10600 || DEFAULT_ABI == ABI_DARWIN"
10602 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10603 output_asm_insn ("crxor 6,6,6", operands);
10605 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10606 output_asm_insn ("creqv 6,6,6", operands);
10610 [(set_attr "type" "jmpreg,jmpreg")
10611 (set_attr "length" "4,8")])
10613 (define_insn "*call_value_nonlocal_sysv"
10614 [(set (match_operand 0 "" "")
10615 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10616 (match_operand 2 "" "g,g")))
10617 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10618 (clobber (match_scratch:SI 4 "=l,l"))]
10619 "(DEFAULT_ABI == ABI_DARWIN
10620 || (DEFAULT_ABI == ABI_V4
10621 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10623 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10624 output_asm_insn ("crxor 6,6,6", operands);
10626 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10627 output_asm_insn ("creqv 6,6,6", operands);
10630 return output_call(insn, operands, 1, 3);
10632 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10635 [(set_attr "type" "branch,branch")
10636 (set_attr "length" "4,8")])
10638 ;; Call subroutine returning any type.
10639 (define_expand "untyped_call"
10640 [(parallel [(call (match_operand 0 "" "")
10642 (match_operand 1 "" "")
10643 (match_operand 2 "" "")])]
10649 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10651 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10653 rtx set = XVECEXP (operands[2], 0, i);
10654 emit_move_insn (SET_DEST (set), SET_SRC (set));
10657 /* The optimizer does not know that the call sets the function value
10658 registers we stored in the result block. We avoid problems by
10659 claiming that all hard registers are used and clobbered at this
10661 emit_insn (gen_blockage ());
10666 ;; sibling call patterns
10667 (define_expand "sibcall"
10668 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10669 (match_operand 1 "" ""))
10670 (use (match_operand 2 "" ""))
10671 (use (match_operand 3 "" ""))
10677 if (MACHOPIC_INDIRECT)
10678 operands[0] = machopic_indirect_call_target (operands[0]);
10681 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10684 operands[0] = XEXP (operands[0], 0);
10685 operands[3] = gen_reg_rtx (SImode);
10689 ;; this and similar patterns must be marked as using LR, otherwise
10690 ;; dataflow will try to delete the store into it. This is true
10691 ;; even when the actual reg to jump to is in CTR, when LR was
10692 ;; saved and restored around the PIC-setting BCL.
10693 (define_insn "*sibcall_local32"
10694 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10695 (match_operand 1 "" "g,g"))
10696 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10697 (use (match_operand:SI 3 "register_operand" "l,l"))
10699 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10702 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10703 output_asm_insn (\"crxor 6,6,6\", operands);
10705 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10706 output_asm_insn (\"creqv 6,6,6\", operands);
10708 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10710 [(set_attr "type" "branch")
10711 (set_attr "length" "4,8")])
10713 (define_insn "*sibcall_local64"
10714 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10715 (match_operand 1 "" "g,g"))
10716 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10717 (use (match_operand:SI 3 "register_operand" "l,l"))
10719 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10722 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10723 output_asm_insn (\"crxor 6,6,6\", operands);
10725 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10726 output_asm_insn (\"creqv 6,6,6\", operands);
10728 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10730 [(set_attr "type" "branch")
10731 (set_attr "length" "4,8")])
10733 (define_insn "*sibcall_value_local32"
10734 [(set (match_operand 0 "" "")
10735 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10736 (match_operand 2 "" "g,g")))
10737 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10738 (use (match_operand:SI 4 "register_operand" "l,l"))
10740 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10743 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10744 output_asm_insn (\"crxor 6,6,6\", operands);
10746 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10747 output_asm_insn (\"creqv 6,6,6\", operands);
10749 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10751 [(set_attr "type" "branch")
10752 (set_attr "length" "4,8")])
10755 (define_insn "*sibcall_value_local64"
10756 [(set (match_operand 0 "" "")
10757 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10758 (match_operand 2 "" "g,g")))
10759 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10760 (use (match_operand:SI 4 "register_operand" "l,l"))
10762 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10765 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10766 output_asm_insn (\"crxor 6,6,6\", operands);
10768 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10769 output_asm_insn (\"creqv 6,6,6\", operands);
10771 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10773 [(set_attr "type" "branch")
10774 (set_attr "length" "4,8")])
10776 (define_insn "*sibcall_nonlocal_aix32"
10777 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10778 (match_operand 1 "" "g"))
10779 (use (match_operand:SI 2 "immediate_operand" "O"))
10780 (use (match_operand:SI 3 "register_operand" "l"))
10783 && DEFAULT_ABI == ABI_AIX
10784 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10786 [(set_attr "type" "branch")
10787 (set_attr "length" "4")])
10789 (define_insn "*sibcall_nonlocal_aix64"
10790 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10791 (match_operand 1 "" "g"))
10792 (use (match_operand:SI 2 "immediate_operand" "O"))
10793 (use (match_operand:SI 3 "register_operand" "l"))
10796 && DEFAULT_ABI == ABI_AIX
10797 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10799 [(set_attr "type" "branch")
10800 (set_attr "length" "4")])
10802 (define_insn "*sibcall_value_nonlocal_aix32"
10803 [(set (match_operand 0 "" "")
10804 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10805 (match_operand 2 "" "g")))
10806 (use (match_operand:SI 3 "immediate_operand" "O"))
10807 (use (match_operand:SI 4 "register_operand" "l"))
10810 && DEFAULT_ABI == ABI_AIX
10811 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10813 [(set_attr "type" "branch")
10814 (set_attr "length" "4")])
10816 (define_insn "*sibcall_value_nonlocal_aix64"
10817 [(set (match_operand 0 "" "")
10818 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10819 (match_operand 2 "" "g")))
10820 (use (match_operand:SI 3 "immediate_operand" "O"))
10821 (use (match_operand:SI 4 "register_operand" "l"))
10824 && DEFAULT_ABI == ABI_AIX
10825 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10827 [(set_attr "type" "branch")
10828 (set_attr "length" "4")])
10830 (define_insn "*sibcall_nonlocal_sysv"
10831 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10832 (match_operand 1 "" ""))
10833 (use (match_operand 2 "immediate_operand" "O,n"))
10834 (use (match_operand:SI 3 "register_operand" "l,l"))
10836 "(DEFAULT_ABI == ABI_DARWIN
10837 || DEFAULT_ABI == ABI_V4)
10838 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10841 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10842 output_asm_insn (\"crxor 6,6,6\", operands);
10844 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10845 output_asm_insn (\"creqv 6,6,6\", operands);
10847 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10849 [(set_attr "type" "branch,branch")
10850 (set_attr "length" "4,8")])
10852 (define_expand "sibcall_value"
10853 [(parallel [(set (match_operand 0 "register_operand" "")
10854 (call (mem:SI (match_operand 1 "address_operand" ""))
10855 (match_operand 2 "" "")))
10856 (use (match_operand 3 "" ""))
10857 (use (match_operand 4 "" ""))
10863 if (MACHOPIC_INDIRECT)
10864 operands[1] = machopic_indirect_call_target (operands[1]);
10867 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10870 operands[1] = XEXP (operands[1], 0);
10871 operands[4] = gen_reg_rtx (SImode);
10875 (define_insn "*sibcall_value_nonlocal_sysv"
10876 [(set (match_operand 0 "" "")
10877 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10878 (match_operand 2 "" "")))
10879 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10880 (use (match_operand:SI 4 "register_operand" "l,l"))
10882 "(DEFAULT_ABI == ABI_DARWIN
10883 || DEFAULT_ABI == ABI_V4)
10884 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10887 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10888 output_asm_insn (\"crxor 6,6,6\", operands);
10890 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10891 output_asm_insn (\"creqv 6,6,6\", operands);
10893 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10895 [(set_attr "type" "branch,branch")
10896 (set_attr "length" "4,8")])
10898 (define_expand "sibcall_epilogue"
10899 [(use (const_int 0))]
10900 "TARGET_SCHED_PROLOG"
10903 rs6000_emit_epilogue (TRUE);
10907 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10908 ;; all of memory. This blocks insns from being moved across this point.
10910 (define_insn "blockage"
10911 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10915 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10916 ;; signed & unsigned, and one type of branch.
10918 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10919 ;; insns, and branches. We store the operands of compares until we see
10921 (define_expand "cmpsi"
10923 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10924 (match_operand:SI 1 "reg_or_short_operand" "")))]
10928 /* Take care of the possibility that operands[1] might be negative but
10929 this might be a logical operation. That insn doesn't exist. */
10930 if (GET_CODE (operands[1]) == CONST_INT
10931 && INTVAL (operands[1]) < 0)
10932 operands[1] = force_reg (SImode, operands[1]);
10934 rs6000_compare_op0 = operands[0];
10935 rs6000_compare_op1 = operands[1];
10936 rs6000_compare_fp_p = 0;
10940 (define_expand "cmpdi"
10942 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10943 (match_operand:DI 1 "reg_or_short_operand" "")))]
10947 /* Take care of the possibility that operands[1] might be negative but
10948 this might be a logical operation. That insn doesn't exist. */
10949 if (GET_CODE (operands[1]) == CONST_INT
10950 && INTVAL (operands[1]) < 0)
10951 operands[1] = force_reg (DImode, operands[1]);
10953 rs6000_compare_op0 = operands[0];
10954 rs6000_compare_op1 = operands[1];
10955 rs6000_compare_fp_p = 0;
10959 (define_expand "cmpsf"
10960 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10961 (match_operand:SF 1 "gpc_reg_operand" "")))]
10962 "TARGET_HARD_FLOAT"
10965 rs6000_compare_op0 = operands[0];
10966 rs6000_compare_op1 = operands[1];
10967 rs6000_compare_fp_p = 1;
10971 (define_expand "cmpdf"
10972 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10973 (match_operand:DF 1 "gpc_reg_operand" "")))]
10974 "TARGET_HARD_FLOAT && TARGET_FPRS"
10977 rs6000_compare_op0 = operands[0];
10978 rs6000_compare_op1 = operands[1];
10979 rs6000_compare_fp_p = 1;
10983 (define_expand "cmptf"
10984 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10985 (match_operand:TF 1 "gpc_reg_operand" "")))]
10986 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10987 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
10990 rs6000_compare_op0 = operands[0];
10991 rs6000_compare_op1 = operands[1];
10992 rs6000_compare_fp_p = 1;
10996 (define_expand "beq"
10997 [(use (match_operand 0 "" ""))]
10999 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11001 (define_expand "bne"
11002 [(use (match_operand 0 "" ""))]
11004 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11006 (define_expand "bge"
11007 [(use (match_operand 0 "" ""))]
11009 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11011 (define_expand "bgt"
11012 [(use (match_operand 0 "" ""))]
11014 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11016 (define_expand "ble"
11017 [(use (match_operand 0 "" ""))]
11019 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11021 (define_expand "blt"
11022 [(use (match_operand 0 "" ""))]
11024 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11026 (define_expand "bgeu"
11027 [(use (match_operand 0 "" ""))]
11029 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11031 (define_expand "bgtu"
11032 [(use (match_operand 0 "" ""))]
11034 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11036 (define_expand "bleu"
11037 [(use (match_operand 0 "" ""))]
11039 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11041 (define_expand "bltu"
11042 [(use (match_operand 0 "" ""))]
11044 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11046 (define_expand "bunordered"
11047 [(use (match_operand 0 "" ""))]
11049 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11051 (define_expand "bordered"
11052 [(use (match_operand 0 "" ""))]
11054 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11056 (define_expand "buneq"
11057 [(use (match_operand 0 "" ""))]
11059 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11061 (define_expand "bunge"
11062 [(use (match_operand 0 "" ""))]
11064 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11066 (define_expand "bungt"
11067 [(use (match_operand 0 "" ""))]
11069 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11071 (define_expand "bunle"
11072 [(use (match_operand 0 "" ""))]
11074 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11076 (define_expand "bunlt"
11077 [(use (match_operand 0 "" ""))]
11079 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11081 (define_expand "bltgt"
11082 [(use (match_operand 0 "" ""))]
11084 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11086 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11087 ;; For SEQ, likewise, except that comparisons with zero should be done
11088 ;; with an scc insns. However, due to the order that combine see the
11089 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11090 ;; the cases we don't want to handle.
11091 (define_expand "seq"
11092 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11094 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11096 (define_expand "sne"
11097 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11101 if (! rs6000_compare_fp_p)
11104 rs6000_emit_sCOND (NE, operands[0]);
11108 ;; A >= 0 is best done the portable way for A an integer.
11109 (define_expand "sge"
11110 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11114 if (! rs6000_compare_fp_p
11115 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11118 rs6000_emit_sCOND (GE, operands[0]);
11122 ;; A > 0 is best done using the portable sequence, so fail in that case.
11123 (define_expand "sgt"
11124 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11128 if (! rs6000_compare_fp_p
11129 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11132 rs6000_emit_sCOND (GT, operands[0]);
11136 ;; A <= 0 is best done the portable way for A an integer.
11137 (define_expand "sle"
11138 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11142 if (! rs6000_compare_fp_p
11143 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11146 rs6000_emit_sCOND (LE, operands[0]);
11150 ;; A < 0 is best done in the portable way for A an integer.
11151 (define_expand "slt"
11152 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11156 if (! rs6000_compare_fp_p
11157 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11160 rs6000_emit_sCOND (LT, operands[0]);
11164 (define_expand "sgeu"
11165 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11167 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11169 (define_expand "sgtu"
11170 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11172 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11174 (define_expand "sleu"
11175 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11177 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11179 (define_expand "sltu"
11180 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11182 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11184 (define_expand "sunordered"
11185 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11187 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11189 (define_expand "sordered"
11190 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11192 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11194 (define_expand "suneq"
11195 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11197 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11199 (define_expand "sunge"
11200 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11202 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11204 (define_expand "sungt"
11205 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11207 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11209 (define_expand "sunle"
11210 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11212 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11214 (define_expand "sunlt"
11215 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11217 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11219 (define_expand "sltgt"
11220 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11222 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11225 ;; Here are the actual compare insns.
11226 (define_insn "*cmpsi_internal1"
11227 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11228 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11229 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11231 "{cmp%I2|cmpw%I2} %0,%1,%2"
11232 [(set_attr "type" "cmp")])
11234 (define_insn "*cmpdi_internal1"
11235 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11236 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11237 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11240 [(set_attr "type" "cmp")])
11242 ;; If we are comparing a register for equality with a large constant,
11243 ;; we can do this with an XOR followed by a compare. But we need a scratch
11244 ;; register for the result of the XOR.
11247 [(set (match_operand:CC 0 "cc_reg_operand" "")
11248 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11249 (match_operand:SI 2 "non_short_cint_operand" "")))
11250 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11251 "find_single_use (operands[0], insn, 0)
11252 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11253 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11254 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11255 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11258 /* Get the constant we are comparing against, C, and see what it looks like
11259 sign-extended to 16 bits. Then see what constant could be XOR'ed
11260 with C to get the sign-extended value. */
11262 HOST_WIDE_INT c = INTVAL (operands[2]);
11263 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11264 HOST_WIDE_INT xorv = c ^ sextc;
11266 operands[4] = GEN_INT (xorv);
11267 operands[5] = GEN_INT (sextc);
11270 (define_insn "*cmpsi_internal2"
11271 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11272 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11273 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11275 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11276 [(set_attr "type" "cmp")])
11278 (define_insn "*cmpdi_internal2"
11279 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11280 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11281 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11283 "cmpld%I2 %0,%1,%b2"
11284 [(set_attr "type" "cmp")])
11286 ;; The following two insns don't exist as single insns, but if we provide
11287 ;; them, we can swap an add and compare, which will enable us to overlap more
11288 ;; of the required delay between a compare and branch. We generate code for
11289 ;; them by splitting.
11292 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11293 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11294 (match_operand:SI 2 "short_cint_operand" "i")))
11295 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11296 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11299 [(set_attr "length" "8")])
11302 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11303 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11304 (match_operand:SI 2 "u_short_cint_operand" "i")))
11305 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11306 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11309 [(set_attr "length" "8")])
11312 [(set (match_operand:CC 3 "cc_reg_operand" "")
11313 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11314 (match_operand:SI 2 "short_cint_operand" "")))
11315 (set (match_operand:SI 0 "gpc_reg_operand" "")
11316 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11318 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11319 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11322 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11323 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11324 (match_operand:SI 2 "u_short_cint_operand" "")))
11325 (set (match_operand:SI 0 "gpc_reg_operand" "")
11326 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11328 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11329 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11331 (define_insn "*cmpsf_internal1"
11332 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11333 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11334 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11335 "TARGET_HARD_FLOAT && TARGET_FPRS"
11337 [(set_attr "type" "fpcompare")])
11339 (define_insn "*cmpdf_internal1"
11340 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11341 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11342 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11343 "TARGET_HARD_FLOAT && TARGET_FPRS"
11345 [(set_attr "type" "fpcompare")])
11347 ;; Only need to compare second words if first words equal
11348 (define_insn "*cmptf_internal1"
11349 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11350 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11351 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11352 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11353 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11354 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11355 [(set_attr "type" "fpcompare")
11356 (set_attr "length" "12")])
11358 ;; Now we have the scc insns. We can do some combinations because of the
11359 ;; way the machine works.
11361 ;; Note that this is probably faster if we can put an insn between the
11362 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11363 ;; cases the insns below which don't use an intermediate CR field will
11364 ;; be used instead.
11366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11367 (match_operator:SI 1 "scc_comparison_operator"
11368 [(match_operand 2 "cc_reg_operand" "y")
11371 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11372 [(set (attr "type")
11373 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11374 (const_string "mfcrf")
11376 (const_string "mfcr")))
11377 (set_attr "length" "12")])
11379 ;; Same as above, but get the GT bit.
11380 (define_insn "move_from_CR_gt_bit"
11381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11382 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11384 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
11385 [(set_attr "type" "mfcr")
11386 (set_attr "length" "12")])
11388 ;; Same as above, but get the OV/ORDERED bit.
11389 (define_insn "move_from_CR_ov_bit"
11390 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11391 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11393 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11394 [(set_attr "type" "mfcr")
11395 (set_attr "length" "12")])
11398 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11399 (match_operator:DI 1 "scc_comparison_operator"
11400 [(match_operand 2 "cc_reg_operand" "y")
11403 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11404 [(set (attr "type")
11405 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11406 (const_string "mfcrf")
11408 (const_string "mfcr")))
11409 (set_attr "length" "12")])
11412 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11413 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11414 [(match_operand 2 "cc_reg_operand" "y,y")
11417 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11418 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11421 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11423 [(set_attr "type" "delayed_compare")
11424 (set_attr "length" "12,16")])
11427 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11428 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11429 [(match_operand 2 "cc_reg_operand" "")
11432 (set (match_operand:SI 3 "gpc_reg_operand" "")
11433 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11434 "TARGET_32BIT && reload_completed"
11435 [(set (match_dup 3)
11436 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11438 (compare:CC (match_dup 3)
11443 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11444 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11445 [(match_operand 2 "cc_reg_operand" "y")
11447 (match_operand:SI 3 "const_int_operand" "n")))]
11451 int is_bit = ccr_bit (operands[1], 1);
11452 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11455 if (is_bit >= put_bit)
11456 count = is_bit - put_bit;
11458 count = 32 - (put_bit - is_bit);
11460 operands[4] = GEN_INT (count);
11461 operands[5] = GEN_INT (put_bit);
11463 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11465 [(set (attr "type")
11466 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11467 (const_string "mfcrf")
11469 (const_string "mfcr")))
11470 (set_attr "length" "12")])
11473 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11475 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11476 [(match_operand 2 "cc_reg_operand" "y,y")
11478 (match_operand:SI 3 "const_int_operand" "n,n"))
11480 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11481 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11486 int is_bit = ccr_bit (operands[1], 1);
11487 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11490 /* Force split for non-cc0 compare. */
11491 if (which_alternative == 1)
11494 if (is_bit >= put_bit)
11495 count = is_bit - put_bit;
11497 count = 32 - (put_bit - is_bit);
11499 operands[5] = GEN_INT (count);
11500 operands[6] = GEN_INT (put_bit);
11502 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11504 [(set_attr "type" "delayed_compare")
11505 (set_attr "length" "12,16")])
11508 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11510 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11511 [(match_operand 2 "cc_reg_operand" "")
11513 (match_operand:SI 3 "const_int_operand" ""))
11515 (set (match_operand:SI 4 "gpc_reg_operand" "")
11516 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11519 [(set (match_dup 4)
11520 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11523 (compare:CC (match_dup 4)
11527 ;; There is a 3 cycle delay between consecutive mfcr instructions
11528 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11531 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11532 (match_operator:SI 1 "scc_comparison_operator"
11533 [(match_operand 2 "cc_reg_operand" "y")
11535 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11536 (match_operator:SI 4 "scc_comparison_operator"
11537 [(match_operand 5 "cc_reg_operand" "y")
11539 "REGNO (operands[2]) != REGNO (operands[5])"
11540 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11541 [(set_attr "type" "mfcr")
11542 (set_attr "length" "20")])
11545 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11546 (match_operator:DI 1 "scc_comparison_operator"
11547 [(match_operand 2 "cc_reg_operand" "y")
11549 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11550 (match_operator:DI 4 "scc_comparison_operator"
11551 [(match_operand 5 "cc_reg_operand" "y")
11553 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11554 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11555 [(set_attr "type" "mfcr")
11556 (set_attr "length" "20")])
11558 ;; There are some scc insns that can be done directly, without a compare.
11559 ;; These are faster because they don't involve the communications between
11560 ;; the FXU and branch units. In fact, we will be replacing all of the
11561 ;; integer scc insns here or in the portable methods in emit_store_flag.
11563 ;; Also support (neg (scc ..)) since that construct is used to replace
11564 ;; branches, (plus (scc ..) ..) since that construct is common and
11565 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11566 ;; cases where it is no more expensive than (neg (scc ..)).
11568 ;; Have reload force a constant into a register for the simple insns that
11569 ;; otherwise won't accept constants. We do this because it is faster than
11570 ;; the cmp/mfcr sequence we would otherwise generate.
11573 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11574 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11575 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11576 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11579 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11580 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11581 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11582 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11583 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11584 [(set_attr "length" "12,8,12,12,12")])
11587 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11588 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11589 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11590 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11593 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11594 subfic %3,%1,0\;adde %0,%3,%1
11595 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11596 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11597 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11598 [(set_attr "length" "12,8,12,12,12")])
11601 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11603 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11604 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11606 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11607 (eq:SI (match_dup 1) (match_dup 2)))
11608 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11611 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11612 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11613 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11614 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11615 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11621 [(set_attr "type" "compare")
11622 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11625 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11627 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11628 (match_operand:SI 2 "reg_or_cint_operand" ""))
11630 (set (match_operand:SI 0 "gpc_reg_operand" "")
11631 (eq:SI (match_dup 1) (match_dup 2)))
11632 (clobber (match_scratch:SI 3 ""))]
11633 "TARGET_32BIT && reload_completed"
11634 [(parallel [(set (match_dup 0)
11635 (eq:SI (match_dup 1) (match_dup 2)))
11636 (clobber (match_dup 3))])
11638 (compare:CC (match_dup 0)
11643 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11645 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11646 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11648 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11649 (eq:DI (match_dup 1) (match_dup 2)))
11650 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11653 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11654 subfic %3,%1,0\;adde. %0,%3,%1
11655 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11656 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11657 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11663 [(set_attr "type" "compare")
11664 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11667 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11669 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11670 (match_operand:DI 2 "reg_or_cint_operand" ""))
11672 (set (match_operand:DI 0 "gpc_reg_operand" "")
11673 (eq:DI (match_dup 1) (match_dup 2)))
11674 (clobber (match_scratch:DI 3 ""))]
11675 "TARGET_64BIT && reload_completed"
11676 [(parallel [(set (match_dup 0)
11677 (eq:DI (match_dup 1) (match_dup 2)))
11678 (clobber (match_dup 3))])
11680 (compare:CC (match_dup 0)
11684 ;; We have insns of the form shown by the first define_insn below. If
11685 ;; there is something inside the comparison operation, we must split it.
11687 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11688 (plus:SI (match_operator 1 "comparison_operator"
11689 [(match_operand:SI 2 "" "")
11690 (match_operand:SI 3
11691 "reg_or_cint_operand" "")])
11692 (match_operand:SI 4 "gpc_reg_operand" "")))
11693 (clobber (match_operand:SI 5 "register_operand" ""))]
11694 "! gpc_reg_operand (operands[2], SImode)"
11695 [(set (match_dup 5) (match_dup 2))
11696 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11700 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11701 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11702 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11703 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11706 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11707 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11708 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11709 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11710 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11711 [(set_attr "length" "12,8,12,12,12")])
11714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11717 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11718 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11719 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11721 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11724 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11725 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11726 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11727 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11728 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11734 [(set_attr "type" "compare")
11735 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11738 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11741 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11742 (match_operand:SI 2 "reg_or_cint_operand" ""))
11743 (match_operand:SI 3 "gpc_reg_operand" ""))
11745 (clobber (match_scratch:SI 4 ""))]
11746 "TARGET_32BIT && reload_completed"
11747 [(set (match_dup 4)
11748 (plus:SI (eq:SI (match_dup 1)
11752 (compare:CC (match_dup 4)
11757 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11760 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11761 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11762 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11764 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11765 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11768 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11769 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11770 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11771 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11772 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11778 [(set_attr "type" "compare")
11779 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11782 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11785 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11786 (match_operand:SI 2 "reg_or_cint_operand" ""))
11787 (match_operand:SI 3 "gpc_reg_operand" ""))
11789 (set (match_operand:SI 0 "gpc_reg_operand" "")
11790 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11791 "TARGET_32BIT && reload_completed"
11792 [(set (match_dup 0)
11793 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11795 (compare:CC (match_dup 0)
11800 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11801 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11802 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
11805 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11806 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11807 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11808 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11809 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11810 [(set_attr "length" "12,8,12,12,12")])
11812 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11813 ;; since it nabs/sr is just as fast.
11814 (define_insn "*ne0"
11815 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11816 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11818 (clobber (match_scratch:SI 2 "=&r"))]
11819 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
11820 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11821 [(set_attr "length" "8")])
11824 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11825 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11827 (clobber (match_scratch:DI 2 "=&r"))]
11829 "addic %2,%1,-1\;subfe %0,%2,%1"
11830 [(set_attr "length" "8")])
11832 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11835 (plus:SI (lshiftrt:SI
11836 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11838 (match_operand:SI 2 "gpc_reg_operand" "r")))
11839 (clobber (match_scratch:SI 3 "=&r"))]
11841 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11842 [(set_attr "length" "8")])
11845 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11846 (plus:DI (lshiftrt:DI
11847 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11849 (match_operand:DI 2 "gpc_reg_operand" "r")))
11850 (clobber (match_scratch:DI 3 "=&r"))]
11852 "addic %3,%1,-1\;addze %0,%2"
11853 [(set_attr "length" "8")])
11856 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11858 (plus:SI (lshiftrt:SI
11859 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11861 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11863 (clobber (match_scratch:SI 3 "=&r,&r"))
11864 (clobber (match_scratch:SI 4 "=X,&r"))]
11867 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11869 [(set_attr "type" "compare")
11870 (set_attr "length" "8,12")])
11873 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11875 (plus:SI (lshiftrt:SI
11876 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11878 (match_operand:SI 2 "gpc_reg_operand" ""))
11880 (clobber (match_scratch:SI 3 ""))
11881 (clobber (match_scratch:SI 4 ""))]
11882 "TARGET_32BIT && reload_completed"
11883 [(parallel [(set (match_dup 3)
11884 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11887 (clobber (match_dup 4))])
11889 (compare:CC (match_dup 3)
11894 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11896 (plus:DI (lshiftrt:DI
11897 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11899 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11901 (clobber (match_scratch:DI 3 "=&r,&r"))]
11904 addic %3,%1,-1\;addze. %3,%2
11906 [(set_attr "type" "compare")
11907 (set_attr "length" "8,12")])
11910 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11912 (plus:DI (lshiftrt:DI
11913 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11915 (match_operand:DI 2 "gpc_reg_operand" ""))
11917 (clobber (match_scratch:DI 3 ""))]
11918 "TARGET_64BIT && reload_completed"
11919 [(set (match_dup 3)
11920 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11924 (compare:CC (match_dup 3)
11929 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11931 (plus:SI (lshiftrt:SI
11932 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11934 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11936 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11937 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11939 (clobber (match_scratch:SI 3 "=&r,&r"))]
11942 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11944 [(set_attr "type" "compare")
11945 (set_attr "length" "8,12")])
11948 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11950 (plus:SI (lshiftrt:SI
11951 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11953 (match_operand:SI 2 "gpc_reg_operand" ""))
11955 (set (match_operand:SI 0 "gpc_reg_operand" "")
11956 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11958 (clobber (match_scratch:SI 3 ""))]
11959 "TARGET_32BIT && reload_completed"
11960 [(parallel [(set (match_dup 0)
11961 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11963 (clobber (match_dup 3))])
11965 (compare:CC (match_dup 0)
11970 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11972 (plus:DI (lshiftrt:DI
11973 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11975 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11977 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11978 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11980 (clobber (match_scratch:DI 3 "=&r,&r"))]
11983 addic %3,%1,-1\;addze. %0,%2
11985 [(set_attr "type" "compare")
11986 (set_attr "length" "8,12")])
11989 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11991 (plus:DI (lshiftrt:DI
11992 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11994 (match_operand:DI 2 "gpc_reg_operand" ""))
11996 (set (match_operand:DI 0 "gpc_reg_operand" "")
11997 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11999 (clobber (match_scratch:DI 3 ""))]
12000 "TARGET_64BIT && reload_completed"
12001 [(parallel [(set (match_dup 0)
12002 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12004 (clobber (match_dup 3))])
12006 (compare:CC (match_dup 0)
12011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12012 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12013 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12014 (clobber (match_scratch:SI 3 "=r,X"))]
12017 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12018 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12019 [(set_attr "length" "12")])
12022 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12024 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12025 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12027 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12028 (le:SI (match_dup 1) (match_dup 2)))
12029 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12032 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12033 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12036 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12037 (set_attr "length" "12,12,16,16")])
12040 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12042 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12043 (match_operand:SI 2 "reg_or_short_operand" ""))
12045 (set (match_operand:SI 0 "gpc_reg_operand" "")
12046 (le:SI (match_dup 1) (match_dup 2)))
12047 (clobber (match_scratch:SI 3 ""))]
12048 "TARGET_POWER && reload_completed"
12049 [(parallel [(set (match_dup 0)
12050 (le:SI (match_dup 1) (match_dup 2)))
12051 (clobber (match_dup 3))])
12053 (compare:CC (match_dup 0)
12058 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12059 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12060 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12061 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12064 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12065 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12066 [(set_attr "length" "12")])
12069 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12071 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12072 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12073 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12075 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12078 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12079 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12082 [(set_attr "type" "compare")
12083 (set_attr "length" "12,12,16,16")])
12086 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12088 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12089 (match_operand:SI 2 "reg_or_short_operand" ""))
12090 (match_operand:SI 3 "gpc_reg_operand" ""))
12092 (clobber (match_scratch:SI 4 ""))]
12093 "TARGET_POWER && reload_completed"
12094 [(set (match_dup 4)
12095 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12098 (compare:CC (match_dup 4)
12103 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12105 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12106 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12107 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12109 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12110 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12113 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12114 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12117 [(set_attr "type" "compare")
12118 (set_attr "length" "12,12,16,16")])
12121 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12123 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12124 (match_operand:SI 2 "reg_or_short_operand" ""))
12125 (match_operand:SI 3 "gpc_reg_operand" ""))
12127 (set (match_operand:SI 0 "gpc_reg_operand" "")
12128 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12129 "TARGET_POWER && reload_completed"
12130 [(set (match_dup 0)
12131 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12133 (compare:CC (match_dup 0)
12138 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12139 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12140 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12143 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12144 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12145 [(set_attr "length" "12")])
12148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12149 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12150 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12152 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12153 [(set_attr "length" "12")])
12156 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12157 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12158 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12160 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12161 [(set_attr "length" "12")])
12164 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12166 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12167 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12169 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12170 (leu:DI (match_dup 1) (match_dup 2)))]
12173 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12175 [(set_attr "type" "compare")
12176 (set_attr "length" "12,16")])
12179 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12181 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12182 (match_operand:DI 2 "reg_or_short_operand" ""))
12184 (set (match_operand:DI 0 "gpc_reg_operand" "")
12185 (leu:DI (match_dup 1) (match_dup 2)))]
12186 "TARGET_64BIT && reload_completed"
12187 [(set (match_dup 0)
12188 (leu:DI (match_dup 1) (match_dup 2)))
12190 (compare:CC (match_dup 0)
12195 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12197 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12198 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12200 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12201 (leu:SI (match_dup 1) (match_dup 2)))]
12204 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12206 [(set_attr "type" "compare")
12207 (set_attr "length" "12,16")])
12210 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12212 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12213 (match_operand:SI 2 "reg_or_short_operand" ""))
12215 (set (match_operand:SI 0 "gpc_reg_operand" "")
12216 (leu:SI (match_dup 1) (match_dup 2)))]
12217 "TARGET_32BIT && reload_completed"
12218 [(set (match_dup 0)
12219 (leu:SI (match_dup 1) (match_dup 2)))
12221 (compare:CC (match_dup 0)
12226 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12227 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12228 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12229 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12231 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12232 [(set_attr "length" "8")])
12235 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12237 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12238 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12239 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12241 (clobber (match_scratch:SI 4 "=&r,&r"))]
12244 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12246 [(set_attr "type" "compare")
12247 (set_attr "length" "8,12")])
12250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12252 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12253 (match_operand:SI 2 "reg_or_short_operand" ""))
12254 (match_operand:SI 3 "gpc_reg_operand" ""))
12256 (clobber (match_scratch:SI 4 ""))]
12257 "TARGET_32BIT && reload_completed"
12258 [(set (match_dup 4)
12259 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12262 (compare:CC (match_dup 4)
12267 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12269 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12270 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12271 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12273 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12274 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12277 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12279 [(set_attr "type" "compare")
12280 (set_attr "length" "8,12")])
12283 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12285 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12286 (match_operand:SI 2 "reg_or_short_operand" ""))
12287 (match_operand:SI 3 "gpc_reg_operand" ""))
12289 (set (match_operand:SI 0 "gpc_reg_operand" "")
12290 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12291 "TARGET_32BIT && reload_completed"
12292 [(set (match_dup 0)
12293 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12295 (compare:CC (match_dup 0)
12300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12301 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12302 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12304 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12305 [(set_attr "length" "12")])
12308 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12310 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12311 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12312 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12314 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12315 [(set_attr "length" "12")])
12318 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12321 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12322 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12323 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12325 (clobber (match_scratch:SI 4 "=&r,&r"))]
12328 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12330 [(set_attr "type" "compare")
12331 (set_attr "length" "12,16")])
12334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12337 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12338 (match_operand:SI 2 "reg_or_short_operand" "")))
12339 (match_operand:SI 3 "gpc_reg_operand" ""))
12341 (clobber (match_scratch:SI 4 ""))]
12342 "TARGET_32BIT && reload_completed"
12343 [(set (match_dup 4)
12344 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12347 (compare:CC (match_dup 4)
12352 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12355 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12356 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12357 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12359 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12360 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12363 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12365 [(set_attr "type" "compare")
12366 (set_attr "length" "12,16")])
12369 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12372 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12373 (match_operand:SI 2 "reg_or_short_operand" "")))
12374 (match_operand:SI 3 "gpc_reg_operand" ""))
12376 (set (match_operand:SI 0 "gpc_reg_operand" "")
12377 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12378 "TARGET_32BIT && reload_completed"
12379 [(set (match_dup 0)
12380 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12383 (compare:CC (match_dup 0)
12388 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12389 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12390 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12392 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12393 [(set_attr "length" "12")])
12396 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12398 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12399 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12401 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12402 (lt:SI (match_dup 1) (match_dup 2)))]
12405 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12407 [(set_attr "type" "delayed_compare")
12408 (set_attr "length" "12,16")])
12411 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12413 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12414 (match_operand:SI 2 "reg_or_short_operand" ""))
12416 (set (match_operand:SI 0 "gpc_reg_operand" "")
12417 (lt:SI (match_dup 1) (match_dup 2)))]
12418 "TARGET_POWER && reload_completed"
12419 [(set (match_dup 0)
12420 (lt:SI (match_dup 1) (match_dup 2)))
12422 (compare:CC (match_dup 0)
12427 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12428 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12429 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12430 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12432 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12433 [(set_attr "length" "12")])
12436 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12438 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12439 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12440 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12442 (clobber (match_scratch:SI 4 "=&r,&r"))]
12445 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12447 [(set_attr "type" "compare")
12448 (set_attr "length" "12,16")])
12451 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12453 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12454 (match_operand:SI 2 "reg_or_short_operand" ""))
12455 (match_operand:SI 3 "gpc_reg_operand" ""))
12457 (clobber (match_scratch:SI 4 ""))]
12458 "TARGET_POWER && reload_completed"
12459 [(set (match_dup 4)
12460 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12463 (compare:CC (match_dup 4)
12468 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12470 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12471 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12472 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12474 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12475 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12478 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12480 [(set_attr "type" "compare")
12481 (set_attr "length" "12,16")])
12484 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12486 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12487 (match_operand:SI 2 "reg_or_short_operand" ""))
12488 (match_operand:SI 3 "gpc_reg_operand" ""))
12490 (set (match_operand:SI 0 "gpc_reg_operand" "")
12491 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12492 "TARGET_POWER && reload_completed"
12493 [(set (match_dup 0)
12494 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12496 (compare:CC (match_dup 0)
12501 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12502 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12503 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12505 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12506 [(set_attr "length" "12")])
12509 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12510 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12511 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12514 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12515 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12516 [(set_attr "length" "12")])
12519 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12521 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12522 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12524 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12525 (ltu:SI (match_dup 1) (match_dup 2)))]
12528 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12529 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12532 [(set_attr "type" "compare")
12533 (set_attr "length" "12,12,16,16")])
12536 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12538 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12539 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12541 (set (match_operand:SI 0 "gpc_reg_operand" "")
12542 (ltu:SI (match_dup 1) (match_dup 2)))]
12543 "TARGET_32BIT && reload_completed"
12544 [(set (match_dup 0)
12545 (ltu:SI (match_dup 1) (match_dup 2)))
12547 (compare:CC (match_dup 0)
12552 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12553 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12554 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12555 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12558 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12559 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12560 [(set_attr "length" "12")])
12563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12565 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12566 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12567 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12569 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12572 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12573 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12576 [(set_attr "type" "compare")
12577 (set_attr "length" "12,12,16,16")])
12580 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12582 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12583 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12584 (match_operand:SI 3 "gpc_reg_operand" ""))
12586 (clobber (match_scratch:SI 4 ""))]
12587 "TARGET_32BIT && reload_completed"
12588 [(set (match_dup 4)
12589 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12592 (compare:CC (match_dup 4)
12597 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12599 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12600 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12601 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12603 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12604 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12607 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12608 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12611 [(set_attr "type" "compare")
12612 (set_attr "length" "12,12,16,16")])
12615 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12617 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12618 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12619 (match_operand:SI 3 "gpc_reg_operand" ""))
12621 (set (match_operand:SI 0 "gpc_reg_operand" "")
12622 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12623 "TARGET_32BIT && reload_completed"
12624 [(set (match_dup 0)
12625 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12627 (compare:CC (match_dup 0)
12632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12633 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12634 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12637 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12638 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12639 [(set_attr "length" "8")])
12642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12643 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12644 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12645 (clobber (match_scratch:SI 3 "=r"))]
12647 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12648 [(set_attr "length" "12")])
12651 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12653 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12654 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12656 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12657 (ge:SI (match_dup 1) (match_dup 2)))
12658 (clobber (match_scratch:SI 3 "=r,r"))]
12661 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12663 [(set_attr "type" "compare")
12664 (set_attr "length" "12,16")])
12667 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12669 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12670 (match_operand:SI 2 "reg_or_short_operand" ""))
12672 (set (match_operand:SI 0 "gpc_reg_operand" "")
12673 (ge:SI (match_dup 1) (match_dup 2)))
12674 (clobber (match_scratch:SI 3 ""))]
12675 "TARGET_POWER && reload_completed"
12676 [(parallel [(set (match_dup 0)
12677 (ge:SI (match_dup 1) (match_dup 2)))
12678 (clobber (match_dup 3))])
12680 (compare:CC (match_dup 0)
12685 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12686 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12687 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12688 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12690 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12691 [(set_attr "length" "12")])
12694 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12696 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12697 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12698 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12700 (clobber (match_scratch:SI 4 "=&r,&r"))]
12703 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12705 [(set_attr "type" "compare")
12706 (set_attr "length" "12,16")])
12709 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12711 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12712 (match_operand:SI 2 "reg_or_short_operand" ""))
12713 (match_operand:SI 3 "gpc_reg_operand" ""))
12715 (clobber (match_scratch:SI 4 ""))]
12716 "TARGET_POWER && reload_completed"
12717 [(set (match_dup 4)
12718 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12721 (compare:CC (match_dup 4)
12726 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12728 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12729 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12730 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12732 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12733 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12736 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12738 [(set_attr "type" "compare")
12739 (set_attr "length" "12,16")])
12742 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12744 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12745 (match_operand:SI 2 "reg_or_short_operand" ""))
12746 (match_operand:SI 3 "gpc_reg_operand" ""))
12748 (set (match_operand:SI 0 "gpc_reg_operand" "")
12749 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12750 "TARGET_POWER && reload_completed"
12751 [(set (match_dup 0)
12752 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12754 (compare:CC (match_dup 0)
12759 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12760 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12761 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12763 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12764 [(set_attr "length" "12")])
12767 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12768 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12769 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12772 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12773 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12774 [(set_attr "length" "12")])
12777 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12778 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12779 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12782 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12783 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12784 [(set_attr "length" "12")])
12787 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12789 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12790 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12792 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12793 (geu:SI (match_dup 1) (match_dup 2)))]
12796 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12797 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12800 [(set_attr "type" "compare")
12801 (set_attr "length" "12,12,16,16")])
12804 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12806 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12807 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12809 (set (match_operand:SI 0 "gpc_reg_operand" "")
12810 (geu:SI (match_dup 1) (match_dup 2)))]
12811 "TARGET_32BIT && reload_completed"
12812 [(set (match_dup 0)
12813 (geu:SI (match_dup 1) (match_dup 2)))
12815 (compare:CC (match_dup 0)
12820 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12822 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12823 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12825 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12826 (geu:DI (match_dup 1) (match_dup 2)))]
12829 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12830 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12833 [(set_attr "type" "compare")
12834 (set_attr "length" "12,12,16,16")])
12837 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12839 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12840 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12842 (set (match_operand:DI 0 "gpc_reg_operand" "")
12843 (geu:DI (match_dup 1) (match_dup 2)))]
12844 "TARGET_64BIT && reload_completed"
12845 [(set (match_dup 0)
12846 (geu:DI (match_dup 1) (match_dup 2)))
12848 (compare:CC (match_dup 0)
12853 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12854 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12855 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12856 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12859 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12860 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
12861 [(set_attr "length" "8")])
12864 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12866 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12867 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12868 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12870 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12873 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12874 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12877 [(set_attr "type" "compare")
12878 (set_attr "length" "8,8,12,12")])
12881 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12883 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12884 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12885 (match_operand:SI 3 "gpc_reg_operand" ""))
12887 (clobber (match_scratch:SI 4 ""))]
12888 "TARGET_32BIT && reload_completed"
12889 [(set (match_dup 4)
12890 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12893 (compare:CC (match_dup 4)
12898 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12900 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12901 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12902 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12904 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12905 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12908 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12909 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
12912 [(set_attr "type" "compare")
12913 (set_attr "length" "8,8,12,12")])
12916 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12918 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12919 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12920 (match_operand:SI 3 "gpc_reg_operand" ""))
12922 (set (match_operand:SI 0 "gpc_reg_operand" "")
12923 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12924 "TARGET_32BIT && reload_completed"
12925 [(set (match_dup 0)
12926 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12928 (compare:CC (match_dup 0)
12933 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12934 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12935 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12938 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12939 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12940 [(set_attr "length" "12")])
12943 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12945 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12946 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12947 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12950 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12951 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12952 [(set_attr "length" "12")])
12955 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12958 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12959 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12960 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12962 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12965 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12966 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12969 [(set_attr "type" "compare")
12970 (set_attr "length" "12,12,16,16")])
12973 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12976 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12977 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12978 (match_operand:SI 3 "gpc_reg_operand" ""))
12980 (clobber (match_scratch:SI 4 ""))]
12981 "TARGET_32BIT && reload_completed"
12982 [(set (match_dup 4)
12983 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12986 (compare:CC (match_dup 4)
12991 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12994 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12995 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12996 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12998 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12999 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13002 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13003 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13006 [(set_attr "type" "compare")
13007 (set_attr "length" "12,12,16,16")])
13010 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13013 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13014 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13015 (match_operand:SI 3 "gpc_reg_operand" ""))
13017 (set (match_operand:SI 0 "gpc_reg_operand" "")
13018 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13019 "TARGET_32BIT && reload_completed"
13020 [(set (match_dup 0)
13021 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13023 (compare:CC (match_dup 0)
13028 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13029 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13032 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
13033 [(set_attr "length" "12")])
13036 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13037 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13040 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13041 [(set_attr "length" "12")])
13044 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13046 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13049 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13050 (gt:SI (match_dup 1) (const_int 0)))]
13053 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13055 [(set_attr "type" "delayed_compare")
13056 (set_attr "length" "12,16")])
13059 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13061 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13064 (set (match_operand:SI 0 "gpc_reg_operand" "")
13065 (gt:SI (match_dup 1) (const_int 0)))]
13066 "TARGET_32BIT && reload_completed"
13067 [(set (match_dup 0)
13068 (gt:SI (match_dup 1) (const_int 0)))
13070 (compare:CC (match_dup 0)
13075 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13077 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13080 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13081 (gt:DI (match_dup 1) (const_int 0)))]
13084 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13086 [(set_attr "type" "delayed_compare")
13087 (set_attr "length" "12,16")])
13090 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13092 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13095 (set (match_operand:DI 0 "gpc_reg_operand" "")
13096 (gt:DI (match_dup 1) (const_int 0)))]
13097 "TARGET_64BIT && reload_completed"
13098 [(set (match_dup 0)
13099 (gt:DI (match_dup 1) (const_int 0)))
13101 (compare:CC (match_dup 0)
13106 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13107 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13108 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13110 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13111 [(set_attr "length" "12")])
13114 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13116 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13117 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13119 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13120 (gt:SI (match_dup 1) (match_dup 2)))]
13123 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13125 [(set_attr "type" "delayed_compare")
13126 (set_attr "length" "12,16")])
13129 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13131 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13132 (match_operand:SI 2 "reg_or_short_operand" ""))
13134 (set (match_operand:SI 0 "gpc_reg_operand" "")
13135 (gt:SI (match_dup 1) (match_dup 2)))]
13136 "TARGET_POWER && reload_completed"
13137 [(set (match_dup 0)
13138 (gt:SI (match_dup 1) (match_dup 2)))
13140 (compare:CC (match_dup 0)
13145 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13146 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13148 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13150 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13151 [(set_attr "length" "12")])
13154 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13155 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13157 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13159 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13160 [(set_attr "length" "12")])
13163 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13165 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13167 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13169 (clobber (match_scratch:SI 3 "=&r,&r"))]
13172 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13174 [(set_attr "type" "compare")
13175 (set_attr "length" "12,16")])
13178 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13180 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13182 (match_operand:SI 2 "gpc_reg_operand" ""))
13184 (clobber (match_scratch:SI 3 ""))]
13185 "TARGET_32BIT && reload_completed"
13186 [(set (match_dup 3)
13187 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13190 (compare:CC (match_dup 3)
13195 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13197 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13199 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13201 (clobber (match_scratch:DI 3 "=&r,&r"))]
13204 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13206 [(set_attr "type" "compare")
13207 (set_attr "length" "12,16")])
13210 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13212 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13214 (match_operand:DI 2 "gpc_reg_operand" ""))
13216 (clobber (match_scratch:DI 3 ""))]
13217 "TARGET_64BIT && reload_completed"
13218 [(set (match_dup 3)
13219 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13222 (compare:CC (match_dup 3)
13227 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13229 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13231 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13233 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13234 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13237 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13239 [(set_attr "type" "compare")
13240 (set_attr "length" "12,16")])
13243 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13245 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13247 (match_operand:SI 2 "gpc_reg_operand" ""))
13249 (set (match_operand:SI 0 "gpc_reg_operand" "")
13250 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13251 "TARGET_32BIT && reload_completed"
13252 [(set (match_dup 0)
13253 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13255 (compare:CC (match_dup 0)
13260 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13262 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13264 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13266 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13267 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13270 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13272 [(set_attr "type" "compare")
13273 (set_attr "length" "12,16")])
13276 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13278 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13280 (match_operand:DI 2 "gpc_reg_operand" ""))
13282 (set (match_operand:DI 0 "gpc_reg_operand" "")
13283 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13284 "TARGET_64BIT && reload_completed"
13285 [(set (match_dup 0)
13286 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13288 (compare:CC (match_dup 0)
13293 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13294 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13295 (match_operand:SI 2 "reg_or_short_operand" "r"))
13296 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13298 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13299 [(set_attr "length" "12")])
13302 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13304 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13305 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13306 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13308 (clobber (match_scratch:SI 4 "=&r,&r"))]
13311 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13313 [(set_attr "type" "compare")
13314 (set_attr "length" "12,16")])
13317 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13319 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13320 (match_operand:SI 2 "reg_or_short_operand" ""))
13321 (match_operand:SI 3 "gpc_reg_operand" ""))
13323 (clobber (match_scratch:SI 4 ""))]
13324 "TARGET_POWER && reload_completed"
13325 [(set (match_dup 4)
13326 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13328 (compare:CC (match_dup 4)
13333 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13335 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13336 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13337 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13339 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13340 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13343 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13345 [(set_attr "type" "compare")
13346 (set_attr "length" "12,16")])
13349 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13351 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13352 (match_operand:SI 2 "reg_or_short_operand" ""))
13353 (match_operand:SI 3 "gpc_reg_operand" ""))
13355 (set (match_operand:SI 0 "gpc_reg_operand" "")
13356 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13357 "TARGET_POWER && reload_completed"
13358 [(set (match_dup 0)
13359 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13361 (compare:CC (match_dup 0)
13366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13367 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13370 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13371 [(set_attr "length" "12")])
13374 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13375 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13378 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13379 [(set_attr "length" "12")])
13382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13383 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13384 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13386 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13387 [(set_attr "length" "12")])
13390 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13391 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13392 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13394 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
13395 [(set_attr "length" "12")])
13398 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13399 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13400 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13402 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13403 [(set_attr "length" "12")])
13406 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13408 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13409 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13411 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13412 (gtu:SI (match_dup 1) (match_dup 2)))]
13415 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13417 [(set_attr "type" "compare")
13418 (set_attr "length" "12,16")])
13421 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13423 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13424 (match_operand:SI 2 "reg_or_short_operand" ""))
13426 (set (match_operand:SI 0 "gpc_reg_operand" "")
13427 (gtu:SI (match_dup 1) (match_dup 2)))]
13428 "TARGET_32BIT && reload_completed"
13429 [(set (match_dup 0)
13430 (gtu:SI (match_dup 1) (match_dup 2)))
13432 (compare:CC (match_dup 0)
13437 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13439 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13440 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13442 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13443 (gtu:DI (match_dup 1) (match_dup 2)))]
13446 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13448 [(set_attr "type" "compare")
13449 (set_attr "length" "12,16")])
13452 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13454 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13455 (match_operand:DI 2 "reg_or_short_operand" ""))
13457 (set (match_operand:DI 0 "gpc_reg_operand" "")
13458 (gtu:DI (match_dup 1) (match_dup 2)))]
13459 "TARGET_64BIT && reload_completed"
13460 [(set (match_dup 0)
13461 (gtu:DI (match_dup 1) (match_dup 2)))
13463 (compare:CC (match_dup 0)
13468 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13469 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13470 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
13471 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
13474 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13475 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
13476 [(set_attr "length" "8,12")])
13479 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13480 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13481 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
13482 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
13485 addic %0,%1,%k2\;addze %0,%3
13486 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
13487 [(set_attr "length" "8,12")])
13490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13492 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13493 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13494 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13496 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13499 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13500 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13503 [(set_attr "type" "compare")
13504 (set_attr "length" "8,12,12,16")])
13507 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13509 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13510 (match_operand:SI 2 "reg_or_short_operand" ""))
13511 (match_operand:SI 3 "gpc_reg_operand" ""))
13513 (clobber (match_scratch:SI 4 ""))]
13514 "TARGET_32BIT && reload_completed"
13515 [(set (match_dup 4)
13516 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13519 (compare:CC (match_dup 4)
13524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13526 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13527 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13528 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13530 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13533 addic %4,%1,%k2\;addze. %4,%3
13534 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13537 [(set_attr "type" "compare")
13538 (set_attr "length" "8,12,12,16")])
13541 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13543 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13544 (match_operand:DI 2 "reg_or_short_operand" ""))
13545 (match_operand:DI 3 "gpc_reg_operand" ""))
13547 (clobber (match_scratch:DI 4 ""))]
13548 "TARGET_64BIT && reload_completed"
13549 [(set (match_dup 4)
13550 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13553 (compare:CC (match_dup 4)
13558 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13560 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13561 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13562 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13564 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13565 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13568 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13569 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
13572 [(set_attr "type" "compare")
13573 (set_attr "length" "8,12,12,16")])
13576 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13578 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13579 (match_operand:SI 2 "reg_or_short_operand" ""))
13580 (match_operand:SI 3 "gpc_reg_operand" ""))
13582 (set (match_operand:SI 0 "gpc_reg_operand" "")
13583 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13584 "TARGET_32BIT && reload_completed"
13585 [(set (match_dup 0)
13586 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13588 (compare:CC (match_dup 0)
13593 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13595 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13596 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13597 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13599 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13600 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13603 addic %0,%1,%k2\;addze. %0,%3
13604 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
13607 [(set_attr "type" "compare")
13608 (set_attr "length" "8,12,12,16")])
13611 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13613 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13614 (match_operand:DI 2 "reg_or_short_operand" ""))
13615 (match_operand:DI 3 "gpc_reg_operand" ""))
13617 (set (match_operand:DI 0 "gpc_reg_operand" "")
13618 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13619 "TARGET_64BIT && reload_completed"
13620 [(set (match_dup 0)
13621 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13623 (compare:CC (match_dup 0)
13628 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13629 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13630 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13632 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13633 [(set_attr "length" "8")])
13636 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13637 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13638 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13640 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13641 [(set_attr "length" "8")])
13643 ;; Define both directions of branch and return. If we need a reload
13644 ;; register, we'd rather use CR0 since it is much easier to copy a
13645 ;; register CC value to there.
13649 (if_then_else (match_operator 1 "branch_comparison_operator"
13651 "cc_reg_operand" "y")
13653 (label_ref (match_operand 0 "" ""))
13658 return output_cbranch (operands[1], \"%l0\", 0, insn);
13660 [(set_attr "type" "branch")])
13664 (if_then_else (match_operator 0 "branch_comparison_operator"
13666 "cc_reg_operand" "y")
13673 return output_cbranch (operands[0], NULL, 0, insn);
13675 [(set_attr "type" "branch")
13676 (set_attr "length" "4")])
13680 (if_then_else (match_operator 1 "branch_comparison_operator"
13682 "cc_reg_operand" "y")
13685 (label_ref (match_operand 0 "" ""))))]
13689 return output_cbranch (operands[1], \"%l0\", 1, insn);
13691 [(set_attr "type" "branch")])
13695 (if_then_else (match_operator 0 "branch_comparison_operator"
13697 "cc_reg_operand" "y")
13704 return output_cbranch (operands[0], NULL, 1, insn);
13706 [(set_attr "type" "branch")
13707 (set_attr "length" "4")])
13709 ;; Logic on condition register values.
13711 ; This pattern matches things like
13712 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13713 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13715 ; which are generated by the branch logic.
13716 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13718 (define_insn "*cceq_ior_compare"
13719 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13720 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13721 [(match_operator:SI 2
13722 "branch_positive_comparison_operator"
13724 "cc_reg_operand" "y,y")
13726 (match_operator:SI 4
13727 "branch_positive_comparison_operator"
13729 "cc_reg_operand" "0,y")
13733 "cr%q1 %E0,%j2,%j4"
13734 [(set_attr "type" "cr_logical,delayed_cr")])
13736 ; Why is the constant -1 here, but 1 in the previous pattern?
13737 ; Because ~1 has all but the low bit set.
13739 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13740 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13741 [(not:SI (match_operator:SI 2
13742 "branch_positive_comparison_operator"
13744 "cc_reg_operand" "y,y")
13746 (match_operator:SI 4
13747 "branch_positive_comparison_operator"
13749 "cc_reg_operand" "0,y")
13753 "cr%q1 %E0,%j2,%j4"
13754 [(set_attr "type" "cr_logical,delayed_cr")])
13756 (define_insn "*cceq_rev_compare"
13757 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13758 (compare:CCEQ (match_operator:SI 1
13759 "branch_positive_comparison_operator"
13761 "cc_reg_operand" "0,y")
13765 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13766 [(set_attr "type" "cr_logical,delayed_cr")])
13768 ;; If we are comparing the result of two comparisons, this can be done
13769 ;; using creqv or crxor.
13771 (define_insn_and_split ""
13772 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13773 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13774 [(match_operand 2 "cc_reg_operand" "y")
13776 (match_operator 3 "branch_comparison_operator"
13777 [(match_operand 4 "cc_reg_operand" "y")
13782 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13786 int positive_1, positive_2;
13788 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13789 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13792 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
13793 GET_CODE (operands[1])),
13795 operands[2], const0_rtx);
13796 else if (GET_MODE (operands[1]) != SImode)
13797 operands[1] = gen_rtx (GET_CODE (operands[1]),
13799 operands[2], const0_rtx);
13802 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
13803 GET_CODE (operands[3])),
13805 operands[4], const0_rtx);
13806 else if (GET_MODE (operands[3]) != SImode)
13807 operands[3] = gen_rtx (GET_CODE (operands[3]),
13809 operands[4], const0_rtx);
13811 if (positive_1 == positive_2)
13813 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13814 operands[5] = constm1_rtx;
13818 operands[5] = const1_rtx;
13822 ;; Unconditional branch and return.
13824 (define_insn "jump"
13826 (label_ref (match_operand 0 "" "")))]
13829 [(set_attr "type" "branch")])
13831 (define_insn "return"
13835 [(set_attr "type" "jmpreg")])
13837 (define_expand "indirect_jump"
13838 [(set (pc) (match_operand 0 "register_operand" ""))]
13843 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13845 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13849 (define_insn "indirect_jumpsi"
13850 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
13855 [(set_attr "type" "jmpreg")])
13857 (define_insn "indirect_jumpdi"
13858 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
13863 [(set_attr "type" "jmpreg")])
13865 ;; Table jump for switch statements:
13866 (define_expand "tablejump"
13867 [(use (match_operand 0 "" ""))
13868 (use (label_ref (match_operand 1 "" "")))]
13873 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13875 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13879 (define_expand "tablejumpsi"
13880 [(set (match_dup 3)
13881 (plus:SI (match_operand:SI 0 "" "")
13883 (parallel [(set (pc) (match_dup 3))
13884 (use (label_ref (match_operand 1 "" "")))])]
13887 { operands[0] = force_reg (SImode, operands[0]);
13888 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13889 operands[3] = gen_reg_rtx (SImode);
13892 (define_expand "tablejumpdi"
13893 [(set (match_dup 4)
13894 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13896 (plus:DI (match_dup 4)
13898 (parallel [(set (pc) (match_dup 3))
13899 (use (label_ref (match_operand 1 "" "")))])]
13902 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13903 operands[3] = gen_reg_rtx (DImode);
13904 operands[4] = gen_reg_rtx (DImode);
13909 (match_operand:SI 0 "register_operand" "c,*l"))
13910 (use (label_ref (match_operand 1 "" "")))]
13915 [(set_attr "type" "jmpreg")])
13919 (match_operand:DI 0 "register_operand" "c,*l"))
13920 (use (label_ref (match_operand 1 "" "")))]
13925 [(set_attr "type" "jmpreg")])
13930 "{cror 0,0,0|nop}")
13932 ;; Define the subtract-one-and-jump insns, starting with the template
13933 ;; so loop.c knows what to generate.
13935 (define_expand "doloop_end"
13936 [(use (match_operand 0 "" "")) ; loop pseudo
13937 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13938 (use (match_operand 2 "" "")) ; max iterations
13939 (use (match_operand 3 "" "")) ; loop level
13940 (use (match_operand 4 "" ""))] ; label
13944 /* Only use this on innermost loops. */
13945 if (INTVAL (operands[3]) > 1)
13949 if (GET_MODE (operands[0]) != DImode)
13951 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13955 if (GET_MODE (operands[0]) != SImode)
13957 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13962 (define_expand "ctrsi"
13963 [(parallel [(set (pc)
13964 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13966 (label_ref (match_operand 1 "" ""))
13969 (plus:SI (match_dup 0)
13971 (clobber (match_scratch:CC 2 ""))
13972 (clobber (match_scratch:SI 3 ""))])]
13976 (define_expand "ctrdi"
13977 [(parallel [(set (pc)
13978 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13980 (label_ref (match_operand 1 "" ""))
13983 (plus:DI (match_dup 0)
13985 (clobber (match_scratch:CC 2 ""))
13986 (clobber (match_scratch:DI 3 ""))])]
13990 ;; We need to be able to do this for any operand, including MEM, or we
13991 ;; will cause reload to blow up since we don't allow output reloads on
13993 ;; For the length attribute to be calculated correctly, the
13994 ;; label MUST be operand 0.
13996 (define_insn "*ctrsi_internal1"
13998 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14000 (label_ref (match_operand 0 "" ""))
14002 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14003 (plus:SI (match_dup 1)
14005 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14006 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14010 if (which_alternative != 0)
14012 else if (get_attr_length (insn) == 4)
14013 return \"{bdn|bdnz} %l0\";
14015 return \"bdz $+8\;b %l0\";
14017 [(set_attr "type" "branch")
14018 (set_attr "length" "*,12,16,16")])
14020 (define_insn "*ctrsi_internal2"
14022 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14025 (label_ref (match_operand 0 "" ""))))
14026 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14027 (plus:SI (match_dup 1)
14029 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14030 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14034 if (which_alternative != 0)
14036 else if (get_attr_length (insn) == 4)
14037 return \"bdz %l0\";
14039 return \"{bdn|bdnz} $+8\;b %l0\";
14041 [(set_attr "type" "branch")
14042 (set_attr "length" "*,12,16,16")])
14044 (define_insn "*ctrdi_internal1"
14046 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14048 (label_ref (match_operand 0 "" ""))
14050 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14051 (plus:DI (match_dup 1)
14053 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14054 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14058 if (which_alternative != 0)
14060 else if (get_attr_length (insn) == 4)
14061 return \"{bdn|bdnz} %l0\";
14063 return \"bdz $+8\;b %l0\";
14065 [(set_attr "type" "branch")
14066 (set_attr "length" "*,12,16,16")])
14068 (define_insn "*ctrdi_internal2"
14070 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14073 (label_ref (match_operand 0 "" ""))))
14074 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14075 (plus:DI (match_dup 1)
14077 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14078 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14082 if (which_alternative != 0)
14084 else if (get_attr_length (insn) == 4)
14085 return \"bdz %l0\";
14087 return \"{bdn|bdnz} $+8\;b %l0\";
14089 [(set_attr "type" "branch")
14090 (set_attr "length" "*,12,16,16")])
14092 ;; Similar, but we can use GE since we have a REG_NONNEG.
14094 (define_insn "*ctrsi_internal3"
14096 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14098 (label_ref (match_operand 0 "" ""))
14100 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14101 (plus:SI (match_dup 1)
14103 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14104 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14105 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14108 if (which_alternative != 0)
14110 else if (get_attr_length (insn) == 4)
14111 return \"{bdn|bdnz} %l0\";
14113 return \"bdz $+8\;b %l0\";
14115 [(set_attr "type" "branch")
14116 (set_attr "length" "*,12,16,16")])
14118 (define_insn "*ctrsi_internal4"
14120 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14123 (label_ref (match_operand 0 "" ""))))
14124 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14125 (plus:SI (match_dup 1)
14127 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14128 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14129 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
14132 if (which_alternative != 0)
14134 else if (get_attr_length (insn) == 4)
14135 return \"bdz %l0\";
14137 return \"{bdn|bdnz} $+8\;b %l0\";
14139 [(set_attr "type" "branch")
14140 (set_attr "length" "*,12,16,16")])
14142 (define_insn "*ctrdi_internal3"
14144 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14146 (label_ref (match_operand 0 "" ""))
14148 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14149 (plus:DI (match_dup 1)
14151 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14152 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14153 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14156 if (which_alternative != 0)
14158 else if (get_attr_length (insn) == 4)
14159 return \"{bdn|bdnz} %l0\";
14161 return \"bdz $+8\;b %l0\";
14163 [(set_attr "type" "branch")
14164 (set_attr "length" "*,12,16,16")])
14166 (define_insn "*ctrdi_internal4"
14168 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14171 (label_ref (match_operand 0 "" ""))))
14172 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14173 (plus:DI (match_dup 1)
14175 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14176 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14177 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
14180 if (which_alternative != 0)
14182 else if (get_attr_length (insn) == 4)
14183 return \"bdz %l0\";
14185 return \"{bdn|bdnz} $+8\;b %l0\";
14187 [(set_attr "type" "branch")
14188 (set_attr "length" "*,12,16,16")])
14190 ;; Similar but use EQ
14192 (define_insn "*ctrsi_internal5"
14194 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14196 (label_ref (match_operand 0 "" ""))
14198 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14199 (plus:SI (match_dup 1)
14201 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14202 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14206 if (which_alternative != 0)
14208 else if (get_attr_length (insn) == 4)
14209 return \"bdz %l0\";
14211 return \"{bdn|bdnz} $+8\;b %l0\";
14213 [(set_attr "type" "branch")
14214 (set_attr "length" "*,12,16,16")])
14216 (define_insn "*ctrsi_internal6"
14218 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
14221 (label_ref (match_operand 0 "" ""))))
14222 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
14223 (plus:SI (match_dup 1)
14225 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14226 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
14230 if (which_alternative != 0)
14232 else if (get_attr_length (insn) == 4)
14233 return \"{bdn|bdnz} %l0\";
14235 return \"bdz $+8\;b %l0\";
14237 [(set_attr "type" "branch")
14238 (set_attr "length" "*,12,16,16")])
14240 (define_insn "*ctrdi_internal5"
14242 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14244 (label_ref (match_operand 0 "" ""))
14246 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14247 (plus:DI (match_dup 1)
14249 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14250 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14254 if (which_alternative != 0)
14256 else if (get_attr_length (insn) == 4)
14257 return \"bdz %l0\";
14259 return \"{bdn|bdnz} $+8\;b %l0\";
14261 [(set_attr "type" "branch")
14262 (set_attr "length" "*,12,16,16")])
14264 (define_insn "*ctrdi_internal6"
14266 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
14269 (label_ref (match_operand 0 "" ""))))
14270 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
14271 (plus:DI (match_dup 1)
14273 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14274 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
14278 if (which_alternative != 0)
14280 else if (get_attr_length (insn) == 4)
14281 return \"{bdn|bdnz} %l0\";
14283 return \"bdz $+8\;b %l0\";
14285 [(set_attr "type" "branch")
14286 (set_attr "length" "*,12,16,16")])
14288 ;; Now the splitters if we could not allocate the CTR register
14292 (if_then_else (match_operator 2 "comparison_operator"
14293 [(match_operand:SI 1 "gpc_reg_operand" "")
14295 (match_operand 5 "" "")
14296 (match_operand 6 "" "")))
14297 (set (match_operand:SI 0 "gpc_reg_operand" "")
14298 (plus:SI (match_dup 1)
14300 (clobber (match_scratch:CC 3 ""))
14301 (clobber (match_scratch:SI 4 ""))]
14302 "TARGET_32BIT && reload_completed"
14303 [(parallel [(set (match_dup 3)
14304 (compare:CC (plus:SI (match_dup 1)
14308 (plus:SI (match_dup 1)
14310 (set (pc) (if_then_else (match_dup 7)
14314 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14319 (if_then_else (match_operator 2 "comparison_operator"
14320 [(match_operand:SI 1 "gpc_reg_operand" "")
14322 (match_operand 5 "" "")
14323 (match_operand 6 "" "")))
14324 (set (match_operand:SI 0 "nonimmediate_operand" "")
14325 (plus:SI (match_dup 1) (const_int -1)))
14326 (clobber (match_scratch:CC 3 ""))
14327 (clobber (match_scratch:SI 4 ""))]
14328 "TARGET_32BIT && reload_completed
14329 && ! gpc_reg_operand (operands[0], SImode)"
14330 [(parallel [(set (match_dup 3)
14331 (compare:CC (plus:SI (match_dup 1)
14335 (plus:SI (match_dup 1)
14339 (set (pc) (if_then_else (match_dup 7)
14343 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14347 (if_then_else (match_operator 2 "comparison_operator"
14348 [(match_operand:DI 1 "gpc_reg_operand" "")
14350 (match_operand 5 "" "")
14351 (match_operand 6 "" "")))
14352 (set (match_operand:DI 0 "gpc_reg_operand" "")
14353 (plus:DI (match_dup 1)
14355 (clobber (match_scratch:CC 3 ""))
14356 (clobber (match_scratch:DI 4 ""))]
14357 "TARGET_64BIT && reload_completed"
14358 [(parallel [(set (match_dup 3)
14359 (compare:CC (plus:DI (match_dup 1)
14363 (plus:DI (match_dup 1)
14365 (set (pc) (if_then_else (match_dup 7)
14369 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14374 (if_then_else (match_operator 2 "comparison_operator"
14375 [(match_operand:DI 1 "gpc_reg_operand" "")
14377 (match_operand 5 "" "")
14378 (match_operand 6 "" "")))
14379 (set (match_operand:DI 0 "nonimmediate_operand" "")
14380 (plus:DI (match_dup 1) (const_int -1)))
14381 (clobber (match_scratch:CC 3 ""))
14382 (clobber (match_scratch:DI 4 ""))]
14383 "TARGET_64BIT && reload_completed
14384 && ! gpc_reg_operand (operands[0], DImode)"
14385 [(parallel [(set (match_dup 3)
14386 (compare:CC (plus:DI (match_dup 1)
14390 (plus:DI (match_dup 1)
14394 (set (pc) (if_then_else (match_dup 7)
14398 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14401 (define_insn "trap"
14402 [(trap_if (const_int 1) (const_int 0))]
14406 (define_expand "conditional_trap"
14407 [(trap_if (match_operator 0 "trap_comparison_operator"
14408 [(match_dup 2) (match_dup 3)])
14409 (match_operand 1 "const_int_operand" ""))]
14411 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14412 operands[2] = rs6000_compare_op0;
14413 operands[3] = rs6000_compare_op1;")
14416 [(trap_if (match_operator 0 "trap_comparison_operator"
14417 [(match_operand:SI 1 "register_operand" "r")
14418 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14421 "{t|tw}%V0%I2 %1,%2")
14424 [(trap_if (match_operator 0 "trap_comparison_operator"
14425 [(match_operand:DI 1 "register_operand" "r")
14426 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14431 ;; Insns related to generating the function prologue and epilogue.
14433 (define_expand "prologue"
14434 [(use (const_int 0))]
14435 "TARGET_SCHED_PROLOG"
14438 rs6000_emit_prologue ();
14442 (define_insn "*movesi_from_cr_one"
14443 [(match_parallel 0 "mfcr_operation"
14444 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14445 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14446 (match_operand 3 "immediate_operand" "n")]
14447 UNSPEC_MOVESI_FROM_CR))])]
14453 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14455 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14456 operands[4] = GEN_INT (mask);
14457 output_asm_insn (\"mfcr %1,%4\", operands);
14461 [(set_attr "type" "mfcrf")])
14463 (define_insn "movesi_from_cr"
14464 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14465 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14466 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14467 UNSPEC_MOVESI_FROM_CR))]
14470 [(set_attr "type" "mfcr")])
14472 (define_insn "*stmw"
14473 [(match_parallel 0 "stmw_operation"
14474 [(set (match_operand:SI 1 "memory_operand" "=m")
14475 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14477 "{stm|stmw} %2,%1")
14479 (define_insn "*save_fpregs_si"
14480 [(match_parallel 0 "any_operand"
14481 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14482 (use (match_operand:SI 2 "call_operand" "s"))
14483 (set (match_operand:DF 3 "memory_operand" "=m")
14484 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14487 [(set_attr "type" "branch")
14488 (set_attr "length" "4")])
14490 (define_insn "*save_fpregs_di"
14491 [(match_parallel 0 "any_operand"
14492 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14493 (use (match_operand:DI 2 "call_operand" "s"))
14494 (set (match_operand:DF 3 "memory_operand" "=m")
14495 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14498 [(set_attr "type" "branch")
14499 (set_attr "length" "4")])
14501 ; These are to explain that changes to the stack pointer should
14502 ; not be moved over stores to stack memory.
14503 (define_insn "stack_tie"
14504 [(set (match_operand:BLK 0 "memory_operand" "+m")
14505 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14508 [(set_attr "length" "0")])
14511 (define_expand "epilogue"
14512 [(use (const_int 0))]
14513 "TARGET_SCHED_PROLOG"
14516 rs6000_emit_epilogue (FALSE);
14520 ; On some processors, doing the mtcrf one CC register at a time is
14521 ; faster (like on the 604e). On others, doing them all at once is
14522 ; faster; for instance, on the 601 and 750.
14524 (define_expand "movsi_to_cr_one"
14525 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14526 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14527 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14529 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14531 (define_insn "*movsi_to_cr"
14532 [(match_parallel 0 "mtcrf_operation"
14533 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14534 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14535 (match_operand 3 "immediate_operand" "n")]
14536 UNSPEC_MOVESI_TO_CR))])]
14542 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14543 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14544 operands[4] = GEN_INT (mask);
14545 return \"mtcrf %4,%2\";
14547 [(set_attr "type" "mtcr")])
14549 (define_insn "*mtcrfsi"
14550 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14551 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14552 (match_operand 2 "immediate_operand" "n")]
14553 UNSPEC_MOVESI_TO_CR))]
14554 "GET_CODE (operands[0]) == REG
14555 && CR_REGNO_P (REGNO (operands[0]))
14556 && GET_CODE (operands[2]) == CONST_INT
14557 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14559 [(set_attr "type" "mtcr")])
14561 ; The load-multiple instructions have similar properties.
14562 ; Note that "load_multiple" is a name known to the machine-independent
14563 ; code that actually corresponds to the powerpc load-string.
14565 (define_insn "*lmw"
14566 [(match_parallel 0 "lmw_operation"
14567 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14568 (match_operand:SI 2 "memory_operand" "m"))])]
14572 (define_insn "*return_internal_si"
14574 (use (match_operand:SI 0 "register_operand" "lc"))]
14577 [(set_attr "type" "jmpreg")])
14579 (define_insn "*return_internal_di"
14581 (use (match_operand:DI 0 "register_operand" "lc"))]
14584 [(set_attr "type" "jmpreg")])
14586 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14587 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14589 (define_insn "*return_and_restore_fpregs_si"
14590 [(match_parallel 0 "any_operand"
14592 (use (match_operand:SI 1 "register_operand" "l"))
14593 (use (match_operand:SI 2 "call_operand" "s"))
14594 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14595 (match_operand:DF 4 "memory_operand" "m"))])]
14599 (define_insn "*return_and_restore_fpregs_di"
14600 [(match_parallel 0 "any_operand"
14602 (use (match_operand:DI 1 "register_operand" "l"))
14603 (use (match_operand:DI 2 "call_operand" "s"))
14604 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14605 (match_operand:DF 4 "memory_operand" "m"))])]
14609 ; This is used in compiling the unwind routines.
14610 (define_expand "eh_return"
14611 [(use (match_operand 0 "general_operand" ""))]
14616 emit_insn (gen_eh_set_lr_si (operands[0]));
14618 emit_insn (gen_eh_set_lr_di (operands[0]));
14622 ; We can't expand this before we know where the link register is stored.
14623 (define_insn "eh_set_lr_si"
14624 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14626 (clobber (match_scratch:SI 1 "=&b"))]
14630 (define_insn "eh_set_lr_di"
14631 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14633 (clobber (match_scratch:DI 1 "=&b"))]
14638 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14639 (clobber (match_scratch 1 ""))]
14644 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14648 (define_insn "prefetch"
14649 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14650 (match_operand:SI 1 "const_int_operand" "n")
14651 (match_operand:SI 2 "const_int_operand" "n"))]
14655 if (GET_CODE (operands[0]) == REG)
14656 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14657 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14659 [(set_attr "type" "load")])
14661 (include "altivec.md")