1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 ;; See constraints.md for a description of constraints specific to s390.
28 ;; Special formats used for outputting 390 instructions.
30 ;; %C: print opcode suffix for branch condition.
31 ;; %D: print opcode suffix for inverse branch condition.
32 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
33 ;; %G: print the size of the operand in bytes.
34 ;; %O: print only the displacement of a memory reference.
35 ;; %R: print only the base register of a memory reference.
36 ;; %S: print S-type memory reference (base+displacement).
37 ;; %N: print the second word of a DImode operand.
38 ;; %M: print the second word of a TImode operand.
39 ;; %Y: print shift count operand.
41 ;; %b: print integer X as if it's an unsigned byte.
42 ;; %x: print integer X as if it's an unsigned halfword.
43 ;; %h: print integer X as if it's a signed halfword.
44 ;; %i: print the first nonzero HImode part of X.
45 ;; %j: print the first HImode part unequal to -1 of X.
46 ;; %k: print the first nonzero SImode part of X.
47 ;; %m: print the first SImode part unequal to -1 of X.
48 ;; %o: print integer X as if it's an unsigned 32bit word.
50 ;; We have a special constraint for pattern matching.
52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
65 ; GOT/PLT and lt-relative accesses
66 (UNSPEC_LTREL_OFFSET 100)
67 (UNSPEC_LTREL_BASE 101)
75 (UNSPEC_RELOAD_BASE 210)
76 (UNSPEC_MAIN_BASE 211)
81 ; TLS relocation specifiers
86 (UNSPEC_GOTNTPOFF 504)
87 (UNSPEC_INDNTPOFF 505)
90 (UNSPEC_TLSLDM_NTPOFF 511)
97 ; Stack Smashing Protector
103 ;; UNSPEC_VOLATILE usage
111 (UNSPECV_TPF_PROLOGUE 20)
112 (UNSPECV_TPF_EPILOGUE 21)
116 (UNSPECV_POOL_SECTION 201)
117 (UNSPECV_POOL_ALIGN 202)
118 (UNSPECV_POOL_ENTRY 203)
119 (UNSPECV_MAIN_POOL 300)
135 ; Sibling call register.
137 ; Literal pool base register.
139 ; Return address register.
141 ; Condition code register.
143 ; Thread local storage pointer register.
148 ;; Instruction operand type as used in the Principles of Operation.
149 ;; Used to determine defaults for length and other attribute values.
151 (define_attr "op_type"
152 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
155 ;; Instruction type attribute used for scheduling.
157 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
158 cs,vs,store,sem,idiv,
159 imulhi,imulsi,imuldi,
160 branch,jsr,fsimptf,fsimpdf,fsimpsf,
161 floadtf,floaddf,floadsf,fstoredf,fstoresf,
162 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
163 ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf,
164 ftrunctf,ftruncdf,other"
165 (cond [(eq_attr "op_type" "NN") (const_string "other")
166 (eq_attr "op_type" "SS") (const_string "cs")]
167 (const_string "integer")))
169 ;; Another attribute used for scheduling purposes:
170 ;; agen: Instruction uses the address generation unit
171 ;; reg: Instruction does not use the agen unit
173 (define_attr "atype" "agen,reg"
174 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
176 (const_string "agen")))
180 (define_attr "length" ""
181 (cond [(eq_attr "op_type" "E,RR") (const_int 2)
182 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
186 ;; Processor type. This attribute must exactly match the processor_type
187 ;; enumeration in s390.h. The current machine description does not
188 ;; distinguish between g5 and g6, but there are differences between the two
189 ;; CPUs could in theory be modeled.
191 (define_attr "cpu" "g5,g6,z900,z990,z9_109"
192 (const (symbol_ref "s390_tune")))
194 ;; Pipeline description for z900. For lack of anything better,
195 ;; this description is also used for the g5 and g6.
198 ;; Pipeline description for z990.
202 (include "predicates.md")
204 ;; Constraint definitions
205 (include "constraints.md")
212 ;; This mode macro allows floating point patterns to be generated from the
214 (define_mode_macro FPR [TF DF SF])
215 (define_mode_macro DSF [DF SF])
217 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
218 ;; from the same template.
219 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
221 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
222 ;; from the same template.
223 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
224 (define_mode_macro DSI [DI SI])
226 ;; This mode macro allows :P to be used for patterns that operate on
227 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
228 (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
229 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
231 ;; This mode macro allows the QI and HI patterns to be defined from
232 ;; the same template.
233 (define_mode_macro HQI [HI QI])
235 ;; This mode macro allows the integer patterns to be defined from the
237 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
239 ;; This macro allows to unify all 'bCOND' expander patterns.
240 (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered
241 ordered uneq unlt ungt unle unge ltgt])
243 ;; This macro allows to unify all 'sCOND' patterns.
244 (define_code_macro SCOND [ltu gtu leu geu])
246 ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from
247 ;; the same template.
248 (define_code_macro SHIFT [ashift lshiftrt])
250 ;; These macros allow to combine most atomic operations.
251 (define_code_macro ATOMIC [and ior xor plus minus mult])
252 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
253 (plus "add") (minus "sub") (mult "nand")])
256 ;; In FPR templates, a string like "lt<de>br" will expand to "ltxbr" in TFmode,
257 ;; "ltdbr" in DFmode, and "ltebr" in SFmode.
258 (define_mode_attr xde [(TF "x") (DF "d") (SF "e")])
260 ;; In FPR templates, a string like "m<dee>br" will expand to "mxbr" in TFmode,
261 ;; "mdbr" in DFmode, and "meebr" in SFmode.
262 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")])
264 ;; In FPR templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
265 ;; Likewise for "<RXe>".
266 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
267 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
269 ;; In FPR templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
270 ;; This is used to disable the memory alternative in TFmode patterns.
271 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R")])
273 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
274 ;; and "0" in SImode. This allows to combine instructions of which the 31bit
275 ;; version only operates on one register.
276 (define_mode_attr d0 [(DI "d") (SI "0")])
278 ;; In combination with d0 this allows to combine instructions of which the 31bit
279 ;; version only operates on one register. The DImode version needs an additional
280 ;; register for the assembler output.
281 (define_mode_attr 1 [(DI "%1,") (SI "")])
283 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in
284 ;; 'ashift' and "srdl" in 'lshiftrt'.
285 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
287 ;; In SHIFT templates, this attribute holds the correct standard name for the
288 ;; pattern itself and the corresponding function calls.
289 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")])
291 ;; This attribute handles differences in the instruction 'type' and will result
292 ;; in "RRE" for DImode and "RR" for SImode.
293 (define_mode_attr E [(DI "E") (SI "")])
295 ;; This attribute handles differences in the instruction 'type' and makes RX<Y>
296 ;; to result in "RXY" for DImode and "RX" for SImode.
297 (define_mode_attr Y [(DI "Y") (SI "")])
299 ;; This attribute handles differences in the instruction 'type' and will result
300 ;; in "RSE" for TImode and "RS" for DImode.
301 (define_mode_attr TE [(TI "E") (DI "")])
303 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
304 ;; and "lcr" in SImode.
305 (define_mode_attr g [(DI "g") (SI "")])
307 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
308 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions
309 ;; were enhanced with long displacements whereas 31bit instructions got a ..y
310 ;; variant for long displacements.
311 (define_mode_attr y [(DI "g") (SI "y")])
313 ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
314 ;; and "cds" in DImode.
315 (define_mode_attr tg [(TI "g") (DI "")])
317 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
318 ;; and "cfdbr" in SImode.
319 (define_mode_attr gf [(DI "g") (SI "f")])
321 ;; ICM mask required to load MODE value into the lowest subreg
322 ;; of a SImode register.
323 (define_mode_attr icm_lo [(HI "3") (QI "1")])
325 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in
326 ;; HImode and "llgc" in QImode.
327 (define_mode_attr hc [(HI "h") (QI "c")])
329 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI"
331 (define_mode_attr DBL [(DI "TI") (SI "DI")])
333 ;; Maximum unsigned integer that fits in MODE.
334 (define_mode_attr max_uint [(HI "65535") (QI "255")])
338 ;;- Compare instructions.
341 (define_expand "cmp<mode>"
342 [(set (reg:CC CC_REGNUM)
343 (compare:CC (match_operand:GPR 0 "register_operand" "")
344 (match_operand:GPR 1 "general_operand" "")))]
347 s390_compare_op0 = operands[0];
348 s390_compare_op1 = operands[1];
352 (define_expand "cmp<mode>"
353 [(set (reg:CC CC_REGNUM)
354 (compare:CC (match_operand:FPR 0 "register_operand" "")
355 (match_operand:FPR 1 "general_operand" "")))]
358 s390_compare_op0 = operands[0];
359 s390_compare_op1 = operands[1];
364 ; Test-under-Mask instructions
366 (define_insn "*tmqi_mem"
367 [(set (reg CC_REGNUM)
368 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
369 (match_operand:QI 1 "immediate_operand" "n,n"))
370 (match_operand:QI 2 "immediate_operand" "n,n")))]
371 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))"
375 [(set_attr "op_type" "SI,SIY")])
377 (define_insn "*tmdi_reg"
378 [(set (reg CC_REGNUM)
379 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
380 (match_operand:DI 1 "immediate_operand"
381 "N0HD0,N1HD0,N2HD0,N3HD0"))
382 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
384 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
385 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
391 [(set_attr "op_type" "RI")])
393 (define_insn "*tmsi_reg"
394 [(set (reg CC_REGNUM)
395 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
396 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
397 (match_operand:SI 2 "immediate_operand" "n,n")))]
398 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
399 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
403 [(set_attr "op_type" "RI")])
405 (define_insn "*tm<mode>_full"
406 [(set (reg CC_REGNUM)
407 (compare (match_operand:HQI 0 "register_operand" "d")
408 (match_operand:HQI 1 "immediate_operand" "n")))]
409 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
411 [(set_attr "op_type" "RI")])
415 ; Load-and-Test instructions
418 ; tst(di|si) instruction pattern(s).
420 (define_insn "*tstdi_sign"
421 [(set (reg CC_REGNUM)
422 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
423 (const_int 32)) (const_int 32))
424 (match_operand:DI 1 "const0_operand" "")))
425 (set (match_operand:DI 2 "register_operand" "=d")
426 (sign_extend:DI (match_dup 0)))]
427 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
429 [(set_attr "op_type" "RRE")])
432 (define_insn "*tst<mode>_extimm"
433 [(set (reg CC_REGNUM)
434 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
435 (match_operand:GPR 1 "const0_operand" "")))
436 (set (match_operand:GPR 2 "register_operand" "=d,d")
438 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
442 [(set_attr "op_type" "RR<E>,RXY")])
445 (define_insn "*tst<mode>_cconly_extimm"
446 [(set (reg CC_REGNUM)
447 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m")
448 (match_operand:GPR 1 "const0_operand" "")))
449 (clobber (match_scratch:GPR 2 "=X,d"))]
450 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
454 [(set_attr "op_type" "RR<E>,RXY")])
456 (define_insn "*tstdi"
457 [(set (reg CC_REGNUM)
458 (compare (match_operand:DI 0 "register_operand" "d")
459 (match_operand:DI 1 "const0_operand" "")))
460 (set (match_operand:DI 2 "register_operand" "=d")
462 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
464 [(set_attr "op_type" "RRE")])
466 (define_insn "*tstsi"
467 [(set (reg CC_REGNUM)
468 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
469 (match_operand:SI 1 "const0_operand" "")))
470 (set (match_operand:SI 2 "register_operand" "=d,d,d")
472 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM"
477 [(set_attr "op_type" "RR,RS,RSY")])
479 (define_insn "*tstsi_cconly"
480 [(set (reg CC_REGNUM)
481 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
482 (match_operand:SI 1 "const0_operand" "")))
483 (clobber (match_scratch:SI 2 "=X,d,d"))]
484 "s390_match_ccmode(insn, CCSmode)"
489 [(set_attr "op_type" "RR,RS,RSY")])
491 (define_insn "*tstdi_cconly_31"
492 [(set (reg CC_REGNUM)
493 (compare (match_operand:DI 0 "register_operand" "d")
494 (match_operand:DI 1 "const0_operand" "")))]
495 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
497 [(set_attr "op_type" "RS")
498 (set_attr "atype" "reg")])
501 (define_insn "*tst<mode>_cconly2"
502 [(set (reg CC_REGNUM)
503 (compare (match_operand:GPR 0 "register_operand" "d")
504 (match_operand:GPR 1 "const0_operand" "")))]
505 "s390_match_ccmode(insn, CCSmode)"
507 [(set_attr "op_type" "RR<E>")])
509 ; tst(hi|qi) instruction pattern(s).
511 (define_insn "*tst<mode>CCT"
512 [(set (reg CC_REGNUM)
513 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d")
514 (match_operand:HQI 1 "const0_operand" "")))
515 (set (match_operand:HQI 2 "register_operand" "=d,d,0")
517 "s390_match_ccmode(insn, CCTmode)"
520 icmy\t%2,<icm_lo>,%S0
522 [(set_attr "op_type" "RS,RSY,RI")])
524 (define_insn "*tsthiCCT_cconly"
525 [(set (reg CC_REGNUM)
526 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
527 (match_operand:HI 1 "const0_operand" "")))
528 (clobber (match_scratch:HI 2 "=d,d,X"))]
529 "s390_match_ccmode(insn, CCTmode)"
534 [(set_attr "op_type" "RS,RSY,RI")])
536 (define_insn "*tstqiCCT_cconly"
537 [(set (reg CC_REGNUM)
538 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
539 (match_operand:QI 1 "const0_operand" "")))]
540 "s390_match_ccmode(insn, CCTmode)"
545 [(set_attr "op_type" "SI,SIY,RI")])
547 (define_insn "*tst<mode>"
548 [(set (reg CC_REGNUM)
549 (compare (match_operand:HQI 0 "s_operand" "Q,S")
550 (match_operand:HQI 1 "const0_operand" "")))
551 (set (match_operand:HQI 2 "register_operand" "=d,d")
553 "s390_match_ccmode(insn, CCSmode)"
556 icmy\t%2,<icm_lo>,%S0"
557 [(set_attr "op_type" "RS,RSY")])
559 (define_insn "*tst<mode>_cconly"
560 [(set (reg CC_REGNUM)
561 (compare (match_operand:HQI 0 "s_operand" "Q,S")
562 (match_operand:HQI 1 "const0_operand" "")))
563 (clobber (match_scratch:HQI 2 "=d,d"))]
564 "s390_match_ccmode(insn, CCSmode)"
567 icmy\t%2,<icm_lo>,%S0"
568 [(set_attr "op_type" "RS,RSY")])
571 ; Compare (equality) instructions
573 (define_insn "*cmpdi_cct"
574 [(set (reg CC_REGNUM)
575 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
576 (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))]
577 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
584 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")])
586 (define_insn "*cmpsi_cct"
587 [(set (reg CC_REGNUM)
588 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q")
589 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))]
590 "s390_match_ccmode (insn, CCTmode)"
598 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")])
601 ; Compare (signed) instructions
603 (define_insn "*cmpdi_ccs_sign"
604 [(set (reg CC_REGNUM)
605 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
606 (match_operand:DI 0 "register_operand" "d,d")))]
607 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
611 [(set_attr "op_type" "RRE,RXY")])
613 (define_insn "*cmpsi_ccs_sign"
614 [(set (reg CC_REGNUM)
615 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
616 (match_operand:SI 0 "register_operand" "d,d")))]
617 "s390_match_ccmode(insn, CCSRmode)"
621 [(set_attr "op_type" "RX,RXY")])
623 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg
624 (define_insn "*cmp<mode>_ccs"
625 [(set (reg CC_REGNUM)
626 (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d")
627 (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))]
628 "s390_match_ccmode(insn, CCSmode)"
635 [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")])
638 ; Compare (unsigned) instructions
640 (define_insn "*cmpdi_ccu_zero"
641 [(set (reg CC_REGNUM)
642 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
643 (match_operand:DI 0 "register_operand" "d,d")))]
644 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
648 [(set_attr "op_type" "RRE,RXY")])
650 (define_insn "*cmpdi_ccu"
651 [(set (reg CC_REGNUM)
652 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
653 (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))]
654 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
661 [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")])
663 (define_insn "*cmpsi_ccu"
664 [(set (reg CC_REGNUM)
665 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ")
666 (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))]
667 "s390_match_ccmode (insn, CCUmode)"
675 [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")])
677 (define_insn "*cmphi_ccu"
678 [(set (reg CC_REGNUM)
679 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
680 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
681 "s390_match_ccmode (insn, CCUmode)
682 && !register_operand (operands[1], HImode)"
688 [(set_attr "op_type" "RS,RSY,SS,SS")])
690 (define_insn "*cmpqi_ccu"
691 [(set (reg CC_REGNUM)
692 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
693 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
694 "s390_match_ccmode (insn, CCUmode)
695 && !register_operand (operands[1], QImode)"
703 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
706 ; Block compare (CLC) instruction patterns.
709 [(set (reg CC_REGNUM)
710 (compare (match_operand:BLK 0 "memory_operand" "Q")
711 (match_operand:BLK 1 "memory_operand" "Q")))
712 (use (match_operand 2 "const_int_operand" "n"))]
713 "s390_match_ccmode (insn, CCUmode)
714 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
715 "clc\t%O0(%2,%R0),%S1"
716 [(set_attr "op_type" "SS")])
719 [(set (reg CC_REGNUM)
720 (compare (match_operand 0 "memory_operand" "")
721 (match_operand 1 "memory_operand" "")))]
723 && s390_match_ccmode (insn, CCUmode)
724 && GET_MODE (operands[0]) == GET_MODE (operands[1])
725 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
727 [(set (match_dup 0) (match_dup 1))
728 (use (match_dup 2))])]
730 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
731 operands[0] = adjust_address (operands[0], BLKmode, 0);
732 operands[1] = adjust_address (operands[1], BLKmode, 0);
734 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
735 operands[0], operands[1]);
736 operands[0] = SET_DEST (PATTERN (curr_insn));
740 ; (DF|SF) instructions
742 ; ltxbr, ltdbr, ltebr
743 (define_insn "*cmp<mode>_ccs_0"
744 [(set (reg CC_REGNUM)
745 (compare (match_operand:FPR 0 "register_operand" "f")
746 (match_operand:FPR 1 "const0_operand" "")))]
747 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
749 [(set_attr "op_type" "RRE")
750 (set_attr "type" "fsimp<mode>")])
753 (define_insn "*cmp<mode>_ccs_0_ibm"
754 [(set (reg CC_REGNUM)
755 (compare (match_operand:FPR 0 "register_operand" "f")
756 (match_operand:FPR 1 "const0_operand" "")))]
757 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
759 [(set_attr "op_type" "<RRe>")
760 (set_attr "type" "fsimp<mode>")])
762 ; cxbr, cdbr, cebr, cxb, cdb, ceb
763 (define_insn "*cmp<mode>_ccs"
764 [(set (reg CC_REGNUM)
765 (compare (match_operand:FPR 0 "register_operand" "f,f")
766 (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
767 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
771 [(set_attr "op_type" "RRE,RXE")
772 (set_attr "type" "fsimp<mode>")])
774 ; cxr, cdr, cer, cx, cd, ce
775 (define_insn "*cmp<mode>_ccs_ibm"
776 [(set (reg CC_REGNUM)
777 (compare (match_operand:FPR 0 "register_operand" "f,f")
778 (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
779 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
783 [(set_attr "op_type" "<RRe>,<RXe>")
784 (set_attr "type" "fsimp<mode>")])
788 ;;- Move instructions.
792 ; movti instruction pattern(s).
796 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
797 (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))]
805 [(set_attr "op_type" "RSY,RSY,*,*,SS")
806 (set_attr "type" "lm,stm,*,*,*")])
809 [(set (match_operand:TI 0 "nonimmediate_operand" "")
810 (match_operand:TI 1 "general_operand" ""))]
811 "TARGET_64BIT && reload_completed
812 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
813 [(set (match_dup 2) (match_dup 4))
814 (set (match_dup 3) (match_dup 5))]
816 operands[2] = operand_subword (operands[0], 0, 0, TImode);
817 operands[3] = operand_subword (operands[0], 1, 0, TImode);
818 operands[4] = operand_subword (operands[1], 0, 0, TImode);
819 operands[5] = operand_subword (operands[1], 1, 0, TImode);
823 [(set (match_operand:TI 0 "nonimmediate_operand" "")
824 (match_operand:TI 1 "general_operand" ""))]
825 "TARGET_64BIT && reload_completed
826 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
827 [(set (match_dup 2) (match_dup 4))
828 (set (match_dup 3) (match_dup 5))]
830 operands[2] = operand_subword (operands[0], 1, 0, TImode);
831 operands[3] = operand_subword (operands[0], 0, 0, TImode);
832 operands[4] = operand_subword (operands[1], 1, 0, TImode);
833 operands[5] = operand_subword (operands[1], 0, 0, TImode);
837 [(set (match_operand:TI 0 "register_operand" "")
838 (match_operand:TI 1 "memory_operand" ""))]
839 "TARGET_64BIT && reload_completed
840 && !s_operand (operands[1], VOIDmode)"
841 [(set (match_dup 0) (match_dup 1))]
843 rtx addr = operand_subword (operands[0], 1, 0, TImode);
844 s390_load_address (addr, XEXP (operands[1], 0));
845 operands[1] = replace_equiv_address (operands[1], addr);
848 (define_expand "reload_outti"
849 [(parallel [(match_operand:TI 0 "" "")
850 (match_operand:TI 1 "register_operand" "d")
851 (match_operand:DI 2 "register_operand" "=&a")])]
854 gcc_assert (MEM_P (operands[0]));
855 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
856 operands[0] = replace_equiv_address (operands[0], operands[2]);
857 emit_move_insn (operands[0], operands[1]);
862 ; movdi instruction pattern(s).
865 (define_expand "movdi"
866 [(set (match_operand:DI 0 "general_operand" "")
867 (match_operand:DI 1 "general_operand" ""))]
870 /* Handle symbolic constants. */
872 && (SYMBOLIC_CONST (operands[1])
873 || (GET_CODE (operands[1]) == PLUS
874 && XEXP (operands[1], 0) == pic_offset_table_rtx
875 && SYMBOLIC_CONST (XEXP (operands[1], 1)))))
876 emit_symbolic_move (operands);
879 (define_insn "*movdi_larl"
880 [(set (match_operand:DI 0 "register_operand" "=d")
881 (match_operand:DI 1 "larl_operand" "X"))]
883 && !FP_REG_P (operands[0])"
885 [(set_attr "op_type" "RIL")
886 (set_attr "type" "larl")])
888 (define_insn "*movdi_64extimm"
889 [(set (match_operand:DI 0 "nonimmediate_operand"
890 "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
891 (match_operand:DI 1 "general_operand"
892 "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
893 "TARGET_64BIT && TARGET_EXTIMM"
917 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY,
918 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
919 (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store,
920 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
922 (define_insn "*movdi_64"
923 [(set (match_operand:DI 0 "nonimmediate_operand"
924 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
925 (match_operand:DI 1 "general_operand"
926 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
927 "TARGET_64BIT && !TARGET_EXTIMM"
948 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
949 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
950 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
951 floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")])
954 [(set (match_operand:DI 0 "register_operand" "")
955 (match_operand:DI 1 "register_operand" ""))]
956 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
957 [(set (match_dup 2) (match_dup 3))
958 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
959 (set (strict_low_part (match_dup 2)) (match_dup 4))]
960 "operands[2] = gen_lowpart (SImode, operands[0]);
961 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
964 [(set (match_operand:DI 0 "register_operand" "")
965 (match_operand:DI 1 "register_operand" ""))]
966 "TARGET_64BIT && ACCESS_REG_P (operands[0])
967 && dead_or_set_p (insn, operands[1])"
968 [(set (match_dup 3) (match_dup 2))
969 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
970 (set (match_dup 4) (match_dup 2))]
971 "operands[2] = gen_lowpart (SImode, operands[1]);
972 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
975 [(set (match_operand:DI 0 "register_operand" "")
976 (match_operand:DI 1 "register_operand" ""))]
977 "TARGET_64BIT && ACCESS_REG_P (operands[0])
978 && !dead_or_set_p (insn, operands[1])"
979 [(set (match_dup 3) (match_dup 2))
980 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
981 (set (match_dup 4) (match_dup 2))
982 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
983 "operands[2] = gen_lowpart (SImode, operands[1]);
984 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
986 (define_insn "*movdi_31"
987 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q")
988 (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))]
1003 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS")
1004 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")])
1007 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1008 (match_operand:DI 1 "general_operand" ""))]
1009 "!TARGET_64BIT && reload_completed
1010 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
1011 [(set (match_dup 2) (match_dup 4))
1012 (set (match_dup 3) (match_dup 5))]
1014 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1015 operands[3] = operand_subword (operands[0], 1, 0, DImode);
1016 operands[4] = operand_subword (operands[1], 0, 0, DImode);
1017 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1021 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1022 (match_operand:DI 1 "general_operand" ""))]
1023 "!TARGET_64BIT && reload_completed
1024 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
1025 [(set (match_dup 2) (match_dup 4))
1026 (set (match_dup 3) (match_dup 5))]
1028 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1029 operands[3] = operand_subword (operands[0], 0, 0, DImode);
1030 operands[4] = operand_subword (operands[1], 1, 0, DImode);
1031 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1035 [(set (match_operand:DI 0 "register_operand" "")
1036 (match_operand:DI 1 "memory_operand" ""))]
1037 "!TARGET_64BIT && reload_completed
1038 && !FP_REG_P (operands[0])
1039 && !s_operand (operands[1], VOIDmode)"
1040 [(set (match_dup 0) (match_dup 1))]
1042 rtx addr = operand_subword (operands[0], 1, 0, DImode);
1043 s390_load_address (addr, XEXP (operands[1], 0));
1044 operands[1] = replace_equiv_address (operands[1], addr);
1047 (define_expand "reload_outdi"
1048 [(parallel [(match_operand:DI 0 "" "")
1049 (match_operand:DI 1 "register_operand" "d")
1050 (match_operand:SI 2 "register_operand" "=&a")])]
1053 gcc_assert (MEM_P (operands[0]));
1054 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1055 operands[0] = replace_equiv_address (operands[0], operands[2]);
1056 emit_move_insn (operands[0], operands[1]);
1061 [(set (match_operand:DI 0 "register_operand" "")
1062 (mem:DI (match_operand 1 "address_operand" "")))]
1064 && !FP_REG_P (operands[0])
1065 && GET_CODE (operands[1]) == SYMBOL_REF
1066 && CONSTANT_POOL_ADDRESS_P (operands[1])
1067 && get_pool_mode (operands[1]) == DImode
1068 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1069 [(set (match_dup 0) (match_dup 2))]
1070 "operands[2] = get_pool_constant (operands[1]);")
1072 (define_insn "*la_64"
1073 [(set (match_operand:DI 0 "register_operand" "=d,d")
1074 (match_operand:QI 1 "address_operand" "U,W"))]
1079 [(set_attr "op_type" "RX,RXY")
1080 (set_attr "type" "la")])
1084 [(set (match_operand:DI 0 "register_operand" "")
1085 (match_operand:QI 1 "address_operand" ""))
1086 (clobber (reg:CC CC_REGNUM))])]
1088 && preferred_la_operand_p (operands[1], const0_rtx)"
1089 [(set (match_dup 0) (match_dup 1))]
1093 [(set (match_operand:DI 0 "register_operand" "")
1094 (match_operand:DI 1 "register_operand" ""))
1097 (plus:DI (match_dup 0)
1098 (match_operand:DI 2 "nonmemory_operand" "")))
1099 (clobber (reg:CC CC_REGNUM))])]
1101 && !reg_overlap_mentioned_p (operands[0], operands[2])
1102 && preferred_la_operand_p (operands[1], operands[2])"
1103 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1106 (define_expand "reload_indi"
1107 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1108 (match_operand:DI 1 "s390_plus_operand" "")
1109 (match_operand:DI 2 "register_operand" "=&a")])]
1112 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1117 ; movsi instruction pattern(s).
1120 (define_expand "movsi"
1121 [(set (match_operand:SI 0 "general_operand" "")
1122 (match_operand:SI 1 "general_operand" ""))]
1125 /* Handle symbolic constants. */
1127 && (SYMBOLIC_CONST (operands[1])
1128 || (GET_CODE (operands[1]) == PLUS
1129 && XEXP (operands[1], 0) == pic_offset_table_rtx
1130 && SYMBOLIC_CONST (XEXP(operands[1], 1)))))
1131 emit_symbolic_move (operands);
1134 (define_insn "*movsi_larl"
1135 [(set (match_operand:SI 0 "register_operand" "=d")
1136 (match_operand:SI 1 "larl_operand" "X"))]
1137 "!TARGET_64BIT && TARGET_CPU_ZARCH
1138 && !FP_REG_P (operands[0])"
1140 [(set_attr "op_type" "RIL")
1141 (set_attr "type" "larl")])
1143 (define_insn "*movsi_zarch"
1144 [(set (match_operand:SI 0 "nonimmediate_operand"
1145 "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1146 (match_operand:SI 1 "general_operand"
1147 "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1170 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY,
1171 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1172 (set_attr "type" "*,*,*,*,la,lr,load,load,store,store,
1173 floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")])
1175 (define_insn "*movsi_esa"
1176 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1177 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1192 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1193 (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")])
1196 [(set (match_operand:SI 0 "register_operand" "")
1197 (mem:SI (match_operand 1 "address_operand" "")))]
1198 "!FP_REG_P (operands[0])
1199 && GET_CODE (operands[1]) == SYMBOL_REF
1200 && CONSTANT_POOL_ADDRESS_P (operands[1])
1201 && get_pool_mode (operands[1]) == SImode
1202 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1203 [(set (match_dup 0) (match_dup 2))]
1204 "operands[2] = get_pool_constant (operands[1]);")
1206 (define_insn "*la_31"
1207 [(set (match_operand:SI 0 "register_operand" "=d,d")
1208 (match_operand:QI 1 "address_operand" "U,W"))]
1209 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1213 [(set_attr "op_type" "RX,RXY")
1214 (set_attr "type" "la")])
1218 [(set (match_operand:SI 0 "register_operand" "")
1219 (match_operand:QI 1 "address_operand" ""))
1220 (clobber (reg:CC CC_REGNUM))])]
1222 && preferred_la_operand_p (operands[1], const0_rtx)"
1223 [(set (match_dup 0) (match_dup 1))]
1227 [(set (match_operand:SI 0 "register_operand" "")
1228 (match_operand:SI 1 "register_operand" ""))
1231 (plus:SI (match_dup 0)
1232 (match_operand:SI 2 "nonmemory_operand" "")))
1233 (clobber (reg:CC CC_REGNUM))])]
1235 && !reg_overlap_mentioned_p (operands[0], operands[2])
1236 && preferred_la_operand_p (operands[1], operands[2])"
1237 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1240 (define_insn "*la_31_and"
1241 [(set (match_operand:SI 0 "register_operand" "=d,d")
1242 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1243 (const_int 2147483647)))]
1248 [(set_attr "op_type" "RX,RXY")
1249 (set_attr "type" "la")])
1251 (define_insn_and_split "*la_31_and_cc"
1252 [(set (match_operand:SI 0 "register_operand" "=d")
1253 (and:SI (match_operand:QI 1 "address_operand" "p")
1254 (const_int 2147483647)))
1255 (clobber (reg:CC CC_REGNUM))]
1258 "&& reload_completed"
1260 (and:SI (match_dup 1) (const_int 2147483647)))]
1262 [(set_attr "op_type" "RX")
1263 (set_attr "type" "la")])
1265 (define_insn "force_la_31"
1266 [(set (match_operand:SI 0 "register_operand" "=d,d")
1267 (match_operand:QI 1 "address_operand" "U,W"))
1268 (use (const_int 0))]
1273 [(set_attr "op_type" "RX")
1274 (set_attr "type" "la")])
1276 (define_expand "reload_insi"
1277 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1278 (match_operand:SI 1 "s390_plus_operand" "")
1279 (match_operand:SI 2 "register_operand" "=&a")])]
1282 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1287 ; movhi instruction pattern(s).
1290 (define_expand "movhi"
1291 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1292 (match_operand:HI 1 "general_operand" ""))]
1295 /* Make it explicit that loading a register from memory
1296 always sign-extends (at least) to SImode. */
1297 if (optimize && !no_new_pseudos
1298 && register_operand (operands[0], VOIDmode)
1299 && GET_CODE (operands[1]) == MEM)
1301 rtx tmp = gen_reg_rtx (SImode);
1302 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1303 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1304 operands[1] = gen_lowpart (HImode, tmp);
1308 (define_insn "*movhi"
1309 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1310 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1320 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1321 (set_attr "type" "lr,*,*,*,store,store,*")])
1324 [(set (match_operand:HI 0 "register_operand" "")
1325 (mem:HI (match_operand 1 "address_operand" "")))]
1326 "GET_CODE (operands[1]) == SYMBOL_REF
1327 && CONSTANT_POOL_ADDRESS_P (operands[1])
1328 && get_pool_mode (operands[1]) == HImode
1329 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1330 [(set (match_dup 0) (match_dup 2))]
1331 "operands[2] = get_pool_constant (operands[1]);")
1334 ; movqi instruction pattern(s).
1337 (define_expand "movqi"
1338 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1339 (match_operand:QI 1 "general_operand" ""))]
1342 /* On z/Architecture, zero-extending from memory to register
1343 is just as fast as a QImode load. */
1344 if (TARGET_ZARCH && optimize && !no_new_pseudos
1345 && register_operand (operands[0], VOIDmode)
1346 && GET_CODE (operands[1]) == MEM)
1348 rtx tmp = gen_reg_rtx (word_mode);
1349 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1350 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1351 operands[1] = gen_lowpart (QImode, tmp);
1355 (define_insn "*movqi"
1356 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1357 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1369 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1370 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1373 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1374 (mem:QI (match_operand 1 "address_operand" "")))]
1375 "GET_CODE (operands[1]) == SYMBOL_REF
1376 && CONSTANT_POOL_ADDRESS_P (operands[1])
1377 && get_pool_mode (operands[1]) == QImode
1378 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1379 [(set (match_dup 0) (match_dup 2))]
1380 "operands[2] = get_pool_constant (operands[1]);")
1383 ; movstrictqi instruction pattern(s).
1386 (define_insn "*movstrictqi"
1387 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1388 (match_operand:QI 1 "memory_operand" "R,T"))]
1393 [(set_attr "op_type" "RX,RXY")])
1396 ; movstricthi instruction pattern(s).
1399 (define_insn "*movstricthi"
1400 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1401 (match_operand:HI 1 "memory_operand" "Q,S"))
1402 (clobber (reg:CC CC_REGNUM))]
1407 [(set_attr "op_type" "RS,RSY")])
1410 ; movstrictsi instruction pattern(s).
1413 (define_insn "movstrictsi"
1414 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1415 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1422 [(set_attr "op_type" "RR,RX,RXY,RRE")
1423 (set_attr "type" "lr,load,load,*")])
1426 ; movtf instruction pattern(s).
1429 (define_expand "movtf"
1430 [(set (match_operand:TF 0 "nonimmediate_operand" "")
1431 (match_operand:TF 1 "general_operand" ""))]
1435 (define_insn "*movtf_64"
1436 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,d,QS,d,o,Q")
1437 (match_operand:TF 1 "general_operand" "G,f,o,f,QS,d,dm,d,Q"))]
1449 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
1450 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
1452 (define_insn "*movtf_31"
1453 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
1454 (match_operand:TF 1 "general_operand" "G,f,o,f,Q"))]
1462 [(set_attr "op_type" "RRE,RRE,*,*,*")
1463 (set_attr "type" "fsimptf,fsimptf,*,*,*")])
1465 ; TFmode in GPRs splitters
1468 [(set (match_operand:TF 0 "nonimmediate_operand" "")
1469 (match_operand:TF 1 "general_operand" ""))]
1470 "TARGET_64BIT && reload_completed
1471 && s390_split_ok_p (operands[0], operands[1], TFmode, 0)"
1472 [(set (match_dup 2) (match_dup 4))
1473 (set (match_dup 3) (match_dup 5))]
1475 operands[2] = operand_subword (operands[0], 0, 0, TFmode);
1476 operands[3] = operand_subword (operands[0], 1, 0, TFmode);
1477 operands[4] = operand_subword (operands[1], 0, 0, TFmode);
1478 operands[5] = operand_subword (operands[1], 1, 0, TFmode);
1482 [(set (match_operand:TF 0 "nonimmediate_operand" "")
1483 (match_operand:TF 1 "general_operand" ""))]
1484 "TARGET_64BIT && reload_completed
1485 && s390_split_ok_p (operands[0], operands[1], TFmode, 1)"
1486 [(set (match_dup 2) (match_dup 4))
1487 (set (match_dup 3) (match_dup 5))]
1489 operands[2] = operand_subword (operands[0], 1, 0, TFmode);
1490 operands[3] = operand_subword (operands[0], 0, 0, TFmode);
1491 operands[4] = operand_subword (operands[1], 1, 0, TFmode);
1492 operands[5] = operand_subword (operands[1], 0, 0, TFmode);
1496 [(set (match_operand:TF 0 "register_operand" "")
1497 (match_operand:TF 1 "memory_operand" ""))]
1498 "TARGET_64BIT && reload_completed
1499 && !FP_REG_P (operands[0])
1500 && !s_operand (operands[1], VOIDmode)"
1501 [(set (match_dup 0) (match_dup 1))]
1503 rtx addr = operand_subword (operands[0], 1, 0, TFmode);
1504 s390_load_address (addr, XEXP (operands[1], 0));
1505 operands[1] = replace_equiv_address (operands[1], addr);
1508 ; TFmode in FPRs splitters
1511 [(set (match_operand:TF 0 "register_operand" "")
1512 (match_operand:TF 1 "memory_operand" ""))]
1513 "reload_completed && offsettable_memref_p (operands[1])
1514 && FP_REG_P (operands[0])"
1515 [(set (match_dup 2) (match_dup 4))
1516 (set (match_dup 3) (match_dup 5))]
1518 operands[2] = simplify_gen_subreg (DFmode, operands[0], TFmode, 0);
1519 operands[3] = simplify_gen_subreg (DFmode, operands[0], TFmode, 8);
1520 operands[4] = adjust_address_nv (operands[1], DFmode, 0);
1521 operands[5] = adjust_address_nv (operands[1], DFmode, 8);
1525 [(set (match_operand:TF 0 "memory_operand" "")
1526 (match_operand:TF 1 "register_operand" ""))]
1527 "reload_completed && offsettable_memref_p (operands[0])
1528 && FP_REG_P (operands[1])"
1529 [(set (match_dup 2) (match_dup 4))
1530 (set (match_dup 3) (match_dup 5))]
1532 operands[2] = adjust_address_nv (operands[0], DFmode, 0);
1533 operands[3] = adjust_address_nv (operands[0], DFmode, 8);
1534 operands[4] = simplify_gen_subreg (DFmode, operands[1], TFmode, 0);
1535 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, 8);
1538 (define_expand "reload_outtf"
1539 [(parallel [(match_operand:TF 0 "" "")
1540 (match_operand:TF 1 "register_operand" "f")
1541 (match_operand:SI 2 "register_operand" "=&a")])]
1544 rtx addr = gen_lowpart (Pmode, operands[2]);
1546 gcc_assert (MEM_P (operands[0]));
1547 s390_load_address (addr, find_replacement (&XEXP (operands[0], 0)));
1548 operands[0] = replace_equiv_address (operands[0], addr);
1549 emit_move_insn (operands[0], operands[1]);
1553 (define_expand "reload_intf"
1554 [(parallel [(match_operand:TF 0 "register_operand" "=f")
1555 (match_operand:TF 1 "" "")
1556 (match_operand:SI 2 "register_operand" "=&a")])]
1559 rtx addr = gen_lowpart (Pmode, operands[2]);
1561 gcc_assert (MEM_P (operands[1]));
1562 s390_load_address (addr, find_replacement (&XEXP (operands[1], 0)));
1563 operands[1] = replace_equiv_address (operands[1], addr);
1564 emit_move_insn (operands[0], operands[1]);
1569 ; movdf instruction pattern(s).
1572 (define_expand "movdf"
1573 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1574 (match_operand:DF 1 "general_operand" ""))]
1578 (define_insn "*movdf_64"
1579 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
1580 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
1593 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1594 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
1596 (define_insn "*movdf_31"
1597 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q")
1598 (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))]
1614 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
1615 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\
1616 lm,lm,stm,stm,*,*,*")])
1619 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1620 (match_operand:DF 1 "general_operand" ""))]
1621 "!TARGET_64BIT && reload_completed
1622 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1623 [(set (match_dup 2) (match_dup 4))
1624 (set (match_dup 3) (match_dup 5))]
1626 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1627 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1628 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1629 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1633 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1634 (match_operand:DF 1 "general_operand" ""))]
1635 "!TARGET_64BIT && reload_completed
1636 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1637 [(set (match_dup 2) (match_dup 4))
1638 (set (match_dup 3) (match_dup 5))]
1640 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1641 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1642 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1643 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1647 [(set (match_operand:DF 0 "register_operand" "")
1648 (match_operand:DF 1 "memory_operand" ""))]
1649 "!TARGET_64BIT && reload_completed
1650 && !FP_REG_P (operands[0])
1651 && !s_operand (operands[1], VOIDmode)"
1652 [(set (match_dup 0) (match_dup 1))]
1654 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1655 s390_load_address (addr, XEXP (operands[1], 0));
1656 operands[1] = replace_equiv_address (operands[1], addr);
1659 (define_expand "reload_outdf"
1660 [(parallel [(match_operand:DF 0 "" "")
1661 (match_operand:DF 1 "register_operand" "d")
1662 (match_operand:SI 2 "register_operand" "=&a")])]
1665 gcc_assert (MEM_P (operands[0]));
1666 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0)));
1667 operands[0] = replace_equiv_address (operands[0], operands[2]);
1668 emit_move_insn (operands[0], operands[1]);
1673 ; movsf instruction pattern(s).
1676 (define_insn "movsf"
1677 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
1678 (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
1693 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1694 (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
1695 lr,load,load,store,store,*")])
1698 ; movcc instruction pattern
1701 (define_insn "movcc"
1702 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1703 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1713 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1714 (set_attr "type" "lr,*,*,store,store,load,load")])
1717 ; Block move (MVC) patterns.
1721 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1722 (match_operand:BLK 1 "memory_operand" "Q"))
1723 (use (match_operand 2 "const_int_operand" "n"))]
1724 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1725 "mvc\t%O0(%2,%R0),%S1"
1726 [(set_attr "op_type" "SS")])
1729 [(set (match_operand 0 "memory_operand" "")
1730 (match_operand 1 "memory_operand" ""))]
1732 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1733 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1735 [(set (match_dup 0) (match_dup 1))
1736 (use (match_dup 2))])]
1738 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1739 operands[0] = adjust_address (operands[0], BLKmode, 0);
1740 operands[1] = adjust_address (operands[1], BLKmode, 0);
1745 [(set (match_operand:BLK 0 "memory_operand" "")
1746 (match_operand:BLK 1 "memory_operand" ""))
1747 (use (match_operand 2 "const_int_operand" ""))])
1749 [(set (match_operand:BLK 3 "memory_operand" "")
1750 (match_operand:BLK 4 "memory_operand" ""))
1751 (use (match_operand 5 "const_int_operand" ""))])]
1752 "s390_offset_p (operands[0], operands[3], operands[2])
1753 && s390_offset_p (operands[1], operands[4], operands[2])
1754 && !s390_overlap_p (operands[0], operands[1],
1755 INTVAL (operands[2]) + INTVAL (operands[5]))
1756 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1758 [(set (match_dup 6) (match_dup 7))
1759 (use (match_dup 8))])]
1760 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1761 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1762 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1766 ; load_multiple pattern(s).
1768 ; ??? Due to reload problems with replacing registers inside match_parallel
1769 ; we currently support load_multiple/store_multiple only after reload.
1772 (define_expand "load_multiple"
1773 [(match_par_dup 3 [(set (match_operand 0 "" "")
1774 (match_operand 1 "" ""))
1775 (use (match_operand 2 "" ""))])]
1778 enum machine_mode mode;
1784 /* Support only loading a constant number of fixed-point registers from
1785 memory and only bother with this if more than two */
1786 if (GET_CODE (operands[2]) != CONST_INT
1787 || INTVAL (operands[2]) < 2
1788 || INTVAL (operands[2]) > 16
1789 || GET_CODE (operands[1]) != MEM
1790 || GET_CODE (operands[0]) != REG
1791 || REGNO (operands[0]) >= 16)
1794 count = INTVAL (operands[2]);
1795 regno = REGNO (operands[0]);
1796 mode = GET_MODE (operands[0]);
1797 if (mode != SImode && mode != word_mode)
1800 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1803 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1805 from = XEXP (operands[1], 0);
1808 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1809 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1810 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1812 from = XEXP (XEXP (operands[1], 0), 0);
1813 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1820 from = force_reg (Pmode, XEXP (operands[1], 0));
1824 for (i = 0; i < count; i++)
1825 XVECEXP (operands[3], 0, i)
1826 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1827 change_address (operands[1], mode,
1828 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1831 (define_insn "*load_multiple_di"
1832 [(match_parallel 0 "load_multiple_operation"
1833 [(set (match_operand:DI 1 "register_operand" "=r")
1834 (match_operand:DI 2 "s_operand" "QS"))])]
1835 "reload_completed && word_mode == DImode"
1837 int words = XVECLEN (operands[0], 0);
1838 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1839 return "lmg\t%1,%0,%S2";
1841 [(set_attr "op_type" "RSY")
1842 (set_attr "type" "lm")])
1844 (define_insn "*load_multiple_si"
1845 [(match_parallel 0 "load_multiple_operation"
1846 [(set (match_operand:SI 1 "register_operand" "=r,r")
1847 (match_operand:SI 2 "s_operand" "Q,S"))])]
1850 int words = XVECLEN (operands[0], 0);
1851 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1852 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1854 [(set_attr "op_type" "RS,RSY")
1855 (set_attr "type" "lm")])
1858 ; store multiple pattern(s).
1861 (define_expand "store_multiple"
1862 [(match_par_dup 3 [(set (match_operand 0 "" "")
1863 (match_operand 1 "" ""))
1864 (use (match_operand 2 "" ""))])]
1867 enum machine_mode mode;
1873 /* Support only storing a constant number of fixed-point registers to
1874 memory and only bother with this if more than two. */
1875 if (GET_CODE (operands[2]) != CONST_INT
1876 || INTVAL (operands[2]) < 2
1877 || INTVAL (operands[2]) > 16
1878 || GET_CODE (operands[0]) != MEM
1879 || GET_CODE (operands[1]) != REG
1880 || REGNO (operands[1]) >= 16)
1883 count = INTVAL (operands[2]);
1884 regno = REGNO (operands[1]);
1885 mode = GET_MODE (operands[1]);
1886 if (mode != SImode && mode != word_mode)
1889 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1893 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1895 to = XEXP (operands[0], 0);
1898 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1899 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1900 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1902 to = XEXP (XEXP (operands[0], 0), 0);
1903 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1910 to = force_reg (Pmode, XEXP (operands[0], 0));
1914 for (i = 0; i < count; i++)
1915 XVECEXP (operands[3], 0, i)
1916 = gen_rtx_SET (VOIDmode,
1917 change_address (operands[0], mode,
1918 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1919 gen_rtx_REG (mode, regno + i));
1922 (define_insn "*store_multiple_di"
1923 [(match_parallel 0 "store_multiple_operation"
1924 [(set (match_operand:DI 1 "s_operand" "=QS")
1925 (match_operand:DI 2 "register_operand" "r"))])]
1926 "reload_completed && word_mode == DImode"
1928 int words = XVECLEN (operands[0], 0);
1929 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1930 return "stmg\t%2,%0,%S1";
1932 [(set_attr "op_type" "RSY")
1933 (set_attr "type" "stm")])
1936 (define_insn "*store_multiple_si"
1937 [(match_parallel 0 "store_multiple_operation"
1938 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1939 (match_operand:SI 2 "register_operand" "r,r"))])]
1942 int words = XVECLEN (operands[0], 0);
1943 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1944 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1946 [(set_attr "op_type" "RS,RSY")
1947 (set_attr "type" "stm")])
1950 ;; String instructions.
1953 (define_insn "*execute"
1954 [(match_parallel 0 ""
1955 [(unspec [(match_operand 1 "register_operand" "a")
1956 (match_operand:BLK 2 "memory_operand" "R")
1957 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1958 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1959 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1961 [(set_attr "op_type" "RX")
1962 (set_attr "type" "cs")])
1966 ; strlenM instruction pattern(s).
1969 (define_expand "strlen<mode>"
1970 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
1973 (unspec:P [(const_int 0)
1974 (match_operand:BLK 1 "memory_operand" "")
1976 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1977 (clobber (scratch:P))
1978 (clobber (reg:CC CC_REGNUM))])
1980 [(set (match_operand:P 0 "register_operand" "")
1981 (minus:P (match_dup 4) (match_dup 5)))
1982 (clobber (reg:CC CC_REGNUM))])]
1985 operands[4] = gen_reg_rtx (Pmode);
1986 operands[5] = gen_reg_rtx (Pmode);
1987 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1988 operands[1] = replace_equiv_address (operands[1], operands[5]);
1991 (define_insn "*strlen<mode>"
1992 [(set (match_operand:P 0 "register_operand" "=a")
1993 (unspec:P [(match_operand:P 2 "general_operand" "0")
1994 (mem:BLK (match_operand:P 3 "register_operand" "1"))
1996 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1997 (clobber (match_scratch:P 1 "=a"))
1998 (clobber (reg:CC CC_REGNUM))]
2000 "srst\t%0,%1\;jo\t.-4"
2001 [(set_attr "length" "8")
2002 (set_attr "type" "vs")])
2005 ; cmpstrM instruction pattern(s).
2008 (define_expand "cmpstrsi"
2009 [(set (reg:SI 0) (const_int 0))
2011 [(clobber (match_operand 3 "" ""))
2012 (clobber (match_dup 4))
2013 (set (reg:CCU CC_REGNUM)
2014 (compare:CCU (match_operand:BLK 1 "memory_operand" "")
2015 (match_operand:BLK 2 "memory_operand" "")))
2018 [(set (match_operand:SI 0 "register_operand" "=d")
2019 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
2020 (clobber (reg:CC CC_REGNUM))])]
2023 /* As the result of CMPINT is inverted compared to what we need,
2024 we have to swap the operands. */
2025 rtx op1 = operands[2];
2026 rtx op2 = operands[1];
2027 rtx addr1 = gen_reg_rtx (Pmode);
2028 rtx addr2 = gen_reg_rtx (Pmode);
2030 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
2031 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
2032 operands[1] = replace_equiv_address_nv (op1, addr1);
2033 operands[2] = replace_equiv_address_nv (op2, addr2);
2034 operands[3] = addr1;
2035 operands[4] = addr2;
2038 (define_insn "*cmpstr<mode>"
2039 [(clobber (match_operand:P 0 "register_operand" "=d"))
2040 (clobber (match_operand:P 1 "register_operand" "=d"))
2041 (set (reg:CCU CC_REGNUM)
2042 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
2043 (mem:BLK (match_operand:P 3 "register_operand" "1"))))
2046 "clst\t%0,%1\;jo\t.-4"
2047 [(set_attr "length" "8")
2048 (set_attr "type" "vs")])
2051 ; movstr instruction pattern.
2054 (define_expand "movstr"
2055 [(set (reg:SI 0) (const_int 0))
2057 [(clobber (match_dup 3))
2058 (set (match_operand:BLK 1 "memory_operand" "")
2059 (match_operand:BLK 2 "memory_operand" ""))
2060 (set (match_operand 0 "register_operand" "")
2061 (unspec [(match_dup 1)
2063 (reg:SI 0)] UNSPEC_MVST))
2064 (clobber (reg:CC CC_REGNUM))])]
2067 rtx addr1 = gen_reg_rtx (Pmode);
2068 rtx addr2 = gen_reg_rtx (Pmode);
2070 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2071 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
2072 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2073 operands[2] = replace_equiv_address_nv (operands[2], addr2);
2074 operands[3] = addr2;
2077 (define_insn "*movstr"
2078 [(clobber (match_operand:P 2 "register_operand" "=d"))
2079 (set (mem:BLK (match_operand:P 1 "register_operand" "0"))
2080 (mem:BLK (match_operand:P 3 "register_operand" "2")))
2081 (set (match_operand:P 0 "register_operand" "=d")
2082 (unspec [(mem:BLK (match_dup 1))
2083 (mem:BLK (match_dup 3))
2084 (reg:SI 0)] UNSPEC_MVST))
2085 (clobber (reg:CC CC_REGNUM))]
2087 "mvst\t%1,%2\;jo\t.-4"
2088 [(set_attr "length" "8")
2089 (set_attr "type" "vs")])
2093 ; movmemM instruction pattern(s).
2096 (define_expand "movmem<mode>"
2097 [(set (match_operand:BLK 0 "memory_operand" "")
2098 (match_operand:BLK 1 "memory_operand" ""))
2099 (use (match_operand:GPR 2 "general_operand" ""))
2100 (match_operand 3 "" "")]
2102 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
2104 ; Move a block that is up to 256 bytes in length.
2105 ; The block length is taken as (operands[2] % 256) + 1.
2107 (define_expand "movmem_short"
2109 [(set (match_operand:BLK 0 "memory_operand" "")
2110 (match_operand:BLK 1 "memory_operand" ""))
2111 (use (match_operand 2 "nonmemory_operand" ""))
2112 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2113 (clobber (match_dup 3))])]
2115 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2117 (define_insn "*movmem_short"
2118 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2119 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
2120 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2121 (use (match_operand 3 "immediate_operand" "X,R,X"))
2122 (clobber (match_scratch 4 "=X,X,&a"))]
2123 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2124 && GET_MODE (operands[4]) == Pmode"
2126 [(set_attr "type" "cs")])
2129 [(set (match_operand:BLK 0 "memory_operand" "")
2130 (match_operand:BLK 1 "memory_operand" ""))
2131 (use (match_operand 2 "const_int_operand" ""))
2132 (use (match_operand 3 "immediate_operand" ""))
2133 (clobber (scratch))]
2136 [(set (match_dup 0) (match_dup 1))
2137 (use (match_dup 2))])]
2138 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2141 [(set (match_operand:BLK 0 "memory_operand" "")
2142 (match_operand:BLK 1 "memory_operand" ""))
2143 (use (match_operand 2 "register_operand" ""))
2144 (use (match_operand 3 "memory_operand" ""))
2145 (clobber (scratch))]
2148 [(unspec [(match_dup 2) (match_dup 3)
2149 (const_int 0)] UNSPEC_EXECUTE)
2150 (set (match_dup 0) (match_dup 1))
2151 (use (const_int 1))])]
2155 [(set (match_operand:BLK 0 "memory_operand" "")
2156 (match_operand:BLK 1 "memory_operand" ""))
2157 (use (match_operand 2 "register_operand" ""))
2158 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2159 (clobber (match_operand 3 "register_operand" ""))]
2160 "reload_completed && TARGET_CPU_ZARCH"
2161 [(set (match_dup 3) (label_ref (match_dup 4)))
2163 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2164 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2165 (set (match_dup 0) (match_dup 1))
2166 (use (const_int 1))])]
2167 "operands[4] = gen_label_rtx ();")
2169 ; Move a block of arbitrary length.
2171 (define_expand "movmem_long"
2173 [(clobber (match_dup 2))
2174 (clobber (match_dup 3))
2175 (set (match_operand:BLK 0 "memory_operand" "")
2176 (match_operand:BLK 1 "memory_operand" ""))
2177 (use (match_operand 2 "general_operand" ""))
2179 (clobber (reg:CC CC_REGNUM))])]
2182 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2183 rtx reg0 = gen_reg_rtx (dword_mode);
2184 rtx reg1 = gen_reg_rtx (dword_mode);
2185 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2186 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2187 rtx len0 = gen_lowpart (Pmode, reg0);
2188 rtx len1 = gen_lowpart (Pmode, reg1);
2190 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2191 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2192 emit_move_insn (len0, operands[2]);
2194 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2195 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2196 emit_move_insn (len1, operands[2]);
2198 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2199 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2204 (define_insn "*movmem_long"
2205 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2206 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2207 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2208 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))
2211 (clobber (reg:CC CC_REGNUM))]
2213 "mvcle\t%0,%1,0\;jo\t.-4"
2214 [(set_attr "length" "8")
2215 (set_attr "type" "vs")])
2218 ; setmemM instruction pattern(s).
2221 (define_expand "setmem<mode>"
2222 [(set (match_operand:BLK 0 "memory_operand" "")
2223 (match_operand:QI 2 "general_operand" ""))
2224 (use (match_operand:GPR 1 "general_operand" ""))
2225 (match_operand 3 "" "")]
2227 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;")
2229 ; Clear a block that is up to 256 bytes in length.
2230 ; The block length is taken as (operands[1] % 256) + 1.
2232 (define_expand "clrmem_short"
2234 [(set (match_operand:BLK 0 "memory_operand" "")
2236 (use (match_operand 1 "nonmemory_operand" ""))
2237 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2238 (clobber (match_dup 2))
2239 (clobber (reg:CC CC_REGNUM))])]
2241 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2243 (define_insn "*clrmem_short"
2244 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2246 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2247 (use (match_operand 2 "immediate_operand" "X,R,X"))
2248 (clobber (match_scratch 3 "=X,X,&a"))
2249 (clobber (reg:CC CC_REGNUM))]
2250 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2251 && GET_MODE (operands[3]) == Pmode"
2253 [(set_attr "type" "cs")])
2256 [(set (match_operand:BLK 0 "memory_operand" "")
2258 (use (match_operand 1 "const_int_operand" ""))
2259 (use (match_operand 2 "immediate_operand" ""))
2261 (clobber (reg:CC CC_REGNUM))]
2264 [(set (match_dup 0) (const_int 0))
2266 (clobber (reg:CC CC_REGNUM))])]
2267 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2270 [(set (match_operand:BLK 0 "memory_operand" "")
2272 (use (match_operand 1 "register_operand" ""))
2273 (use (match_operand 2 "memory_operand" ""))
2275 (clobber (reg:CC CC_REGNUM))]
2278 [(unspec [(match_dup 1) (match_dup 2)
2279 (const_int 0)] UNSPEC_EXECUTE)
2280 (set (match_dup 0) (const_int 0))
2282 (clobber (reg:CC CC_REGNUM))])]
2286 [(set (match_operand:BLK 0 "memory_operand" "")
2288 (use (match_operand 1 "register_operand" ""))
2289 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2290 (clobber (match_operand 2 "register_operand" ""))
2291 (clobber (reg:CC CC_REGNUM))]
2292 "reload_completed && TARGET_CPU_ZARCH"
2293 [(set (match_dup 2) (label_ref (match_dup 3)))
2295 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2296 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2297 (set (match_dup 0) (const_int 0))
2299 (clobber (reg:CC CC_REGNUM))])]
2300 "operands[3] = gen_label_rtx ();")
2302 ; Initialize a block of arbitrary length with (operands[2] % 256).
2304 (define_expand "setmem_long"
2306 [(clobber (match_dup 1))
2307 (set (match_operand:BLK 0 "memory_operand" "")
2308 (match_operand 2 "shift_count_or_setmem_operand" ""))
2309 (use (match_operand 1 "general_operand" ""))
2311 (clobber (reg:CC CC_REGNUM))])]
2314 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2315 rtx reg0 = gen_reg_rtx (dword_mode);
2316 rtx reg1 = gen_reg_rtx (dword_mode);
2317 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2318 rtx len0 = gen_lowpart (Pmode, reg0);
2320 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2321 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2322 emit_move_insn (len0, operands[1]);
2324 emit_move_insn (reg1, const0_rtx);
2326 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2331 (define_insn "*setmem_long"
2332 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2333 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2334 (match_operand 2 "shift_count_or_setmem_operand" "Y"))
2336 (use (match_operand:<DBL> 1 "register_operand" "d"))
2337 (clobber (reg:CC CC_REGNUM))]
2339 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2340 [(set_attr "length" "8")
2341 (set_attr "type" "vs")])
2343 (define_insn "*setmem_long_and"
2344 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2345 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
2346 (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
2347 (match_operand 4 "const_int_operand" "n")))
2349 (use (match_operand:<DBL> 1 "register_operand" "d"))
2350 (clobber (reg:CC CC_REGNUM))]
2351 "(INTVAL (operands[4]) & 255) == 255"
2352 "mvcle\t%0,%1,%Y2\;jo\t.-4"
2353 [(set_attr "length" "8")
2354 (set_attr "type" "vs")])
2356 ; cmpmemM instruction pattern(s).
2359 (define_expand "cmpmemsi"
2360 [(set (match_operand:SI 0 "register_operand" "")
2361 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2362 (match_operand:BLK 2 "memory_operand" "") ) )
2363 (use (match_operand:SI 3 "general_operand" ""))
2364 (use (match_operand:SI 4 "" ""))]
2366 "s390_expand_cmpmem (operands[0], operands[1],
2367 operands[2], operands[3]); DONE;")
2369 ; Compare a block that is up to 256 bytes in length.
2370 ; The block length is taken as (operands[2] % 256) + 1.
2372 (define_expand "cmpmem_short"
2374 [(set (reg:CCU CC_REGNUM)
2375 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2376 (match_operand:BLK 1 "memory_operand" "")))
2377 (use (match_operand 2 "nonmemory_operand" ""))
2378 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2379 (clobber (match_dup 3))])]
2381 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2383 (define_insn "*cmpmem_short"
2384 [(set (reg:CCU CC_REGNUM)
2385 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2386 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2387 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2388 (use (match_operand 3 "immediate_operand" "X,R,X"))
2389 (clobber (match_scratch 4 "=X,X,&a"))]
2390 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2391 && GET_MODE (operands[4]) == Pmode"
2393 [(set_attr "type" "cs")])
2396 [(set (reg:CCU CC_REGNUM)
2397 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2398 (match_operand:BLK 1 "memory_operand" "")))
2399 (use (match_operand 2 "const_int_operand" ""))
2400 (use (match_operand 3 "immediate_operand" ""))
2401 (clobber (scratch))]
2404 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2405 (use (match_dup 2))])]
2406 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2409 [(set (reg:CCU CC_REGNUM)
2410 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2411 (match_operand:BLK 1 "memory_operand" "")))
2412 (use (match_operand 2 "register_operand" ""))
2413 (use (match_operand 3 "memory_operand" ""))
2414 (clobber (scratch))]
2417 [(unspec [(match_dup 2) (match_dup 3)
2418 (const_int 0)] UNSPEC_EXECUTE)
2419 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2420 (use (const_int 1))])]
2424 [(set (reg:CCU CC_REGNUM)
2425 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2426 (match_operand:BLK 1 "memory_operand" "")))
2427 (use (match_operand 2 "register_operand" ""))
2428 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2429 (clobber (match_operand 3 "register_operand" ""))]
2430 "reload_completed && TARGET_CPU_ZARCH"
2431 [(set (match_dup 3) (label_ref (match_dup 4)))
2433 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2434 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2435 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1)))
2436 (use (const_int 1))])]
2437 "operands[4] = gen_label_rtx ();")
2439 ; Compare a block of arbitrary length.
2441 (define_expand "cmpmem_long"
2443 [(clobber (match_dup 2))
2444 (clobber (match_dup 3))
2445 (set (reg:CCU CC_REGNUM)
2446 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2447 (match_operand:BLK 1 "memory_operand" "")))
2448 (use (match_operand 2 "general_operand" ""))
2449 (use (match_dup 3))])]
2452 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2453 rtx reg0 = gen_reg_rtx (dword_mode);
2454 rtx reg1 = gen_reg_rtx (dword_mode);
2455 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2456 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2457 rtx len0 = gen_lowpart (Pmode, reg0);
2458 rtx len1 = gen_lowpart (Pmode, reg1);
2460 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2461 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2462 emit_move_insn (len0, operands[2]);
2464 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2465 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2466 emit_move_insn (len1, operands[2]);
2468 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2469 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2474 (define_insn "*cmpmem_long"
2475 [(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
2476 (clobber (match_operand:<DBL> 1 "register_operand" "=d"))
2477 (set (reg:CCU CC_REGNUM)
2478 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0))
2479 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
2481 (use (match_dup 3))]
2483 "clcle\t%0,%1,0\;jo\t.-4"
2484 [(set_attr "length" "8")
2485 (set_attr "type" "vs")])
2487 ; Convert CCUmode condition code to integer.
2488 ; Result is zero if EQ, positive if LTU, negative if GTU.
2490 (define_insn_and_split "cmpint"
2491 [(set (match_operand:SI 0 "register_operand" "=d")
2492 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2494 (clobber (reg:CC CC_REGNUM))]
2498 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2500 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2501 (clobber (reg:CC CC_REGNUM))])])
2503 (define_insn_and_split "*cmpint_cc"
2504 [(set (reg CC_REGNUM)
2505 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2508 (set (match_operand:SI 0 "register_operand" "=d")
2509 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2510 "s390_match_ccmode (insn, CCSmode)"
2512 "&& reload_completed"
2513 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2515 [(set (match_dup 2) (match_dup 3))
2516 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2518 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2519 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2520 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2523 (define_insn_and_split "*cmpint_sign"
2524 [(set (match_operand:DI 0 "register_operand" "=d")
2525 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2527 (clobber (reg:CC CC_REGNUM))]
2530 "&& reload_completed"
2531 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2533 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2534 (clobber (reg:CC CC_REGNUM))])])
2536 (define_insn_and_split "*cmpint_sign_cc"
2537 [(set (reg CC_REGNUM)
2538 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2539 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2541 (const_int 32)) (const_int 32))
2543 (set (match_operand:DI 0 "register_operand" "=d")
2544 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2545 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2547 "&& reload_completed"
2548 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2550 [(set (match_dup 2) (match_dup 3))
2551 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2553 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2554 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2555 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2560 ;;- Conversion instructions.
2563 (define_insn "*sethighpartsi"
2564 [(set (match_operand:SI 0 "register_operand" "=d,d")
2565 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S")
2566 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2567 (clobber (reg:CC CC_REGNUM))]
2572 [(set_attr "op_type" "RS,RSY")])
2574 (define_insn "*sethighpartdi_64"
2575 [(set (match_operand:DI 0 "register_operand" "=d")
2576 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
2577 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
2578 (clobber (reg:CC CC_REGNUM))]
2581 [(set_attr "op_type" "RSY")])
2583 (define_insn "*sethighpartdi_31"
2584 [(set (match_operand:DI 0 "register_operand" "=d,d")
2585 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
2586 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
2587 (clobber (reg:CC CC_REGNUM))]
2592 [(set_attr "op_type" "RS,RSY")])
2594 (define_insn_and_split "*extzv<mode>"
2595 [(set (match_operand:GPR 0 "register_operand" "=d")
2596 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2597 (match_operand 2 "const_int_operand" "n")
2599 (clobber (reg:CC CC_REGNUM))]
2600 "INTVAL (operands[2]) > 0
2601 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2603 "&& reload_completed"
2605 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2606 (clobber (reg:CC CC_REGNUM))])
2607 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
2609 int bitsize = INTVAL (operands[2]);
2610 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2611 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2613 operands[1] = adjust_address (operands[1], BLKmode, 0);
2614 set_mem_size (operands[1], GEN_INT (size));
2615 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2616 operands[3] = GEN_INT (mask);
2619 (define_insn_and_split "*extv<mode>"
2620 [(set (match_operand:GPR 0 "register_operand" "=d")
2621 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
2622 (match_operand 2 "const_int_operand" "n")
2624 (clobber (reg:CC CC_REGNUM))]
2625 "INTVAL (operands[2]) > 0
2626 && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)"
2628 "&& reload_completed"
2630 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM))
2631 (clobber (reg:CC CC_REGNUM))])
2633 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2634 (clobber (reg:CC CC_REGNUM))])]
2636 int bitsize = INTVAL (operands[2]);
2637 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
2638 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
2640 operands[1] = adjust_address (operands[1], BLKmode, 0);
2641 set_mem_size (operands[1], GEN_INT (size));
2642 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize);
2643 operands[3] = GEN_INT (mask);
2647 ; insv instruction patterns
2650 (define_expand "insv"
2651 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2652 (match_operand 1 "const_int_operand" "")
2653 (match_operand 2 "const_int_operand" ""))
2654 (match_operand 3 "general_operand" ""))]
2657 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3]))
2662 (define_insn "*insv<mode>_mem_reg"
2663 [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
2664 (match_operand 1 "const_int_operand" "n,n")
2666 (match_operand:P 2 "register_operand" "d,d"))]
2667 "INTVAL (operands[1]) > 0
2668 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2669 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2671 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2673 operands[1] = GEN_INT ((1ul << size) - 1);
2674 return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
2675 : "stcmy\t%2,%1,%S0";
2677 [(set_attr "op_type" "RS,RSY")])
2679 (define_insn "*insvdi_mem_reghigh"
2680 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
2681 (match_operand 1 "const_int_operand" "n")
2683 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
2686 && INTVAL (operands[1]) > 0
2687 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
2688 && INTVAL (operands[1]) % BITS_PER_UNIT == 0"
2690 int size = INTVAL (operands[1]) / BITS_PER_UNIT;
2692 operands[1] = GEN_INT ((1ul << size) - 1);
2693 return "stcmh\t%2,%1,%S0";
2695 [(set_attr "op_type" "RSY")])
2697 (define_insn "*insv<mode>_reg_imm"
2698 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2700 (match_operand 1 "const_int_operand" "n"))
2701 (match_operand:P 2 "const_int_operand" "n"))]
2703 && INTVAL (operands[1]) >= 0
2704 && INTVAL (operands[1]) < BITS_PER_WORD
2705 && INTVAL (operands[1]) % 16 == 0"
2707 switch (BITS_PER_WORD - INTVAL (operands[1]))
2709 case 64: return "iihh\t%0,%x2"; break;
2710 case 48: return "iihl\t%0,%x2"; break;
2711 case 32: return "iilh\t%0,%x2"; break;
2712 case 16: return "iill\t%0,%x2"; break;
2713 default: gcc_unreachable();
2716 [(set_attr "op_type" "RI")])
2718 (define_insn "*insv<mode>_reg_extimm"
2719 [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
2721 (match_operand 1 "const_int_operand" "n"))
2722 (match_operand:P 2 "const_int_operand" "n"))]
2724 && INTVAL (operands[1]) >= 0
2725 && INTVAL (operands[1]) < BITS_PER_WORD
2726 && INTVAL (operands[1]) % 32 == 0"
2728 switch (BITS_PER_WORD - INTVAL (operands[1]))
2730 case 64: return "iihf\t%0,%o2"; break;
2731 case 32: return "iilf\t%0,%o2"; break;
2732 default: gcc_unreachable();
2735 [(set_attr "op_type" "RIL")])
2738 ; extendsidi2 instruction pattern(s).
2741 (define_expand "extendsidi2"
2742 [(set (match_operand:DI 0 "register_operand" "")
2743 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2748 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2749 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2750 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2751 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2756 (define_insn "*extendsidi2"
2757 [(set (match_operand:DI 0 "register_operand" "=d,d")
2758 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2763 [(set_attr "op_type" "RRE,RXY")])
2766 ; extend(hi|qi)(si|di)2 instruction pattern(s).
2769 (define_expand "extend<HQI:mode><DSI:mode>2"
2770 [(set (match_operand:DSI 0 "register_operand" "")
2771 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2774 if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
2776 rtx tmp = gen_reg_rtx (SImode);
2777 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
2778 emit_insn (gen_extendsidi2 (operands[0], tmp));
2781 else if (!TARGET_EXTIMM)
2783 rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) -
2784 GET_MODE_BITSIZE (<HQI:MODE>mode));
2786 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]);
2787 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount));
2788 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount));
2794 ; extendhidi2 instruction pattern(s).
2797 (define_insn "*extendhidi2_extimm"
2798 [(set (match_operand:DI 0 "register_operand" "=d,d")
2799 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2800 "TARGET_64BIT && TARGET_EXTIMM"
2804 [(set_attr "op_type" "RRE,RXY")])
2806 (define_insn "*extendhidi2"
2807 [(set (match_operand:DI 0 "register_operand" "=d")
2808 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2811 [(set_attr "op_type" "RXY")])
2814 ; extendhisi2 instruction pattern(s).
2817 (define_insn "*extendhisi2_extimm"
2818 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2819 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))]
2825 [(set_attr "op_type" "RRE,RX,RXY")])
2827 (define_insn "*extendhisi2"
2828 [(set (match_operand:SI 0 "register_operand" "=d,d")
2829 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2834 [(set_attr "op_type" "RX,RXY")])
2837 ; extendqi(si|di)2 instruction pattern(s).
2840 ; lbr, lgbr, lb, lgb
2841 (define_insn "*extendqi<mode>2_extimm"
2842 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2843 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2848 [(set_attr "op_type" "RRE,RXY")])
2851 (define_insn "*extendqi<mode>2"
2852 [(set (match_operand:GPR 0 "register_operand" "=d")
2853 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))]
2854 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
2856 [(set_attr "op_type" "RXY")])
2858 (define_insn_and_split "*extendqi<mode>2_short_displ"
2859 [(set (match_operand:GPR 0 "register_operand" "=d")
2860 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q")))
2861 (clobber (reg:CC CC_REGNUM))]
2862 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT"
2864 "&& reload_completed"
2866 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM))
2867 (clobber (reg:CC CC_REGNUM))])
2869 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))
2870 (clobber (reg:CC CC_REGNUM))])]
2872 operands[1] = adjust_address (operands[1], BLKmode, 0);
2873 set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode)));
2874 operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)
2875 - GET_MODE_BITSIZE (QImode));
2879 ; zero_extendsidi2 instruction pattern(s).
2882 (define_expand "zero_extendsidi2"
2883 [(set (match_operand:DI 0 "register_operand" "")
2884 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2889 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2890 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2891 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2896 (define_insn "*zero_extendsidi2"
2897 [(set (match_operand:DI 0 "register_operand" "=d,d")
2898 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2903 [(set_attr "op_type" "RRE,RXY")])
2906 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2909 (define_insn "*llgt_sidi"
2910 [(set (match_operand:DI 0 "register_operand" "=d")
2911 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2912 (const_int 2147483647)))]
2915 [(set_attr "op_type" "RXE")])
2917 (define_insn_and_split "*llgt_sidi_split"
2918 [(set (match_operand:DI 0 "register_operand" "=d")
2919 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2920 (const_int 2147483647)))
2921 (clobber (reg:CC CC_REGNUM))]
2924 "&& reload_completed"
2926 (and:DI (subreg:DI (match_dup 1) 0)
2927 (const_int 2147483647)))]
2930 (define_insn "*llgt_sisi"
2931 [(set (match_operand:SI 0 "register_operand" "=d,d")
2932 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2933 (const_int 2147483647)))]
2938 [(set_attr "op_type" "RRE,RXE")])
2940 (define_insn "*llgt_didi"
2941 [(set (match_operand:DI 0 "register_operand" "=d,d")
2942 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2943 (const_int 2147483647)))]
2948 [(set_attr "op_type" "RRE,RXE")])
2951 [(set (match_operand:GPR 0 "register_operand" "")
2952 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
2953 (const_int 2147483647)))
2954 (clobber (reg:CC CC_REGNUM))]
2955 "TARGET_ZARCH && reload_completed"
2957 (and:GPR (match_dup 1)
2958 (const_int 2147483647)))]
2962 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s).
2965 (define_expand "zero_extend<mode>di2"
2966 [(set (match_operand:DI 0 "register_operand" "")
2967 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2972 rtx tmp = gen_reg_rtx (SImode);
2973 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
2974 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2977 else if (!TARGET_EXTIMM)
2979 rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) -
2980 GET_MODE_BITSIZE(<MODE>mode));
2981 operands[1] = gen_lowpart (DImode, operands[1]);
2982 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount));
2983 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount));
2988 (define_expand "zero_extend<mode>si2"
2989 [(set (match_operand:SI 0 "register_operand" "")
2990 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))]
2995 operands[1] = gen_lowpart (SImode, operands[1]);
2996 emit_insn (gen_andsi3 (operands[0], operands[1],
2997 GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1)));
3002 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
3003 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
3004 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3005 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))]
3010 [(set_attr "op_type" "RRE,RXY")])
3013 (define_insn "*zero_extend<HQI:mode><GPR:mode>2"
3014 [(set (match_operand:GPR 0 "register_operand" "=d")
3015 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))]
3016 "TARGET_ZARCH && !TARGET_EXTIMM"
3018 [(set_attr "op_type" "RXY")])
3020 (define_insn_and_split "*zero_extendhisi2_31"
3021 [(set (match_operand:SI 0 "register_operand" "=&d")
3022 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
3023 (clobber (reg:CC CC_REGNUM))]
3026 "&& reload_completed"
3027 [(set (match_dup 0) (const_int 0))
3029 [(set (strict_low_part (match_dup 2)) (match_dup 1))
3030 (clobber (reg:CC CC_REGNUM))])]
3031 "operands[2] = gen_lowpart (HImode, operands[0]);")
3033 (define_insn_and_split "*zero_extendqisi2_31"
3034 [(set (match_operand:SI 0 "register_operand" "=&d")
3035 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3038 "&& reload_completed"
3039 [(set (match_dup 0) (const_int 0))
3040 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3041 "operands[2] = gen_lowpart (QImode, operands[0]);")
3044 ; zero_extendqihi2 instruction pattern(s).
3047 (define_expand "zero_extendqihi2"
3048 [(set (match_operand:HI 0 "register_operand" "")
3049 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3050 "TARGET_ZARCH && !TARGET_EXTIMM"
3052 operands[1] = gen_lowpart (HImode, operands[1]);
3053 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
3057 (define_insn "*zero_extendqihi2_64"
3058 [(set (match_operand:HI 0 "register_operand" "=d")
3059 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3060 "TARGET_ZARCH && !TARGET_EXTIMM"
3062 [(set_attr "op_type" "RXY")])
3064 (define_insn_and_split "*zero_extendqihi2_31"
3065 [(set (match_operand:HI 0 "register_operand" "=&d")
3066 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3069 "&& reload_completed"
3070 [(set (match_dup 0) (const_int 0))
3071 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3072 "operands[2] = gen_lowpart (QImode, operands[0]);")
3076 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
3079 (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
3080 [(set (match_operand:GPR 0 "register_operand" "")
3081 (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
3082 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3084 rtx label1 = gen_label_rtx ();
3085 rtx label2 = gen_label_rtx ();
3086 rtx temp = gen_reg_rtx (<FPR:MODE>mode);
3087 REAL_VALUE_TYPE cmp, sub;
3089 operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
3090 real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
3091 real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
3093 emit_insn (gen_cmp<FPR:mode> (operands[1],
3094 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
3095 emit_jump_insn (gen_blt (label1));
3096 emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
3097 CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
3098 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
3102 emit_label (label1);
3103 emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
3104 operands[1], GEN_INT(5)));
3105 emit_label (label2);
3109 (define_expand "fix_trunc<mode>di2"
3110 [(set (match_operand:DI 0 "register_operand" "")
3111 (fix:DI (match_operand:DSF 1 "nonimmediate_operand" "")))]
3112 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3114 operands[1] = force_reg (<MODE>mode, operands[1]);
3115 emit_insn (gen_fix_trunc<mode>di2_ieee (operands[0], operands[1],
3120 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
3121 (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
3122 [(set (match_operand:GPR 0 "register_operand" "=d")
3123 (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
3124 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
3125 (clobber (reg:CC CC_REGNUM))]
3126 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3127 "c<GPR:gf><FPR:xde>br\t%0,%h2,%1"
3128 [(set_attr "op_type" "RRE")
3129 (set_attr "type" "ftoi")])
3132 ; fix_trunctf(si|di)2 instruction pattern(s).
3135 (define_expand "fix_trunctf<mode>2"
3136 [(parallel [(set (match_operand:GPR 0 "register_operand" "")
3137 (fix:GPR (match_operand:TF 1 "register_operand" "")))
3138 (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
3139 (clobber (reg:CC CC_REGNUM))])]
3140 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3144 ; fix_truncdfsi2 instruction pattern(s).
3147 (define_expand "fix_truncdfsi2"
3148 [(set (match_operand:SI 0 "register_operand" "")
3149 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
3152 if (TARGET_IBM_FLOAT)
3154 /* This is the algorithm from POP chapter A.5.7.2. */
3156 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3157 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
3158 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
3160 operands[1] = force_reg (DFmode, operands[1]);
3161 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
3162 two31r, two32, temp));
3166 operands[1] = force_reg (DFmode, operands[1]);
3167 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3173 (define_insn "fix_truncdfsi2_ibm"
3174 [(set (match_operand:SI 0 "register_operand" "=d")
3175 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
3176 (use (match_operand:DI 2 "immediate_operand" "m"))
3177 (use (match_operand:DI 3 "immediate_operand" "m"))
3178 (use (match_operand:BLK 4 "memory_operand" "m"))
3179 (clobber (reg:CC CC_REGNUM))]
3180 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3182 output_asm_insn ("sd\t%1,%2", operands);
3183 output_asm_insn ("aw\t%1,%3", operands);
3184 output_asm_insn ("std\t%1,%4", operands);
3185 output_asm_insn ("xi\t%N4,128", operands);
3188 [(set_attr "length" "20")])
3191 ; fix_truncsfsi2 instruction pattern(s).
3194 (define_expand "fix_truncsfsi2"
3195 [(set (match_operand:SI 0 "register_operand" "")
3196 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3199 if (TARGET_IBM_FLOAT)
3201 /* Convert to DFmode and then use the POP algorithm. */
3202 rtx temp = gen_reg_rtx (DFmode);
3203 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3204 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3208 operands[1] = force_reg (SFmode, operands[1]);
3209 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3216 ; float(si|di)(tf|df|sf)2 instruction pattern(s).
3219 ; cxgbr, cdgbr, cegbr
3220 (define_insn "floatdi<mode>2"
3221 [(set (match_operand:FPR 0 "register_operand" "=f")
3222 (float:FPR (match_operand:DI 1 "register_operand" "d")))]
3223 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3225 [(set_attr "op_type" "RRE")
3226 (set_attr "type" "itof" )])
3228 ; cxfbr, cdfbr, cefbr
3229 (define_insn "floatsi<mode>2_ieee"
3230 [(set (match_operand:FPR 0 "register_operand" "=f")
3231 (float:FPR (match_operand:SI 1 "register_operand" "d")))]
3232 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3234 [(set_attr "op_type" "RRE")
3235 (set_attr "type" "itof" )])
3239 ; floatsi(tf|df)2 instruction pattern(s).
3242 (define_expand "floatsitf2"
3243 [(set (match_operand:TF 0 "register_operand" "")
3244 (float:TF (match_operand:SI 1 "register_operand" "")))]
3245 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3248 (define_expand "floatsidf2"
3249 [(set (match_operand:DF 0 "register_operand" "")
3250 (float:DF (match_operand:SI 1 "register_operand" "")))]
3253 if (TARGET_IBM_FLOAT)
3255 /* This is the algorithm from POP chapter A.5.7.1. */
3257 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3258 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3260 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3265 (define_insn "floatsidf2_ibm"
3266 [(set (match_operand:DF 0 "register_operand" "=f")
3267 (float:DF (match_operand:SI 1 "register_operand" "d")))
3268 (use (match_operand:DI 2 "immediate_operand" "m"))
3269 (use (match_operand:BLK 3 "memory_operand" "m"))
3270 (clobber (reg:CC CC_REGNUM))]
3271 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3273 output_asm_insn ("st\t%1,%N3", operands);
3274 output_asm_insn ("xi\t%N3,128", operands);
3275 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3276 output_asm_insn ("ld\t%0,%3", operands);
3279 [(set_attr "length" "20")])
3282 ; floatsisf2 instruction pattern(s).
3285 (define_expand "floatsisf2"
3286 [(set (match_operand:SF 0 "register_operand" "")
3287 (float:SF (match_operand:SI 1 "register_operand" "")))]
3290 if (TARGET_IBM_FLOAT)
3292 /* Use the POP algorithm to convert to DFmode and then truncate. */
3293 rtx temp = gen_reg_rtx (DFmode);
3294 emit_insn (gen_floatsidf2 (temp, operands[1]));
3295 emit_insn (gen_truncdfsf2 (operands[0], temp));
3301 ; truncdfsf2 instruction pattern(s).
3304 (define_expand "truncdfsf2"
3305 [(set (match_operand:SF 0 "register_operand" "")
3306 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3310 (define_insn "truncdfsf2_ieee"
3311 [(set (match_operand:SF 0 "register_operand" "=f")
3312 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3313 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3315 [(set_attr "op_type" "RRE")
3316 (set_attr "type" "ftruncdf")])
3318 (define_insn "truncdfsf2_ibm"
3319 [(set (match_operand:SF 0 "register_operand" "=f,f")
3320 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3321 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3325 [(set_attr "op_type" "RR,RX")
3326 (set_attr "type" "floadsf")])
3329 ; trunctfdf2 instruction pattern(s).
3332 (define_expand "trunctfdf2"
3334 [(set (match_operand:DF 0 "register_operand" "")
3335 (float_truncate:DF (match_operand:TF 1 "register_operand" "")))
3336 (clobber (match_scratch:TF 2 "=f"))])]
3340 (define_insn "*trunctfdf2_ieee"
3341 [(set (match_operand:DF 0 "register_operand" "=f")
3342 (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
3343 (clobber (match_scratch:TF 2 "=f"))]
3344 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3345 "ldxbr\t%2,%1\;ldr\t%0,%2"
3346 [(set_attr "length" "6")
3347 (set_attr "type" "ftrunctf")])
3349 (define_insn "*trunctfdf2_ibm"
3350 [(set (match_operand:DF 0 "register_operand" "=f")
3351 (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
3352 (clobber (match_scratch:TF 2 "=f"))]
3353 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3354 "ldxr\t%2,%1\;ldr\t%0,%2"
3355 [(set_attr "length" "4")
3356 (set_attr "type" "ftrunctf")])
3359 ; trunctfsf2 instruction pattern(s).
3362 (define_expand "trunctfsf2"
3364 [(set (match_operand:SF 0 "register_operand" "=f")
3365 (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3366 (clobber (match_scratch:TF 2 "=f"))])]
3370 (define_insn "*trunctfsf2_ieee"
3371 [(set (match_operand:SF 0 "register_operand" "=f")
3372 (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3373 (clobber (match_scratch:TF 2 "=f"))]
3374 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3375 "lexbr\t%2,%1\;ler\t%0,%2"
3376 [(set_attr "length" "6")
3377 (set_attr "type" "ftrunctf")])
3379 (define_insn "*trunctfsf2_ibm"
3380 [(set (match_operand:SF 0 "register_operand" "=f")
3381 (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
3382 (clobber (match_scratch:TF 2 "=f"))]
3383 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3384 "lexr\t%2,%1\;ler\t%0,%2"
3385 [(set_attr "length" "6")
3386 (set_attr "type" "ftrunctf")])
3389 ; extendsfdf2 instruction pattern(s).
3392 (define_expand "extendsfdf2"
3393 [(set (match_operand:DF 0 "register_operand" "")
3394 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3397 if (TARGET_IBM_FLOAT)
3399 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3404 (define_insn "extendsfdf2_ieee"
3405 [(set (match_operand:DF 0 "register_operand" "=f,f")
3406 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3407 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3411 [(set_attr "op_type" "RRE,RXE")
3412 (set_attr "type" "fsimpsf, floadsf")])
3414 (define_insn "extendsfdf2_ibm"
3415 [(set (match_operand:DF 0 "register_operand" "=f,f")
3416 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3417 (clobber (reg:CC CC_REGNUM))]
3418 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3420 sdr\t%0,%0\;ler\t%0,%1
3421 sdr\t%0,%0\;le\t%0,%1"
3422 [(set_attr "length" "4,6")
3423 (set_attr "type" "floadsf")])
3426 ; extenddftf2 instruction pattern(s).
3429 (define_expand "extenddftf2"
3430 [(set (match_operand:TF 0 "register_operand" "")
3431 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
3435 (define_insn "*extenddftf2_ieee"
3436 [(set (match_operand:TF 0 "register_operand" "=f,f")
3437 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3438 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3442 [(set_attr "op_type" "RRE,RXE")
3443 (set_attr "type" "fsimptf, floadtf")])
3445 (define_insn "*extenddftf2_ibm"
3446 [(set (match_operand:TF 0 "register_operand" "=f,f")
3447 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3448 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3452 [(set_attr "op_type" "RRE,RXE")
3453 (set_attr "type" "fsimptf, floadtf")])
3456 ; extendsftf2 instruction pattern(s).
3459 (define_expand "extendsftf2"
3460 [(set (match_operand:TF 0 "register_operand" "")
3461 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
3465 (define_insn "*extendsftf2_ieee"
3466 [(set (match_operand:TF 0 "register_operand" "=f,f")
3467 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3468 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3472 [(set_attr "op_type" "RRE,RXE")
3473 (set_attr "type" "fsimptf, floadtf")])
3475 (define_insn "*extendsftf2_ibm"
3476 [(set (match_operand:TF 0 "register_operand" "=f,f")
3477 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3478 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3482 [(set_attr "op_type" "RRE,RXE")
3483 (set_attr "type" "fsimptf, floadtf")])
3487 ;; ARITHMETIC OPERATIONS
3489 ; arithmetic operations set the ConditionCode,
3490 ; because of unpredictable Bits in Register for Halfword and Byte
3491 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3494 ;;- Add instructions.
3498 ; addti3 instruction pattern(s).
3501 (define_insn_and_split "addti3"
3502 [(set (match_operand:TI 0 "register_operand" "=&d")
3503 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3504 (match_operand:TI 2 "general_operand" "do") ) )
3505 (clobber (reg:CC CC_REGNUM))]
3508 "&& reload_completed"
3510 [(set (reg:CCL1 CC_REGNUM)
3511 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3513 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3515 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3516 (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0))))
3517 (clobber (reg:CC CC_REGNUM))])]
3518 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3519 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3520 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3521 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3522 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3523 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3526 ; adddi3 instruction pattern(s).
3529 (define_expand "adddi3"
3531 [(set (match_operand:DI 0 "register_operand" "")
3532 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3533 (match_operand:DI 2 "general_operand" "")))
3534 (clobber (reg:CC CC_REGNUM))])]
3538 (define_insn "*adddi3_sign"
3539 [(set (match_operand:DI 0 "register_operand" "=d,d")
3540 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3541 (match_operand:DI 1 "register_operand" "0,0")))
3542 (clobber (reg:CC CC_REGNUM))]
3547 [(set_attr "op_type" "RRE,RXY")])
3549 (define_insn "*adddi3_zero_cc"
3550 [(set (reg CC_REGNUM)
3551 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3552 (match_operand:DI 1 "register_operand" "0,0"))
3554 (set (match_operand:DI 0 "register_operand" "=d,d")
3555 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3556 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3560 [(set_attr "op_type" "RRE,RXY")])
3562 (define_insn "*adddi3_zero_cconly"
3563 [(set (reg CC_REGNUM)
3564 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3565 (match_operand:DI 1 "register_operand" "0,0"))
3567 (clobber (match_scratch:DI 0 "=d,d"))]
3568 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3572 [(set_attr "op_type" "RRE,RXY")])
3574 (define_insn "*adddi3_zero"
3575 [(set (match_operand:DI 0 "register_operand" "=d,d")
3576 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3577 (match_operand:DI 1 "register_operand" "0,0")))
3578 (clobber (reg:CC CC_REGNUM))]
3583 [(set_attr "op_type" "RRE,RXY")])
3585 (define_insn_and_split "*adddi3_31z"
3586 [(set (match_operand:DI 0 "register_operand" "=&d")
3587 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3588 (match_operand:DI 2 "general_operand" "do") ) )
3589 (clobber (reg:CC CC_REGNUM))]
3590 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3592 "&& reload_completed"
3594 [(set (reg:CCL1 CC_REGNUM)
3595 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3597 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3599 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3600 (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0))))
3601 (clobber (reg:CC CC_REGNUM))])]
3602 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3603 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3604 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3605 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3606 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3607 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3609 (define_insn_and_split "*adddi3_31"
3610 [(set (match_operand:DI 0 "register_operand" "=&d")
3611 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3612 (match_operand:DI 2 "general_operand" "do") ) )
3613 (clobber (reg:CC CC_REGNUM))]
3616 "&& reload_completed"
3618 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3619 (clobber (reg:CC CC_REGNUM))])
3621 [(set (reg:CCL1 CC_REGNUM)
3622 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3624 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3626 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
3628 (label_ref (match_dup 9))))
3630 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3631 (clobber (reg:CC CC_REGNUM))])
3633 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3634 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3635 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3636 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3637 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3638 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3639 operands[9] = gen_label_rtx ();")
3642 ; addsi3 instruction pattern(s).
3645 (define_expand "addsi3"
3647 [(set (match_operand:SI 0 "register_operand" "")
3648 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
3649 (match_operand:SI 2 "general_operand" "")))
3650 (clobber (reg:CC CC_REGNUM))])]
3654 (define_insn "*addsi3_sign"
3655 [(set (match_operand:SI 0 "register_operand" "=d,d")
3656 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3657 (match_operand:SI 1 "register_operand" "0,0")))
3658 (clobber (reg:CC CC_REGNUM))]
3663 [(set_attr "op_type" "RX,RXY")])
3666 ; add(di|si)3 instruction pattern(s).
3669 ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag
3670 (define_insn "*add<mode>3"
3671 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d")
3672 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
3673 (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) )
3674 (clobber (reg:CC CC_REGNUM))]
3683 [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY")])
3685 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3686 (define_insn "*add<mode>3_carry1_cc"
3687 [(set (reg CC_REGNUM)
3688 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3689 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3691 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3692 (plus:GPR (match_dup 1) (match_dup 2)))]
3693 "s390_match_ccmode (insn, CCL1mode)"
3700 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3702 ; alr, al, aly, algr, alg
3703 (define_insn "*add<mode>3_carry1_cconly"
3704 [(set (reg CC_REGNUM)
3705 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3706 (match_operand:GPR 2 "general_operand" "d,R,T"))
3708 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3709 "s390_match_ccmode (insn, CCL1mode)"
3714 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3716 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3717 (define_insn "*add<mode>3_carry2_cc"
3718 [(set (reg CC_REGNUM)
3719 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3720 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3722 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3723 (plus:GPR (match_dup 1) (match_dup 2)))]
3724 "s390_match_ccmode (insn, CCL1mode)"
3731 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3733 ; alr, al, aly, algr, alg
3734 (define_insn "*add<mode>3_carry2_cconly"
3735 [(set (reg CC_REGNUM)
3736 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3737 (match_operand:GPR 2 "general_operand" "d,R,T"))
3739 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3740 "s390_match_ccmode (insn, CCL1mode)"
3745 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3747 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg
3748 (define_insn "*add<mode>3_cc"
3749 [(set (reg CC_REGNUM)
3750 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0")
3751 (match_operand:GPR 2 "general_operand" "d,Op,On,R,T"))
3753 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3754 (plus:GPR (match_dup 1) (match_dup 2)))]
3755 "s390_match_ccmode (insn, CCLmode)"
3762 [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")])
3764 ; alr, al, aly, algr, alg
3765 (define_insn "*add<mode>3_cconly"
3766 [(set (reg CC_REGNUM)
3767 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3768 (match_operand:GPR 2 "general_operand" "d,R,T"))
3770 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3771 "s390_match_ccmode (insn, CCLmode)"
3776 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3778 ; alr, al, aly, algr, alg
3779 (define_insn "*add<mode>3_cconly2"
3780 [(set (reg CC_REGNUM)
3781 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
3782 (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
3783 (clobber (match_scratch:GPR 0 "=d,d,d"))]
3784 "s390_match_ccmode(insn, CCLmode)"
3789 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
3791 ; ahi, afi, aghi, agfi
3792 (define_insn "*add<mode>3_imm_cc"
3793 [(set (reg CC_REGNUM)
3794 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
3795 (match_operand:GPR 2 "const_int_operand" "K,Os"))
3797 (set (match_operand:GPR 0 "register_operand" "=d,d")
3798 (plus:GPR (match_dup 1) (match_dup 2)))]
3799 "s390_match_ccmode (insn, CCAmode)
3800 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
3801 || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))
3802 && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
3806 [(set_attr "op_type" "RI,RIL")])
3809 ; add(df|sf)3 instruction pattern(s).
3812 (define_expand "add<mode>3"
3814 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3815 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3816 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
3817 (clobber (reg:CC CC_REGNUM))])]
3821 ; axbr, adbr, aebr, axb, adb, aeb
3822 (define_insn "*add<mode>3"
3823 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3824 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3825 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
3826 (clobber (reg:CC CC_REGNUM))]
3827 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3831 [(set_attr "op_type" "RRE,RXE")
3832 (set_attr "type" "fsimp<mode>")])
3834 ; axbr, adbr, aebr, axb, adb, aeb
3835 (define_insn "*add<mode>3_cc"
3836 [(set (reg CC_REGNUM)
3837 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3838 (match_operand:FPR 2 "general_operand" "f,<Rf>"))
3839 (match_operand:FPR 3 "const0_operand" "")))
3840 (set (match_operand:FPR 0 "register_operand" "=f,f")
3841 (plus:FPR (match_dup 1) (match_dup 2)))]
3842 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3846 [(set_attr "op_type" "RRE,RXE")
3847 (set_attr "type" "fsimp<mode>")])
3849 ; axbr, adbr, aebr, axb, adb, aeb
3850 (define_insn "*add<mode>3_cconly"
3851 [(set (reg CC_REGNUM)
3852 (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3853 (match_operand:FPR 2 "general_operand" "f,<Rf>"))
3854 (match_operand:FPR 3 "const0_operand" "")))
3855 (clobber (match_scratch:FPR 0 "=f,f"))]
3856 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3860 [(set_attr "op_type" "RRE,RXE")
3861 (set_attr "type" "fsimp<mode>")])
3863 ; axr, adr, aer, ax, ad, ae
3864 (define_insn "*add<mode>3_ibm"
3865 [(set (match_operand:FPR 0 "register_operand" "=f,f")
3866 (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
3867 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
3868 (clobber (reg:CC CC_REGNUM))]
3869 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3873 [(set_attr "op_type" "<RRe>,<RXe>")
3874 (set_attr "type" "fsimp<mode>")])
3878 ;;- Subtract instructions.
3882 ; subti3 instruction pattern(s).
3885 (define_insn_and_split "subti3"
3886 [(set (match_operand:TI 0 "register_operand" "=&d")
3887 (minus:TI (match_operand:TI 1 "register_operand" "0")
3888 (match_operand:TI 2 "general_operand" "do") ) )
3889 (clobber (reg:CC CC_REGNUM))]
3892 "&& reload_completed"
3894 [(set (reg:CCL2 CC_REGNUM)
3895 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3897 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3899 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3900 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0))))
3901 (clobber (reg:CC CC_REGNUM))])]
3902 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3903 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3904 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3905 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3906 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3907 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3910 ; subdi3 instruction pattern(s).
3913 (define_expand "subdi3"
3915 [(set (match_operand:DI 0 "register_operand" "")
3916 (minus:DI (match_operand:DI 1 "register_operand" "")
3917 (match_operand:DI 2 "general_operand" "")))
3918 (clobber (reg:CC CC_REGNUM))])]
3922 (define_insn "*subdi3_sign"
3923 [(set (match_operand:DI 0 "register_operand" "=d,d")
3924 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3925 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3926 (clobber (reg:CC CC_REGNUM))]
3931 [(set_attr "op_type" "RRE,RXY")])
3933 (define_insn "*subdi3_zero_cc"
3934 [(set (reg CC_REGNUM)
3935 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3936 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3938 (set (match_operand:DI 0 "register_operand" "=d,d")
3939 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3940 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3944 [(set_attr "op_type" "RRE,RXY")])
3946 (define_insn "*subdi3_zero_cconly"
3947 [(set (reg CC_REGNUM)
3948 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3949 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3951 (clobber (match_scratch:DI 0 "=d,d"))]
3952 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3956 [(set_attr "op_type" "RRE,RXY")])
3958 (define_insn "*subdi3_zero"
3959 [(set (match_operand:DI 0 "register_operand" "=d,d")
3960 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3961 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3962 (clobber (reg:CC CC_REGNUM))]
3967 [(set_attr "op_type" "RRE,RXY")])
3969 (define_insn_and_split "*subdi3_31z"
3970 [(set (match_operand:DI 0 "register_operand" "=&d")
3971 (minus:DI (match_operand:DI 1 "register_operand" "0")
3972 (match_operand:DI 2 "general_operand" "do") ) )
3973 (clobber (reg:CC CC_REGNUM))]
3974 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3976 "&& reload_completed"
3978 [(set (reg:CCL2 CC_REGNUM)
3979 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3981 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3983 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3984 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0))))
3985 (clobber (reg:CC CC_REGNUM))])]
3986 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3987 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3988 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3989 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3990 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3991 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3993 (define_insn_and_split "*subdi3_31"
3994 [(set (match_operand:DI 0 "register_operand" "=&d")
3995 (minus:DI (match_operand:DI 1 "register_operand" "0")
3996 (match_operand:DI 2 "general_operand" "do") ) )
3997 (clobber (reg:CC CC_REGNUM))]
4000 "&& reload_completed"
4002 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
4003 (clobber (reg:CC CC_REGNUM))])
4005 [(set (reg:CCL2 CC_REGNUM)
4006 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4008 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4010 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
4012 (label_ref (match_dup 9))))
4014 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4015 (clobber (reg:CC CC_REGNUM))])
4017 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4018 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4019 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4020 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4021 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4022 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4023 operands[9] = gen_label_rtx ();")
4026 ; subsi3 instruction pattern(s).
4029 (define_expand "subsi3"
4031 [(set (match_operand:SI 0 "register_operand" "")
4032 (minus:SI (match_operand:SI 1 "register_operand" "")
4033 (match_operand:SI 2 "general_operand" "")))
4034 (clobber (reg:CC CC_REGNUM))])]
4038 (define_insn "*subsi3_sign"
4039 [(set (match_operand:SI 0 "register_operand" "=d,d")
4040 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4041 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4042 (clobber (reg:CC CC_REGNUM))]
4047 [(set_attr "op_type" "RX,RXY")])
4050 ; sub(di|si)3 instruction pattern(s).
4053 ; sr, s, sy, sgr, sg
4054 (define_insn "*sub<mode>3"
4055 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
4056 (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4057 (match_operand:GPR 2 "general_operand" "d,R,T") ) )
4058 (clobber (reg:CC CC_REGNUM))]
4064 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4066 ; slr, sl, sly, slgr, slg
4067 (define_insn "*sub<mode>3_borrow_cc"
4068 [(set (reg CC_REGNUM)
4069 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4070 (match_operand:GPR 2 "general_operand" "d,R,T"))
4072 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4073 (minus:GPR (match_dup 1) (match_dup 2)))]
4074 "s390_match_ccmode (insn, CCL2mode)"
4079 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4081 ; slr, sl, sly, slgr, slg
4082 (define_insn "*sub<mode>3_borrow_cconly"
4083 [(set (reg CC_REGNUM)
4084 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4085 (match_operand:GPR 2 "general_operand" "d,R,T"))
4087 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4088 "s390_match_ccmode (insn, CCL2mode)"
4093 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4095 ; slr, sl, sly, slgr, slg
4096 (define_insn "*sub<mode>3_cc"
4097 [(set (reg CC_REGNUM)
4098 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4099 (match_operand:GPR 2 "general_operand" "d,R,T"))
4101 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4102 (minus:GPR (match_dup 1) (match_dup 2)))]
4103 "s390_match_ccmode (insn, CCLmode)"
4108 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4110 ; slr, sl, sly, slgr, slg
4111 (define_insn "*sub<mode>3_cc2"
4112 [(set (reg CC_REGNUM)
4113 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4114 (match_operand:GPR 2 "general_operand" "d,R,T")))
4115 (set (match_operand:GPR 0 "register_operand" "=d,d,d")
4116 (minus:GPR (match_dup 1) (match_dup 2)))]
4117 "s390_match_ccmode (insn, CCL3mode)"
4122 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4124 ; slr, sl, sly, slgr, slg
4125 (define_insn "*sub<mode>3_cconly"
4126 [(set (reg CC_REGNUM)
4127 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
4128 (match_operand:GPR 2 "general_operand" "d,R,T"))
4130 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4131 "s390_match_ccmode (insn, CCLmode)"
4136 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4138 ; slr, sl, sly, slgr, slg
4139 (define_insn "*sub<mode>3_cconly2"
4140 [(set (reg CC_REGNUM)
4141 (compare (match_operand:GPR 1 "register_operand" "0,0,0")
4142 (match_operand:GPR 2 "general_operand" "d,R,T")))
4143 (clobber (match_scratch:GPR 0 "=d,d,d"))]
4144 "s390_match_ccmode (insn, CCL3mode)"
4149 [(set_attr "op_type" "RR<E>,RX<Y>,RXY")])
4152 ; sub(df|sf)3 instruction pattern(s).
4155 (define_expand "sub<mode>3"
4157 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4158 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4159 (match_operand:FPR 2 "general_operand" "f,R")))
4160 (clobber (reg:CC CC_REGNUM))])]
4164 ; sxbr, sdbr, sebr, sxb, sdb, seb
4165 (define_insn "*sub<mode>3"
4166 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4167 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4168 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
4169 (clobber (reg:CC CC_REGNUM))]
4170 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4174 [(set_attr "op_type" "RRE,RXE")
4175 (set_attr "type" "fsimp<mode>")])
4177 ; sxbr, sdbr, sebr, sxb, sdb, seb
4178 (define_insn "*sub<mode>3_cc"
4179 [(set (reg CC_REGNUM)
4180 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4181 (match_operand:FPR 2 "general_operand" "f,<Rf>"))
4182 (match_operand:FPR 3 "const0_operand" "")))
4183 (set (match_operand:FPR 0 "register_operand" "=f,f")
4184 (minus:FPR (match_dup 1) (match_dup 2)))]
4185 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4189 [(set_attr "op_type" "RRE,RXE")
4190 (set_attr "type" "fsimp<mode>")])
4192 ; sxbr, sdbr, sebr, sxb, sdb, seb
4193 (define_insn "*sub<mode>3_cconly"
4194 [(set (reg CC_REGNUM)
4195 (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
4196 (match_operand:FPR 2 "general_operand" "f,<Rf>"))
4197 (match_operand:FPR 3 "const0_operand" "")))
4198 (clobber (match_scratch:FPR 0 "=f,f"))]
4199 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4203 [(set_attr "op_type" "RRE,RXE")
4204 (set_attr "type" "fsimp<mode>")])
4206 ; sxr, sdr, ser, sx, sd, se
4207 (define_insn "*sub<mode>3_ibm"
4208 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4209 (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
4210 (match_operand:FPR 2 "general_operand" "f,<Rf>")))
4211 (clobber (reg:CC CC_REGNUM))]
4212 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4216 [(set_attr "op_type" "<RRe>,<RXe>")
4217 (set_attr "type" "fsimp<mode>")])
4221 ;;- Conditional add/subtract instructions.
4225 ; add(di|si)cc instruction pattern(s).
4228 ; alcr, alc, alcgr, alcg
4229 (define_insn "*add<mode>3_alc_cc"
4230 [(set (reg CC_REGNUM)
4232 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4233 (match_operand:GPR 2 "general_operand" "d,m"))
4234 (match_operand:GPR 3 "s390_alc_comparison" ""))
4236 (set (match_operand:GPR 0 "register_operand" "=d,d")
4237 (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4238 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4242 [(set_attr "op_type" "RRE,RXY")])
4244 ; alcr, alc, alcgr, alcg
4245 (define_insn "*add<mode>3_alc"
4246 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4247 (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0")
4248 (match_operand:GPR 2 "general_operand" "d,m"))
4249 (match_operand:GPR 3 "s390_alc_comparison" "")))
4250 (clobber (reg:CC CC_REGNUM))]
4255 [(set_attr "op_type" "RRE,RXY")])
4257 ; slbr, slb, slbgr, slbg
4258 (define_insn "*sub<mode>3_slb_cc"
4259 [(set (reg CC_REGNUM)
4261 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4262 (match_operand:GPR 2 "general_operand" "d,m"))
4263 (match_operand:GPR 3 "s390_slb_comparison" ""))
4265 (set (match_operand:GPR 0 "register_operand" "=d,d")
4266 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
4267 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4271 [(set_attr "op_type" "RRE,RXY")])
4273 ; slbr, slb, slbgr, slbg
4274 (define_insn "*sub<mode>3_slb"
4275 [(set (match_operand:GPR 0 "register_operand" "=d,d")
4276 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
4277 (match_operand:GPR 2 "general_operand" "d,m"))
4278 (match_operand:GPR 3 "s390_slb_comparison" "")))
4279 (clobber (reg:CC CC_REGNUM))]
4284 [(set_attr "op_type" "RRE,RXY")])
4286 (define_expand "add<mode>cc"
4287 [(match_operand:GPR 0 "register_operand" "")
4288 (match_operand 1 "comparison_operator" "")
4289 (match_operand:GPR 2 "register_operand" "")
4290 (match_operand:GPR 3 "const_int_operand" "")]
4292 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4293 s390_compare_op0, s390_compare_op1,
4294 operands[0], operands[2],
4295 operands[3])) FAIL; DONE;")
4298 ; scond instruction pattern(s).
4301 (define_insn_and_split "*scond<mode>"
4302 [(set (match_operand:GPR 0 "register_operand" "=&d")
4303 (match_operand:GPR 1 "s390_alc_comparison" ""))
4304 (clobber (reg:CC CC_REGNUM))]
4307 "&& reload_completed"
4308 [(set (match_dup 0) (const_int 0))
4310 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0))
4312 (clobber (reg:CC CC_REGNUM))])]
4315 (define_insn_and_split "*scond<mode>_neg"
4316 [(set (match_operand:GPR 0 "register_operand" "=&d")
4317 (match_operand:GPR 1 "s390_slb_comparison" ""))
4318 (clobber (reg:CC CC_REGNUM))]
4321 "&& reload_completed"
4322 [(set (match_dup 0) (const_int 0))
4324 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0))
4326 (clobber (reg:CC CC_REGNUM))])
4328 [(set (match_dup 0) (neg:GPR (match_dup 0)))
4329 (clobber (reg:CC CC_REGNUM))])]
4333 (define_expand "s<code>"
4334 [(set (match_operand:SI 0 "register_operand" "")
4335 (SCOND (match_dup 0)
4338 "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1,
4339 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4341 (define_expand "seq"
4343 [(set (match_operand:SI 0 "register_operand" "=d")
4345 (clobber (reg:CC CC_REGNUM))])
4347 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))
4348 (clobber (reg:CC CC_REGNUM))])]
4351 if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode)
4353 operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1);
4354 PUT_MODE (operands[1], SImode);
4357 (define_insn_and_split "*sne"
4358 [(set (match_operand:SI 0 "register_operand" "=d")
4359 (ne:SI (match_operand:CCZ1 1 "register_operand" "0")
4361 (clobber (reg:CC CC_REGNUM))]
4366 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28)))
4367 (clobber (reg:CC CC_REGNUM))])])
4371 ;;- Multiply instructions.
4375 ; muldi3 instruction pattern(s).
4378 (define_insn "*muldi3_sign"
4379 [(set (match_operand:DI 0 "register_operand" "=d,d")
4380 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4381 (match_operand:DI 1 "register_operand" "0,0")))]
4386 [(set_attr "op_type" "RRE,RXY")
4387 (set_attr "type" "imuldi")])
4389 (define_insn "muldi3"
4390 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4391 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4392 (match_operand:DI 2 "general_operand" "d,K,m")))]
4398 [(set_attr "op_type" "RRE,RI,RXY")
4399 (set_attr "type" "imuldi")])
4402 ; mulsi3 instruction pattern(s).
4405 (define_insn "*mulsi3_sign"
4406 [(set (match_operand:SI 0 "register_operand" "=d")
4407 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4408 (match_operand:SI 1 "register_operand" "0")))]
4411 [(set_attr "op_type" "RX")
4412 (set_attr "type" "imulhi")])
4414 (define_insn "mulsi3"
4415 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4416 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4417 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4424 [(set_attr "op_type" "RRE,RI,RX,RXY")
4425 (set_attr "type" "imulsi,imulhi,imulsi,imulsi")])
4428 ; mulsidi3 instruction pattern(s).
4431 (define_insn "mulsidi3"
4432 [(set (match_operand:DI 0 "register_operand" "=d,d")
4433 (mult:DI (sign_extend:DI
4434 (match_operand:SI 1 "register_operand" "%0,0"))
4436 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4441 [(set_attr "op_type" "RR,RX")
4442 (set_attr "type" "imulsi")])
4445 ; umulsidi3 instruction pattern(s).
4448 (define_insn "umulsidi3"
4449 [(set (match_operand:DI 0 "register_operand" "=d,d")
4450 (mult:DI (zero_extend:DI
4451 (match_operand:SI 1 "register_operand" "%0,0"))
4453 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4454 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4458 [(set_attr "op_type" "RRE,RXY")
4459 (set_attr "type" "imulsi")])
4462 ; mul(df|sf)3 instruction pattern(s).
4465 (define_expand "mul<mode>3"
4466 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4467 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4468 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4472 ; mxbr mdbr, meebr, mxb, mxb, meeb
4473 (define_insn "*mul<mode>3"
4474 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4475 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4476 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4477 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4481 [(set_attr "op_type" "RRE,RXE")
4482 (set_attr "type" "fmul<mode>")])
4484 ; mxr, mdr, mer, mx, md, me
4485 (define_insn "*mul<mode>3_ibm"
4486 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4487 (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
4488 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4489 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4493 [(set_attr "op_type" "<RRe>,<RXe>")
4494 (set_attr "type" "fmul<mode>")])
4496 ; maxbr, madbr, maebr, maxb, madb, maeb
4497 (define_insn "*fmadd<mode>"
4498 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4499 (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
4500 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4501 (match_operand:DSF 3 "register_operand" "0,0")))]
4502 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4506 [(set_attr "op_type" "RRE,RXE")
4507 (set_attr "type" "fmul<mode>")])
4509 ; msxbr, msdbr, msebr, msxb, msdb, mseb
4510 (define_insn "*fmsub<mode>"
4511 [(set (match_operand:DSF 0 "register_operand" "=f,f")
4512 (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
4513 (match_operand:DSF 2 "nonimmediate_operand" "f,R"))
4514 (match_operand:DSF 3 "register_operand" "0,0")))]
4515 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4519 [(set_attr "op_type" "RRE,RXE")
4520 (set_attr "type" "fmul<mode>")])
4523 ;;- Divide and modulo instructions.
4527 ; divmoddi4 instruction pattern(s).
4530 (define_expand "divmoddi4"
4531 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4532 (div:DI (match_operand:DI 1 "register_operand" "")
4533 (match_operand:DI 2 "general_operand" "")))
4534 (set (match_operand:DI 3 "general_operand" "")
4535 (mod:DI (match_dup 1) (match_dup 2)))])
4536 (clobber (match_dup 4))]
4539 rtx insn, div_equal, mod_equal;
4541 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4542 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4544 operands[4] = gen_reg_rtx(TImode);
4545 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4547 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4549 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4551 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4553 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4558 (define_insn "divmodtidi3"
4559 [(set (match_operand:TI 0 "register_operand" "=d,d")
4563 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4564 (match_operand:DI 2 "general_operand" "d,m")))
4566 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4571 [(set_attr "op_type" "RRE,RXY")
4572 (set_attr "type" "idiv")])
4574 (define_insn "divmodtisi3"
4575 [(set (match_operand:TI 0 "register_operand" "=d,d")
4579 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4581 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4584 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4589 [(set_attr "op_type" "RRE,RXY")
4590 (set_attr "type" "idiv")])
4593 ; udivmoddi4 instruction pattern(s).
4596 (define_expand "udivmoddi4"
4597 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4598 (udiv:DI (match_operand:DI 1 "general_operand" "")
4599 (match_operand:DI 2 "nonimmediate_operand" "")))
4600 (set (match_operand:DI 3 "general_operand" "")
4601 (umod:DI (match_dup 1) (match_dup 2)))])
4602 (clobber (match_dup 4))]
4605 rtx insn, div_equal, mod_equal, equal;
4607 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4608 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4609 equal = gen_rtx_IOR (TImode,
4610 gen_rtx_ASHIFT (TImode,
4611 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4613 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4615 operands[4] = gen_reg_rtx(TImode);
4616 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4617 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4618 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4619 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4621 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4623 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4625 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4627 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4629 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4634 (define_insn "udivmodtidi3"
4635 [(set (match_operand:TI 0 "register_operand" "=d,d")
4640 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4642 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4646 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4651 [(set_attr "op_type" "RRE,RXY")
4652 (set_attr "type" "idiv")])
4655 ; divmodsi4 instruction pattern(s).
4658 (define_expand "divmodsi4"
4659 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4660 (div:SI (match_operand:SI 1 "general_operand" "")
4661 (match_operand:SI 2 "nonimmediate_operand" "")))
4662 (set (match_operand:SI 3 "general_operand" "")
4663 (mod:SI (match_dup 1) (match_dup 2)))])
4664 (clobber (match_dup 4))]
4667 rtx insn, div_equal, mod_equal, equal;
4669 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4670 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4671 equal = gen_rtx_IOR (DImode,
4672 gen_rtx_ASHIFT (DImode,
4673 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4675 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4677 operands[4] = gen_reg_rtx(DImode);
4678 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4679 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4681 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4683 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4685 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4687 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4689 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4694 (define_insn "divmoddisi3"
4695 [(set (match_operand:DI 0 "register_operand" "=d,d")
4700 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4702 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4706 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4711 [(set_attr "op_type" "RR,RX")
4712 (set_attr "type" "idiv")])
4715 ; udivsi3 and umodsi3 instruction pattern(s).
4718 (define_expand "udivmodsi4"
4719 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4720 (udiv:SI (match_operand:SI 1 "general_operand" "")
4721 (match_operand:SI 2 "nonimmediate_operand" "")))
4722 (set (match_operand:SI 3 "general_operand" "")
4723 (umod:SI (match_dup 1) (match_dup 2)))])
4724 (clobber (match_dup 4))]
4725 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4727 rtx insn, div_equal, mod_equal, equal;
4729 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4730 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4731 equal = gen_rtx_IOR (DImode,
4732 gen_rtx_ASHIFT (DImode,
4733 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4735 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4737 operands[4] = gen_reg_rtx(DImode);
4738 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4739 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4740 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4741 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4743 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4745 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4747 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4749 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4751 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4756 (define_insn "udivmoddisi3"
4757 [(set (match_operand:DI 0 "register_operand" "=d,d")
4762 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4764 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4768 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4769 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4773 [(set_attr "op_type" "RRE,RXY")
4774 (set_attr "type" "idiv")])
4776 (define_expand "udivsi3"
4777 [(set (match_operand:SI 0 "register_operand" "=d")
4778 (udiv:SI (match_operand:SI 1 "general_operand" "")
4779 (match_operand:SI 2 "general_operand" "")))
4780 (clobber (match_dup 3))]
4781 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4783 rtx insn, udiv_equal, umod_equal, equal;
4785 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4786 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4787 equal = gen_rtx_IOR (DImode,
4788 gen_rtx_ASHIFT (DImode,
4789 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4791 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4793 operands[3] = gen_reg_rtx (DImode);
4795 if (CONSTANT_P (operands[2]))
4797 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4799 rtx label1 = gen_label_rtx ();
4801 operands[1] = make_safe_from (operands[1], operands[0]);
4802 emit_move_insn (operands[0], const0_rtx);
4803 emit_insn (gen_cmpsi (operands[1], operands[2]));
4804 emit_jump_insn (gen_bltu (label1));
4805 emit_move_insn (operands[0], const1_rtx);
4806 emit_label (label1);
4810 operands[2] = force_reg (SImode, operands[2]);
4811 operands[2] = make_safe_from (operands[2], operands[0]);
4813 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4814 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4817 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4819 insn = emit_move_insn (operands[0],
4820 gen_lowpart (SImode, operands[3]));
4822 gen_rtx_EXPR_LIST (REG_EQUAL,
4823 udiv_equal, REG_NOTES (insn));
4828 rtx label1 = gen_label_rtx ();
4829 rtx label2 = gen_label_rtx ();
4830 rtx label3 = gen_label_rtx ();
4832 operands[1] = force_reg (SImode, operands[1]);
4833 operands[1] = make_safe_from (operands[1], operands[0]);
4834 operands[2] = force_reg (SImode, operands[2]);
4835 operands[2] = make_safe_from (operands[2], operands[0]);
4837 emit_move_insn (operands[0], const0_rtx);
4838 emit_insn (gen_cmpsi (operands[2], operands[1]));
4839 emit_jump_insn (gen_bgtu (label3));
4840 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4841 emit_jump_insn (gen_blt (label2));
4842 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4843 emit_jump_insn (gen_beq (label1));
4844 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4845 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4848 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4850 insn = emit_move_insn (operands[0],
4851 gen_lowpart (SImode, operands[3]));
4853 gen_rtx_EXPR_LIST (REG_EQUAL,
4854 udiv_equal, REG_NOTES (insn));
4856 emit_label (label1);
4857 emit_move_insn (operands[0], operands[1]);
4859 emit_label (label2);
4860 emit_move_insn (operands[0], const1_rtx);
4861 emit_label (label3);
4863 emit_move_insn (operands[0], operands[0]);
4867 (define_expand "umodsi3"
4868 [(set (match_operand:SI 0 "register_operand" "=d")
4869 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
4870 (match_operand:SI 2 "nonimmediate_operand" "")))
4871 (clobber (match_dup 3))]
4872 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4874 rtx insn, udiv_equal, umod_equal, equal;
4876 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4877 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4878 equal = gen_rtx_IOR (DImode,
4879 gen_rtx_ASHIFT (DImode,
4880 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4882 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4884 operands[3] = gen_reg_rtx (DImode);
4886 if (CONSTANT_P (operands[2]))
4888 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
4890 rtx label1 = gen_label_rtx ();
4892 operands[1] = make_safe_from (operands[1], operands[0]);
4893 emit_move_insn (operands[0], operands[1]);
4894 emit_insn (gen_cmpsi (operands[0], operands[2]));
4895 emit_jump_insn (gen_bltu (label1));
4896 emit_insn (gen_abssi2 (operands[0], operands[2]));
4897 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
4898 emit_label (label1);
4902 operands[2] = force_reg (SImode, operands[2]);
4903 operands[2] = make_safe_from (operands[2], operands[0]);
4905 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4906 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4909 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4911 insn = emit_move_insn (operands[0],
4912 gen_highpart (SImode, operands[3]));
4914 gen_rtx_EXPR_LIST (REG_EQUAL,
4915 umod_equal, REG_NOTES (insn));
4920 rtx label1 = gen_label_rtx ();
4921 rtx label2 = gen_label_rtx ();
4922 rtx label3 = gen_label_rtx ();
4924 operands[1] = force_reg (SImode, operands[1]);
4925 operands[1] = make_safe_from (operands[1], operands[0]);
4926 operands[2] = force_reg (SImode, operands[2]);
4927 operands[2] = make_safe_from (operands[2], operands[0]);
4929 emit_move_insn(operands[0], operands[1]);
4930 emit_insn (gen_cmpsi (operands[2], operands[1]));
4931 emit_jump_insn (gen_bgtu (label3));
4932 emit_insn (gen_cmpsi (operands[2], const0_rtx));
4933 emit_jump_insn (gen_blt (label2));
4934 emit_insn (gen_cmpsi (operands[2], const1_rtx));
4935 emit_jump_insn (gen_beq (label1));
4936 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4937 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4940 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4942 insn = emit_move_insn (operands[0],
4943 gen_highpart (SImode, operands[3]));
4945 gen_rtx_EXPR_LIST (REG_EQUAL,
4946 umod_equal, REG_NOTES (insn));
4948 emit_label (label1);
4949 emit_move_insn (operands[0], const0_rtx);
4951 emit_label (label2);
4952 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
4953 emit_label (label3);
4959 ; div(df|sf)3 instruction pattern(s).
4962 (define_expand "div<mode>3"
4963 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4964 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4965 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4969 ; dxbr, ddbr, debr, dxb, ddb, deb
4970 (define_insn "*div<mode>3"
4971 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4972 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4973 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4974 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4978 [(set_attr "op_type" "RRE,RXE")
4979 (set_attr "type" "fdiv<mode>")])
4981 ; dxr, ddr, der, dx, dd, de
4982 (define_insn "*div<mode>3_ibm"
4983 [(set (match_operand:FPR 0 "register_operand" "=f,f")
4984 (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
4985 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
4986 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4990 [(set_attr "op_type" "<RRe>,<RXe>")
4991 (set_attr "type" "fdiv<mode>")])
4995 ;;- And instructions.
4998 (define_expand "and<mode>3"
4999 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5000 (and:INT (match_operand:INT 1 "nonimmediate_operand" "")
5001 (match_operand:INT 2 "general_operand" "")))
5002 (clobber (reg:CC CC_REGNUM))]
5004 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;")
5007 ; anddi3 instruction pattern(s).
5010 (define_insn "*anddi3_cc"
5011 [(set (reg CC_REGNUM)
5012 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5013 (match_operand:DI 2 "general_operand" "d,m"))
5015 (set (match_operand:DI 0 "register_operand" "=d,d")
5016 (and:DI (match_dup 1) (match_dup 2)))]
5017 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5021 [(set_attr "op_type" "RRE,RXY")])
5023 (define_insn "*anddi3_cconly"
5024 [(set (reg CC_REGNUM)
5025 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5026 (match_operand:DI 2 "general_operand" "d,m"))
5028 (clobber (match_scratch:DI 0 "=d,d"))]
5029 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5030 /* Do not steal TM patterns. */
5031 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5035 [(set_attr "op_type" "RRE,RXY")])
5037 (define_insn "*anddi3_extimm"
5038 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
5039 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5040 "%d,o,0,0,0,0,0,0,0,0,0,0")
5041 (match_operand:DI 2 "general_operand"
5042 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q")))
5043 (clobber (reg:CC CC_REGNUM))]
5044 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5058 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5060 (define_insn "*anddi3"
5061 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5062 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5063 "%d,o,0,0,0,0,0,0,0,0")
5064 (match_operand:DI 2 "general_operand"
5065 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5066 (clobber (reg:CC CC_REGNUM))]
5067 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5079 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5082 [(set (match_operand:DI 0 "s_operand" "")
5083 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5084 (clobber (reg:CC CC_REGNUM))]
5087 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5088 (clobber (reg:CC CC_REGNUM))])]
5089 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5093 ; andsi3 instruction pattern(s).
5096 (define_insn "*andsi3_cc"
5097 [(set (reg CC_REGNUM)
5098 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5099 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5101 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5102 (and:SI (match_dup 1) (match_dup 2)))]
5103 "s390_match_ccmode(insn, CCTmode)"
5109 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5111 (define_insn "*andsi3_cconly"
5112 [(set (reg CC_REGNUM)
5113 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5114 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5116 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5117 "s390_match_ccmode(insn, CCTmode)
5118 /* Do not steal TM patterns. */
5119 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5125 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5127 (define_insn "*andsi3_zarch"
5128 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5129 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5130 "%d,o,0,0,0,0,0,0,0,0")
5131 (match_operand:SI 2 "general_operand"
5132 "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
5133 (clobber (reg:CC CC_REGNUM))]
5134 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5146 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")])
5148 (define_insn "*andsi3_esa"
5149 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5150 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5151 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5152 (clobber (reg:CC CC_REGNUM))]
5153 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5159 [(set_attr "op_type" "RR,RX,SI,SS")])
5162 [(set (match_operand:SI 0 "s_operand" "")
5163 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5164 (clobber (reg:CC CC_REGNUM))]
5167 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5168 (clobber (reg:CC CC_REGNUM))])]
5169 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5172 ; andhi3 instruction pattern(s).
5175 (define_insn "*andhi3_zarch"
5176 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5177 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5178 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5179 (clobber (reg:CC CC_REGNUM))]
5180 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5186 [(set_attr "op_type" "RR,RI,SI,SS")])
5188 (define_insn "*andhi3_esa"
5189 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5190 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5191 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5192 (clobber (reg:CC CC_REGNUM))]
5193 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5198 [(set_attr "op_type" "RR,SI,SS")])
5201 [(set (match_operand:HI 0 "s_operand" "")
5202 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5203 (clobber (reg:CC CC_REGNUM))]
5206 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5207 (clobber (reg:CC CC_REGNUM))])]
5208 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5211 ; andqi3 instruction pattern(s).
5214 (define_insn "*andqi3_zarch"
5215 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5216 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5217 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5218 (clobber (reg:CC CC_REGNUM))]
5219 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5226 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5228 (define_insn "*andqi3_esa"
5229 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5230 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5231 (match_operand:QI 2 "general_operand" "d,n,Q")))
5232 (clobber (reg:CC CC_REGNUM))]
5233 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5238 [(set_attr "op_type" "RR,SI,SS")])
5241 ; Block and (NC) patterns.
5245 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5246 (and:BLK (match_dup 0)
5247 (match_operand:BLK 1 "memory_operand" "Q")))
5248 (use (match_operand 2 "const_int_operand" "n"))
5249 (clobber (reg:CC CC_REGNUM))]
5250 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5251 "nc\t%O0(%2,%R0),%S1"
5252 [(set_attr "op_type" "SS")])
5255 [(set (match_operand 0 "memory_operand" "")
5257 (match_operand 1 "memory_operand" "")))
5258 (clobber (reg:CC CC_REGNUM))]
5260 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5261 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5263 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5265 (clobber (reg:CC CC_REGNUM))])]
5267 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5268 operands[0] = adjust_address (operands[0], BLKmode, 0);
5269 operands[1] = adjust_address (operands[1], BLKmode, 0);
5274 [(set (match_operand:BLK 0 "memory_operand" "")
5275 (and:BLK (match_dup 0)
5276 (match_operand:BLK 1 "memory_operand" "")))
5277 (use (match_operand 2 "const_int_operand" ""))
5278 (clobber (reg:CC CC_REGNUM))])
5280 [(set (match_operand:BLK 3 "memory_operand" "")
5281 (and:BLK (match_dup 3)
5282 (match_operand:BLK 4 "memory_operand" "")))
5283 (use (match_operand 5 "const_int_operand" ""))
5284 (clobber (reg:CC CC_REGNUM))])]
5285 "s390_offset_p (operands[0], operands[3], operands[2])
5286 && s390_offset_p (operands[1], operands[4], operands[2])
5287 && !s390_overlap_p (operands[0], operands[1],
5288 INTVAL (operands[2]) + INTVAL (operands[5]))
5289 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5291 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5293 (clobber (reg:CC CC_REGNUM))])]
5294 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5295 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5296 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5300 ;;- Bit set (inclusive or) instructions.
5303 (define_expand "ior<mode>3"
5304 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5305 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "")
5306 (match_operand:INT 2 "general_operand" "")))
5307 (clobber (reg:CC CC_REGNUM))]
5309 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;")
5312 ; iordi3 instruction pattern(s).
5315 (define_insn "*iordi3_cc"
5316 [(set (reg CC_REGNUM)
5317 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5318 (match_operand:DI 2 "general_operand" "d,m"))
5320 (set (match_operand:DI 0 "register_operand" "=d,d")
5321 (ior:DI (match_dup 1) (match_dup 2)))]
5322 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5326 [(set_attr "op_type" "RRE,RXY")])
5328 (define_insn "*iordi3_cconly"
5329 [(set (reg CC_REGNUM)
5330 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5331 (match_operand:DI 2 "general_operand" "d,m"))
5333 (clobber (match_scratch:DI 0 "=d,d"))]
5334 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5338 [(set_attr "op_type" "RRE,RXY")])
5340 (define_insn "*iordi3_extimm"
5341 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5342 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
5343 (match_operand:DI 2 "general_operand"
5344 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q")))
5345 (clobber (reg:CC CC_REGNUM))]
5346 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5358 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")])
5360 (define_insn "*iordi3"
5361 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5362 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5363 (match_operand:DI 2 "general_operand"
5364 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5365 (clobber (reg:CC CC_REGNUM))]
5366 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5376 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5379 [(set (match_operand:DI 0 "s_operand" "")
5380 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5381 (clobber (reg:CC CC_REGNUM))]
5384 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5385 (clobber (reg:CC CC_REGNUM))])]
5386 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5389 ; iorsi3 instruction pattern(s).
5392 (define_insn "*iorsi3_cc"
5393 [(set (reg CC_REGNUM)
5394 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5395 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5397 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5398 (ior:SI (match_dup 1) (match_dup 2)))]
5399 "s390_match_ccmode(insn, CCTmode)"
5405 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5407 (define_insn "*iorsi3_cconly"
5408 [(set (reg CC_REGNUM)
5409 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5410 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5412 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5413 "s390_match_ccmode(insn, CCTmode)"
5419 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5421 (define_insn "*iorsi3_zarch"
5422 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5423 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5424 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
5425 (clobber (reg:CC CC_REGNUM))]
5426 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5436 [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")])
5438 (define_insn "*iorsi3_esa"
5439 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5440 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5441 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5442 (clobber (reg:CC CC_REGNUM))]
5443 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5449 [(set_attr "op_type" "RR,RX,SI,SS")])
5452 [(set (match_operand:SI 0 "s_operand" "")
5453 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5454 (clobber (reg:CC CC_REGNUM))]
5457 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5458 (clobber (reg:CC CC_REGNUM))])]
5459 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5462 ; iorhi3 instruction pattern(s).
5465 (define_insn "*iorhi3_zarch"
5466 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5467 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5468 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5469 (clobber (reg:CC CC_REGNUM))]
5470 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5476 [(set_attr "op_type" "RR,RI,SI,SS")])
5478 (define_insn "*iorhi3_esa"
5479 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5480 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5481 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5482 (clobber (reg:CC CC_REGNUM))]
5483 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5488 [(set_attr "op_type" "RR,SI,SS")])
5491 [(set (match_operand:HI 0 "s_operand" "")
5492 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5493 (clobber (reg:CC CC_REGNUM))]
5496 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5497 (clobber (reg:CC CC_REGNUM))])]
5498 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5501 ; iorqi3 instruction pattern(s).
5504 (define_insn "*iorqi3_zarch"
5505 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5506 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5507 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5508 (clobber (reg:CC CC_REGNUM))]
5509 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5516 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5518 (define_insn "*iorqi3_esa"
5519 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5520 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5521 (match_operand:QI 2 "general_operand" "d,n,Q")))
5522 (clobber (reg:CC CC_REGNUM))]
5523 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5528 [(set_attr "op_type" "RR,SI,SS")])
5531 ; Block inclusive or (OC) patterns.
5535 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5536 (ior:BLK (match_dup 0)
5537 (match_operand:BLK 1 "memory_operand" "Q")))
5538 (use (match_operand 2 "const_int_operand" "n"))
5539 (clobber (reg:CC CC_REGNUM))]
5540 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5541 "oc\t%O0(%2,%R0),%S1"
5542 [(set_attr "op_type" "SS")])
5545 [(set (match_operand 0 "memory_operand" "")
5547 (match_operand 1 "memory_operand" "")))
5548 (clobber (reg:CC CC_REGNUM))]
5550 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5551 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5553 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5555 (clobber (reg:CC CC_REGNUM))])]
5557 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5558 operands[0] = adjust_address (operands[0], BLKmode, 0);
5559 operands[1] = adjust_address (operands[1], BLKmode, 0);
5564 [(set (match_operand:BLK 0 "memory_operand" "")
5565 (ior:BLK (match_dup 0)
5566 (match_operand:BLK 1 "memory_operand" "")))
5567 (use (match_operand 2 "const_int_operand" ""))
5568 (clobber (reg:CC CC_REGNUM))])
5570 [(set (match_operand:BLK 3 "memory_operand" "")
5571 (ior:BLK (match_dup 3)
5572 (match_operand:BLK 4 "memory_operand" "")))
5573 (use (match_operand 5 "const_int_operand" ""))
5574 (clobber (reg:CC CC_REGNUM))])]
5575 "s390_offset_p (operands[0], operands[3], operands[2])
5576 && s390_offset_p (operands[1], operands[4], operands[2])
5577 && !s390_overlap_p (operands[0], operands[1],
5578 INTVAL (operands[2]) + INTVAL (operands[5]))
5579 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5581 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5583 (clobber (reg:CC CC_REGNUM))])]
5584 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5585 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5586 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5590 ;;- Xor instructions.
5593 (define_expand "xor<mode>3"
5594 [(set (match_operand:INT 0 "nonimmediate_operand" "")
5595 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "")
5596 (match_operand:INT 2 "general_operand" "")))
5597 (clobber (reg:CC CC_REGNUM))]
5599 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;")
5602 ; xordi3 instruction pattern(s).
5605 (define_insn "*xordi3_cc"
5606 [(set (reg CC_REGNUM)
5607 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5608 (match_operand:DI 2 "general_operand" "d,m"))
5610 (set (match_operand:DI 0 "register_operand" "=d,d")
5611 (xor:DI (match_dup 1) (match_dup 2)))]
5612 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5616 [(set_attr "op_type" "RRE,RXY")])
5618 (define_insn "*xordi3_cconly"
5619 [(set (reg CC_REGNUM)
5620 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5621 (match_operand:DI 2 "general_operand" "d,m"))
5623 (clobber (match_scratch:DI 0 "=d,d"))]
5624 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5628 [(set_attr "op_type" "RRE,RXY")])
5630 (define_insn "*xordi3_extimm"
5631 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5632 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5633 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q")))
5634 (clobber (reg:CC CC_REGNUM))]
5635 "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5643 [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")])
5645 (define_insn "*xordi3"
5646 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5647 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5648 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5649 (clobber (reg:CC CC_REGNUM))]
5650 "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)"
5656 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5659 [(set (match_operand:DI 0 "s_operand" "")
5660 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5661 (clobber (reg:CC CC_REGNUM))]
5664 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5665 (clobber (reg:CC CC_REGNUM))])]
5666 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5669 ; xorsi3 instruction pattern(s).
5672 (define_insn "*xorsi3_cc"
5673 [(set (reg CC_REGNUM)
5674 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5675 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5677 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
5678 (xor:SI (match_dup 1) (match_dup 2)))]
5679 "s390_match_ccmode(insn, CCTmode)"
5685 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5687 (define_insn "*xorsi3_cconly"
5688 [(set (reg CC_REGNUM)
5689 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5690 (match_operand:SI 2 "general_operand" "Os,d,R,T"))
5692 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
5693 "s390_match_ccmode(insn, CCTmode)"
5699 [(set_attr "op_type" "RIL,RR,RX,RXY")])
5701 (define_insn "*xorsi3"
5702 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
5703 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
5704 (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
5705 (clobber (reg:CC CC_REGNUM))]
5706 "s390_logical_operator_ok_p (operands)"
5714 [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")])
5717 [(set (match_operand:SI 0 "s_operand" "")
5718 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5719 (clobber (reg:CC CC_REGNUM))]
5722 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5723 (clobber (reg:CC CC_REGNUM))])]
5724 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5727 ; xorhi3 instruction pattern(s).
5730 (define_insn "*xorhi3"
5731 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5732 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5733 (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
5734 (clobber (reg:CC CC_REGNUM))]
5735 "s390_logical_operator_ok_p (operands)"
5741 [(set_attr "op_type" "RIL,RR,SI,SS")])
5744 [(set (match_operand:HI 0 "s_operand" "")
5745 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5746 (clobber (reg:CC CC_REGNUM))]
5749 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5750 (clobber (reg:CC CC_REGNUM))])]
5751 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5754 ; xorqi3 instruction pattern(s).
5757 (define_insn "*xorqi3"
5758 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5759 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5760 (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
5761 (clobber (reg:CC CC_REGNUM))]
5762 "s390_logical_operator_ok_p (operands)"
5769 [(set_attr "op_type" "RIL,RR,SI,SIY,SS")])
5772 ; Block exclusive or (XC) patterns.
5776 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5777 (xor:BLK (match_dup 0)
5778 (match_operand:BLK 1 "memory_operand" "Q")))
5779 (use (match_operand 2 "const_int_operand" "n"))
5780 (clobber (reg:CC CC_REGNUM))]
5781 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5782 "xc\t%O0(%2,%R0),%S1"
5783 [(set_attr "op_type" "SS")])
5786 [(set (match_operand 0 "memory_operand" "")
5788 (match_operand 1 "memory_operand" "")))
5789 (clobber (reg:CC CC_REGNUM))]
5791 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5792 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5794 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
5796 (clobber (reg:CC CC_REGNUM))])]
5798 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5799 operands[0] = adjust_address (operands[0], BLKmode, 0);
5800 operands[1] = adjust_address (operands[1], BLKmode, 0);
5805 [(set (match_operand:BLK 0 "memory_operand" "")
5806 (xor:BLK (match_dup 0)
5807 (match_operand:BLK 1 "memory_operand" "")))
5808 (use (match_operand 2 "const_int_operand" ""))
5809 (clobber (reg:CC CC_REGNUM))])
5811 [(set (match_operand:BLK 3 "memory_operand" "")
5812 (xor:BLK (match_dup 3)
5813 (match_operand:BLK 4 "memory_operand" "")))
5814 (use (match_operand 5 "const_int_operand" ""))
5815 (clobber (reg:CC CC_REGNUM))])]
5816 "s390_offset_p (operands[0], operands[3], operands[2])
5817 && s390_offset_p (operands[1], operands[4], operands[2])
5818 && !s390_overlap_p (operands[0], operands[1],
5819 INTVAL (operands[2]) + INTVAL (operands[5]))
5820 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5822 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
5824 (clobber (reg:CC CC_REGNUM))])]
5825 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5826 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5827 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5830 ; Block xor (XC) patterns with src == dest.
5833 (define_insn "*xc_zero"
5834 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5836 (use (match_operand 1 "const_int_operand" "n"))
5837 (clobber (reg:CC CC_REGNUM))]
5838 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
5839 "xc\t%O0(%1,%R0),%S0"
5840 [(set_attr "op_type" "SS")])
5844 [(set (match_operand:BLK 0 "memory_operand" "")
5846 (use (match_operand 1 "const_int_operand" ""))
5847 (clobber (reg:CC CC_REGNUM))])
5849 [(set (match_operand:BLK 2 "memory_operand" "")
5851 (use (match_operand 3 "const_int_operand" ""))
5852 (clobber (reg:CC CC_REGNUM))])]
5853 "s390_offset_p (operands[0], operands[2], operands[1])
5854 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
5856 [(set (match_dup 4) (const_int 0))
5858 (clobber (reg:CC CC_REGNUM))])]
5859 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5860 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
5864 ;;- Negate instructions.
5868 ; neg(di|si)2 instruction pattern(s).
5871 (define_expand "neg<mode>2"
5873 [(set (match_operand:DSI 0 "register_operand" "=d")
5874 (neg:DSI (match_operand:DSI 1 "register_operand" "d")))
5875 (clobber (reg:CC CC_REGNUM))])]
5879 (define_insn "*negdi2_sign_cc"
5880 [(set (reg CC_REGNUM)
5881 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
5882 (match_operand:SI 1 "register_operand" "d") 0)
5883 (const_int 32)) (const_int 32)))
5885 (set (match_operand:DI 0 "register_operand" "=d")
5886 (neg:DI (sign_extend:DI (match_dup 1))))]
5887 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
5889 [(set_attr "op_type" "RRE")])
5891 (define_insn "*negdi2_sign"
5892 [(set (match_operand:DI 0 "register_operand" "=d")
5893 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
5894 (clobber (reg:CC CC_REGNUM))]
5897 [(set_attr "op_type" "RRE")])
5900 (define_insn "*neg<mode>2_cc"
5901 [(set (reg CC_REGNUM)
5902 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5904 (set (match_operand:GPR 0 "register_operand" "=d")
5905 (neg:GPR (match_dup 1)))]
5906 "s390_match_ccmode (insn, CCAmode)"
5908 [(set_attr "op_type" "RR<E>")])
5911 (define_insn "*neg<mode>2_cconly"
5912 [(set (reg CC_REGNUM)
5913 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d"))
5915 (clobber (match_scratch:GPR 0 "=d"))]
5916 "s390_match_ccmode (insn, CCAmode)"
5918 [(set_attr "op_type" "RR<E>")])
5921 (define_insn "*neg<mode>2"
5922 [(set (match_operand:GPR 0 "register_operand" "=d")
5923 (neg:GPR (match_operand:GPR 1 "register_operand" "d")))
5924 (clobber (reg:CC CC_REGNUM))]
5927 [(set_attr "op_type" "RR<E>")])
5929 (define_insn_and_split "*negdi2_31"
5930 [(set (match_operand:DI 0 "register_operand" "=d")
5931 (neg:DI (match_operand:DI 1 "register_operand" "d")))
5932 (clobber (reg:CC CC_REGNUM))]
5935 "&& reload_completed"
5937 [(set (match_dup 2) (neg:SI (match_dup 3)))
5938 (clobber (reg:CC CC_REGNUM))])
5940 [(set (reg:CCAP CC_REGNUM)
5941 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
5942 (set (match_dup 4) (neg:SI (match_dup 5)))])
5944 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0))
5946 (label_ref (match_dup 6))))
5948 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
5949 (clobber (reg:CC CC_REGNUM))])
5951 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
5952 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5953 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5954 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5955 operands[6] = gen_label_rtx ();")
5958 ; neg(df|sf)2 instruction pattern(s).
5961 (define_expand "neg<mode>2"
5963 [(set (match_operand:FPR 0 "register_operand" "=f")
5964 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5965 (clobber (reg:CC CC_REGNUM))])]
5969 ; lcxbr, lcdbr, lcebr
5970 (define_insn "*neg<mode>2_cc"
5971 [(set (reg CC_REGNUM)
5972 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5973 (match_operand:FPR 2 "const0_operand" "")))
5974 (set (match_operand:FPR 0 "register_operand" "=f")
5975 (neg:FPR (match_dup 1)))]
5976 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5978 [(set_attr "op_type" "RRE")
5979 (set_attr "type" "fsimp<mode>")])
5981 ; lcxbr, lcdbr, lcebr
5982 (define_insn "*neg<mode>2_cconly"
5983 [(set (reg CC_REGNUM)
5984 (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
5985 (match_operand:FPR 2 "const0_operand" "")))
5986 (clobber (match_scratch:FPR 0 "=f"))]
5987 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5989 [(set_attr "op_type" "RRE")
5990 (set_attr "type" "fsimp<mode>")])
5992 ; lcxbr, lcdbr, lcebr
5993 (define_insn "*neg<mode>2"
5994 [(set (match_operand:FPR 0 "register_operand" "=f")
5995 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
5996 (clobber (reg:CC CC_REGNUM))]
5997 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5999 [(set_attr "op_type" "RRE")
6000 (set_attr "type" "fsimp<mode>")])
6003 (define_insn "*neg<mode>2_ibm"
6004 [(set (match_operand:FPR 0 "register_operand" "=f")
6005 (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
6006 (clobber (reg:CC CC_REGNUM))]
6007 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6009 [(set_attr "op_type" "<RRe>")
6010 (set_attr "type" "fsimp<mode>")])
6014 ;;- Absolute value instructions.
6018 ; abs(di|si)2 instruction pattern(s).
6021 (define_insn "*absdi2_sign_cc"
6022 [(set (reg CC_REGNUM)
6023 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6024 (match_operand:SI 1 "register_operand" "d") 0)
6025 (const_int 32)) (const_int 32)))
6027 (set (match_operand:DI 0 "register_operand" "=d")
6028 (abs:DI (sign_extend:DI (match_dup 1))))]
6029 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6031 [(set_attr "op_type" "RRE")])
6033 (define_insn "*absdi2_sign"
6034 [(set (match_operand:DI 0 "register_operand" "=d")
6035 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6036 (clobber (reg:CC CC_REGNUM))]
6039 [(set_attr "op_type" "RRE")])
6042 (define_insn "*abs<mode>2_cc"
6043 [(set (reg CC_REGNUM)
6044 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d"))
6046 (set (match_operand:GPR 0 "register_operand" "=d")
6047 (abs:GPR (match_dup 1)))]
6048 "s390_match_ccmode (insn, CCAmode)"
6050 [(set_attr "op_type" "RR<E>")])
6053 (define_insn "*abs<mode>2_cconly"
6054 [(set (reg CC_REGNUM)
6055 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d"))
6057 (clobber (match_scratch:GPR 0 "=d"))]
6058 "s390_match_ccmode (insn, CCAmode)"
6060 [(set_attr "op_type" "RR<E>")])
6063 (define_insn "abs<mode>2"
6064 [(set (match_operand:GPR 0 "register_operand" "=d")
6065 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6066 (clobber (reg:CC CC_REGNUM))]
6069 [(set_attr "op_type" "RR<E>")])
6072 ; abs(df|sf)2 instruction pattern(s).
6075 (define_expand "abs<mode>2"
6077 [(set (match_operand:FPR 0 "register_operand" "=f")
6078 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6079 (clobber (reg:CC CC_REGNUM))])]
6083 ; lpxbr, lpdbr, lpebr
6084 (define_insn "*abs<mode>2_cc"
6085 [(set (reg CC_REGNUM)
6086 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6087 (match_operand:FPR 2 "const0_operand" "")))
6088 (set (match_operand:FPR 0 "register_operand" "=f")
6089 (abs:FPR (match_dup 1)))]
6090 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6092 [(set_attr "op_type" "RRE")
6093 (set_attr "type" "fsimp<mode>")])
6095 ; lpxbr, lpdbr, lpebr
6096 (define_insn "*abs<mode>2_cconly"
6097 [(set (reg CC_REGNUM)
6098 (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
6099 (match_operand:FPR 2 "const0_operand" "")))
6100 (clobber (match_scratch:FPR 0 "=f"))]
6101 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6103 [(set_attr "op_type" "RRE")
6104 (set_attr "type" "fsimp<mode>")])
6106 ; lpxbr, lpdbr, lpebr
6107 (define_insn "*abs<mode>2"
6108 [(set (match_operand:FPR 0 "register_operand" "=f")
6109 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6110 (clobber (reg:CC CC_REGNUM))]
6111 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6113 [(set_attr "op_type" "RRE")
6114 (set_attr "type" "fsimp<mode>")])
6117 (define_insn "*abs<mode>2_ibm"
6118 [(set (match_operand:FPR 0 "register_operand" "=f")
6119 (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6120 (clobber (reg:CC CC_REGNUM))]
6121 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6123 [(set_attr "op_type" "<RRe>")
6124 (set_attr "type" "fsimp<mode>")])
6127 ;;- Negated absolute value instructions
6134 (define_insn "*negabsdi2_sign_cc"
6135 [(set (reg CC_REGNUM)
6136 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6137 (match_operand:SI 1 "register_operand" "d") 0)
6138 (const_int 32)) (const_int 32))))
6140 (set (match_operand:DI 0 "register_operand" "=d")
6141 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6142 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6144 [(set_attr "op_type" "RRE")])
6146 (define_insn "*negabsdi2_sign"
6147 [(set (match_operand:DI 0 "register_operand" "=d")
6148 (neg:DI (abs:DI (sign_extend:DI
6149 (match_operand:SI 1 "register_operand" "d")))))
6150 (clobber (reg:CC CC_REGNUM))]
6153 [(set_attr "op_type" "RRE")])
6156 (define_insn "*negabs<mode>2_cc"
6157 [(set (reg CC_REGNUM)
6158 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6160 (set (match_operand:GPR 0 "register_operand" "=d")
6161 (neg:GPR (abs:GPR (match_dup 1))))]
6162 "s390_match_ccmode (insn, CCAmode)"
6164 [(set_attr "op_type" "RR<E>")])
6167 (define_insn "*negabs<mode>2_cconly"
6168 [(set (reg CC_REGNUM)
6169 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))
6171 (clobber (match_scratch:GPR 0 "=d"))]
6172 "s390_match_ccmode (insn, CCAmode)"
6174 [(set_attr "op_type" "RR<E>")])
6177 (define_insn "*negabs<mode>2"
6178 [(set (match_operand:GPR 0 "register_operand" "=d")
6179 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))))
6180 (clobber (reg:CC CC_REGNUM))]
6183 [(set_attr "op_type" "RR<E>")])
6189 ; lnxbr, lndbr, lnebr
6190 (define_insn "*negabs<mode>2_cc"
6191 [(set (reg CC_REGNUM)
6192 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6193 (match_operand:FPR 2 "const0_operand" "")))
6194 (set (match_operand:FPR 0 "register_operand" "=f")
6195 (neg:FPR (abs:FPR (match_dup 1))))]
6196 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6198 [(set_attr "op_type" "RRE")
6199 (set_attr "type" "fsimp<mode>")])
6201 ; lnxbr, lndbr, lnebr
6202 (define_insn "*negabs<mode>2_cconly"
6203 [(set (reg CC_REGNUM)
6204 (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
6205 (match_operand:FPR 2 "const0_operand" "")))
6206 (clobber (match_scratch:FPR 0 "=f"))]
6207 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6209 [(set_attr "op_type" "RRE")
6210 (set_attr "type" "fsimp<mode>")])
6212 ; lnxbr, lndbr, lnebr
6213 (define_insn "*negabs<mode>2"
6214 [(set (match_operand:FPR 0 "register_operand" "=f")
6215 (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
6216 (clobber (reg:CC CC_REGNUM))]
6217 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6219 [(set_attr "op_type" "RRE")
6220 (set_attr "type" "fsimp<mode>")])
6223 ;;- Square root instructions.
6227 ; sqrt(df|sf)2 instruction pattern(s).
6230 ; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
6231 (define_insn "sqrt<mode>2"
6232 [(set (match_operand:FPR 0 "register_operand" "=f,f")
6233 (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
6234 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6238 [(set_attr "op_type" "RRE,RXE")
6239 (set_attr "type" "fsqrt<mode>")])
6243 ;;- One complement instructions.
6247 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s).
6250 (define_expand "one_cmpl<mode>2"
6252 [(set (match_operand:INT 0 "register_operand" "")
6253 (xor:INT (match_operand:INT 1 "register_operand" "")
6255 (clobber (reg:CC CC_REGNUM))])]
6261 ;; Find leftmost bit instructions.
6264 (define_expand "clzdi2"
6265 [(set (match_operand:DI 0 "register_operand" "=d")
6266 (clz:DI (match_operand:DI 1 "register_operand" "d")))]
6267 "TARGET_EXTIMM && TARGET_64BIT"
6269 rtx insn, clz_equal;
6270 rtx wide_reg = gen_reg_rtx (TImode);
6271 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
6273 clz_equal = gen_rtx_CLZ (DImode, operands[1]);
6275 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb));
6277 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg));
6279 gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn));
6284 (define_insn "clztidi2"
6285 [(set (match_operand:TI 0 "register_operand" "=d")
6289 (xor:DI (match_operand:DI 1 "register_operand" "d")
6290 (lshiftrt (match_operand:DI 2 "const_int_operand" "")
6291 (subreg:SI (clz:DI (match_dup 1)) 4))))
6294 (zero_extend:TI (clz:DI (match_dup 1)))))
6295 (clobber (reg:CC CC_REGNUM))]
6296 "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
6297 == (unsigned HOST_WIDE_INT) 1 << 63
6298 && TARGET_EXTIMM && TARGET_64BIT"
6300 [(set_attr "op_type" "RRE")])
6304 ;;- Rotate instructions.
6308 ; rotl(di|si)3 instruction pattern(s).
6312 (define_insn "rotl<mode>3"
6313 [(set (match_operand:GPR 0 "register_operand" "=d")
6314 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6315 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6318 [(set_attr "op_type" "RSE")
6319 (set_attr "atype" "reg")])
6322 (define_insn "*rotl<mode>3_and"
6323 [(set (match_operand:GPR 0 "register_operand" "=d")
6324 (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
6325 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6326 (match_operand:SI 3 "const_int_operand" "n"))))]
6327 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
6329 [(set_attr "op_type" "RSE")
6330 (set_attr "atype" "reg")])
6334 ;;- Shift instructions.
6338 ; (ashl|lshr)(di|si)3 instruction pattern(s).
6341 (define_expand "<shift><mode>3"
6342 [(set (match_operand:DSI 0 "register_operand" "")
6343 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
6344 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
6349 (define_insn "*<shift>di3_31"
6350 [(set (match_operand:DI 0 "register_operand" "=d")
6351 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6352 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6355 [(set_attr "op_type" "RS")
6356 (set_attr "atype" "reg")])
6358 ; sll, srl, sllg, srlg
6359 (define_insn "*<shift><mode>3"
6360 [(set (match_operand:GPR 0 "register_operand" "=d")
6361 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6362 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
6364 "s<lr>l<g>\t%0,<1>%Y2"
6365 [(set_attr "op_type" "RS<E>")
6366 (set_attr "atype" "reg")])
6369 (define_insn "*<shift>di3_31_and"
6370 [(set (match_operand:DI 0 "register_operand" "=d")
6371 (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
6372 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6373 (match_operand:SI 3 "const_int_operand" "n"))))]
6374 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6376 [(set_attr "op_type" "RS")
6377 (set_attr "atype" "reg")])
6379 ; sll, srl, sllg, srlg
6380 (define_insn "*<shift><mode>3_and"
6381 [(set (match_operand:GPR 0 "register_operand" "=d")
6382 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6383 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6384 (match_operand:SI 3 "const_int_operand" "n"))))]
6385 "(INTVAL (operands[3]) & 63) == 63"
6386 "s<lr>l<g>\t%0,<1>%Y2"
6387 [(set_attr "op_type" "RS<E>")
6388 (set_attr "atype" "reg")])
6391 ; ashr(di|si)3 instruction pattern(s).
6394 (define_expand "ashr<mode>3"
6396 [(set (match_operand:DSI 0 "register_operand" "")
6397 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
6398 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
6399 (clobber (reg:CC CC_REGNUM))])]
6403 (define_insn "*ashrdi3_cc_31"
6404 [(set (reg CC_REGNUM)
6405 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6406 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6408 (set (match_operand:DI 0 "register_operand" "=d")
6409 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6410 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6412 [(set_attr "op_type" "RS")
6413 (set_attr "atype" "reg")])
6415 (define_insn "*ashrdi3_cconly_31"
6416 [(set (reg CC_REGNUM)
6417 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6418 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6420 (clobber (match_scratch:DI 0 "=d"))]
6421 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6423 [(set_attr "op_type" "RS")
6424 (set_attr "atype" "reg")])
6426 (define_insn "*ashrdi3_31"
6427 [(set (match_operand:DI 0 "register_operand" "=d")
6428 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6429 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6430 (clobber (reg:CC CC_REGNUM))]
6433 [(set_attr "op_type" "RS")
6434 (set_attr "atype" "reg")])
6437 (define_insn "*ashr<mode>3_cc"
6438 [(set (reg CC_REGNUM)
6439 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6440 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6442 (set (match_operand:GPR 0 "register_operand" "=d")
6443 (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
6444 "s390_match_ccmode(insn, CCSmode)"
6446 [(set_attr "op_type" "RS<E>")
6447 (set_attr "atype" "reg")])
6450 (define_insn "*ashr<mode>3_cconly"
6451 [(set (reg CC_REGNUM)
6452 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6453 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
6455 (clobber (match_scratch:GPR 0 "=d"))]
6456 "s390_match_ccmode(insn, CCSmode)"
6458 [(set_attr "op_type" "RS<E>")
6459 (set_attr "atype" "reg")])
6462 (define_insn "*ashr<mode>3"
6463 [(set (match_operand:GPR 0 "register_operand" "=d")
6464 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6465 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
6466 (clobber (reg:CC CC_REGNUM))]
6469 [(set_attr "op_type" "RS<E>")
6470 (set_attr "atype" "reg")])
6473 ; shift pattern with implicit ANDs
6475 (define_insn "*ashrdi3_cc_31_and"
6476 [(set (reg CC_REGNUM)
6477 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6478 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6479 (match_operand:SI 3 "const_int_operand" "n")))
6481 (set (match_operand:DI 0 "register_operand" "=d")
6482 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6483 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6484 && (INTVAL (operands[3]) & 63) == 63"
6486 [(set_attr "op_type" "RS")
6487 (set_attr "atype" "reg")])
6489 (define_insn "*ashrdi3_cconly_31_and"
6490 [(set (reg CC_REGNUM)
6491 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6492 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6493 (match_operand:SI 3 "const_int_operand" "n")))
6495 (clobber (match_scratch:DI 0 "=d"))]
6496 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
6497 && (INTVAL (operands[3]) & 63) == 63"
6499 [(set_attr "op_type" "RS")
6500 (set_attr "atype" "reg")])
6502 (define_insn "*ashrdi3_31_and"
6503 [(set (match_operand:DI 0 "register_operand" "=d")
6504 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6505 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6506 (match_operand:SI 3 "const_int_operand" "n"))))
6507 (clobber (reg:CC CC_REGNUM))]
6508 "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
6510 [(set_attr "op_type" "RS")
6511 (set_attr "atype" "reg")])
6514 (define_insn "*ashr<mode>3_cc_and"
6515 [(set (reg CC_REGNUM)
6516 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6517 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6518 (match_operand:SI 3 "const_int_operand" "n")))
6520 (set (match_operand:GPR 0 "register_operand" "=d")
6521 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
6522 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6524 [(set_attr "op_type" "RS<E>")
6525 (set_attr "atype" "reg")])
6528 (define_insn "*ashr<mode>3_cconly_and"
6529 [(set (reg CC_REGNUM)
6530 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6531 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6532 (match_operand:SI 3 "const_int_operand" "n")))
6534 (clobber (match_scratch:GPR 0 "=d"))]
6535 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
6537 [(set_attr "op_type" "RS<E>")
6538 (set_attr "atype" "reg")])
6541 (define_insn "*ashr<mode>3_and"
6542 [(set (match_operand:GPR 0 "register_operand" "=d")
6543 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
6544 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
6545 (match_operand:SI 3 "const_int_operand" "n"))))
6546 (clobber (reg:CC CC_REGNUM))]
6547 "(INTVAL (operands[3]) & 63) == 63"
6549 [(set_attr "op_type" "RS<E>")
6550 (set_attr "atype" "reg")])
6554 ;; Branch instruction patterns.
6557 (define_expand "b<code>"
6559 (if_then_else (COMPARE (match_operand 0 "" "")
6564 "s390_emit_jump (operands[0],
6565 s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;")
6569 ;;- Conditional jump instructions.
6572 (define_insn "*cjump_64"
6575 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6576 (label_ref (match_operand 0 "" ""))
6580 if (get_attr_length (insn) == 4)
6583 return "jg%C1\t%l0";
6585 [(set_attr "op_type" "RI")
6586 (set_attr "type" "branch")
6587 (set (attr "length")
6588 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6589 (const_int 4) (const_int 6)))])
6591 (define_insn "*cjump_31"
6594 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6595 (label_ref (match_operand 0 "" ""))
6599 gcc_assert (get_attr_length (insn) == 4);
6602 [(set_attr "op_type" "RI")
6603 (set_attr "type" "branch")
6604 (set (attr "length")
6605 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6606 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6607 (const_int 4) (const_int 6))
6608 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6609 (const_int 4) (const_int 8))))])
6611 (define_insn "*cjump_long"
6614 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6615 (match_operand 0 "address_operand" "U")
6619 if (get_attr_op_type (insn) == OP_TYPE_RR)
6624 [(set (attr "op_type")
6625 (if_then_else (match_operand 0 "register_operand" "")
6626 (const_string "RR") (const_string "RX")))
6627 (set_attr "type" "branch")
6628 (set_attr "atype" "agen")])
6632 ;;- Negated conditional jump instructions.
6635 (define_insn "*icjump_64"
6638 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6640 (label_ref (match_operand 0 "" ""))))]
6643 if (get_attr_length (insn) == 4)
6646 return "jg%D1\t%l0";
6648 [(set_attr "op_type" "RI")
6649 (set_attr "type" "branch")
6650 (set (attr "length")
6651 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6652 (const_int 4) (const_int 6)))])
6654 (define_insn "*icjump_31"
6657 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6659 (label_ref (match_operand 0 "" ""))))]
6662 gcc_assert (get_attr_length (insn) == 4);
6665 [(set_attr "op_type" "RI")
6666 (set_attr "type" "branch")
6667 (set (attr "length")
6668 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6669 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6670 (const_int 4) (const_int 6))
6671 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6672 (const_int 4) (const_int 8))))])
6674 (define_insn "*icjump_long"
6677 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6679 (match_operand 0 "address_operand" "U")))]
6682 if (get_attr_op_type (insn) == OP_TYPE_RR)
6687 [(set (attr "op_type")
6688 (if_then_else (match_operand 0 "register_operand" "")
6689 (const_string "RR") (const_string "RX")))
6690 (set_attr "type" "branch")
6691 (set_attr "atype" "agen")])
6694 ;;- Trap instructions.
6698 [(trap_if (const_int 1) (const_int 0))]
6701 [(set_attr "op_type" "RI")
6702 (set_attr "type" "branch")])
6704 (define_expand "conditional_trap"
6705 [(trap_if (match_operand 0 "comparison_operator" "")
6706 (match_operand 1 "general_operand" ""))]
6709 if (operands[1] != const0_rtx) FAIL;
6710 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
6711 s390_compare_op0, s390_compare_op1);
6714 (define_insn "*trap"
6715 [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
6719 [(set_attr "op_type" "RI")
6720 (set_attr "type" "branch")])
6723 ;;- Loop instructions.
6725 ;; This is all complicated by the fact that since this is a jump insn
6726 ;; we must handle our own output reloads.
6728 (define_expand "doloop_end"
6729 [(use (match_operand 0 "" "")) ; loop pseudo
6730 (use (match_operand 1 "" "")) ; iterations; zero if unknown
6731 (use (match_operand 2 "" "")) ; max iterations
6732 (use (match_operand 3 "" "")) ; loop level
6733 (use (match_operand 4 "" ""))] ; label
6736 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
6737 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
6738 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
6739 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
6740 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
6741 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
6748 (define_insn_and_split "doloop_si64"
6751 (ne (match_operand:SI 1 "register_operand" "d,d,d")
6753 (label_ref (match_operand 0 "" ""))
6755 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
6756 (plus:SI (match_dup 1) (const_int -1)))
6757 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
6758 (clobber (reg:CC CC_REGNUM))]
6761 if (which_alternative != 0)
6763 else if (get_attr_length (insn) == 4)
6764 return "brct\t%1,%l0";
6766 return "ahi\t%1,-1\;jgne\t%l0";
6768 "&& reload_completed
6769 && (! REG_P (operands[2])
6770 || ! rtx_equal_p (operands[1], operands[2]))"
6771 [(set (match_dup 3) (match_dup 1))
6772 (parallel [(set (reg:CCAN CC_REGNUM)
6773 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6775 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6776 (set (match_dup 2) (match_dup 3))
6777 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6778 (label_ref (match_dup 0))
6781 [(set_attr "op_type" "RI")
6782 (set_attr "type" "branch")
6783 (set (attr "length")
6784 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6785 (const_int 4) (const_int 10)))])
6787 (define_insn_and_split "doloop_si31"
6790 (ne (match_operand:SI 1 "register_operand" "d,d,d")
6792 (label_ref (match_operand 0 "" ""))
6794 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
6795 (plus:SI (match_dup 1) (const_int -1)))
6796 (clobber (match_scratch:SI 3 "=X,&1,&?d"))
6797 (clobber (reg:CC CC_REGNUM))]
6800 if (which_alternative != 0)
6802 else if (get_attr_length (insn) == 4)
6803 return "brct\t%1,%l0";
6807 "&& reload_completed
6808 && (! REG_P (operands[2])
6809 || ! rtx_equal_p (operands[1], operands[2]))"
6810 [(set (match_dup 3) (match_dup 1))
6811 (parallel [(set (reg:CCAN CC_REGNUM)
6812 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
6814 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
6815 (set (match_dup 2) (match_dup 3))
6816 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6817 (label_ref (match_dup 0))
6820 [(set_attr "op_type" "RI")
6821 (set_attr "type" "branch")
6822 (set (attr "length")
6823 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6824 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6825 (const_int 4) (const_int 6))
6826 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6827 (const_int 4) (const_int 8))))])
6829 (define_insn "*doloop_si_long"
6832 (ne (match_operand:SI 1 "register_operand" "d")
6834 (match_operand 0 "address_operand" "U")
6836 (set (match_operand:SI 2 "register_operand" "=1")
6837 (plus:SI (match_dup 1) (const_int -1)))
6838 (clobber (match_scratch:SI 3 "=X"))
6839 (clobber (reg:CC CC_REGNUM))]
6842 if (get_attr_op_type (insn) == OP_TYPE_RR)
6843 return "bctr\t%1,%0";
6845 return "bct\t%1,%a0";
6847 [(set (attr "op_type")
6848 (if_then_else (match_operand 0 "register_operand" "")
6849 (const_string "RR") (const_string "RX")))
6850 (set_attr "type" "branch")
6851 (set_attr "atype" "agen")])
6853 (define_insn_and_split "doloop_di"
6856 (ne (match_operand:DI 1 "register_operand" "d,d,d")
6858 (label_ref (match_operand 0 "" ""))
6860 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X")
6861 (plus:DI (match_dup 1) (const_int -1)))
6862 (clobber (match_scratch:DI 3 "=X,&1,&?d"))
6863 (clobber (reg:CC CC_REGNUM))]
6866 if (which_alternative != 0)
6868 else if (get_attr_length (insn) == 4)
6869 return "brctg\t%1,%l0";
6871 return "aghi\t%1,-1\;jgne\t%l0";
6873 "&& reload_completed
6874 && (! REG_P (operands[2])
6875 || ! rtx_equal_p (operands[1], operands[2]))"
6876 [(set (match_dup 3) (match_dup 1))
6877 (parallel [(set (reg:CCAN CC_REGNUM)
6878 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
6880 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
6881 (set (match_dup 2) (match_dup 3))
6882 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
6883 (label_ref (match_dup 0))
6886 [(set_attr "op_type" "RI")
6887 (set_attr "type" "branch")
6888 (set (attr "length")
6889 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6890 (const_int 4) (const_int 10)))])
6893 ;;- Unconditional jump instructions.
6897 ; jump instruction pattern(s).
6900 (define_expand "jump"
6901 [(match_operand 0 "" "")]
6903 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
6905 (define_insn "*jump64"
6906 [(set (pc) (label_ref (match_operand 0 "" "")))]
6909 if (get_attr_length (insn) == 4)
6914 [(set_attr "op_type" "RI")
6915 (set_attr "type" "branch")
6916 (set (attr "length")
6917 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6918 (const_int 4) (const_int 6)))])
6920 (define_insn "*jump31"
6921 [(set (pc) (label_ref (match_operand 0 "" "")))]
6924 gcc_assert (get_attr_length (insn) == 4);
6927 [(set_attr "op_type" "RI")
6928 (set_attr "type" "branch")
6929 (set (attr "length")
6930 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6931 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6932 (const_int 4) (const_int 6))
6933 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
6934 (const_int 4) (const_int 8))))])
6937 ; indirect-jump instruction pattern(s).
6940 (define_insn "indirect_jump"
6941 [(set (pc) (match_operand 0 "address_operand" "U"))]
6944 if (get_attr_op_type (insn) == OP_TYPE_RR)
6949 [(set (attr "op_type")
6950 (if_then_else (match_operand 0 "register_operand" "")
6951 (const_string "RR") (const_string "RX")))
6952 (set_attr "type" "branch")
6953 (set_attr "atype" "agen")])
6956 ; casesi instruction pattern(s).
6959 (define_insn "casesi_jump"
6960 [(set (pc) (match_operand 0 "address_operand" "U"))
6961 (use (label_ref (match_operand 1 "" "")))]
6964 if (get_attr_op_type (insn) == OP_TYPE_RR)
6969 [(set (attr "op_type")
6970 (if_then_else (match_operand 0 "register_operand" "")
6971 (const_string "RR") (const_string "RX")))
6972 (set_attr "type" "branch")
6973 (set_attr "atype" "agen")])
6975 (define_expand "casesi"
6976 [(match_operand:SI 0 "general_operand" "")
6977 (match_operand:SI 1 "general_operand" "")
6978 (match_operand:SI 2 "general_operand" "")
6979 (label_ref (match_operand 3 "" ""))
6980 (label_ref (match_operand 4 "" ""))]
6983 rtx index = gen_reg_rtx (SImode);
6984 rtx base = gen_reg_rtx (Pmode);
6985 rtx target = gen_reg_rtx (Pmode);
6987 emit_move_insn (index, operands[0]);
6988 emit_insn (gen_subsi3 (index, index, operands[1]));
6989 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
6992 if (Pmode != SImode)
6993 index = convert_to_mode (Pmode, index, 1);
6994 if (GET_CODE (index) != REG)
6995 index = copy_to_mode_reg (Pmode, index);
6998 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7000 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7002 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7004 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7005 emit_move_insn (target, index);
7008 target = gen_rtx_PLUS (Pmode, base, target);
7009 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7016 ;;- Jump to subroutine.
7021 ; untyped call instruction pattern(s).
7024 ;; Call subroutine returning any type.
7025 (define_expand "untyped_call"
7026 [(parallel [(call (match_operand 0 "" "")
7028 (match_operand 1 "" "")
7029 (match_operand 2 "" "")])]
7034 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7036 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7038 rtx set = XVECEXP (operands[2], 0, i);
7039 emit_move_insn (SET_DEST (set), SET_SRC (set));
7042 /* The optimizer does not know that the call sets the function value
7043 registers we stored in the result block. We avoid problems by
7044 claiming that all hard registers are used and clobbered at this
7046 emit_insn (gen_blockage ());
7051 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7052 ;; all of memory. This blocks insns from being moved across this point.
7054 (define_insn "blockage"
7055 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7058 [(set_attr "type" "none")
7059 (set_attr "length" "0")])
7065 (define_expand "sibcall"
7066 [(call (match_operand 0 "" "")
7067 (match_operand 1 "" ""))]
7070 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7074 (define_insn "*sibcall_br"
7075 [(call (mem:QI (reg SIBCALL_REGNUM))
7076 (match_operand 0 "const_int_operand" "n"))]
7077 "SIBLING_CALL_P (insn)
7078 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7080 [(set_attr "op_type" "RR")
7081 (set_attr "type" "branch")
7082 (set_attr "atype" "agen")])
7084 (define_insn "*sibcall_brc"
7085 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7086 (match_operand 1 "const_int_operand" "n"))]
7087 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7089 [(set_attr "op_type" "RI")
7090 (set_attr "type" "branch")])
7092 (define_insn "*sibcall_brcl"
7093 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7094 (match_operand 1 "const_int_operand" "n"))]
7095 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7097 [(set_attr "op_type" "RIL")
7098 (set_attr "type" "branch")])
7101 ; sibcall_value patterns
7104 (define_expand "sibcall_value"
7105 [(set (match_operand 0 "" "")
7106 (call (match_operand 1 "" "")
7107 (match_operand 2 "" "")))]
7110 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7114 (define_insn "*sibcall_value_br"
7115 [(set (match_operand 0 "" "")
7116 (call (mem:QI (reg SIBCALL_REGNUM))
7117 (match_operand 1 "const_int_operand" "n")))]
7118 "SIBLING_CALL_P (insn)
7119 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7121 [(set_attr "op_type" "RR")
7122 (set_attr "type" "branch")
7123 (set_attr "atype" "agen")])
7125 (define_insn "*sibcall_value_brc"
7126 [(set (match_operand 0 "" "")
7127 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7128 (match_operand 2 "const_int_operand" "n")))]
7129 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7131 [(set_attr "op_type" "RI")
7132 (set_attr "type" "branch")])
7134 (define_insn "*sibcall_value_brcl"
7135 [(set (match_operand 0 "" "")
7136 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7137 (match_operand 2 "const_int_operand" "n")))]
7138 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7140 [(set_attr "op_type" "RIL")
7141 (set_attr "type" "branch")])
7145 ; call instruction pattern(s).
7148 (define_expand "call"
7149 [(call (match_operand 0 "" "")
7150 (match_operand 1 "" ""))
7151 (use (match_operand 2 "" ""))]
7154 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7155 gen_rtx_REG (Pmode, RETURN_REGNUM));
7159 (define_insn "*bras"
7160 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7161 (match_operand 1 "const_int_operand" "n"))
7162 (clobber (match_operand 2 "register_operand" "=r"))]
7163 "!SIBLING_CALL_P (insn)
7164 && TARGET_SMALL_EXEC
7165 && GET_MODE (operands[2]) == Pmode"
7167 [(set_attr "op_type" "RI")
7168 (set_attr "type" "jsr")])
7170 (define_insn "*brasl"
7171 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7172 (match_operand 1 "const_int_operand" "n"))
7173 (clobber (match_operand 2 "register_operand" "=r"))]
7174 "!SIBLING_CALL_P (insn)
7176 && GET_MODE (operands[2]) == Pmode"
7178 [(set_attr "op_type" "RIL")
7179 (set_attr "type" "jsr")])
7181 (define_insn "*basr"
7182 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7183 (match_operand 1 "const_int_operand" "n"))
7184 (clobber (match_operand 2 "register_operand" "=r"))]
7185 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7187 if (get_attr_op_type (insn) == OP_TYPE_RR)
7188 return "basr\t%2,%0";
7190 return "bas\t%2,%a0";
7192 [(set (attr "op_type")
7193 (if_then_else (match_operand 0 "register_operand" "")
7194 (const_string "RR") (const_string "RX")))
7195 (set_attr "type" "jsr")
7196 (set_attr "atype" "agen")])
7199 ; call_value instruction pattern(s).
7202 (define_expand "call_value"
7203 [(set (match_operand 0 "" "")
7204 (call (match_operand 1 "" "")
7205 (match_operand 2 "" "")))
7206 (use (match_operand 3 "" ""))]
7209 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7210 gen_rtx_REG (Pmode, RETURN_REGNUM));
7214 (define_insn "*bras_r"
7215 [(set (match_operand 0 "" "")
7216 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7217 (match_operand:SI 2 "const_int_operand" "n")))
7218 (clobber (match_operand 3 "register_operand" "=r"))]
7219 "!SIBLING_CALL_P (insn)
7220 && TARGET_SMALL_EXEC
7221 && GET_MODE (operands[3]) == Pmode"
7223 [(set_attr "op_type" "RI")
7224 (set_attr "type" "jsr")])
7226 (define_insn "*brasl_r"
7227 [(set (match_operand 0 "" "")
7228 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7229 (match_operand 2 "const_int_operand" "n")))
7230 (clobber (match_operand 3 "register_operand" "=r"))]
7231 "!SIBLING_CALL_P (insn)
7233 && GET_MODE (operands[3]) == Pmode"
7235 [(set_attr "op_type" "RIL")
7236 (set_attr "type" "jsr")])
7238 (define_insn "*basr_r"
7239 [(set (match_operand 0 "" "")
7240 (call (mem:QI (match_operand 1 "address_operand" "U"))
7241 (match_operand 2 "const_int_operand" "n")))
7242 (clobber (match_operand 3 "register_operand" "=r"))]
7243 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7245 if (get_attr_op_type (insn) == OP_TYPE_RR)
7246 return "basr\t%3,%1";
7248 return "bas\t%3,%a1";
7250 [(set (attr "op_type")
7251 (if_then_else (match_operand 1 "register_operand" "")
7252 (const_string "RR") (const_string "RX")))
7253 (set_attr "type" "jsr")
7254 (set_attr "atype" "agen")])
7257 ;;- Thread-local storage support.
7260 (define_expand "get_tp_64"
7261 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))]
7265 (define_expand "get_tp_31"
7266 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))]
7270 (define_expand "set_tp_64"
7271 [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" ""))
7272 (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))]
7276 (define_expand "set_tp_31"
7277 [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" ""))
7278 (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))]
7282 (define_insn "*set_tp"
7283 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))]
7286 [(set_attr "type" "none")
7287 (set_attr "length" "0")])
7289 (define_insn "*tls_load_64"
7290 [(set (match_operand:DI 0 "register_operand" "=d")
7291 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7292 (match_operand:DI 2 "" "")]
7296 [(set_attr "op_type" "RXE")])
7298 (define_insn "*tls_load_31"
7299 [(set (match_operand:SI 0 "register_operand" "=d,d")
7300 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7301 (match_operand:SI 2 "" "")]
7307 [(set_attr "op_type" "RX,RXY")])
7309 (define_insn "*bras_tls"
7310 [(set (match_operand 0 "" "")
7311 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7312 (match_operand 2 "const_int_operand" "n")))
7313 (clobber (match_operand 3 "register_operand" "=r"))
7314 (use (match_operand 4 "" ""))]
7315 "!SIBLING_CALL_P (insn)
7316 && TARGET_SMALL_EXEC
7317 && GET_MODE (operands[3]) == Pmode"
7319 [(set_attr "op_type" "RI")
7320 (set_attr "type" "jsr")])
7322 (define_insn "*brasl_tls"
7323 [(set (match_operand 0 "" "")
7324 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7325 (match_operand 2 "const_int_operand" "n")))
7326 (clobber (match_operand 3 "register_operand" "=r"))
7327 (use (match_operand 4 "" ""))]
7328 "!SIBLING_CALL_P (insn)
7330 && GET_MODE (operands[3]) == Pmode"
7332 [(set_attr "op_type" "RIL")
7333 (set_attr "type" "jsr")])
7335 (define_insn "*basr_tls"
7336 [(set (match_operand 0 "" "")
7337 (call (mem:QI (match_operand 1 "address_operand" "U"))
7338 (match_operand 2 "const_int_operand" "n")))
7339 (clobber (match_operand 3 "register_operand" "=r"))
7340 (use (match_operand 4 "" ""))]
7341 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7343 if (get_attr_op_type (insn) == OP_TYPE_RR)
7344 return "basr\t%3,%1%J4";
7346 return "bas\t%3,%a1%J4";
7348 [(set (attr "op_type")
7349 (if_then_else (match_operand 1 "register_operand" "")
7350 (const_string "RR") (const_string "RX")))
7351 (set_attr "type" "jsr")
7352 (set_attr "atype" "agen")])
7355 ;;- Atomic operations
7359 ; memory barrier pattern.
7362 (define_expand "memory_barrier"
7363 [(set (mem:BLK (match_dup 0))
7364 (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))]
7367 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
7368 MEM_VOLATILE_P (operands[0]) = 1;
7371 (define_insn "*memory_barrier"
7372 [(set (match_operand:BLK 0 "" "")
7373 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))]
7376 [(set_attr "op_type" "RR")])
7379 ; compare and swap patterns.
7382 (define_expand "sync_compare_and_swap<mode>"
7384 [(set (match_operand:TDSI 0 "register_operand" "")
7385 (match_operand:TDSI 1 "memory_operand" ""))
7387 (unspec_volatile:TDSI
7389 (match_operand:TDSI 2 "register_operand" "")
7390 (match_operand:TDSI 3 "register_operand" "")]
7392 (set (reg:CCZ1 CC_REGNUM)
7393 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7396 (define_expand "sync_compare_and_swap<mode>"
7398 [(set (match_operand:HQI 0 "register_operand" "")
7399 (match_operand:HQI 1 "memory_operand" ""))
7401 (unspec_volatile:HQI
7403 (match_operand:HQI 2 "general_operand" "")
7404 (match_operand:HQI 3 "general_operand" "")]
7406 (set (reg:CCZ1 CC_REGNUM)
7407 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7409 "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1],
7410 operands[2], operands[3]); DONE;")
7412 (define_expand "sync_compare_and_swap_cc<mode>"
7414 [(set (match_operand:TDSI 0 "register_operand" "")
7415 (match_operand:TDSI 1 "memory_operand" ""))
7417 (unspec_volatile:TDSI
7419 (match_operand:TDSI 2 "register_operand" "")
7420 (match_operand:TDSI 3 "register_operand" "")]
7423 (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
7426 /* Emulate compare. */
7427 operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM);
7428 s390_compare_op0 = operands[1];
7429 s390_compare_op1 = operands[2];
7430 s390_compare_emitted = operands[4];
7434 (define_insn "*sync_compare_and_swap<mode>"
7435 [(set (match_operand:DP 0 "register_operand" "=r")
7436 (match_operand:DP 1 "memory_operand" "+Q"))
7440 (match_operand:DP 2 "register_operand" "0")
7441 (match_operand:DP 3 "register_operand" "r")]
7443 (set (reg:CCZ1 CC_REGNUM)
7444 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7446 "cds<tg>\t%0,%3,%S1"
7447 [(set_attr "op_type" "RS<TE>")
7448 (set_attr "type" "sem")])
7451 (define_insn "*sync_compare_and_swap<mode>"
7452 [(set (match_operand:GPR 0 "register_operand" "=r")
7453 (match_operand:GPR 1 "memory_operand" "+Q"))
7455 (unspec_volatile:GPR
7457 (match_operand:GPR 2 "register_operand" "0")
7458 (match_operand:GPR 3 "register_operand" "r")]
7460 (set (reg:CCZ1 CC_REGNUM)
7461 (compare:CCZ1 (match_dup 1) (match_dup 2)))]
7464 [(set_attr "op_type" "RS<E>")
7465 (set_attr "type" "sem")])
7469 ; Other atomic instruction patterns.
7472 (define_expand "sync_lock_test_and_set<mode>"
7473 [(match_operand:HQI 0 "register_operand")
7474 (match_operand:HQI 1 "memory_operand")
7475 (match_operand:HQI 2 "general_operand")]
7477 "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
7478 operands[2], false); DONE;")
7480 (define_expand "sync_<atomic><mode>"
7481 [(set (match_operand:HQI 0 "memory_operand")
7482 (ATOMIC:HQI (match_dup 0)
7483 (match_operand:HQI 1 "general_operand")))]
7485 "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0],
7486 operands[1], false); DONE;")
7488 (define_expand "sync_old_<atomic><mode>"
7489 [(set (match_operand:HQI 0 "register_operand")
7490 (match_operand:HQI 1 "memory_operand"))
7492 (ATOMIC:HQI (match_dup 1)
7493 (match_operand:HQI 2 "general_operand")))]
7495 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7496 operands[2], false); DONE;")
7498 (define_expand "sync_new_<atomic><mode>"
7499 [(set (match_operand:HQI 0 "register_operand")
7500 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
7501 (match_operand:HQI 2 "general_operand")))
7502 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
7504 "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1],
7505 operands[2], true); DONE;")
7508 ;;- Miscellaneous instructions.
7512 ; allocate stack instruction pattern(s).
7515 (define_expand "allocate_stack"
7516 [(match_operand 0 "general_operand" "")
7517 (match_operand 1 "general_operand" "")]
7520 rtx temp = gen_reg_rtx (Pmode);
7522 emit_move_insn (temp, s390_back_chain_rtx ());
7523 anti_adjust_stack (operands[1]);
7524 emit_move_insn (s390_back_chain_rtx (), temp);
7526 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7532 ; setjmp instruction pattern.
7535 (define_expand "builtin_setjmp_receiver"
7536 [(match_operand 0 "" "")]
7539 emit_insn (s390_load_got ());
7540 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7544 ;; These patterns say how to save and restore the stack pointer. We need not
7545 ;; save the stack pointer at function level since we are careful to
7546 ;; preserve the backchain. At block level, we have to restore the backchain
7547 ;; when we restore the stack pointer.
7549 ;; For nonlocal gotos, we must save both the stack pointer and its
7550 ;; backchain and restore both. Note that in the nonlocal case, the
7551 ;; save area is a memory location.
7553 (define_expand "save_stack_function"
7554 [(match_operand 0 "general_operand" "")
7555 (match_operand 1 "general_operand" "")]
7559 (define_expand "restore_stack_function"
7560 [(match_operand 0 "general_operand" "")
7561 (match_operand 1 "general_operand" "")]
7565 (define_expand "restore_stack_block"
7566 [(match_operand 0 "register_operand" "")
7567 (match_operand 1 "register_operand" "")]
7570 rtx temp = gen_reg_rtx (Pmode);
7572 emit_move_insn (temp, s390_back_chain_rtx ());
7573 emit_move_insn (operands[0], operands[1]);
7574 emit_move_insn (s390_back_chain_rtx (), temp);
7579 (define_expand "save_stack_nonlocal"
7580 [(match_operand 0 "memory_operand" "")
7581 (match_operand 1 "register_operand" "")]
7584 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7585 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7587 /* Copy the backchain to the first word, sp to the second and the
7588 literal pool base to the third. */
7590 if (TARGET_BACKCHAIN)
7592 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7593 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7596 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7597 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7602 (define_expand "restore_stack_nonlocal"
7603 [(match_operand 0 "register_operand" "")
7604 (match_operand 1 "memory_operand" "")]
7607 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7608 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7609 rtx temp = NULL_RTX;
7611 /* Restore the backchain from the first word, sp from the second and the
7612 literal pool base from the third. */
7614 if (TARGET_BACKCHAIN)
7615 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7617 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7618 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7621 emit_move_insn (s390_back_chain_rtx (), temp);
7623 emit_insn (gen_rtx_USE (VOIDmode, base));
7627 (define_expand "exception_receiver"
7631 s390_set_has_landing_pad_p (true);
7636 ; nop instruction pattern(s).
7643 [(set_attr "op_type" "RR")])
7647 ; Special literal pool access instruction pattern(s).
7650 (define_insn "*pool_entry"
7651 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
7652 UNSPECV_POOL_ENTRY)]
7655 enum machine_mode mode = GET_MODE (PATTERN (insn));
7656 unsigned int align = GET_MODE_BITSIZE (mode);
7657 s390_output_pool_entry (operands[0], mode, align);
7660 [(set (attr "length")
7661 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
7663 (define_insn "pool_align"
7664 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
7665 UNSPECV_POOL_ALIGN)]
7668 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7670 (define_insn "pool_section_start"
7671 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
7674 [(set_attr "length" "0")])
7676 (define_insn "pool_section_end"
7677 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
7680 [(set_attr "length" "0")])
7682 (define_insn "main_base_31_small"
7683 [(set (match_operand 0 "register_operand" "=a")
7684 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7685 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7687 [(set_attr "op_type" "RR")
7688 (set_attr "type" "la")])
7690 (define_insn "main_base_31_large"
7691 [(set (match_operand 0 "register_operand" "=a")
7692 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
7693 (set (pc) (label_ref (match_operand 2 "" "")))]
7694 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7696 [(set_attr "op_type" "RI")])
7698 (define_insn "main_base_64"
7699 [(set (match_operand 0 "register_operand" "=a")
7700 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
7701 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7703 [(set_attr "op_type" "RIL")
7704 (set_attr "type" "larl")])
7706 (define_insn "main_pool"
7707 [(set (match_operand 0 "register_operand" "=a")
7708 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
7709 "GET_MODE (operands[0]) == Pmode"
7714 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
7715 (const_string "larl") (const_string "la")))])
7717 (define_insn "reload_base_31"
7718 [(set (match_operand 0 "register_operand" "=a")
7719 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7720 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7721 "basr\t%0,0\;la\t%0,%1-.(%0)"
7722 [(set_attr "length" "6")
7723 (set_attr "type" "la")])
7725 (define_insn "reload_base_64"
7726 [(set (match_operand 0 "register_operand" "=a")
7727 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
7728 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
7730 [(set_attr "op_type" "RIL")
7731 (set_attr "type" "larl")])
7734 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
7739 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
7742 ;; Insns related to generating the function prologue and epilogue.
7746 (define_expand "prologue"
7747 [(use (const_int 0))]
7749 "s390_emit_prologue (); DONE;")
7751 (define_expand "epilogue"
7752 [(use (const_int 1))]
7754 "s390_emit_epilogue (false); DONE;")
7756 (define_expand "sibcall_epilogue"
7757 [(use (const_int 0))]
7759 "s390_emit_epilogue (true); DONE;")
7761 (define_insn "*return"
7763 (use (match_operand 0 "register_operand" "a"))]
7764 "GET_MODE (operands[0]) == Pmode"
7766 [(set_attr "op_type" "RR")
7767 (set_attr "type" "jsr")
7768 (set_attr "atype" "agen")])
7771 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
7772 ;; pointer. This is used for compatibility.
7774 (define_expand "ptr_extend"
7775 [(set (match_operand:DI 0 "register_operand" "=r")
7776 (match_operand:SI 1 "register_operand" "r"))]
7779 emit_insn (gen_anddi3 (operands[0],
7780 gen_lowpart (DImode, operands[1]),
7781 GEN_INT (0x7fffffff)));
7785 ;; Instruction definition to expand eh_return macro to support
7786 ;; swapping in special linkage return addresses.
7788 (define_expand "eh_return"
7789 [(use (match_operand 0 "register_operand" ""))]
7792 s390_emit_tpf_eh_return (operands[0]);
7797 ; Stack Protector Patterns
7800 (define_expand "stack_protect_set"
7801 [(set (match_operand 0 "memory_operand" "")
7802 (match_operand 1 "memory_operand" ""))]
7805 #ifdef TARGET_THREAD_SSP_OFFSET
7807 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7808 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7811 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
7813 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
7818 (define_insn "stack_protect_set<mode>"
7819 [(set (match_operand:DSI 0 "memory_operand" "=Q")
7820 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))]
7822 "mvc\t%O0(%G0,%R0),%S1"
7823 [(set_attr "op_type" "SS")])
7825 (define_expand "stack_protect_test"
7826 [(set (reg:CC CC_REGNUM)
7827 (compare (match_operand 0 "memory_operand" "")
7828 (match_operand 1 "memory_operand" "")))
7829 (match_operand 2 "" "")]
7832 #ifdef TARGET_THREAD_SSP_OFFSET
7834 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (),
7835 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
7837 s390_compare_op0 = operands[0];
7838 s390_compare_op1 = operands[1];
7839 s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM);
7842 emit_insn (gen_stack_protect_testdi (operands[0], operands[1]));
7844 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
7846 emit_jump_insn (gen_beq (operands[2]));
7851 (define_insn "stack_protect_test<mode>"
7852 [(set (reg:CCZ CC_REGNUM)
7853 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q")
7854 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))]
7856 "clc\t%O0(%G0,%R0),%S1"
7857 [(set_attr "op_type" "SS")])