1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static HOST_WIDE_INT apparent_fsize;
71 static HOST_WIDE_INT actual_fsize;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83 bool sparc_emitting_epilogue;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 struct machine_function GTY(())
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name;
128 /* Name of where we pretend to think the frame pointer points.
129 Normally, this is "%fp", but if we are in a leaf procedure,
130 this is "%sp+something". We record "something" separately as it may be
131 too big for reg+constant addressing. */
133 static const char *frame_base_name;
134 static HOST_WIDE_INT frame_base_offset;
136 static void sparc_init_modes (void);
137 static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT);
138 static int restore_regs (FILE *, int, int, const char *, int, int);
139 static void build_big_number (FILE *, HOST_WIDE_INT, const char *);
140 static void scan_record_type (tree, int *, int *, int *);
141 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
142 tree, int, int, int *, int *);
144 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
145 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
147 static void sparc_output_addr_vec (rtx);
148 static void sparc_output_addr_diff_vec (rtx);
149 static void sparc_output_deferred_case_vectors (void);
150 static int check_return_regs (rtx);
151 static int epilogue_renumber (rtx *, int);
152 static bool sparc_assemble_integer (rtx, unsigned int, int);
153 static int set_extends (rtx);
154 static void output_restore_regs (FILE *, int);
155 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
156 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
157 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
158 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
159 static void sparc_flat_save_restore (FILE *, const char *, int,
160 unsigned long, unsigned long,
161 const char *, const char *,
163 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
164 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
165 #ifdef OBJECT_FORMAT_ELF
166 static void sparc_elf_asm_named_section (const char *, unsigned int);
168 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
170 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
171 unsigned HOST_WIDE_INT)
174 static int sparc_adjust_cost (rtx, rtx, rtx, int);
175 static int sparc_issue_rate (void);
176 static void sparc_sched_init (FILE *, int, int);
177 static int sparc_use_dfa_pipeline_interface (void);
178 static int sparc_use_sched_lookahead (void);
180 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
181 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
182 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
183 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
184 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
186 static bool sparc_function_ok_for_sibcall (tree, tree);
187 static void sparc_init_libfuncs (void);
188 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
189 HOST_WIDE_INT, tree);
190 static bool sparc_can_output_mi_thunk (tree, HOST_WIDE_INT,
191 HOST_WIDE_INT, tree);
192 static struct machine_function * sparc_init_machine_status (void);
193 static bool sparc_cannot_force_const_mem (rtx);
194 static rtx sparc_tls_get_addr (void);
195 static rtx sparc_tls_got (void);
196 static const char *get_some_local_dynamic_name (void);
197 static int get_some_local_dynamic_name_1 (rtx *, void *);
198 static bool sparc_rtx_costs (rtx, int, int, int *);
200 /* Option handling. */
202 /* Code model option as passed by user. */
203 const char *sparc_cmodel_string;
205 enum cmodel sparc_cmodel;
207 char sparc_hard_reg_printed[8];
209 struct sparc_cpu_select sparc_select[] =
211 /* switch name, tune arch */
212 { (char *)0, "default", 1, 1 },
213 { (char *)0, "-mcpu=", 1, 1 },
214 { (char *)0, "-mtune=", 1, 0 },
218 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
219 enum processor_type sparc_cpu;
221 /* Initialize the GCC target structure. */
223 /* The sparc default is to use .half rather than .short for aligned
224 HI objects. Use .word instead of .long on non-ELF systems. */
225 #undef TARGET_ASM_ALIGNED_HI_OP
226 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
227 #ifndef OBJECT_FORMAT_ELF
228 #undef TARGET_ASM_ALIGNED_SI_OP
229 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
232 #undef TARGET_ASM_UNALIGNED_HI_OP
233 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
234 #undef TARGET_ASM_UNALIGNED_SI_OP
235 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
236 #undef TARGET_ASM_UNALIGNED_DI_OP
237 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
239 /* The target hook has to handle DI-mode values. */
240 #undef TARGET_ASM_INTEGER
241 #define TARGET_ASM_INTEGER sparc_assemble_integer
243 #undef TARGET_ASM_FUNCTION_PROLOGUE
244 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
245 #undef TARGET_ASM_FUNCTION_EPILOGUE
246 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
248 #undef TARGET_SCHED_ADJUST_COST
249 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
250 #undef TARGET_SCHED_ISSUE_RATE
251 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
252 #undef TARGET_SCHED_INIT
253 #define TARGET_SCHED_INIT sparc_sched_init
254 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
255 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
256 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
257 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
259 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
260 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
262 #undef TARGET_INIT_LIBFUNCS
263 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
266 #undef TARGET_HAVE_TLS
267 #define TARGET_HAVE_TLS true
269 #undef TARGET_CANNOT_FORCE_CONST_MEM
270 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
272 #undef TARGET_ASM_OUTPUT_MI_THUNK
273 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
274 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
275 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
277 #undef TARGET_RTX_COSTS
278 #define TARGET_RTX_COSTS sparc_rtx_costs
279 #undef TARGET_ADDRESS_COST
280 #define TARGET_ADDRESS_COST hook_int_rtx_0
282 struct gcc_target targetm = TARGET_INITIALIZER;
284 /* Validate and override various options, and do some machine dependent
288 sparc_override_options (void)
290 static struct code_model {
291 const char *const name;
293 } const cmodels[] = {
295 { "medlow", CM_MEDLOW },
296 { "medmid", CM_MEDMID },
297 { "medany", CM_MEDANY },
298 { "embmedany", CM_EMBMEDANY },
301 const struct code_model *cmodel;
302 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
303 static struct cpu_default {
305 const char *const name;
306 } const cpu_default[] = {
307 /* There must be one entry here for each TARGET_CPU value. */
308 { TARGET_CPU_sparc, "cypress" },
309 { TARGET_CPU_sparclet, "tsc701" },
310 { TARGET_CPU_sparclite, "f930" },
311 { TARGET_CPU_v8, "v8" },
312 { TARGET_CPU_hypersparc, "hypersparc" },
313 { TARGET_CPU_sparclite86x, "sparclite86x" },
314 { TARGET_CPU_supersparc, "supersparc" },
315 { TARGET_CPU_v9, "v9" },
316 { TARGET_CPU_ultrasparc, "ultrasparc" },
317 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
320 const struct cpu_default *def;
321 /* Table of values for -m{cpu,tune}=. */
322 static struct cpu_table {
323 const char *const name;
324 const enum processor_type processor;
327 } const cpu_table[] = {
328 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
329 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
330 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
331 /* TI TMS390Z55 supersparc */
332 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
333 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
334 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
335 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
336 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
337 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
338 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
339 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
341 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
343 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
344 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
345 /* TI ultrasparc I, II, IIi */
346 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
347 /* Although insns using %y are deprecated, it is a clear win on current
349 |MASK_DEPRECATED_V8_INSNS},
350 /* TI ultrasparc III */
351 /* ??? Check if %y issue still holds true in ultra3. */
352 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
355 const struct cpu_table *cpu;
356 const struct sparc_cpu_select *sel;
359 #ifndef SPARC_BI_ARCH
360 /* Check for unsupported architecture size. */
361 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
362 error ("%s is not supported by this configuration",
363 DEFAULT_ARCH32_P ? "-m64" : "-m32");
366 /* We force all 64bit archs to use 128 bit long double */
367 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
369 error ("-mlong-double-64 not allowed with -m64");
370 target_flags |= MASK_LONG_DOUBLE_128;
373 /* Code model selection. */
374 sparc_cmodel = SPARC_DEFAULT_CMODEL;
378 sparc_cmodel = CM_32;
381 if (sparc_cmodel_string != NULL)
385 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
386 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
388 if (cmodel->name == NULL)
389 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
391 sparc_cmodel = cmodel->value;
394 error ("-mcmodel= is not supported on 32 bit systems");
397 fpu = TARGET_FPU; /* save current -mfpu status */
399 /* Set the default CPU. */
400 for (def = &cpu_default[0]; def->name; ++def)
401 if (def->cpu == TARGET_CPU_DEFAULT)
405 sparc_select[0].string = def->name;
407 for (sel = &sparc_select[0]; sel->name; ++sel)
411 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
412 if (! strcmp (sel->string, cpu->name))
415 sparc_cpu = cpu->processor;
419 target_flags &= ~cpu->disable;
420 target_flags |= cpu->enable;
426 error ("bad value (%s) for %s switch", sel->string, sel->name);
430 /* If -mfpu or -mno-fpu was explicitly used, don't override with
431 the processor default. Clear MASK_FPU_SET to avoid confusing
432 the reverse mapping from switch values to names. */
435 target_flags = (target_flags & ~MASK_FPU) | fpu;
436 target_flags &= ~MASK_FPU_SET;
439 /* Don't allow -mvis if FPU is disabled. */
441 target_flags &= ~MASK_VIS;
443 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
445 -m64 also implies v9. */
446 if (TARGET_VIS || TARGET_ARCH64)
448 target_flags |= MASK_V9;
449 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
452 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
453 if (TARGET_V9 && TARGET_ARCH32)
454 target_flags |= MASK_DEPRECATED_V8_INSNS;
456 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
457 if (! TARGET_V9 || TARGET_ARCH64)
458 target_flags &= ~MASK_V8PLUS;
460 /* Don't use stack biasing in 32 bit mode. */
462 target_flags &= ~MASK_STACK_BIAS;
464 /* Supply a default value for align_functions. */
465 if (align_functions == 0
466 && (sparc_cpu == PROCESSOR_ULTRASPARC
467 || sparc_cpu == PROCESSOR_ULTRASPARC3))
468 align_functions = 32;
470 /* Validate PCC_STRUCT_RETURN. */
471 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
472 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
474 /* Only use .uaxword when compiling for a 64-bit target. */
476 targetm.asm_out.unaligned_op.di = NULL;
478 /* Do various machine dependent initializations. */
481 /* Set up function hooks. */
482 init_machine_status = sparc_init_machine_status;
485 /* Miscellaneous utilities. */
487 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
488 or branch on register contents instructions. */
491 v9_regcmp_p (enum rtx_code code)
493 return (code == EQ || code == NE || code == GE || code == LT
494 || code == LE || code == GT);
498 /* Operand constraints. */
500 /* Return nonzero only if OP is a register of mode MODE,
504 reg_or_0_operand (rtx op, enum machine_mode mode)
506 if (register_operand (op, mode))
508 if (op == const0_rtx)
510 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
511 && CONST_DOUBLE_HIGH (op) == 0
512 && CONST_DOUBLE_LOW (op) == 0)
514 if (fp_zero_operand (op, mode))
519 /* Return nonzero only if OP is const1_rtx. */
522 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
524 return op == const1_rtx;
527 /* Nonzero if OP is a floating point value with value 0.0. */
530 fp_zero_operand (rtx op, enum machine_mode mode)
532 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
534 return op == CONST0_RTX (mode);
537 /* Nonzero if OP is a register operand in floating point register. */
540 fp_register_operand (rtx op, enum machine_mode mode)
542 if (! register_operand (op, mode))
544 if (GET_CODE (op) == SUBREG)
545 op = SUBREG_REG (op);
546 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
549 /* Nonzero if OP is a floating point constant which can
550 be loaded into an integer register using a single
551 sethi instruction. */
556 if (GET_CODE (op) == CONST_DOUBLE)
561 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
562 if (REAL_VALUES_EQUAL (r, dconst0) &&
563 ! REAL_VALUE_MINUS_ZERO (r))
565 REAL_VALUE_TO_TARGET_SINGLE (r, i);
566 if (SPARC_SETHI_P (i))
573 /* Nonzero if OP is a floating point constant which can
574 be loaded into an integer register using a single
580 if (GET_CODE (op) == CONST_DOUBLE)
585 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
586 if (REAL_VALUES_EQUAL (r, dconst0) &&
587 ! REAL_VALUE_MINUS_ZERO (r))
589 REAL_VALUE_TO_TARGET_SINGLE (r, i);
590 if (SPARC_SIMM13_P (i))
597 /* Nonzero if OP is a floating point constant which can
598 be loaded into an integer register using a high/losum
599 instruction sequence. */
602 fp_high_losum_p (rtx op)
604 /* The constraints calling this should only be in
605 SFmode move insns, so any constant which cannot
606 be moved using a single insn will do. */
607 if (GET_CODE (op) == CONST_DOUBLE)
612 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
613 if (REAL_VALUES_EQUAL (r, dconst0) &&
614 ! REAL_VALUE_MINUS_ZERO (r))
616 REAL_VALUE_TO_TARGET_SINGLE (r, i);
617 if (! SPARC_SETHI_P (i)
618 && ! SPARC_SIMM13_P (i))
625 /* Nonzero if OP is an integer register. */
628 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
630 return (register_operand (op, SImode)
631 || (TARGET_ARCH64 && register_operand (op, DImode)));
634 /* Nonzero if OP is a floating point condition code register. */
637 fcc_reg_operand (rtx op, enum machine_mode mode)
639 /* This can happen when recog is called from combine. Op may be a MEM.
640 Fail instead of calling abort in this case. */
641 if (GET_CODE (op) != REG)
644 if (mode != VOIDmode && mode != GET_MODE (op))
647 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
650 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
651 if (reg_renumber == 0)
652 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
653 return REGNO_OK_FOR_CCFP_P (REGNO (op));
655 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
659 /* Nonzero if OP is a floating point condition code fcc0 register. */
662 fcc0_reg_operand (rtx op, enum machine_mode mode)
664 /* This can happen when recog is called from combine. Op may be a MEM.
665 Fail instead of calling abort in this case. */
666 if (GET_CODE (op) != REG)
669 if (mode != VOIDmode && mode != GET_MODE (op))
672 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
675 return REGNO (op) == SPARC_FCC_REG;
678 /* Nonzero if OP is an integer or floating point condition code register. */
681 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
683 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
685 if (mode != VOIDmode && mode != GET_MODE (op))
688 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
693 return fcc_reg_operand (op, mode);
696 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
698 restore_operand (rtx op, enum machine_mode mode)
700 return (GET_CODE (op) == REG && GET_MODE (op) == mode
701 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
704 /* Call insn on SPARC can take a PC-relative constant address, or any regular
708 call_operand (rtx op, enum machine_mode mode)
710 if (GET_CODE (op) != MEM)
713 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
717 call_operand_address (rtx op, enum machine_mode mode)
719 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
722 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
723 otherwise return 0. */
726 tls_symbolic_operand (rtx op)
728 if (GET_CODE (op) != SYMBOL_REF)
730 return SYMBOL_REF_TLS_MODEL (op);
734 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
736 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
740 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
742 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
746 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
748 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
752 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
754 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
757 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
758 reference and a constant. */
761 symbolic_operand (register rtx op, enum machine_mode mode)
763 enum machine_mode omode = GET_MODE (op);
765 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
768 switch (GET_CODE (op))
771 return !SYMBOL_REF_TLS_MODEL (op);
778 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
779 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
780 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
781 && GET_CODE (XEXP (op, 1)) == CONST_INT);
788 /* Return truth value of statement that OP is a symbolic memory
789 operand of mode MODE. */
792 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
794 if (GET_CODE (op) == SUBREG)
795 op = SUBREG_REG (op);
796 if (GET_CODE (op) != MEM)
799 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
800 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
801 || GET_CODE (op) == LABEL_REF);
804 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
807 label_ref_operand (rtx op, enum machine_mode mode)
809 if (GET_CODE (op) != LABEL_REF)
811 if (GET_MODE (op) != mode)
816 /* Return 1 if the operand is an argument used in generating pic references
817 in either the medium/low or medium/anywhere code models of sparc64. */
820 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
822 /* Check for (const (minus (symbol_ref:GOT)
823 (const (minus (label) (pc))))). */
824 if (GET_CODE (op) != CONST)
827 if (GET_CODE (op) != MINUS)
829 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
831 /* ??? Ensure symbol is GOT. */
832 if (GET_CODE (XEXP (op, 1)) != CONST)
834 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
839 /* Return 1 if the operand is a data segment reference. This includes
840 the readonly data segment, or in other words anything but the text segment.
841 This is needed in the medium/anywhere code model on v9. These values
842 are accessed with EMBMEDANY_BASE_REG. */
845 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
847 switch (GET_CODE (op))
850 return ! SYMBOL_REF_FUNCTION_P (op);
852 /* Assume canonical format of symbol + constant.
855 return data_segment_operand (XEXP (op, 0), VOIDmode);
861 /* Return 1 if the operand is a text segment reference.
862 This is needed in the medium/anywhere code model on v9. */
865 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
867 switch (GET_CODE (op))
872 return SYMBOL_REF_FUNCTION_P (op);
874 /* Assume canonical format of symbol + constant.
877 return text_segment_operand (XEXP (op, 0), VOIDmode);
883 /* Return 1 if the operand is either a register or a memory operand that is
887 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
889 if (register_operand (op, mode))
892 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
899 splittable_symbolic_memory_operand (rtx op,
900 enum machine_mode mode ATTRIBUTE_UNUSED)
902 if (GET_CODE (op) != MEM)
904 if (! symbolic_operand (XEXP (op, 0), Pmode))
910 splittable_immediate_memory_operand (rtx op,
911 enum machine_mode mode ATTRIBUTE_UNUSED)
913 if (GET_CODE (op) != MEM)
915 if (! immediate_operand (XEXP (op, 0), Pmode))
920 /* Return truth value of whether OP is EQ or NE. */
923 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
925 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
928 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
929 or LTU for non-floating-point. We handle those specially. */
932 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
934 enum rtx_code code = GET_CODE (op);
936 if (GET_RTX_CLASS (code) != '<')
939 if (GET_MODE (XEXP (op, 0)) == CCFPmode
940 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
943 return (code != NE && code != EQ && code != GEU && code != LTU);
946 /* Return 1 if this is a comparison operator. This allows the use of
947 MATCH_OPERATOR to recognize all the branch insns. */
950 noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
952 enum rtx_code code = GET_CODE (op);
954 if (GET_RTX_CLASS (code) != '<')
957 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
958 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
959 /* These are the only branches which work with CC_NOOVmode. */
960 return (code == EQ || code == NE || code == GE || code == LT);
964 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
965 MATCH_OPERATOR to recognize all the branch insns. */
968 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
970 enum rtx_code code = GET_CODE (op);
975 if (GET_RTX_CLASS (code) != '<')
978 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
979 /* These are the only branches which work with CCX_NOOVmode. */
980 return (code == EQ || code == NE || code == GE || code == LT);
981 return (GET_MODE (XEXP (op, 0)) == CCXmode);
984 /* Nonzero if OP is a comparison operator suitable for use in v9
985 conditional move or branch on register contents instructions. */
988 v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
990 enum rtx_code code = GET_CODE (op);
992 if (GET_RTX_CLASS (code) != '<')
995 return v9_regcmp_p (code);
998 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1001 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1003 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1006 /* Return nonzero if OP is an operator of mode MODE which can set
1007 the condition codes explicitly. We do not include PLUS and MINUS
1008 because these require CC_NOOVmode, which we handle explicitly. */
1011 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1013 if (GET_CODE (op) == AND
1014 || GET_CODE (op) == IOR
1015 || GET_CODE (op) == XOR)
1021 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1022 complement its second operand and set the condition codes explicitly. */
1025 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1027 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1028 and (xor ... (not ...)) to (not (xor ...)). */
1029 return (GET_CODE (op) == AND
1030 || GET_CODE (op) == IOR);
1033 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1034 signed 13 bit immediate field. This is an acceptable SImode operand for
1035 most 3 address instructions. */
1038 arith_operand (rtx op, enum machine_mode mode)
1040 if (register_operand (op, mode))
1042 if (GET_CODE (op) != CONST_INT)
1044 return SMALL_INT32 (op);
1047 /* Return true if OP is a constant 4096 */
1050 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1052 if (GET_CODE (op) != CONST_INT)
1055 return INTVAL (op) == 4096;
1058 /* Return true if OP is suitable as second operand for add/sub */
1061 arith_add_operand (rtx op, enum machine_mode mode)
1063 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1066 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1067 immediate field of OR and XOR instructions. Used for 64-bit
1068 constant formation patterns. */
1070 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1072 return ((GET_CODE (op) == CONST_INT
1073 && SPARC_SIMM13_P (INTVAL (op)))
1074 #if HOST_BITS_PER_WIDE_INT != 64
1075 || (GET_CODE (op) == CONST_DOUBLE
1076 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1077 && (CONST_DOUBLE_HIGH (op) ==
1078 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1079 (HOST_WIDE_INT)-1 : 0)))
1084 /* The same, but only for sethi instructions. */
1086 const64_high_operand (rtx op, enum machine_mode mode)
1088 return ((GET_CODE (op) == CONST_INT
1089 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1090 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1092 || (GET_CODE (op) == CONST_DOUBLE
1093 && CONST_DOUBLE_HIGH (op) == 0
1094 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1095 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1098 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1099 signed 11 bit immediate field. This is an acceptable SImode operand for
1100 the movcc instructions. */
1103 arith11_operand (rtx op, enum machine_mode mode)
1105 return (register_operand (op, mode)
1106 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1109 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1110 signed 10 bit immediate field. This is an acceptable SImode operand for
1111 the movrcc instructions. */
1114 arith10_operand (rtx op, enum machine_mode mode)
1116 return (register_operand (op, mode)
1117 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1120 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1121 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1123 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1124 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1125 for most 3 address instructions. */
1128 arith_double_operand (rtx op, enum machine_mode mode)
1130 return (register_operand (op, mode)
1131 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1133 && GET_CODE (op) == CONST_DOUBLE
1134 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1135 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1137 && GET_CODE (op) == CONST_DOUBLE
1138 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1139 && ((CONST_DOUBLE_HIGH (op) == -1
1140 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1141 || (CONST_DOUBLE_HIGH (op) == 0
1142 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1145 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1148 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1150 return (TARGET_ARCH64 &&
1151 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1152 (GET_CODE (op) == CONST_DOUBLE &&
1153 CONST_DOUBLE_LOW (op) == 4096 &&
1154 CONST_DOUBLE_HIGH (op) == 0)));
1157 /* Return true if OP is suitable as second operand for add/sub in DImode */
1160 arith_double_add_operand (rtx op, enum machine_mode mode)
1162 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1165 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1166 can fit in an 11 bit immediate field. This is an acceptable DImode
1167 operand for the movcc instructions. */
1168 /* ??? Replace with arith11_operand? */
1171 arith11_double_operand (rtx op, enum machine_mode mode)
1173 return (register_operand (op, mode)
1174 || (GET_CODE (op) == CONST_DOUBLE
1175 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1176 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1177 && ((CONST_DOUBLE_HIGH (op) == -1
1178 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1179 || (CONST_DOUBLE_HIGH (op) == 0
1180 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1181 || (GET_CODE (op) == CONST_INT
1182 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1183 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1186 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1187 can fit in an 10 bit immediate field. This is an acceptable DImode
1188 operand for the movrcc instructions. */
1189 /* ??? Replace with arith10_operand? */
1192 arith10_double_operand (rtx op, enum machine_mode mode)
1194 return (register_operand (op, mode)
1195 || (GET_CODE (op) == CONST_DOUBLE
1196 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1197 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1198 && ((CONST_DOUBLE_HIGH (op) == -1
1199 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1200 || (CONST_DOUBLE_HIGH (op) == 0
1201 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1202 || (GET_CODE (op) == CONST_INT
1203 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1204 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1207 /* Return truth value of whether OP is an integer which fits the
1208 range constraining immediate operands in most three-address insns,
1209 which have a 13 bit immediate field. */
1212 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1214 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1218 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1220 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1221 || (GET_CODE (op) == CONST_DOUBLE
1222 && CONST_DOUBLE_HIGH (op) == 0
1223 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1226 /* Recognize operand values for the umul instruction. That instruction sign
1227 extends immediate values just like all other sparc instructions, but
1228 interprets the extended result as an unsigned number. */
1231 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1233 #if HOST_BITS_PER_WIDE_INT > 32
1234 /* All allowed constants will fit a CONST_INT. */
1235 return (GET_CODE (op) == CONST_INT
1236 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1237 || (INTVAL (op) >= 0xFFFFF000
1238 && INTVAL (op) <= 0xFFFFFFFF)));
1240 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1241 || (GET_CODE (op) == CONST_DOUBLE
1242 && CONST_DOUBLE_HIGH (op) == 0
1243 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1248 uns_arith_operand (rtx op, enum machine_mode mode)
1250 return register_operand (op, mode) || uns_small_int (op, mode);
1253 /* Return truth value of statement that OP is a call-clobbered register. */
1255 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1257 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1260 /* Return 1 if OP is a valid operand for the source of a move insn. */
1263 input_operand (rtx op, enum machine_mode mode)
1265 /* If both modes are non-void they must be the same. */
1266 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1269 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1270 if (GET_CODE (op) == CONSTANT_P_RTX)
1273 /* Allow any one instruction integer constant, and all CONST_INT
1274 variants when we are working in DImode and !arch64. */
1275 if (GET_MODE_CLASS (mode) == MODE_INT
1276 && ((GET_CODE (op) == CONST_INT
1277 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1278 || SPARC_SIMM13_P (INTVAL (op))
1280 && ! TARGET_ARCH64)))
1282 && GET_CODE (op) == CONST_DOUBLE
1283 && ((CONST_DOUBLE_HIGH (op) == 0
1284 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1286 #if HOST_BITS_PER_WIDE_INT == 64
1287 (CONST_DOUBLE_HIGH (op) == 0
1288 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1290 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1291 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1292 && CONST_DOUBLE_HIGH (op) == 0)
1293 || (CONST_DOUBLE_HIGH (op) == -1
1294 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1299 /* If !arch64 and this is a DImode const, allow it so that
1300 the splits can be generated. */
1303 && GET_CODE (op) == CONST_DOUBLE)
1306 if (register_operand (op, mode))
1309 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1310 && GET_CODE (op) == CONST_DOUBLE)
1313 /* If this is a SUBREG, look inside so that we handle
1314 paradoxical ones. */
1315 if (GET_CODE (op) == SUBREG)
1316 op = SUBREG_REG (op);
1318 /* Check for valid MEM forms. */
1319 if (GET_CODE (op) == MEM)
1320 return memory_address_p (mode, XEXP (op, 0));
1325 /* Return 1 if OP is valid for the lhs of a compare insn. */
1328 compare_operand (rtx op, enum machine_mode mode)
1330 if (GET_CODE (op) == ZERO_EXTRACT)
1331 return (register_operand (XEXP (op, 0), mode)
1332 && small_int_or_double (XEXP (op, 1), mode)
1333 && small_int_or_double (XEXP (op, 2), mode)
1334 /* This matches cmp_zero_extract. */
1336 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1337 && INTVAL (XEXP (op, 2)) > 19)
1338 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1339 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1340 /* This matches cmp_zero_extract_sp64. */
1343 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1344 && INTVAL (XEXP (op, 2)) > 51)
1345 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1346 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1348 return register_operand (op, mode);
1352 /* We know it can't be done in one insn when we get here,
1353 the movsi expander guarantees this. */
1355 sparc_emit_set_const32 (rtx op0, rtx op1)
1357 enum machine_mode mode = GET_MODE (op0);
1360 if (GET_CODE (op1) == CONST_INT)
1362 HOST_WIDE_INT value = INTVAL (op1);
1364 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1365 || SPARC_SIMM13_P (value))
1369 /* Full 2-insn decomposition is needed. */
1370 if (reload_in_progress || reload_completed)
1373 temp = gen_reg_rtx (mode);
1375 if (GET_CODE (op1) == CONST_INT)
1377 /* Emit them as real moves instead of a HIGH/LO_SUM,
1378 this way CSE can see everything and reuse intermediate
1379 values if it wants. */
1381 && HOST_BITS_PER_WIDE_INT != 64
1382 && (INTVAL (op1) & 0x80000000) != 0)
1383 emit_insn (gen_rtx_SET
1385 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1388 emit_insn (gen_rtx_SET (VOIDmode, temp,
1389 GEN_INT (INTVAL (op1)
1390 & ~(HOST_WIDE_INT)0x3ff)));
1392 emit_insn (gen_rtx_SET (VOIDmode,
1394 gen_rtx_IOR (mode, temp,
1395 GEN_INT (INTVAL (op1) & 0x3ff))));
1399 /* A symbol, emit in the traditional way. */
1400 emit_insn (gen_rtx_SET (VOIDmode, temp,
1401 gen_rtx_HIGH (mode, op1)));
1402 emit_insn (gen_rtx_SET (VOIDmode,
1403 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1409 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1410 If TEMP is non-zero, we are forbidden to use any other scratch
1411 registers. Otherwise, we are allowed to generate them as needed.
1413 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1414 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1416 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1418 rtx temp1, temp2, temp3, temp4, temp5;
1421 if (temp && GET_MODE (temp) == TImode)
1424 temp = gen_rtx_REG (DImode, REGNO (temp));
1427 /* SPARC-V9 code-model support. */
1428 switch (sparc_cmodel)
1431 /* The range spanned by all instructions in the object is less
1432 than 2^31 bytes (2GB) and the distance from any instruction
1433 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1434 than 2^31 bytes (2GB).
1436 The executable must be in the low 4TB of the virtual address
1439 sethi %hi(symbol), %temp1
1440 or %temp1, %lo(symbol), %reg */
1442 temp1 = temp; /* op0 is allowed. */
1444 temp1 = gen_reg_rtx (DImode);
1446 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1447 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1451 /* The range spanned by all instructions in the object is less
1452 than 2^31 bytes (2GB) and the distance from any instruction
1453 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1454 than 2^31 bytes (2GB).
1456 The executable must be in the low 16TB of the virtual address
1459 sethi %h44(symbol), %temp1
1460 or %temp1, %m44(symbol), %temp2
1461 sllx %temp2, 12, %temp3
1462 or %temp3, %l44(symbol), %reg */
1467 temp3 = temp; /* op0 is allowed. */
1471 temp1 = gen_reg_rtx (DImode);
1472 temp2 = gen_reg_rtx (DImode);
1473 temp3 = gen_reg_rtx (DImode);
1476 emit_insn (gen_seth44 (temp1, op1));
1477 emit_insn (gen_setm44 (temp2, temp1, op1));
1478 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1479 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1480 emit_insn (gen_setl44 (op0, temp3, op1));
1484 /* The range spanned by all instructions in the object is less
1485 than 2^31 bytes (2GB) and the distance from any instruction
1486 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1487 than 2^31 bytes (2GB).
1489 The executable can be placed anywhere in the virtual address
1492 sethi %hh(symbol), %temp1
1493 sethi %lm(symbol), %temp2
1494 or %temp1, %hm(symbol), %temp3
1495 sllx %temp3, 32, %temp4
1496 or %temp4, %temp2, %temp5
1497 or %temp5, %lo(symbol), %reg */
1500 /* It is possible that one of the registers we got for operands[2]
1501 might coincide with that of operands[0] (which is why we made
1502 it TImode). Pick the other one to use as our scratch. */
1503 if (rtx_equal_p (temp, op0))
1506 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1511 temp2 = temp; /* op0 is _not_ allowed, see above. */
1518 temp1 = gen_reg_rtx (DImode);
1519 temp2 = gen_reg_rtx (DImode);
1520 temp3 = gen_reg_rtx (DImode);
1521 temp4 = gen_reg_rtx (DImode);
1522 temp5 = gen_reg_rtx (DImode);
1525 emit_insn (gen_sethh (temp1, op1));
1526 emit_insn (gen_setlm (temp2, op1));
1527 emit_insn (gen_sethm (temp3, temp1, op1));
1528 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1529 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1530 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1531 gen_rtx_PLUS (DImode, temp4, temp2)));
1532 emit_insn (gen_setlo (op0, temp5, op1));
1536 /* Old old old backwards compatibility kruft here.
1537 Essentially it is MEDLOW with a fixed 64-bit
1538 virtual base added to all data segment addresses.
1539 Text-segment stuff is computed like MEDANY, we can't
1540 reuse the code above because the relocation knobs
1543 Data segment: sethi %hi(symbol), %temp1
1544 add %temp1, EMBMEDANY_BASE_REG, %temp2
1545 or %temp2, %lo(symbol), %reg */
1546 if (data_segment_operand (op1, GET_MODE (op1)))
1550 temp1 = temp; /* op0 is allowed. */
1555 temp1 = gen_reg_rtx (DImode);
1556 temp2 = gen_reg_rtx (DImode);
1559 emit_insn (gen_embmedany_sethi (temp1, op1));
1560 emit_insn (gen_embmedany_brsum (temp2, temp1));
1561 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1564 /* Text segment: sethi %uhi(symbol), %temp1
1565 sethi %hi(symbol), %temp2
1566 or %temp1, %ulo(symbol), %temp3
1567 sllx %temp3, 32, %temp4
1568 or %temp4, %temp2, %temp5
1569 or %temp5, %lo(symbol), %reg */
1574 /* It is possible that one of the registers we got for operands[2]
1575 might coincide with that of operands[0] (which is why we made
1576 it TImode). Pick the other one to use as our scratch. */
1577 if (rtx_equal_p (temp, op0))
1580 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1585 temp2 = temp; /* op0 is _not_ allowed, see above. */
1592 temp1 = gen_reg_rtx (DImode);
1593 temp2 = gen_reg_rtx (DImode);
1594 temp3 = gen_reg_rtx (DImode);
1595 temp4 = gen_reg_rtx (DImode);
1596 temp5 = gen_reg_rtx (DImode);
1599 emit_insn (gen_embmedany_textuhi (temp1, op1));
1600 emit_insn (gen_embmedany_texthi (temp2, op1));
1601 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1602 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1603 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1604 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1605 gen_rtx_PLUS (DImode, temp4, temp2)));
1606 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1615 /* These avoid problems when cross compiling. If we do not
1616 go through all this hair then the optimizer will see
1617 invalid REG_EQUAL notes or in some cases none at all. */
1618 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1619 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1620 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1621 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1623 #if HOST_BITS_PER_WIDE_INT == 64
1624 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1625 #define GEN_INT64(__x) GEN_INT (__x)
1627 #define GEN_HIGHINT64(__x) \
1628 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1629 #define GEN_INT64(__x) \
1630 immed_double_const ((__x) & 0xffffffff, \
1631 ((__x) & 0x80000000 ? -1 : 0), DImode)
1634 /* The optimizer is not to assume anything about exactly
1635 which bits are set for a HIGH, they are unspecified.
1636 Unfortunately this leads to many missed optimizations
1637 during CSE. We mask out the non-HIGH bits, and matches
1638 a plain movdi, to alleviate this problem. */
1640 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1642 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1646 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1648 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1652 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1654 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1658 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1660 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1663 /* Worker routines for 64-bit constant formation on arch64.
1664 One of the key things to be doing in these emissions is
1665 to create as many temp REGs as possible. This makes it
1666 possible for half-built constants to be used later when
1667 such values are similar to something required later on.
1668 Without doing this, the optimizer cannot see such
1671 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1672 unsigned HOST_WIDE_INT, int);
1675 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1676 unsigned HOST_WIDE_INT low_bits, int is_neg)
1678 unsigned HOST_WIDE_INT high_bits;
1681 high_bits = (~low_bits) & 0xffffffff;
1683 high_bits = low_bits;
1685 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1688 emit_insn (gen_rtx_SET (VOIDmode, op0,
1689 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1693 /* If we are XOR'ing with -1, then we should emit a one's complement
1694 instead. This way the combiner will notice logical operations
1695 such as ANDN later on and substitute. */
1696 if ((low_bits & 0x3ff) == 0x3ff)
1698 emit_insn (gen_rtx_SET (VOIDmode, op0,
1699 gen_rtx_NOT (DImode, temp)));
1703 emit_insn (gen_rtx_SET (VOIDmode, op0,
1704 gen_safe_XOR64 (temp,
1705 (-(HOST_WIDE_INT)0x400
1706 | (low_bits & 0x3ff)))));
1711 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1712 unsigned HOST_WIDE_INT, int);
1715 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1716 unsigned HOST_WIDE_INT high_bits,
1717 unsigned HOST_WIDE_INT low_immediate,
1722 if ((high_bits & 0xfffffc00) != 0)
1724 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1725 if ((high_bits & ~0xfffffc00) != 0)
1726 emit_insn (gen_rtx_SET (VOIDmode, op0,
1727 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1733 emit_insn (gen_safe_SET64 (temp, high_bits));
1737 /* Now shift it up into place. */
1738 emit_insn (gen_rtx_SET (VOIDmode, op0,
1739 gen_rtx_ASHIFT (DImode, temp2,
1740 GEN_INT (shift_count))));
1742 /* If there is a low immediate part piece, finish up by
1743 putting that in as well. */
1744 if (low_immediate != 0)
1745 emit_insn (gen_rtx_SET (VOIDmode, op0,
1746 gen_safe_OR64 (op0, low_immediate)));
1749 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1750 unsigned HOST_WIDE_INT);
1752 /* Full 64-bit constant decomposition. Even though this is the
1753 'worst' case, we still optimize a few things away. */
1755 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1756 unsigned HOST_WIDE_INT high_bits,
1757 unsigned HOST_WIDE_INT low_bits)
1761 if (reload_in_progress || reload_completed)
1764 sub_temp = gen_reg_rtx (DImode);
1766 if ((high_bits & 0xfffffc00) != 0)
1768 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1769 if ((high_bits & ~0xfffffc00) != 0)
1770 emit_insn (gen_rtx_SET (VOIDmode,
1772 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1778 emit_insn (gen_safe_SET64 (temp, high_bits));
1782 if (!reload_in_progress && !reload_completed)
1784 rtx temp2 = gen_reg_rtx (DImode);
1785 rtx temp3 = gen_reg_rtx (DImode);
1786 rtx temp4 = gen_reg_rtx (DImode);
1788 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1789 gen_rtx_ASHIFT (DImode, sub_temp,
1792 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1793 if ((low_bits & ~0xfffffc00) != 0)
1795 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1796 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1797 emit_insn (gen_rtx_SET (VOIDmode, op0,
1798 gen_rtx_PLUS (DImode, temp4, temp3)));
1802 emit_insn (gen_rtx_SET (VOIDmode, op0,
1803 gen_rtx_PLUS (DImode, temp4, temp2)));
1808 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1809 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1810 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1813 /* We are in the middle of reload, so this is really
1814 painful. However we do still make an attempt to
1815 avoid emitting truly stupid code. */
1816 if (low1 != const0_rtx)
1818 emit_insn (gen_rtx_SET (VOIDmode, op0,
1819 gen_rtx_ASHIFT (DImode, sub_temp,
1820 GEN_INT (to_shift))));
1821 emit_insn (gen_rtx_SET (VOIDmode, op0,
1822 gen_rtx_IOR (DImode, op0, low1)));
1830 if (low2 != const0_rtx)
1832 emit_insn (gen_rtx_SET (VOIDmode, op0,
1833 gen_rtx_ASHIFT (DImode, sub_temp,
1834 GEN_INT (to_shift))));
1835 emit_insn (gen_rtx_SET (VOIDmode, op0,
1836 gen_rtx_IOR (DImode, op0, low2)));
1844 emit_insn (gen_rtx_SET (VOIDmode, op0,
1845 gen_rtx_ASHIFT (DImode, sub_temp,
1846 GEN_INT (to_shift))));
1847 if (low3 != const0_rtx)
1848 emit_insn (gen_rtx_SET (VOIDmode, op0,
1849 gen_rtx_IOR (DImode, op0, low3)));
1854 /* Analyze a 64-bit constant for certain properties. */
1855 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1856 unsigned HOST_WIDE_INT,
1857 int *, int *, int *);
1860 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1861 unsigned HOST_WIDE_INT low_bits,
1862 int *hbsp, int *lbsp, int *abbasp)
1864 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1867 lowest_bit_set = highest_bit_set = -1;
1871 if ((lowest_bit_set == -1)
1872 && ((low_bits >> i) & 1))
1874 if ((highest_bit_set == -1)
1875 && ((high_bits >> (32 - i - 1)) & 1))
1876 highest_bit_set = (64 - i - 1);
1879 && ((highest_bit_set == -1)
1880 || (lowest_bit_set == -1)));
1886 if ((lowest_bit_set == -1)
1887 && ((high_bits >> i) & 1))
1888 lowest_bit_set = i + 32;
1889 if ((highest_bit_set == -1)
1890 && ((low_bits >> (32 - i - 1)) & 1))
1891 highest_bit_set = 32 - i - 1;
1894 && ((highest_bit_set == -1)
1895 || (lowest_bit_set == -1)));
1897 /* If there are no bits set this should have gone out
1898 as one instruction! */
1899 if (lowest_bit_set == -1
1900 || highest_bit_set == -1)
1902 all_bits_between_are_set = 1;
1903 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1907 if ((low_bits & (1 << i)) != 0)
1912 if ((high_bits & (1 << (i - 32))) != 0)
1915 all_bits_between_are_set = 0;
1918 *hbsp = highest_bit_set;
1919 *lbsp = lowest_bit_set;
1920 *abbasp = all_bits_between_are_set;
1923 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1926 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1927 unsigned HOST_WIDE_INT low_bits)
1929 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1932 || high_bits == 0xffffffff)
1935 analyze_64bit_constant (high_bits, low_bits,
1936 &highest_bit_set, &lowest_bit_set,
1937 &all_bits_between_are_set);
1939 if ((highest_bit_set == 63
1940 || lowest_bit_set == 0)
1941 && all_bits_between_are_set != 0)
1944 if ((highest_bit_set - lowest_bit_set) < 21)
1950 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1951 unsigned HOST_WIDE_INT,
1954 static unsigned HOST_WIDE_INT
1955 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1956 unsigned HOST_WIDE_INT low_bits,
1957 int lowest_bit_set, int shift)
1959 HOST_WIDE_INT hi, lo;
1961 if (lowest_bit_set < 32)
1963 lo = (low_bits >> lowest_bit_set) << shift;
1964 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1969 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1976 /* Here we are sure to be arch64 and this is an integer constant
1977 being loaded into a register. Emit the most efficient
1978 insn sequence possible. Detection of all the 1-insn cases
1979 has been done already. */
1981 sparc_emit_set_const64 (rtx op0, rtx op1)
1983 unsigned HOST_WIDE_INT high_bits, low_bits;
1984 int lowest_bit_set, highest_bit_set;
1985 int all_bits_between_are_set;
1988 /* Sanity check that we know what we are working with. */
1989 if (! TARGET_ARCH64)
1992 if (GET_CODE (op0) != SUBREG)
1994 if (GET_CODE (op0) != REG
1995 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1996 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2000 if (reload_in_progress || reload_completed)
2003 if (GET_CODE (op1) != CONST_DOUBLE
2004 && GET_CODE (op1) != CONST_INT)
2006 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2011 temp = gen_reg_rtx (DImode);
2013 if (GET_CODE (op1) == CONST_DOUBLE)
2015 #if HOST_BITS_PER_WIDE_INT == 64
2016 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2017 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2019 high_bits = CONST_DOUBLE_HIGH (op1);
2020 low_bits = CONST_DOUBLE_LOW (op1);
2025 #if HOST_BITS_PER_WIDE_INT == 64
2026 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2027 low_bits = (INTVAL (op1) & 0xffffffff);
2029 high_bits = ((INTVAL (op1) < 0) ?
2032 low_bits = INTVAL (op1);
2036 /* low_bits bits 0 --> 31
2037 high_bits bits 32 --> 63 */
2039 analyze_64bit_constant (high_bits, low_bits,
2040 &highest_bit_set, &lowest_bit_set,
2041 &all_bits_between_are_set);
2043 /* First try for a 2-insn sequence. */
2045 /* These situations are preferred because the optimizer can
2046 * do more things with them:
2048 * sllx %reg, shift, %reg
2050 * srlx %reg, shift, %reg
2051 * 3) mov some_small_const, %reg
2052 * sllx %reg, shift, %reg
2054 if (((highest_bit_set == 63
2055 || lowest_bit_set == 0)
2056 && all_bits_between_are_set != 0)
2057 || ((highest_bit_set - lowest_bit_set) < 12))
2059 HOST_WIDE_INT the_const = -1;
2060 int shift = lowest_bit_set;
2062 if ((highest_bit_set != 63
2063 && lowest_bit_set != 0)
2064 || all_bits_between_are_set == 0)
2067 create_simple_focus_bits (high_bits, low_bits,
2070 else if (lowest_bit_set == 0)
2071 shift = -(63 - highest_bit_set);
2073 if (! SPARC_SIMM13_P (the_const))
2076 emit_insn (gen_safe_SET64 (temp, the_const));
2078 emit_insn (gen_rtx_SET (VOIDmode,
2080 gen_rtx_ASHIFT (DImode,
2084 emit_insn (gen_rtx_SET (VOIDmode,
2086 gen_rtx_LSHIFTRT (DImode,
2088 GEN_INT (-shift))));
2094 /* Now a range of 22 or less bits set somewhere.
2095 * 1) sethi %hi(focus_bits), %reg
2096 * sllx %reg, shift, %reg
2097 * 2) sethi %hi(focus_bits), %reg
2098 * srlx %reg, shift, %reg
2100 if ((highest_bit_set - lowest_bit_set) < 21)
2102 unsigned HOST_WIDE_INT focus_bits =
2103 create_simple_focus_bits (high_bits, low_bits,
2104 lowest_bit_set, 10);
2106 if (! SPARC_SETHI_P (focus_bits))
2109 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2111 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2112 if (lowest_bit_set < 10)
2113 emit_insn (gen_rtx_SET (VOIDmode,
2115 gen_rtx_LSHIFTRT (DImode, temp,
2116 GEN_INT (10 - lowest_bit_set))));
2117 else if (lowest_bit_set > 10)
2118 emit_insn (gen_rtx_SET (VOIDmode,
2120 gen_rtx_ASHIFT (DImode, temp,
2121 GEN_INT (lowest_bit_set - 10))));
2127 /* 1) sethi %hi(low_bits), %reg
2128 * or %reg, %lo(low_bits), %reg
2129 * 2) sethi %hi(~low_bits), %reg
2130 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2133 || high_bits == 0xffffffff)
2135 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2136 (high_bits == 0xffffffff));
2140 /* Now, try 3-insn sequences. */
2142 /* 1) sethi %hi(high_bits), %reg
2143 * or %reg, %lo(high_bits), %reg
2144 * sllx %reg, 32, %reg
2148 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2152 /* We may be able to do something quick
2153 when the constant is negated, so try that. */
2154 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2155 (~low_bits) & 0xfffffc00))
2157 /* NOTE: The trailing bits get XOR'd so we need the
2158 non-negated bits, not the negated ones. */
2159 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2161 if ((((~high_bits) & 0xffffffff) == 0
2162 && ((~low_bits) & 0x80000000) == 0)
2163 || (((~high_bits) & 0xffffffff) == 0xffffffff
2164 && ((~low_bits) & 0x80000000) != 0))
2166 int fast_int = (~low_bits & 0xffffffff);
2168 if ((SPARC_SETHI_P (fast_int)
2169 && (~high_bits & 0xffffffff) == 0)
2170 || SPARC_SIMM13_P (fast_int))
2171 emit_insn (gen_safe_SET64 (temp, fast_int));
2173 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2178 #if HOST_BITS_PER_WIDE_INT == 64
2179 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2180 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2182 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2183 (~high_bits) & 0xffffffff,
2186 sparc_emit_set_const64 (temp, negated_const);
2189 /* If we are XOR'ing with -1, then we should emit a one's complement
2190 instead. This way the combiner will notice logical operations
2191 such as ANDN later on and substitute. */
2192 if (trailing_bits == 0x3ff)
2194 emit_insn (gen_rtx_SET (VOIDmode, op0,
2195 gen_rtx_NOT (DImode, temp)));
2199 emit_insn (gen_rtx_SET (VOIDmode,
2201 gen_safe_XOR64 (temp,
2202 (-0x400 | trailing_bits))));
2207 /* 1) sethi %hi(xxx), %reg
2208 * or %reg, %lo(xxx), %reg
2209 * sllx %reg, yyy, %reg
2211 * ??? This is just a generalized version of the low_bits==0
2212 * thing above, FIXME...
2214 if ((highest_bit_set - lowest_bit_set) < 32)
2216 unsigned HOST_WIDE_INT focus_bits =
2217 create_simple_focus_bits (high_bits, low_bits,
2220 /* We can't get here in this state. */
2221 if (highest_bit_set < 32
2222 || lowest_bit_set >= 32)
2225 /* So what we know is that the set bits straddle the
2226 middle of the 64-bit word. */
2227 sparc_emit_set_const64_quick2 (op0, temp,
2233 /* 1) sethi %hi(high_bits), %reg
2234 * or %reg, %lo(high_bits), %reg
2235 * sllx %reg, 32, %reg
2236 * or %reg, low_bits, %reg
2238 if (SPARC_SIMM13_P(low_bits)
2239 && ((int)low_bits > 0))
2241 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2245 /* The easiest way when all else fails, is full decomposition. */
2247 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2248 high_bits, low_bits, ~high_bits, ~low_bits);
2250 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2253 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2254 return the mode to be used for the comparison. For floating-point,
2255 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2256 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2257 processing is needed. */
2260 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2262 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2288 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2289 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2291 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2292 return CCX_NOOVmode;
2298 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2305 /* X and Y are two things to compare using CODE. Emit the compare insn and
2306 return the rtx for the cc reg in the proper mode. */
2309 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2311 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2314 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2315 fcc regs (cse can't tell they're really call clobbered regs and will
2316 remove a duplicate comparison even if there is an intervening function
2317 call - it will then try to reload the cc reg via an int reg which is why
2318 we need the movcc patterns). It is possible to provide the movcc
2319 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2320 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2321 to tell cse that CCFPE mode registers (even pseudos) are call
2324 /* ??? This is an experiment. Rather than making changes to cse which may
2325 or may not be easy/clean, we do our own cse. This is possible because
2326 we will generate hard registers. Cse knows they're call clobbered (it
2327 doesn't know the same thing about pseudos). If we guess wrong, no big
2328 deal, but if we win, great! */
2330 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2331 #if 1 /* experiment */
2334 /* We cycle through the registers to ensure they're all exercised. */
2335 static int next_fcc_reg = 0;
2336 /* Previous x,y for each fcc reg. */
2337 static rtx prev_args[4][2];
2339 /* Scan prev_args for x,y. */
2340 for (reg = 0; reg < 4; reg++)
2341 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2346 prev_args[reg][0] = x;
2347 prev_args[reg][1] = y;
2348 next_fcc_reg = (next_fcc_reg + 1) & 3;
2350 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2353 cc_reg = gen_reg_rtx (mode);
2354 #endif /* ! experiment */
2355 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2356 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2358 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2360 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2361 gen_rtx_COMPARE (mode, x, y)));
2366 /* This function is used for v9 only.
2367 CODE is the code for an Scc's comparison.
2368 OPERANDS[0] is the target of the Scc insn.
2369 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2370 been generated yet).
2372 This function is needed to turn
2375 (gt (reg:CCX 100 %icc)
2379 (gt:DI (reg:CCX 100 %icc)
2382 IE: The instruction recognizer needs to see the mode of the comparison to
2383 find the right instruction. We could use "gt:DI" right in the
2384 define_expand, but leaving it out allows us to handle DI, SI, etc.
2386 We refer to the global sparc compare operands sparc_compare_op0 and
2387 sparc_compare_op1. */
2390 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2395 && (GET_MODE (sparc_compare_op0) == DImode
2396 || GET_MODE (operands[0]) == DImode))
2399 op0 = sparc_compare_op0;
2400 op1 = sparc_compare_op1;
2402 /* Try to use the movrCC insns. */
2404 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2405 && op1 == const0_rtx
2406 && v9_regcmp_p (compare_code))
2408 /* Special case for op0 != 0. This can be done with one instruction if
2409 operands[0] == sparc_compare_op0. */
2411 if (compare_code == NE
2412 && GET_MODE (operands[0]) == DImode
2413 && rtx_equal_p (op0, operands[0]))
2415 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2416 gen_rtx_IF_THEN_ELSE (DImode,
2417 gen_rtx_fmt_ee (compare_code, DImode,
2424 if (reg_overlap_mentioned_p (operands[0], op0))
2426 /* Handle the case where operands[0] == sparc_compare_op0.
2427 We "early clobber" the result. */
2428 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2429 emit_move_insn (op0, sparc_compare_op0);
2432 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2433 if (GET_MODE (op0) != DImode)
2435 temp = gen_reg_rtx (DImode);
2436 convert_move (temp, op0, 0);
2440 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2441 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2442 gen_rtx_fmt_ee (compare_code, DImode,
2450 operands[1] = gen_compare_reg (compare_code, op0, op1);
2452 switch (GET_MODE (operands[1]))
2462 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2463 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2464 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2465 gen_rtx_fmt_ee (compare_code,
2466 GET_MODE (operands[1]),
2467 operands[1], const0_rtx),
2468 const1_rtx, operands[0])));
2473 /* Emit a conditional jump insn for the v9 architecture using comparison code
2474 CODE and jump target LABEL.
2475 This function exists to take advantage of the v9 brxx insns. */
2478 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2480 emit_jump_insn (gen_rtx_SET (VOIDmode,
2482 gen_rtx_IF_THEN_ELSE (VOIDmode,
2483 gen_rtx_fmt_ee (code, GET_MODE (op0),
2485 gen_rtx_LABEL_REF (VOIDmode, label),
2489 /* Generate a DFmode part of a hard TFmode register.
2490 REG is the TFmode hard register, LOW is 1 for the
2491 low 64bit of the register and 0 otherwise.
2494 gen_df_reg (rtx reg, int low)
2496 int regno = REGNO (reg);
2498 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2499 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2500 return gen_rtx_REG (DFmode, regno);
2503 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2504 Unlike normal calls, TFmode operands are passed by reference. It is
2505 assumed that no more than 3 operands are required. */
2508 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2510 rtx ret_slot = NULL, arg[3], func_sym;
2513 /* We only expect to be called for conversions, unary, and binary ops. */
2514 if (nargs < 2 || nargs > 3)
2517 for (i = 0; i < nargs; ++i)
2519 rtx this_arg = operands[i];
2522 /* TFmode arguments and return values are passed by reference. */
2523 if (GET_MODE (this_arg) == TFmode)
2525 int force_stack_temp;
2527 force_stack_temp = 0;
2528 if (TARGET_BUGGY_QP_LIB && i == 0)
2529 force_stack_temp = 1;
2531 if (GET_CODE (this_arg) == MEM
2532 && ! force_stack_temp)
2533 this_arg = XEXP (this_arg, 0);
2534 else if (CONSTANT_P (this_arg)
2535 && ! force_stack_temp)
2537 this_slot = force_const_mem (TFmode, this_arg);
2538 this_arg = XEXP (this_slot, 0);
2542 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2544 /* Operand 0 is the return value. We'll copy it out later. */
2546 emit_move_insn (this_slot, this_arg);
2548 ret_slot = this_slot;
2550 this_arg = XEXP (this_slot, 0);
2557 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2559 if (GET_MODE (operands[0]) == TFmode)
2562 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2563 arg[0], GET_MODE (arg[0]),
2564 arg[1], GET_MODE (arg[1]));
2566 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2567 arg[0], GET_MODE (arg[0]),
2568 arg[1], GET_MODE (arg[1]),
2569 arg[2], GET_MODE (arg[2]));
2572 emit_move_insn (operands[0], ret_slot);
2581 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2582 GET_MODE (operands[0]), 1,
2583 arg[1], GET_MODE (arg[1]));
2585 if (ret != operands[0])
2586 emit_move_insn (operands[0], ret);
2590 /* Expand soft-float TFmode calls to sparc abi routines. */
2593 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2615 emit_soft_tfmode_libcall (func, 3, operands);
2619 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2632 emit_soft_tfmode_libcall (func, 2, operands);
2636 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2643 switch (GET_MODE (operands[1]))
2656 case FLOAT_TRUNCATE:
2657 switch (GET_MODE (operands[0]))
2671 switch (GET_MODE (operands[1]))
2684 case UNSIGNED_FLOAT:
2685 switch (GET_MODE (operands[1]))
2699 switch (GET_MODE (operands[0]))
2713 switch (GET_MODE (operands[0]))
2730 emit_soft_tfmode_libcall (func, 2, operands);
2733 /* Expand a hard-float tfmode operation. All arguments must be in
2737 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2741 if (GET_RTX_CLASS (code) == '1')
2743 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2744 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2748 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2749 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2750 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2751 operands[1], operands[2]);
2754 if (register_operand (operands[0], VOIDmode))
2757 dest = gen_reg_rtx (GET_MODE (operands[0]));
2759 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2761 if (dest != operands[0])
2762 emit_move_insn (operands[0], dest);
2766 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2768 if (TARGET_HARD_QUAD)
2769 emit_hard_tfmode_operation (code, operands);
2771 emit_soft_tfmode_binop (code, operands);
2775 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2777 if (TARGET_HARD_QUAD)
2778 emit_hard_tfmode_operation (code, operands);
2780 emit_soft_tfmode_unop (code, operands);
2784 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2786 if (TARGET_HARD_QUAD)
2787 emit_hard_tfmode_operation (code, operands);
2789 emit_soft_tfmode_cvt (code, operands);
2792 /* Return nonzero if a return peephole merging return with
2793 setting of output register is ok. */
2795 leaf_return_peephole_ok (void)
2797 return (actual_fsize == 0);
2800 /* Return nonzero if a branch/jump/call instruction will be emitting
2801 nop into its delay slot. */
2804 empty_delay_slot (rtx insn)
2808 /* If no previous instruction (should not happen), return true. */
2809 if (PREV_INSN (insn) == NULL)
2812 seq = NEXT_INSN (PREV_INSN (insn));
2813 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2819 /* Return nonzero if TRIAL can go into the function epilogue's
2820 delay slot. SLOT is the slot we are trying to fill. */
2823 eligible_for_epilogue_delay (rtx trial, int slot)
2830 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2833 if (get_attr_length (trial) != 1)
2836 /* If there are any call-saved registers, we should scan TRIAL if it
2837 does not reference them. For now just make it easy. */
2841 /* If the function uses __builtin_eh_return, the eh_return machinery
2842 occupies the delay slot. */
2843 if (current_function_calls_eh_return)
2846 /* In the case of a true leaf function, anything can go into the delay slot.
2847 A delay slot only exists however if the frame size is zero, otherwise
2848 we will put an insn to adjust the stack after the return. */
2849 if (current_function_uses_only_leaf_regs)
2851 if (leaf_return_peephole_ok ())
2852 return ((get_attr_in_uncond_branch_delay (trial)
2853 == IN_BRANCH_DELAY_TRUE));
2857 pat = PATTERN (trial);
2859 /* Otherwise, only operations which can be done in tandem with
2860 a `restore' or `return' insn can go into the delay slot. */
2861 if (GET_CODE (SET_DEST (pat)) != REG
2862 || REGNO (SET_DEST (pat)) < 24)
2865 /* If this instruction sets up floating point register and we have a return
2866 instruction, it can probably go in. But restore will not work
2868 if (REGNO (SET_DEST (pat)) >= 32)
2870 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2871 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2876 /* The set of insns matched here must agree precisely with the set of
2877 patterns paired with a RETURN in sparc.md. */
2879 src = SET_SRC (pat);
2881 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2882 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2883 && arith_operand (src, GET_MODE (src)))
2886 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2888 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2891 /* This matches "*return_di". */
2892 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2893 && arith_double_operand (src, GET_MODE (src)))
2894 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2896 /* This matches "*return_sf_no_fpu". */
2897 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2898 && register_operand (src, SFmode))
2901 /* If we have return instruction, anything that does not use
2902 local or output registers and can go into a delay slot wins. */
2903 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2904 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2907 /* This matches "*return_addsi". */
2908 else if (GET_CODE (src) == PLUS
2909 && arith_operand (XEXP (src, 0), SImode)
2910 && arith_operand (XEXP (src, 1), SImode)
2911 && (register_operand (XEXP (src, 0), SImode)
2912 || register_operand (XEXP (src, 1), SImode)))
2915 /* This matches "*return_adddi". */
2916 else if (GET_CODE (src) == PLUS
2917 && arith_double_operand (XEXP (src, 0), DImode)
2918 && arith_double_operand (XEXP (src, 1), DImode)
2919 && (register_operand (XEXP (src, 0), DImode)
2920 || register_operand (XEXP (src, 1), DImode)))
2923 /* This can match "*return_losum_[sd]i".
2924 Catch only some cases, so that return_losum* don't have
2926 else if (GET_CODE (src) == LO_SUM
2927 && ! TARGET_CM_MEDMID
2928 && ((register_operand (XEXP (src, 0), SImode)
2929 && immediate_operand (XEXP (src, 1), SImode))
2931 && register_operand (XEXP (src, 0), DImode)
2932 && immediate_operand (XEXP (src, 1), DImode))))
2935 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2936 else if (GET_CODE (src) == ASHIFT
2937 && (register_operand (XEXP (src, 0), SImode)
2938 || register_operand (XEXP (src, 0), DImode))
2939 && XEXP (src, 1) == const1_rtx)
2945 /* Return nonzero if TRIAL can go into the call delay slot. */
2947 tls_call_delay (rtx trial)
2952 call __tls_get_addr, %tgd_call (foo)
2953 add %l7, %o0, %o0, %tgd_add (foo)
2954 while Sun as/ld does not. */
2955 if (TARGET_GNU_TLS || !TARGET_TLS)
2958 pat = PATTERN (trial);
2960 /* We must reject tgd_add{32|64}, i.e.
2961 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2962 and tldm_add{32|64}, i.e.
2963 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2965 if (GET_CODE (pat) == SET
2966 && GET_CODE (SET_SRC (pat)) == PLUS)
2968 rtx unspec = XEXP (SET_SRC (pat), 1);
2970 if (GET_CODE (unspec) == UNSPEC
2971 && (XINT (unspec, 1) == UNSPEC_TLSGD
2972 || XINT (unspec, 1) == UNSPEC_TLSLDM))
2979 /* Return nonzero if TRIAL can go into the sibling call
2983 eligible_for_sibcall_delay (rtx trial)
2987 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2990 if (get_attr_length (trial) != 1)
2993 pat = PATTERN (trial);
2995 if (current_function_uses_only_leaf_regs)
2997 /* If the tail call is done using the call instruction,
2998 we have to restore %o7 in the delay slot. */
2999 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
3002 /* %g1 is used to build the function address */
3003 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3009 /* Otherwise, only operations which can be done in tandem with
3010 a `restore' insn can go into the delay slot. */
3011 if (GET_CODE (SET_DEST (pat)) != REG
3012 || REGNO (SET_DEST (pat)) < 24
3013 || REGNO (SET_DEST (pat)) >= 32)
3016 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3018 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3021 src = SET_SRC (pat);
3023 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3024 && arith_operand (src, GET_MODE (src)))
3027 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3029 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3032 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3033 && arith_double_operand (src, GET_MODE (src)))
3034 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3036 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
3037 && register_operand (src, SFmode))
3040 else if (GET_CODE (src) == PLUS
3041 && arith_operand (XEXP (src, 0), SImode)
3042 && arith_operand (XEXP (src, 1), SImode)
3043 && (register_operand (XEXP (src, 0), SImode)
3044 || register_operand (XEXP (src, 1), SImode)))
3047 else if (GET_CODE (src) == PLUS
3048 && arith_double_operand (XEXP (src, 0), DImode)
3049 && arith_double_operand (XEXP (src, 1), DImode)
3050 && (register_operand (XEXP (src, 0), DImode)
3051 || register_operand (XEXP (src, 1), DImode)))
3054 else if (GET_CODE (src) == LO_SUM
3055 && ! TARGET_CM_MEDMID
3056 && ((register_operand (XEXP (src, 0), SImode)
3057 && immediate_operand (XEXP (src, 1), SImode))
3059 && register_operand (XEXP (src, 0), DImode)
3060 && immediate_operand (XEXP (src, 1), DImode))))
3063 else if (GET_CODE (src) == ASHIFT
3064 && (register_operand (XEXP (src, 0), SImode)
3065 || register_operand (XEXP (src, 0), DImode))
3066 && XEXP (src, 1) == const1_rtx)
3073 check_return_regs (rtx x)
3075 switch (GET_CODE (x))
3078 return IN_OR_GLOBAL_P (x);
3093 if (check_return_regs (XEXP (x, 1)) == 0)
3098 return check_return_regs (XEXP (x, 0));
3107 short_branch (int uid1, int uid2)
3109 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3111 /* Leave a few words of "slop". */
3112 if (delta >= -1023 && delta <= 1022)
3118 /* Return nonzero if REG is not used after INSN.
3119 We assume REG is a reload reg, and therefore does
3120 not live past labels or calls or jumps. */
3122 reg_unused_after (rtx reg, rtx insn)
3124 enum rtx_code code, prev_code = UNKNOWN;
3126 while ((insn = NEXT_INSN (insn)))
3128 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3131 code = GET_CODE (insn);
3132 if (GET_CODE (insn) == CODE_LABEL)
3135 if (GET_RTX_CLASS (code) == 'i')
3137 rtx set = single_set (insn);
3138 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3141 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3143 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3151 /* Determine if it's legal to put X into the constant pool. This
3152 is not possible if X contains the address of a symbol that is
3153 not constant (TLS) or not known at final link time (PIC). */
3156 sparc_cannot_force_const_mem (rtx x)
3158 switch (GET_CODE (x))
3162 /* Accept all non-symbolic constants. */
3166 /* Labels are OK iff we are non-PIC. */
3167 return flag_pic != 0;
3170 /* 'Naked' TLS symbol references are never OK,
3171 non-TLS symbols are OK iff we are non-PIC. */
3172 if (SYMBOL_REF_TLS_MODEL (x))
3175 return flag_pic != 0;
3178 return sparc_cannot_force_const_mem (XEXP (x, 0));
3181 return sparc_cannot_force_const_mem (XEXP (x, 0))
3182 || sparc_cannot_force_const_mem (XEXP (x, 1));
3190 /* The table we use to reference PIC data. */
3191 static GTY(()) rtx global_offset_table;
3193 /* The function we use to get at it. */
3194 static GTY(()) rtx get_pc_symbol;
3195 static GTY(()) char get_pc_symbol_name[256];
3197 /* Ensure that we are not using patterns that are not OK with PIC. */
3205 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3206 || (GET_CODE (recog_data.operand[i]) == CONST
3207 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3208 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3209 == global_offset_table)
3210 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3219 /* Return true if X is an address which needs a temporary register when
3220 reloaded while generating PIC code. */
3223 pic_address_needs_scratch (rtx x)
3225 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3226 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3227 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3228 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3229 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3235 /* Determine if a given RTX is a valid constant. We already know this
3236 satisfies CONSTANT_P. */
3239 legitimate_constant_p (rtx x)
3243 switch (GET_CODE (x))
3246 /* TLS symbols are not constant. */
3247 if (SYMBOL_REF_TLS_MODEL (x))
3252 inner = XEXP (x, 0);
3254 /* Offsets of TLS symbols are never valid.
3255 Discourage CSE from creating them. */
3256 if (GET_CODE (inner) == PLUS
3257 && tls_symbolic_operand (XEXP (inner, 0)))
3262 if (GET_MODE (x) == VOIDmode)
3265 /* Floating point constants are generally not ok.
3266 The only exception is 0.0 in VIS. */
3268 && (GET_MODE (x) == SFmode
3269 || GET_MODE (x) == DFmode
3270 || GET_MODE (x) == TFmode)
3271 && fp_zero_operand (x, GET_MODE (x)))
3283 /* Determine if a given RTX is a valid constant address. */
3286 constant_address_p (rtx x)
3288 switch (GET_CODE (x))
3296 if (flag_pic && pic_address_needs_scratch (x))
3298 return legitimate_constant_p (x);
3301 return !flag_pic && legitimate_constant_p (x);
3308 /* Nonzero if the constant value X is a legitimate general operand
3309 when generating PIC code. It is given that flag_pic is on and
3310 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3313 legitimate_pic_operand_p (rtx x)
3315 if (pic_address_needs_scratch (x))
3317 if (tls_symbolic_operand (x)
3318 || (GET_CODE (x) == CONST
3319 && GET_CODE (XEXP (x, 0)) == PLUS
3320 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3325 /* Return nonzero if ADDR is a valid memory address.
3326 STRICT specifies whether strict register checking applies. */
3329 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3331 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3333 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3335 else if (GET_CODE (addr) == PLUS)
3337 rs1 = XEXP (addr, 0);
3338 rs2 = XEXP (addr, 1);
3340 /* Canonicalize. REG comes first, if there are no regs,
3341 LO_SUM comes first. */
3343 && GET_CODE (rs1) != SUBREG
3345 || GET_CODE (rs2) == SUBREG
3346 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3348 rs1 = XEXP (addr, 1);
3349 rs2 = XEXP (addr, 0);
3353 && rs1 == pic_offset_table_rtx
3355 && GET_CODE (rs2) != SUBREG
3356 && GET_CODE (rs2) != LO_SUM
3357 && GET_CODE (rs2) != MEM
3358 && !tls_symbolic_operand (rs2)
3359 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3360 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3362 || GET_CODE (rs1) == SUBREG)
3363 && RTX_OK_FOR_OFFSET_P (rs2)))
3368 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3369 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3371 /* We prohibit REG + REG for TFmode when there are no quad move insns
3372 and we consequently need to split. We do this because REG+REG
3373 is not an offsettable address. If we get the situation in reload
3374 where source and destination of a movtf pattern are both MEMs with
3375 REG+REG address, then only one of them gets converted to an
3376 offsettable address. */
3378 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
3381 /* We prohibit REG + REG on ARCH32 if not optimizing for
3382 DFmode/DImode because then mem_min_alignment is likely to be zero
3383 after reload and the forced split would lack a matching splitter
3385 if (TARGET_ARCH32 && !optimize
3386 && (mode == DFmode || mode == DImode))
3389 else if (USE_AS_OFFSETABLE_LO10
3390 && GET_CODE (rs1) == LO_SUM
3392 && ! TARGET_CM_MEDMID
3393 && RTX_OK_FOR_OLO10_P (rs2))
3396 imm1 = XEXP (rs1, 1);
3397 rs1 = XEXP (rs1, 0);
3398 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3402 else if (GET_CODE (addr) == LO_SUM)
3404 rs1 = XEXP (addr, 0);
3405 imm1 = XEXP (addr, 1);
3407 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3410 /* We can't allow TFmode in 32-bit mode, because an offset greater
3411 than the alignment (8) may cause the LO_SUM to overflow. */
3412 if (mode == TFmode && TARGET_ARCH32)
3415 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3420 if (GET_CODE (rs1) == SUBREG)
3421 rs1 = SUBREG_REG (rs1);
3427 if (GET_CODE (rs2) == SUBREG)
3428 rs2 = SUBREG_REG (rs2);
3435 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3436 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3441 if ((REGNO (rs1) >= 32
3442 && REGNO (rs1) != FRAME_POINTER_REGNUM
3443 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3445 && (REGNO (rs2) >= 32
3446 && REGNO (rs2) != FRAME_POINTER_REGNUM
3447 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3453 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3455 static GTY(()) rtx sparc_tls_symbol;
3457 sparc_tls_get_addr (void)
3459 if (!sparc_tls_symbol)
3460 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3462 return sparc_tls_symbol;
3466 sparc_tls_got (void)
3471 current_function_uses_pic_offset_table = 1;
3472 return pic_offset_table_rtx;
3475 if (!global_offset_table)
3476 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3477 temp = gen_reg_rtx (Pmode);
3478 emit_move_insn (temp, global_offset_table);
3483 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3484 this (thread-local) address. */
3487 legitimize_tls_address (rtx addr)
3489 rtx temp1, temp2, temp3, ret, o0, got, insn;
3494 if (GET_CODE (addr) == SYMBOL_REF)
3495 switch (SYMBOL_REF_TLS_MODEL (addr))
3497 case TLS_MODEL_GLOBAL_DYNAMIC:
3499 temp1 = gen_reg_rtx (SImode);
3500 temp2 = gen_reg_rtx (SImode);
3501 ret = gen_reg_rtx (Pmode);
3502 o0 = gen_rtx_REG (Pmode, 8);
3503 got = sparc_tls_got ();
3504 emit_insn (gen_tgd_hi22 (temp1, addr));
3505 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3508 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3509 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3514 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3515 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3518 CALL_INSN_FUNCTION_USAGE (insn)
3519 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3520 CALL_INSN_FUNCTION_USAGE (insn));
3521 insn = get_insns ();
3523 emit_libcall_block (insn, ret, o0, addr);
3526 case TLS_MODEL_LOCAL_DYNAMIC:
3528 temp1 = gen_reg_rtx (SImode);
3529 temp2 = gen_reg_rtx (SImode);
3530 temp3 = gen_reg_rtx (Pmode);
3531 ret = gen_reg_rtx (Pmode);
3532 o0 = gen_rtx_REG (Pmode, 8);
3533 got = sparc_tls_got ();
3534 emit_insn (gen_tldm_hi22 (temp1));
3535 emit_insn (gen_tldm_lo10 (temp2, temp1));
3538 emit_insn (gen_tldm_add32 (o0, got, temp2));
3539 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3544 emit_insn (gen_tldm_add64 (o0, got, temp2));
3545 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3548 CALL_INSN_FUNCTION_USAGE (insn)
3549 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3550 CALL_INSN_FUNCTION_USAGE (insn));
3551 insn = get_insns ();
3553 emit_libcall_block (insn, temp3, o0,
3554 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3555 UNSPEC_TLSLD_BASE));
3556 temp1 = gen_reg_rtx (SImode);
3557 temp2 = gen_reg_rtx (SImode);
3558 emit_insn (gen_tldo_hix22 (temp1, addr));
3559 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3561 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3563 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3566 case TLS_MODEL_INITIAL_EXEC:
3567 temp1 = gen_reg_rtx (SImode);
3568 temp2 = gen_reg_rtx (SImode);
3569 temp3 = gen_reg_rtx (Pmode);
3570 got = sparc_tls_got ();
3571 emit_insn (gen_tie_hi22 (temp1, addr));
3572 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3574 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3576 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3579 ret = gen_reg_rtx (Pmode);
3581 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3584 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3588 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3591 case TLS_MODEL_LOCAL_EXEC:
3592 temp1 = gen_reg_rtx (Pmode);
3593 temp2 = gen_reg_rtx (Pmode);
3596 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3597 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3601 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3602 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3604 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3612 abort (); /* for now ... */
3618 /* Legitimize PIC addresses. If the address is already position-independent,
3619 we return ORIG. Newly generated position-independent addresses go into a
3620 reg. This is REG if nonzero, otherwise we allocate register(s) as
3624 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3627 if (GET_CODE (orig) == SYMBOL_REF)
3629 rtx pic_ref, address;
3634 if (reload_in_progress || reload_completed)
3637 reg = gen_reg_rtx (Pmode);
3642 /* If not during reload, allocate another temp reg here for loading
3643 in the address, so that these instructions can be optimized
3645 rtx temp_reg = ((reload_in_progress || reload_completed)
3646 ? reg : gen_reg_rtx (Pmode));
3648 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3649 won't get confused into thinking that these two instructions
3650 are loading in the true address of the symbol. If in the
3651 future a PIC rtx exists, that should be used instead. */
3652 if (Pmode == SImode)
3654 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3655 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3659 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3660 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3667 pic_ref = gen_rtx_MEM (Pmode,
3668 gen_rtx_PLUS (Pmode,
3669 pic_offset_table_rtx, address));
3670 current_function_uses_pic_offset_table = 1;
3671 RTX_UNCHANGING_P (pic_ref) = 1;
3672 insn = emit_move_insn (reg, pic_ref);
3673 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3675 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3679 else if (GET_CODE (orig) == CONST)
3683 if (GET_CODE (XEXP (orig, 0)) == PLUS
3684 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3689 if (reload_in_progress || reload_completed)
3692 reg = gen_reg_rtx (Pmode);
3695 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3697 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3698 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3699 base == reg ? 0 : reg);
3704 if (GET_CODE (offset) == CONST_INT)
3706 if (SMALL_INT (offset))
3707 return plus_constant (base, INTVAL (offset));
3708 else if (! reload_in_progress && ! reload_completed)
3709 offset = force_reg (Pmode, offset);
3711 /* If we reach here, then something is seriously wrong. */
3714 return gen_rtx_PLUS (Pmode, base, offset);
3716 else if (GET_CODE (orig) == LABEL_REF)
3717 /* ??? Why do we do this? */
3718 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3719 the register is live instead, in case it is eliminated. */
3720 current_function_uses_pic_offset_table = 1;
3725 /* Try machine-dependent ways of modifying an illegitimate address X
3726 to be legitimate. If we find one, return the new, valid address.
3728 OLDX is the address as it was before break_out_memory_refs was called.
3729 In some cases it is useful to look at this to decide what needs to be done.
3731 MODE is the mode of the operand pointed to by X. */
3734 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3738 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3739 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3740 force_operand (XEXP (x, 0), NULL_RTX));
3741 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3742 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3743 force_operand (XEXP (x, 1), NULL_RTX));
3744 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3745 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3747 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3748 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3749 force_operand (XEXP (x, 1), NULL_RTX));
3751 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3754 if (tls_symbolic_operand (x))
3755 x = legitimize_tls_address (x);
3757 x = legitimize_pic_address (x, mode, 0);
3758 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3759 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3760 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3761 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3762 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3763 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3764 else if (GET_CODE (x) == SYMBOL_REF
3765 || GET_CODE (x) == CONST
3766 || GET_CODE (x) == LABEL_REF)
3767 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3771 /* Emit special PIC prologues. */
3774 load_pic_register (void)
3776 /* Labels to get the PC in the prologue of this function. */
3777 int orig_flag_pic = flag_pic;
3782 /* If we haven't emitted the special get_pc helper function, do so now. */
3783 if (get_pc_symbol_name[0] == 0)
3787 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3790 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3792 ASM_OUTPUT_ALIGN (asm_out_file, align);
3793 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3794 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3797 /* Initialize every time through, since we can't easily
3798 know this to be permanent. */
3799 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3800 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3803 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3806 flag_pic = orig_flag_pic;
3808 /* Need to emit this whether or not we obey regdecls,
3809 since setjmp/longjmp can cause life info to screw up.
3810 ??? In the case where we don't obey regdecls, this is not sufficient
3811 since we may not fall out the bottom. */
3812 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3815 /* Return 1 if RTX is a MEM which is known to be aligned to at
3816 least a DESIRED byte boundary. */
3819 mem_min_alignment (rtx mem, int desired)
3821 rtx addr, base, offset;
3823 /* If it's not a MEM we can't accept it. */
3824 if (GET_CODE (mem) != MEM)
3827 addr = XEXP (mem, 0);
3828 base = offset = NULL_RTX;
3829 if (GET_CODE (addr) == PLUS)
3831 if (GET_CODE (XEXP (addr, 0)) == REG)
3833 base = XEXP (addr, 0);
3835 /* What we are saying here is that if the base
3836 REG is aligned properly, the compiler will make
3837 sure any REG based index upon it will be so
3839 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3840 offset = XEXP (addr, 1);
3842 offset = const0_rtx;
3845 else if (GET_CODE (addr) == REG)
3848 offset = const0_rtx;
3851 if (base != NULL_RTX)
3853 int regno = REGNO (base);
3855 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3857 /* Check if the compiler has recorded some information
3858 about the alignment of the base REG. If reload has
3859 completed, we already matched with proper alignments.
3860 If not running global_alloc, reload might give us
3861 unaligned pointer to local stack though. */
3863 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3864 || (optimize && reload_completed))
3865 && (INTVAL (offset) & (desired - 1)) == 0)
3870 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3874 else if (! TARGET_UNALIGNED_DOUBLES
3875 || CONSTANT_P (addr)
3876 || GET_CODE (addr) == LO_SUM)
3878 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3879 is true, in which case we can only assume that an access is aligned if
3880 it is to a constant address, or the address involves a LO_SUM. */
3884 /* An obviously unaligned address. */
3889 /* Vectors to keep interesting information about registers where it can easily
3890 be got. We used to use the actual mode value as the bit number, but there
3891 are more than 32 modes now. Instead we use two tables: one indexed by
3892 hard register number, and one indexed by mode. */
3894 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3895 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3896 mapped into one sparc_mode_class mode. */
3898 enum sparc_mode_class {
3899 S_MODE, D_MODE, T_MODE, O_MODE,
3900 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3904 /* Modes for single-word and smaller quantities. */
3905 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3907 /* Modes for double-word and smaller quantities. */
3908 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3910 /* Modes for quad-word and smaller quantities. */
3911 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3913 /* Modes for 8-word and smaller quantities. */
3914 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3916 /* Modes for single-float quantities. We must allow any single word or
3917 smaller quantity. This is because the fix/float conversion instructions
3918 take integer inputs/outputs from the float registers. */
3919 #define SF_MODES (S_MODES)
3921 /* Modes for double-float and smaller quantities. */
3922 #define DF_MODES (S_MODES | D_MODES)
3924 /* Modes for double-float only quantities. */
3925 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3927 /* Modes for quad-float only quantities. */
3928 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3930 /* Modes for quad-float and smaller quantities. */
3931 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3933 /* Modes for quad-float and double-float quantities. */
3934 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3936 /* Modes for quad-float pair only quantities. */
3937 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3939 /* Modes for quad-float pairs and smaller quantities. */
3940 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3942 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3944 /* Modes for condition codes. */
3945 #define CC_MODES (1 << (int) CC_MODE)
3946 #define CCFP_MODES (1 << (int) CCFP_MODE)
3948 /* Value is 1 if register/mode pair is acceptable on sparc.
3949 The funny mixture of D and T modes is because integer operations
3950 do not specially operate on tetra quantities, so non-quad-aligned
3951 registers can hold quadword quantities (except %o4 and %i4 because
3952 they cross fixed registers). */
3954 /* This points to either the 32 bit or the 64 bit version. */
3955 const int *hard_regno_mode_classes;
3957 static const int hard_32bit_mode_classes[] = {
3958 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3959 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3960 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3961 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3963 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3964 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3965 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3966 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3968 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3969 and none can hold SFmode/SImode values. */
3970 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3971 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3972 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3973 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3976 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3982 static const int hard_64bit_mode_classes[] = {
3983 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3984 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3985 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3986 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3988 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3989 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3990 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3991 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3993 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3994 and none can hold SFmode/SImode values. */
3995 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3996 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3997 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3998 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4001 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4007 int sparc_mode_class [NUM_MACHINE_MODES];
4009 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4012 sparc_init_modes (void)
4016 for (i = 0; i < NUM_MACHINE_MODES; i++)
4018 switch (GET_MODE_CLASS (i))
4021 case MODE_PARTIAL_INT:
4022 case MODE_COMPLEX_INT:
4023 if (GET_MODE_SIZE (i) <= 4)
4024 sparc_mode_class[i] = 1 << (int) S_MODE;
4025 else if (GET_MODE_SIZE (i) == 8)
4026 sparc_mode_class[i] = 1 << (int) D_MODE;
4027 else if (GET_MODE_SIZE (i) == 16)
4028 sparc_mode_class[i] = 1 << (int) T_MODE;
4029 else if (GET_MODE_SIZE (i) == 32)
4030 sparc_mode_class[i] = 1 << (int) O_MODE;
4032 sparc_mode_class[i] = 0;
4035 case MODE_COMPLEX_FLOAT:
4036 if (GET_MODE_SIZE (i) <= 4)
4037 sparc_mode_class[i] = 1 << (int) SF_MODE;
4038 else if (GET_MODE_SIZE (i) == 8)
4039 sparc_mode_class[i] = 1 << (int) DF_MODE;
4040 else if (GET_MODE_SIZE (i) == 16)
4041 sparc_mode_class[i] = 1 << (int) TF_MODE;
4042 else if (GET_MODE_SIZE (i) == 32)
4043 sparc_mode_class[i] = 1 << (int) OF_MODE;
4045 sparc_mode_class[i] = 0;
4048 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4049 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4051 sparc_mode_class[i] = 1 << (int) CC_MODE;
4054 sparc_mode_class[i] = 0;
4060 hard_regno_mode_classes = hard_64bit_mode_classes;
4062 hard_regno_mode_classes = hard_32bit_mode_classes;
4064 /* Initialize the array used by REGNO_REG_CLASS. */
4065 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4067 if (i < 16 && TARGET_V8PLUS)
4068 sparc_regno_reg_class[i] = I64_REGS;
4069 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4070 sparc_regno_reg_class[i] = GENERAL_REGS;
4072 sparc_regno_reg_class[i] = FP_REGS;
4074 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4076 sparc_regno_reg_class[i] = FPCC_REGS;
4078 sparc_regno_reg_class[i] = NO_REGS;
4082 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
4083 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4084 v9 int regs as it simplifies the code. */
4087 save_regs (FILE *file, int low, int high, const char *base,
4088 int offset, int n_regs, HOST_WIDE_INT real_offset)
4092 if (TARGET_ARCH64 && high <= 32)
4094 for (i = low; i < high; i++)
4096 if (regs_ever_live[i] && ! call_used_regs[i])
4098 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4099 reg_names[i], base, offset + 4 * n_regs);
4100 if (dwarf2out_do_frame ())
4101 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4108 for (i = low; i < high; i += 2)
4110 if (regs_ever_live[i] && ! call_used_regs[i])
4112 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4114 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4115 reg_names[i], base, offset + 4 * n_regs);
4116 if (dwarf2out_do_frame ())
4118 char *l = dwarf2out_cfi_label ();
4119 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4120 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4126 fprintf (file, "\tst\t%s, [%s+%d]\n",
4127 reg_names[i], base, offset + 4 * n_regs);
4128 if (dwarf2out_do_frame ())
4129 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4135 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4137 fprintf (file, "\tst\t%s, [%s+%d]\n",
4138 reg_names[i+1], base, offset + 4 * n_regs + 4);
4139 if (dwarf2out_do_frame ())
4140 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4149 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4151 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4152 v9 int regs as it simplifies the code. */
4155 restore_regs (FILE *file, int low, int high, const char *base,
4156 int offset, int n_regs)
4160 if (TARGET_ARCH64 && high <= 32)
4162 for (i = low; i < high; i++)
4164 if (regs_ever_live[i] && ! call_used_regs[i])
4165 fprintf (file, "\tldx\t[%s+%d], %s\n",
4166 base, offset + 4 * n_regs, reg_names[i]),
4172 for (i = low; i < high; i += 2)
4174 if (regs_ever_live[i] && ! call_used_regs[i])
4175 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4176 fprintf (file, "\tldd\t[%s+%d], %s\n",
4177 base, offset + 4 * n_regs, reg_names[i]),
4180 fprintf (file, "\tld\t[%s+%d], %s\n",
4181 base, offset + 4 * n_regs, reg_names[i]),
4183 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4184 fprintf (file, "\tld\t[%s+%d], %s\n",
4185 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4192 /* Compute the frame size required by the function. This function is called
4193 during the reload pass and also by output_function_prologue(). */
4196 compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4199 int outgoing_args_size = (current_function_outgoing_args_size
4200 + REG_PARM_STACK_SPACE (current_function_decl));
4202 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4203 even to v9 int regs to be consistent with save_regs/restore_regs. */
4207 for (i = 0; i < 8; i++)
4208 if (regs_ever_live[i] && ! call_used_regs[i])
4213 for (i = 0; i < 8; i += 2)
4214 if ((regs_ever_live[i] && ! call_used_regs[i])
4215 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4219 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4220 if ((regs_ever_live[i] && ! call_used_regs[i])
4221 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4224 /* Set up values for use in `function_epilogue'. */
4225 num_gfregs = n_regs;
4227 if (leaf_function && n_regs == 0
4228 && size == 0 && current_function_outgoing_args_size == 0)
4230 actual_fsize = apparent_fsize = 0;
4234 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4235 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4236 apparent_fsize += n_regs * 4;
4237 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4240 /* Make sure nothing can clobber our register windows.
4241 If a SAVE must be done, or there is a stack-local variable,
4242 the register window area must be allocated.
4243 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4244 if (leaf_function == 0 || size > 0)
4245 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4247 return SPARC_STACK_ALIGN (actual_fsize);
4250 /* Build big number NUM in register REG and output the result to FILE.
4251 REG is guaranteed to be the only clobbered register. The function
4252 will very likely emit several instructions, so it must not be called
4253 from within a delay slot. */
4256 build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg)
4258 #if HOST_BITS_PER_WIDE_INT == 64
4259 HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff;
4267 /* We don't use the 'set' macro because it appears to be broken
4268 in the Solaris 7 assembler. */
4269 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4271 if ((num & 0x3ff) != 0)
4272 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4275 #if HOST_BITS_PER_WIDE_INT == 64
4276 else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */
4278 else /* num < 0 && TARGET_ARCH64 */
4281 /* Sethi does not sign extend, so we must use a little trickery
4282 to use it for negative numbers. Invert the constant before
4283 loading it in, then use xor immediate to invert the loaded bits
4284 (along with the upper 32 bits) to the desired constant. This
4285 works because the sethi and immediate fields overlap. */
4286 HOST_WIDE_INT inv = ~num;
4287 HOST_WIDE_INT low = -0x400 + (num & 0x3ff);
4289 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4291 fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4294 #if HOST_BITS_PER_WIDE_INT == 64
4295 else /* TARGET_ARCH64 */
4297 /* We don't use the 'setx' macro because if requires a scratch register.
4298 This is the translation of sparc_emit_set_const64_longway into asm.
4299 Hopefully we will soon have prologue/epilogue emitted as RTL. */
4300 HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff;
4301 HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff;
4302 HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff;
4305 /* We don't use the 'set' macro because it appears to be broken
4306 in the Solaris 7 assembler. */
4307 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4309 if ((high_bits & 0x3ff) != 0)
4310 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4311 reg, high_bits, reg);
4315 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4316 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4326 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4327 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4335 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4337 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4343 /* Output any necessary .register pseudo-ops. */
4345 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4347 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4353 /* Check if %g[2367] were used without
4354 .register being printed for them already. */
4355 for (i = 2; i < 8; i++)
4357 if (regs_ever_live [i]
4358 && ! sparc_hard_reg_printed [i])
4360 sparc_hard_reg_printed [i] = 1;
4361 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4368 /* This function generates the assembly code for function entry.
4369 FILE is a stdio stream to output the code to.
4370 SIZE is an int: how many units of temporary storage to allocate.
4371 Refer to the array `regs_ever_live' to determine which registers
4372 to save; `regs_ever_live[I]' is nonzero if register number I
4373 is ever used in the function. This macro is responsible for
4374 knowing which registers should not be saved even if used. */
4376 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4377 of memory. If any fpu reg is used in the function, we allocate
4378 such a block here, at the bottom of the frame, just in case it's needed.
4380 If this function is a leaf procedure, then we may choose not
4381 to do a "save" insn. The decision about whether or not
4382 to do this is made in regclass.c. */
4385 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4388 sparc_flat_function_prologue (file, size);
4390 sparc_nonflat_function_prologue (file, size,
4391 current_function_uses_only_leaf_regs);
4394 /* Output code for the function prologue. */
4397 sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
4400 sparc_output_scratch_registers (file);
4402 /* Need to use actual_fsize, since we are also allocating
4403 space for our callee (and our own register save area). */
4404 actual_fsize = compute_frame_size (size, leaf_function);
4408 frame_base_name = "%sp";
4409 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4413 frame_base_name = "%fp";
4414 frame_base_offset = SPARC_STACK_BIAS;
4417 /* This is only for the human reader. */
4418 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4420 if (actual_fsize == 0)
4422 else if (! leaf_function)
4424 if (actual_fsize <= 4096)
4425 fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4427 else if (actual_fsize <= 8192)
4429 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4430 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4431 actual_fsize - 4096);
4435 build_big_number (file, -actual_fsize, "%g1");
4436 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4439 else /* leaf function */
4441 if (actual_fsize <= 4096)
4442 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4444 else if (actual_fsize <= 8192)
4446 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4447 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4448 actual_fsize - 4096);
4452 build_big_number (file, -actual_fsize, "%g1");
4453 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4457 if (dwarf2out_do_frame () && actual_fsize)
4459 char *label = dwarf2out_cfi_label ();
4461 /* The canonical frame address refers to the top of the frame. */
4462 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4463 : HARD_FRAME_POINTER_REGNUM),
4466 if (! leaf_function)
4468 /* Note the register window save. This tells the unwinder that
4469 it needs to restore the window registers from the previous
4470 frame's window save area at 0(cfa). */
4471 dwarf2out_window_save (label);
4473 /* The return address (-8) is now in %i7. */
4474 dwarf2out_return_reg (label, 31);
4478 /* If doing anything with PIC, do it now. */
4480 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4482 /* Call saved registers are saved just above the outgoing argument area. */
4485 HOST_WIDE_INT offset, real_offset;
4489 real_offset = -apparent_fsize;
4490 offset = -apparent_fsize + frame_base_offset;
4491 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4493 /* ??? This might be optimized a little as %g1 might already have a
4494 value close enough that a single add insn will do. */
4495 /* ??? Although, all of this is probably only a temporary fix
4496 because if %g1 can hold a function result, then
4497 output_function_epilogue will lose (the result will get
4499 build_big_number (file, offset, "%g1");
4500 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4506 base = frame_base_name;
4509 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4510 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4515 /* Output code to restore any call saved registers. */
4518 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4520 HOST_WIDE_INT offset;
4524 offset = -apparent_fsize + frame_base_offset;
4525 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4527 build_big_number (file, offset, "%g1");
4528 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4534 base = frame_base_name;
4537 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4538 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4541 /* This function generates the assembly code for function exit,
4542 on machines that need it.
4544 The function epilogue should not depend on the current stack pointer!
4545 It should use the frame pointer only. This is mandatory because
4546 of alloca; we also take advantage of it to omit stack adjustments
4547 before returning. */
4550 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4553 sparc_flat_function_epilogue (file, size);
4555 sparc_nonflat_function_epilogue (file, size,
4556 current_function_uses_only_leaf_regs);
4559 /* Output code for the function epilogue. */
4562 sparc_nonflat_function_epilogue (FILE *file,
4563 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4568 if (current_function_epilogue_delay_list == 0)
4570 /* If code does not drop into the epilogue, we need
4571 do nothing except output pending case vectors.
4573 We have to still output a dummy nop for the sake of
4574 sane backtraces. Otherwise, if the last two instructions
4575 of a function were call foo; dslot; this can make the return
4576 PC of foo (ie. address of call instruction plus 8) point to
4577 the first instruction in the next function. */
4578 rtx insn, last_real_insn;
4580 insn = get_last_insn ();
4582 last_real_insn = prev_real_insn (insn);
4584 && GET_CODE (last_real_insn) == INSN
4585 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4586 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4588 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4589 fputs("\tnop\n", file);
4591 if (GET_CODE (insn) == NOTE)
4592 insn = prev_nonnote_insn (insn);
4593 if (insn && GET_CODE (insn) == BARRIER)
4594 goto output_vectors;
4598 output_restore_regs (file, leaf_function);
4600 /* Work out how to skip the caller's unimp instruction if required. */
4602 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4604 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4606 if (! leaf_function)
4608 if (current_function_calls_eh_return)
4610 if (current_function_epilogue_delay_list)
4612 if (SKIP_CALLERS_UNIMP_P)
4615 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4617 /* If we wound up with things in our delay slot, flush them here. */
4618 else if (current_function_epilogue_delay_list)
4620 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4622 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4624 epilogue_renumber (&delay, 0);
4625 fputs (SKIP_CALLERS_UNIMP_P
4626 ? "\treturn\t%i7+12\n"
4627 : "\treturn\t%i7+8\n", file);
4628 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4629 file, 1, 0, 0, NULL);
4635 if (GET_CODE (delay) != SET)
4638 src = SET_SRC (delay);
4639 if (GET_CODE (src) == ASHIFT)
4641 if (XEXP (src, 1) != const1_rtx)
4644 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4648 insn = gen_rtx_PARALLEL (VOIDmode,
4649 gen_rtvec (2, delay,
4650 gen_rtx_RETURN (VOIDmode)));
4651 insn = emit_jump_insn (insn);
4653 sparc_emitting_epilogue = true;
4654 final_scan_insn (insn, file, 1, 0, 1, NULL);
4655 sparc_emitting_epilogue = false;
4658 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4659 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4661 fprintf (file, "\t%s\n\trestore\n", ret);
4663 /* All of the following cases are for leaf functions. */
4664 else if (current_function_calls_eh_return)
4666 else if (current_function_epilogue_delay_list)
4668 /* eligible_for_epilogue_delay_slot ensures that if this is a
4669 leaf function, then we will only have insn in the delay slot
4670 if the frame size is zero, thus no adjust for the stack is
4672 if (actual_fsize != 0)
4674 fprintf (file, "\t%s\n", ret);
4675 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4676 file, 1, 0, 1, NULL);
4678 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4679 avoid generating confusing assembly language output. */
4680 else if (actual_fsize == 0)
4681 fprintf (file, "\t%s\n\tnop\n", ret);
4682 else if (actual_fsize <= 4096)
4683 fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4685 else if (actual_fsize <= 8192)
4686 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4687 ret, actual_fsize - 4096);
4690 build_big_number (file, actual_fsize, "%g1");
4691 fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret);
4695 sparc_output_deferred_case_vectors ();
4698 /* Output a sibling call. */
4701 output_sibcall (rtx insn, rtx call_operand)
4703 int leaf_regs = current_function_uses_only_leaf_regs;
4705 int delay_slot = dbr_sequence_length () > 0;
4709 /* Call to restore global regs might clobber
4710 the delay slot. Instead of checking for this
4711 output the delay slot now. */
4714 rtx delay = NEXT_INSN (insn);
4719 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4720 PATTERN (delay) = gen_blockage ();
4721 INSN_CODE (delay) = -1;
4724 output_restore_regs (asm_out_file, leaf_regs);
4727 operands[0] = call_operand;
4731 #ifdef HAVE_AS_RELAX_OPTION
4732 /* If as and ld are relaxing tail call insns into branch always,
4733 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4734 be optimized. With sethi/jmpl as nor ld has no easy way how to
4735 find out if somebody does not branch between the sethi and jmpl. */
4738 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4740 HOST_WIDE_INT size = 0;
4742 if ((actual_fsize || ! spare_slot) && delay_slot)
4744 rtx delay = NEXT_INSN (insn);
4749 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4750 PATTERN (delay) = gen_blockage ();
4751 INSN_CODE (delay) = -1;
4756 if (actual_fsize <= 4096)
4757 size = actual_fsize;
4758 else if (actual_fsize <= 8192)
4760 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4761 size = actual_fsize - 4096;
4765 build_big_number (asm_out_file, actual_fsize, "%g1");
4766 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4771 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4772 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4774 fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4775 else if (! delay_slot)
4776 fputs ("\t nop\n", asm_out_file);
4781 fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4782 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4783 it into branch if possible. */
4784 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4785 output_asm_insn ("call\t%a0, 0", operands);
4786 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4791 output_asm_insn ("call\t%a0, 0", operands);
4794 rtx delay = NEXT_INSN (insn), pat;
4799 pat = PATTERN (delay);
4800 if (GET_CODE (pat) != SET)
4803 operands[0] = SET_DEST (pat);
4804 pat = SET_SRC (pat);
4805 switch (GET_CODE (pat))
4808 operands[1] = XEXP (pat, 0);
4809 operands[2] = XEXP (pat, 1);
4810 output_asm_insn (" restore %r1, %2, %Y0", operands);
4813 operands[1] = XEXP (pat, 0);
4814 operands[2] = XEXP (pat, 1);
4815 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4818 operands[1] = XEXP (pat, 0);
4819 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4823 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4826 PATTERN (delay) = gen_blockage ();
4827 INSN_CODE (delay) = -1;
4830 fputs ("\t restore\n", asm_out_file);
4834 /* Functions for handling argument passing.
4836 For v8 the first six args are normally in registers and the rest are
4837 pushed. Any arg that starts within the first 6 words is at least
4838 partially passed in a register unless its data type forbids.
4840 For v9, the argument registers are laid out as an array of 16 elements
4841 and arguments are added sequentially. The first 6 int args and up to the
4842 first 16 fp args (depending on size) are passed in regs.
4844 Slot Stack Integral Float Float in structure Double Long Double
4845 ---- ----- -------- ----- ------------------ ------ -----------
4846 15 [SP+248] %f31 %f30,%f31 %d30
4847 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4848 13 [SP+232] %f27 %f26,%f27 %d26
4849 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4850 11 [SP+216] %f23 %f22,%f23 %d22
4851 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4852 9 [SP+200] %f19 %f18,%f19 %d18
4853 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4854 7 [SP+184] %f15 %f14,%f15 %d14
4855 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4856 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4857 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4858 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4859 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4860 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4861 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4863 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4865 Integral arguments are always passed as 64 bit quantities appropriately
4868 Passing of floating point values is handled as follows.
4869 If a prototype is in scope:
4870 If the value is in a named argument (i.e. not a stdarg function or a
4871 value not part of the `...') then the value is passed in the appropriate
4873 If the value is part of the `...' and is passed in one of the first 6
4874 slots then the value is passed in the appropriate int reg.
4875 If the value is part of the `...' and is not passed in one of the first 6
4876 slots then the value is passed in memory.
4877 If a prototype is not in scope:
4878 If the value is one of the first 6 arguments the value is passed in the
4879 appropriate integer reg and the appropriate fp reg.
4880 If the value is not one of the first 6 arguments the value is passed in
4881 the appropriate fp reg and in memory.
4884 /* Maximum number of int regs for args. */
4885 #define SPARC_INT_ARG_MAX 6
4886 /* Maximum number of fp regs for args. */
4887 #define SPARC_FP_ARG_MAX 16
4889 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4891 /* Handle the INIT_CUMULATIVE_ARGS macro.
4892 Initialize a variable CUM of type CUMULATIVE_ARGS
4893 for a call to a function whose data type is FNTYPE.
4894 For a library call, FNTYPE is 0. */
4897 init_cumulative_args (struct sparc_args *cum, tree fntype,
4898 rtx libname ATTRIBUTE_UNUSED,
4899 tree fndecl ATTRIBUTE_UNUSED)
4902 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4903 cum->libcall_p = fntype == 0;
4906 /* Scan the record type TYPE and return the following predicates:
4907 - INTREGS_P: the record contains at least one field or sub-field
4908 that is eligible for promotion in integer registers.
4909 - FP_REGS_P: the record contains at least one field or sub-field
4910 that is eligible for promotion in floating-point registers.
4911 - PACKED_P: the record contains at least one field that is packed.
4913 Sub-fields are not taken into account for the PACKED_P predicate. */
4916 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
4920 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4922 if (TREE_CODE (field) == FIELD_DECL)
4924 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4925 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
4926 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
4931 if (packed_p && DECL_PACKED (field))
4937 /* Compute the slot number to pass an argument in.
4938 Return the slot number or -1 if passing on the stack.
4940 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4941 the preceding args and about the function being called.
4942 MODE is the argument's machine mode.
4943 TYPE is the data type of the argument (as a tree).
4944 This is null for libcalls where that information may
4946 NAMED is nonzero if this argument is a named parameter
4947 (otherwise it is an extra parameter matching an ellipsis).
4948 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4949 *PREGNO records the register number to use if scalar type.
4950 *PPADDING records the amount of padding needed in words. */
4953 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4954 tree type, int named, int incoming_p,
4955 int *pregno, int *ppadding)
4957 int regbase = (incoming_p
4958 ? SPARC_INCOMING_INT_ARG_FIRST
4959 : SPARC_OUTGOING_INT_ARG_FIRST);
4960 int slotno = cum->words;
4965 if (type != 0 && TREE_ADDRESSABLE (type))
4968 && type != 0 && mode == BLKmode
4969 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4975 /* MODE is VOIDmode when generating the actual call.
4979 case TImode : case CTImode :
4980 if (TARGET_ARCH64 && (slotno & 1) != 0)
4981 slotno++, *ppadding = 1;
4984 case QImode : case CQImode :
4985 case HImode : case CHImode :
4986 case SImode : case CSImode :
4987 case DImode : case CDImode :
4988 if (slotno >= SPARC_INT_ARG_MAX)
4990 regno = regbase + slotno;
4993 case TFmode : case TCmode :
4994 if (TARGET_ARCH64 && (slotno & 1) != 0)
4995 slotno++, *ppadding = 1;
4998 case SFmode : case SCmode :
4999 case DFmode : case DCmode :
5002 if (slotno >= SPARC_INT_ARG_MAX)
5004 regno = regbase + slotno;
5008 if (TARGET_FPU && named)
5010 if (slotno >= SPARC_FP_ARG_MAX)
5012 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5018 if (slotno >= SPARC_INT_ARG_MAX)
5020 regno = regbase + slotno;
5026 /* For sparc64, objects requiring 16 byte alignment get it. */
5029 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
5030 slotno++, *ppadding = 1;
5034 || (type && TREE_CODE (type) == UNION_TYPE))
5036 if (slotno >= SPARC_INT_ARG_MAX)
5038 regno = regbase + slotno;
5042 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5044 /* First see what kinds of registers we would need. */
5045 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5047 /* The ABI obviously doesn't specify how packed structures
5048 are passed. These are defined to be passed in int regs
5049 if possible, otherwise memory. */
5050 if (packed_p || !named)
5051 fpregs_p = 0, intregs_p = 1;
5053 /* If all arg slots are filled, then must pass on stack. */
5054 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5056 /* If there are only int args and all int arg slots are filled,
5057 then must pass on stack. */
5058 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5060 /* Note that even if all int arg slots are filled, fp members may
5061 still be passed in regs if such regs are available.
5062 *PREGNO isn't set because there may be more than one, it's up
5063 to the caller to compute them. */
5076 /* Handle recursive register counting for structure field layout. */
5078 struct function_arg_record_value_parms
5080 rtx ret; /* return expression being built. */
5081 int slotno; /* slot number of the argument. */
5082 int named; /* whether the argument is named. */
5083 int regbase; /* regno of the base register. */
5084 int stack; /* 1 if part of the argument is on the stack. */
5085 int intoffset; /* offset of the first pending integer field. */
5086 unsigned int nregs; /* number of words passed in registers. */
5089 static void function_arg_record_value_3
5090 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5091 static void function_arg_record_value_2
5092 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5093 static void function_arg_record_value_1
5094 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5095 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5096 static rtx function_arg_union_value (int, enum machine_mode, int, int);
5098 /* A subroutine of function_arg_record_value. Traverse the structure
5099 recursively and determine how many registers will be required. */
5102 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5103 struct function_arg_record_value_parms *parms,
5108 /* We need to compute how many registers are needed so we can
5109 allocate the PARALLEL but before we can do that we need to know
5110 whether there are any packed fields. The ABI obviously doesn't
5111 specify how structures are passed in this case, so they are
5112 defined to be passed in int regs if possible, otherwise memory,
5113 regardless of whether there are fp values present. */
5116 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5118 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5125 /* Compute how many registers we need. */
5126 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5128 if (TREE_CODE (field) == FIELD_DECL)
5130 HOST_WIDE_INT bitpos = startbitpos;
5132 if (DECL_SIZE (field) != 0
5133 && host_integerp (bit_position (field), 1))
5134 bitpos += int_bit_position (field);
5136 /* ??? FIXME: else assume zero offset. */
5138 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5139 function_arg_record_value_1 (TREE_TYPE (field),
5143 else if (FLOAT_TYPE_P (TREE_TYPE (field))
5148 if (parms->intoffset != -1)
5150 unsigned int startbit, endbit;
5151 int intslots, this_slotno;
5153 startbit = parms->intoffset & -BITS_PER_WORD;
5154 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5156 intslots = (endbit - startbit) / BITS_PER_WORD;
5157 this_slotno = parms->slotno + parms->intoffset
5160 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5162 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5163 /* We need to pass this field on the stack. */
5167 parms->nregs += intslots;
5168 parms->intoffset = -1;
5171 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5172 If it wasn't true we wouldn't be here. */
5174 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5179 if (parms->intoffset == -1)
5180 parms->intoffset = bitpos;
5186 /* A subroutine of function_arg_record_value. Assign the bits of the
5187 structure between parms->intoffset and bitpos to integer registers. */
5190 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5191 struct function_arg_record_value_parms *parms)
5193 enum machine_mode mode;
5195 unsigned int startbit, endbit;
5196 int this_slotno, intslots, intoffset;
5199 if (parms->intoffset == -1)
5202 intoffset = parms->intoffset;
5203 parms->intoffset = -1;
5205 startbit = intoffset & -BITS_PER_WORD;
5206 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5207 intslots = (endbit - startbit) / BITS_PER_WORD;
5208 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5210 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5214 /* If this is the trailing part of a word, only load that much into
5215 the register. Otherwise load the whole register. Note that in
5216 the latter case we may pick up unwanted bits. It's not a problem
5217 at the moment but may wish to revisit. */
5219 if (intoffset % BITS_PER_WORD != 0)
5220 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5225 intoffset /= BITS_PER_UNIT;
5228 regno = parms->regbase + this_slotno;
5229 reg = gen_rtx_REG (mode, regno);
5230 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5231 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5234 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5239 while (intslots > 0);
5242 /* A subroutine of function_arg_record_value. Traverse the structure
5243 recursively and assign bits to floating point registers. Track which
5244 bits in between need integer registers; invoke function_arg_record_value_3
5245 to make that happen. */
5248 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5249 struct function_arg_record_value_parms *parms,
5255 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5257 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5264 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5266 if (TREE_CODE (field) == FIELD_DECL)
5268 HOST_WIDE_INT bitpos = startbitpos;
5270 if (DECL_SIZE (field) != 0
5271 && host_integerp (bit_position (field), 1))
5272 bitpos += int_bit_position (field);
5274 /* ??? FIXME: else assume zero offset. */
5276 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5277 function_arg_record_value_2 (TREE_TYPE (field),
5281 else if (FLOAT_TYPE_P (TREE_TYPE (field))
5286 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5288 enum machine_mode mode = DECL_MODE (field);
5291 function_arg_record_value_3 (bitpos, parms);
5292 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
5293 + ((mode == SFmode || mode == SCmode)
5294 && (bitpos & 32) != 0);
5297 case SCmode: mode = SFmode; break;
5298 case DCmode: mode = DFmode; break;
5299 case TCmode: mode = TFmode; break;
5302 reg = gen_rtx_REG (mode, regno);
5303 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5304 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5305 GEN_INT (bitpos / BITS_PER_UNIT));
5307 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5309 regno += GET_MODE_SIZE (mode) / 4;
5310 reg = gen_rtx_REG (mode, regno);
5311 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5312 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5313 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5320 if (parms->intoffset == -1)
5321 parms->intoffset = bitpos;
5327 /* Used by function_arg and function_value to implement the complex
5328 conventions of the 64-bit ABI for passing and returning structures.
5329 Return an expression valid as a return value for the two macros
5330 FUNCTION_ARG and FUNCTION_VALUE.
5332 TYPE is the data type of the argument (as a tree).
5333 This is null for libcalls where that information may
5335 MODE is the argument's machine mode.
5336 SLOTNO is the index number of the argument's slot in the parameter array.
5337 NAMED is nonzero if this argument is a named parameter
5338 (otherwise it is an extra parameter matching an ellipsis).
5339 REGBASE is the regno of the base register for the parameter array. */
5342 function_arg_record_value (tree type, enum machine_mode mode,
5343 int slotno, int named, int regbase)
5345 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5346 struct function_arg_record_value_parms parms;
5349 parms.ret = NULL_RTX;
5350 parms.slotno = slotno;
5351 parms.named = named;
5352 parms.regbase = regbase;
5355 /* Compute how many registers we need. */
5357 parms.intoffset = 0;
5358 function_arg_record_value_1 (type, 0, &parms, false);
5360 /* Take into account pending integer fields. */
5361 if (parms.intoffset != -1)
5363 unsigned int startbit, endbit;
5364 int intslots, this_slotno;
5366 startbit = parms.intoffset & -BITS_PER_WORD;
5367 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5368 intslots = (endbit - startbit) / BITS_PER_WORD;
5369 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5371 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5373 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5374 /* We need to pass this field on the stack. */
5378 parms.nregs += intslots;
5380 nregs = parms.nregs;
5382 /* Allocate the vector and handle some annoying special cases. */
5385 /* ??? Empty structure has no value? Duh? */
5388 /* Though there's nothing really to store, return a word register
5389 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5390 leads to breakage due to the fact that there are zero bytes to
5392 return gen_rtx_REG (mode, regbase);
5396 /* ??? C++ has structures with no fields, and yet a size. Give up
5397 for now and pass everything back in integer registers. */
5398 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5400 if (nregs + slotno > SPARC_INT_ARG_MAX)
5401 nregs = SPARC_INT_ARG_MAX - slotno;
5406 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5408 /* If at least one field must be passed on the stack, generate
5409 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5410 also be passed on the stack. We can't do much better because the
5411 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5412 of structures for which the fields passed exclusively in registers
5413 are not at the beginning of the structure. */
5415 XVECEXP (parms.ret, 0, 0)
5416 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5418 /* Fill in the entries. */
5420 parms.intoffset = 0;
5421 function_arg_record_value_2 (type, 0, &parms, false);
5422 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5424 if (parms.nregs != nregs)
5430 /* Used by function_arg and function_value to implement the conventions
5431 of the 64-bit ABI for passing and returning unions.
5432 Return an expression valid as a return value for the two macros
5433 FUNCTION_ARG and FUNCTION_VALUE.
5435 SIZE is the size in bytes of the union.
5436 MODE is the argument's machine mode.
5437 REGNO is the hard register the union will be passed in. */
5440 function_arg_union_value (int size, enum machine_mode mode, int slotno,
5443 int nwords = ROUND_ADVANCE (size), i;
5446 /* See comment in previous function for empty structures. */
5448 return gen_rtx_REG (mode, regno);
5450 if (slotno == SPARC_INT_ARG_MAX - 1)
5453 /* Unions are passed left-justified. */
5454 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5456 for (i = 0; i < nwords; i++)
5457 XVECEXP (regs, 0, i)
5458 = gen_rtx_EXPR_LIST (VOIDmode,
5459 gen_rtx_REG (word_mode, regno + i),
5460 GEN_INT (UNITS_PER_WORD * i));
5465 /* Handle the FUNCTION_ARG macro.
5466 Determine where to put an argument to a function.
5467 Value is zero to push the argument on the stack,
5468 or a hard register in which to store the argument.
5470 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5471 the preceding args and about the function being called.
5472 MODE is the argument's machine mode.
5473 TYPE is the data type of the argument (as a tree).
5474 This is null for libcalls where that information may
5476 NAMED is nonzero if this argument is a named parameter
5477 (otherwise it is an extra parameter matching an ellipsis).
5478 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5481 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5482 tree type, int named, int incoming_p)
5484 int regbase = (incoming_p
5485 ? SPARC_INCOMING_INT_ARG_FIRST
5486 : SPARC_OUTGOING_INT_ARG_FIRST);
5487 int slotno, regno, padding;
5490 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5498 reg = gen_rtx_REG (mode, regno);
5502 if (type && TREE_CODE (type) == RECORD_TYPE)
5504 /* Structures up to 16 bytes in size are passed in arg slots on the
5505 stack and are promoted to registers where possible. */
5507 if (int_size_in_bytes (type) > 16)
5508 abort (); /* shouldn't get here */
5510 return function_arg_record_value (type, mode, slotno, named, regbase);
5512 else if (type && TREE_CODE (type) == UNION_TYPE)
5514 HOST_WIDE_INT size = int_size_in_bytes (type);
5517 abort (); /* shouldn't get here */
5519 return function_arg_union_value (size, mode, slotno, regno);
5521 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5522 but also have the slot allocated for them.
5523 If no prototype is in scope fp values in register slots get passed
5524 in two places, either fp regs and int regs or fp regs and memory. */
5525 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5526 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5527 && SPARC_FP_REG_P (regno))
5529 reg = gen_rtx_REG (mode, regno);
5530 if (cum->prototype_p || cum->libcall_p)
5532 /* "* 2" because fp reg numbers are recorded in 4 byte
5535 /* ??? This will cause the value to be passed in the fp reg and
5536 in the stack. When a prototype exists we want to pass the
5537 value in the reg but reserve space on the stack. That's an
5538 optimization, and is deferred [for a bit]. */
5539 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5540 return gen_rtx_PARALLEL (mode,
5542 gen_rtx_EXPR_LIST (VOIDmode,
5543 NULL_RTX, const0_rtx),
5544 gen_rtx_EXPR_LIST (VOIDmode,
5548 /* ??? It seems that passing back a register even when past
5549 the area declared by REG_PARM_STACK_SPACE will allocate
5550 space appropriately, and will not copy the data onto the
5551 stack, exactly as we desire.
5553 This is due to locate_and_pad_parm being called in
5554 expand_call whenever reg_parm_stack_space > 0, which
5555 while beneficial to our example here, would seem to be
5556 in error from what had been intended. Ho hum... -- r~ */
5564 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5568 /* On incoming, we don't need to know that the value
5569 is passed in %f0 and %i0, and it confuses other parts
5570 causing needless spillage even on the simplest cases. */
5574 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5575 + (regno - SPARC_FP_ARG_FIRST) / 2);
5577 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5578 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5580 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5584 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5585 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5586 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5592 /* Scalar or complex int. */
5593 reg = gen_rtx_REG (mode, regno);
5599 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5600 For an arg passed partly in registers and partly in memory,
5601 this is the number of registers used.
5602 For args passed entirely in registers or entirely in memory, zero.
5604 Any arg that starts in the first 6 regs but won't entirely fit in them
5605 needs partial registers on v8. On v9, structures with integer
5606 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5607 values that begin in the last fp reg [where "last fp reg" varies with the
5608 mode] will be split between that reg and memory. */
5611 function_arg_partial_nregs (const struct sparc_args *cum,
5612 enum machine_mode mode, tree type, int named)
5614 int slotno, regno, padding;
5616 /* We pass 0 for incoming_p here, it doesn't matter. */
5617 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5624 if ((slotno + (mode == BLKmode
5625 ? ROUND_ADVANCE (int_size_in_bytes (type))
5626 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5627 > NPARM_REGS (SImode))
5628 return NPARM_REGS (SImode) - slotno;
5633 if (type && AGGREGATE_TYPE_P (type))
5635 int size = int_size_in_bytes (type);
5636 int align = TYPE_ALIGN (type);
5639 slotno += slotno & 1;
5640 if (size > 8 && size <= 16
5641 && slotno == SPARC_INT_ARG_MAX - 1)
5644 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5645 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5646 && ! (TARGET_FPU && named)))
5648 /* The complex types are passed as packed types. */
5649 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
5652 if (GET_MODE_ALIGNMENT (mode) == 128)
5654 slotno += slotno & 1;
5656 /* ??? The mode needs 3 slots? */
5657 if (slotno == SPARC_INT_ARG_MAX - 2)
5662 if (slotno == SPARC_INT_ARG_MAX - 1)
5666 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5668 if (GET_MODE_ALIGNMENT (mode) == 128)
5669 slotno += slotno & 1;
5670 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5678 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5679 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5680 quad-precision floats by invisible reference.
5681 v9: Aggregates greater than 16 bytes are passed by reference.
5682 For Pascal, also pass arrays by reference. */
5685 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5686 enum machine_mode mode, tree type,
5687 int named ATTRIBUTE_UNUSED)
5691 return ((type && AGGREGATE_TYPE_P (type))
5693 || GET_MODE_SIZE (mode) > 8);
5697 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5698 /* Consider complex values as aggregates, so care
5699 for CTImode and TCmode. */
5700 || GET_MODE_SIZE (mode) > 16
5702 && AGGREGATE_TYPE_P (type)
5703 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5707 /* Handle the FUNCTION_ARG_ADVANCE macro.
5708 Update the data in CUM to advance over an argument
5709 of mode MODE and data type TYPE.
5710 TYPE is null for libcalls where that information may not be available. */
5713 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5714 tree type, int named)
5716 int slotno, regno, padding;
5718 /* We pass 0 for incoming_p here, it doesn't matter. */
5719 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5721 /* If register required leading padding, add it. */
5723 cum->words += padding;
5727 cum->words += (mode != BLKmode
5728 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5729 : ROUND_ADVANCE (int_size_in_bytes (type)));
5733 if (type && AGGREGATE_TYPE_P (type))
5735 int size = int_size_in_bytes (type);
5739 else if (size <= 16)
5741 else /* passed by reference */
5746 cum->words += (mode != BLKmode
5747 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5748 : ROUND_ADVANCE (int_size_in_bytes (type)));
5753 /* Handle the FUNCTION_ARG_PADDING macro.
5754 For the 64 bit ABI structs are always stored left shifted in their
5758 function_arg_padding (enum machine_mode mode, tree type)
5760 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5763 /* Fall back to the default. */
5764 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5767 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5768 For v9, function return values are subject to the same rules as arguments,
5769 except that up to 32-bytes may be returned in registers. */
5772 function_value (tree type, enum machine_mode mode, int incoming_p)
5776 if (TARGET_ARCH64 && type)
5778 int regbase = (incoming_p
5779 ? SPARC_OUTGOING_INT_ARG_FIRST
5780 : SPARC_INCOMING_INT_ARG_FIRST);
5782 if (TREE_CODE (type) == RECORD_TYPE)
5784 /* Structures up to 32 bytes in size are passed in registers,
5785 promoted to fp registers where possible. */
5787 if (int_size_in_bytes (type) > 32)
5788 abort (); /* shouldn't get here */
5790 return function_arg_record_value (type, mode, 0, 1, regbase);
5792 else if (TREE_CODE (type) == UNION_TYPE)
5794 HOST_WIDE_INT size = int_size_in_bytes (type);
5797 abort (); /* shouldn't get here */
5799 return function_arg_union_value (size, mode, 0, regbase);
5801 else if (AGGREGATE_TYPE_P (type))
5803 /* All other aggregate types are passed in an integer register
5804 in a mode corresponding to the size of the type. */
5805 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5810 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5812 /* ??? We probably should have made the same ABI change in
5813 3.4.0 as the one we made for unions. The latter was
5814 required by the SCD though, while the former is not
5815 specified, so we favored compatibility and efficiency.
5817 Now we're stuck for aggregates larger than 16 bytes,
5818 because OImode vanished in the meantime. Let's not
5819 try to be unduly clever, and simply follow the ABI
5820 for unions in that case. */
5821 if (mode == BLKmode)
5822 return function_arg_union_value (bytes, mode, 0, regbase);
5824 else if (GET_MODE_CLASS (mode) == MODE_INT
5825 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5830 regno = BASE_RETURN_VALUE_REG (mode);
5832 regno = BASE_OUTGOING_VALUE_REG (mode);
5834 return gen_rtx_REG (mode, regno);
5837 /* Do what is necessary for `va_start'. We look at the current function
5838 to determine if stdarg or varargs is used and return the address of
5839 the first unnamed parameter. */
5842 sparc_builtin_saveregs (void)
5844 int first_reg = current_function_args_info.words;
5848 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5849 emit_move_insn (gen_rtx_MEM (word_mode,
5850 gen_rtx_PLUS (Pmode,
5852 GEN_INT (FIRST_PARM_OFFSET (0)
5855 gen_rtx_REG (word_mode,
5856 BASE_INCOMING_ARG_REG (word_mode) + regno));
5858 address = gen_rtx_PLUS (Pmode,
5860 GEN_INT (FIRST_PARM_OFFSET (0)
5861 + UNITS_PER_WORD * first_reg));
5866 /* Implement `va_start' for varargs and stdarg. */
5869 sparc_va_start (tree valist, rtx nextarg)
5871 nextarg = expand_builtin_saveregs ();
5872 std_expand_builtin_va_start (valist, nextarg);
5875 /* Implement `va_arg'. */
5878 sparc_va_arg (tree valist, tree type)
5880 HOST_WIDE_INT size, rsize, align;
5885 /* Round up sizeof(type) to a word. */
5886 size = int_size_in_bytes (type);
5887 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5892 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5893 align = 2 * UNITS_PER_WORD;
5895 /* Consider complex values as aggregates, so care
5896 for CTImode and TCmode. */
5897 if ((unsigned HOST_WIDE_INT) size > 16)
5900 size = rsize = UNITS_PER_WORD;
5903 else if (AGGREGATE_TYPE_P (type))
5905 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5906 are given whole slots as needed. */
5908 size = rsize = UNITS_PER_WORD;
5915 if (AGGREGATE_TYPE_P (type)
5916 || TYPE_MODE (type) == SCmode
5917 || GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5920 size = rsize = UNITS_PER_WORD;
5927 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5928 build_int_2 (align - 1, 0)));
5929 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5930 build_int_2 (-align, -1)));
5933 addr = incr = save_expr (incr);
5934 if (BYTES_BIG_ENDIAN && size < rsize)
5936 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5937 build_int_2 (rsize - size, 0)));
5939 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5940 build_int_2 (rsize, 0)));
5942 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5943 TREE_SIDE_EFFECTS (incr) = 1;
5944 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5946 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5948 /* If the address isn't aligned properly for the type,
5949 we may need to copy to a temporary.
5950 FIXME: This is inefficient. Usually we can do this
5953 && TYPE_ALIGN (type) > BITS_PER_WORD
5956 /* FIXME: We really need to specify that the temporary is live
5957 for the whole function because expand_builtin_va_arg wants
5958 the alias set to be get_varargs_alias_set (), but in this
5959 case the alias set is that for TYPE and if the memory gets
5960 reused it will be reused with alias set TYPE. */
5961 rtx tmp = assign_temp (type, 0, 1, 0);
5964 addr_rtx = force_reg (Pmode, addr_rtx);
5965 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5966 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5967 set_mem_align (addr_rtx, BITS_PER_WORD);
5968 tmp = shallow_copy_rtx (tmp);
5969 PUT_MODE (tmp, BLKmode);
5970 set_mem_alias_set (tmp, 0);
5972 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5974 if (dest_addr != NULL_RTX)
5975 addr_rtx = dest_addr;
5977 addr_rtx = XCEXP (tmp, 0, MEM);
5982 addr_rtx = force_reg (Pmode, addr_rtx);
5983 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5984 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5990 /* Return the string to output an unconditional branch to LABEL, which is
5991 the operand number of the label.
5993 DEST is the destination insn (i.e. the label), INSN is the source. */
5996 output_ubranch (rtx dest, int label, rtx insn)
5998 static char string[64];
6002 /* TurboSPARC is reported to have problems with
6005 i.e. an empty loop with the annul bit set. The workaround is to use
6009 if (! TARGET_V9 && flag_delayed_branch
6010 && (INSN_ADDRESSES (INSN_UID (dest))
6011 == INSN_ADDRESSES (INSN_UID (insn))))
6013 strcpy (string, "b\t");
6018 bool v9_form = false;
6020 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6022 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6023 - INSN_ADDRESSES (INSN_UID (insn)));
6024 /* Leave some instructions for "slop". */
6025 if (delta >= -260000 && delta < 260000)
6030 strcpy (string, "ba%*,pt\t%%xcc, ");
6032 strcpy (string, "b%*\t");
6035 p = strchr (string, '\0');
6049 /* Return the string to output a conditional branch to LABEL, which is
6050 the operand number of the label. OP is the conditional expression.
6051 XEXP (OP, 0) is assumed to be a condition code register (integer or
6052 floating point) and its mode specifies what kind of comparison we made.
6054 DEST is the destination insn (i.e. the label), INSN is the source.
6056 REVERSED is nonzero if we should reverse the sense of the comparison.
6058 ANNUL is nonzero if we should generate an annulling branch.
6060 NOOP is nonzero if we have to follow this branch by a noop. */
6063 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6066 static char string[50];
6067 enum rtx_code code = GET_CODE (op);
6068 rtx cc_reg = XEXP (op, 0);
6069 enum machine_mode mode = GET_MODE (cc_reg);
6070 const char *labelno, *branch;
6071 int spaces = 8, far;
6074 /* v9 branches are limited to +-1MB. If it is too far away,
6087 fbne,a,pn %fcc2, .LC29
6095 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6098 /* Reversal of FP compares takes care -- an ordered compare
6099 becomes an unordered compare and vice versa. */
6100 if (mode == CCFPmode || mode == CCFPEmode)
6101 code = reverse_condition_maybe_unordered (code);
6103 code = reverse_condition (code);
6106 /* Start by writing the branch condition. */
6107 if (mode == CCFPmode || mode == CCFPEmode)
6158 /* ??? !v9: FP branches cannot be preceded by another floating point
6159 insn. Because there is currently no concept of pre-delay slots,
6160 we can fix this only by always emitting a nop before a floating
6165 strcpy (string, "nop\n\t");
6166 strcat (string, branch);
6179 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6191 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6212 strcpy (string, branch);
6214 spaces -= strlen (branch);
6215 p = strchr (string, '\0');
6217 /* Now add the annulling, the label, and a possible noop. */
6230 if (! far && insn && INSN_ADDRESSES_SET_P ())
6232 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6233 - INSN_ADDRESSES (INSN_UID (insn)));
6234 /* Leave some instructions for "slop". */
6235 if (delta < -260000 || delta >= 260000)
6239 if (mode == CCFPmode || mode == CCFPEmode)
6241 static char v9_fcc_labelno[] = "%%fccX, ";
6242 /* Set the char indicating the number of the fcc reg to use. */
6243 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6244 labelno = v9_fcc_labelno;
6247 if (REGNO (cc_reg) == SPARC_FCC_REG)
6253 else if (mode == CCXmode || mode == CCX_NOOVmode)
6255 labelno = "%%xcc, ";
6261 labelno = "%%icc, ";
6266 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6269 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6282 strcpy (p, labelno);
6283 p = strchr (p, '\0');
6286 strcpy (p, ".+12\n\tnop\n\tb\t");
6293 /* Set the char indicating the number of the operand containing the
6298 strcpy (p, "\n\tnop");
6303 /* Emit a library call comparison between floating point X and Y.
6304 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6305 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6306 values as arguments instead of the TFmode registers themselves,
6307 that's why we cannot call emit_float_lib_cmp. */
6309 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6312 rtx slot0, slot1, result, tem, tem2;
6313 enum machine_mode mode;
6318 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6322 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6326 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6330 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6334 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6338 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6349 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6359 if (GET_CODE (x) != MEM)
6361 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6362 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6367 if (GET_CODE (y) != MEM)
6369 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6370 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6375 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6377 XEXP (slot0, 0), Pmode,
6378 XEXP (slot1, 0), Pmode);
6384 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6386 x, TFmode, y, TFmode);
6392 /* Immediately move the result of the libcall into a pseudo
6393 register so reload doesn't clobber the value if it needs
6394 the return register for a spill reg. */
6395 result = gen_reg_rtx (mode);
6396 emit_move_insn (result, hard_libcall_value (mode));
6401 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6405 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6410 emit_cmp_insn (result, const1_rtx,
6411 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6414 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6417 tem = gen_reg_rtx (mode);
6419 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6421 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6422 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6426 tem = gen_reg_rtx (mode);
6428 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6430 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6431 tem2 = gen_reg_rtx (mode);
6433 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6435 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6436 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6442 /* Generate an unsigned DImode to FP conversion. This is the same code
6443 optabs would emit if we didn't have TFmode patterns. */
6446 sparc_emit_floatunsdi (rtx *operands)
6448 rtx neglab, donelab, i0, i1, f0, in, out;
6449 enum machine_mode mode;
6452 in = force_reg (DImode, operands[1]);
6453 mode = GET_MODE (out);
6454 neglab = gen_label_rtx ();
6455 donelab = gen_label_rtx ();
6456 i0 = gen_reg_rtx (DImode);
6457 i1 = gen_reg_rtx (DImode);
6458 f0 = gen_reg_rtx (mode);
6460 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6462 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6463 emit_jump_insn (gen_jump (donelab));
6466 emit_label (neglab);
6468 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6469 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6470 emit_insn (gen_iordi3 (i0, i0, i1));
6471 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6472 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6474 emit_label (donelab);
6477 /* Return the string to output a conditional branch to LABEL, testing
6478 register REG. LABEL is the operand number of the label; REG is the
6479 operand number of the reg. OP is the conditional expression. The mode
6480 of REG says what kind of comparison we made.
6482 DEST is the destination insn (i.e. the label), INSN is the source.
6484 REVERSED is nonzero if we should reverse the sense of the comparison.
6486 ANNUL is nonzero if we should generate an annulling branch.
6488 NOOP is nonzero if we have to follow this branch by a noop. */
6491 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6492 int annul, int noop, rtx insn)
6494 static char string[50];
6495 enum rtx_code code = GET_CODE (op);
6496 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6501 /* branch on register are limited to +-128KB. If it is too far away,
6514 brgez,a,pn %o1, .LC29
6520 ba,pt %xcc, .LC29 */
6522 far = get_attr_length (insn) >= 3;
6524 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6526 code = reverse_condition (code);
6528 /* Only 64 bit versions of these instructions exist. */
6532 /* Start by writing the branch condition. */
6537 strcpy (string, "brnz");
6541 strcpy (string, "brz");
6545 strcpy (string, "brgez");
6549 strcpy (string, "brlz");
6553 strcpy (string, "brlez");
6557 strcpy (string, "brgz");
6564 p = strchr (string, '\0');
6566 /* Now add the annulling, reg, label, and nop. */
6573 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6576 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6581 *p = p < string + 8 ? '\t' : ' ';
6589 int veryfar = 1, delta;
6591 if (INSN_ADDRESSES_SET_P ())
6593 delta = (INSN_ADDRESSES (INSN_UID (dest))
6594 - INSN_ADDRESSES (INSN_UID (insn)));
6595 /* Leave some instructions for "slop". */
6596 if (delta >= -260000 && delta < 260000)
6600 strcpy (p, ".+12\n\tnop\n\t");
6611 strcpy (p, "ba,pt\t%%xcc, ");
6621 strcpy (p, "\n\tnop");
6626 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6627 Such instructions cannot be used in the delay slot of return insn on v9.
6628 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6632 epilogue_renumber (register rtx *where, int test)
6634 register const char *fmt;
6636 register enum rtx_code code;
6641 code = GET_CODE (*where);
6646 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6648 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6649 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6657 /* Do not replace the frame pointer with the stack pointer because
6658 it can cause the delayed instruction to load below the stack.
6659 This occurs when instructions like:
6661 (set (reg/i:SI 24 %i0)
6662 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6663 (const_int -20 [0xffffffec])) 0))
6665 are in the return delayed slot. */
6667 if (GET_CODE (XEXP (*where, 0)) == REG
6668 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6669 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6670 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6675 if (SPARC_STACK_BIAS
6676 && GET_CODE (XEXP (*where, 0)) == REG
6677 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6685 fmt = GET_RTX_FORMAT (code);
6687 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6692 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6693 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6696 else if (fmt[i] == 'e'
6697 && epilogue_renumber (&(XEXP (*where, i)), test))
6703 /* Leaf functions and non-leaf functions have different needs. */
6706 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6709 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6711 static const int *const reg_alloc_orders[] = {
6712 reg_leaf_alloc_order,
6713 reg_nonleaf_alloc_order};
6716 order_regs_for_local_alloc (void)
6718 static int last_order_nonleaf = 1;
6720 if (regs_ever_live[15] != last_order_nonleaf)
6722 last_order_nonleaf = !last_order_nonleaf;
6723 memcpy ((char *) reg_alloc_order,
6724 (const char *) reg_alloc_orders[last_order_nonleaf],
6725 FIRST_PSEUDO_REGISTER * sizeof (int));
6729 /* Return 1 if REG and MEM are legitimate enough to allow the various
6730 mem<-->reg splits to be run. */
6733 sparc_splitdi_legitimate (rtx reg, rtx mem)
6735 /* Punt if we are here by mistake. */
6736 if (! reload_completed)
6739 /* We must have an offsettable memory reference. */
6740 if (! offsettable_memref_p (mem))
6743 /* If we have legitimate args for ldd/std, we do not want
6744 the split to happen. */
6745 if ((REGNO (reg) % 2) == 0
6746 && mem_min_alignment (mem, 8))
6753 /* Return 1 if x and y are some kind of REG and they refer to
6754 different hard registers. This test is guaranteed to be
6755 run after reload. */
6758 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6760 if (GET_CODE (x) != REG)
6762 if (GET_CODE (y) != REG)
6764 if (REGNO (x) == REGNO (y))
6769 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6770 This makes them candidates for using ldd and std insns.
6772 Note reg1 and reg2 *must* be hard registers. */
6775 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6777 /* We might have been passed a SUBREG. */
6778 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6781 if (REGNO (reg1) % 2 != 0)
6784 /* Integer ldd is deprecated in SPARC V9 */
6785 if (TARGET_V9 && REGNO (reg1) < 32)
6788 return (REGNO (reg1) == REGNO (reg2) - 1);
6791 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6794 This can only happen when addr1 and addr2, the addresses in mem1
6795 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6796 addr1 must also be aligned on a 64-bit boundary.
6798 Also iff dependent_reg_rtx is not null it should not be used to
6799 compute the address for mem1, i.e. we cannot optimize a sequence
6811 But, note that the transformation from:
6816 is perfectly fine. Thus, the peephole2 patterns always pass us
6817 the destination register of the first load, never the second one.
6819 For stores we don't have a similar problem, so dependent_reg_rtx is
6823 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6827 HOST_WIDE_INT offset1;
6829 /* The mems cannot be volatile. */
6830 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6833 /* MEM1 should be aligned on a 64-bit boundary. */
6834 if (MEM_ALIGN (mem1) < 64)
6837 addr1 = XEXP (mem1, 0);
6838 addr2 = XEXP (mem2, 0);
6840 /* Extract a register number and offset (if used) from the first addr. */
6841 if (GET_CODE (addr1) == PLUS)
6843 /* If not a REG, return zero. */
6844 if (GET_CODE (XEXP (addr1, 0)) != REG)
6848 reg1 = REGNO (XEXP (addr1, 0));
6849 /* The offset must be constant! */
6850 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6852 offset1 = INTVAL (XEXP (addr1, 1));
6855 else if (GET_CODE (addr1) != REG)
6859 reg1 = REGNO (addr1);
6860 /* This was a simple (mem (reg)) expression. Offset is 0. */
6864 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6865 if (GET_CODE (addr2) != PLUS)
6868 if (GET_CODE (XEXP (addr2, 0)) != REG
6869 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6872 if (reg1 != REGNO (XEXP (addr2, 0)))
6875 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6878 /* The first offset must be evenly divisible by 8 to ensure the
6879 address is 64 bit aligned. */
6880 if (offset1 % 8 != 0)
6883 /* The offset for the second addr must be 4 more than the first addr. */
6884 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6887 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6892 /* Return 1 if reg is a pseudo, or is the first register in
6893 a hard register pair. This makes it a candidate for use in
6894 ldd and std insns. */
6897 register_ok_for_ldd (rtx reg)
6899 /* We might have been passed a SUBREG. */
6900 if (GET_CODE (reg) != REG)
6903 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6904 return (REGNO (reg) % 2 == 0);
6909 /* Print operand X (an rtx) in assembler syntax to file FILE.
6910 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6911 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6914 print_operand (FILE *file, rtx x, int code)
6919 /* Output a 'nop' if there's nothing for the delay slot. */
6920 if (dbr_sequence_length () == 0)
6921 fputs ("\n\t nop", file);
6924 /* Output an annul flag if there's nothing for the delay slot and we
6925 are optimizing. This is always used with '(' below. */
6926 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6927 this is a dbx bug. So, we only do this when optimizing. */
6928 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6929 Always emit a nop in case the next instruction is a branch. */
6930 if (dbr_sequence_length () == 0
6931 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6935 /* Output a 'nop' if there's nothing for the delay slot and we are
6936 not optimizing. This is always used with '*' above. */
6937 if (dbr_sequence_length () == 0
6938 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6939 fputs ("\n\t nop", file);
6942 /* Output the Embedded Medium/Anywhere code model base register. */
6943 fputs (EMBMEDANY_BASE_REG, file);
6946 /* Print out what we are using as the frame pointer. This might
6947 be %fp, or might be %sp+offset. */
6948 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6949 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset);
6952 /* Print some local dynamic TLS name. */
6953 assemble_name (file, get_some_local_dynamic_name ());
6956 /* Adjust the operand to take into account a RESTORE operation. */
6957 if (GET_CODE (x) == CONST_INT)
6959 else if (GET_CODE (x) != REG)
6960 output_operand_lossage ("invalid %%Y operand");
6961 else if (REGNO (x) < 8)
6962 fputs (reg_names[REGNO (x)], file);
6963 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6964 fputs (reg_names[REGNO (x)-16], file);
6966 output_operand_lossage ("invalid %%Y operand");
6969 /* Print out the low order register name of a register pair. */
6970 if (WORDS_BIG_ENDIAN)
6971 fputs (reg_names[REGNO (x)+1], file);
6973 fputs (reg_names[REGNO (x)], file);
6976 /* Print out the high order register name of a register pair. */
6977 if (WORDS_BIG_ENDIAN)
6978 fputs (reg_names[REGNO (x)], file);
6980 fputs (reg_names[REGNO (x)+1], file);
6983 /* Print out the second register name of a register pair or quad.
6984 I.e., R (%o0) => %o1. */
6985 fputs (reg_names[REGNO (x)+1], file);
6988 /* Print out the third register name of a register quad.
6989 I.e., S (%o0) => %o2. */
6990 fputs (reg_names[REGNO (x)+2], file);
6993 /* Print out the fourth register name of a register quad.
6994 I.e., T (%o0) => %o3. */
6995 fputs (reg_names[REGNO (x)+3], file);
6998 /* Print a condition code register. */
6999 if (REGNO (x) == SPARC_ICC_REG)
7001 /* We don't handle CC[X]_NOOVmode because they're not supposed
7003 if (GET_MODE (x) == CCmode)
7004 fputs ("%icc", file);
7005 else if (GET_MODE (x) == CCXmode)
7006 fputs ("%xcc", file);
7011 /* %fccN register */
7012 fputs (reg_names[REGNO (x)], file);
7015 /* Print the operand's address only. */
7016 output_address (XEXP (x, 0));
7019 /* In this case we need a register. Use %g0 if the
7020 operand is const0_rtx. */
7022 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7024 fputs ("%g0", file);
7031 switch (GET_CODE (x))
7033 case IOR: fputs ("or", file); break;
7034 case AND: fputs ("and", file); break;
7035 case XOR: fputs ("xor", file); break;
7036 default: output_operand_lossage ("invalid %%A operand");
7041 switch (GET_CODE (x))
7043 case IOR: fputs ("orn", file); break;
7044 case AND: fputs ("andn", file); break;
7045 case XOR: fputs ("xnor", file); break;
7046 default: output_operand_lossage ("invalid %%B operand");
7050 /* These are used by the conditional move instructions. */
7054 enum rtx_code rc = GET_CODE (x);
7058 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7059 if (mode == CCFPmode || mode == CCFPEmode)
7060 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7062 rc = reverse_condition (GET_CODE (x));
7066 case NE: fputs ("ne", file); break;
7067 case EQ: fputs ("e", file); break;
7068 case GE: fputs ("ge", file); break;
7069 case GT: fputs ("g", file); break;
7070 case LE: fputs ("le", file); break;
7071 case LT: fputs ("l", file); break;
7072 case GEU: fputs ("geu", file); break;
7073 case GTU: fputs ("gu", file); break;
7074 case LEU: fputs ("leu", file); break;
7075 case LTU: fputs ("lu", file); break;
7076 case LTGT: fputs ("lg", file); break;
7077 case UNORDERED: fputs ("u", file); break;
7078 case ORDERED: fputs ("o", file); break;
7079 case UNLT: fputs ("ul", file); break;
7080 case UNLE: fputs ("ule", file); break;
7081 case UNGT: fputs ("ug", file); break;
7082 case UNGE: fputs ("uge", file); break;
7083 case UNEQ: fputs ("ue", file); break;
7084 default: output_operand_lossage (code == 'c'
7085 ? "invalid %%c operand"
7086 : "invalid %%C operand");
7091 /* These are used by the movr instruction pattern. */
7095 enum rtx_code rc = (code == 'd'
7096 ? reverse_condition (GET_CODE (x))
7100 case NE: fputs ("ne", file); break;
7101 case EQ: fputs ("e", file); break;
7102 case GE: fputs ("gez", file); break;
7103 case LT: fputs ("lz", file); break;
7104 case LE: fputs ("lez", file); break;
7105 case GT: fputs ("gz", file); break;
7106 default: output_operand_lossage (code == 'd'
7107 ? "invalid %%d operand"
7108 : "invalid %%D operand");
7115 /* Print a sign-extended character. */
7116 int i = trunc_int_for_mode (INTVAL (x), QImode);
7117 fprintf (file, "%d", i);
7122 /* Operand must be a MEM; write its address. */
7123 if (GET_CODE (x) != MEM)
7124 output_operand_lossage ("invalid %%f operand");
7125 output_address (XEXP (x, 0));
7130 /* Print a sign-extended 32-bit value. */
7132 if (GET_CODE(x) == CONST_INT)
7134 else if (GET_CODE(x) == CONST_DOUBLE)
7135 i = CONST_DOUBLE_LOW (x);
7138 output_operand_lossage ("invalid %%s operand");
7141 i = trunc_int_for_mode (i, SImode);
7142 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7147 /* Do nothing special. */
7151 /* Undocumented flag. */
7152 output_operand_lossage ("invalid operand output code");
7155 if (GET_CODE (x) == REG)
7156 fputs (reg_names[REGNO (x)], file);
7157 else if (GET_CODE (x) == MEM)
7160 /* Poor Sun assembler doesn't understand absolute addressing. */
7161 if (CONSTANT_P (XEXP (x, 0)))
7162 fputs ("%g0+", file);
7163 output_address (XEXP (x, 0));
7166 else if (GET_CODE (x) == HIGH)
7168 fputs ("%hi(", file);
7169 output_addr_const (file, XEXP (x, 0));
7172 else if (GET_CODE (x) == LO_SUM)
7174 print_operand (file, XEXP (x, 0), 0);
7175 if (TARGET_CM_MEDMID)
7176 fputs ("+%l44(", file);
7178 fputs ("+%lo(", file);
7179 output_addr_const (file, XEXP (x, 1));
7182 else if (GET_CODE (x) == CONST_DOUBLE
7183 && (GET_MODE (x) == VOIDmode
7184 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7186 if (CONST_DOUBLE_HIGH (x) == 0)
7187 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7188 else if (CONST_DOUBLE_HIGH (x) == -1
7189 && CONST_DOUBLE_LOW (x) < 0)
7190 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7192 output_operand_lossage ("long long constant not a valid immediate operand");
7194 else if (GET_CODE (x) == CONST_DOUBLE)
7195 output_operand_lossage ("floating point constant not a valid immediate operand");
7196 else { output_addr_const (file, x); }
7199 /* Target hook for assembling integer objects. The sparc version has
7200 special handling for aligned DI-mode objects. */
7203 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7205 /* ??? We only output .xword's for symbols and only then in environments
7206 where the assembler can handle them. */
7207 if (aligned_p && size == 8
7208 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7212 assemble_integer_with_op ("\t.xword\t", x);
7217 assemble_aligned_integer (4, const0_rtx);
7218 assemble_aligned_integer (4, x);
7222 return default_assemble_integer (x, size, aligned_p);
7225 /* Return the value of a code used in the .proc pseudo-op that says
7226 what kind of result this function returns. For non-C types, we pick
7227 the closest C type. */
7229 #ifndef SHORT_TYPE_SIZE
7230 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7233 #ifndef INT_TYPE_SIZE
7234 #define INT_TYPE_SIZE BITS_PER_WORD
7237 #ifndef LONG_TYPE_SIZE
7238 #define LONG_TYPE_SIZE BITS_PER_WORD
7241 #ifndef LONG_LONG_TYPE_SIZE
7242 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7245 #ifndef FLOAT_TYPE_SIZE
7246 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7249 #ifndef DOUBLE_TYPE_SIZE
7250 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7253 #ifndef LONG_DOUBLE_TYPE_SIZE
7254 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7258 sparc_type_code (register tree type)
7260 register unsigned long qualifiers = 0;
7261 register unsigned shift;
7263 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7264 setting more, since some assemblers will give an error for this. Also,
7265 we must be careful to avoid shifts of 32 bits or more to avoid getting
7266 unpredictable results. */
7268 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7270 switch (TREE_CODE (type))
7276 qualifiers |= (3 << shift);
7281 qualifiers |= (2 << shift);
7285 case REFERENCE_TYPE:
7287 qualifiers |= (1 << shift);
7291 return (qualifiers | 8);
7294 case QUAL_UNION_TYPE:
7295 return (qualifiers | 9);
7298 return (qualifiers | 10);
7301 return (qualifiers | 16);
7304 /* If this is a range type, consider it to be the underlying
7306 if (TREE_TYPE (type) != 0)
7309 /* Carefully distinguish all the standard types of C,
7310 without messing up if the language is not C. We do this by
7311 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7312 look at both the names and the above fields, but that's redundant.
7313 Any type whose size is between two C types will be considered
7314 to be the wider of the two types. Also, we do not have a
7315 special code to use for "long long", so anything wider than
7316 long is treated the same. Note that we can't distinguish
7317 between "int" and "long" in this code if they are the same
7318 size, but that's fine, since neither can the assembler. */
7320 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7321 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7323 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7324 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7326 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7327 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7330 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7333 /* If this is a range type, consider it to be the underlying
7335 if (TREE_TYPE (type) != 0)
7338 /* Carefully distinguish all the standard types of C,
7339 without messing up if the language is not C. */
7341 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7342 return (qualifiers | 6);
7345 return (qualifiers | 7);
7347 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7348 /* ??? We need to distinguish between double and float complex types,
7349 but I don't know how yet because I can't reach this code from
7350 existing front-ends. */
7351 return (qualifiers | 7); /* Who knows? */
7353 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7354 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7355 case FILE_TYPE: /* GNU Pascal FILE type. */
7356 case SET_TYPE: /* GNU Pascal SET type. */
7357 case LANG_TYPE: /* ? */
7361 abort (); /* Not a type! */
7368 /* Nested function support. */
7370 /* Emit RTL insns to initialize the variable parts of a trampoline.
7371 FNADDR is an RTX for the address of the function's pure code.
7372 CXT is an RTX for the static chain value for the function.
7374 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7375 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7376 (to store insns). This is a bit excessive. Perhaps a different
7377 mechanism would be better here.
7379 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7382 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7384 /* SPARC 32-bit trampoline:
7387 sethi %hi(static), %g2
7389 or %g2, %lo(static), %g2
7391 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7392 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7396 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7397 expand_binop (SImode, ior_optab,
7398 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7399 size_int (10), 0, 1),
7400 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7401 NULL_RTX, 1, OPTAB_DIRECT));
7404 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7405 expand_binop (SImode, ior_optab,
7406 expand_shift (RSHIFT_EXPR, SImode, cxt,
7407 size_int (10), 0, 1),
7408 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7409 NULL_RTX, 1, OPTAB_DIRECT));
7412 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7413 expand_binop (SImode, ior_optab,
7414 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7415 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7416 NULL_RTX, 1, OPTAB_DIRECT));
7419 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7420 expand_binop (SImode, ior_optab,
7421 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7422 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7423 NULL_RTX, 1, OPTAB_DIRECT));
7425 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7426 aligned on a 16 byte boundary so one flush clears it all. */
7427 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7428 if (sparc_cpu != PROCESSOR_ULTRASPARC
7429 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7430 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7431 plus_constant (tramp, 8)))));
7433 /* Call __enable_execute_stack after writing onto the stack to make sure
7434 the stack address is accessible. */
7435 #ifdef ENABLE_EXECUTE_STACK
7436 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7437 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7442 /* The 64-bit version is simpler because it makes more sense to load the
7443 values as "immediate" data out of the trampoline. It's also easier since
7444 we can read the PC without clobbering a register. */
7447 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7449 /* SPARC 64-bit trampoline:
7458 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7459 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7460 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7461 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7462 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7463 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7464 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7465 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7466 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7467 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7468 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7470 if (sparc_cpu != PROCESSOR_ULTRASPARC
7471 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7472 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7474 /* Call __enable_execute_stack after writing onto the stack to make sure
7475 the stack address is accessible. */
7476 #ifdef ENABLE_EXECUTE_STACK
7477 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7478 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7482 /* Subroutines to support a flat (single) register window calling
7485 /* Single-register window sparc stack frames look like:
7487 Before call After call
7488 +-----------------------+ +-----------------------+
7490 mem | caller's temps. | | caller's temps. |
7492 +-----------------------+ +-----------------------+
7494 | arguments on stack. | | arguments on stack. |
7496 +-----------------------+FP+92->+-----------------------+
7497 | 6 words to save | | 6 words to save |
7498 | arguments passed | | arguments passed |
7499 | in registers, even | | in registers, even |
7500 | if not passed. | | if not passed. |
7501 SP+68->+-----------------------+FP+68->+-----------------------+
7502 | 1 word struct addr | | 1 word struct addr |
7503 +-----------------------+FP+64->+-----------------------+
7505 | 16 word reg save area | | 16 word reg save area |
7507 SP->+-----------------------+ FP->+-----------------------+
7509 | fp/alu reg moves |
7510 FP-16->+-----------------------+
7514 +-----------------------+
7516 | fp register save |
7518 +-----------------------+
7520 | gp register save |
7522 +-----------------------+
7524 | alloca allocations |
7526 +-----------------------+
7528 | arguments on stack |
7530 SP+92->+-----------------------+
7532 | arguments passed |
7533 | in registers, even |
7534 low | if not passed. |
7535 memory SP+68->+-----------------------+
7536 | 1 word struct addr |
7537 SP+64->+-----------------------+
7539 I 16 word reg save area |
7541 SP->+-----------------------+ */
7543 /* Structure to be filled in by sparc_flat_compute_frame_size with register
7544 save masks, and offsets for the current function. */
7546 struct sparc_frame_info
7548 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7549 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7550 int args_size; /* # bytes that outgoing arguments take up. */
7551 int extra_size; /* # bytes of extra gunk. */
7552 int gp_reg_size; /* # bytes needed to store gp regs. */
7553 int fp_reg_size; /* # bytes needed to store fp regs. */
7554 unsigned long gmask; /* Mask of saved gp registers. */
7555 unsigned long fmask; /* Mask of saved fp registers. */
7556 int reg_offset; /* Offset from new sp to store regs. */
7557 int initialized; /* Nonzero if frame size already calculated. */
7560 /* Current frame information calculated by sparc_flat_compute_frame_size. */
7561 struct sparc_frame_info current_frame_info;
7563 /* Zero structure to initialize current_frame_info. */
7564 struct sparc_frame_info zero_frame_info;
7566 #define RETURN_ADDR_REGNUM 15
7567 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
7568 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
7570 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
7573 sparc_flat_must_save_register_p (int regno)
7575 /* General case: call-saved registers live at some point. */
7576 if (!call_used_regs[regno] && regs_ever_live[regno])
7579 /* Frame pointer register (%i7) if needed. */
7580 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7583 /* PIC register (%l7) if needed. */
7584 if (regno == (int) PIC_OFFSET_TABLE_REGNUM
7585 && flag_pic && current_function_uses_pic_offset_table)
7588 /* Return address register (%o7) if needed. */
7589 if (regno == RETURN_ADDR_REGNUM
7590 && (regs_ever_live[RETURN_ADDR_REGNUM]
7591 /* When the PIC offset table is used, the PIC register
7592 is set by using a bare call that clobbers %o7. */
7593 || (flag_pic && current_function_uses_pic_offset_table)))
7599 /* Return the bytes needed to compute the frame pointer from the current
7603 sparc_flat_compute_frame_size (HOST_WIDE_INT size)
7604 /* # of var. bytes allocated. */
7607 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7608 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7609 int args_size; /* # bytes that outgoing arguments take up. */
7610 int extra_size; /* # extra bytes. */
7611 int gp_reg_size; /* # bytes needed to store gp regs. */
7612 int fp_reg_size; /* # bytes needed to store fp regs. */
7613 unsigned long gmask; /* Mask of saved gp registers. */
7614 unsigned long fmask; /* Mask of saved fp registers. */
7615 int reg_offset; /* Offset to register save area. */
7616 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7618 /* This is the size of the 16 word reg save area, 1 word struct addr
7619 area, and 4 word fp/alu register copy area. */
7620 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
7630 if (!leaf_function_p ())
7632 /* Also include the size needed for the 6 parameter registers. */
7633 args_size = current_function_outgoing_args_size + 24;
7635 total_size = var_size + args_size;
7637 /* Calculate space needed for gp registers. */
7638 for (regno = 1; regno <= 31; regno++)
7640 if (sparc_flat_must_save_register_p (regno))
7642 /* If we need to save two regs in a row, ensure there's room to bump
7643 up the address to align it to a doubleword boundary. */
7644 if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1))
7646 if (gp_reg_size % 8 != 0)
7648 gp_reg_size += 2 * UNITS_PER_WORD;
7649 gmask |= 3 << regno;
7655 gp_reg_size += UNITS_PER_WORD;
7656 gmask |= 1 << regno;
7661 /* Calculate space needed for fp registers. */
7662 for (regno = 32; regno <= 63; regno++)
7664 if (regs_ever_live[regno] && !call_used_regs[regno])
7666 fp_reg_size += UNITS_PER_WORD;
7667 fmask |= 1 << (regno - 32);
7674 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7675 /* Ensure save area is 8 byte aligned if we need it. */
7677 if (need_aligned_p && n != 0)
7679 total_size += 8 - n;
7680 reg_offset += 8 - n;
7682 total_size += gp_reg_size + fp_reg_size;
7685 /* If we must allocate a stack frame at all, we must also allocate
7686 room for register window spillage, so as to be binary compatible
7687 with libraries and operating systems that do not use -mflat. */
7689 total_size += extra_size;
7693 total_size = SPARC_STACK_ALIGN (total_size);
7695 /* Save other computed information. */
7696 current_frame_info.total_size = total_size;
7697 current_frame_info.var_size = var_size;
7698 current_frame_info.args_size = args_size;
7699 current_frame_info.extra_size = extra_size;
7700 current_frame_info.gp_reg_size = gp_reg_size;
7701 current_frame_info.fp_reg_size = fp_reg_size;
7702 current_frame_info.gmask = gmask;
7703 current_frame_info.fmask = fmask;
7704 current_frame_info.reg_offset = reg_offset;
7705 current_frame_info.initialized = reload_completed;
7707 /* Ok, we're done. */
7711 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7714 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7715 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7716 [BASE_REG+OFFSET] will always be a valid address.
7718 WORD_OP is either "st" for save, "ld" for restore.
7719 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7722 sparc_flat_save_restore (FILE *file, const char *base_reg, int offset,
7723 unsigned long gmask, unsigned long fmask,
7724 const char *word_op, const char *doubleword_op,
7725 HOST_WIDE_INT base_offset)
7729 if (gmask == 0 && fmask == 0)
7732 /* Save registers starting from high to low. We've already saved the
7733 previous frame pointer and previous return address for the debugger's
7734 sake. The debugger allows us to not need a nop in the epilog if at least
7735 one register is reloaded in addition to return address. */
7739 for (regno = 1; regno <= 31; regno++)
7741 if ((gmask & (1L << regno)) != 0)
7743 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7745 /* We can save two registers in a row. If we're not at a
7746 double word boundary, move to one.
7747 sparc_flat_compute_frame_size ensures there's room to do
7749 if (offset % 8 != 0)
7750 offset += UNITS_PER_WORD;
7752 if (word_op[0] == 's')
7754 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7755 doubleword_op, reg_names[regno],
7757 if (dwarf2out_do_frame ())
7759 char *l = dwarf2out_cfi_label ();
7760 dwarf2out_reg_save (l, regno, offset + base_offset);
7762 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7766 fprintf (file, "\t%s\t[%s+%d], %s\n",
7767 doubleword_op, base_reg, offset,
7770 offset += 2 * UNITS_PER_WORD;
7775 if (word_op[0] == 's')
7777 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7778 word_op, reg_names[regno],
7780 if (dwarf2out_do_frame ())
7781 dwarf2out_reg_save ("", regno, offset + base_offset);
7784 fprintf (file, "\t%s\t[%s+%d], %s\n",
7785 word_op, base_reg, offset, reg_names[regno]);
7787 offset += UNITS_PER_WORD;
7795 for (regno = 32; regno <= 63; regno++)
7797 if ((fmask & (1L << (regno - 32))) != 0)
7799 if (word_op[0] == 's')
7801 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7802 word_op, reg_names[regno],
7804 if (dwarf2out_do_frame ())
7805 dwarf2out_reg_save ("", regno, offset + base_offset);
7808 fprintf (file, "\t%s\t[%s+%d], %s\n",
7809 word_op, base_reg, offset, reg_names[regno]);
7811 offset += UNITS_PER_WORD;
7817 /* Set up the stack and frame (if desired) for the function. */
7820 sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
7822 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7823 unsigned long gmask = current_frame_info.gmask;
7825 sparc_output_scratch_registers (file);
7827 /* This is only for the human reader. */
7828 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7829 fprintf (file, "\t%s# vars= "HOST_WIDE_INT_PRINT_DEC", "
7830 "regs= %d/%d, args= %d, extra= %d\n",
7832 current_frame_info.var_size,
7833 current_frame_info.gp_reg_size / 4,
7834 current_frame_info.fp_reg_size / 4,
7835 current_function_outgoing_args_size,
7836 current_frame_info.extra_size);
7838 size = SPARC_STACK_ALIGN (size);
7839 size = (! current_frame_info.initialized
7840 ? sparc_flat_compute_frame_size (size)
7841 : current_frame_info.total_size);
7843 /* These cases shouldn't happen. Catch them now. */
7844 if (size == 0 && (gmask || current_frame_info.fmask))
7847 /* Allocate our stack frame by decrementing %sp.
7848 At present, the only algorithm gdb can use to determine if this is a
7849 flat frame is if we always set %i7 if we set %sp. This can be optimized
7850 in the future by putting in some sort of debugging information that says
7851 this is a `flat' function. However, there is still the case of debugging
7852 code without such debugging information (including cases where most fns
7853 have such info, but there is one that doesn't). So, always do this now
7854 so we don't get a lot of code out there that gdb can't handle.
7855 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7856 distinguish us from a non-flat function but there won't (and shouldn't)
7857 be any differences anyway. The return pc is saved (if necessary) right
7858 after %i7 so gdb won't have to look too far to find it. */
7861 int reg_offset = current_frame_info.reg_offset;
7862 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7863 static const char *const t1_str = "%g1";
7865 /* Things get a little tricky if local variables take up more than ~4096
7866 bytes and outgoing arguments take up more than ~4096 bytes. When that
7867 happens, the register save area can't be accessed from either end of
7868 the frame. Handle this by decrementing %sp to the start of the gp
7869 register save area, save the regs, update %i7, and then set %sp to its
7870 final value. Given that we only have one scratch register to play
7871 with it is the cheapest solution, and it helps gdb out as it won't
7872 slow down recognition of flat functions.
7873 Don't change the order of insns emitted here without checking with
7874 the gdb folk first. */
7876 /* Is the entire register save area offsettable from %sp? */
7877 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
7881 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7882 sp_str, size, sp_str);
7883 if (gmask & HARD_FRAME_POINTER_MASK)
7885 fprintf (file, "\tst\t%s, [%s+%d]\n",
7886 fp_str, sp_str, reg_offset);
7887 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7888 "\t%s# set up frame pointer\n",
7889 sp_str, size, fp_str, ASM_COMMENT_START);
7895 build_big_number (file, size, t1_str);
7896 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7897 if (gmask & HARD_FRAME_POINTER_MASK)
7899 fprintf (file, "\tst\t%s, [%s+%d]\n",
7900 fp_str, sp_str, reg_offset);
7901 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7902 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7906 if (dwarf2out_do_frame ())
7908 char *l = dwarf2out_cfi_label ();
7909 if (gmask & HARD_FRAME_POINTER_MASK)
7911 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7912 reg_offset - 4 - size);
7913 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7916 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7918 if (gmask & RETURN_ADDR_MASK)
7920 fprintf (file, "\tst\t%s, [%s+%d]\n",
7921 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7922 if (dwarf2out_do_frame ())
7923 dwarf2out_return_save ("", reg_offset - size);
7926 sparc_flat_save_restore (file, sp_str, reg_offset,
7927 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7928 current_frame_info.fmask,
7929 "st", "std", -size);
7933 /* Subtract %sp in two steps, but make sure there is always a
7934 64-byte register save area, and %sp is properly aligned. */
7936 /* Amount to decrement %sp by, the first time. */
7937 HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7939 /* Amount to decrement %sp by, the second time. */
7940 HOST_WIDE_INT size2 = size - size1;
7942 /* Offset to register save area from %sp after first decrement. */
7943 int offset = (int)(size1 - (size - reg_offset));
7947 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7948 sp_str, size1, sp_str);
7949 if (gmask & HARD_FRAME_POINTER_MASK)
7951 fprintf (file, "\tst\t%s, [%s+%d]\n"
7952 "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7953 "\t%s# set up frame pointer\n",
7954 fp_str, sp_str, offset, sp_str, size1,
7955 fp_str, ASM_COMMENT_START);
7961 build_big_number (file, size1, t1_str);
7962 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7963 if (gmask & HARD_FRAME_POINTER_MASK)
7965 fprintf (file, "\tst\t%s, [%s+%d]\n"
7966 "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7967 fp_str, sp_str, offset, sp_str, t1_str,
7968 fp_str, ASM_COMMENT_START);
7972 if (dwarf2out_do_frame ())
7974 char *l = dwarf2out_cfi_label ();
7975 if (gmask & HARD_FRAME_POINTER_MASK)
7977 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7978 offset - 4 - size1);
7979 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7982 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7984 if (gmask & RETURN_ADDR_MASK)
7986 fprintf (file, "\tst\t%s, [%s+%d]\n",
7987 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
7988 if (dwarf2out_do_frame ())
7989 /* offset - size1 == reg_offset - size
7990 if reg_offset were updated above like offset. */
7991 dwarf2out_return_save ("", offset - size1);
7994 sparc_flat_save_restore (file, sp_str, offset,
7995 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7996 current_frame_info.fmask,
7997 "st", "std", -size1);
7999 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
8000 sp_str, size2, sp_str);
8003 build_big_number (file, size2, t1_str);
8004 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8006 if (dwarf2out_do_frame ())
8007 if (! (gmask & HARD_FRAME_POINTER_MASK))
8008 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
8012 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
8015 /* Do any necessary cleanup after a function to restore stack, frame,
8019 sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
8021 rtx epilogue_delay = current_function_epilogue_delay_list;
8022 int noepilogue = FALSE;
8024 /* This is only for the human reader. */
8025 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
8027 /* The epilogue does not depend on any registers, but the stack
8028 registers, so we assume that if we have 1 pending nop, it can be
8029 ignored, and 2 it must be filled (2 nops occur for integer
8030 multiply and divide). */
8032 size = SPARC_STACK_ALIGN (size);
8033 size = (!current_frame_info.initialized
8034 ? sparc_flat_compute_frame_size (size)
8035 : current_frame_info.total_size);
8037 if (size == 0 && epilogue_delay == 0)
8039 rtx insn = get_last_insn ();
8041 /* If the last insn was a BARRIER, we don't have to write any code
8042 because a jump (aka return) was put there. */
8043 if (GET_CODE (insn) == NOTE)
8044 insn = prev_nonnote_insn (insn);
8045 if (insn && GET_CODE (insn) == BARRIER)
8051 int reg_offset = current_frame_info.reg_offset;
8053 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
8054 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
8055 static const char *const t1_str = "%g1";
8057 /* In the reload sequence, we don't need to fill the load delay
8058 slots for most of the loads, also see if we can fill the final
8059 delay slot if not otherwise filled by the reload sequence. */
8062 build_big_number (file, size, t1_str);
8064 if (frame_pointer_needed)
8067 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
8068 fp_str, t1_str, sp_str, ASM_COMMENT_START);
8070 fprintf (file,"\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
8071 "\t\t%s# sp not trusted here\n",
8072 fp_str, size, sp_str, ASM_COMMENT_START);
8075 /* Is the entire register save area offsettable from %sp? */
8076 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
8082 /* Restore %sp in two steps, but make sure there is always a
8083 64-byte register save area, and %sp is properly aligned. */
8085 /* Amount to increment %sp by, the first time. */
8086 reg_offset1 = ((reg_offset - 64 - 16) + 15) & -16;
8088 /* Offset to register save area from %sp. */
8089 reg_offset = reg_offset1 - reg_offset;
8091 if (reg_offset1 > 4096)
8093 build_big_number (file, reg_offset1, t1_str);
8094 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8097 fprintf (file, "\tsub\t%s, -%d, %s\n", sp_str, reg_offset1, sp_str);
8100 /* We must restore the frame pointer and return address reg first
8101 because they are treated specially by the prologue output code. */
8102 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
8104 fprintf (file, "\tld\t[%s+%d], %s\n",
8105 sp_str, reg_offset, fp_str);
8108 if (current_frame_info.gmask & RETURN_ADDR_MASK)
8110 fprintf (file, "\tld\t[%s+%d], %s\n",
8111 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
8115 /* Restore any remaining saved registers. */
8116 sparc_flat_save_restore (file, sp_str, reg_offset,
8117 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
8118 current_frame_info.fmask,
8121 /* If we had to increment %sp in two steps, record it so the second
8122 restoration in the epilogue finishes up. */
8123 if (reg_offset1 > 0)
8125 size -= reg_offset1;
8127 build_big_number (file, size, t1_str);
8130 if (current_function_returns_struct)
8131 fprintf (file, "\tjmp\t%%o7+12\n");
8133 fprintf (file, "\tretl\n");
8135 /* If the only register saved is the return address, we need a
8136 nop, unless we have an instruction to put into it. Otherwise
8137 we don't since reloading multiple registers doesn't reference
8138 the register being loaded. */
8144 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1, NULL);
8147 else if (size > 4096)
8148 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8151 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
8152 sp_str, size, sp_str);
8155 fprintf (file, "\tnop\n");
8158 /* Reset state info for each function. */
8159 current_frame_info = zero_frame_info;
8161 sparc_output_deferred_case_vectors ();
8164 /* Define the number of delay slots needed for the function epilogue.
8166 On the sparc, we need a slot if either no stack has been allocated,
8167 or the only register saved is the return register. */
8170 sparc_flat_epilogue_delay_slots (void)
8172 if (!current_frame_info.initialized)
8173 (void) sparc_flat_compute_frame_size (get_frame_size ());
8175 if (current_frame_info.total_size == 0)
8181 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
8182 Any single length instruction which doesn't reference the stack or frame
8186 sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
8188 rtx pat = PATTERN (trial);
8190 if (get_attr_length (trial) != 1)
8193 if (! reg_mentioned_p (stack_pointer_rtx, pat)
8194 && ! reg_mentioned_p (frame_pointer_rtx, pat))
8200 /* Adjust the cost of a scheduling dependency. Return the new cost of
8201 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8204 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8206 enum attr_type insn_type;
8208 if (! recog_memoized (insn))
8211 insn_type = get_attr_type (insn);
8213 if (REG_NOTE_KIND (link) == 0)
8215 /* Data dependency; DEP_INSN writes a register that INSN reads some
8218 /* if a load, then the dependence must be on the memory address;
8219 add an extra "cycle". Note that the cost could be two cycles
8220 if the reg was written late in an instruction group; we ca not tell
8222 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8225 /* Get the delay only if the address of the store is the dependence. */
8226 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8228 rtx pat = PATTERN(insn);
8229 rtx dep_pat = PATTERN (dep_insn);
8231 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8232 return cost; /* This should not happen! */
8234 /* The dependency between the two instructions was on the data that
8235 is being stored. Assume that this implies that the address of the
8236 store is not dependent. */
8237 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8240 return cost + 3; /* An approximation. */
8243 /* A shift instruction cannot receive its data from an instruction
8244 in the same cycle; add a one cycle penalty. */
8245 if (insn_type == TYPE_SHIFT)
8246 return cost + 3; /* Split before cascade into shift. */
8250 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8251 INSN writes some cycles later. */
8253 /* These are only significant for the fpu unit; writing a fp reg before
8254 the fpu has finished with it stalls the processor. */
8256 /* Reusing an integer register causes no problems. */
8257 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8265 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8267 enum attr_type insn_type, dep_type;
8268 rtx pat = PATTERN(insn);
8269 rtx dep_pat = PATTERN (dep_insn);
8271 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8274 insn_type = get_attr_type (insn);
8275 dep_type = get_attr_type (dep_insn);
8277 switch (REG_NOTE_KIND (link))
8280 /* Data dependency; DEP_INSN writes a register that INSN reads some
8287 /* Get the delay iff the address of the store is the dependence. */
8288 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8291 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8298 /* If a load, then the dependence must be on the memory address. If
8299 the addresses aren't equal, then it might be a false dependency */
8300 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8302 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8303 || GET_CODE (SET_DEST (dep_pat)) != MEM
8304 || GET_CODE (SET_SRC (pat)) != MEM
8305 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8306 XEXP (SET_SRC (pat), 0)))
8314 /* Compare to branch latency is 0. There is no benefit from
8315 separating compare and branch. */
8316 if (dep_type == TYPE_COMPARE)
8318 /* Floating point compare to branch latency is less than
8319 compare to conditional move. */
8320 if (dep_type == TYPE_FPCMP)
8329 /* Anti-dependencies only penalize the fpu unit. */
8330 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8342 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8346 case PROCESSOR_SUPERSPARC:
8347 cost = supersparc_adjust_cost (insn, link, dep, cost);
8349 case PROCESSOR_HYPERSPARC:
8350 case PROCESSOR_SPARCLITE86X:
8351 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8360 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8361 int sched_verbose ATTRIBUTE_UNUSED,
8362 int max_ready ATTRIBUTE_UNUSED)
8367 sparc_use_dfa_pipeline_interface (void)
8369 if ((1 << sparc_cpu) &
8370 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
8371 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8372 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
8373 (1 << PROCESSOR_ULTRASPARC3)))
8379 sparc_use_sched_lookahead (void)
8381 if (sparc_cpu == PROCESSOR_ULTRASPARC
8382 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8384 if ((1 << sparc_cpu) &
8385 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8386 (1 << PROCESSOR_SPARCLITE86X)))
8392 sparc_issue_rate (void)
8399 /* Assume V9 processors are capable of at least dual-issue. */
8401 case PROCESSOR_SUPERSPARC:
8403 case PROCESSOR_HYPERSPARC:
8404 case PROCESSOR_SPARCLITE86X:
8406 case PROCESSOR_ULTRASPARC:
8407 case PROCESSOR_ULTRASPARC3:
8413 set_extends (rtx insn)
8415 register rtx pat = PATTERN (insn);
8417 switch (GET_CODE (SET_SRC (pat)))
8419 /* Load and some shift instructions zero extend. */
8422 /* sethi clears the high bits */
8424 /* LO_SUM is used with sethi. sethi cleared the high
8425 bits and the values used with lo_sum are positive */
8427 /* Store flag stores 0 or 1 */
8437 rtx op0 = XEXP (SET_SRC (pat), 0);
8438 rtx op1 = XEXP (SET_SRC (pat), 1);
8439 if (GET_CODE (op1) == CONST_INT)
8440 return INTVAL (op1) >= 0;
8441 if (GET_CODE (op0) != REG)
8443 if (sparc_check_64 (op0, insn) == 1)
8445 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8450 rtx op0 = XEXP (SET_SRC (pat), 0);
8451 rtx op1 = XEXP (SET_SRC (pat), 1);
8452 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8454 if (GET_CODE (op1) == CONST_INT)
8455 return INTVAL (op1) >= 0;
8456 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8459 return GET_MODE (SET_SRC (pat)) == SImode;
8460 /* Positive integers leave the high bits zero. */
8462 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8464 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8467 return - (GET_MODE (SET_SRC (pat)) == SImode);
8469 return sparc_check_64 (SET_SRC (pat), insn);
8475 /* We _ought_ to have only one kind per function, but... */
8476 static GTY(()) rtx sparc_addr_diff_list;
8477 static GTY(()) rtx sparc_addr_list;
8480 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8482 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8484 sparc_addr_diff_list
8485 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8487 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8491 sparc_output_addr_vec (rtx vec)
8493 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8494 int idx, vlen = XVECLEN (body, 0);
8496 #ifdef ASM_OUTPUT_ADDR_VEC_START
8497 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8500 #ifdef ASM_OUTPUT_CASE_LABEL
8501 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8504 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8507 for (idx = 0; idx < vlen; idx++)
8509 ASM_OUTPUT_ADDR_VEC_ELT
8510 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8513 #ifdef ASM_OUTPUT_ADDR_VEC_END
8514 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8519 sparc_output_addr_diff_vec (rtx vec)
8521 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8522 rtx base = XEXP (XEXP (body, 0), 0);
8523 int idx, vlen = XVECLEN (body, 1);
8525 #ifdef ASM_OUTPUT_ADDR_VEC_START
8526 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8529 #ifdef ASM_OUTPUT_CASE_LABEL
8530 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8533 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8536 for (idx = 0; idx < vlen; idx++)
8538 ASM_OUTPUT_ADDR_DIFF_ELT
8541 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8542 CODE_LABEL_NUMBER (base));
8545 #ifdef ASM_OUTPUT_ADDR_VEC_END
8546 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8551 sparc_output_deferred_case_vectors (void)
8556 if (sparc_addr_list == NULL_RTX
8557 && sparc_addr_diff_list == NULL_RTX)
8560 /* Align to cache line in the function's code section. */
8561 function_section (current_function_decl);
8563 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8565 ASM_OUTPUT_ALIGN (asm_out_file, align);
8567 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8568 sparc_output_addr_vec (XEXP (t, 0));
8569 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8570 sparc_output_addr_diff_vec (XEXP (t, 0));
8572 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8575 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8576 unknown. Return 1 if the high bits are zero, -1 if the register is
8579 sparc_check_64 (rtx x, rtx insn)
8581 /* If a register is set only once it is safe to ignore insns this
8582 code does not know how to handle. The loop will either recognize
8583 the single set and return the correct value or fail to recognize
8588 if (GET_CODE (x) != REG)
8591 if (GET_MODE (x) == DImode)
8592 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8594 if (flag_expensive_optimizations
8595 && REG_N_SETS (REGNO (y)) == 1)
8601 insn = get_last_insn_anywhere ();
8606 while ((insn = PREV_INSN (insn)))
8608 switch (GET_CODE (insn))
8621 rtx pat = PATTERN (insn);
8622 if (GET_CODE (pat) != SET)
8624 if (rtx_equal_p (x, SET_DEST (pat)))
8625 return set_extends (insn);
8626 if (y && rtx_equal_p (y, SET_DEST (pat)))
8627 return set_extends (insn);
8628 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8636 /* Returns assembly code to perform a DImode shift using
8637 a 64-bit global or out register on SPARC-V8+. */
8639 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8641 static char asm_code[60];
8643 /* The scratch register is only required when the destination
8644 register is not a 64-bit global or out register. */
8645 if (which_alternative != 2)
8646 operands[3] = operands[0];
8648 /* We can only shift by constants <= 63. */
8649 if (GET_CODE (operands[2]) == CONST_INT)
8650 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8652 if (GET_CODE (operands[1]) == CONST_INT)
8654 output_asm_insn ("mov\t%1, %3", operands);
8658 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8659 if (sparc_check_64 (operands[1], insn) <= 0)
8660 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8661 output_asm_insn ("or\t%L1, %3, %3", operands);
8664 strcpy(asm_code, opcode);
8666 if (which_alternative != 2)
8667 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8669 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8672 /* Output rtl to increment the profiler label LABELNO
8673 for profiling a function entry. */
8676 sparc_profile_hook (int labelno)
8681 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8682 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8683 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8685 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8688 #ifdef OBJECT_FORMAT_ELF
8690 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8692 if (flags & SECTION_MERGE)
8694 /* entsize cannot be expressed in this section attributes
8696 default_elf_asm_named_section (name, flags);
8700 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8702 if (!(flags & SECTION_DEBUG))
8703 fputs (",#alloc", asm_out_file);
8704 if (flags & SECTION_WRITE)
8705 fputs (",#write", asm_out_file);
8706 if (flags & SECTION_TLS)
8707 fputs (",#tls", asm_out_file);
8708 if (flags & SECTION_CODE)
8709 fputs (",#execinstr", asm_out_file);
8711 /* ??? Handle SECTION_BSS. */
8713 fputc ('\n', asm_out_file);
8715 #endif /* OBJECT_FORMAT_ELF */
8717 /* We do not allow sibling calls if -mflat, nor
8718 we do not allow indirect calls to be optimized into sibling calls.
8720 Also, on sparc 32-bit we cannot emit a sibling call when the
8721 current function returns a structure. This is because the "unimp
8722 after call" convention would cause the callee to return to the
8723 wrong place. The generic code already disallows cases where the
8724 function being called returns a structure.
8726 It may seem strange how this last case could occur. Usually there
8727 is code after the call which jumps to epilogue code which dumps the
8728 return value into the struct return area. That ought to invalidate
8729 the sibling call right? Well, in the c++ case we can end up passing
8730 the pointer to the struct return area to a constructor (which returns
8731 void) and then nothing else happens. Such a sibling call would look
8732 valid without the added check here. */
8734 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8738 && (TARGET_ARCH64 || ! current_function_returns_struct));
8741 /* libfunc renaming. */
8742 #include "config/gofast.h"
8745 sparc_init_libfuncs (void)
8749 /* Use the subroutines that Sun's library provides for integer
8750 multiply and divide. The `*' prevents an underscore from
8751 being prepended by the compiler. .umul is a little faster
8753 set_optab_libfunc (smul_optab, SImode, "*.umul");
8754 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8755 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8756 set_optab_libfunc (smod_optab, SImode, "*.rem");
8757 set_optab_libfunc (umod_optab, SImode, "*.urem");
8759 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8760 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8761 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8762 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8763 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8764 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8766 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8767 is because with soft-float, the SFmode and DFmode sqrt
8768 instructions will be absent, and the compiler will notice and
8769 try to use the TFmode sqrt instruction for calls to the
8770 builtin function sqrt, but this fails. */
8772 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8774 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8775 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8776 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8777 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8778 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8779 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8781 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8782 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8783 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8784 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8786 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8787 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8788 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8790 if (DITF_CONVERSION_LIBFUNCS)
8792 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8793 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8794 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8797 if (SUN_CONVERSION_LIBFUNCS)
8799 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8800 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8801 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8802 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8807 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8808 do not exist in the library. Make sure the compiler does not
8809 emit calls to them by accident. (It should always use the
8810 hardware instructions.) */
8811 set_optab_libfunc (smul_optab, SImode, 0);
8812 set_optab_libfunc (sdiv_optab, SImode, 0);
8813 set_optab_libfunc (udiv_optab, SImode, 0);
8814 set_optab_libfunc (smod_optab, SImode, 0);
8815 set_optab_libfunc (umod_optab, SImode, 0);
8817 if (SUN_INTEGER_MULTIPLY_64)
8819 set_optab_libfunc (smul_optab, DImode, "__mul64");
8820 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8821 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8822 set_optab_libfunc (smod_optab, DImode, "__rem64");
8823 set_optab_libfunc (umod_optab, DImode, "__urem64");
8826 if (SUN_CONVERSION_LIBFUNCS)
8828 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8829 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8830 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8831 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8835 gofast_maybe_init_libfuncs ();
8838 /* ??? Similar to the standard section selection, but force reloc-y-ness
8839 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8840 pretending PIC always on), but that's what the old code did. */
8843 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8845 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8848 /* Use text section for a constant unless we need more alignment than
8852 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8853 unsigned HOST_WIDE_INT align)
8855 if (align <= MAX_TEXT_ALIGN
8856 && ! (flag_pic && (symbolic_operand (x, mode)
8857 || SUNOS4_SHARED_LIBRARIES)))
8858 readonly_data_section ();
8864 sparc_extra_constraint_check (rtx op, int c, int strict)
8869 && (c == 'T' || c == 'U'))
8875 return fp_sethi_p (op);
8878 return fp_mov_p (op);
8881 return fp_high_losum_p (op);
8885 || (GET_CODE (op) == REG
8886 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8887 || reg_renumber[REGNO (op)] >= 0)))
8888 return register_ok_for_ldd (op);
8900 /* Our memory extra constraints have to emulate the
8901 behavior of 'm' and 'o' in order for reload to work
8903 if (GET_CODE (op) == MEM)
8906 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8908 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8913 reload_ok_mem = (reload_in_progress
8914 && GET_CODE (op) == REG
8915 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8916 && reg_renumber [REGNO (op)] < 0);
8919 return reload_ok_mem;
8922 /* ??? This duplicates information provided to the compiler by the
8923 ??? scheduler description. Some day, teach genautomata to output
8924 ??? the latencies and then CSE will just use that. */
8927 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8931 case PLUS: case MINUS: case ABS: case NEG:
8932 case FLOAT: case UNSIGNED_FLOAT:
8933 case FIX: case UNSIGNED_FIX:
8934 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8935 if (FLOAT_MODE_P (GET_MODE (x)))
8939 case PROCESSOR_ULTRASPARC:
8940 case PROCESSOR_ULTRASPARC3:
8941 *total = COSTS_N_INSNS (4);
8944 case PROCESSOR_SUPERSPARC:
8945 *total = COSTS_N_INSNS (3);
8948 case PROCESSOR_CYPRESS:
8949 *total = COSTS_N_INSNS (5);
8952 case PROCESSOR_HYPERSPARC:
8953 case PROCESSOR_SPARCLITE86X:
8955 *total = COSTS_N_INSNS (1);
8960 *total = COSTS_N_INSNS (1);
8966 case PROCESSOR_ULTRASPARC:
8967 if (GET_MODE (x) == SFmode)
8968 *total = COSTS_N_INSNS (13);
8970 *total = COSTS_N_INSNS (23);
8973 case PROCESSOR_ULTRASPARC3:
8974 if (GET_MODE (x) == SFmode)
8975 *total = COSTS_N_INSNS (20);
8977 *total = COSTS_N_INSNS (29);
8980 case PROCESSOR_SUPERSPARC:
8981 *total = COSTS_N_INSNS (12);
8984 case PROCESSOR_CYPRESS:
8985 *total = COSTS_N_INSNS (63);
8988 case PROCESSOR_HYPERSPARC:
8989 case PROCESSOR_SPARCLITE86X:
8990 *total = COSTS_N_INSNS (17);
8994 *total = COSTS_N_INSNS (30);
8999 if (FLOAT_MODE_P (GET_MODE (x)))
9003 case PROCESSOR_ULTRASPARC:
9004 case PROCESSOR_ULTRASPARC3:
9005 *total = COSTS_N_INSNS (1);
9008 case PROCESSOR_SUPERSPARC:
9009 *total = COSTS_N_INSNS (3);
9012 case PROCESSOR_CYPRESS:
9013 *total = COSTS_N_INSNS (5);
9016 case PROCESSOR_HYPERSPARC:
9017 case PROCESSOR_SPARCLITE86X:
9019 *total = COSTS_N_INSNS (1);
9024 /* ??? Maybe mark integer compares as zero cost on
9025 ??? all UltraSPARC processors because the result
9026 ??? can be bypassed to a branch in the same group. */
9028 *total = COSTS_N_INSNS (1);
9032 if (FLOAT_MODE_P (GET_MODE (x)))
9036 case PROCESSOR_ULTRASPARC:
9037 case PROCESSOR_ULTRASPARC3:
9038 *total = COSTS_N_INSNS (4);
9041 case PROCESSOR_SUPERSPARC:
9042 *total = COSTS_N_INSNS (3);
9045 case PROCESSOR_CYPRESS:
9046 *total = COSTS_N_INSNS (7);
9049 case PROCESSOR_HYPERSPARC:
9050 case PROCESSOR_SPARCLITE86X:
9051 *total = COSTS_N_INSNS (1);
9055 *total = COSTS_N_INSNS (5);
9060 /* The latency is actually variable for Ultra-I/II
9061 And if one of the inputs have a known constant
9062 value, we could calculate this precisely.
9064 However, for that to be useful we would need to
9065 add some machine description changes which would
9066 make sure small constants ended up in rs1 of the
9067 multiply instruction. This is because the multiply
9068 latency is determined by the number of clear (or
9069 set if the value is negative) bits starting from
9070 the most significant bit of the first input.
9072 The algorithm for computing num_cycles of a multiply
9076 highest_bit = highest_clear_bit(rs1);
9078 highest_bit = highest_set_bit(rs1);
9081 num_cycles = 4 + ((highest_bit - 3) / 2);
9083 If we did that we would have to also consider register
9084 allocation issues that would result from forcing such
9085 a value into a register.
9087 There are other similar tricks we could play if we
9088 knew, for example, that one input was an array index.
9090 Since we do not play any such tricks currently the
9091 safest thing to do is report the worst case latency. */
9092 if (sparc_cpu == PROCESSOR_ULTRASPARC)
9094 *total = (GET_MODE (x) == DImode
9095 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
9099 /* Multiply latency on Ultra-III, fortunately, is constant. */
9100 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
9102 *total = COSTS_N_INSNS (6);
9106 if (sparc_cpu == PROCESSOR_HYPERSPARC
9107 || sparc_cpu == PROCESSOR_SPARCLITE86X)
9109 *total = COSTS_N_INSNS (17);
9113 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
9120 if (FLOAT_MODE_P (GET_MODE (x)))
9124 case PROCESSOR_ULTRASPARC:
9125 if (GET_MODE (x) == SFmode)
9126 *total = COSTS_N_INSNS (13);
9128 *total = COSTS_N_INSNS (23);
9131 case PROCESSOR_ULTRASPARC3:
9132 if (GET_MODE (x) == SFmode)
9133 *total = COSTS_N_INSNS (17);
9135 *total = COSTS_N_INSNS (20);
9138 case PROCESSOR_SUPERSPARC:
9139 if (GET_MODE (x) == SFmode)
9140 *total = COSTS_N_INSNS (6);
9142 *total = COSTS_N_INSNS (9);
9145 case PROCESSOR_HYPERSPARC:
9146 case PROCESSOR_SPARCLITE86X:
9147 if (GET_MODE (x) == SFmode)
9148 *total = COSTS_N_INSNS (8);
9150 *total = COSTS_N_INSNS (12);
9154 *total = COSTS_N_INSNS (7);
9159 if (sparc_cpu == PROCESSOR_ULTRASPARC)
9160 *total = (GET_MODE (x) == DImode
9161 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
9162 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
9163 *total = (GET_MODE (x) == DImode
9164 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
9166 *total = COSTS_N_INSNS (25);
9170 /* Conditional moves. */
9173 case PROCESSOR_ULTRASPARC:
9174 *total = COSTS_N_INSNS (2);
9177 case PROCESSOR_ULTRASPARC3:
9178 if (FLOAT_MODE_P (GET_MODE (x)))
9179 *total = COSTS_N_INSNS (3);
9181 *total = COSTS_N_INSNS (2);
9185 *total = COSTS_N_INSNS (1);
9190 /* If outer-code is SIGN/ZERO extension we have to subtract
9191 out COSTS_N_INSNS (1) from whatever we return in determining
9195 case PROCESSOR_ULTRASPARC:
9196 if (outer_code == ZERO_EXTEND)
9197 *total = COSTS_N_INSNS (1);
9199 *total = COSTS_N_INSNS (2);
9202 case PROCESSOR_ULTRASPARC3:
9203 if (outer_code == ZERO_EXTEND)
9205 if (GET_MODE (x) == QImode
9206 || GET_MODE (x) == HImode
9207 || outer_code == SIGN_EXTEND)
9208 *total = COSTS_N_INSNS (2);
9210 *total = COSTS_N_INSNS (1);
9214 /* This handles sign extension (3 cycles)
9215 and everything else (2 cycles). */
9216 *total = COSTS_N_INSNS (2);
9220 case PROCESSOR_SUPERSPARC:
9221 if (FLOAT_MODE_P (GET_MODE (x))
9222 || outer_code == ZERO_EXTEND
9223 || outer_code == SIGN_EXTEND)
9224 *total = COSTS_N_INSNS (0);
9226 *total = COSTS_N_INSNS (1);
9229 case PROCESSOR_TSC701:
9230 if (outer_code == ZERO_EXTEND
9231 || outer_code == SIGN_EXTEND)
9232 *total = COSTS_N_INSNS (2);
9234 *total = COSTS_N_INSNS (3);
9237 case PROCESSOR_CYPRESS:
9238 if (outer_code == ZERO_EXTEND
9239 || outer_code == SIGN_EXTEND)
9240 *total = COSTS_N_INSNS (1);
9242 *total = COSTS_N_INSNS (2);
9245 case PROCESSOR_HYPERSPARC:
9246 case PROCESSOR_SPARCLITE86X:
9248 if (outer_code == ZERO_EXTEND
9249 || outer_code == SIGN_EXTEND)
9250 *total = COSTS_N_INSNS (0);
9252 *total = COSTS_N_INSNS (1);
9257 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
9275 if (GET_MODE (x) == DImode
9276 && ((XINT (x, 3) == 0
9277 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
9278 || (XINT (x, 3) == -1
9280 && XINT (x, 2) >= -0x1000)))
9291 /* Output the assembler code for a thunk function. THUNK_DECL is the
9292 declaration for the thunk function itself, FUNCTION is the decl for
9293 the target function. DELTA is an immediate constant offset to be
9294 added to THIS. If VCALL_OFFSET is nonzero, the word at address
9295 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
9298 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
9299 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9302 rtx this, insn, funexp;
9304 reload_completed = 1;
9305 epilogue_completed = 1;
9307 current_function_uses_only_leaf_regs = 1;
9309 emit_note (NOTE_INSN_PROLOGUE_END);
9311 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9312 returns a structure, the structure return pointer is there instead. */
9313 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9314 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
9316 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
9318 /* Add DELTA. When possible use a plain add, otherwise load it into
9319 a register first. */
9322 rtx delta_rtx = GEN_INT (delta);
9324 if (! SPARC_SIMM13_P (delta))
9326 rtx scratch = gen_rtx_REG (Pmode, 1);
9327 emit_move_insn (scratch, delta_rtx);
9328 delta_rtx = scratch;
9331 /* THIS += DELTA. */
9332 emit_insn (gen_add2_insn (this, delta_rtx));
9335 /* Add the word at address (*THIS + VCALL_OFFSET). */
9338 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
9339 rtx scratch = gen_rtx_REG (Pmode, 1);
9341 if (vcall_offset >= 0)
9344 /* SCRATCH = *THIS. */
9345 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this));
9347 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
9348 may not have any available scratch register at this point. */
9349 if (SPARC_SIMM13_P (vcall_offset))
9351 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
9352 else if (! fixed_regs[5]
9353 /* The below sequence is made up of at least 2 insns,
9354 while the default method may need only one. */
9355 && vcall_offset < -8192)
9357 rtx scratch2 = gen_rtx_REG (Pmode, 5);
9358 emit_move_insn (scratch2, vcall_offset_rtx);
9359 vcall_offset_rtx = scratch2;
9363 rtx increment = GEN_INT (-4096);
9365 /* VCALL_OFFSET is a negative number whose typical range can be
9366 estimated as -32768..0 in 32-bit mode. In almost all cases
9367 it is therefore cheaper to emit multiple add insns than
9368 spilling and loading the constant into a register (at least
9370 while (! SPARC_SIMM13_P (vcall_offset))
9372 emit_insn (gen_add2_insn (scratch, increment));
9373 vcall_offset += 4096;
9375 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
9378 /* SCRATCH = *(*THIS + VCALL_OFFSET). */
9379 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
9380 gen_rtx_PLUS (Pmode,
9382 vcall_offset_rtx)));
9384 /* THIS += *(*THIS + VCALL_OFFSET). */
9385 emit_insn (gen_add2_insn (this, scratch));
9388 /* Generate a tail call to the target function. */
9389 if (! TREE_USED (function))
9391 assemble_external (function);
9392 TREE_USED (function) = 1;
9394 funexp = XEXP (DECL_RTL (function), 0);
9395 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9396 insn = emit_call_insn (gen_sibcall (funexp));
9397 SIBLING_CALL_P (insn) = 1;
9400 /* Run just enough of rest_of_compilation to get the insns emitted.
9401 There's not really enough bulk here to make other passes such as
9402 instruction scheduling worth while. Note that use_thunk calls
9403 assemble_start_function and assemble_end_function. */
9404 insn = get_insns ();
9405 insn_locators_initialize ();
9406 shorten_branches (insn);
9407 final_start_function (insn, file, 1);
9408 final (insn, file, 1, 0);
9409 final_end_function ();
9411 reload_completed = 0;
9412 epilogue_completed = 0;
9416 /* Return true if sparc_output_mi_thunk would be able to output the
9417 assembler code for the thunk function specified by the arguments
9418 it is passed, and false otherwise. */
9420 sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED,
9421 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
9422 HOST_WIDE_INT vcall_offset,
9423 tree function ATTRIBUTE_UNUSED)
9425 /* Bound the loop used in the default method above. */
9426 return (vcall_offset >= -32768 || ! fixed_regs[5]);
9429 /* How to allocate a 'struct machine_function'. */
9431 static struct machine_function *
9432 sparc_init_machine_status (void)
9434 return ggc_alloc_cleared (sizeof (struct machine_function));
9437 /* Locate some local-dynamic symbol still in use by this function
9438 so that we can print its name in local-dynamic base patterns. */
9441 get_some_local_dynamic_name (void)
9445 if (cfun->machine->some_ld_name)
9446 return cfun->machine->some_ld_name;
9448 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9450 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9451 return cfun->machine->some_ld_name;
9457 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9462 && GET_CODE (x) == SYMBOL_REF
9463 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9465 cfun->machine->some_ld_name = XSTR (x, 0);
9472 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9473 We need to emit DTP-relative relocations. */
9476 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9481 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9484 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9489 output_addr_const (file, x);
9493 #include "gt-sparc.h"