1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
62 /* Global variables for machine-dependent things. */
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static HOST_WIDE_INT apparent_fsize;
71 static HOST_WIDE_INT actual_fsize;
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
81 /* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83 bool sparc_emitting_epilogue;
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
122 struct machine_function GTY(())
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name;
128 /* Name of where we pretend to think the frame pointer points.
129 Normally, this is "%fp", but if we are in a leaf procedure,
130 this is "%sp+something". We record "something" separately as it may be
131 too big for reg+constant addressing. */
133 static const char *frame_base_name;
134 static HOST_WIDE_INT frame_base_offset;
136 static void sparc_init_modes (void);
137 static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT);
138 static int restore_regs (FILE *, int, int, const char *, int, int);
139 static void build_big_number (FILE *, HOST_WIDE_INT, const char *);
140 static void scan_record_type (tree, int *, int *, int *);
141 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
142 tree, int, int, int *, int *);
144 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
145 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
147 static void sparc_output_addr_vec (rtx);
148 static void sparc_output_addr_diff_vec (rtx);
149 static void sparc_output_deferred_case_vectors (void);
150 static int check_return_regs (rtx);
151 static int epilogue_renumber (rtx *, int);
152 static bool sparc_assemble_integer (rtx, unsigned int, int);
153 static int set_extends (rtx);
154 static void output_restore_regs (FILE *, int);
155 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
156 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
157 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
158 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
159 static void sparc_flat_save_restore (FILE *, const char *, int,
160 unsigned long, unsigned long,
161 const char *, const char *,
163 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
164 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
165 #ifdef OBJECT_FORMAT_ELF
166 static void sparc_elf_asm_named_section (const char *, unsigned int);
168 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
170 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
171 unsigned HOST_WIDE_INT)
174 static int sparc_adjust_cost (rtx, rtx, rtx, int);
175 static int sparc_issue_rate (void);
176 static void sparc_sched_init (FILE *, int, int);
177 static int sparc_use_dfa_pipeline_interface (void);
178 static int sparc_use_sched_lookahead (void);
180 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
181 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
182 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
183 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
184 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
186 static bool sparc_function_ok_for_sibcall (tree, tree);
187 static void sparc_init_libfuncs (void);
188 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
189 HOST_WIDE_INT, tree);
190 static bool sparc_can_output_mi_thunk (tree, HOST_WIDE_INT,
191 HOST_WIDE_INT, tree);
192 static struct machine_function * sparc_init_machine_status (void);
193 static bool sparc_cannot_force_const_mem (rtx);
194 static rtx sparc_tls_get_addr (void);
195 static rtx sparc_tls_got (void);
196 static const char *get_some_local_dynamic_name (void);
197 static int get_some_local_dynamic_name_1 (rtx *, void *);
198 static bool sparc_rtx_costs (rtx, int, int, int *);
200 /* Option handling. */
202 /* Code model option as passed by user. */
203 const char *sparc_cmodel_string;
205 enum cmodel sparc_cmodel;
207 char sparc_hard_reg_printed[8];
209 struct sparc_cpu_select sparc_select[] =
211 /* switch name, tune arch */
212 { (char *)0, "default", 1, 1 },
213 { (char *)0, "-mcpu=", 1, 1 },
214 { (char *)0, "-mtune=", 1, 0 },
218 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
219 enum processor_type sparc_cpu;
221 /* Initialize the GCC target structure. */
223 /* The sparc default is to use .half rather than .short for aligned
224 HI objects. Use .word instead of .long on non-ELF systems. */
225 #undef TARGET_ASM_ALIGNED_HI_OP
226 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
227 #ifndef OBJECT_FORMAT_ELF
228 #undef TARGET_ASM_ALIGNED_SI_OP
229 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
232 #undef TARGET_ASM_UNALIGNED_HI_OP
233 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
234 #undef TARGET_ASM_UNALIGNED_SI_OP
235 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
236 #undef TARGET_ASM_UNALIGNED_DI_OP
237 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
239 /* The target hook has to handle DI-mode values. */
240 #undef TARGET_ASM_INTEGER
241 #define TARGET_ASM_INTEGER sparc_assemble_integer
243 #undef TARGET_ASM_FUNCTION_PROLOGUE
244 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
245 #undef TARGET_ASM_FUNCTION_EPILOGUE
246 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
248 #undef TARGET_SCHED_ADJUST_COST
249 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
250 #undef TARGET_SCHED_ISSUE_RATE
251 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
252 #undef TARGET_SCHED_INIT
253 #define TARGET_SCHED_INIT sparc_sched_init
254 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
255 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
256 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
257 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
259 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
260 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
262 #undef TARGET_INIT_LIBFUNCS
263 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
266 #undef TARGET_HAVE_TLS
267 #define TARGET_HAVE_TLS true
269 #undef TARGET_CANNOT_FORCE_CONST_MEM
270 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
272 #undef TARGET_ASM_OUTPUT_MI_THUNK
273 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
274 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
275 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
277 #undef TARGET_RTX_COSTS
278 #define TARGET_RTX_COSTS sparc_rtx_costs
279 #undef TARGET_ADDRESS_COST
280 #define TARGET_ADDRESS_COST hook_int_rtx_0
282 struct gcc_target targetm = TARGET_INITIALIZER;
284 /* Validate and override various options, and do some machine dependent
288 sparc_override_options (void)
290 static struct code_model {
291 const char *const name;
293 } const cmodels[] = {
295 { "medlow", CM_MEDLOW },
296 { "medmid", CM_MEDMID },
297 { "medany", CM_MEDANY },
298 { "embmedany", CM_EMBMEDANY },
301 const struct code_model *cmodel;
302 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
303 static struct cpu_default {
305 const char *const name;
306 } const cpu_default[] = {
307 /* There must be one entry here for each TARGET_CPU value. */
308 { TARGET_CPU_sparc, "cypress" },
309 { TARGET_CPU_sparclet, "tsc701" },
310 { TARGET_CPU_sparclite, "f930" },
311 { TARGET_CPU_v8, "v8" },
312 { TARGET_CPU_hypersparc, "hypersparc" },
313 { TARGET_CPU_sparclite86x, "sparclite86x" },
314 { TARGET_CPU_supersparc, "supersparc" },
315 { TARGET_CPU_v9, "v9" },
316 { TARGET_CPU_ultrasparc, "ultrasparc" },
317 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
320 const struct cpu_default *def;
321 /* Table of values for -m{cpu,tune}=. */
322 static struct cpu_table {
323 const char *const name;
324 const enum processor_type processor;
327 } const cpu_table[] = {
328 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
329 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
330 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
331 /* TI TMS390Z55 supersparc */
332 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
333 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
334 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
335 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
336 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
337 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
338 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
339 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
341 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
343 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
344 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
345 /* TI ultrasparc I, II, IIi */
346 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
347 /* Although insns using %y are deprecated, it is a clear win on current
349 |MASK_DEPRECATED_V8_INSNS},
350 /* TI ultrasparc III */
351 /* ??? Check if %y issue still holds true in ultra3. */
352 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
355 const struct cpu_table *cpu;
356 const struct sparc_cpu_select *sel;
359 #ifndef SPARC_BI_ARCH
360 /* Check for unsupported architecture size. */
361 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
362 error ("%s is not supported by this configuration",
363 DEFAULT_ARCH32_P ? "-m64" : "-m32");
366 /* We force all 64bit archs to use 128 bit long double */
367 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
369 error ("-mlong-double-64 not allowed with -m64");
370 target_flags |= MASK_LONG_DOUBLE_128;
373 /* Code model selection. */
374 sparc_cmodel = SPARC_DEFAULT_CMODEL;
378 sparc_cmodel = CM_32;
381 if (sparc_cmodel_string != NULL)
385 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
386 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
388 if (cmodel->name == NULL)
389 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
391 sparc_cmodel = cmodel->value;
394 error ("-mcmodel= is not supported on 32 bit systems");
397 fpu = TARGET_FPU; /* save current -mfpu status */
399 /* Set the default CPU. */
400 for (def = &cpu_default[0]; def->name; ++def)
401 if (def->cpu == TARGET_CPU_DEFAULT)
405 sparc_select[0].string = def->name;
407 for (sel = &sparc_select[0]; sel->name; ++sel)
411 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
412 if (! strcmp (sel->string, cpu->name))
415 sparc_cpu = cpu->processor;
419 target_flags &= ~cpu->disable;
420 target_flags |= cpu->enable;
426 error ("bad value (%s) for %s switch", sel->string, sel->name);
430 /* If -mfpu or -mno-fpu was explicitly used, don't override with
431 the processor default. Clear MASK_FPU_SET to avoid confusing
432 the reverse mapping from switch values to names. */
435 target_flags = (target_flags & ~MASK_FPU) | fpu;
436 target_flags &= ~MASK_FPU_SET;
439 /* Don't allow -mvis if FPU is disabled. */
441 target_flags &= ~MASK_VIS;
443 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
445 -m64 also implies v9. */
446 if (TARGET_VIS || TARGET_ARCH64)
448 target_flags |= MASK_V9;
449 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
452 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
453 if (TARGET_V9 && TARGET_ARCH32)
454 target_flags |= MASK_DEPRECATED_V8_INSNS;
456 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
457 if (! TARGET_V9 || TARGET_ARCH64)
458 target_flags &= ~MASK_V8PLUS;
460 /* Don't use stack biasing in 32 bit mode. */
462 target_flags &= ~MASK_STACK_BIAS;
464 /* Supply a default value for align_functions. */
465 if (align_functions == 0
466 && (sparc_cpu == PROCESSOR_ULTRASPARC
467 || sparc_cpu == PROCESSOR_ULTRASPARC3))
468 align_functions = 32;
470 /* Validate PCC_STRUCT_RETURN. */
471 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
472 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
474 /* Only use .uaxword when compiling for a 64-bit target. */
476 targetm.asm_out.unaligned_op.di = NULL;
478 /* Do various machine dependent initializations. */
481 /* Set up function hooks. */
482 init_machine_status = sparc_init_machine_status;
485 /* Miscellaneous utilities. */
487 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
488 or branch on register contents instructions. */
491 v9_regcmp_p (enum rtx_code code)
493 return (code == EQ || code == NE || code == GE || code == LT
494 || code == LE || code == GT);
498 /* Operand constraints. */
500 /* Return nonzero only if OP is a register of mode MODE,
504 reg_or_0_operand (rtx op, enum machine_mode mode)
506 if (register_operand (op, mode))
508 if (op == const0_rtx)
510 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
511 && CONST_DOUBLE_HIGH (op) == 0
512 && CONST_DOUBLE_LOW (op) == 0)
514 if (fp_zero_operand (op, mode))
519 /* Return nonzero only if OP is const1_rtx. */
522 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
524 return op == const1_rtx;
527 /* Nonzero if OP is a floating point value with value 0.0. */
530 fp_zero_operand (rtx op, enum machine_mode mode)
532 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
534 return op == CONST0_RTX (mode);
537 /* Nonzero if OP is a register operand in floating point register. */
540 fp_register_operand (rtx op, enum machine_mode mode)
542 if (! register_operand (op, mode))
544 if (GET_CODE (op) == SUBREG)
545 op = SUBREG_REG (op);
546 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
549 /* Nonzero if OP is a floating point constant which can
550 be loaded into an integer register using a single
551 sethi instruction. */
556 if (GET_CODE (op) == CONST_DOUBLE)
561 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
562 if (REAL_VALUES_EQUAL (r, dconst0) &&
563 ! REAL_VALUE_MINUS_ZERO (r))
565 REAL_VALUE_TO_TARGET_SINGLE (r, i);
566 if (SPARC_SETHI_P (i))
573 /* Nonzero if OP is a floating point constant which can
574 be loaded into an integer register using a single
580 if (GET_CODE (op) == CONST_DOUBLE)
585 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
586 if (REAL_VALUES_EQUAL (r, dconst0) &&
587 ! REAL_VALUE_MINUS_ZERO (r))
589 REAL_VALUE_TO_TARGET_SINGLE (r, i);
590 if (SPARC_SIMM13_P (i))
597 /* Nonzero if OP is a floating point constant which can
598 be loaded into an integer register using a high/losum
599 instruction sequence. */
602 fp_high_losum_p (rtx op)
604 /* The constraints calling this should only be in
605 SFmode move insns, so any constant which cannot
606 be moved using a single insn will do. */
607 if (GET_CODE (op) == CONST_DOUBLE)
612 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
613 if (REAL_VALUES_EQUAL (r, dconst0) &&
614 ! REAL_VALUE_MINUS_ZERO (r))
616 REAL_VALUE_TO_TARGET_SINGLE (r, i);
617 if (! SPARC_SETHI_P (i)
618 && ! SPARC_SIMM13_P (i))
625 /* Nonzero if OP is an integer register. */
628 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
630 return (register_operand (op, SImode)
631 || (TARGET_ARCH64 && register_operand (op, DImode)));
634 /* Nonzero if OP is a floating point condition code register. */
637 fcc_reg_operand (rtx op, enum machine_mode mode)
639 /* This can happen when recog is called from combine. Op may be a MEM.
640 Fail instead of calling abort in this case. */
641 if (GET_CODE (op) != REG)
644 if (mode != VOIDmode && mode != GET_MODE (op))
647 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
650 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
651 if (reg_renumber == 0)
652 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
653 return REGNO_OK_FOR_CCFP_P (REGNO (op));
655 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
659 /* Nonzero if OP is a floating point condition code fcc0 register. */
662 fcc0_reg_operand (rtx op, enum machine_mode mode)
664 /* This can happen when recog is called from combine. Op may be a MEM.
665 Fail instead of calling abort in this case. */
666 if (GET_CODE (op) != REG)
669 if (mode != VOIDmode && mode != GET_MODE (op))
672 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
675 return REGNO (op) == SPARC_FCC_REG;
678 /* Nonzero if OP is an integer or floating point condition code register. */
681 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
683 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
685 if (mode != VOIDmode && mode != GET_MODE (op))
688 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
693 return fcc_reg_operand (op, mode);
696 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
698 restore_operand (rtx op, enum machine_mode mode)
700 return (GET_CODE (op) == REG && GET_MODE (op) == mode
701 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
704 /* Call insn on SPARC can take a PC-relative constant address, or any regular
708 call_operand (rtx op, enum machine_mode mode)
710 if (GET_CODE (op) != MEM)
713 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
717 call_operand_address (rtx op, enum machine_mode mode)
719 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
722 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
723 otherwise return 0. */
726 tls_symbolic_operand (rtx op)
728 if (GET_CODE (op) != SYMBOL_REF)
730 return SYMBOL_REF_TLS_MODEL (op);
734 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
736 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
740 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
742 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
746 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
748 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
752 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
754 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
757 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
758 reference and a constant. */
761 symbolic_operand (register rtx op, enum machine_mode mode)
763 enum machine_mode omode = GET_MODE (op);
765 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
768 switch (GET_CODE (op))
771 return !SYMBOL_REF_TLS_MODEL (op);
778 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
779 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
780 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
781 && GET_CODE (XEXP (op, 1)) == CONST_INT);
788 /* Return truth value of statement that OP is a symbolic memory
789 operand of mode MODE. */
792 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
794 if (GET_CODE (op) == SUBREG)
795 op = SUBREG_REG (op);
796 if (GET_CODE (op) != MEM)
799 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
800 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
801 || GET_CODE (op) == LABEL_REF);
804 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
807 label_ref_operand (rtx op, enum machine_mode mode)
809 if (GET_CODE (op) != LABEL_REF)
811 if (GET_MODE (op) != mode)
816 /* Return 1 if the operand is an argument used in generating pic references
817 in either the medium/low or medium/anywhere code models of sparc64. */
820 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
822 /* Check for (const (minus (symbol_ref:GOT)
823 (const (minus (label) (pc))))). */
824 if (GET_CODE (op) != CONST)
827 if (GET_CODE (op) != MINUS)
829 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
831 /* ??? Ensure symbol is GOT. */
832 if (GET_CODE (XEXP (op, 1)) != CONST)
834 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
839 /* Return 1 if the operand is a data segment reference. This includes
840 the readonly data segment, or in other words anything but the text segment.
841 This is needed in the medium/anywhere code model on v9. These values
842 are accessed with EMBMEDANY_BASE_REG. */
845 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
847 switch (GET_CODE (op))
850 return ! SYMBOL_REF_FUNCTION_P (op);
852 /* Assume canonical format of symbol + constant.
855 return data_segment_operand (XEXP (op, 0), VOIDmode);
861 /* Return 1 if the operand is a text segment reference.
862 This is needed in the medium/anywhere code model on v9. */
865 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
867 switch (GET_CODE (op))
872 return SYMBOL_REF_FUNCTION_P (op);
874 /* Assume canonical format of symbol + constant.
877 return text_segment_operand (XEXP (op, 0), VOIDmode);
883 /* Return 1 if the operand is either a register or a memory operand that is
887 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
889 if (register_operand (op, mode))
892 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
899 splittable_symbolic_memory_operand (rtx op,
900 enum machine_mode mode ATTRIBUTE_UNUSED)
902 if (GET_CODE (op) != MEM)
904 if (! symbolic_operand (XEXP (op, 0), Pmode))
910 splittable_immediate_memory_operand (rtx op,
911 enum machine_mode mode ATTRIBUTE_UNUSED)
913 if (GET_CODE (op) != MEM)
915 if (! immediate_operand (XEXP (op, 0), Pmode))
920 /* Return truth value of whether OP is EQ or NE. */
923 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
925 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
928 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
929 or LTU for non-floating-point. We handle those specially. */
932 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
934 enum rtx_code code = GET_CODE (op);
936 if (GET_RTX_CLASS (code) != '<')
939 if (GET_MODE (XEXP (op, 0)) == CCFPmode
940 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
943 return (code != NE && code != EQ && code != GEU && code != LTU);
946 /* Return 1 if this is a comparison operator. This allows the use of
947 MATCH_OPERATOR to recognize all the branch insns. */
950 noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
952 enum rtx_code code = GET_CODE (op);
954 if (GET_RTX_CLASS (code) != '<')
957 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
958 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
959 /* These are the only branches which work with CC_NOOVmode. */
960 return (code == EQ || code == NE || code == GE || code == LT);
964 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
965 MATCH_OPERATOR to recognize all the branch insns. */
968 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
970 enum rtx_code code = GET_CODE (op);
975 if (GET_RTX_CLASS (code) != '<')
978 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
979 /* These are the only branches which work with CCX_NOOVmode. */
980 return (code == EQ || code == NE || code == GE || code == LT);
981 return (GET_MODE (XEXP (op, 0)) == CCXmode);
984 /* Nonzero if OP is a comparison operator suitable for use in v9
985 conditional move or branch on register contents instructions. */
988 v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
990 enum rtx_code code = GET_CODE (op);
992 if (GET_RTX_CLASS (code) != '<')
995 return v9_regcmp_p (code);
998 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1001 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1003 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1006 /* Return nonzero if OP is an operator of mode MODE which can set
1007 the condition codes explicitly. We do not include PLUS and MINUS
1008 because these require CC_NOOVmode, which we handle explicitly. */
1011 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1013 if (GET_CODE (op) == AND
1014 || GET_CODE (op) == IOR
1015 || GET_CODE (op) == XOR)
1021 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1022 complement its second operand and set the condition codes explicitly. */
1025 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1027 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1028 and (xor ... (not ...)) to (not (xor ...)). */
1029 return (GET_CODE (op) == AND
1030 || GET_CODE (op) == IOR);
1033 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1034 signed 13 bit immediate field. This is an acceptable SImode operand for
1035 most 3 address instructions. */
1038 arith_operand (rtx op, enum machine_mode mode)
1040 if (register_operand (op, mode))
1042 if (GET_CODE (op) != CONST_INT)
1044 return SMALL_INT32 (op);
1047 /* Return true if OP is a constant 4096 */
1050 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1052 if (GET_CODE (op) != CONST_INT)
1055 return INTVAL (op) == 4096;
1058 /* Return true if OP is suitable as second operand for add/sub */
1061 arith_add_operand (rtx op, enum machine_mode mode)
1063 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1066 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1067 immediate field of OR and XOR instructions. Used for 64-bit
1068 constant formation patterns. */
1070 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1072 return ((GET_CODE (op) == CONST_INT
1073 && SPARC_SIMM13_P (INTVAL (op)))
1074 #if HOST_BITS_PER_WIDE_INT != 64
1075 || (GET_CODE (op) == CONST_DOUBLE
1076 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1077 && (CONST_DOUBLE_HIGH (op) ==
1078 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1079 (HOST_WIDE_INT)-1 : 0)))
1084 /* The same, but only for sethi instructions. */
1086 const64_high_operand (rtx op, enum machine_mode mode)
1088 return ((GET_CODE (op) == CONST_INT
1089 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1090 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1092 || (GET_CODE (op) == CONST_DOUBLE
1093 && CONST_DOUBLE_HIGH (op) == 0
1094 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1095 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1098 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1099 signed 11 bit immediate field. This is an acceptable SImode operand for
1100 the movcc instructions. */
1103 arith11_operand (rtx op, enum machine_mode mode)
1105 return (register_operand (op, mode)
1106 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1109 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1110 signed 10 bit immediate field. This is an acceptable SImode operand for
1111 the movrcc instructions. */
1114 arith10_operand (rtx op, enum machine_mode mode)
1116 return (register_operand (op, mode)
1117 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1120 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1121 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1123 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1124 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1125 for most 3 address instructions. */
1128 arith_double_operand (rtx op, enum machine_mode mode)
1130 return (register_operand (op, mode)
1131 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1133 && GET_CODE (op) == CONST_DOUBLE
1134 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1135 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1137 && GET_CODE (op) == CONST_DOUBLE
1138 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1139 && ((CONST_DOUBLE_HIGH (op) == -1
1140 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1141 || (CONST_DOUBLE_HIGH (op) == 0
1142 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1145 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1148 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1150 return (TARGET_ARCH64 &&
1151 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1152 (GET_CODE (op) == CONST_DOUBLE &&
1153 CONST_DOUBLE_LOW (op) == 4096 &&
1154 CONST_DOUBLE_HIGH (op) == 0)));
1157 /* Return true if OP is suitable as second operand for add/sub in DImode */
1160 arith_double_add_operand (rtx op, enum machine_mode mode)
1162 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1165 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1166 can fit in an 11 bit immediate field. This is an acceptable DImode
1167 operand for the movcc instructions. */
1168 /* ??? Replace with arith11_operand? */
1171 arith11_double_operand (rtx op, enum machine_mode mode)
1173 return (register_operand (op, mode)
1174 || (GET_CODE (op) == CONST_DOUBLE
1175 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1176 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1177 && ((CONST_DOUBLE_HIGH (op) == -1
1178 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1179 || (CONST_DOUBLE_HIGH (op) == 0
1180 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1181 || (GET_CODE (op) == CONST_INT
1182 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1183 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1186 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1187 can fit in an 10 bit immediate field. This is an acceptable DImode
1188 operand for the movrcc instructions. */
1189 /* ??? Replace with arith10_operand? */
1192 arith10_double_operand (rtx op, enum machine_mode mode)
1194 return (register_operand (op, mode)
1195 || (GET_CODE (op) == CONST_DOUBLE
1196 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1197 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1198 && ((CONST_DOUBLE_HIGH (op) == -1
1199 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1200 || (CONST_DOUBLE_HIGH (op) == 0
1201 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1202 || (GET_CODE (op) == CONST_INT
1203 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1204 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1207 /* Return truth value of whether OP is an integer which fits the
1208 range constraining immediate operands in most three-address insns,
1209 which have a 13 bit immediate field. */
1212 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1214 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1218 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1220 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1221 || (GET_CODE (op) == CONST_DOUBLE
1222 && CONST_DOUBLE_HIGH (op) == 0
1223 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1226 /* Recognize operand values for the umul instruction. That instruction sign
1227 extends immediate values just like all other sparc instructions, but
1228 interprets the extended result as an unsigned number. */
1231 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1233 #if HOST_BITS_PER_WIDE_INT > 32
1234 /* All allowed constants will fit a CONST_INT. */
1235 return (GET_CODE (op) == CONST_INT
1236 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1237 || (INTVAL (op) >= 0xFFFFF000
1238 && INTVAL (op) <= 0xFFFFFFFF)));
1240 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1241 || (GET_CODE (op) == CONST_DOUBLE
1242 && CONST_DOUBLE_HIGH (op) == 0
1243 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1248 uns_arith_operand (rtx op, enum machine_mode mode)
1250 return register_operand (op, mode) || uns_small_int (op, mode);
1253 /* Return truth value of statement that OP is a call-clobbered register. */
1255 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1257 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1260 /* Return 1 if OP is a valid operand for the source of a move insn. */
1263 input_operand (rtx op, enum machine_mode mode)
1265 /* If both modes are non-void they must be the same. */
1266 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1269 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1270 if (GET_CODE (op) == CONSTANT_P_RTX)
1273 /* Allow any one instruction integer constant, and all CONST_INT
1274 variants when we are working in DImode and !arch64. */
1275 if (GET_MODE_CLASS (mode) == MODE_INT
1276 && ((GET_CODE (op) == CONST_INT
1277 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1278 || SPARC_SIMM13_P (INTVAL (op))
1280 && ! TARGET_ARCH64)))
1282 && GET_CODE (op) == CONST_DOUBLE
1283 && ((CONST_DOUBLE_HIGH (op) == 0
1284 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1286 #if HOST_BITS_PER_WIDE_INT == 64
1287 (CONST_DOUBLE_HIGH (op) == 0
1288 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1290 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1291 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1292 && CONST_DOUBLE_HIGH (op) == 0)
1293 || (CONST_DOUBLE_HIGH (op) == -1
1294 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1299 /* If !arch64 and this is a DImode const, allow it so that
1300 the splits can be generated. */
1303 && GET_CODE (op) == CONST_DOUBLE)
1306 if (register_operand (op, mode))
1309 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1310 && GET_CODE (op) == CONST_DOUBLE)
1313 /* If this is a SUBREG, look inside so that we handle
1314 paradoxical ones. */
1315 if (GET_CODE (op) == SUBREG)
1316 op = SUBREG_REG (op);
1318 /* Check for valid MEM forms. */
1319 if (GET_CODE (op) == MEM)
1320 return memory_address_p (mode, XEXP (op, 0));
1325 /* Return 1 if OP is valid for the lhs of a compare insn. */
1328 compare_operand (rtx op, enum machine_mode mode)
1330 if (GET_CODE (op) == ZERO_EXTRACT)
1331 return (register_operand (XEXP (op, 0), mode)
1332 && small_int_or_double (XEXP (op, 1), mode)
1333 && small_int_or_double (XEXP (op, 2), mode)
1334 /* This matches cmp_zero_extract. */
1336 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1337 && INTVAL (XEXP (op, 2)) > 19)
1338 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1339 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1340 /* This matches cmp_zero_extract_sp64. */
1343 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1344 && INTVAL (XEXP (op, 2)) > 51)
1345 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1346 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1348 return register_operand (op, mode);
1352 /* We know it can't be done in one insn when we get here,
1353 the movsi expander guarantees this. */
1355 sparc_emit_set_const32 (rtx op0, rtx op1)
1357 enum machine_mode mode = GET_MODE (op0);
1360 if (GET_CODE (op1) == CONST_INT)
1362 HOST_WIDE_INT value = INTVAL (op1);
1364 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1365 || SPARC_SIMM13_P (value))
1369 /* Full 2-insn decomposition is needed. */
1370 if (reload_in_progress || reload_completed)
1373 temp = gen_reg_rtx (mode);
1375 if (GET_CODE (op1) == CONST_INT)
1377 /* Emit them as real moves instead of a HIGH/LO_SUM,
1378 this way CSE can see everything and reuse intermediate
1379 values if it wants. */
1381 && HOST_BITS_PER_WIDE_INT != 64
1382 && (INTVAL (op1) & 0x80000000) != 0)
1383 emit_insn (gen_rtx_SET
1385 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1388 emit_insn (gen_rtx_SET (VOIDmode, temp,
1389 GEN_INT (INTVAL (op1)
1390 & ~(HOST_WIDE_INT)0x3ff)));
1392 emit_insn (gen_rtx_SET (VOIDmode,
1394 gen_rtx_IOR (mode, temp,
1395 GEN_INT (INTVAL (op1) & 0x3ff))));
1399 /* A symbol, emit in the traditional way. */
1400 emit_insn (gen_rtx_SET (VOIDmode, temp,
1401 gen_rtx_HIGH (mode, op1)));
1402 emit_insn (gen_rtx_SET (VOIDmode,
1403 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1409 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1410 If TEMP is non-zero, we are forbidden to use any other scratch
1411 registers. Otherwise, we are allowed to generate them as needed.
1413 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1414 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1416 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1418 rtx temp1, temp2, temp3, temp4, temp5;
1421 if (temp && GET_MODE (temp) == TImode)
1424 temp = gen_rtx_REG (DImode, REGNO (temp));
1427 /* SPARC-V9 code-model support. */
1428 switch (sparc_cmodel)
1431 /* The range spanned by all instructions in the object is less
1432 than 2^31 bytes (2GB) and the distance from any instruction
1433 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1434 than 2^31 bytes (2GB).
1436 The executable must be in the low 4TB of the virtual address
1439 sethi %hi(symbol), %temp1
1440 or %temp1, %lo(symbol), %reg */
1442 temp1 = temp; /* op0 is allowed. */
1444 temp1 = gen_reg_rtx (DImode);
1446 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1447 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1451 /* The range spanned by all instructions in the object is less
1452 than 2^31 bytes (2GB) and the distance from any instruction
1453 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1454 than 2^31 bytes (2GB).
1456 The executable must be in the low 16TB of the virtual address
1459 sethi %h44(symbol), %temp1
1460 or %temp1, %m44(symbol), %temp2
1461 sllx %temp2, 12, %temp3
1462 or %temp3, %l44(symbol), %reg */
1467 temp3 = temp; /* op0 is allowed. */
1471 temp1 = gen_reg_rtx (DImode);
1472 temp2 = gen_reg_rtx (DImode);
1473 temp3 = gen_reg_rtx (DImode);
1476 emit_insn (gen_seth44 (temp1, op1));
1477 emit_insn (gen_setm44 (temp2, temp1, op1));
1478 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1479 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1480 emit_insn (gen_setl44 (op0, temp3, op1));
1484 /* The range spanned by all instructions in the object is less
1485 than 2^31 bytes (2GB) and the distance from any instruction
1486 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1487 than 2^31 bytes (2GB).
1489 The executable can be placed anywhere in the virtual address
1492 sethi %hh(symbol), %temp1
1493 sethi %lm(symbol), %temp2
1494 or %temp1, %hm(symbol), %temp3
1495 sllx %temp3, 32, %temp4
1496 or %temp4, %temp2, %temp5
1497 or %temp5, %lo(symbol), %reg */
1500 /* It is possible that one of the registers we got for operands[2]
1501 might coincide with that of operands[0] (which is why we made
1502 it TImode). Pick the other one to use as our scratch. */
1503 if (rtx_equal_p (temp, op0))
1506 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1511 temp2 = temp; /* op0 is _not_ allowed, see above. */
1518 temp1 = gen_reg_rtx (DImode);
1519 temp2 = gen_reg_rtx (DImode);
1520 temp3 = gen_reg_rtx (DImode);
1521 temp4 = gen_reg_rtx (DImode);
1522 temp5 = gen_reg_rtx (DImode);
1525 emit_insn (gen_sethh (temp1, op1));
1526 emit_insn (gen_setlm (temp2, op1));
1527 emit_insn (gen_sethm (temp3, temp1, op1));
1528 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1529 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1530 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1531 gen_rtx_PLUS (DImode, temp4, temp2)));
1532 emit_insn (gen_setlo (op0, temp5, op1));
1536 /* Old old old backwards compatibility kruft here.
1537 Essentially it is MEDLOW with a fixed 64-bit
1538 virtual base added to all data segment addresses.
1539 Text-segment stuff is computed like MEDANY, we can't
1540 reuse the code above because the relocation knobs
1543 Data segment: sethi %hi(symbol), %temp1
1544 add %temp1, EMBMEDANY_BASE_REG, %temp2
1545 or %temp2, %lo(symbol), %reg */
1546 if (data_segment_operand (op1, GET_MODE (op1)))
1550 temp1 = temp; /* op0 is allowed. */
1555 temp1 = gen_reg_rtx (DImode);
1556 temp2 = gen_reg_rtx (DImode);
1559 emit_insn (gen_embmedany_sethi (temp1, op1));
1560 emit_insn (gen_embmedany_brsum (temp2, temp1));
1561 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1564 /* Text segment: sethi %uhi(symbol), %temp1
1565 sethi %hi(symbol), %temp2
1566 or %temp1, %ulo(symbol), %temp3
1567 sllx %temp3, 32, %temp4
1568 or %temp4, %temp2, %temp5
1569 or %temp5, %lo(symbol), %reg */
1574 /* It is possible that one of the registers we got for operands[2]
1575 might coincide with that of operands[0] (which is why we made
1576 it TImode). Pick the other one to use as our scratch. */
1577 if (rtx_equal_p (temp, op0))
1580 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1585 temp2 = temp; /* op0 is _not_ allowed, see above. */
1592 temp1 = gen_reg_rtx (DImode);
1593 temp2 = gen_reg_rtx (DImode);
1594 temp3 = gen_reg_rtx (DImode);
1595 temp4 = gen_reg_rtx (DImode);
1596 temp5 = gen_reg_rtx (DImode);
1599 emit_insn (gen_embmedany_textuhi (temp1, op1));
1600 emit_insn (gen_embmedany_texthi (temp2, op1));
1601 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1602 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1603 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1604 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1605 gen_rtx_PLUS (DImode, temp4, temp2)));
1606 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1615 /* These avoid problems when cross compiling. If we do not
1616 go through all this hair then the optimizer will see
1617 invalid REG_EQUAL notes or in some cases none at all. */
1618 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1619 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1620 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1621 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1623 #if HOST_BITS_PER_WIDE_INT == 64
1624 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1625 #define GEN_INT64(__x) GEN_INT (__x)
1627 #define GEN_HIGHINT64(__x) \
1628 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1629 #define GEN_INT64(__x) \
1630 immed_double_const ((__x) & 0xffffffff, \
1631 ((__x) & 0x80000000 ? -1 : 0), DImode)
1634 /* The optimizer is not to assume anything about exactly
1635 which bits are set for a HIGH, they are unspecified.
1636 Unfortunately this leads to many missed optimizations
1637 during CSE. We mask out the non-HIGH bits, and matches
1638 a plain movdi, to alleviate this problem. */
1640 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1642 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1646 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1648 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1652 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1654 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1658 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1660 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1663 /* Worker routines for 64-bit constant formation on arch64.
1664 One of the key things to be doing in these emissions is
1665 to create as many temp REGs as possible. This makes it
1666 possible for half-built constants to be used later when
1667 such values are similar to something required later on.
1668 Without doing this, the optimizer cannot see such
1671 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1672 unsigned HOST_WIDE_INT, int);
1675 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1676 unsigned HOST_WIDE_INT low_bits, int is_neg)
1678 unsigned HOST_WIDE_INT high_bits;
1681 high_bits = (~low_bits) & 0xffffffff;
1683 high_bits = low_bits;
1685 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1688 emit_insn (gen_rtx_SET (VOIDmode, op0,
1689 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1693 /* If we are XOR'ing with -1, then we should emit a one's complement
1694 instead. This way the combiner will notice logical operations
1695 such as ANDN later on and substitute. */
1696 if ((low_bits & 0x3ff) == 0x3ff)
1698 emit_insn (gen_rtx_SET (VOIDmode, op0,
1699 gen_rtx_NOT (DImode, temp)));
1703 emit_insn (gen_rtx_SET (VOIDmode, op0,
1704 gen_safe_XOR64 (temp,
1705 (-(HOST_WIDE_INT)0x400
1706 | (low_bits & 0x3ff)))));
1711 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1712 unsigned HOST_WIDE_INT, int);
1715 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1716 unsigned HOST_WIDE_INT high_bits,
1717 unsigned HOST_WIDE_INT low_immediate,
1722 if ((high_bits & 0xfffffc00) != 0)
1724 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1725 if ((high_bits & ~0xfffffc00) != 0)
1726 emit_insn (gen_rtx_SET (VOIDmode, op0,
1727 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1733 emit_insn (gen_safe_SET64 (temp, high_bits));
1737 /* Now shift it up into place. */
1738 emit_insn (gen_rtx_SET (VOIDmode, op0,
1739 gen_rtx_ASHIFT (DImode, temp2,
1740 GEN_INT (shift_count))));
1742 /* If there is a low immediate part piece, finish up by
1743 putting that in as well. */
1744 if (low_immediate != 0)
1745 emit_insn (gen_rtx_SET (VOIDmode, op0,
1746 gen_safe_OR64 (op0, low_immediate)));
1749 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1750 unsigned HOST_WIDE_INT);
1752 /* Full 64-bit constant decomposition. Even though this is the
1753 'worst' case, we still optimize a few things away. */
1755 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1756 unsigned HOST_WIDE_INT high_bits,
1757 unsigned HOST_WIDE_INT low_bits)
1761 if (reload_in_progress || reload_completed)
1764 sub_temp = gen_reg_rtx (DImode);
1766 if ((high_bits & 0xfffffc00) != 0)
1768 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1769 if ((high_bits & ~0xfffffc00) != 0)
1770 emit_insn (gen_rtx_SET (VOIDmode,
1772 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1778 emit_insn (gen_safe_SET64 (temp, high_bits));
1782 if (!reload_in_progress && !reload_completed)
1784 rtx temp2 = gen_reg_rtx (DImode);
1785 rtx temp3 = gen_reg_rtx (DImode);
1786 rtx temp4 = gen_reg_rtx (DImode);
1788 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1789 gen_rtx_ASHIFT (DImode, sub_temp,
1792 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1793 if ((low_bits & ~0xfffffc00) != 0)
1795 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1796 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1797 emit_insn (gen_rtx_SET (VOIDmode, op0,
1798 gen_rtx_PLUS (DImode, temp4, temp3)));
1802 emit_insn (gen_rtx_SET (VOIDmode, op0,
1803 gen_rtx_PLUS (DImode, temp4, temp2)));
1808 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1809 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1810 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1813 /* We are in the middle of reload, so this is really
1814 painful. However we do still make an attempt to
1815 avoid emitting truly stupid code. */
1816 if (low1 != const0_rtx)
1818 emit_insn (gen_rtx_SET (VOIDmode, op0,
1819 gen_rtx_ASHIFT (DImode, sub_temp,
1820 GEN_INT (to_shift))));
1821 emit_insn (gen_rtx_SET (VOIDmode, op0,
1822 gen_rtx_IOR (DImode, op0, low1)));
1830 if (low2 != const0_rtx)
1832 emit_insn (gen_rtx_SET (VOIDmode, op0,
1833 gen_rtx_ASHIFT (DImode, sub_temp,
1834 GEN_INT (to_shift))));
1835 emit_insn (gen_rtx_SET (VOIDmode, op0,
1836 gen_rtx_IOR (DImode, op0, low2)));
1844 emit_insn (gen_rtx_SET (VOIDmode, op0,
1845 gen_rtx_ASHIFT (DImode, sub_temp,
1846 GEN_INT (to_shift))));
1847 if (low3 != const0_rtx)
1848 emit_insn (gen_rtx_SET (VOIDmode, op0,
1849 gen_rtx_IOR (DImode, op0, low3)));
1854 /* Analyze a 64-bit constant for certain properties. */
1855 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1856 unsigned HOST_WIDE_INT,
1857 int *, int *, int *);
1860 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1861 unsigned HOST_WIDE_INT low_bits,
1862 int *hbsp, int *lbsp, int *abbasp)
1864 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1867 lowest_bit_set = highest_bit_set = -1;
1871 if ((lowest_bit_set == -1)
1872 && ((low_bits >> i) & 1))
1874 if ((highest_bit_set == -1)
1875 && ((high_bits >> (32 - i - 1)) & 1))
1876 highest_bit_set = (64 - i - 1);
1879 && ((highest_bit_set == -1)
1880 || (lowest_bit_set == -1)));
1886 if ((lowest_bit_set == -1)
1887 && ((high_bits >> i) & 1))
1888 lowest_bit_set = i + 32;
1889 if ((highest_bit_set == -1)
1890 && ((low_bits >> (32 - i - 1)) & 1))
1891 highest_bit_set = 32 - i - 1;
1894 && ((highest_bit_set == -1)
1895 || (lowest_bit_set == -1)));
1897 /* If there are no bits set this should have gone out
1898 as one instruction! */
1899 if (lowest_bit_set == -1
1900 || highest_bit_set == -1)
1902 all_bits_between_are_set = 1;
1903 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1907 if ((low_bits & (1 << i)) != 0)
1912 if ((high_bits & (1 << (i - 32))) != 0)
1915 all_bits_between_are_set = 0;
1918 *hbsp = highest_bit_set;
1919 *lbsp = lowest_bit_set;
1920 *abbasp = all_bits_between_are_set;
1923 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1926 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1927 unsigned HOST_WIDE_INT low_bits)
1929 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1932 || high_bits == 0xffffffff)
1935 analyze_64bit_constant (high_bits, low_bits,
1936 &highest_bit_set, &lowest_bit_set,
1937 &all_bits_between_are_set);
1939 if ((highest_bit_set == 63
1940 || lowest_bit_set == 0)
1941 && all_bits_between_are_set != 0)
1944 if ((highest_bit_set - lowest_bit_set) < 21)
1950 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1951 unsigned HOST_WIDE_INT,
1954 static unsigned HOST_WIDE_INT
1955 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1956 unsigned HOST_WIDE_INT low_bits,
1957 int lowest_bit_set, int shift)
1959 HOST_WIDE_INT hi, lo;
1961 if (lowest_bit_set < 32)
1963 lo = (low_bits >> lowest_bit_set) << shift;
1964 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1969 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1976 /* Here we are sure to be arch64 and this is an integer constant
1977 being loaded into a register. Emit the most efficient
1978 insn sequence possible. Detection of all the 1-insn cases
1979 has been done already. */
1981 sparc_emit_set_const64 (rtx op0, rtx op1)
1983 unsigned HOST_WIDE_INT high_bits, low_bits;
1984 int lowest_bit_set, highest_bit_set;
1985 int all_bits_between_are_set;
1988 /* Sanity check that we know what we are working with. */
1989 if (! TARGET_ARCH64)
1992 if (GET_CODE (op0) != SUBREG)
1994 if (GET_CODE (op0) != REG
1995 || (REGNO (op0) >= SPARC_FIRST_FP_REG
1996 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2000 if (reload_in_progress || reload_completed)
2003 if (GET_CODE (op1) != CONST_DOUBLE
2004 && GET_CODE (op1) != CONST_INT)
2006 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2011 temp = gen_reg_rtx (DImode);
2013 if (GET_CODE (op1) == CONST_DOUBLE)
2015 #if HOST_BITS_PER_WIDE_INT == 64
2016 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2017 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2019 high_bits = CONST_DOUBLE_HIGH (op1);
2020 low_bits = CONST_DOUBLE_LOW (op1);
2025 #if HOST_BITS_PER_WIDE_INT == 64
2026 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2027 low_bits = (INTVAL (op1) & 0xffffffff);
2029 high_bits = ((INTVAL (op1) < 0) ?
2032 low_bits = INTVAL (op1);
2036 /* low_bits bits 0 --> 31
2037 high_bits bits 32 --> 63 */
2039 analyze_64bit_constant (high_bits, low_bits,
2040 &highest_bit_set, &lowest_bit_set,
2041 &all_bits_between_are_set);
2043 /* First try for a 2-insn sequence. */
2045 /* These situations are preferred because the optimizer can
2046 * do more things with them:
2048 * sllx %reg, shift, %reg
2050 * srlx %reg, shift, %reg
2051 * 3) mov some_small_const, %reg
2052 * sllx %reg, shift, %reg
2054 if (((highest_bit_set == 63
2055 || lowest_bit_set == 0)
2056 && all_bits_between_are_set != 0)
2057 || ((highest_bit_set - lowest_bit_set) < 12))
2059 HOST_WIDE_INT the_const = -1;
2060 int shift = lowest_bit_set;
2062 if ((highest_bit_set != 63
2063 && lowest_bit_set != 0)
2064 || all_bits_between_are_set == 0)
2067 create_simple_focus_bits (high_bits, low_bits,
2070 else if (lowest_bit_set == 0)
2071 shift = -(63 - highest_bit_set);
2073 if (! SPARC_SIMM13_P (the_const))
2076 emit_insn (gen_safe_SET64 (temp, the_const));
2078 emit_insn (gen_rtx_SET (VOIDmode,
2080 gen_rtx_ASHIFT (DImode,
2084 emit_insn (gen_rtx_SET (VOIDmode,
2086 gen_rtx_LSHIFTRT (DImode,
2088 GEN_INT (-shift))));
2094 /* Now a range of 22 or less bits set somewhere.
2095 * 1) sethi %hi(focus_bits), %reg
2096 * sllx %reg, shift, %reg
2097 * 2) sethi %hi(focus_bits), %reg
2098 * srlx %reg, shift, %reg
2100 if ((highest_bit_set - lowest_bit_set) < 21)
2102 unsigned HOST_WIDE_INT focus_bits =
2103 create_simple_focus_bits (high_bits, low_bits,
2104 lowest_bit_set, 10);
2106 if (! SPARC_SETHI_P (focus_bits))
2109 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2111 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2112 if (lowest_bit_set < 10)
2113 emit_insn (gen_rtx_SET (VOIDmode,
2115 gen_rtx_LSHIFTRT (DImode, temp,
2116 GEN_INT (10 - lowest_bit_set))));
2117 else if (lowest_bit_set > 10)
2118 emit_insn (gen_rtx_SET (VOIDmode,
2120 gen_rtx_ASHIFT (DImode, temp,
2121 GEN_INT (lowest_bit_set - 10))));
2127 /* 1) sethi %hi(low_bits), %reg
2128 * or %reg, %lo(low_bits), %reg
2129 * 2) sethi %hi(~low_bits), %reg
2130 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2133 || high_bits == 0xffffffff)
2135 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2136 (high_bits == 0xffffffff));
2140 /* Now, try 3-insn sequences. */
2142 /* 1) sethi %hi(high_bits), %reg
2143 * or %reg, %lo(high_bits), %reg
2144 * sllx %reg, 32, %reg
2148 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2152 /* We may be able to do something quick
2153 when the constant is negated, so try that. */
2154 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2155 (~low_bits) & 0xfffffc00))
2157 /* NOTE: The trailing bits get XOR'd so we need the
2158 non-negated bits, not the negated ones. */
2159 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2161 if ((((~high_bits) & 0xffffffff) == 0
2162 && ((~low_bits) & 0x80000000) == 0)
2163 || (((~high_bits) & 0xffffffff) == 0xffffffff
2164 && ((~low_bits) & 0x80000000) != 0))
2166 int fast_int = (~low_bits & 0xffffffff);
2168 if ((SPARC_SETHI_P (fast_int)
2169 && (~high_bits & 0xffffffff) == 0)
2170 || SPARC_SIMM13_P (fast_int))
2171 emit_insn (gen_safe_SET64 (temp, fast_int));
2173 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2178 #if HOST_BITS_PER_WIDE_INT == 64
2179 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2180 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2182 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2183 (~high_bits) & 0xffffffff,
2186 sparc_emit_set_const64 (temp, negated_const);
2189 /* If we are XOR'ing with -1, then we should emit a one's complement
2190 instead. This way the combiner will notice logical operations
2191 such as ANDN later on and substitute. */
2192 if (trailing_bits == 0x3ff)
2194 emit_insn (gen_rtx_SET (VOIDmode, op0,
2195 gen_rtx_NOT (DImode, temp)));
2199 emit_insn (gen_rtx_SET (VOIDmode,
2201 gen_safe_XOR64 (temp,
2202 (-0x400 | trailing_bits))));
2207 /* 1) sethi %hi(xxx), %reg
2208 * or %reg, %lo(xxx), %reg
2209 * sllx %reg, yyy, %reg
2211 * ??? This is just a generalized version of the low_bits==0
2212 * thing above, FIXME...
2214 if ((highest_bit_set - lowest_bit_set) < 32)
2216 unsigned HOST_WIDE_INT focus_bits =
2217 create_simple_focus_bits (high_bits, low_bits,
2220 /* We can't get here in this state. */
2221 if (highest_bit_set < 32
2222 || lowest_bit_set >= 32)
2225 /* So what we know is that the set bits straddle the
2226 middle of the 64-bit word. */
2227 sparc_emit_set_const64_quick2 (op0, temp,
2233 /* 1) sethi %hi(high_bits), %reg
2234 * or %reg, %lo(high_bits), %reg
2235 * sllx %reg, 32, %reg
2236 * or %reg, low_bits, %reg
2238 if (SPARC_SIMM13_P(low_bits)
2239 && ((int)low_bits > 0))
2241 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2245 /* The easiest way when all else fails, is full decomposition. */
2247 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2248 high_bits, low_bits, ~high_bits, ~low_bits);
2250 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2253 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2254 return the mode to be used for the comparison. For floating-point,
2255 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2256 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2257 processing is needed. */
2260 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2262 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2288 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2289 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2291 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2292 return CCX_NOOVmode;
2298 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2305 /* X and Y are two things to compare using CODE. Emit the compare insn and
2306 return the rtx for the cc reg in the proper mode. */
2309 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2311 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2314 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2315 fcc regs (cse can't tell they're really call clobbered regs and will
2316 remove a duplicate comparison even if there is an intervening function
2317 call - it will then try to reload the cc reg via an int reg which is why
2318 we need the movcc patterns). It is possible to provide the movcc
2319 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2320 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2321 to tell cse that CCFPE mode registers (even pseudos) are call
2324 /* ??? This is an experiment. Rather than making changes to cse which may
2325 or may not be easy/clean, we do our own cse. This is possible because
2326 we will generate hard registers. Cse knows they're call clobbered (it
2327 doesn't know the same thing about pseudos). If we guess wrong, no big
2328 deal, but if we win, great! */
2330 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2331 #if 1 /* experiment */
2334 /* We cycle through the registers to ensure they're all exercised. */
2335 static int next_fcc_reg = 0;
2336 /* Previous x,y for each fcc reg. */
2337 static rtx prev_args[4][2];
2339 /* Scan prev_args for x,y. */
2340 for (reg = 0; reg < 4; reg++)
2341 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2346 prev_args[reg][0] = x;
2347 prev_args[reg][1] = y;
2348 next_fcc_reg = (next_fcc_reg + 1) & 3;
2350 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2353 cc_reg = gen_reg_rtx (mode);
2354 #endif /* ! experiment */
2355 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2356 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2358 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2360 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2361 gen_rtx_COMPARE (mode, x, y)));
2366 /* This function is used for v9 only.
2367 CODE is the code for an Scc's comparison.
2368 OPERANDS[0] is the target of the Scc insn.
2369 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2370 been generated yet).
2372 This function is needed to turn
2375 (gt (reg:CCX 100 %icc)
2379 (gt:DI (reg:CCX 100 %icc)
2382 IE: The instruction recognizer needs to see the mode of the comparison to
2383 find the right instruction. We could use "gt:DI" right in the
2384 define_expand, but leaving it out allows us to handle DI, SI, etc.
2386 We refer to the global sparc compare operands sparc_compare_op0 and
2387 sparc_compare_op1. */
2390 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2395 && (GET_MODE (sparc_compare_op0) == DImode
2396 || GET_MODE (operands[0]) == DImode))
2399 op0 = sparc_compare_op0;
2400 op1 = sparc_compare_op1;
2402 /* Try to use the movrCC insns. */
2404 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2405 && op1 == const0_rtx
2406 && v9_regcmp_p (compare_code))
2408 /* Special case for op0 != 0. This can be done with one instruction if
2409 operands[0] == sparc_compare_op0. */
2411 if (compare_code == NE
2412 && GET_MODE (operands[0]) == DImode
2413 && rtx_equal_p (op0, operands[0]))
2415 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2416 gen_rtx_IF_THEN_ELSE (DImode,
2417 gen_rtx_fmt_ee (compare_code, DImode,
2424 if (reg_overlap_mentioned_p (operands[0], op0))
2426 /* Handle the case where operands[0] == sparc_compare_op0.
2427 We "early clobber" the result. */
2428 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2429 emit_move_insn (op0, sparc_compare_op0);
2432 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2433 if (GET_MODE (op0) != DImode)
2435 temp = gen_reg_rtx (DImode);
2436 convert_move (temp, op0, 0);
2440 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2441 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2442 gen_rtx_fmt_ee (compare_code, DImode,
2450 operands[1] = gen_compare_reg (compare_code, op0, op1);
2452 switch (GET_MODE (operands[1]))
2462 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2463 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2464 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2465 gen_rtx_fmt_ee (compare_code,
2466 GET_MODE (operands[1]),
2467 operands[1], const0_rtx),
2468 const1_rtx, operands[0])));
2473 /* Emit a conditional jump insn for the v9 architecture using comparison code
2474 CODE and jump target LABEL.
2475 This function exists to take advantage of the v9 brxx insns. */
2478 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2480 emit_jump_insn (gen_rtx_SET (VOIDmode,
2482 gen_rtx_IF_THEN_ELSE (VOIDmode,
2483 gen_rtx_fmt_ee (code, GET_MODE (op0),
2485 gen_rtx_LABEL_REF (VOIDmode, label),
2489 /* Generate a DFmode part of a hard TFmode register.
2490 REG is the TFmode hard register, LOW is 1 for the
2491 low 64bit of the register and 0 otherwise.
2494 gen_df_reg (rtx reg, int low)
2496 int regno = REGNO (reg);
2498 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2499 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2500 return gen_rtx_REG (DFmode, regno);
2503 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2504 Unlike normal calls, TFmode operands are passed by reference. It is
2505 assumed that no more than 3 operands are required. */
2508 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2510 rtx ret_slot = NULL, arg[3], func_sym;
2513 /* We only expect to be called for conversions, unary, and binary ops. */
2514 if (nargs < 2 || nargs > 3)
2517 for (i = 0; i < nargs; ++i)
2519 rtx this_arg = operands[i];
2522 /* TFmode arguments and return values are passed by reference. */
2523 if (GET_MODE (this_arg) == TFmode)
2525 int force_stack_temp;
2527 force_stack_temp = 0;
2528 if (TARGET_BUGGY_QP_LIB && i == 0)
2529 force_stack_temp = 1;
2531 if (GET_CODE (this_arg) == MEM
2532 && ! force_stack_temp)
2533 this_arg = XEXP (this_arg, 0);
2534 else if (CONSTANT_P (this_arg)
2535 && ! force_stack_temp)
2537 this_slot = force_const_mem (TFmode, this_arg);
2538 this_arg = XEXP (this_slot, 0);
2542 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2544 /* Operand 0 is the return value. We'll copy it out later. */
2546 emit_move_insn (this_slot, this_arg);
2548 ret_slot = this_slot;
2550 this_arg = XEXP (this_slot, 0);
2557 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2559 if (GET_MODE (operands[0]) == TFmode)
2562 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2563 arg[0], GET_MODE (arg[0]),
2564 arg[1], GET_MODE (arg[1]));
2566 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2567 arg[0], GET_MODE (arg[0]),
2568 arg[1], GET_MODE (arg[1]),
2569 arg[2], GET_MODE (arg[2]));
2572 emit_move_insn (operands[0], ret_slot);
2581 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2582 GET_MODE (operands[0]), 1,
2583 arg[1], GET_MODE (arg[1]));
2585 if (ret != operands[0])
2586 emit_move_insn (operands[0], ret);
2590 /* Expand soft-float TFmode calls to sparc abi routines. */
2593 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2615 emit_soft_tfmode_libcall (func, 3, operands);
2619 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2632 emit_soft_tfmode_libcall (func, 2, operands);
2636 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2643 switch (GET_MODE (operands[1]))
2656 case FLOAT_TRUNCATE:
2657 switch (GET_MODE (operands[0]))
2671 switch (GET_MODE (operands[1]))
2684 case UNSIGNED_FLOAT:
2685 switch (GET_MODE (operands[1]))
2699 switch (GET_MODE (operands[0]))
2713 switch (GET_MODE (operands[0]))
2730 emit_soft_tfmode_libcall (func, 2, operands);
2733 /* Expand a hard-float tfmode operation. All arguments must be in
2737 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2741 if (GET_RTX_CLASS (code) == '1')
2743 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2744 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2748 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2749 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2750 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2751 operands[1], operands[2]);
2754 if (register_operand (operands[0], VOIDmode))
2757 dest = gen_reg_rtx (GET_MODE (operands[0]));
2759 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2761 if (dest != operands[0])
2762 emit_move_insn (operands[0], dest);
2766 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2768 if (TARGET_HARD_QUAD)
2769 emit_hard_tfmode_operation (code, operands);
2771 emit_soft_tfmode_binop (code, operands);
2775 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2777 if (TARGET_HARD_QUAD)
2778 emit_hard_tfmode_operation (code, operands);
2780 emit_soft_tfmode_unop (code, operands);
2784 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2786 if (TARGET_HARD_QUAD)
2787 emit_hard_tfmode_operation (code, operands);
2789 emit_soft_tfmode_cvt (code, operands);
2792 /* Return nonzero if a return peephole merging return with
2793 setting of output register is ok. */
2795 leaf_return_peephole_ok (void)
2797 return (actual_fsize == 0);
2800 /* Return nonzero if a branch/jump/call instruction will be emitting
2801 nop into its delay slot. */
2804 empty_delay_slot (rtx insn)
2808 /* If no previous instruction (should not happen), return true. */
2809 if (PREV_INSN (insn) == NULL)
2812 seq = NEXT_INSN (PREV_INSN (insn));
2813 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2819 /* Return nonzero if TRIAL can go into the function epilogue's
2820 delay slot. SLOT is the slot we are trying to fill. */
2823 eligible_for_epilogue_delay (rtx trial, int slot)
2830 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2833 if (get_attr_length (trial) != 1)
2836 /* If there are any call-saved registers, we should scan TRIAL if it
2837 does not reference them. For now just make it easy. */
2841 /* If the function uses __builtin_eh_return, the eh_return machinery
2842 occupies the delay slot. */
2843 if (current_function_calls_eh_return)
2846 /* In the case of a true leaf function, anything can go into the delay slot.
2847 A delay slot only exists however if the frame size is zero, otherwise
2848 we will put an insn to adjust the stack after the return. */
2849 if (current_function_uses_only_leaf_regs)
2851 if (leaf_return_peephole_ok ())
2852 return ((get_attr_in_uncond_branch_delay (trial)
2853 == IN_BRANCH_DELAY_TRUE));
2857 pat = PATTERN (trial);
2859 /* Otherwise, only operations which can be done in tandem with
2860 a `restore' or `return' insn can go into the delay slot. */
2861 if (GET_CODE (SET_DEST (pat)) != REG
2862 || REGNO (SET_DEST (pat)) < 24)
2865 /* If this instruction sets up floating point register and we have a return
2866 instruction, it can probably go in. But restore will not work
2868 if (REGNO (SET_DEST (pat)) >= 32)
2870 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2871 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2876 /* The set of insns matched here must agree precisely with the set of
2877 patterns paired with a RETURN in sparc.md. */
2879 src = SET_SRC (pat);
2881 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2882 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2883 && arith_operand (src, GET_MODE (src)))
2886 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2888 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2891 /* This matches "*return_di". */
2892 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2893 && arith_double_operand (src, GET_MODE (src)))
2894 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2896 /* This matches "*return_sf_no_fpu". */
2897 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2898 && register_operand (src, SFmode))
2901 /* If we have return instruction, anything that does not use
2902 local or output registers and can go into a delay slot wins. */
2903 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2904 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2907 /* This matches "*return_addsi". */
2908 else if (GET_CODE (src) == PLUS
2909 && arith_operand (XEXP (src, 0), SImode)
2910 && arith_operand (XEXP (src, 1), SImode)
2911 && (register_operand (XEXP (src, 0), SImode)
2912 || register_operand (XEXP (src, 1), SImode)))
2915 /* This matches "*return_adddi". */
2916 else if (GET_CODE (src) == PLUS
2917 && arith_double_operand (XEXP (src, 0), DImode)
2918 && arith_double_operand (XEXP (src, 1), DImode)
2919 && (register_operand (XEXP (src, 0), DImode)
2920 || register_operand (XEXP (src, 1), DImode)))
2923 /* This can match "*return_losum_[sd]i".
2924 Catch only some cases, so that return_losum* don't have
2926 else if (GET_CODE (src) == LO_SUM
2927 && ! TARGET_CM_MEDMID
2928 && ((register_operand (XEXP (src, 0), SImode)
2929 && immediate_operand (XEXP (src, 1), SImode))
2931 && register_operand (XEXP (src, 0), DImode)
2932 && immediate_operand (XEXP (src, 1), DImode))))
2935 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2936 else if (GET_CODE (src) == ASHIFT
2937 && (register_operand (XEXP (src, 0), SImode)
2938 || register_operand (XEXP (src, 0), DImode))
2939 && XEXP (src, 1) == const1_rtx)
2945 /* Return nonzero if TRIAL can go into the call delay slot. */
2947 tls_call_delay (rtx trial)
2952 call __tls_get_addr, %tgd_call (foo)
2953 add %l7, %o0, %o0, %tgd_add (foo)
2954 while Sun as/ld does not. */
2955 if (TARGET_GNU_TLS || !TARGET_TLS)
2958 pat = PATTERN (trial);
2959 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2962 unspec = XEXP (SET_DEST (pat), 1);
2963 if (GET_CODE (unspec) != UNSPEC
2964 || (XINT (unspec, 1) != UNSPEC_TLSGD
2965 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2971 /* Return nonzero if TRIAL can go into the sibling call
2975 eligible_for_sibcall_delay (rtx trial)
2979 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2982 if (get_attr_length (trial) != 1)
2985 pat = PATTERN (trial);
2987 if (current_function_uses_only_leaf_regs)
2989 /* If the tail call is done using the call instruction,
2990 we have to restore %o7 in the delay slot. */
2991 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
2994 /* %g1 is used to build the function address */
2995 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3001 /* Otherwise, only operations which can be done in tandem with
3002 a `restore' insn can go into the delay slot. */
3003 if (GET_CODE (SET_DEST (pat)) != REG
3004 || REGNO (SET_DEST (pat)) < 24
3005 || REGNO (SET_DEST (pat)) >= 32)
3008 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3010 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3013 src = SET_SRC (pat);
3015 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3016 && arith_operand (src, GET_MODE (src)))
3019 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3021 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3024 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3025 && arith_double_operand (src, GET_MODE (src)))
3026 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3028 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
3029 && register_operand (src, SFmode))
3032 else if (GET_CODE (src) == PLUS
3033 && arith_operand (XEXP (src, 0), SImode)
3034 && arith_operand (XEXP (src, 1), SImode)
3035 && (register_operand (XEXP (src, 0), SImode)
3036 || register_operand (XEXP (src, 1), SImode)))
3039 else if (GET_CODE (src) == PLUS
3040 && arith_double_operand (XEXP (src, 0), DImode)
3041 && arith_double_operand (XEXP (src, 1), DImode)
3042 && (register_operand (XEXP (src, 0), DImode)
3043 || register_operand (XEXP (src, 1), DImode)))
3046 else if (GET_CODE (src) == LO_SUM
3047 && ! TARGET_CM_MEDMID
3048 && ((register_operand (XEXP (src, 0), SImode)
3049 && immediate_operand (XEXP (src, 1), SImode))
3051 && register_operand (XEXP (src, 0), DImode)
3052 && immediate_operand (XEXP (src, 1), DImode))))
3055 else if (GET_CODE (src) == ASHIFT
3056 && (register_operand (XEXP (src, 0), SImode)
3057 || register_operand (XEXP (src, 0), DImode))
3058 && XEXP (src, 1) == const1_rtx)
3065 check_return_regs (rtx x)
3067 switch (GET_CODE (x))
3070 return IN_OR_GLOBAL_P (x);
3085 if (check_return_regs (XEXP (x, 1)) == 0)
3090 return check_return_regs (XEXP (x, 0));
3099 short_branch (int uid1, int uid2)
3101 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3103 /* Leave a few words of "slop". */
3104 if (delta >= -1023 && delta <= 1022)
3110 /* Return nonzero if REG is not used after INSN.
3111 We assume REG is a reload reg, and therefore does
3112 not live past labels or calls or jumps. */
3114 reg_unused_after (rtx reg, rtx insn)
3116 enum rtx_code code, prev_code = UNKNOWN;
3118 while ((insn = NEXT_INSN (insn)))
3120 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3123 code = GET_CODE (insn);
3124 if (GET_CODE (insn) == CODE_LABEL)
3127 if (GET_RTX_CLASS (code) == 'i')
3129 rtx set = single_set (insn);
3130 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3133 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3135 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3143 /* Determine if it's legal to put X into the constant pool. This
3144 is not possible if X contains the address of a symbol that is
3145 not constant (TLS) or not known at final link time (PIC). */
3148 sparc_cannot_force_const_mem (rtx x)
3150 switch (GET_CODE (x))
3154 /* Accept all non-symbolic constants. */
3158 /* Labels are OK iff we are non-PIC. */
3159 return flag_pic != 0;
3162 /* 'Naked' TLS symbol references are never OK,
3163 non-TLS symbols are OK iff we are non-PIC. */
3164 if (SYMBOL_REF_TLS_MODEL (x))
3167 return flag_pic != 0;
3170 return sparc_cannot_force_const_mem (XEXP (x, 0));
3173 return sparc_cannot_force_const_mem (XEXP (x, 0))
3174 || sparc_cannot_force_const_mem (XEXP (x, 1));
3182 /* The table we use to reference PIC data. */
3183 static GTY(()) rtx global_offset_table;
3185 /* The function we use to get at it. */
3186 static GTY(()) rtx get_pc_symbol;
3187 static GTY(()) char get_pc_symbol_name[256];
3189 /* Ensure that we are not using patterns that are not OK with PIC. */
3197 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3198 || (GET_CODE (recog_data.operand[i]) == CONST
3199 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3200 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3201 == global_offset_table)
3202 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3211 /* Return true if X is an address which needs a temporary register when
3212 reloaded while generating PIC code. */
3215 pic_address_needs_scratch (rtx x)
3217 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3218 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3219 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3220 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3221 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3227 /* Determine if a given RTX is a valid constant. We already know this
3228 satisfies CONSTANT_P. */
3231 legitimate_constant_p (rtx x)
3235 switch (GET_CODE (x))
3238 /* TLS symbols are not constant. */
3239 if (SYMBOL_REF_TLS_MODEL (x))
3244 inner = XEXP (x, 0);
3246 /* Offsets of TLS symbols are never valid.
3247 Discourage CSE from creating them. */
3248 if (GET_CODE (inner) == PLUS
3249 && tls_symbolic_operand (XEXP (inner, 0)))
3254 if (GET_MODE (x) == VOIDmode)
3257 /* Floating point constants are generally not ok.
3258 The only exception is 0.0 in VIS. */
3260 && (GET_MODE (x) == SFmode
3261 || GET_MODE (x) == DFmode
3262 || GET_MODE (x) == TFmode)
3263 && fp_zero_operand (x, GET_MODE (x)))
3275 /* Determine if a given RTX is a valid constant address. */
3278 constant_address_p (rtx x)
3280 switch (GET_CODE (x))
3288 if (flag_pic && pic_address_needs_scratch (x))
3290 return legitimate_constant_p (x);
3293 return !flag_pic && legitimate_constant_p (x);
3300 /* Nonzero if the constant value X is a legitimate general operand
3301 when generating PIC code. It is given that flag_pic is on and
3302 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3305 legitimate_pic_operand_p (rtx x)
3307 if (pic_address_needs_scratch (x))
3309 if (tls_symbolic_operand (x)
3310 || (GET_CODE (x) == CONST
3311 && GET_CODE (XEXP (x, 0)) == PLUS
3312 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3317 /* Return nonzero if ADDR is a valid memory address.
3318 STRICT specifies whether strict register checking applies. */
3321 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3323 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
3325 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3327 else if (GET_CODE (addr) == PLUS)
3329 rs1 = XEXP (addr, 0);
3330 rs2 = XEXP (addr, 1);
3332 /* Canonicalize. REG comes first, if there are no regs,
3333 LO_SUM comes first. */
3335 && GET_CODE (rs1) != SUBREG
3337 || GET_CODE (rs2) == SUBREG
3338 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3340 rs1 = XEXP (addr, 1);
3341 rs2 = XEXP (addr, 0);
3345 && rs1 == pic_offset_table_rtx
3347 && GET_CODE (rs2) != SUBREG
3348 && GET_CODE (rs2) != LO_SUM
3349 && GET_CODE (rs2) != MEM
3350 && !tls_symbolic_operand (rs2)
3351 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3352 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3354 || GET_CODE (rs1) == SUBREG)
3355 && RTX_OK_FOR_OFFSET_P (rs2)))
3360 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3361 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3363 /* We prohibit REG + REG for TFmode when there are no quad move insns
3364 and we consequently need to split. We do this because REG+REG
3365 is not an offsettable address. If we get the situation in reload
3366 where source and destination of a movtf pattern are both MEMs with
3367 REG+REG address, then only one of them gets converted to an
3368 offsettable address. */
3370 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
3373 /* We prohibit REG + REG on ARCH32 if not optimizing for
3374 DFmode/DImode because then mem_min_alignment is likely to be zero
3375 after reload and the forced split would lack a matching splitter
3377 if (TARGET_ARCH32 && !optimize
3378 && (mode == DFmode || mode == DImode))
3381 else if (USE_AS_OFFSETABLE_LO10
3382 && GET_CODE (rs1) == LO_SUM
3384 && ! TARGET_CM_MEDMID
3385 && RTX_OK_FOR_OLO10_P (rs2))
3388 imm1 = XEXP (rs1, 1);
3389 rs1 = XEXP (rs1, 0);
3390 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3394 else if (GET_CODE (addr) == LO_SUM)
3396 rs1 = XEXP (addr, 0);
3397 imm1 = XEXP (addr, 1);
3399 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3402 /* We can't allow TFmode in 32-bit mode, because an offset greater
3403 than the alignment (8) may cause the LO_SUM to overflow. */
3404 if (mode == TFmode && TARGET_ARCH32)
3407 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3412 if (GET_CODE (rs1) == SUBREG)
3413 rs1 = SUBREG_REG (rs1);
3419 if (GET_CODE (rs2) == SUBREG)
3420 rs2 = SUBREG_REG (rs2);
3427 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3428 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3433 if ((REGNO (rs1) >= 32
3434 && REGNO (rs1) != FRAME_POINTER_REGNUM
3435 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3437 && (REGNO (rs2) >= 32
3438 && REGNO (rs2) != FRAME_POINTER_REGNUM
3439 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3445 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3447 static GTY(()) rtx sparc_tls_symbol;
3449 sparc_tls_get_addr (void)
3451 if (!sparc_tls_symbol)
3452 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3454 return sparc_tls_symbol;
3458 sparc_tls_got (void)
3463 current_function_uses_pic_offset_table = 1;
3464 return pic_offset_table_rtx;
3467 if (!global_offset_table)
3468 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3469 temp = gen_reg_rtx (Pmode);
3470 emit_move_insn (temp, global_offset_table);
3475 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3476 this (thread-local) address. */
3479 legitimize_tls_address (rtx addr)
3481 rtx temp1, temp2, temp3, ret, o0, got, insn;
3486 if (GET_CODE (addr) == SYMBOL_REF)
3487 switch (SYMBOL_REF_TLS_MODEL (addr))
3489 case TLS_MODEL_GLOBAL_DYNAMIC:
3491 temp1 = gen_reg_rtx (SImode);
3492 temp2 = gen_reg_rtx (SImode);
3493 ret = gen_reg_rtx (Pmode);
3494 o0 = gen_rtx_REG (Pmode, 8);
3495 got = sparc_tls_got ();
3496 emit_insn (gen_tgd_hi22 (temp1, addr));
3497 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3500 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3501 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3506 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3507 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3510 CALL_INSN_FUNCTION_USAGE (insn)
3511 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3512 CALL_INSN_FUNCTION_USAGE (insn));
3513 insn = get_insns ();
3515 emit_libcall_block (insn, ret, o0, addr);
3518 case TLS_MODEL_LOCAL_DYNAMIC:
3520 temp1 = gen_reg_rtx (SImode);
3521 temp2 = gen_reg_rtx (SImode);
3522 temp3 = gen_reg_rtx (Pmode);
3523 ret = gen_reg_rtx (Pmode);
3524 o0 = gen_rtx_REG (Pmode, 8);
3525 got = sparc_tls_got ();
3526 emit_insn (gen_tldm_hi22 (temp1));
3527 emit_insn (gen_tldm_lo10 (temp2, temp1));
3530 emit_insn (gen_tldm_add32 (o0, got, temp2));
3531 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3536 emit_insn (gen_tldm_add64 (o0, got, temp2));
3537 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3540 CALL_INSN_FUNCTION_USAGE (insn)
3541 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3542 CALL_INSN_FUNCTION_USAGE (insn));
3543 insn = get_insns ();
3545 emit_libcall_block (insn, temp3, o0,
3546 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3547 UNSPEC_TLSLD_BASE));
3548 temp1 = gen_reg_rtx (SImode);
3549 temp2 = gen_reg_rtx (SImode);
3550 emit_insn (gen_tldo_hix22 (temp1, addr));
3551 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3553 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3555 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3558 case TLS_MODEL_INITIAL_EXEC:
3559 temp1 = gen_reg_rtx (SImode);
3560 temp2 = gen_reg_rtx (SImode);
3561 temp3 = gen_reg_rtx (Pmode);
3562 got = sparc_tls_got ();
3563 emit_insn (gen_tie_hi22 (temp1, addr));
3564 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3566 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3568 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3571 ret = gen_reg_rtx (Pmode);
3573 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3576 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3580 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3583 case TLS_MODEL_LOCAL_EXEC:
3584 temp1 = gen_reg_rtx (Pmode);
3585 temp2 = gen_reg_rtx (Pmode);
3588 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3589 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3593 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3594 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3596 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3604 abort (); /* for now ... */
3610 /* Legitimize PIC addresses. If the address is already position-independent,
3611 we return ORIG. Newly generated position-independent addresses go into a
3612 reg. This is REG if nonzero, otherwise we allocate register(s) as
3616 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3619 if (GET_CODE (orig) == SYMBOL_REF)
3621 rtx pic_ref, address;
3626 if (reload_in_progress || reload_completed)
3629 reg = gen_reg_rtx (Pmode);
3634 /* If not during reload, allocate another temp reg here for loading
3635 in the address, so that these instructions can be optimized
3637 rtx temp_reg = ((reload_in_progress || reload_completed)
3638 ? reg : gen_reg_rtx (Pmode));
3640 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3641 won't get confused into thinking that these two instructions
3642 are loading in the true address of the symbol. If in the
3643 future a PIC rtx exists, that should be used instead. */
3644 if (Pmode == SImode)
3646 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3647 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3651 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3652 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3659 pic_ref = gen_rtx_MEM (Pmode,
3660 gen_rtx_PLUS (Pmode,
3661 pic_offset_table_rtx, address));
3662 current_function_uses_pic_offset_table = 1;
3663 RTX_UNCHANGING_P (pic_ref) = 1;
3664 insn = emit_move_insn (reg, pic_ref);
3665 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3667 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3671 else if (GET_CODE (orig) == CONST)
3675 if (GET_CODE (XEXP (orig, 0)) == PLUS
3676 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3681 if (reload_in_progress || reload_completed)
3684 reg = gen_reg_rtx (Pmode);
3687 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3689 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3690 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3691 base == reg ? 0 : reg);
3696 if (GET_CODE (offset) == CONST_INT)
3698 if (SMALL_INT (offset))
3699 return plus_constant (base, INTVAL (offset));
3700 else if (! reload_in_progress && ! reload_completed)
3701 offset = force_reg (Pmode, offset);
3703 /* If we reach here, then something is seriously wrong. */
3706 return gen_rtx_PLUS (Pmode, base, offset);
3708 else if (GET_CODE (orig) == LABEL_REF)
3709 /* ??? Why do we do this? */
3710 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3711 the register is live instead, in case it is eliminated. */
3712 current_function_uses_pic_offset_table = 1;
3717 /* Try machine-dependent ways of modifying an illegitimate address X
3718 to be legitimate. If we find one, return the new, valid address.
3720 OLDX is the address as it was before break_out_memory_refs was called.
3721 In some cases it is useful to look at this to decide what needs to be done.
3723 MODE is the mode of the operand pointed to by X. */
3726 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3730 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3731 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3732 force_operand (XEXP (x, 0), NULL_RTX));
3733 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3734 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3735 force_operand (XEXP (x, 1), NULL_RTX));
3736 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3737 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3739 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3740 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3741 force_operand (XEXP (x, 1), NULL_RTX));
3743 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3746 if (tls_symbolic_operand (x))
3747 x = legitimize_tls_address (x);
3749 x = legitimize_pic_address (x, mode, 0);
3750 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3751 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3752 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3753 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3754 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3755 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3756 else if (GET_CODE (x) == SYMBOL_REF
3757 || GET_CODE (x) == CONST
3758 || GET_CODE (x) == LABEL_REF)
3759 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3763 /* Emit special PIC prologues. */
3766 load_pic_register (void)
3768 /* Labels to get the PC in the prologue of this function. */
3769 int orig_flag_pic = flag_pic;
3774 /* If we haven't emitted the special get_pc helper function, do so now. */
3775 if (get_pc_symbol_name[0] == 0)
3779 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3782 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3784 ASM_OUTPUT_ALIGN (asm_out_file, align);
3785 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3786 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3789 /* Initialize every time through, since we can't easily
3790 know this to be permanent. */
3791 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3792 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3795 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3798 flag_pic = orig_flag_pic;
3800 /* Need to emit this whether or not we obey regdecls,
3801 since setjmp/longjmp can cause life info to screw up.
3802 ??? In the case where we don't obey regdecls, this is not sufficient
3803 since we may not fall out the bottom. */
3804 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3807 /* Return 1 if RTX is a MEM which is known to be aligned to at
3808 least a DESIRED byte boundary. */
3811 mem_min_alignment (rtx mem, int desired)
3813 rtx addr, base, offset;
3815 /* If it's not a MEM we can't accept it. */
3816 if (GET_CODE (mem) != MEM)
3819 addr = XEXP (mem, 0);
3820 base = offset = NULL_RTX;
3821 if (GET_CODE (addr) == PLUS)
3823 if (GET_CODE (XEXP (addr, 0)) == REG)
3825 base = XEXP (addr, 0);
3827 /* What we are saying here is that if the base
3828 REG is aligned properly, the compiler will make
3829 sure any REG based index upon it will be so
3831 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3832 offset = XEXP (addr, 1);
3834 offset = const0_rtx;
3837 else if (GET_CODE (addr) == REG)
3840 offset = const0_rtx;
3843 if (base != NULL_RTX)
3845 int regno = REGNO (base);
3847 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3849 /* Check if the compiler has recorded some information
3850 about the alignment of the base REG. If reload has
3851 completed, we already matched with proper alignments.
3852 If not running global_alloc, reload might give us
3853 unaligned pointer to local stack though. */
3855 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3856 || (optimize && reload_completed))
3857 && (INTVAL (offset) & (desired - 1)) == 0)
3862 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3866 else if (! TARGET_UNALIGNED_DOUBLES
3867 || CONSTANT_P (addr)
3868 || GET_CODE (addr) == LO_SUM)
3870 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3871 is true, in which case we can only assume that an access is aligned if
3872 it is to a constant address, or the address involves a LO_SUM. */
3876 /* An obviously unaligned address. */
3881 /* Vectors to keep interesting information about registers where it can easily
3882 be got. We used to use the actual mode value as the bit number, but there
3883 are more than 32 modes now. Instead we use two tables: one indexed by
3884 hard register number, and one indexed by mode. */
3886 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3887 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3888 mapped into one sparc_mode_class mode. */
3890 enum sparc_mode_class {
3891 S_MODE, D_MODE, T_MODE, O_MODE,
3892 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3896 /* Modes for single-word and smaller quantities. */
3897 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3899 /* Modes for double-word and smaller quantities. */
3900 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3902 /* Modes for quad-word and smaller quantities. */
3903 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3905 /* Modes for 8-word and smaller quantities. */
3906 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3908 /* Modes for single-float quantities. We must allow any single word or
3909 smaller quantity. This is because the fix/float conversion instructions
3910 take integer inputs/outputs from the float registers. */
3911 #define SF_MODES (S_MODES)
3913 /* Modes for double-float and smaller quantities. */
3914 #define DF_MODES (S_MODES | D_MODES)
3916 /* Modes for double-float only quantities. */
3917 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3919 /* Modes for quad-float only quantities. */
3920 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3922 /* Modes for quad-float and smaller quantities. */
3923 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3925 /* Modes for quad-float and double-float quantities. */
3926 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3928 /* Modes for quad-float pair only quantities. */
3929 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3931 /* Modes for quad-float pairs and smaller quantities. */
3932 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3934 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3936 /* Modes for condition codes. */
3937 #define CC_MODES (1 << (int) CC_MODE)
3938 #define CCFP_MODES (1 << (int) CCFP_MODE)
3940 /* Value is 1 if register/mode pair is acceptable on sparc.
3941 The funny mixture of D and T modes is because integer operations
3942 do not specially operate on tetra quantities, so non-quad-aligned
3943 registers can hold quadword quantities (except %o4 and %i4 because
3944 they cross fixed registers). */
3946 /* This points to either the 32 bit or the 64 bit version. */
3947 const int *hard_regno_mode_classes;
3949 static const int hard_32bit_mode_classes[] = {
3950 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3951 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3952 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3953 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3955 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3956 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3957 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3958 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3960 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3961 and none can hold SFmode/SImode values. */
3962 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3963 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3964 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3965 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3968 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3974 static const int hard_64bit_mode_classes[] = {
3975 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3976 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3977 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3978 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3980 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3981 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3982 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3983 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3985 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3986 and none can hold SFmode/SImode values. */
3987 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3988 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3989 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3990 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3993 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3999 int sparc_mode_class [NUM_MACHINE_MODES];
4001 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4004 sparc_init_modes (void)
4008 for (i = 0; i < NUM_MACHINE_MODES; i++)
4010 switch (GET_MODE_CLASS (i))
4013 case MODE_PARTIAL_INT:
4014 case MODE_COMPLEX_INT:
4015 if (GET_MODE_SIZE (i) <= 4)
4016 sparc_mode_class[i] = 1 << (int) S_MODE;
4017 else if (GET_MODE_SIZE (i) == 8)
4018 sparc_mode_class[i] = 1 << (int) D_MODE;
4019 else if (GET_MODE_SIZE (i) == 16)
4020 sparc_mode_class[i] = 1 << (int) T_MODE;
4021 else if (GET_MODE_SIZE (i) == 32)
4022 sparc_mode_class[i] = 1 << (int) O_MODE;
4024 sparc_mode_class[i] = 0;
4027 case MODE_COMPLEX_FLOAT:
4028 if (GET_MODE_SIZE (i) <= 4)
4029 sparc_mode_class[i] = 1 << (int) SF_MODE;
4030 else if (GET_MODE_SIZE (i) == 8)
4031 sparc_mode_class[i] = 1 << (int) DF_MODE;
4032 else if (GET_MODE_SIZE (i) == 16)
4033 sparc_mode_class[i] = 1 << (int) TF_MODE;
4034 else if (GET_MODE_SIZE (i) == 32)
4035 sparc_mode_class[i] = 1 << (int) OF_MODE;
4037 sparc_mode_class[i] = 0;
4040 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4041 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4043 sparc_mode_class[i] = 1 << (int) CC_MODE;
4046 sparc_mode_class[i] = 0;
4052 hard_regno_mode_classes = hard_64bit_mode_classes;
4054 hard_regno_mode_classes = hard_32bit_mode_classes;
4056 /* Initialize the array used by REGNO_REG_CLASS. */
4057 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4059 if (i < 16 && TARGET_V8PLUS)
4060 sparc_regno_reg_class[i] = I64_REGS;
4061 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4062 sparc_regno_reg_class[i] = GENERAL_REGS;
4064 sparc_regno_reg_class[i] = FP_REGS;
4066 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4068 sparc_regno_reg_class[i] = FPCC_REGS;
4070 sparc_regno_reg_class[i] = NO_REGS;
4074 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
4075 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4076 v9 int regs as it simplifies the code. */
4079 save_regs (FILE *file, int low, int high, const char *base,
4080 int offset, int n_regs, HOST_WIDE_INT real_offset)
4084 if (TARGET_ARCH64 && high <= 32)
4086 for (i = low; i < high; i++)
4088 if (regs_ever_live[i] && ! call_used_regs[i])
4090 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4091 reg_names[i], base, offset + 4 * n_regs);
4092 if (dwarf2out_do_frame ())
4093 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4100 for (i = low; i < high; i += 2)
4102 if (regs_ever_live[i] && ! call_used_regs[i])
4104 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4106 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4107 reg_names[i], base, offset + 4 * n_regs);
4108 if (dwarf2out_do_frame ())
4110 char *l = dwarf2out_cfi_label ();
4111 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4112 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4118 fprintf (file, "\tst\t%s, [%s+%d]\n",
4119 reg_names[i], base, offset + 4 * n_regs);
4120 if (dwarf2out_do_frame ())
4121 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4127 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4129 fprintf (file, "\tst\t%s, [%s+%d]\n",
4130 reg_names[i+1], base, offset + 4 * n_regs + 4);
4131 if (dwarf2out_do_frame ())
4132 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4141 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4143 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4144 v9 int regs as it simplifies the code. */
4147 restore_regs (FILE *file, int low, int high, const char *base,
4148 int offset, int n_regs)
4152 if (TARGET_ARCH64 && high <= 32)
4154 for (i = low; i < high; i++)
4156 if (regs_ever_live[i] && ! call_used_regs[i])
4157 fprintf (file, "\tldx\t[%s+%d], %s\n",
4158 base, offset + 4 * n_regs, reg_names[i]),
4164 for (i = low; i < high; i += 2)
4166 if (regs_ever_live[i] && ! call_used_regs[i])
4167 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4168 fprintf (file, "\tldd\t[%s+%d], %s\n",
4169 base, offset + 4 * n_regs, reg_names[i]),
4172 fprintf (file, "\tld\t[%s+%d], %s\n",
4173 base, offset + 4 * n_regs, reg_names[i]),
4175 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4176 fprintf (file, "\tld\t[%s+%d], %s\n",
4177 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4184 /* Compute the frame size required by the function. This function is called
4185 during the reload pass and also by output_function_prologue(). */
4188 compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4191 int outgoing_args_size = (current_function_outgoing_args_size
4192 + REG_PARM_STACK_SPACE (current_function_decl));
4194 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4195 even to v9 int regs to be consistent with save_regs/restore_regs. */
4199 for (i = 0; i < 8; i++)
4200 if (regs_ever_live[i] && ! call_used_regs[i])
4205 for (i = 0; i < 8; i += 2)
4206 if ((regs_ever_live[i] && ! call_used_regs[i])
4207 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4211 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4212 if ((regs_ever_live[i] && ! call_used_regs[i])
4213 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4216 /* Set up values for use in `function_epilogue'. */
4217 num_gfregs = n_regs;
4219 if (leaf_function && n_regs == 0
4220 && size == 0 && current_function_outgoing_args_size == 0)
4222 actual_fsize = apparent_fsize = 0;
4226 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4227 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4228 apparent_fsize += n_regs * 4;
4229 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4232 /* Make sure nothing can clobber our register windows.
4233 If a SAVE must be done, or there is a stack-local variable,
4234 the register window area must be allocated.
4235 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4236 if (leaf_function == 0 || size > 0)
4237 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4239 return SPARC_STACK_ALIGN (actual_fsize);
4242 /* Build big number NUM in register REG and output the result to FILE.
4243 REG is guaranteed to be the only clobbered register. The function
4244 will very likely emit several instructions, so it must not be called
4245 from within a delay slot. */
4248 build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg)
4250 #if HOST_BITS_PER_WIDE_INT == 64
4251 HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff;
4259 /* We don't use the 'set' macro because it appears to be broken
4260 in the Solaris 7 assembler. */
4261 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4263 if ((num & 0x3ff) != 0)
4264 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4267 #if HOST_BITS_PER_WIDE_INT == 64
4268 else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */
4270 else /* num < 0 && TARGET_ARCH64 */
4273 /* Sethi does not sign extend, so we must use a little trickery
4274 to use it for negative numbers. Invert the constant before
4275 loading it in, then use xor immediate to invert the loaded bits
4276 (along with the upper 32 bits) to the desired constant. This
4277 works because the sethi and immediate fields overlap. */
4278 HOST_WIDE_INT inv = ~num;
4279 HOST_WIDE_INT low = -0x400 + (num & 0x3ff);
4281 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4283 fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4286 #if HOST_BITS_PER_WIDE_INT == 64
4287 else /* TARGET_ARCH64 */
4289 /* We don't use the 'setx' macro because if requires a scratch register.
4290 This is the translation of sparc_emit_set_const64_longway into asm.
4291 Hopefully we will soon have prologue/epilogue emitted as RTL. */
4292 HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff;
4293 HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff;
4294 HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff;
4297 /* We don't use the 'set' macro because it appears to be broken
4298 in the Solaris 7 assembler. */
4299 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4301 if ((high_bits & 0x3ff) != 0)
4302 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4303 reg, high_bits, reg);
4307 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4308 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4318 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4319 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4327 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4329 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4335 /* Output any necessary .register pseudo-ops. */
4337 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4339 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4345 /* Check if %g[2367] were used without
4346 .register being printed for them already. */
4347 for (i = 2; i < 8; i++)
4349 if (regs_ever_live [i]
4350 && ! sparc_hard_reg_printed [i])
4352 sparc_hard_reg_printed [i] = 1;
4353 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4360 /* This function generates the assembly code for function entry.
4361 FILE is a stdio stream to output the code to.
4362 SIZE is an int: how many units of temporary storage to allocate.
4363 Refer to the array `regs_ever_live' to determine which registers
4364 to save; `regs_ever_live[I]' is nonzero if register number I
4365 is ever used in the function. This macro is responsible for
4366 knowing which registers should not be saved even if used. */
4368 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4369 of memory. If any fpu reg is used in the function, we allocate
4370 such a block here, at the bottom of the frame, just in case it's needed.
4372 If this function is a leaf procedure, then we may choose not
4373 to do a "save" insn. The decision about whether or not
4374 to do this is made in regclass.c. */
4377 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4380 sparc_flat_function_prologue (file, size);
4382 sparc_nonflat_function_prologue (file, size,
4383 current_function_uses_only_leaf_regs);
4386 /* Output code for the function prologue. */
4389 sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
4392 sparc_output_scratch_registers (file);
4394 /* Need to use actual_fsize, since we are also allocating
4395 space for our callee (and our own register save area). */
4396 actual_fsize = compute_frame_size (size, leaf_function);
4400 frame_base_name = "%sp";
4401 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4405 frame_base_name = "%fp";
4406 frame_base_offset = SPARC_STACK_BIAS;
4409 /* This is only for the human reader. */
4410 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4412 if (actual_fsize == 0)
4414 else if (! leaf_function)
4416 if (actual_fsize <= 4096)
4417 fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4419 else if (actual_fsize <= 8192)
4421 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4422 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4423 actual_fsize - 4096);
4427 build_big_number (file, -actual_fsize, "%g1");
4428 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4431 else /* leaf function */
4433 if (actual_fsize <= 4096)
4434 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4436 else if (actual_fsize <= 8192)
4438 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4439 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4440 actual_fsize - 4096);
4444 build_big_number (file, -actual_fsize, "%g1");
4445 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4449 if (dwarf2out_do_frame () && actual_fsize)
4451 char *label = dwarf2out_cfi_label ();
4453 /* The canonical frame address refers to the top of the frame. */
4454 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4455 : HARD_FRAME_POINTER_REGNUM),
4458 if (! leaf_function)
4460 /* Note the register window save. This tells the unwinder that
4461 it needs to restore the window registers from the previous
4462 frame's window save area at 0(cfa). */
4463 dwarf2out_window_save (label);
4465 /* The return address (-8) is now in %i7. */
4466 dwarf2out_return_reg (label, 31);
4470 /* If doing anything with PIC, do it now. */
4472 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4474 /* Call saved registers are saved just above the outgoing argument area. */
4477 HOST_WIDE_INT offset, real_offset;
4481 real_offset = -apparent_fsize;
4482 offset = -apparent_fsize + frame_base_offset;
4483 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4485 /* ??? This might be optimized a little as %g1 might already have a
4486 value close enough that a single add insn will do. */
4487 /* ??? Although, all of this is probably only a temporary fix
4488 because if %g1 can hold a function result, then
4489 output_function_epilogue will lose (the result will get
4491 build_big_number (file, offset, "%g1");
4492 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4498 base = frame_base_name;
4501 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4502 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4507 /* Output code to restore any call saved registers. */
4510 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4512 HOST_WIDE_INT offset;
4516 offset = -apparent_fsize + frame_base_offset;
4517 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4519 build_big_number (file, offset, "%g1");
4520 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4526 base = frame_base_name;
4529 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4530 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4533 /* This function generates the assembly code for function exit,
4534 on machines that need it.
4536 The function epilogue should not depend on the current stack pointer!
4537 It should use the frame pointer only. This is mandatory because
4538 of alloca; we also take advantage of it to omit stack adjustments
4539 before returning. */
4542 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4545 sparc_flat_function_epilogue (file, size);
4547 sparc_nonflat_function_epilogue (file, size,
4548 current_function_uses_only_leaf_regs);
4551 /* Output code for the function epilogue. */
4554 sparc_nonflat_function_epilogue (FILE *file,
4555 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4560 if (current_function_epilogue_delay_list == 0)
4562 /* If code does not drop into the epilogue, we need
4563 do nothing except output pending case vectors.
4565 We have to still output a dummy nop for the sake of
4566 sane backtraces. Otherwise, if the last two instructions
4567 of a function were call foo; dslot; this can make the return
4568 PC of foo (ie. address of call instruction plus 8) point to
4569 the first instruction in the next function. */
4570 rtx insn, last_real_insn;
4572 insn = get_last_insn ();
4574 last_real_insn = prev_real_insn (insn);
4576 && GET_CODE (last_real_insn) == INSN
4577 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4578 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4580 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4581 fputs("\tnop\n", file);
4583 if (GET_CODE (insn) == NOTE)
4584 insn = prev_nonnote_insn (insn);
4585 if (insn && GET_CODE (insn) == BARRIER)
4586 goto output_vectors;
4590 output_restore_regs (file, leaf_function);
4592 /* Work out how to skip the caller's unimp instruction if required. */
4594 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4596 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4598 if (! leaf_function)
4600 if (current_function_calls_eh_return)
4602 if (current_function_epilogue_delay_list)
4604 if (SKIP_CALLERS_UNIMP_P)
4607 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4609 /* If we wound up with things in our delay slot, flush them here. */
4610 else if (current_function_epilogue_delay_list)
4612 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4614 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4616 epilogue_renumber (&delay, 0);
4617 fputs (SKIP_CALLERS_UNIMP_P
4618 ? "\treturn\t%i7+12\n"
4619 : "\treturn\t%i7+8\n", file);
4620 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4621 file, 1, 0, 0, NULL);
4627 if (GET_CODE (delay) != SET)
4630 src = SET_SRC (delay);
4631 if (GET_CODE (src) == ASHIFT)
4633 if (XEXP (src, 1) != const1_rtx)
4636 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4640 insn = gen_rtx_PARALLEL (VOIDmode,
4641 gen_rtvec (2, delay,
4642 gen_rtx_RETURN (VOIDmode)));
4643 insn = emit_jump_insn (insn);
4645 sparc_emitting_epilogue = true;
4646 final_scan_insn (insn, file, 1, 0, 1, NULL);
4647 sparc_emitting_epilogue = false;
4650 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4651 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4653 fprintf (file, "\t%s\n\trestore\n", ret);
4655 /* All of the following cases are for leaf functions. */
4656 else if (current_function_calls_eh_return)
4658 else if (current_function_epilogue_delay_list)
4660 /* eligible_for_epilogue_delay_slot ensures that if this is a
4661 leaf function, then we will only have insn in the delay slot
4662 if the frame size is zero, thus no adjust for the stack is
4664 if (actual_fsize != 0)
4666 fprintf (file, "\t%s\n", ret);
4667 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4668 file, 1, 0, 1, NULL);
4670 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4671 avoid generating confusing assembly language output. */
4672 else if (actual_fsize == 0)
4673 fprintf (file, "\t%s\n\tnop\n", ret);
4674 else if (actual_fsize <= 4096)
4675 fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4677 else if (actual_fsize <= 8192)
4678 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4679 ret, actual_fsize - 4096);
4682 build_big_number (file, actual_fsize, "%g1");
4683 fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret);
4687 sparc_output_deferred_case_vectors ();
4690 /* Output a sibling call. */
4693 output_sibcall (rtx insn, rtx call_operand)
4695 int leaf_regs = current_function_uses_only_leaf_regs;
4697 int delay_slot = dbr_sequence_length () > 0;
4701 /* Call to restore global regs might clobber
4702 the delay slot. Instead of checking for this
4703 output the delay slot now. */
4706 rtx delay = NEXT_INSN (insn);
4711 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4712 PATTERN (delay) = gen_blockage ();
4713 INSN_CODE (delay) = -1;
4716 output_restore_regs (asm_out_file, leaf_regs);
4719 operands[0] = call_operand;
4723 #ifdef HAVE_AS_RELAX_OPTION
4724 /* If as and ld are relaxing tail call insns into branch always,
4725 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4726 be optimized. With sethi/jmpl as nor ld has no easy way how to
4727 find out if somebody does not branch between the sethi and jmpl. */
4730 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4732 HOST_WIDE_INT size = 0;
4734 if ((actual_fsize || ! spare_slot) && delay_slot)
4736 rtx delay = NEXT_INSN (insn);
4741 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4742 PATTERN (delay) = gen_blockage ();
4743 INSN_CODE (delay) = -1;
4748 if (actual_fsize <= 4096)
4749 size = actual_fsize;
4750 else if (actual_fsize <= 8192)
4752 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4753 size = actual_fsize - 4096;
4757 build_big_number (asm_out_file, actual_fsize, "%g1");
4758 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4763 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4764 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4766 fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4767 else if (! delay_slot)
4768 fputs ("\t nop\n", asm_out_file);
4773 fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4774 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4775 it into branch if possible. */
4776 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4777 output_asm_insn ("call\t%a0, 0", operands);
4778 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4783 output_asm_insn ("call\t%a0, 0", operands);
4786 rtx delay = NEXT_INSN (insn), pat;
4791 pat = PATTERN (delay);
4792 if (GET_CODE (pat) != SET)
4795 operands[0] = SET_DEST (pat);
4796 pat = SET_SRC (pat);
4797 switch (GET_CODE (pat))
4800 operands[1] = XEXP (pat, 0);
4801 operands[2] = XEXP (pat, 1);
4802 output_asm_insn (" restore %r1, %2, %Y0", operands);
4805 operands[1] = XEXP (pat, 0);
4806 operands[2] = XEXP (pat, 1);
4807 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4810 operands[1] = XEXP (pat, 0);
4811 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4815 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4818 PATTERN (delay) = gen_blockage ();
4819 INSN_CODE (delay) = -1;
4822 fputs ("\t restore\n", asm_out_file);
4826 /* Functions for handling argument passing.
4828 For v8 the first six args are normally in registers and the rest are
4829 pushed. Any arg that starts within the first 6 words is at least
4830 partially passed in a register unless its data type forbids.
4832 For v9, the argument registers are laid out as an array of 16 elements
4833 and arguments are added sequentially. The first 6 int args and up to the
4834 first 16 fp args (depending on size) are passed in regs.
4836 Slot Stack Integral Float Float in structure Double Long Double
4837 ---- ----- -------- ----- ------------------ ------ -----------
4838 15 [SP+248] %f31 %f30,%f31 %d30
4839 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4840 13 [SP+232] %f27 %f26,%f27 %d26
4841 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4842 11 [SP+216] %f23 %f22,%f23 %d22
4843 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4844 9 [SP+200] %f19 %f18,%f19 %d18
4845 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4846 7 [SP+184] %f15 %f14,%f15 %d14
4847 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4848 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4849 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4850 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4851 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4852 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4853 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4855 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4857 Integral arguments are always passed as 64 bit quantities appropriately
4860 Passing of floating point values is handled as follows.
4861 If a prototype is in scope:
4862 If the value is in a named argument (i.e. not a stdarg function or a
4863 value not part of the `...') then the value is passed in the appropriate
4865 If the value is part of the `...' and is passed in one of the first 6
4866 slots then the value is passed in the appropriate int reg.
4867 If the value is part of the `...' and is not passed in one of the first 6
4868 slots then the value is passed in memory.
4869 If a prototype is not in scope:
4870 If the value is one of the first 6 arguments the value is passed in the
4871 appropriate integer reg and the appropriate fp reg.
4872 If the value is not one of the first 6 arguments the value is passed in
4873 the appropriate fp reg and in memory.
4876 /* Maximum number of int regs for args. */
4877 #define SPARC_INT_ARG_MAX 6
4878 /* Maximum number of fp regs for args. */
4879 #define SPARC_FP_ARG_MAX 16
4881 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4883 /* Handle the INIT_CUMULATIVE_ARGS macro.
4884 Initialize a variable CUM of type CUMULATIVE_ARGS
4885 for a call to a function whose data type is FNTYPE.
4886 For a library call, FNTYPE is 0. */
4889 init_cumulative_args (struct sparc_args *cum, tree fntype,
4890 rtx libname ATTRIBUTE_UNUSED,
4891 tree fndecl ATTRIBUTE_UNUSED)
4894 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4895 cum->libcall_p = fntype == 0;
4898 /* Scan the record type TYPE and return the following predicates:
4899 - INTREGS_P: the record contains at least one field or sub-field
4900 that is eligible for promotion in integer registers.
4901 - FP_REGS_P: the record contains at least one field or sub-field
4902 that is eligible for promotion in floating-point registers.
4903 - PACKED_P: the record contains at least one field that is packed.
4905 Sub-fields are not taken into account for the PACKED_P predicate. */
4908 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
4912 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4914 if (TREE_CODE (field) == FIELD_DECL)
4916 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4917 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
4918 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
4923 if (packed_p && DECL_PACKED (field))
4929 /* Compute the slot number to pass an argument in.
4930 Return the slot number or -1 if passing on the stack.
4932 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4933 the preceding args and about the function being called.
4934 MODE is the argument's machine mode.
4935 TYPE is the data type of the argument (as a tree).
4936 This is null for libcalls where that information may
4938 NAMED is nonzero if this argument is a named parameter
4939 (otherwise it is an extra parameter matching an ellipsis).
4940 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4941 *PREGNO records the register number to use if scalar type.
4942 *PPADDING records the amount of padding needed in words. */
4945 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4946 tree type, int named, int incoming_p,
4947 int *pregno, int *ppadding)
4949 int regbase = (incoming_p
4950 ? SPARC_INCOMING_INT_ARG_FIRST
4951 : SPARC_OUTGOING_INT_ARG_FIRST);
4952 int slotno = cum->words;
4957 if (type != 0 && TREE_ADDRESSABLE (type))
4960 && type != 0 && mode == BLKmode
4961 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4967 /* MODE is VOIDmode when generating the actual call.
4971 case TImode : case CTImode :
4972 if (TARGET_ARCH64 && (slotno & 1) != 0)
4973 slotno++, *ppadding = 1;
4976 case QImode : case CQImode :
4977 case HImode : case CHImode :
4978 case SImode : case CSImode :
4979 case DImode : case CDImode :
4980 if (slotno >= SPARC_INT_ARG_MAX)
4982 regno = regbase + slotno;
4985 case TFmode : case TCmode :
4986 if (TARGET_ARCH64 && (slotno & 1) != 0)
4987 slotno++, *ppadding = 1;
4990 case SFmode : case SCmode :
4991 case DFmode : case DCmode :
4994 if (slotno >= SPARC_INT_ARG_MAX)
4996 regno = regbase + slotno;
5000 if (TARGET_FPU && named)
5002 if (slotno >= SPARC_FP_ARG_MAX)
5004 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5010 if (slotno >= SPARC_INT_ARG_MAX)
5012 regno = regbase + slotno;
5018 /* For sparc64, objects requiring 16 byte alignment get it. */
5021 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
5022 slotno++, *ppadding = 1;
5026 || (type && TREE_CODE (type) == UNION_TYPE))
5028 if (slotno >= SPARC_INT_ARG_MAX)
5030 regno = regbase + slotno;
5034 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5036 /* First see what kinds of registers we would need. */
5037 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5039 /* The ABI obviously doesn't specify how packed structures
5040 are passed. These are defined to be passed in int regs
5041 if possible, otherwise memory. */
5042 if (packed_p || !named)
5043 fpregs_p = 0, intregs_p = 1;
5045 /* If all arg slots are filled, then must pass on stack. */
5046 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5048 /* If there are only int args and all int arg slots are filled,
5049 then must pass on stack. */
5050 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5052 /* Note that even if all int arg slots are filled, fp members may
5053 still be passed in regs if such regs are available.
5054 *PREGNO isn't set because there may be more than one, it's up
5055 to the caller to compute them. */
5068 /* Handle recursive register counting for structure field layout. */
5070 struct function_arg_record_value_parms
5072 rtx ret; /* return expression being built. */
5073 int slotno; /* slot number of the argument. */
5074 int named; /* whether the argument is named. */
5075 int regbase; /* regno of the base register. */
5076 int stack; /* 1 if part of the argument is on the stack. */
5077 int intoffset; /* offset of the first pending integer field. */
5078 unsigned int nregs; /* number of words passed in registers. */
5081 static void function_arg_record_value_3
5082 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5083 static void function_arg_record_value_2
5084 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5085 static void function_arg_record_value_1
5086 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5087 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5088 static rtx function_arg_union_value (int, enum machine_mode, int, int);
5090 /* A subroutine of function_arg_record_value. Traverse the structure
5091 recursively and determine how many registers will be required. */
5094 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5095 struct function_arg_record_value_parms *parms,
5100 /* We need to compute how many registers are needed so we can
5101 allocate the PARALLEL but before we can do that we need to know
5102 whether there are any packed fields. The ABI obviously doesn't
5103 specify how structures are passed in this case, so they are
5104 defined to be passed in int regs if possible, otherwise memory,
5105 regardless of whether there are fp values present. */
5108 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5110 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5117 /* Compute how many registers we need. */
5118 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5120 if (TREE_CODE (field) == FIELD_DECL)
5122 HOST_WIDE_INT bitpos = startbitpos;
5124 if (DECL_SIZE (field) != 0
5125 && host_integerp (bit_position (field), 1))
5126 bitpos += int_bit_position (field);
5128 /* ??? FIXME: else assume zero offset. */
5130 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5131 function_arg_record_value_1 (TREE_TYPE (field),
5135 else if (FLOAT_TYPE_P (TREE_TYPE (field))
5140 if (parms->intoffset != -1)
5142 unsigned int startbit, endbit;
5143 int intslots, this_slotno;
5145 startbit = parms->intoffset & -BITS_PER_WORD;
5146 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5148 intslots = (endbit - startbit) / BITS_PER_WORD;
5149 this_slotno = parms->slotno + parms->intoffset
5152 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5154 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5155 /* We need to pass this field on the stack. */
5159 parms->nregs += intslots;
5160 parms->intoffset = -1;
5163 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5164 If it wasn't true we wouldn't be here. */
5166 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5171 if (parms->intoffset == -1)
5172 parms->intoffset = bitpos;
5178 /* A subroutine of function_arg_record_value. Assign the bits of the
5179 structure between parms->intoffset and bitpos to integer registers. */
5182 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5183 struct function_arg_record_value_parms *parms)
5185 enum machine_mode mode;
5187 unsigned int startbit, endbit;
5188 int this_slotno, intslots, intoffset;
5191 if (parms->intoffset == -1)
5194 intoffset = parms->intoffset;
5195 parms->intoffset = -1;
5197 startbit = intoffset & -BITS_PER_WORD;
5198 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5199 intslots = (endbit - startbit) / BITS_PER_WORD;
5200 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5202 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5206 /* If this is the trailing part of a word, only load that much into
5207 the register. Otherwise load the whole register. Note that in
5208 the latter case we may pick up unwanted bits. It's not a problem
5209 at the moment but may wish to revisit. */
5211 if (intoffset % BITS_PER_WORD != 0)
5212 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5217 intoffset /= BITS_PER_UNIT;
5220 regno = parms->regbase + this_slotno;
5221 reg = gen_rtx_REG (mode, regno);
5222 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5223 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5226 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5231 while (intslots > 0);
5234 /* A subroutine of function_arg_record_value. Traverse the structure
5235 recursively and assign bits to floating point registers. Track which
5236 bits in between need integer registers; invoke function_arg_record_value_3
5237 to make that happen. */
5240 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5241 struct function_arg_record_value_parms *parms,
5247 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5249 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5256 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5258 if (TREE_CODE (field) == FIELD_DECL)
5260 HOST_WIDE_INT bitpos = startbitpos;
5262 if (DECL_SIZE (field) != 0
5263 && host_integerp (bit_position (field), 1))
5264 bitpos += int_bit_position (field);
5266 /* ??? FIXME: else assume zero offset. */
5268 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5269 function_arg_record_value_2 (TREE_TYPE (field),
5273 else if (FLOAT_TYPE_P (TREE_TYPE (field))
5278 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5280 enum machine_mode mode = DECL_MODE (field);
5283 function_arg_record_value_3 (bitpos, parms);
5284 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
5285 + ((mode == SFmode || mode == SCmode)
5286 && (bitpos & 32) != 0);
5289 case SCmode: mode = SFmode; break;
5290 case DCmode: mode = DFmode; break;
5291 case TCmode: mode = TFmode; break;
5294 reg = gen_rtx_REG (mode, regno);
5295 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5296 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5297 GEN_INT (bitpos / BITS_PER_UNIT));
5299 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5301 regno += GET_MODE_SIZE (mode) / 4;
5302 reg = gen_rtx_REG (mode, regno);
5303 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5304 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5305 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5312 if (parms->intoffset == -1)
5313 parms->intoffset = bitpos;
5319 /* Used by function_arg and function_value to implement the complex
5320 conventions of the 64-bit ABI for passing and returning structures.
5321 Return an expression valid as a return value for the two macros
5322 FUNCTION_ARG and FUNCTION_VALUE.
5324 TYPE is the data type of the argument (as a tree).
5325 This is null for libcalls where that information may
5327 MODE is the argument's machine mode.
5328 SLOTNO is the index number of the argument's slot in the parameter array.
5329 NAMED is nonzero if this argument is a named parameter
5330 (otherwise it is an extra parameter matching an ellipsis).
5331 REGBASE is the regno of the base register for the parameter array. */
5334 function_arg_record_value (tree type, enum machine_mode mode,
5335 int slotno, int named, int regbase)
5337 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5338 struct function_arg_record_value_parms parms;
5341 parms.ret = NULL_RTX;
5342 parms.slotno = slotno;
5343 parms.named = named;
5344 parms.regbase = regbase;
5347 /* Compute how many registers we need. */
5349 parms.intoffset = 0;
5350 function_arg_record_value_1 (type, 0, &parms, false);
5352 /* Take into account pending integer fields. */
5353 if (parms.intoffset != -1)
5355 unsigned int startbit, endbit;
5356 int intslots, this_slotno;
5358 startbit = parms.intoffset & -BITS_PER_WORD;
5359 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5360 intslots = (endbit - startbit) / BITS_PER_WORD;
5361 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5363 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5365 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5366 /* We need to pass this field on the stack. */
5370 parms.nregs += intslots;
5372 nregs = parms.nregs;
5374 /* Allocate the vector and handle some annoying special cases. */
5377 /* ??? Empty structure has no value? Duh? */
5380 /* Though there's nothing really to store, return a word register
5381 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5382 leads to breakage due to the fact that there are zero bytes to
5384 return gen_rtx_REG (mode, regbase);
5388 /* ??? C++ has structures with no fields, and yet a size. Give up
5389 for now and pass everything back in integer registers. */
5390 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5392 if (nregs + slotno > SPARC_INT_ARG_MAX)
5393 nregs = SPARC_INT_ARG_MAX - slotno;
5398 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5400 /* If at least one field must be passed on the stack, generate
5401 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5402 also be passed on the stack. We can't do much better because the
5403 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5404 of structures for which the fields passed exclusively in registers
5405 are not at the beginning of the structure. */
5407 XVECEXP (parms.ret, 0, 0)
5408 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5410 /* Fill in the entries. */
5412 parms.intoffset = 0;
5413 function_arg_record_value_2 (type, 0, &parms, false);
5414 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5416 if (parms.nregs != nregs)
5422 /* Used by function_arg and function_value to implement the conventions
5423 of the 64-bit ABI for passing and returning unions.
5424 Return an expression valid as a return value for the two macros
5425 FUNCTION_ARG and FUNCTION_VALUE.
5427 SIZE is the size in bytes of the union.
5428 MODE is the argument's machine mode.
5429 REGNO is the hard register the union will be passed in. */
5432 function_arg_union_value (int size, enum machine_mode mode, int slotno,
5435 int nwords = ROUND_ADVANCE (size), i;
5438 /* See comment in previous function for empty structures. */
5440 return gen_rtx_REG (mode, regno);
5442 if (slotno == SPARC_INT_ARG_MAX - 1)
5445 /* Unions are passed left-justified. */
5446 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5448 for (i = 0; i < nwords; i++)
5449 XVECEXP (regs, 0, i)
5450 = gen_rtx_EXPR_LIST (VOIDmode,
5451 gen_rtx_REG (word_mode, regno + i),
5452 GEN_INT (UNITS_PER_WORD * i));
5457 /* Handle the FUNCTION_ARG macro.
5458 Determine where to put an argument to a function.
5459 Value is zero to push the argument on the stack,
5460 or a hard register in which to store the argument.
5462 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5463 the preceding args and about the function being called.
5464 MODE is the argument's machine mode.
5465 TYPE is the data type of the argument (as a tree).
5466 This is null for libcalls where that information may
5468 NAMED is nonzero if this argument is a named parameter
5469 (otherwise it is an extra parameter matching an ellipsis).
5470 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5473 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5474 tree type, int named, int incoming_p)
5476 int regbase = (incoming_p
5477 ? SPARC_INCOMING_INT_ARG_FIRST
5478 : SPARC_OUTGOING_INT_ARG_FIRST);
5479 int slotno, regno, padding;
5482 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5490 reg = gen_rtx_REG (mode, regno);
5494 if (type && TREE_CODE (type) == RECORD_TYPE)
5496 /* Structures up to 16 bytes in size are passed in arg slots on the
5497 stack and are promoted to registers where possible. */
5499 if (int_size_in_bytes (type) > 16)
5500 abort (); /* shouldn't get here */
5502 return function_arg_record_value (type, mode, slotno, named, regbase);
5504 else if (type && TREE_CODE (type) == UNION_TYPE)
5506 HOST_WIDE_INT size = int_size_in_bytes (type);
5509 abort (); /* shouldn't get here */
5511 return function_arg_union_value (size, mode, slotno, regno);
5513 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5514 but also have the slot allocated for them.
5515 If no prototype is in scope fp values in register slots get passed
5516 in two places, either fp regs and int regs or fp regs and memory. */
5517 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5518 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5519 && SPARC_FP_REG_P (regno))
5521 reg = gen_rtx_REG (mode, regno);
5522 if (cum->prototype_p || cum->libcall_p)
5524 /* "* 2" because fp reg numbers are recorded in 4 byte
5527 /* ??? This will cause the value to be passed in the fp reg and
5528 in the stack. When a prototype exists we want to pass the
5529 value in the reg but reserve space on the stack. That's an
5530 optimization, and is deferred [for a bit]. */
5531 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5532 return gen_rtx_PARALLEL (mode,
5534 gen_rtx_EXPR_LIST (VOIDmode,
5535 NULL_RTX, const0_rtx),
5536 gen_rtx_EXPR_LIST (VOIDmode,
5540 /* ??? It seems that passing back a register even when past
5541 the area declared by REG_PARM_STACK_SPACE will allocate
5542 space appropriately, and will not copy the data onto the
5543 stack, exactly as we desire.
5545 This is due to locate_and_pad_parm being called in
5546 expand_call whenever reg_parm_stack_space > 0, which
5547 while beneficial to our example here, would seem to be
5548 in error from what had been intended. Ho hum... -- r~ */
5556 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5560 /* On incoming, we don't need to know that the value
5561 is passed in %f0 and %i0, and it confuses other parts
5562 causing needless spillage even on the simplest cases. */
5566 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5567 + (regno - SPARC_FP_ARG_FIRST) / 2);
5569 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5570 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5572 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5576 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5577 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5578 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5584 /* Scalar or complex int. */
5585 reg = gen_rtx_REG (mode, regno);
5591 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5592 For an arg passed partly in registers and partly in memory,
5593 this is the number of registers used.
5594 For args passed entirely in registers or entirely in memory, zero.
5596 Any arg that starts in the first 6 regs but won't entirely fit in them
5597 needs partial registers on v8. On v9, structures with integer
5598 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5599 values that begin in the last fp reg [where "last fp reg" varies with the
5600 mode] will be split between that reg and memory. */
5603 function_arg_partial_nregs (const struct sparc_args *cum,
5604 enum machine_mode mode, tree type, int named)
5606 int slotno, regno, padding;
5608 /* We pass 0 for incoming_p here, it doesn't matter. */
5609 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5616 if ((slotno + (mode == BLKmode
5617 ? ROUND_ADVANCE (int_size_in_bytes (type))
5618 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5619 > NPARM_REGS (SImode))
5620 return NPARM_REGS (SImode) - slotno;
5625 if (type && AGGREGATE_TYPE_P (type))
5627 int size = int_size_in_bytes (type);
5628 int align = TYPE_ALIGN (type);
5631 slotno += slotno & 1;
5632 if (size > 8 && size <= 16
5633 && slotno == SPARC_INT_ARG_MAX - 1)
5636 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5637 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5638 && ! (TARGET_FPU && named)))
5640 /* The complex types are passed as packed types. */
5641 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
5644 if (GET_MODE_ALIGNMENT (mode) == 128)
5646 slotno += slotno & 1;
5648 /* ??? The mode needs 3 slots? */
5649 if (slotno == SPARC_INT_ARG_MAX - 2)
5654 if (slotno == SPARC_INT_ARG_MAX - 1)
5658 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5660 if (GET_MODE_ALIGNMENT (mode) == 128)
5661 slotno += slotno & 1;
5662 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5670 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5671 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5672 quad-precision floats by invisible reference.
5673 v9: Aggregates greater than 16 bytes are passed by reference.
5674 For Pascal, also pass arrays by reference. */
5677 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5678 enum machine_mode mode, tree type,
5679 int named ATTRIBUTE_UNUSED)
5683 return ((type && AGGREGATE_TYPE_P (type))
5685 || GET_MODE_SIZE (mode) > 8);
5689 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5690 /* Consider complex values as aggregates, so care
5691 for CTImode and TCmode. */
5692 || GET_MODE_SIZE (mode) > 16
5694 && AGGREGATE_TYPE_P (type)
5695 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5699 /* Handle the FUNCTION_ARG_ADVANCE macro.
5700 Update the data in CUM to advance over an argument
5701 of mode MODE and data type TYPE.
5702 TYPE is null for libcalls where that information may not be available. */
5705 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5706 tree type, int named)
5708 int slotno, regno, padding;
5710 /* We pass 0 for incoming_p here, it doesn't matter. */
5711 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5713 /* If register required leading padding, add it. */
5715 cum->words += padding;
5719 cum->words += (mode != BLKmode
5720 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5721 : ROUND_ADVANCE (int_size_in_bytes (type)));
5725 if (type && AGGREGATE_TYPE_P (type))
5727 int size = int_size_in_bytes (type);
5731 else if (size <= 16)
5733 else /* passed by reference */
5738 cum->words += (mode != BLKmode
5739 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5740 : ROUND_ADVANCE (int_size_in_bytes (type)));
5745 /* Handle the FUNCTION_ARG_PADDING macro.
5746 For the 64 bit ABI structs are always stored left shifted in their
5750 function_arg_padding (enum machine_mode mode, tree type)
5752 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5755 /* Fall back to the default. */
5756 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5759 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5760 For v9, function return values are subject to the same rules as arguments,
5761 except that up to 32-bytes may be returned in registers. */
5764 function_value (tree type, enum machine_mode mode, int incoming_p)
5768 if (TARGET_ARCH64 && type)
5770 int regbase = (incoming_p
5771 ? SPARC_OUTGOING_INT_ARG_FIRST
5772 : SPARC_INCOMING_INT_ARG_FIRST);
5774 if (TREE_CODE (type) == RECORD_TYPE)
5776 /* Structures up to 32 bytes in size are passed in registers,
5777 promoted to fp registers where possible. */
5779 if (int_size_in_bytes (type) > 32)
5780 abort (); /* shouldn't get here */
5782 return function_arg_record_value (type, mode, 0, 1, regbase);
5784 else if (TREE_CODE (type) == UNION_TYPE)
5786 HOST_WIDE_INT size = int_size_in_bytes (type);
5789 abort (); /* shouldn't get here */
5791 return function_arg_union_value (size, mode, 0, regbase);
5793 else if (AGGREGATE_TYPE_P (type))
5795 /* All other aggregate types are passed in an integer register
5796 in a mode corresponding to the size of the type. */
5797 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5802 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5804 /* ??? We probably should have made the same ABI change in
5805 3.4.0 as the one we made for unions. The latter was
5806 required by the SCD though, while the former is not
5807 specified, so we favored compatibility and efficiency.
5809 Now we're stuck for aggregates larger than 16 bytes,
5810 because OImode vanished in the meantime. Let's not
5811 try to be unduly clever, and simply follow the ABI
5812 for unions in that case. */
5813 if (mode == BLKmode)
5814 return function_arg_union_value (bytes, mode, 0, regbase);
5816 else if (GET_MODE_CLASS (mode) == MODE_INT
5817 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5822 regno = BASE_RETURN_VALUE_REG (mode);
5824 regno = BASE_OUTGOING_VALUE_REG (mode);
5826 return gen_rtx_REG (mode, regno);
5829 /* Do what is necessary for `va_start'. We look at the current function
5830 to determine if stdarg or varargs is used and return the address of
5831 the first unnamed parameter. */
5834 sparc_builtin_saveregs (void)
5836 int first_reg = current_function_args_info.words;
5840 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5841 emit_move_insn (gen_rtx_MEM (word_mode,
5842 gen_rtx_PLUS (Pmode,
5844 GEN_INT (FIRST_PARM_OFFSET (0)
5847 gen_rtx_REG (word_mode,
5848 BASE_INCOMING_ARG_REG (word_mode) + regno));
5850 address = gen_rtx_PLUS (Pmode,
5852 GEN_INT (FIRST_PARM_OFFSET (0)
5853 + UNITS_PER_WORD * first_reg));
5858 /* Implement `va_start' for varargs and stdarg. */
5861 sparc_va_start (tree valist, rtx nextarg)
5863 nextarg = expand_builtin_saveregs ();
5864 std_expand_builtin_va_start (valist, nextarg);
5867 /* Implement `va_arg'. */
5870 sparc_va_arg (tree valist, tree type)
5872 HOST_WIDE_INT size, rsize, align;
5877 /* Round up sizeof(type) to a word. */
5878 size = int_size_in_bytes (type);
5879 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5884 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5885 align = 2 * UNITS_PER_WORD;
5887 /* Consider complex values as aggregates, so care
5888 for CTImode and TCmode. */
5889 if ((unsigned HOST_WIDE_INT) size > 16)
5892 size = rsize = UNITS_PER_WORD;
5895 else if (AGGREGATE_TYPE_P (type))
5897 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5898 are given whole slots as needed. */
5900 size = rsize = UNITS_PER_WORD;
5907 if (AGGREGATE_TYPE_P (type)
5908 || TYPE_MODE (type) == SCmode
5909 || GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5912 size = rsize = UNITS_PER_WORD;
5919 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5920 build_int_2 (align - 1, 0)));
5921 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5922 build_int_2 (-align, -1)));
5925 addr = incr = save_expr (incr);
5926 if (BYTES_BIG_ENDIAN && size < rsize)
5928 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5929 build_int_2 (rsize - size, 0)));
5931 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5932 build_int_2 (rsize, 0)));
5934 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5935 TREE_SIDE_EFFECTS (incr) = 1;
5936 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5938 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5940 /* If the address isn't aligned properly for the type,
5941 we may need to copy to a temporary.
5942 FIXME: This is inefficient. Usually we can do this
5945 && TYPE_ALIGN (type) > BITS_PER_WORD
5948 /* FIXME: We really need to specify that the temporary is live
5949 for the whole function because expand_builtin_va_arg wants
5950 the alias set to be get_varargs_alias_set (), but in this
5951 case the alias set is that for TYPE and if the memory gets
5952 reused it will be reused with alias set TYPE. */
5953 rtx tmp = assign_temp (type, 0, 1, 0);
5956 addr_rtx = force_reg (Pmode, addr_rtx);
5957 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5958 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5959 set_mem_align (addr_rtx, BITS_PER_WORD);
5960 tmp = shallow_copy_rtx (tmp);
5961 PUT_MODE (tmp, BLKmode);
5962 set_mem_alias_set (tmp, 0);
5964 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5966 if (dest_addr != NULL_RTX)
5967 addr_rtx = dest_addr;
5969 addr_rtx = XCEXP (tmp, 0, MEM);
5974 addr_rtx = force_reg (Pmode, addr_rtx);
5975 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5976 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5982 /* Return the string to output an unconditional branch to LABEL, which is
5983 the operand number of the label.
5985 DEST is the destination insn (i.e. the label), INSN is the source. */
5988 output_ubranch (rtx dest, int label, rtx insn)
5990 static char string[64];
5994 /* TurboSPARC is reported to have problems with
5997 i.e. an empty loop with the annul bit set. The workaround is to use
6001 if (! TARGET_V9 && flag_delayed_branch
6002 && (INSN_ADDRESSES (INSN_UID (dest))
6003 == INSN_ADDRESSES (INSN_UID (insn))))
6005 strcpy (string, "b\t");
6010 bool v9_form = false;
6012 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6014 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6015 - INSN_ADDRESSES (INSN_UID (insn)));
6016 /* Leave some instructions for "slop". */
6017 if (delta >= -260000 && delta < 260000)
6022 strcpy (string, "ba%*,pt\t%%xcc, ");
6024 strcpy (string, "b%*\t");
6027 p = strchr (string, '\0');
6041 /* Return the string to output a conditional branch to LABEL, which is
6042 the operand number of the label. OP is the conditional expression.
6043 XEXP (OP, 0) is assumed to be a condition code register (integer or
6044 floating point) and its mode specifies what kind of comparison we made.
6046 DEST is the destination insn (i.e. the label), INSN is the source.
6048 REVERSED is nonzero if we should reverse the sense of the comparison.
6050 ANNUL is nonzero if we should generate an annulling branch.
6052 NOOP is nonzero if we have to follow this branch by a noop. */
6055 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6058 static char string[50];
6059 enum rtx_code code = GET_CODE (op);
6060 rtx cc_reg = XEXP (op, 0);
6061 enum machine_mode mode = GET_MODE (cc_reg);
6062 const char *labelno, *branch;
6063 int spaces = 8, far;
6066 /* v9 branches are limited to +-1MB. If it is too far away,
6079 fbne,a,pn %fcc2, .LC29
6087 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6090 /* Reversal of FP compares takes care -- an ordered compare
6091 becomes an unordered compare and vice versa. */
6092 if (mode == CCFPmode || mode == CCFPEmode)
6093 code = reverse_condition_maybe_unordered (code);
6095 code = reverse_condition (code);
6098 /* Start by writing the branch condition. */
6099 if (mode == CCFPmode || mode == CCFPEmode)
6150 /* ??? !v9: FP branches cannot be preceded by another floating point
6151 insn. Because there is currently no concept of pre-delay slots,
6152 we can fix this only by always emitting a nop before a floating
6157 strcpy (string, "nop\n\t");
6158 strcat (string, branch);
6171 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6183 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6204 strcpy (string, branch);
6206 spaces -= strlen (branch);
6207 p = strchr (string, '\0');
6209 /* Now add the annulling, the label, and a possible noop. */
6222 if (! far && insn && INSN_ADDRESSES_SET_P ())
6224 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6225 - INSN_ADDRESSES (INSN_UID (insn)));
6226 /* Leave some instructions for "slop". */
6227 if (delta < -260000 || delta >= 260000)
6231 if (mode == CCFPmode || mode == CCFPEmode)
6233 static char v9_fcc_labelno[] = "%%fccX, ";
6234 /* Set the char indicating the number of the fcc reg to use. */
6235 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6236 labelno = v9_fcc_labelno;
6239 if (REGNO (cc_reg) == SPARC_FCC_REG)
6245 else if (mode == CCXmode || mode == CCX_NOOVmode)
6247 labelno = "%%xcc, ";
6253 labelno = "%%icc, ";
6258 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6261 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6274 strcpy (p, labelno);
6275 p = strchr (p, '\0');
6278 strcpy (p, ".+12\n\tnop\n\tb\t");
6285 /* Set the char indicating the number of the operand containing the
6290 strcpy (p, "\n\tnop");
6295 /* Emit a library call comparison between floating point X and Y.
6296 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6297 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6298 values as arguments instead of the TFmode registers themselves,
6299 that's why we cannot call emit_float_lib_cmp. */
6301 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6304 rtx slot0, slot1, result, tem, tem2;
6305 enum machine_mode mode;
6310 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6314 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6318 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6322 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6326 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6330 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6341 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6351 if (GET_CODE (x) != MEM)
6353 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6354 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6359 if (GET_CODE (y) != MEM)
6361 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6362 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6367 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6369 XEXP (slot0, 0), Pmode,
6370 XEXP (slot1, 0), Pmode);
6376 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6378 x, TFmode, y, TFmode);
6384 /* Immediately move the result of the libcall into a pseudo
6385 register so reload doesn't clobber the value if it needs
6386 the return register for a spill reg. */
6387 result = gen_reg_rtx (mode);
6388 emit_move_insn (result, hard_libcall_value (mode));
6393 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6397 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6402 emit_cmp_insn (result, const1_rtx,
6403 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6406 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6409 tem = gen_reg_rtx (mode);
6411 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6413 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6414 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6418 tem = gen_reg_rtx (mode);
6420 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6422 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6423 tem2 = gen_reg_rtx (mode);
6425 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6427 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6428 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6434 /* Generate an unsigned DImode to FP conversion. This is the same code
6435 optabs would emit if we didn't have TFmode patterns. */
6438 sparc_emit_floatunsdi (rtx *operands)
6440 rtx neglab, donelab, i0, i1, f0, in, out;
6441 enum machine_mode mode;
6444 in = force_reg (DImode, operands[1]);
6445 mode = GET_MODE (out);
6446 neglab = gen_label_rtx ();
6447 donelab = gen_label_rtx ();
6448 i0 = gen_reg_rtx (DImode);
6449 i1 = gen_reg_rtx (DImode);
6450 f0 = gen_reg_rtx (mode);
6452 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6454 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6455 emit_jump_insn (gen_jump (donelab));
6458 emit_label (neglab);
6460 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6461 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6462 emit_insn (gen_iordi3 (i0, i0, i1));
6463 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6464 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6466 emit_label (donelab);
6469 /* Return the string to output a conditional branch to LABEL, testing
6470 register REG. LABEL is the operand number of the label; REG is the
6471 operand number of the reg. OP is the conditional expression. The mode
6472 of REG says what kind of comparison we made.
6474 DEST is the destination insn (i.e. the label), INSN is the source.
6476 REVERSED is nonzero if we should reverse the sense of the comparison.
6478 ANNUL is nonzero if we should generate an annulling branch.
6480 NOOP is nonzero if we have to follow this branch by a noop. */
6483 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6484 int annul, int noop, rtx insn)
6486 static char string[50];
6487 enum rtx_code code = GET_CODE (op);
6488 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6493 /* branch on register are limited to +-128KB. If it is too far away,
6506 brgez,a,pn %o1, .LC29
6512 ba,pt %xcc, .LC29 */
6514 far = get_attr_length (insn) >= 3;
6516 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6518 code = reverse_condition (code);
6520 /* Only 64 bit versions of these instructions exist. */
6524 /* Start by writing the branch condition. */
6529 strcpy (string, "brnz");
6533 strcpy (string, "brz");
6537 strcpy (string, "brgez");
6541 strcpy (string, "brlz");
6545 strcpy (string, "brlez");
6549 strcpy (string, "brgz");
6556 p = strchr (string, '\0');
6558 /* Now add the annulling, reg, label, and nop. */
6565 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6568 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6573 *p = p < string + 8 ? '\t' : ' ';
6581 int veryfar = 1, delta;
6583 if (INSN_ADDRESSES_SET_P ())
6585 delta = (INSN_ADDRESSES (INSN_UID (dest))
6586 - INSN_ADDRESSES (INSN_UID (insn)));
6587 /* Leave some instructions for "slop". */
6588 if (delta >= -260000 && delta < 260000)
6592 strcpy (p, ".+12\n\tnop\n\t");
6603 strcpy (p, "ba,pt\t%%xcc, ");
6613 strcpy (p, "\n\tnop");
6618 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6619 Such instructions cannot be used in the delay slot of return insn on v9.
6620 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6624 epilogue_renumber (register rtx *where, int test)
6626 register const char *fmt;
6628 register enum rtx_code code;
6633 code = GET_CODE (*where);
6638 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6640 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6641 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6649 /* Do not replace the frame pointer with the stack pointer because
6650 it can cause the delayed instruction to load below the stack.
6651 This occurs when instructions like:
6653 (set (reg/i:SI 24 %i0)
6654 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6655 (const_int -20 [0xffffffec])) 0))
6657 are in the return delayed slot. */
6659 if (GET_CODE (XEXP (*where, 0)) == REG
6660 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6661 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6662 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6667 if (SPARC_STACK_BIAS
6668 && GET_CODE (XEXP (*where, 0)) == REG
6669 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6677 fmt = GET_RTX_FORMAT (code);
6679 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6684 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6685 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6688 else if (fmt[i] == 'e'
6689 && epilogue_renumber (&(XEXP (*where, i)), test))
6695 /* Leaf functions and non-leaf functions have different needs. */
6698 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6701 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6703 static const int *const reg_alloc_orders[] = {
6704 reg_leaf_alloc_order,
6705 reg_nonleaf_alloc_order};
6708 order_regs_for_local_alloc (void)
6710 static int last_order_nonleaf = 1;
6712 if (regs_ever_live[15] != last_order_nonleaf)
6714 last_order_nonleaf = !last_order_nonleaf;
6715 memcpy ((char *) reg_alloc_order,
6716 (const char *) reg_alloc_orders[last_order_nonleaf],
6717 FIRST_PSEUDO_REGISTER * sizeof (int));
6721 /* Return 1 if REG and MEM are legitimate enough to allow the various
6722 mem<-->reg splits to be run. */
6725 sparc_splitdi_legitimate (rtx reg, rtx mem)
6727 /* Punt if we are here by mistake. */
6728 if (! reload_completed)
6731 /* We must have an offsettable memory reference. */
6732 if (! offsettable_memref_p (mem))
6735 /* If we have legitimate args for ldd/std, we do not want
6736 the split to happen. */
6737 if ((REGNO (reg) % 2) == 0
6738 && mem_min_alignment (mem, 8))
6745 /* Return 1 if x and y are some kind of REG and they refer to
6746 different hard registers. This test is guaranteed to be
6747 run after reload. */
6750 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6752 if (GET_CODE (x) != REG)
6754 if (GET_CODE (y) != REG)
6756 if (REGNO (x) == REGNO (y))
6761 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6762 This makes them candidates for using ldd and std insns.
6764 Note reg1 and reg2 *must* be hard registers. */
6767 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6769 /* We might have been passed a SUBREG. */
6770 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6773 if (REGNO (reg1) % 2 != 0)
6776 /* Integer ldd is deprecated in SPARC V9 */
6777 if (TARGET_V9 && REGNO (reg1) < 32)
6780 return (REGNO (reg1) == REGNO (reg2) - 1);
6783 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6786 This can only happen when addr1 and addr2, the addresses in mem1
6787 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6788 addr1 must also be aligned on a 64-bit boundary.
6790 Also iff dependent_reg_rtx is not null it should not be used to
6791 compute the address for mem1, i.e. we cannot optimize a sequence
6803 But, note that the transformation from:
6808 is perfectly fine. Thus, the peephole2 patterns always pass us
6809 the destination register of the first load, never the second one.
6811 For stores we don't have a similar problem, so dependent_reg_rtx is
6815 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6819 HOST_WIDE_INT offset1;
6821 /* The mems cannot be volatile. */
6822 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6825 /* MEM1 should be aligned on a 64-bit boundary. */
6826 if (MEM_ALIGN (mem1) < 64)
6829 addr1 = XEXP (mem1, 0);
6830 addr2 = XEXP (mem2, 0);
6832 /* Extract a register number and offset (if used) from the first addr. */
6833 if (GET_CODE (addr1) == PLUS)
6835 /* If not a REG, return zero. */
6836 if (GET_CODE (XEXP (addr1, 0)) != REG)
6840 reg1 = REGNO (XEXP (addr1, 0));
6841 /* The offset must be constant! */
6842 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6844 offset1 = INTVAL (XEXP (addr1, 1));
6847 else if (GET_CODE (addr1) != REG)
6851 reg1 = REGNO (addr1);
6852 /* This was a simple (mem (reg)) expression. Offset is 0. */
6856 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6857 if (GET_CODE (addr2) != PLUS)
6860 if (GET_CODE (XEXP (addr2, 0)) != REG
6861 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6864 if (reg1 != REGNO (XEXP (addr2, 0)))
6867 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6870 /* The first offset must be evenly divisible by 8 to ensure the
6871 address is 64 bit aligned. */
6872 if (offset1 % 8 != 0)
6875 /* The offset for the second addr must be 4 more than the first addr. */
6876 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6879 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6884 /* Return 1 if reg is a pseudo, or is the first register in
6885 a hard register pair. This makes it a candidate for use in
6886 ldd and std insns. */
6889 register_ok_for_ldd (rtx reg)
6891 /* We might have been passed a SUBREG. */
6892 if (GET_CODE (reg) != REG)
6895 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6896 return (REGNO (reg) % 2 == 0);
6901 /* Print operand X (an rtx) in assembler syntax to file FILE.
6902 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6903 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6906 print_operand (FILE *file, rtx x, int code)
6911 /* Output a 'nop' if there's nothing for the delay slot. */
6912 if (dbr_sequence_length () == 0)
6913 fputs ("\n\t nop", file);
6916 /* Output an annul flag if there's nothing for the delay slot and we
6917 are optimizing. This is always used with '(' below. */
6918 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6919 this is a dbx bug. So, we only do this when optimizing. */
6920 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6921 Always emit a nop in case the next instruction is a branch. */
6922 if (dbr_sequence_length () == 0
6923 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6927 /* Output a 'nop' if there's nothing for the delay slot and we are
6928 not optimizing. This is always used with '*' above. */
6929 if (dbr_sequence_length () == 0
6930 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6931 fputs ("\n\t nop", file);
6934 /* Output the Embedded Medium/Anywhere code model base register. */
6935 fputs (EMBMEDANY_BASE_REG, file);
6938 /* Print out what we are using as the frame pointer. This might
6939 be %fp, or might be %sp+offset. */
6940 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6941 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset);
6944 /* Print some local dynamic TLS name. */
6945 assemble_name (file, get_some_local_dynamic_name ());
6948 /* Adjust the operand to take into account a RESTORE operation. */
6949 if (GET_CODE (x) == CONST_INT)
6951 else if (GET_CODE (x) != REG)
6952 output_operand_lossage ("invalid %%Y operand");
6953 else if (REGNO (x) < 8)
6954 fputs (reg_names[REGNO (x)], file);
6955 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6956 fputs (reg_names[REGNO (x)-16], file);
6958 output_operand_lossage ("invalid %%Y operand");
6961 /* Print out the low order register name of a register pair. */
6962 if (WORDS_BIG_ENDIAN)
6963 fputs (reg_names[REGNO (x)+1], file);
6965 fputs (reg_names[REGNO (x)], file);
6968 /* Print out the high order register name of a register pair. */
6969 if (WORDS_BIG_ENDIAN)
6970 fputs (reg_names[REGNO (x)], file);
6972 fputs (reg_names[REGNO (x)+1], file);
6975 /* Print out the second register name of a register pair or quad.
6976 I.e., R (%o0) => %o1. */
6977 fputs (reg_names[REGNO (x)+1], file);
6980 /* Print out the third register name of a register quad.
6981 I.e., S (%o0) => %o2. */
6982 fputs (reg_names[REGNO (x)+2], file);
6985 /* Print out the fourth register name of a register quad.
6986 I.e., T (%o0) => %o3. */
6987 fputs (reg_names[REGNO (x)+3], file);
6990 /* Print a condition code register. */
6991 if (REGNO (x) == SPARC_ICC_REG)
6993 /* We don't handle CC[X]_NOOVmode because they're not supposed
6995 if (GET_MODE (x) == CCmode)
6996 fputs ("%icc", file);
6997 else if (GET_MODE (x) == CCXmode)
6998 fputs ("%xcc", file);
7003 /* %fccN register */
7004 fputs (reg_names[REGNO (x)], file);
7007 /* Print the operand's address only. */
7008 output_address (XEXP (x, 0));
7011 /* In this case we need a register. Use %g0 if the
7012 operand is const0_rtx. */
7014 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7016 fputs ("%g0", file);
7023 switch (GET_CODE (x))
7025 case IOR: fputs ("or", file); break;
7026 case AND: fputs ("and", file); break;
7027 case XOR: fputs ("xor", file); break;
7028 default: output_operand_lossage ("invalid %%A operand");
7033 switch (GET_CODE (x))
7035 case IOR: fputs ("orn", file); break;
7036 case AND: fputs ("andn", file); break;
7037 case XOR: fputs ("xnor", file); break;
7038 default: output_operand_lossage ("invalid %%B operand");
7042 /* These are used by the conditional move instructions. */
7046 enum rtx_code rc = GET_CODE (x);
7050 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7051 if (mode == CCFPmode || mode == CCFPEmode)
7052 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7054 rc = reverse_condition (GET_CODE (x));
7058 case NE: fputs ("ne", file); break;
7059 case EQ: fputs ("e", file); break;
7060 case GE: fputs ("ge", file); break;
7061 case GT: fputs ("g", file); break;
7062 case LE: fputs ("le", file); break;
7063 case LT: fputs ("l", file); break;
7064 case GEU: fputs ("geu", file); break;
7065 case GTU: fputs ("gu", file); break;
7066 case LEU: fputs ("leu", file); break;
7067 case LTU: fputs ("lu", file); break;
7068 case LTGT: fputs ("lg", file); break;
7069 case UNORDERED: fputs ("u", file); break;
7070 case ORDERED: fputs ("o", file); break;
7071 case UNLT: fputs ("ul", file); break;
7072 case UNLE: fputs ("ule", file); break;
7073 case UNGT: fputs ("ug", file); break;
7074 case UNGE: fputs ("uge", file); break;
7075 case UNEQ: fputs ("ue", file); break;
7076 default: output_operand_lossage (code == 'c'
7077 ? "invalid %%c operand"
7078 : "invalid %%C operand");
7083 /* These are used by the movr instruction pattern. */
7087 enum rtx_code rc = (code == 'd'
7088 ? reverse_condition (GET_CODE (x))
7092 case NE: fputs ("ne", file); break;
7093 case EQ: fputs ("e", file); break;
7094 case GE: fputs ("gez", file); break;
7095 case LT: fputs ("lz", file); break;
7096 case LE: fputs ("lez", file); break;
7097 case GT: fputs ("gz", file); break;
7098 default: output_operand_lossage (code == 'd'
7099 ? "invalid %%d operand"
7100 : "invalid %%D operand");
7107 /* Print a sign-extended character. */
7108 int i = trunc_int_for_mode (INTVAL (x), QImode);
7109 fprintf (file, "%d", i);
7114 /* Operand must be a MEM; write its address. */
7115 if (GET_CODE (x) != MEM)
7116 output_operand_lossage ("invalid %%f operand");
7117 output_address (XEXP (x, 0));
7122 /* Print a sign-extended 32-bit value. */
7124 if (GET_CODE(x) == CONST_INT)
7126 else if (GET_CODE(x) == CONST_DOUBLE)
7127 i = CONST_DOUBLE_LOW (x);
7130 output_operand_lossage ("invalid %%s operand");
7133 i = trunc_int_for_mode (i, SImode);
7134 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7139 /* Do nothing special. */
7143 /* Undocumented flag. */
7144 output_operand_lossage ("invalid operand output code");
7147 if (GET_CODE (x) == REG)
7148 fputs (reg_names[REGNO (x)], file);
7149 else if (GET_CODE (x) == MEM)
7152 /* Poor Sun assembler doesn't understand absolute addressing. */
7153 if (CONSTANT_P (XEXP (x, 0)))
7154 fputs ("%g0+", file);
7155 output_address (XEXP (x, 0));
7158 else if (GET_CODE (x) == HIGH)
7160 fputs ("%hi(", file);
7161 output_addr_const (file, XEXP (x, 0));
7164 else if (GET_CODE (x) == LO_SUM)
7166 print_operand (file, XEXP (x, 0), 0);
7167 if (TARGET_CM_MEDMID)
7168 fputs ("+%l44(", file);
7170 fputs ("+%lo(", file);
7171 output_addr_const (file, XEXP (x, 1));
7174 else if (GET_CODE (x) == CONST_DOUBLE
7175 && (GET_MODE (x) == VOIDmode
7176 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7178 if (CONST_DOUBLE_HIGH (x) == 0)
7179 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7180 else if (CONST_DOUBLE_HIGH (x) == -1
7181 && CONST_DOUBLE_LOW (x) < 0)
7182 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7184 output_operand_lossage ("long long constant not a valid immediate operand");
7186 else if (GET_CODE (x) == CONST_DOUBLE)
7187 output_operand_lossage ("floating point constant not a valid immediate operand");
7188 else { output_addr_const (file, x); }
7191 /* Target hook for assembling integer objects. The sparc version has
7192 special handling for aligned DI-mode objects. */
7195 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7197 /* ??? We only output .xword's for symbols and only then in environments
7198 where the assembler can handle them. */
7199 if (aligned_p && size == 8
7200 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7204 assemble_integer_with_op ("\t.xword\t", x);
7209 assemble_aligned_integer (4, const0_rtx);
7210 assemble_aligned_integer (4, x);
7214 return default_assemble_integer (x, size, aligned_p);
7217 /* Return the value of a code used in the .proc pseudo-op that says
7218 what kind of result this function returns. For non-C types, we pick
7219 the closest C type. */
7221 #ifndef SHORT_TYPE_SIZE
7222 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7225 #ifndef INT_TYPE_SIZE
7226 #define INT_TYPE_SIZE BITS_PER_WORD
7229 #ifndef LONG_TYPE_SIZE
7230 #define LONG_TYPE_SIZE BITS_PER_WORD
7233 #ifndef LONG_LONG_TYPE_SIZE
7234 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7237 #ifndef FLOAT_TYPE_SIZE
7238 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7241 #ifndef DOUBLE_TYPE_SIZE
7242 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7245 #ifndef LONG_DOUBLE_TYPE_SIZE
7246 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7250 sparc_type_code (register tree type)
7252 register unsigned long qualifiers = 0;
7253 register unsigned shift;
7255 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7256 setting more, since some assemblers will give an error for this. Also,
7257 we must be careful to avoid shifts of 32 bits or more to avoid getting
7258 unpredictable results. */
7260 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7262 switch (TREE_CODE (type))
7268 qualifiers |= (3 << shift);
7273 qualifiers |= (2 << shift);
7277 case REFERENCE_TYPE:
7279 qualifiers |= (1 << shift);
7283 return (qualifiers | 8);
7286 case QUAL_UNION_TYPE:
7287 return (qualifiers | 9);
7290 return (qualifiers | 10);
7293 return (qualifiers | 16);
7296 /* If this is a range type, consider it to be the underlying
7298 if (TREE_TYPE (type) != 0)
7301 /* Carefully distinguish all the standard types of C,
7302 without messing up if the language is not C. We do this by
7303 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7304 look at both the names and the above fields, but that's redundant.
7305 Any type whose size is between two C types will be considered
7306 to be the wider of the two types. Also, we do not have a
7307 special code to use for "long long", so anything wider than
7308 long is treated the same. Note that we can't distinguish
7309 between "int" and "long" in this code if they are the same
7310 size, but that's fine, since neither can the assembler. */
7312 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7313 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7315 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7316 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7318 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7319 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7322 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7325 /* If this is a range type, consider it to be the underlying
7327 if (TREE_TYPE (type) != 0)
7330 /* Carefully distinguish all the standard types of C,
7331 without messing up if the language is not C. */
7333 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7334 return (qualifiers | 6);
7337 return (qualifiers | 7);
7339 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7340 /* ??? We need to distinguish between double and float complex types,
7341 but I don't know how yet because I can't reach this code from
7342 existing front-ends. */
7343 return (qualifiers | 7); /* Who knows? */
7345 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7346 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7347 case FILE_TYPE: /* GNU Pascal FILE type. */
7348 case SET_TYPE: /* GNU Pascal SET type. */
7349 case LANG_TYPE: /* ? */
7353 abort (); /* Not a type! */
7360 /* Nested function support. */
7362 /* Emit RTL insns to initialize the variable parts of a trampoline.
7363 FNADDR is an RTX for the address of the function's pure code.
7364 CXT is an RTX for the static chain value for the function.
7366 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7367 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7368 (to store insns). This is a bit excessive. Perhaps a different
7369 mechanism would be better here.
7371 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7374 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7376 /* SPARC 32-bit trampoline:
7379 sethi %hi(static), %g2
7381 or %g2, %lo(static), %g2
7383 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7384 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7388 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7389 expand_binop (SImode, ior_optab,
7390 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7391 size_int (10), 0, 1),
7392 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7393 NULL_RTX, 1, OPTAB_DIRECT));
7396 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7397 expand_binop (SImode, ior_optab,
7398 expand_shift (RSHIFT_EXPR, SImode, cxt,
7399 size_int (10), 0, 1),
7400 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7401 NULL_RTX, 1, OPTAB_DIRECT));
7404 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7405 expand_binop (SImode, ior_optab,
7406 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7407 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7408 NULL_RTX, 1, OPTAB_DIRECT));
7411 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7412 expand_binop (SImode, ior_optab,
7413 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7414 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7415 NULL_RTX, 1, OPTAB_DIRECT));
7417 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7418 aligned on a 16 byte boundary so one flush clears it all. */
7419 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7420 if (sparc_cpu != PROCESSOR_ULTRASPARC
7421 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7422 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7423 plus_constant (tramp, 8)))));
7425 /* Call __enable_execute_stack after writing onto the stack to make sure
7426 the stack address is accessible. */
7427 #ifdef ENABLE_EXECUTE_STACK
7428 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7429 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7434 /* The 64-bit version is simpler because it makes more sense to load the
7435 values as "immediate" data out of the trampoline. It's also easier since
7436 we can read the PC without clobbering a register. */
7439 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7441 /* SPARC 64-bit trampoline:
7450 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7451 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7452 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7453 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7454 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7455 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7456 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7457 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7458 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7459 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7460 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7462 if (sparc_cpu != PROCESSOR_ULTRASPARC
7463 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7464 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7466 /* Call __enable_execute_stack after writing onto the stack to make sure
7467 the stack address is accessible. */
7468 #ifdef ENABLE_EXECUTE_STACK
7469 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7470 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7474 /* Subroutines to support a flat (single) register window calling
7477 /* Single-register window sparc stack frames look like:
7479 Before call After call
7480 +-----------------------+ +-----------------------+
7482 mem | caller's temps. | | caller's temps. |
7484 +-----------------------+ +-----------------------+
7486 | arguments on stack. | | arguments on stack. |
7488 +-----------------------+FP+92->+-----------------------+
7489 | 6 words to save | | 6 words to save |
7490 | arguments passed | | arguments passed |
7491 | in registers, even | | in registers, even |
7492 | if not passed. | | if not passed. |
7493 SP+68->+-----------------------+FP+68->+-----------------------+
7494 | 1 word struct addr | | 1 word struct addr |
7495 +-----------------------+FP+64->+-----------------------+
7497 | 16 word reg save area | | 16 word reg save area |
7499 SP->+-----------------------+ FP->+-----------------------+
7501 | fp/alu reg moves |
7502 FP-16->+-----------------------+
7506 +-----------------------+
7508 | fp register save |
7510 +-----------------------+
7512 | gp register save |
7514 +-----------------------+
7516 | alloca allocations |
7518 +-----------------------+
7520 | arguments on stack |
7522 SP+92->+-----------------------+
7524 | arguments passed |
7525 | in registers, even |
7526 low | if not passed. |
7527 memory SP+68->+-----------------------+
7528 | 1 word struct addr |
7529 SP+64->+-----------------------+
7531 I 16 word reg save area |
7533 SP->+-----------------------+ */
7535 /* Structure to be filled in by sparc_flat_compute_frame_size with register
7536 save masks, and offsets for the current function. */
7538 struct sparc_frame_info
7540 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7541 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7542 int args_size; /* # bytes that outgoing arguments take up. */
7543 int extra_size; /* # bytes of extra gunk. */
7544 int gp_reg_size; /* # bytes needed to store gp regs. */
7545 int fp_reg_size; /* # bytes needed to store fp regs. */
7546 unsigned long gmask; /* Mask of saved gp registers. */
7547 unsigned long fmask; /* Mask of saved fp registers. */
7548 int reg_offset; /* Offset from new sp to store regs. */
7549 int initialized; /* Nonzero if frame size already calculated. */
7552 /* Current frame information calculated by sparc_flat_compute_frame_size. */
7553 struct sparc_frame_info current_frame_info;
7555 /* Zero structure to initialize current_frame_info. */
7556 struct sparc_frame_info zero_frame_info;
7558 #define RETURN_ADDR_REGNUM 15
7559 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
7560 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
7562 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
7565 sparc_flat_must_save_register_p (int regno)
7567 /* General case: call-saved registers live at some point. */
7568 if (!call_used_regs[regno] && regs_ever_live[regno])
7571 /* Frame pointer register (%i7) if needed. */
7572 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7575 /* PIC register (%l7) if needed. */
7576 if (regno == (int) PIC_OFFSET_TABLE_REGNUM
7577 && flag_pic && current_function_uses_pic_offset_table)
7580 /* Return address register (%o7) if needed. */
7581 if (regno == RETURN_ADDR_REGNUM
7582 && (regs_ever_live[RETURN_ADDR_REGNUM]
7583 /* When the PIC offset table is used, the PIC register
7584 is set by using a bare call that clobbers %o7. */
7585 || (flag_pic && current_function_uses_pic_offset_table)))
7591 /* Return the bytes needed to compute the frame pointer from the current
7595 sparc_flat_compute_frame_size (HOST_WIDE_INT size)
7596 /* # of var. bytes allocated. */
7599 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7600 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7601 int args_size; /* # bytes that outgoing arguments take up. */
7602 int extra_size; /* # extra bytes. */
7603 int gp_reg_size; /* # bytes needed to store gp regs. */
7604 int fp_reg_size; /* # bytes needed to store fp regs. */
7605 unsigned long gmask; /* Mask of saved gp registers. */
7606 unsigned long fmask; /* Mask of saved fp registers. */
7607 int reg_offset; /* Offset to register save area. */
7608 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7610 /* This is the size of the 16 word reg save area, 1 word struct addr
7611 area, and 4 word fp/alu register copy area. */
7612 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
7622 if (!leaf_function_p ())
7624 /* Also include the size needed for the 6 parameter registers. */
7625 args_size = current_function_outgoing_args_size + 24;
7627 total_size = var_size + args_size;
7629 /* Calculate space needed for gp registers. */
7630 for (regno = 1; regno <= 31; regno++)
7632 if (sparc_flat_must_save_register_p (regno))
7634 /* If we need to save two regs in a row, ensure there's room to bump
7635 up the address to align it to a doubleword boundary. */
7636 if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1))
7638 if (gp_reg_size % 8 != 0)
7640 gp_reg_size += 2 * UNITS_PER_WORD;
7641 gmask |= 3 << regno;
7647 gp_reg_size += UNITS_PER_WORD;
7648 gmask |= 1 << regno;
7653 /* Calculate space needed for fp registers. */
7654 for (regno = 32; regno <= 63; regno++)
7656 if (regs_ever_live[regno] && !call_used_regs[regno])
7658 fp_reg_size += UNITS_PER_WORD;
7659 fmask |= 1 << (regno - 32);
7666 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7667 /* Ensure save area is 8 byte aligned if we need it. */
7669 if (need_aligned_p && n != 0)
7671 total_size += 8 - n;
7672 reg_offset += 8 - n;
7674 total_size += gp_reg_size + fp_reg_size;
7677 /* If we must allocate a stack frame at all, we must also allocate
7678 room for register window spillage, so as to be binary compatible
7679 with libraries and operating systems that do not use -mflat. */
7681 total_size += extra_size;
7685 total_size = SPARC_STACK_ALIGN (total_size);
7687 /* Save other computed information. */
7688 current_frame_info.total_size = total_size;
7689 current_frame_info.var_size = var_size;
7690 current_frame_info.args_size = args_size;
7691 current_frame_info.extra_size = extra_size;
7692 current_frame_info.gp_reg_size = gp_reg_size;
7693 current_frame_info.fp_reg_size = fp_reg_size;
7694 current_frame_info.gmask = gmask;
7695 current_frame_info.fmask = fmask;
7696 current_frame_info.reg_offset = reg_offset;
7697 current_frame_info.initialized = reload_completed;
7699 /* Ok, we're done. */
7703 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7706 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7707 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7708 [BASE_REG+OFFSET] will always be a valid address.
7710 WORD_OP is either "st" for save, "ld" for restore.
7711 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7714 sparc_flat_save_restore (FILE *file, const char *base_reg, int offset,
7715 unsigned long gmask, unsigned long fmask,
7716 const char *word_op, const char *doubleword_op,
7717 HOST_WIDE_INT base_offset)
7721 if (gmask == 0 && fmask == 0)
7724 /* Save registers starting from high to low. We've already saved the
7725 previous frame pointer and previous return address for the debugger's
7726 sake. The debugger allows us to not need a nop in the epilog if at least
7727 one register is reloaded in addition to return address. */
7731 for (regno = 1; regno <= 31; regno++)
7733 if ((gmask & (1L << regno)) != 0)
7735 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7737 /* We can save two registers in a row. If we're not at a
7738 double word boundary, move to one.
7739 sparc_flat_compute_frame_size ensures there's room to do
7741 if (offset % 8 != 0)
7742 offset += UNITS_PER_WORD;
7744 if (word_op[0] == 's')
7746 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7747 doubleword_op, reg_names[regno],
7749 if (dwarf2out_do_frame ())
7751 char *l = dwarf2out_cfi_label ();
7752 dwarf2out_reg_save (l, regno, offset + base_offset);
7754 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7758 fprintf (file, "\t%s\t[%s+%d], %s\n",
7759 doubleword_op, base_reg, offset,
7762 offset += 2 * UNITS_PER_WORD;
7767 if (word_op[0] == 's')
7769 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7770 word_op, reg_names[regno],
7772 if (dwarf2out_do_frame ())
7773 dwarf2out_reg_save ("", regno, offset + base_offset);
7776 fprintf (file, "\t%s\t[%s+%d], %s\n",
7777 word_op, base_reg, offset, reg_names[regno]);
7779 offset += UNITS_PER_WORD;
7787 for (regno = 32; regno <= 63; regno++)
7789 if ((fmask & (1L << (regno - 32))) != 0)
7791 if (word_op[0] == 's')
7793 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7794 word_op, reg_names[regno],
7796 if (dwarf2out_do_frame ())
7797 dwarf2out_reg_save ("", regno, offset + base_offset);
7800 fprintf (file, "\t%s\t[%s+%d], %s\n",
7801 word_op, base_reg, offset, reg_names[regno]);
7803 offset += UNITS_PER_WORD;
7809 /* Set up the stack and frame (if desired) for the function. */
7812 sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
7814 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7815 unsigned long gmask = current_frame_info.gmask;
7817 sparc_output_scratch_registers (file);
7819 /* This is only for the human reader. */
7820 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7821 fprintf (file, "\t%s# vars= "HOST_WIDE_INT_PRINT_DEC", "
7822 "regs= %d/%d, args= %d, extra= %d\n",
7824 current_frame_info.var_size,
7825 current_frame_info.gp_reg_size / 4,
7826 current_frame_info.fp_reg_size / 4,
7827 current_function_outgoing_args_size,
7828 current_frame_info.extra_size);
7830 size = SPARC_STACK_ALIGN (size);
7831 size = (! current_frame_info.initialized
7832 ? sparc_flat_compute_frame_size (size)
7833 : current_frame_info.total_size);
7835 /* These cases shouldn't happen. Catch them now. */
7836 if (size == 0 && (gmask || current_frame_info.fmask))
7839 /* Allocate our stack frame by decrementing %sp.
7840 At present, the only algorithm gdb can use to determine if this is a
7841 flat frame is if we always set %i7 if we set %sp. This can be optimized
7842 in the future by putting in some sort of debugging information that says
7843 this is a `flat' function. However, there is still the case of debugging
7844 code without such debugging information (including cases where most fns
7845 have such info, but there is one that doesn't). So, always do this now
7846 so we don't get a lot of code out there that gdb can't handle.
7847 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7848 distinguish us from a non-flat function but there won't (and shouldn't)
7849 be any differences anyway. The return pc is saved (if necessary) right
7850 after %i7 so gdb won't have to look too far to find it. */
7853 int reg_offset = current_frame_info.reg_offset;
7854 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7855 static const char *const t1_str = "%g1";
7857 /* Things get a little tricky if local variables take up more than ~4096
7858 bytes and outgoing arguments take up more than ~4096 bytes. When that
7859 happens, the register save area can't be accessed from either end of
7860 the frame. Handle this by decrementing %sp to the start of the gp
7861 register save area, save the regs, update %i7, and then set %sp to its
7862 final value. Given that we only have one scratch register to play
7863 with it is the cheapest solution, and it helps gdb out as it won't
7864 slow down recognition of flat functions.
7865 Don't change the order of insns emitted here without checking with
7866 the gdb folk first. */
7868 /* Is the entire register save area offsettable from %sp? */
7869 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
7873 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7874 sp_str, size, sp_str);
7875 if (gmask & HARD_FRAME_POINTER_MASK)
7877 fprintf (file, "\tst\t%s, [%s+%d]\n",
7878 fp_str, sp_str, reg_offset);
7879 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7880 "\t%s# set up frame pointer\n",
7881 sp_str, size, fp_str, ASM_COMMENT_START);
7887 build_big_number (file, size, t1_str);
7888 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7889 if (gmask & HARD_FRAME_POINTER_MASK)
7891 fprintf (file, "\tst\t%s, [%s+%d]\n",
7892 fp_str, sp_str, reg_offset);
7893 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7894 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7898 if (dwarf2out_do_frame ())
7900 char *l = dwarf2out_cfi_label ();
7901 if (gmask & HARD_FRAME_POINTER_MASK)
7903 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7904 reg_offset - 4 - size);
7905 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7908 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7910 if (gmask & RETURN_ADDR_MASK)
7912 fprintf (file, "\tst\t%s, [%s+%d]\n",
7913 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7914 if (dwarf2out_do_frame ())
7915 dwarf2out_return_save ("", reg_offset - size);
7918 sparc_flat_save_restore (file, sp_str, reg_offset,
7919 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7920 current_frame_info.fmask,
7921 "st", "std", -size);
7925 /* Subtract %sp in two steps, but make sure there is always a
7926 64-byte register save area, and %sp is properly aligned. */
7928 /* Amount to decrement %sp by, the first time. */
7929 HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7931 /* Amount to decrement %sp by, the second time. */
7932 HOST_WIDE_INT size2 = size - size1;
7934 /* Offset to register save area from %sp after first decrement. */
7935 int offset = (int)(size1 - (size - reg_offset));
7939 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7940 sp_str, size1, sp_str);
7941 if (gmask & HARD_FRAME_POINTER_MASK)
7943 fprintf (file, "\tst\t%s, [%s+%d]\n"
7944 "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7945 "\t%s# set up frame pointer\n",
7946 fp_str, sp_str, offset, sp_str, size1,
7947 fp_str, ASM_COMMENT_START);
7953 build_big_number (file, size1, t1_str);
7954 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7955 if (gmask & HARD_FRAME_POINTER_MASK)
7957 fprintf (file, "\tst\t%s, [%s+%d]\n"
7958 "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7959 fp_str, sp_str, offset, sp_str, t1_str,
7960 fp_str, ASM_COMMENT_START);
7964 if (dwarf2out_do_frame ())
7966 char *l = dwarf2out_cfi_label ();
7967 if (gmask & HARD_FRAME_POINTER_MASK)
7969 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7970 offset - 4 - size1);
7971 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7974 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7976 if (gmask & RETURN_ADDR_MASK)
7978 fprintf (file, "\tst\t%s, [%s+%d]\n",
7979 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
7980 if (dwarf2out_do_frame ())
7981 /* offset - size1 == reg_offset - size
7982 if reg_offset were updated above like offset. */
7983 dwarf2out_return_save ("", offset - size1);
7986 sparc_flat_save_restore (file, sp_str, offset,
7987 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7988 current_frame_info.fmask,
7989 "st", "std", -size1);
7991 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7992 sp_str, size2, sp_str);
7995 build_big_number (file, size2, t1_str);
7996 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7998 if (dwarf2out_do_frame ())
7999 if (! (gmask & HARD_FRAME_POINTER_MASK))
8000 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
8004 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
8007 /* Do any necessary cleanup after a function to restore stack, frame,
8011 sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
8013 rtx epilogue_delay = current_function_epilogue_delay_list;
8014 int noepilogue = FALSE;
8016 /* This is only for the human reader. */
8017 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
8019 /* The epilogue does not depend on any registers, but the stack
8020 registers, so we assume that if we have 1 pending nop, it can be
8021 ignored, and 2 it must be filled (2 nops occur for integer
8022 multiply and divide). */
8024 size = SPARC_STACK_ALIGN (size);
8025 size = (!current_frame_info.initialized
8026 ? sparc_flat_compute_frame_size (size)
8027 : current_frame_info.total_size);
8029 if (size == 0 && epilogue_delay == 0)
8031 rtx insn = get_last_insn ();
8033 /* If the last insn was a BARRIER, we don't have to write any code
8034 because a jump (aka return) was put there. */
8035 if (GET_CODE (insn) == NOTE)
8036 insn = prev_nonnote_insn (insn);
8037 if (insn && GET_CODE (insn) == BARRIER)
8043 int reg_offset = current_frame_info.reg_offset;
8045 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
8046 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
8047 static const char *const t1_str = "%g1";
8049 /* In the reload sequence, we don't need to fill the load delay
8050 slots for most of the loads, also see if we can fill the final
8051 delay slot if not otherwise filled by the reload sequence. */
8054 build_big_number (file, size, t1_str);
8056 if (frame_pointer_needed)
8059 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
8060 fp_str, t1_str, sp_str, ASM_COMMENT_START);
8062 fprintf (file,"\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
8063 "\t\t%s# sp not trusted here\n",
8064 fp_str, size, sp_str, ASM_COMMENT_START);
8067 /* Is the entire register save area offsettable from %sp? */
8068 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
8074 /* Restore %sp in two steps, but make sure there is always a
8075 64-byte register save area, and %sp is properly aligned. */
8077 /* Amount to increment %sp by, the first time. */
8078 reg_offset1 = ((reg_offset - 64 - 16) + 15) & -16;
8080 /* Offset to register save area from %sp. */
8081 reg_offset = reg_offset1 - reg_offset;
8083 if (reg_offset1 > 4096)
8085 build_big_number (file, reg_offset1, t1_str);
8086 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8089 fprintf (file, "\tsub\t%s, -%d, %s\n", sp_str, reg_offset1, sp_str);
8092 /* We must restore the frame pointer and return address reg first
8093 because they are treated specially by the prologue output code. */
8094 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
8096 fprintf (file, "\tld\t[%s+%d], %s\n",
8097 sp_str, reg_offset, fp_str);
8100 if (current_frame_info.gmask & RETURN_ADDR_MASK)
8102 fprintf (file, "\tld\t[%s+%d], %s\n",
8103 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
8107 /* Restore any remaining saved registers. */
8108 sparc_flat_save_restore (file, sp_str, reg_offset,
8109 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
8110 current_frame_info.fmask,
8113 /* If we had to increment %sp in two steps, record it so the second
8114 restoration in the epilogue finishes up. */
8115 if (reg_offset1 > 0)
8117 size -= reg_offset1;
8119 build_big_number (file, size, t1_str);
8122 if (current_function_returns_struct)
8123 fprintf (file, "\tjmp\t%%o7+12\n");
8125 fprintf (file, "\tretl\n");
8127 /* If the only register saved is the return address, we need a
8128 nop, unless we have an instruction to put into it. Otherwise
8129 we don't since reloading multiple registers doesn't reference
8130 the register being loaded. */
8136 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1, NULL);
8139 else if (size > 4096)
8140 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8143 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
8144 sp_str, size, sp_str);
8147 fprintf (file, "\tnop\n");
8150 /* Reset state info for each function. */
8151 current_frame_info = zero_frame_info;
8153 sparc_output_deferred_case_vectors ();
8156 /* Define the number of delay slots needed for the function epilogue.
8158 On the sparc, we need a slot if either no stack has been allocated,
8159 or the only register saved is the return register. */
8162 sparc_flat_epilogue_delay_slots (void)
8164 if (!current_frame_info.initialized)
8165 (void) sparc_flat_compute_frame_size (get_frame_size ());
8167 if (current_frame_info.total_size == 0)
8173 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
8174 Any single length instruction which doesn't reference the stack or frame
8178 sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
8180 rtx pat = PATTERN (trial);
8182 if (get_attr_length (trial) != 1)
8185 if (! reg_mentioned_p (stack_pointer_rtx, pat)
8186 && ! reg_mentioned_p (frame_pointer_rtx, pat))
8192 /* Adjust the cost of a scheduling dependency. Return the new cost of
8193 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8196 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8198 enum attr_type insn_type;
8200 if (! recog_memoized (insn))
8203 insn_type = get_attr_type (insn);
8205 if (REG_NOTE_KIND (link) == 0)
8207 /* Data dependency; DEP_INSN writes a register that INSN reads some
8210 /* if a load, then the dependence must be on the memory address;
8211 add an extra "cycle". Note that the cost could be two cycles
8212 if the reg was written late in an instruction group; we ca not tell
8214 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8217 /* Get the delay only if the address of the store is the dependence. */
8218 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8220 rtx pat = PATTERN(insn);
8221 rtx dep_pat = PATTERN (dep_insn);
8223 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8224 return cost; /* This should not happen! */
8226 /* The dependency between the two instructions was on the data that
8227 is being stored. Assume that this implies that the address of the
8228 store is not dependent. */
8229 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8232 return cost + 3; /* An approximation. */
8235 /* A shift instruction cannot receive its data from an instruction
8236 in the same cycle; add a one cycle penalty. */
8237 if (insn_type == TYPE_SHIFT)
8238 return cost + 3; /* Split before cascade into shift. */
8242 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8243 INSN writes some cycles later. */
8245 /* These are only significant for the fpu unit; writing a fp reg before
8246 the fpu has finished with it stalls the processor. */
8248 /* Reusing an integer register causes no problems. */
8249 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8257 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8259 enum attr_type insn_type, dep_type;
8260 rtx pat = PATTERN(insn);
8261 rtx dep_pat = PATTERN (dep_insn);
8263 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8266 insn_type = get_attr_type (insn);
8267 dep_type = get_attr_type (dep_insn);
8269 switch (REG_NOTE_KIND (link))
8272 /* Data dependency; DEP_INSN writes a register that INSN reads some
8279 /* Get the delay iff the address of the store is the dependence. */
8280 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8283 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8290 /* If a load, then the dependence must be on the memory address. If
8291 the addresses aren't equal, then it might be a false dependency */
8292 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8294 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8295 || GET_CODE (SET_DEST (dep_pat)) != MEM
8296 || GET_CODE (SET_SRC (pat)) != MEM
8297 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8298 XEXP (SET_SRC (pat), 0)))
8306 /* Compare to branch latency is 0. There is no benefit from
8307 separating compare and branch. */
8308 if (dep_type == TYPE_COMPARE)
8310 /* Floating point compare to branch latency is less than
8311 compare to conditional move. */
8312 if (dep_type == TYPE_FPCMP)
8321 /* Anti-dependencies only penalize the fpu unit. */
8322 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8334 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8338 case PROCESSOR_SUPERSPARC:
8339 cost = supersparc_adjust_cost (insn, link, dep, cost);
8341 case PROCESSOR_HYPERSPARC:
8342 case PROCESSOR_SPARCLITE86X:
8343 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8352 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8353 int sched_verbose ATTRIBUTE_UNUSED,
8354 int max_ready ATTRIBUTE_UNUSED)
8359 sparc_use_dfa_pipeline_interface (void)
8361 if ((1 << sparc_cpu) &
8362 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
8363 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8364 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
8365 (1 << PROCESSOR_ULTRASPARC3)))
8371 sparc_use_sched_lookahead (void)
8373 if (sparc_cpu == PROCESSOR_ULTRASPARC
8374 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8376 if ((1 << sparc_cpu) &
8377 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8378 (1 << PROCESSOR_SPARCLITE86X)))
8384 sparc_issue_rate (void)
8391 /* Assume V9 processors are capable of at least dual-issue. */
8393 case PROCESSOR_SUPERSPARC:
8395 case PROCESSOR_HYPERSPARC:
8396 case PROCESSOR_SPARCLITE86X:
8398 case PROCESSOR_ULTRASPARC:
8399 case PROCESSOR_ULTRASPARC3:
8405 set_extends (rtx insn)
8407 register rtx pat = PATTERN (insn);
8409 switch (GET_CODE (SET_SRC (pat)))
8411 /* Load and some shift instructions zero extend. */
8414 /* sethi clears the high bits */
8416 /* LO_SUM is used with sethi. sethi cleared the high
8417 bits and the values used with lo_sum are positive */
8419 /* Store flag stores 0 or 1 */
8429 rtx op0 = XEXP (SET_SRC (pat), 0);
8430 rtx op1 = XEXP (SET_SRC (pat), 1);
8431 if (GET_CODE (op1) == CONST_INT)
8432 return INTVAL (op1) >= 0;
8433 if (GET_CODE (op0) != REG)
8435 if (sparc_check_64 (op0, insn) == 1)
8437 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8442 rtx op0 = XEXP (SET_SRC (pat), 0);
8443 rtx op1 = XEXP (SET_SRC (pat), 1);
8444 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8446 if (GET_CODE (op1) == CONST_INT)
8447 return INTVAL (op1) >= 0;
8448 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8451 return GET_MODE (SET_SRC (pat)) == SImode;
8452 /* Positive integers leave the high bits zero. */
8454 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8456 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8459 return - (GET_MODE (SET_SRC (pat)) == SImode);
8461 return sparc_check_64 (SET_SRC (pat), insn);
8467 /* We _ought_ to have only one kind per function, but... */
8468 static GTY(()) rtx sparc_addr_diff_list;
8469 static GTY(()) rtx sparc_addr_list;
8472 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8474 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8476 sparc_addr_diff_list
8477 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8479 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8483 sparc_output_addr_vec (rtx vec)
8485 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8486 int idx, vlen = XVECLEN (body, 0);
8488 #ifdef ASM_OUTPUT_ADDR_VEC_START
8489 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8492 #ifdef ASM_OUTPUT_CASE_LABEL
8493 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8496 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8499 for (idx = 0; idx < vlen; idx++)
8501 ASM_OUTPUT_ADDR_VEC_ELT
8502 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8505 #ifdef ASM_OUTPUT_ADDR_VEC_END
8506 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8511 sparc_output_addr_diff_vec (rtx vec)
8513 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8514 rtx base = XEXP (XEXP (body, 0), 0);
8515 int idx, vlen = XVECLEN (body, 1);
8517 #ifdef ASM_OUTPUT_ADDR_VEC_START
8518 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8521 #ifdef ASM_OUTPUT_CASE_LABEL
8522 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8525 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8528 for (idx = 0; idx < vlen; idx++)
8530 ASM_OUTPUT_ADDR_DIFF_ELT
8533 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8534 CODE_LABEL_NUMBER (base));
8537 #ifdef ASM_OUTPUT_ADDR_VEC_END
8538 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8543 sparc_output_deferred_case_vectors (void)
8548 if (sparc_addr_list == NULL_RTX
8549 && sparc_addr_diff_list == NULL_RTX)
8552 /* Align to cache line in the function's code section. */
8553 function_section (current_function_decl);
8555 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8557 ASM_OUTPUT_ALIGN (asm_out_file, align);
8559 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8560 sparc_output_addr_vec (XEXP (t, 0));
8561 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8562 sparc_output_addr_diff_vec (XEXP (t, 0));
8564 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8567 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8568 unknown. Return 1 if the high bits are zero, -1 if the register is
8571 sparc_check_64 (rtx x, rtx insn)
8573 /* If a register is set only once it is safe to ignore insns this
8574 code does not know how to handle. The loop will either recognize
8575 the single set and return the correct value or fail to recognize
8580 if (GET_CODE (x) != REG)
8583 if (GET_MODE (x) == DImode)
8584 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8586 if (flag_expensive_optimizations
8587 && REG_N_SETS (REGNO (y)) == 1)
8593 insn = get_last_insn_anywhere ();
8598 while ((insn = PREV_INSN (insn)))
8600 switch (GET_CODE (insn))
8613 rtx pat = PATTERN (insn);
8614 if (GET_CODE (pat) != SET)
8616 if (rtx_equal_p (x, SET_DEST (pat)))
8617 return set_extends (insn);
8618 if (y && rtx_equal_p (y, SET_DEST (pat)))
8619 return set_extends (insn);
8620 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8628 /* Returns assembly code to perform a DImode shift using
8629 a 64-bit global or out register on SPARC-V8+. */
8631 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8633 static char asm_code[60];
8635 /* The scratch register is only required when the destination
8636 register is not a 64-bit global or out register. */
8637 if (which_alternative != 2)
8638 operands[3] = operands[0];
8640 /* We can only shift by constants <= 63. */
8641 if (GET_CODE (operands[2]) == CONST_INT)
8642 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8644 if (GET_CODE (operands[1]) == CONST_INT)
8646 output_asm_insn ("mov\t%1, %3", operands);
8650 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8651 if (sparc_check_64 (operands[1], insn) <= 0)
8652 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8653 output_asm_insn ("or\t%L1, %3, %3", operands);
8656 strcpy(asm_code, opcode);
8658 if (which_alternative != 2)
8659 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8661 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8664 /* Output rtl to increment the profiler label LABELNO
8665 for profiling a function entry. */
8668 sparc_profile_hook (int labelno)
8673 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8674 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8675 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8677 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8680 #ifdef OBJECT_FORMAT_ELF
8682 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8684 if (flags & SECTION_MERGE)
8686 /* entsize cannot be expressed in this section attributes
8688 default_elf_asm_named_section (name, flags);
8692 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8694 if (!(flags & SECTION_DEBUG))
8695 fputs (",#alloc", asm_out_file);
8696 if (flags & SECTION_WRITE)
8697 fputs (",#write", asm_out_file);
8698 if (flags & SECTION_TLS)
8699 fputs (",#tls", asm_out_file);
8700 if (flags & SECTION_CODE)
8701 fputs (",#execinstr", asm_out_file);
8703 /* ??? Handle SECTION_BSS. */
8705 fputc ('\n', asm_out_file);
8707 #endif /* OBJECT_FORMAT_ELF */
8709 /* We do not allow sibling calls if -mflat, nor
8710 we do not allow indirect calls to be optimized into sibling calls.
8712 Also, on sparc 32-bit we cannot emit a sibling call when the
8713 current function returns a structure. This is because the "unimp
8714 after call" convention would cause the callee to return to the
8715 wrong place. The generic code already disallows cases where the
8716 function being called returns a structure.
8718 It may seem strange how this last case could occur. Usually there
8719 is code after the call which jumps to epilogue code which dumps the
8720 return value into the struct return area. That ought to invalidate
8721 the sibling call right? Well, in the c++ case we can end up passing
8722 the pointer to the struct return area to a constructor (which returns
8723 void) and then nothing else happens. Such a sibling call would look
8724 valid without the added check here. */
8726 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8730 && (TARGET_ARCH64 || ! current_function_returns_struct));
8733 /* libfunc renaming. */
8734 #include "config/gofast.h"
8737 sparc_init_libfuncs (void)
8741 /* Use the subroutines that Sun's library provides for integer
8742 multiply and divide. The `*' prevents an underscore from
8743 being prepended by the compiler. .umul is a little faster
8745 set_optab_libfunc (smul_optab, SImode, "*.umul");
8746 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8747 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8748 set_optab_libfunc (smod_optab, SImode, "*.rem");
8749 set_optab_libfunc (umod_optab, SImode, "*.urem");
8751 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8752 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8753 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8754 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8755 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8756 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8758 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8759 is because with soft-float, the SFmode and DFmode sqrt
8760 instructions will be absent, and the compiler will notice and
8761 try to use the TFmode sqrt instruction for calls to the
8762 builtin function sqrt, but this fails. */
8764 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8766 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8767 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8768 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8769 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8770 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8771 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8773 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8774 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8775 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8776 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8778 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8779 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8780 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8782 if (DITF_CONVERSION_LIBFUNCS)
8784 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8785 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8786 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8789 if (SUN_CONVERSION_LIBFUNCS)
8791 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8792 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8793 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8794 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8799 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8800 do not exist in the library. Make sure the compiler does not
8801 emit calls to them by accident. (It should always use the
8802 hardware instructions.) */
8803 set_optab_libfunc (smul_optab, SImode, 0);
8804 set_optab_libfunc (sdiv_optab, SImode, 0);
8805 set_optab_libfunc (udiv_optab, SImode, 0);
8806 set_optab_libfunc (smod_optab, SImode, 0);
8807 set_optab_libfunc (umod_optab, SImode, 0);
8809 if (SUN_INTEGER_MULTIPLY_64)
8811 set_optab_libfunc (smul_optab, DImode, "__mul64");
8812 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8813 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8814 set_optab_libfunc (smod_optab, DImode, "__rem64");
8815 set_optab_libfunc (umod_optab, DImode, "__urem64");
8818 if (SUN_CONVERSION_LIBFUNCS)
8820 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8821 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8822 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8823 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8827 gofast_maybe_init_libfuncs ();
8830 /* ??? Similar to the standard section selection, but force reloc-y-ness
8831 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8832 pretending PIC always on), but that's what the old code did. */
8835 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8837 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8840 /* Use text section for a constant unless we need more alignment than
8844 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8845 unsigned HOST_WIDE_INT align)
8847 if (align <= MAX_TEXT_ALIGN
8848 && ! (flag_pic && (symbolic_operand (x, mode)
8849 || SUNOS4_SHARED_LIBRARIES)))
8850 readonly_data_section ();
8856 sparc_extra_constraint_check (rtx op, int c, int strict)
8861 && (c == 'T' || c == 'U'))
8867 return fp_sethi_p (op);
8870 return fp_mov_p (op);
8873 return fp_high_losum_p (op);
8877 || (GET_CODE (op) == REG
8878 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8879 || reg_renumber[REGNO (op)] >= 0)))
8880 return register_ok_for_ldd (op);
8892 /* Our memory extra constraints have to emulate the
8893 behavior of 'm' and 'o' in order for reload to work
8895 if (GET_CODE (op) == MEM)
8898 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8900 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8905 reload_ok_mem = (reload_in_progress
8906 && GET_CODE (op) == REG
8907 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8908 && reg_renumber [REGNO (op)] < 0);
8911 return reload_ok_mem;
8914 /* ??? This duplicates information provided to the compiler by the
8915 ??? scheduler description. Some day, teach genautomata to output
8916 ??? the latencies and then CSE will just use that. */
8919 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8923 case PLUS: case MINUS: case ABS: case NEG:
8924 case FLOAT: case UNSIGNED_FLOAT:
8925 case FIX: case UNSIGNED_FIX:
8926 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8927 if (FLOAT_MODE_P (GET_MODE (x)))
8931 case PROCESSOR_ULTRASPARC:
8932 case PROCESSOR_ULTRASPARC3:
8933 *total = COSTS_N_INSNS (4);
8936 case PROCESSOR_SUPERSPARC:
8937 *total = COSTS_N_INSNS (3);
8940 case PROCESSOR_CYPRESS:
8941 *total = COSTS_N_INSNS (5);
8944 case PROCESSOR_HYPERSPARC:
8945 case PROCESSOR_SPARCLITE86X:
8947 *total = COSTS_N_INSNS (1);
8952 *total = COSTS_N_INSNS (1);
8958 case PROCESSOR_ULTRASPARC:
8959 if (GET_MODE (x) == SFmode)
8960 *total = COSTS_N_INSNS (13);
8962 *total = COSTS_N_INSNS (23);
8965 case PROCESSOR_ULTRASPARC3:
8966 if (GET_MODE (x) == SFmode)
8967 *total = COSTS_N_INSNS (20);
8969 *total = COSTS_N_INSNS (29);
8972 case PROCESSOR_SUPERSPARC:
8973 *total = COSTS_N_INSNS (12);
8976 case PROCESSOR_CYPRESS:
8977 *total = COSTS_N_INSNS (63);
8980 case PROCESSOR_HYPERSPARC:
8981 case PROCESSOR_SPARCLITE86X:
8982 *total = COSTS_N_INSNS (17);
8986 *total = COSTS_N_INSNS (30);
8991 if (FLOAT_MODE_P (GET_MODE (x)))
8995 case PROCESSOR_ULTRASPARC:
8996 case PROCESSOR_ULTRASPARC3:
8997 *total = COSTS_N_INSNS (1);
9000 case PROCESSOR_SUPERSPARC:
9001 *total = COSTS_N_INSNS (3);
9004 case PROCESSOR_CYPRESS:
9005 *total = COSTS_N_INSNS (5);
9008 case PROCESSOR_HYPERSPARC:
9009 case PROCESSOR_SPARCLITE86X:
9011 *total = COSTS_N_INSNS (1);
9016 /* ??? Maybe mark integer compares as zero cost on
9017 ??? all UltraSPARC processors because the result
9018 ??? can be bypassed to a branch in the same group. */
9020 *total = COSTS_N_INSNS (1);
9024 if (FLOAT_MODE_P (GET_MODE (x)))
9028 case PROCESSOR_ULTRASPARC:
9029 case PROCESSOR_ULTRASPARC3:
9030 *total = COSTS_N_INSNS (4);
9033 case PROCESSOR_SUPERSPARC:
9034 *total = COSTS_N_INSNS (3);
9037 case PROCESSOR_CYPRESS:
9038 *total = COSTS_N_INSNS (7);
9041 case PROCESSOR_HYPERSPARC:
9042 case PROCESSOR_SPARCLITE86X:
9043 *total = COSTS_N_INSNS (1);
9047 *total = COSTS_N_INSNS (5);
9052 /* The latency is actually variable for Ultra-I/II
9053 And if one of the inputs have a known constant
9054 value, we could calculate this precisely.
9056 However, for that to be useful we would need to
9057 add some machine description changes which would
9058 make sure small constants ended up in rs1 of the
9059 multiply instruction. This is because the multiply
9060 latency is determined by the number of clear (or
9061 set if the value is negative) bits starting from
9062 the most significant bit of the first input.
9064 The algorithm for computing num_cycles of a multiply
9068 highest_bit = highest_clear_bit(rs1);
9070 highest_bit = highest_set_bit(rs1);
9073 num_cycles = 4 + ((highest_bit - 3) / 2);
9075 If we did that we would have to also consider register
9076 allocation issues that would result from forcing such
9077 a value into a register.
9079 There are other similar tricks we could play if we
9080 knew, for example, that one input was an array index.
9082 Since we do not play any such tricks currently the
9083 safest thing to do is report the worst case latency. */
9084 if (sparc_cpu == PROCESSOR_ULTRASPARC)
9086 *total = (GET_MODE (x) == DImode
9087 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
9091 /* Multiply latency on Ultra-III, fortunately, is constant. */
9092 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
9094 *total = COSTS_N_INSNS (6);
9098 if (sparc_cpu == PROCESSOR_HYPERSPARC
9099 || sparc_cpu == PROCESSOR_SPARCLITE86X)
9101 *total = COSTS_N_INSNS (17);
9105 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
9112 if (FLOAT_MODE_P (GET_MODE (x)))
9116 case PROCESSOR_ULTRASPARC:
9117 if (GET_MODE (x) == SFmode)
9118 *total = COSTS_N_INSNS (13);
9120 *total = COSTS_N_INSNS (23);
9123 case PROCESSOR_ULTRASPARC3:
9124 if (GET_MODE (x) == SFmode)
9125 *total = COSTS_N_INSNS (17);
9127 *total = COSTS_N_INSNS (20);
9130 case PROCESSOR_SUPERSPARC:
9131 if (GET_MODE (x) == SFmode)
9132 *total = COSTS_N_INSNS (6);
9134 *total = COSTS_N_INSNS (9);
9137 case PROCESSOR_HYPERSPARC:
9138 case PROCESSOR_SPARCLITE86X:
9139 if (GET_MODE (x) == SFmode)
9140 *total = COSTS_N_INSNS (8);
9142 *total = COSTS_N_INSNS (12);
9146 *total = COSTS_N_INSNS (7);
9151 if (sparc_cpu == PROCESSOR_ULTRASPARC)
9152 *total = (GET_MODE (x) == DImode
9153 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
9154 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
9155 *total = (GET_MODE (x) == DImode
9156 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
9158 *total = COSTS_N_INSNS (25);
9162 /* Conditional moves. */
9165 case PROCESSOR_ULTRASPARC:
9166 *total = COSTS_N_INSNS (2);
9169 case PROCESSOR_ULTRASPARC3:
9170 if (FLOAT_MODE_P (GET_MODE (x)))
9171 *total = COSTS_N_INSNS (3);
9173 *total = COSTS_N_INSNS (2);
9177 *total = COSTS_N_INSNS (1);
9182 /* If outer-code is SIGN/ZERO extension we have to subtract
9183 out COSTS_N_INSNS (1) from whatever we return in determining
9187 case PROCESSOR_ULTRASPARC:
9188 if (outer_code == ZERO_EXTEND)
9189 *total = COSTS_N_INSNS (1);
9191 *total = COSTS_N_INSNS (2);
9194 case PROCESSOR_ULTRASPARC3:
9195 if (outer_code == ZERO_EXTEND)
9197 if (GET_MODE (x) == QImode
9198 || GET_MODE (x) == HImode
9199 || outer_code == SIGN_EXTEND)
9200 *total = COSTS_N_INSNS (2);
9202 *total = COSTS_N_INSNS (1);
9206 /* This handles sign extension (3 cycles)
9207 and everything else (2 cycles). */
9208 *total = COSTS_N_INSNS (2);
9212 case PROCESSOR_SUPERSPARC:
9213 if (FLOAT_MODE_P (GET_MODE (x))
9214 || outer_code == ZERO_EXTEND
9215 || outer_code == SIGN_EXTEND)
9216 *total = COSTS_N_INSNS (0);
9218 *total = COSTS_N_INSNS (1);
9221 case PROCESSOR_TSC701:
9222 if (outer_code == ZERO_EXTEND
9223 || outer_code == SIGN_EXTEND)
9224 *total = COSTS_N_INSNS (2);
9226 *total = COSTS_N_INSNS (3);
9229 case PROCESSOR_CYPRESS:
9230 if (outer_code == ZERO_EXTEND
9231 || outer_code == SIGN_EXTEND)
9232 *total = COSTS_N_INSNS (1);
9234 *total = COSTS_N_INSNS (2);
9237 case PROCESSOR_HYPERSPARC:
9238 case PROCESSOR_SPARCLITE86X:
9240 if (outer_code == ZERO_EXTEND
9241 || outer_code == SIGN_EXTEND)
9242 *total = COSTS_N_INSNS (0);
9244 *total = COSTS_N_INSNS (1);
9249 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
9267 if (GET_MODE (x) == DImode
9268 && ((XINT (x, 3) == 0
9269 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
9270 || (XINT (x, 3) == -1
9272 && XINT (x, 2) >= -0x1000)))
9283 /* Output the assembler code for a thunk function. THUNK_DECL is the
9284 declaration for the thunk function itself, FUNCTION is the decl for
9285 the target function. DELTA is an immediate constant offset to be
9286 added to THIS. If VCALL_OFFSET is nonzero, the word at address
9287 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
9290 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
9291 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
9294 rtx this, insn, funexp;
9296 reload_completed = 1;
9297 epilogue_completed = 1;
9299 current_function_uses_only_leaf_regs = 1;
9301 emit_note (NOTE_INSN_PROLOGUE_END);
9303 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9304 returns a structure, the structure return pointer is there instead. */
9305 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9306 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
9308 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
9310 /* Add DELTA. When possible use a plain add, otherwise load it into
9311 a register first. */
9314 rtx delta_rtx = GEN_INT (delta);
9316 if (! SPARC_SIMM13_P (delta))
9318 rtx scratch = gen_rtx_REG (Pmode, 1);
9319 emit_move_insn (scratch, delta_rtx);
9320 delta_rtx = scratch;
9323 /* THIS += DELTA. */
9324 emit_insn (gen_add2_insn (this, delta_rtx));
9327 /* Add the word at address (*THIS + VCALL_OFFSET). */
9330 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
9331 rtx scratch = gen_rtx_REG (Pmode, 1);
9333 if (vcall_offset >= 0)
9336 /* SCRATCH = *THIS. */
9337 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this));
9339 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
9340 may not have any available scratch register at this point. */
9341 if (SPARC_SIMM13_P (vcall_offset))
9343 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
9344 else if (! fixed_regs[5]
9345 /* The below sequence is made up of at least 2 insns,
9346 while the default method may need only one. */
9347 && vcall_offset < -8192)
9349 rtx scratch2 = gen_rtx_REG (Pmode, 5);
9350 emit_move_insn (scratch2, vcall_offset_rtx);
9351 vcall_offset_rtx = scratch2;
9355 rtx increment = GEN_INT (-4096);
9357 /* VCALL_OFFSET is a negative number whose typical range can be
9358 estimated as -32768..0 in 32-bit mode. In almost all cases
9359 it is therefore cheaper to emit multiple add insns than
9360 spilling and loading the constant into a register (at least
9362 while (! SPARC_SIMM13_P (vcall_offset))
9364 emit_insn (gen_add2_insn (scratch, increment));
9365 vcall_offset += 4096;
9367 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
9370 /* SCRATCH = *(*THIS + VCALL_OFFSET). */
9371 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
9372 gen_rtx_PLUS (Pmode,
9374 vcall_offset_rtx)));
9376 /* THIS += *(*THIS + VCALL_OFFSET). */
9377 emit_insn (gen_add2_insn (this, scratch));
9380 /* Generate a tail call to the target function. */
9381 if (! TREE_USED (function))
9383 assemble_external (function);
9384 TREE_USED (function) = 1;
9386 funexp = XEXP (DECL_RTL (function), 0);
9387 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9388 insn = emit_call_insn (gen_sibcall (funexp));
9389 SIBLING_CALL_P (insn) = 1;
9392 /* Run just enough of rest_of_compilation to get the insns emitted.
9393 There's not really enough bulk here to make other passes such as
9394 instruction scheduling worth while. Note that use_thunk calls
9395 assemble_start_function and assemble_end_function. */
9396 insn = get_insns ();
9397 insn_locators_initialize ();
9398 shorten_branches (insn);
9399 final_start_function (insn, file, 1);
9400 final (insn, file, 1, 0);
9401 final_end_function ();
9403 reload_completed = 0;
9404 epilogue_completed = 0;
9408 /* Return true if sparc_output_mi_thunk would be able to output the
9409 assembler code for the thunk function specified by the arguments
9410 it is passed, and false otherwise. */
9412 sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED,
9413 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
9414 HOST_WIDE_INT vcall_offset,
9415 tree function ATTRIBUTE_UNUSED)
9417 /* Bound the loop used in the default method above. */
9418 return (vcall_offset >= -32768 || ! fixed_regs[5]);
9421 /* How to allocate a 'struct machine_function'. */
9423 static struct machine_function *
9424 sparc_init_machine_status (void)
9426 return ggc_alloc_cleared (sizeof (struct machine_function));
9429 /* Locate some local-dynamic symbol still in use by this function
9430 so that we can print its name in local-dynamic base patterns. */
9433 get_some_local_dynamic_name (void)
9437 if (cfun->machine->some_ld_name)
9438 return cfun->machine->some_ld_name;
9440 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9442 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9443 return cfun->machine->some_ld_name;
9449 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9454 && GET_CODE (x) == SYMBOL_REF
9455 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9457 cfun->machine->some_ld_name = XSTR (x, 0);
9464 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9465 We need to emit DTP-relative relocations. */
9468 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9473 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9476 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9481 output_addr_const (file, x);
9485 #include "gt-sparc.h"