1 ;; GCC machine description for SPARC synchronization instructions.
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 (define_mode_macro I12MODE [QI HI])
23 (define_mode_macro I24MODE [HI SI])
24 (define_mode_macro I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
25 (define_mode_attr modesuffix [(SI "") (DI "x")])
27 (define_expand "memory_barrier"
28 [(set (mem:BLK (match_dup 0))
29 (unspec_volatile:BLK [(mem:BLK (match_dup 0)) (match_dup 1)]
31 "TARGET_V8 || TARGET_V9"
33 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
34 MEM_VOLATILE_P (operands[0]) = 1;
36 /* member #StoreStore | #LoadStore | #StoreLoad | #LoadLoad */
37 operands[1] = GEN_INT (15);
40 operands[1] = GEN_INT (8);
44 [(set (match_operand:BLK 0 "" "")
45 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")
46 (const_int 8)] UNSPECV_MEMBAR))]
49 [(set_attr "type" "multi")])
51 (define_insn "*membar"
52 [(set (match_operand:BLK 0 "" "")
53 (unspec_volatile:BLK [(match_operand:BLK 1 "" "")
54 (match_operand:SI 2 "immediate_operand" "I")]
58 [(set_attr "type" "multi")])
60 (define_expand "sync_compare_and_swap<mode>"
61 [(match_operand:I12MODE 0 "register_operand" "")
62 (match_operand:I12MODE 1 "memory_operand" "")
63 (match_operand:I12MODE 2 "register_operand" "")
64 (match_operand:I12MODE 3 "register_operand" "")]
67 sparc_expand_compare_and_swap_12 (operands[0], operands[1],
68 operands[2], operands[3]);
72 (define_expand "sync_compare_and_swap<mode>"
74 [(set (match_operand:I48MODE 0 "register_operand" "=r")
75 (match_operand:I48MODE 1 "memory_operand" ""))
77 (unspec_volatile:I48MODE
78 [(match_operand:I48MODE 2 "register_operand" "")
79 (match_operand:I48MODE 3 "register_operand" "")]
83 if (! REG_P (XEXP (operands[1], 0)))
85 rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
86 operands[1] = replace_equiv_address (operands[1], addr);
88 emit_insn (gen_memory_barrier ());
91 (define_insn "*sync_compare_and_swap<mode>"
92 [(set (match_operand:I48MODE 0 "register_operand" "=r")
93 (match_operand:I48MODE 1 "memory_reg_operand" "+m"))
95 (unspec_volatile:I48MODE
96 [(match_operand:I48MODE 2 "register_operand" "r")
97 (match_operand:I48MODE 3 "register_operand" "0")]
99 "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
100 "cas<modesuffix>\t%1, %2, %0"
101 [(set_attr "type" "multi")])
103 (define_insn "*sync_compare_and_swapdi_v8plus"
104 [(set (match_operand:DI 0 "register_operand" "=h")
105 (match_operand:DI 1 "memory_reg_operand" "+m"))
108 [(match_operand:DI 2 "register_operand" "h")
109 (match_operand:DI 3 "register_operand" "0")]
113 if (sparc_check_64 (operands[3], insn) <= 0)
114 output_asm_insn ("srl\t%L3, 0, %L3", operands);
115 output_asm_insn ("sllx\t%H3, 32, %H3", operands);
116 output_asm_insn ("or\t%L3, %H3, %L3", operands);
117 if (sparc_check_64 (operands[2], insn) <= 0)
118 output_asm_insn ("srl\t%L2, 0, %L2", operands);
119 output_asm_insn ("sllx\t%H2, 32, %H3", operands);
120 output_asm_insn ("or\t%L2, %H3, %H3", operands);
121 output_asm_insn ("casx\t%1, %H3, %L3", operands);
122 return "srlx\t%L3, 32, %H3";
124 [(set_attr "type" "multi")
125 (set_attr "length" "8")])
127 (define_expand "sync_lock_test_and_set<mode>"
128 [(match_operand:I12MODE 0 "register_operand" "")
129 (match_operand:I12MODE 1 "memory_operand" "")
130 (match_operand:I12MODE 2 "arith_operand" "")]
133 if (operands[2] != const1_rtx)
136 emit_insn (gen_memory_barrier ());
137 if (<MODE>mode != QImode)
138 operands[1] = adjust_address (operands[1], QImode, 0);
139 emit_insn (gen_ldstub<mode> (operands[0], operands[1]));
143 (define_expand "sync_lock_test_and_setsi"
145 [(set (match_operand:SI 0 "register_operand" "")
146 (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "")]
149 (match_operand:SI 2 "arith_operand" ""))])]
152 if (! TARGET_V8 && ! TARGET_V9)
154 if (operands[2] != const1_rtx)
156 operands[1] = adjust_address (operands[1], QImode, 0);
157 emit_insn (gen_ldstubsi (operands[0], operands[1]));
160 emit_insn (gen_memory_barrier ());
161 operands[2] = force_reg (SImode, operands[2]);
164 (define_insn "*swapsi"
165 [(set (match_operand:SI 0 "register_operand" "=r")
166 (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
169 (match_operand:SI 2 "register_operand" "0"))]
170 "TARGET_V8 || TARGET_V9"
172 [(set_attr "type" "multi")])
174 (define_expand "ldstubqi"
175 [(parallel [(set (match_operand:QI 0 "register_operand" "")
176 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")]
178 (set (match_dup 1) (const_int -1))])]
182 (define_expand "ldstub<mode>"
183 [(parallel [(set (match_operand:I24MODE 0 "register_operand" "")
185 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")]
187 (set (match_dup 1) (const_int -1))])]
191 (define_insn "*ldstubqi"
192 [(set (match_operand:QI 0 "register_operand" "=r")
193 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
195 (set (match_dup 1) (const_int -1))]
198 [(set_attr "type" "multi")])
200 (define_insn "*ldstub<mode>"
201 [(set (match_operand:I24MODE 0 "register_operand" "=r")
203 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
205 (set (match_dup 1) (const_int -1))]
208 [(set_attr "type" "multi")])