1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "hard-reg-set.h"
37 #include "basic-block.h"
41 #ifndef STACK_PUSH_CODE
42 #ifdef STACK_GROWS_DOWNWARD
43 #define STACK_PUSH_CODE PRE_DEC
45 #define STACK_PUSH_CODE PRE_INC
49 #ifndef STACK_POP_CODE
50 #ifdef STACK_GROWS_DOWNWARD
51 #define STACK_POP_CODE POST_INC
53 #define STACK_POP_CODE POST_DEC
57 static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx));
58 static rtx *find_single_use_1 PARAMS ((rtx, rtx *));
59 static void validate_replace_src_1 PARAMS ((rtx *, void *));
60 static rtx split_insn PARAMS ((rtx));
62 /* Nonzero means allow operands to be volatile.
63 This should be 0 if you are generating rtl, such as if you are calling
64 the functions in optabs.c and expmed.c (most of the time).
65 This should be 1 if all valid insns need to be recognized,
66 such as in regclass.c and final.c and reload.c.
68 init_recog and init_recog_no_volatile are responsible for setting this. */
72 struct recog_data recog_data;
74 /* Contains a vector of operand_alternative structures for every operand.
75 Set up by preprocess_constraints. */
76 struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
78 /* On return from `constrain_operands', indicate which alternative
81 int which_alternative;
83 /* Nonzero after end of reload pass.
84 Set to 1 or 0 by toplev.c.
85 Controls the significance of (SUBREG (MEM)). */
89 /* Initialize data used by the function `recog'.
90 This must be called once in the compilation of a function
91 before any insn recognition may be done in the function. */
94 init_recog_no_volatile ()
105 /* Try recognizing the instruction INSN,
106 and return the code number that results.
107 Remember the code so that repeated calls do not
108 need to spend the time for actual rerecognition.
110 This function is the normal interface to instruction recognition.
111 The automatically-generated function `recog' is normally called
112 through this one. (The only exception is in combine.c.) */
115 recog_memoized_1 (insn)
118 if (INSN_CODE (insn) < 0)
119 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
120 return INSN_CODE (insn);
123 /* Check that X is an insn-body for an `asm' with operands
124 and that the operands mentioned in it are legitimate. */
127 check_asm_operands (x)
132 const char **constraints;
135 /* Post-reload, be more strict with things. */
136 if (reload_completed)
138 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
139 extract_insn (make_insn_raw (x));
140 constrain_operands (1);
141 return which_alternative >= 0;
144 noperands = asm_noperands (x);
150 operands = (rtx *) alloca (noperands * sizeof (rtx));
151 constraints = (const char **) alloca (noperands * sizeof (char *));
153 decode_asm_operands (x, operands, NULL, constraints, NULL);
155 for (i = 0; i < noperands; i++)
157 const char *c = constraints[i];
160 if (ISDIGIT ((unsigned char) c[0]) && c[1] == '\0')
161 c = constraints[c[0] - '0'];
163 if (! asm_operand_ok (operands[i], c))
170 /* Static data for the next two routines. */
172 typedef struct change_t
180 static change_t *changes;
181 static int changes_allocated;
183 static int num_changes = 0;
185 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
186 at which NEW will be placed. If OBJECT is zero, no validation is done,
187 the change is simply made.
189 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
190 will be called with the address and mode as parameters. If OBJECT is
191 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
194 IN_GROUP is non-zero if this is part of a group of changes that must be
195 performed as a group. In that case, the changes will be stored. The
196 function `apply_change_group' will validate and apply the changes.
198 If IN_GROUP is zero, this is a single change. Try to recognize the insn
199 or validate the memory reference with the change applied. If the result
200 is not valid for the machine, suppress the change and return zero.
201 Otherwise, perform the change and return 1. */
204 validate_change (object, loc, new, in_group)
212 if (old == new || rtx_equal_p (old, new))
215 if (in_group == 0 && num_changes != 0)
220 /* Save the information describing this change. */
221 if (num_changes >= changes_allocated)
223 if (changes_allocated == 0)
224 /* This value allows for repeated substitutions inside complex
225 indexed addresses, or changes in up to 5 insns. */
226 changes_allocated = MAX_RECOG_OPERANDS * 5;
228 changes_allocated *= 2;
231 (change_t*) xrealloc (changes,
232 sizeof (change_t) * changes_allocated);
235 changes[num_changes].object = object;
236 changes[num_changes].loc = loc;
237 changes[num_changes].old = old;
239 if (object && GET_CODE (object) != MEM)
241 /* Set INSN_CODE to force rerecognition of insn. Save old code in
243 changes[num_changes].old_code = INSN_CODE (object);
244 INSN_CODE (object) = -1;
249 /* If we are making a group of changes, return 1. Otherwise, validate the
250 change group we made. */
255 return apply_change_group ();
258 /* This subroutine of apply_change_group verifies whether the changes to INSN
259 were valid; i.e. whether INSN can still be recognized. */
262 insn_invalid_p (insn)
265 rtx pat = PATTERN (insn);
266 int num_clobbers = 0;
267 /* If we are before reload and the pattern is a SET, see if we can add
269 int icode = recog (pat, insn,
270 (GET_CODE (pat) == SET
271 && ! reload_completed && ! reload_in_progress)
272 ? &num_clobbers : 0);
273 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
276 /* If this is an asm and the operand aren't legal, then fail. Likewise if
277 this is not an asm and the insn wasn't recognized. */
278 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
279 || (!is_asm && icode < 0))
282 /* If we have to add CLOBBERs, fail if we have to add ones that reference
283 hard registers since our callers can't know if they are live or not.
284 Otherwise, add them. */
285 if (num_clobbers > 0)
289 if (added_clobbers_hard_reg_p (icode))
292 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
293 XVECEXP (newpat, 0, 0) = pat;
294 add_clobbers (newpat, icode);
295 PATTERN (insn) = pat = newpat;
298 /* After reload, verify that all constraints are satisfied. */
299 if (reload_completed)
303 if (! constrain_operands (1))
307 INSN_CODE (insn) = icode;
311 /* Apply a group of changes previously issued with `validate_change'.
312 Return 1 if all changes are valid, zero otherwise. */
315 apply_change_group ()
318 rtx last_validated = NULL_RTX;
320 /* The changes have been applied and all INSN_CODEs have been reset to force
323 The changes are valid if we aren't given an object, or if we are
324 given a MEM and it still is a valid address, or if this is in insn
325 and it is recognized. In the latter case, if reload has completed,
326 we also require that the operands meet the constraints for
329 for (i = 0; i < num_changes; i++)
331 rtx object = changes[i].object;
333 /* if there is no object to test or if it is the same as the one we
334 already tested, ignore it. */
335 if (object == 0 || object == last_validated)
338 if (GET_CODE (object) == MEM)
340 if (! memory_address_p (GET_MODE (object), XEXP (object, 0)))
343 else if (insn_invalid_p (object))
345 rtx pat = PATTERN (object);
347 /* Perhaps we couldn't recognize the insn because there were
348 extra CLOBBERs at the end. If so, try to re-recognize
349 without the last CLOBBER (later iterations will cause each of
350 them to be eliminated, in turn). But don't do this if we
351 have an ASM_OPERAND. */
352 if (GET_CODE (pat) == PARALLEL
353 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
354 && asm_noperands (PATTERN (object)) < 0)
358 if (XVECLEN (pat, 0) == 2)
359 newpat = XVECEXP (pat, 0, 0);
365 = gen_rtx_PARALLEL (VOIDmode,
366 rtvec_alloc (XVECLEN (pat, 0) - 1));
367 for (j = 0; j < XVECLEN (newpat, 0); j++)
368 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
371 /* Add a new change to this group to replace the pattern
372 with this new pattern. Then consider this change
373 as having succeeded. The change we added will
374 cause the entire call to fail if things remain invalid.
376 Note that this can lose if a later change than the one
377 we are processing specified &XVECEXP (PATTERN (object), 0, X)
378 but this shouldn't occur. */
380 validate_change (object, &PATTERN (object), newpat, 1);
383 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
384 /* If this insn is a CLOBBER or USE, it is always valid, but is
390 last_validated = object;
393 if (i == num_changes)
405 /* Return the number of changes so far in the current group. */
408 num_validated_changes ()
413 /* Retract the changes numbered NUM and up. */
421 /* Back out all the changes. Do this in the opposite order in which
423 for (i = num_changes - 1; i >= num; i--)
425 *changes[i].loc = changes[i].old;
426 if (changes[i].object && GET_CODE (changes[i].object) != MEM)
427 INSN_CODE (changes[i].object) = changes[i].old_code;
432 /* Replace every occurrence of FROM in X with TO. Mark each change with
433 validate_change passing OBJECT. */
436 validate_replace_rtx_1 (loc, from, to, object)
438 rtx from, to, object;
444 enum machine_mode op0_mode = VOIDmode;
445 int prev_changes = num_changes;
452 fmt = GET_RTX_FORMAT (code);
454 op0_mode = GET_MODE (XEXP (x, 0));
456 /* X matches FROM if it is the same rtx or they are both referring to the
457 same register in the same mode. Avoid calling rtx_equal_p unless the
458 operands look similar. */
461 || (GET_CODE (x) == REG && GET_CODE (from) == REG
462 && GET_MODE (x) == GET_MODE (from)
463 && REGNO (x) == REGNO (from))
464 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
465 && rtx_equal_p (x, from)))
467 validate_change (object, loc, to, 1);
471 /* Call ourself recursively to perform the replacements. */
473 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
476 validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
477 else if (fmt[i] == 'E')
478 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
479 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
482 /* If we didn't substitute, there is nothing more to do. */
483 if (num_changes == prev_changes)
486 /* Allow substituted expression to have different mode. This is used by
487 regmove to change mode of pseudo register. */
488 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode)
489 op0_mode = GET_MODE (XEXP (x, 0));
491 /* Do changes needed to keep rtx consistent. Don't do any other
492 simplifications, as it is not our job. */
494 if ((GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
495 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
497 validate_change (object, loc,
498 gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code
499 : swap_condition (code),
500 GET_MODE (x), XEXP (x, 1),
509 /* If we have a PLUS whose second operand is now a CONST_INT, use
510 plus_constant to try to simplify it.
511 ??? We may want later to remove this, once simplification is
512 separated from this function. */
513 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
514 validate_change (object, loc,
516 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1);
519 if (GET_CODE (XEXP (x, 1)) == CONST_INT
520 || GET_CODE (XEXP (x, 1)) == CONST_DOUBLE)
521 validate_change (object, loc,
523 (PLUS, GET_MODE (x), XEXP (x, 0),
524 simplify_gen_unary (NEG,
525 GET_MODE (x), XEXP (x, 1),
530 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
532 new = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0),
534 /* If any of the above failed, substitute in something that
535 we know won't be recognized. */
537 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
538 validate_change (object, loc, new, 1);
542 /* All subregs possible to simplify should be simplified. */
543 new = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode,
546 /* Subregs of VOIDmode operands are incorrect. */
547 if (!new && GET_MODE (SUBREG_REG (x)) == VOIDmode)
548 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
550 validate_change (object, loc, new, 1);
554 /* If we are replacing a register with memory, try to change the memory
555 to be the mode required for memory in extract operations (this isn't
556 likely to be an insertion operation; if it was, nothing bad will
557 happen, we might just fail in some cases). */
559 if (GET_CODE (XEXP (x, 0)) == MEM
560 && GET_CODE (XEXP (x, 1)) == CONST_INT
561 && GET_CODE (XEXP (x, 2)) == CONST_INT
562 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0))
563 && !MEM_VOLATILE_P (XEXP (x, 0)))
565 enum machine_mode wanted_mode = VOIDmode;
566 enum machine_mode is_mode = GET_MODE (XEXP (x, 0));
567 int pos = INTVAL (XEXP (x, 2));
569 if (GET_CODE (x) == ZERO_EXTRACT)
571 enum machine_mode new_mode
572 = mode_for_extraction (EP_extzv, 1);
573 if (new_mode != MAX_MACHINE_MODE)
574 wanted_mode = new_mode;
576 else if (GET_CODE (x) == SIGN_EXTRACT)
578 enum machine_mode new_mode
579 = mode_for_extraction (EP_extv, 1);
580 if (new_mode != MAX_MACHINE_MODE)
581 wanted_mode = new_mode;
584 /* If we have a narrower mode, we can do something. */
585 if (wanted_mode != VOIDmode
586 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
588 int offset = pos / BITS_PER_UNIT;
591 /* If the bytes and bits are counted differently, we
592 must adjust the offset. */
593 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
595 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
598 pos %= GET_MODE_BITSIZE (wanted_mode);
600 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset);
602 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
603 validate_change (object, &XEXP (x, 0), newmem, 1);
614 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
615 with TO. After all changes have been made, validate by seeing
616 if INSN is still valid. */
619 validate_replace_rtx_subexp (from, to, insn, loc)
620 rtx from, to, insn, *loc;
622 validate_replace_rtx_1 (loc, from, to, insn);
623 return apply_change_group ();
626 /* Try replacing every occurrence of FROM in INSN with TO. After all
627 changes have been made, validate by seeing if INSN is still valid. */
630 validate_replace_rtx (from, to, insn)
633 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
634 return apply_change_group ();
637 /* Try replacing every occurrence of FROM in INSN with TO. */
640 validate_replace_rtx_group (from, to, insn)
643 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
646 /* Function called by note_uses to replace used subexpressions. */
647 struct validate_replace_src_data
649 rtx from; /* Old RTX */
650 rtx to; /* New RTX */
651 rtx insn; /* Insn in which substitution is occurring. */
655 validate_replace_src_1 (x, data)
659 struct validate_replace_src_data *d
660 = (struct validate_replace_src_data *) data;
662 validate_replace_rtx_1 (x, d->from, d->to, d->insn);
665 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
666 SET_DESTs. After all changes have been made, validate by seeing if
667 INSN is still valid. */
670 validate_replace_src (from, to, insn)
673 struct validate_replace_src_data d;
678 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
679 return apply_change_group ();
683 /* Return 1 if the insn using CC0 set by INSN does not contain
684 any ordered tests applied to the condition codes.
685 EQ and NE tests do not count. */
688 next_insn_tests_no_inequality (insn)
691 rtx next = next_cc0_user (insn);
693 /* If there is no next insn, we have to take the conservative choice. */
697 return ((GET_CODE (next) == JUMP_INSN
698 || GET_CODE (next) == INSN
699 || GET_CODE (next) == CALL_INSN)
700 && ! inequality_comparisons_p (PATTERN (next)));
703 #if 0 /* This is useless since the insn that sets the cc's
704 must be followed immediately by the use of them. */
705 /* Return 1 if the CC value set up by INSN is not used. */
708 next_insns_test_no_inequality (insn)
711 rtx next = NEXT_INSN (insn);
713 for (; next != 0; next = NEXT_INSN (next))
715 if (GET_CODE (next) == CODE_LABEL
716 || GET_CODE (next) == BARRIER)
718 if (GET_CODE (next) == NOTE)
720 if (inequality_comparisons_p (PATTERN (next)))
722 if (sets_cc0_p (PATTERN (next)) == 1)
724 if (! reg_mentioned_p (cc0_rtx, PATTERN (next)))
732 /* This is used by find_single_use to locate an rtx that contains exactly one
733 use of DEST, which is typically either a REG or CC0. It returns a
734 pointer to the innermost rtx expression containing DEST. Appearances of
735 DEST that are being used to totally replace it are not counted. */
738 find_single_use_1 (dest, loc)
743 enum rtx_code code = GET_CODE (x);
761 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
762 of a REG that occupies all of the REG, the insn uses DEST if
763 it is mentioned in the destination or the source. Otherwise, we
764 need just check the source. */
765 if (GET_CODE (SET_DEST (x)) != CC0
766 && GET_CODE (SET_DEST (x)) != PC
767 && GET_CODE (SET_DEST (x)) != REG
768 && ! (GET_CODE (SET_DEST (x)) == SUBREG
769 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
770 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
771 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
772 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
773 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
776 return find_single_use_1 (dest, &SET_SRC (x));
780 return find_single_use_1 (dest, &XEXP (x, 0));
786 /* If it wasn't one of the common cases above, check each expression and
787 vector of this code. Look for a unique usage of DEST. */
789 fmt = GET_RTX_FORMAT (code);
790 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
794 if (dest == XEXP (x, i)
795 || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG
796 && REGNO (dest) == REGNO (XEXP (x, i))))
799 this_result = find_single_use_1 (dest, &XEXP (x, i));
802 result = this_result;
803 else if (this_result)
804 /* Duplicate usage. */
807 else if (fmt[i] == 'E')
811 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
813 if (XVECEXP (x, i, j) == dest
814 || (GET_CODE (dest) == REG
815 && GET_CODE (XVECEXP (x, i, j)) == REG
816 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
819 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
822 result = this_result;
823 else if (this_result)
832 /* See if DEST, produced in INSN, is used only a single time in the
833 sequel. If so, return a pointer to the innermost rtx expression in which
836 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
838 This routine will return usually zero either before flow is called (because
839 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
840 note can't be trusted).
842 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
843 care about REG_DEAD notes or LOG_LINKS.
845 Otherwise, we find the single use by finding an insn that has a
846 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
847 only referenced once in that insn, we know that it must be the first
848 and last insn referencing DEST. */
851 find_single_use (dest, insn, ploc)
863 next = NEXT_INSN (insn);
865 || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN))
868 result = find_single_use_1 (dest, &PATTERN (next));
875 if (reload_completed || reload_in_progress || GET_CODE (dest) != REG)
878 for (next = next_nonnote_insn (insn);
879 next != 0 && GET_CODE (next) != CODE_LABEL;
880 next = next_nonnote_insn (next))
881 if (INSN_P (next) && dead_or_set_p (next, dest))
883 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
884 if (XEXP (link, 0) == insn)
889 result = find_single_use_1 (dest, &PATTERN (next));
899 /* Return 1 if OP is a valid general operand for machine mode MODE.
900 This is either a register reference, a memory reference,
901 or a constant. In the case of a memory reference, the address
902 is checked for general validity for the target machine.
904 Register and memory references must have mode MODE in order to be valid,
905 but some constants have no machine mode and are valid for any mode.
907 If MODE is VOIDmode, OP is checked for validity for whatever mode
910 The main use of this function is as a predicate in match_operand
911 expressions in the machine description.
913 For an explanation of this function's behavior for registers of
914 class NO_REGS, see the comment for `register_operand'. */
917 general_operand (op, mode)
919 enum machine_mode mode;
921 enum rtx_code code = GET_CODE (op);
923 if (mode == VOIDmode)
924 mode = GET_MODE (op);
926 /* Don't accept CONST_INT or anything similar
927 if the caller wants something floating. */
928 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
929 && GET_MODE_CLASS (mode) != MODE_INT
930 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
933 if (GET_CODE (op) == CONST_INT
934 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
938 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
940 #ifdef LEGITIMATE_PIC_OPERAND_P
941 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
943 && LEGITIMATE_CONSTANT_P (op));
945 /* Except for certain constants with VOIDmode, already checked for,
946 OP's mode must match MODE if MODE specifies a mode. */
948 if (GET_MODE (op) != mode)
953 #ifdef INSN_SCHEDULING
954 /* On machines that have insn scheduling, we want all memory
955 reference to be explicit, so outlaw paradoxical SUBREGs. */
956 if (GET_CODE (SUBREG_REG (op)) == MEM
957 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
960 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
961 may result in incorrect reference. We should simplify all valid
962 subregs of MEM anyway. But allow this after reload because we
963 might be called from cleanup_subreg_operands.
965 ??? This is a kludge. */
966 if (!reload_completed && SUBREG_BYTE (op) != 0
967 && GET_CODE (SUBREG_REG (op)) == MEM)
970 op = SUBREG_REG (op);
971 code = GET_CODE (op);
975 /* A register whose class is NO_REGS is not a general operand. */
976 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
977 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
981 rtx y = XEXP (op, 0);
983 if (! volatile_ok && MEM_VOLATILE_P (op))
986 if (GET_CODE (y) == ADDRESSOF)
989 /* Use the mem's mode, since it will be reloaded thus. */
990 mode = GET_MODE (op);
991 GO_IF_LEGITIMATE_ADDRESS (mode, y, win);
994 /* Pretend this is an operand for now; we'll run force_operand
995 on its replacement in fixup_var_refs_1. */
996 if (code == ADDRESSOF)
1005 /* Return 1 if OP is a valid memory address for a memory reference
1008 The main use of this function is as a predicate in match_operand
1009 expressions in the machine description. */
1012 address_operand (op, mode)
1014 enum machine_mode mode;
1016 return memory_address_p (mode, op);
1019 /* Return 1 if OP is a register reference of mode MODE.
1020 If MODE is VOIDmode, accept a register in any mode.
1022 The main use of this function is as a predicate in match_operand
1023 expressions in the machine description.
1025 As a special exception, registers whose class is NO_REGS are
1026 not accepted by `register_operand'. The reason for this change
1027 is to allow the representation of special architecture artifacts
1028 (such as a condition code register) without extending the rtl
1029 definitions. Since registers of class NO_REGS cannot be used
1030 as registers in any case where register classes are examined,
1031 it is most consistent to keep this function from accepting them. */
1034 register_operand (op, mode)
1036 enum machine_mode mode;
1038 if (GET_MODE (op) != mode && mode != VOIDmode)
1041 if (GET_CODE (op) == SUBREG)
1043 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1044 because it is guaranteed to be reloaded into one.
1045 Just make sure the MEM is valid in itself.
1046 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1047 but currently it does result from (SUBREG (REG)...) where the
1048 reg went on the stack.) */
1049 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1050 return general_operand (op, mode);
1052 #ifdef CLASS_CANNOT_CHANGE_MODE
1053 if (GET_CODE (SUBREG_REG (op)) == REG
1054 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER
1055 && (TEST_HARD_REG_BIT
1056 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
1057 REGNO (SUBREG_REG (op))))
1058 && CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (SUBREG_REG (op)))
1059 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT
1060 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT)
1064 op = SUBREG_REG (op);
1067 /* If we have an ADDRESSOF, consider it valid since it will be
1068 converted into something that will not be a MEM. */
1069 if (GET_CODE (op) == ADDRESSOF)
1072 /* We don't consider registers whose class is NO_REGS
1073 to be a register operand. */
1074 return (GET_CODE (op) == REG
1075 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1076 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1079 /* Return 1 for a register in Pmode; ignore the tested mode. */
1082 pmode_register_operand (op, mode)
1084 enum machine_mode mode ATTRIBUTE_UNUSED;
1086 return register_operand (op, Pmode);
1089 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1090 or a hard register. */
1093 scratch_operand (op, mode)
1095 enum machine_mode mode;
1097 if (GET_MODE (op) != mode && mode != VOIDmode)
1100 return (GET_CODE (op) == SCRATCH
1101 || (GET_CODE (op) == REG
1102 && REGNO (op) < FIRST_PSEUDO_REGISTER));
1105 /* Return 1 if OP is a valid immediate operand for mode MODE.
1107 The main use of this function is as a predicate in match_operand
1108 expressions in the machine description. */
1111 immediate_operand (op, mode)
1113 enum machine_mode mode;
1115 /* Don't accept CONST_INT or anything similar
1116 if the caller wants something floating. */
1117 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1118 && GET_MODE_CLASS (mode) != MODE_INT
1119 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1122 if (GET_CODE (op) == CONST_INT
1123 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1126 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1127 result in 0/1. It seems a safe assumption that this is
1128 in range for everyone. */
1129 if (GET_CODE (op) == CONSTANT_P_RTX)
1132 return (CONSTANT_P (op)
1133 && (GET_MODE (op) == mode || mode == VOIDmode
1134 || GET_MODE (op) == VOIDmode)
1135 #ifdef LEGITIMATE_PIC_OPERAND_P
1136 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1138 && LEGITIMATE_CONSTANT_P (op));
1141 /* Returns 1 if OP is an operand that is a CONST_INT. */
1144 const_int_operand (op, mode)
1146 enum machine_mode mode;
1148 if (GET_CODE (op) != CONST_INT)
1151 if (mode != VOIDmode
1152 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1158 /* Returns 1 if OP is an operand that is a constant integer or constant
1159 floating-point number. */
1162 const_double_operand (op, mode)
1164 enum machine_mode mode;
1166 /* Don't accept CONST_INT or anything similar
1167 if the caller wants something floating. */
1168 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1169 && GET_MODE_CLASS (mode) != MODE_INT
1170 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1173 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)
1174 && (mode == VOIDmode || GET_MODE (op) == mode
1175 || GET_MODE (op) == VOIDmode));
1178 /* Return 1 if OP is a general operand that is not an immediate operand. */
1181 nonimmediate_operand (op, mode)
1183 enum machine_mode mode;
1185 return (general_operand (op, mode) && ! CONSTANT_P (op));
1188 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1191 nonmemory_operand (op, mode)
1193 enum machine_mode mode;
1195 if (CONSTANT_P (op))
1197 /* Don't accept CONST_INT or anything similar
1198 if the caller wants something floating. */
1199 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1200 && GET_MODE_CLASS (mode) != MODE_INT
1201 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1204 if (GET_CODE (op) == CONST_INT
1205 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op))
1208 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1209 || mode == VOIDmode)
1210 #ifdef LEGITIMATE_PIC_OPERAND_P
1211 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1213 && LEGITIMATE_CONSTANT_P (op));
1216 if (GET_MODE (op) != mode && mode != VOIDmode)
1219 if (GET_CODE (op) == SUBREG)
1221 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1222 because it is guaranteed to be reloaded into one.
1223 Just make sure the MEM is valid in itself.
1224 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1225 but currently it does result from (SUBREG (REG)...) where the
1226 reg went on the stack.) */
1227 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1228 return general_operand (op, mode);
1229 op = SUBREG_REG (op);
1232 /* We don't consider registers whose class is NO_REGS
1233 to be a register operand. */
1234 return (GET_CODE (op) == REG
1235 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1236 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1239 /* Return 1 if OP is a valid operand that stands for pushing a
1240 value of mode MODE onto the stack.
1242 The main use of this function is as a predicate in match_operand
1243 expressions in the machine description. */
1246 push_operand (op, mode)
1248 enum machine_mode mode;
1250 unsigned int rounded_size = GET_MODE_SIZE (mode);
1252 #ifdef PUSH_ROUNDING
1253 rounded_size = PUSH_ROUNDING (rounded_size);
1256 if (GET_CODE (op) != MEM)
1259 if (mode != VOIDmode && GET_MODE (op) != mode)
1264 if (rounded_size == GET_MODE_SIZE (mode))
1266 if (GET_CODE (op) != STACK_PUSH_CODE)
1271 if (GET_CODE (op) != PRE_MODIFY
1272 || GET_CODE (XEXP (op, 1)) != PLUS
1273 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1274 || GET_CODE (XEXP (XEXP (op, 1), 1)) != CONST_INT
1275 #ifdef STACK_GROWS_DOWNWARD
1276 || INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size
1278 || INTVAL (XEXP (XEXP (op, 1), 1)) != rounded_size
1284 return XEXP (op, 0) == stack_pointer_rtx;
1287 /* Return 1 if OP is a valid operand that stands for popping a
1288 value of mode MODE off the stack.
1290 The main use of this function is as a predicate in match_operand
1291 expressions in the machine description. */
1294 pop_operand (op, mode)
1296 enum machine_mode mode;
1298 if (GET_CODE (op) != MEM)
1301 if (mode != VOIDmode && GET_MODE (op) != mode)
1306 if (GET_CODE (op) != STACK_POP_CODE)
1309 return XEXP (op, 0) == stack_pointer_rtx;
1312 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1315 memory_address_p (mode, addr)
1316 enum machine_mode mode ATTRIBUTE_UNUSED;
1319 if (GET_CODE (addr) == ADDRESSOF)
1322 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1329 /* Return 1 if OP is a valid memory reference with mode MODE,
1330 including a valid address.
1332 The main use of this function is as a predicate in match_operand
1333 expressions in the machine description. */
1336 memory_operand (op, mode)
1338 enum machine_mode mode;
1342 if (! reload_completed)
1343 /* Note that no SUBREG is a memory operand before end of reload pass,
1344 because (SUBREG (MEM...)) forces reloading into a register. */
1345 return GET_CODE (op) == MEM && general_operand (op, mode);
1347 if (mode != VOIDmode && GET_MODE (op) != mode)
1351 if (GET_CODE (inner) == SUBREG)
1352 inner = SUBREG_REG (inner);
1354 return (GET_CODE (inner) == MEM && general_operand (op, mode));
1357 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1358 that is, a memory reference whose address is a general_operand. */
1361 indirect_operand (op, mode)
1363 enum machine_mode mode;
1365 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1366 if (! reload_completed
1367 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM)
1369 int offset = SUBREG_BYTE (op);
1370 rtx inner = SUBREG_REG (op);
1372 if (mode != VOIDmode && GET_MODE (op) != mode)
1375 /* The only way that we can have a general_operand as the resulting
1376 address is if OFFSET is zero and the address already is an operand
1377 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1380 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1381 || (GET_CODE (XEXP (inner, 0)) == PLUS
1382 && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT
1383 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1384 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1387 return (GET_CODE (op) == MEM
1388 && memory_operand (op, mode)
1389 && general_operand (XEXP (op, 0), Pmode));
1392 /* Return 1 if this is a comparison operator. This allows the use of
1393 MATCH_OPERATOR to recognize all the branch insns. */
1396 comparison_operator (op, mode)
1398 enum machine_mode mode;
1400 return ((mode == VOIDmode || GET_MODE (op) == mode)
1401 && GET_RTX_CLASS (GET_CODE (op)) == '<');
1404 /* If BODY is an insn body that uses ASM_OPERANDS,
1405 return the number of operands (both input and output) in the insn.
1406 Otherwise return -1. */
1409 asm_noperands (body)
1412 switch (GET_CODE (body))
1415 /* No output operands: return number of input operands. */
1416 return ASM_OPERANDS_INPUT_LENGTH (body);
1418 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1419 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1420 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
1424 if (GET_CODE (XVECEXP (body, 0, 0)) == SET
1425 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
1427 /* Multiple output operands, or 1 output plus some clobbers:
1428 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1432 /* Count backwards through CLOBBERs to determine number of SETs. */
1433 for (i = XVECLEN (body, 0); i > 0; i--)
1435 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1437 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1441 /* N_SETS is now number of output operands. */
1444 /* Verify that all the SETs we have
1445 came from a single original asm_operands insn
1446 (so that invalid combinations are blocked). */
1447 for (i = 0; i < n_sets; i++)
1449 rtx elt = XVECEXP (body, 0, i);
1450 if (GET_CODE (elt) != SET)
1452 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1454 /* If these ASM_OPERANDS rtx's came from different original insns
1455 then they aren't allowed together. */
1456 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1457 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
1460 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
1463 else if (GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1465 /* 0 outputs, but some clobbers:
1466 body is [(asm_operands ...) (clobber (reg ...))...]. */
1469 /* Make sure all the other parallel things really are clobbers. */
1470 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1471 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1474 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
1483 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1484 copy its operands (both input and output) into the vector OPERANDS,
1485 the locations of the operands within the insn into the vector OPERAND_LOCS,
1486 and the constraints for the operands into CONSTRAINTS.
1487 Write the modes of the operands into MODES.
1488 Return the assembler-template.
1490 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1491 we don't store that info. */
1494 decode_asm_operands (body, operands, operand_locs, constraints, modes)
1498 const char **constraints;
1499 enum machine_mode *modes;
1503 const char *template = 0;
1505 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1507 rtx asmop = SET_SRC (body);
1508 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1510 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1;
1512 for (i = 1; i < noperands; i++)
1515 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1);
1517 operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1);
1519 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1);
1521 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1);
1524 /* The output is in the SET.
1525 Its constraint is in the ASM_OPERANDS itself. */
1527 operands[0] = SET_DEST (body);
1529 operand_locs[0] = &SET_DEST (body);
1531 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1533 modes[0] = GET_MODE (SET_DEST (body));
1534 template = ASM_OPERANDS_TEMPLATE (asmop);
1536 else if (GET_CODE (body) == ASM_OPERANDS)
1539 /* No output operands: BODY is (asm_operands ....). */
1541 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop);
1543 /* The input operands are found in the 1st element vector. */
1544 /* Constraints for inputs are in the 2nd element vector. */
1545 for (i = 0; i < noperands; i++)
1548 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1550 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1552 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1554 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1556 template = ASM_OPERANDS_TEMPLATE (asmop);
1558 else if (GET_CODE (body) == PARALLEL
1559 && GET_CODE (XVECEXP (body, 0, 0)) == SET
1560 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
1562 rtx asmop = SET_SRC (XVECEXP (body, 0, 0));
1563 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1564 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1565 int nout = 0; /* Does not include CLOBBERs. */
1567 /* At least one output, plus some CLOBBERs. */
1569 /* The outputs are in the SETs.
1570 Their constraints are in the ASM_OPERANDS itself. */
1571 for (i = 0; i < nparallel; i++)
1573 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1574 break; /* Past last SET */
1577 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1579 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1581 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1583 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1587 for (i = 0; i < nin; i++)
1590 operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i);
1592 operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i);
1594 constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1596 modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1599 template = ASM_OPERANDS_TEMPLATE (asmop);
1601 else if (GET_CODE (body) == PARALLEL
1602 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1604 /* No outputs, but some CLOBBERs. */
1606 rtx asmop = XVECEXP (body, 0, 0);
1607 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1609 for (i = 0; i < nin; i++)
1612 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1614 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1616 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1618 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1621 template = ASM_OPERANDS_TEMPLATE (asmop);
1627 /* Check if an asm_operand matches it's constraints.
1628 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1631 asm_operand_ok (op, constraint)
1633 const char *constraint;
1637 /* Use constrain_operands after reload. */
1638 if (reload_completed)
1643 char c = *constraint++;
1657 case '0': case '1': case '2': case '3': case '4':
1658 case '5': case '6': case '7': case '8': case '9':
1659 /* For best results, our caller should have given us the
1660 proper matching constraint, but we can't actually fail
1661 the check if they didn't. Indicate that results are
1663 while (ISDIGIT (*constraint))
1669 if (address_operand (op, VOIDmode))
1674 case 'V': /* non-offsettable */
1675 if (memory_operand (op, VOIDmode))
1679 case 'o': /* offsettable */
1680 if (offsettable_nonstrict_memref_p (op))
1685 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1686 excepting those that expand_call created. Further, on some
1687 machines which do not have generalized auto inc/dec, an inc/dec
1688 is not a memory_operand.
1690 Match any memory and hope things are resolved after reload. */
1692 if (GET_CODE (op) == MEM
1694 || GET_CODE (XEXP (op, 0)) == PRE_DEC
1695 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1700 if (GET_CODE (op) == MEM
1702 || GET_CODE (XEXP (op, 0)) == PRE_INC
1703 || GET_CODE (XEXP (op, 0)) == POST_INC))
1708 #ifndef REAL_ARITHMETIC
1709 /* Match any floating double constant, but only if
1710 we can examine the bits of it reliably. */
1711 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1712 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1713 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1719 if (GET_CODE (op) == CONST_DOUBLE)
1724 if (GET_CODE (op) == CONST_DOUBLE
1725 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G'))
1729 if (GET_CODE (op) == CONST_DOUBLE
1730 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H'))
1735 if (GET_CODE (op) == CONST_INT
1736 || (GET_CODE (op) == CONST_DOUBLE
1737 && GET_MODE (op) == VOIDmode))
1743 #ifdef LEGITIMATE_PIC_OPERAND_P
1744 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1751 if (GET_CODE (op) == CONST_INT
1752 || (GET_CODE (op) == CONST_DOUBLE
1753 && GET_MODE (op) == VOIDmode))
1758 if (GET_CODE (op) == CONST_INT
1759 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'))
1763 if (GET_CODE (op) == CONST_INT
1764 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J'))
1768 if (GET_CODE (op) == CONST_INT
1769 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
1773 if (GET_CODE (op) == CONST_INT
1774 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'))
1778 if (GET_CODE (op) == CONST_INT
1779 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M'))
1783 if (GET_CODE (op) == CONST_INT
1784 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N'))
1788 if (GET_CODE (op) == CONST_INT
1789 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'))
1793 if (GET_CODE (op) == CONST_INT
1794 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'))
1802 if (general_operand (op, VOIDmode))
1807 /* For all other letters, we first check for a register class,
1808 otherwise it is an EXTRA_CONSTRAINT. */
1809 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1812 if (GET_MODE (op) == BLKmode)
1814 if (register_operand (op, VOIDmode))
1817 #ifdef EXTRA_CONSTRAINT
1818 if (EXTRA_CONSTRAINT (op, c))
1828 /* Given an rtx *P, if it is a sum containing an integer constant term,
1829 return the location (type rtx *) of the pointer to that constant term.
1830 Otherwise, return a null pointer. */
1833 find_constant_term_loc (p)
1837 enum rtx_code code = GET_CODE (*p);
1839 /* If *P IS such a constant term, P is its location. */
1841 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1845 /* Otherwise, if not a sum, it has no constant term. */
1847 if (GET_CODE (*p) != PLUS)
1850 /* If one of the summands is constant, return its location. */
1852 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1853 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1856 /* Otherwise, check each summand for containing a constant term. */
1858 if (XEXP (*p, 0) != 0)
1860 tem = find_constant_term_loc (&XEXP (*p, 0));
1865 if (XEXP (*p, 1) != 0)
1867 tem = find_constant_term_loc (&XEXP (*p, 1));
1875 /* Return 1 if OP is a memory reference
1876 whose address contains no side effects
1877 and remains valid after the addition
1878 of a positive integer less than the
1879 size of the object being referenced.
1881 We assume that the original address is valid and do not check it.
1883 This uses strict_memory_address_p as a subroutine, so
1884 don't use it before reload. */
1887 offsettable_memref_p (op)
1890 return ((GET_CODE (op) == MEM)
1891 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)));
1894 /* Similar, but don't require a strictly valid mem ref:
1895 consider pseudo-regs valid as index or base regs. */
1898 offsettable_nonstrict_memref_p (op)
1901 return ((GET_CODE (op) == MEM)
1902 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0)));
1905 /* Return 1 if Y is a memory address which contains no side effects
1906 and would remain valid after the addition of a positive integer
1907 less than the size of that mode.
1909 We assume that the original address is valid and do not check it.
1910 We do check that it is valid for narrower modes.
1912 If STRICTP is nonzero, we require a strictly valid address,
1913 for the sake of use in reload.c. */
1916 offsettable_address_p (strictp, mode, y)
1918 enum machine_mode mode;
1921 enum rtx_code ycode = GET_CODE (y);
1925 int (*addressp) PARAMS ((enum machine_mode, rtx)) =
1926 (strictp ? strict_memory_address_p : memory_address_p);
1927 unsigned int mode_sz = GET_MODE_SIZE (mode);
1929 if (CONSTANT_ADDRESS_P (y))
1932 /* Adjusting an offsettable address involves changing to a narrower mode.
1933 Make sure that's OK. */
1935 if (mode_dependent_address_p (y))
1938 /* ??? How much offset does an offsettable BLKmode reference need?
1939 Clearly that depends on the situation in which it's being used.
1940 However, the current situation in which we test 0xffffffff is
1941 less than ideal. Caveat user. */
1943 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
1945 /* If the expression contains a constant term,
1946 see if it remains valid when max possible offset is added. */
1948 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1953 *y2 = plus_constant (*y2, mode_sz - 1);
1954 /* Use QImode because an odd displacement may be automatically invalid
1955 for any wider mode. But it should be valid for a single byte. */
1956 good = (*addressp) (QImode, y);
1958 /* In any case, restore old contents of memory. */
1963 if (GET_RTX_CLASS (ycode) == 'a')
1966 /* The offset added here is chosen as the maximum offset that
1967 any instruction could need to add when operating on something
1968 of the specified mode. We assume that if Y and Y+c are
1969 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1970 go inside a LO_SUM here, so we do so as well. */
1971 if (GET_CODE (y) == LO_SUM
1973 && mode_sz <= GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)
1974 z = gen_rtx_LO_SUM (GET_MODE (y), XEXP (y, 0),
1975 plus_constant (XEXP (y, 1), mode_sz - 1));
1977 z = plus_constant (y, mode_sz - 1);
1979 /* Use QImode because an odd displacement may be automatically invalid
1980 for any wider mode. But it should be valid for a single byte. */
1981 return (*addressp) (QImode, z);
1984 /* Return 1 if ADDR is an address-expression whose effect depends
1985 on the mode of the memory reference it is used in.
1987 Autoincrement addressing is a typical example of mode-dependence
1988 because the amount of the increment depends on the mode. */
1991 mode_dependent_address_p (addr)
1992 rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
1994 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
1996 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1997 win: ATTRIBUTE_UNUSED_LABEL
2001 /* Return 1 if OP is a general operand
2002 other than a memory ref with a mode dependent address. */
2005 mode_independent_operand (op, mode)
2006 enum machine_mode mode;
2011 if (! general_operand (op, mode))
2014 if (GET_CODE (op) != MEM)
2017 addr = XEXP (op, 0);
2018 GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
2020 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
2021 lose: ATTRIBUTE_UNUSED_LABEL
2025 /* Like extract_insn, but save insn extracted and don't extract again, when
2026 called again for the same insn expecting that recog_data still contain the
2027 valid information. This is used primary by gen_attr infrastructure that
2028 often does extract insn again and again. */
2030 extract_insn_cached (insn)
2033 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2035 extract_insn (insn);
2036 recog_data.insn = insn;
2038 /* Do cached extract_insn, constrain_operand and complain about failures.
2039 Used by insn_attrtab. */
2041 extract_constrain_insn_cached (insn)
2044 extract_insn_cached (insn);
2045 if (which_alternative == -1
2046 && !constrain_operands (reload_completed))
2047 fatal_insn_not_found (insn);
2049 /* Do cached constrain_operand and complain about failures. */
2051 constrain_operands_cached (strict)
2054 if (which_alternative == -1)
2055 return constrain_operands (strict);
2060 /* Analyze INSN and fill in recog_data. */
2069 rtx body = PATTERN (insn);
2071 recog_data.insn = NULL;
2072 recog_data.n_operands = 0;
2073 recog_data.n_alternatives = 0;
2074 recog_data.n_dups = 0;
2075 which_alternative = -1;
2077 switch (GET_CODE (body))
2087 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2092 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2093 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2094 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
2100 recog_data.n_operands = noperands = asm_noperands (body);
2103 /* This insn is an `asm' with operands. */
2105 /* expand_asm_operands makes sure there aren't too many operands. */
2106 if (noperands > MAX_RECOG_OPERANDS)
2109 /* Now get the operand values and constraints out of the insn. */
2110 decode_asm_operands (body, recog_data.operand,
2111 recog_data.operand_loc,
2112 recog_data.constraints,
2113 recog_data.operand_mode);
2116 const char *p = recog_data.constraints[0];
2117 recog_data.n_alternatives = 1;
2119 recog_data.n_alternatives += (*p++ == ',');
2123 fatal_insn_not_found (insn);
2127 /* Ordinary insn: recognize it, get the operands via insn_extract
2128 and get the constraints. */
2130 icode = recog_memoized (insn);
2132 fatal_insn_not_found (insn);
2134 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2135 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2136 recog_data.n_dups = insn_data[icode].n_dups;
2138 insn_extract (insn);
2140 for (i = 0; i < noperands; i++)
2142 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2143 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2144 /* VOIDmode match_operands gets mode from their real operand. */
2145 if (recog_data.operand_mode[i] == VOIDmode)
2146 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2149 for (i = 0; i < noperands; i++)
2150 recog_data.operand_type[i]
2151 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2152 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2155 if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES)
2159 /* After calling extract_insn, you can use this function to extract some
2160 information from the constraint strings into a more usable form.
2161 The collected data is stored in recog_op_alt. */
2163 preprocess_constraints ()
2167 memset (recog_op_alt, 0, sizeof recog_op_alt);
2168 for (i = 0; i < recog_data.n_operands; i++)
2171 struct operand_alternative *op_alt;
2172 const char *p = recog_data.constraints[i];
2174 op_alt = recog_op_alt[i];
2176 for (j = 0; j < recog_data.n_alternatives; j++)
2178 op_alt[j].class = NO_REGS;
2179 op_alt[j].constraint = p;
2180 op_alt[j].matches = -1;
2181 op_alt[j].matched = -1;
2183 if (*p == '\0' || *p == ',')
2185 op_alt[j].anything_ok = 1;
2195 while (c != ',' && c != '\0');
2196 if (c == ',' || c == '\0')
2201 case '=': case '+': case '*': case '%':
2202 case 'E': case 'F': case 'G': case 'H':
2203 case 's': case 'i': case 'n':
2204 case 'I': case 'J': case 'K': case 'L':
2205 case 'M': case 'N': case 'O': case 'P':
2206 /* These don't say anything we care about. */
2210 op_alt[j].reject += 6;
2213 op_alt[j].reject += 600;
2216 op_alt[j].earlyclobber = 1;
2219 case '0': case '1': case '2': case '3': case '4':
2220 case '5': case '6': case '7': case '8': case '9':
2223 op_alt[j].matches = strtoul (p - 1, &end, 10);
2224 recog_op_alt[op_alt[j].matches][j].matched = i;
2230 op_alt[j].memory_ok = 1;
2233 op_alt[j].decmem_ok = 1;
2236 op_alt[j].incmem_ok = 1;
2239 op_alt[j].nonoffmem_ok = 1;
2242 op_alt[j].offmem_ok = 1;
2245 op_alt[j].anything_ok = 1;
2249 op_alt[j].is_address = 1;
2250 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class]
2251 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
2255 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS];
2259 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)];
2267 /* Check the operands of an insn against the insn's operand constraints
2268 and return 1 if they are valid.
2269 The information about the insn's operands, constraints, operand modes
2270 etc. is obtained from the global variables set up by extract_insn.
2272 WHICH_ALTERNATIVE is set to a number which indicates which
2273 alternative of constraints was matched: 0 for the first alternative,
2274 1 for the next, etc.
2276 In addition, when two operands are match
2277 and it happens that the output operand is (reg) while the
2278 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2279 make the output operand look like the input.
2280 This is because the output operand is the one the template will print.
2282 This is used in final, just before printing the assembler code and by
2283 the routines that determine an insn's attribute.
2285 If STRICT is a positive non-zero value, it means that we have been
2286 called after reload has been completed. In that case, we must
2287 do all checks strictly. If it is zero, it means that we have been called
2288 before reload has completed. In that case, we first try to see if we can
2289 find an alternative that matches strictly. If not, we try again, this
2290 time assuming that reload will fix up the insn. This provides a "best
2291 guess" for the alternative and is used to compute attributes of insns prior
2292 to reload. A negative value of STRICT is used for this internal call. */
2300 constrain_operands (strict)
2303 const char *constraints[MAX_RECOG_OPERANDS];
2304 int matching_operands[MAX_RECOG_OPERANDS];
2305 int earlyclobber[MAX_RECOG_OPERANDS];
2308 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2309 int funny_match_index;
2311 which_alternative = 0;
2312 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2315 for (c = 0; c < recog_data.n_operands; c++)
2317 constraints[c] = recog_data.constraints[c];
2318 matching_operands[c] = -1;
2325 funny_match_index = 0;
2327 for (opno = 0; opno < recog_data.n_operands; opno++)
2329 rtx op = recog_data.operand[opno];
2330 enum machine_mode mode = GET_MODE (op);
2331 const char *p = constraints[opno];
2336 earlyclobber[opno] = 0;
2338 /* A unary operator may be accepted by the predicate, but it
2339 is irrelevant for matching constraints. */
2340 if (GET_RTX_CLASS (GET_CODE (op)) == '1')
2343 if (GET_CODE (op) == SUBREG)
2345 if (GET_CODE (SUBREG_REG (op)) == REG
2346 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2347 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)),
2348 GET_MODE (SUBREG_REG (op)),
2351 op = SUBREG_REG (op);
2354 /* An empty constraint or empty alternative
2355 allows anything which matched the pattern. */
2356 if (*p == 0 || *p == ',')
2359 while (*p && (c = *p++) != ',')
2362 case '?': case '!': case '*': case '%':
2367 /* Ignore rest of this alternative as far as
2368 constraint checking is concerned. */
2369 while (*p && *p != ',')
2374 earlyclobber[opno] = 1;
2377 case '0': case '1': case '2': case '3': case '4':
2378 case '5': case '6': case '7': case '8': case '9':
2380 /* This operand must be the same as a previous one.
2381 This kind of constraint is used for instructions such
2382 as add when they take only two operands.
2384 Note that the lower-numbered operand is passed first.
2386 If we are not testing strictly, assume that this
2387 constraint will be satisfied. */
2392 match = strtoul (p - 1, &end, 10);
2399 rtx op1 = recog_data.operand[match];
2400 rtx op2 = recog_data.operand[opno];
2402 /* A unary operator may be accepted by the predicate,
2403 but it is irrelevant for matching constraints. */
2404 if (GET_RTX_CLASS (GET_CODE (op1)) == '1')
2405 op1 = XEXP (op1, 0);
2406 if (GET_RTX_CLASS (GET_CODE (op2)) == '1')
2407 op2 = XEXP (op2, 0);
2409 val = operands_match_p (op1, op2);
2412 matching_operands[opno] = match;
2413 matching_operands[match] = opno;
2418 /* If output is *x and input is *--x, arrange later
2419 to change the output to *--x as well, since the
2420 output op is the one that will be printed. */
2421 if (val == 2 && strict > 0)
2423 funny_match[funny_match_index].this = opno;
2424 funny_match[funny_match_index++].other = match;
2430 /* p is used for address_operands. When we are called by
2431 gen_reload, no one will have checked that the address is
2432 strictly valid, i.e., that all pseudos requiring hard regs
2433 have gotten them. */
2435 || (strict_memory_address_p (recog_data.operand_mode[opno],
2440 /* No need to check general_operand again;
2441 it was done in insn-recog.c. */
2443 /* Anything goes unless it is a REG and really has a hard reg
2444 but the hard reg is not in the class GENERAL_REGS. */
2446 || GENERAL_REGS == ALL_REGS
2447 || GET_CODE (op) != REG
2448 || (reload_in_progress
2449 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2450 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2455 /* This is used for a MATCH_SCRATCH in the cases when
2456 we don't actually need anything. So anything goes
2462 if (GET_CODE (op) == MEM
2463 /* Before reload, accept what reload can turn into mem. */
2464 || (strict < 0 && CONSTANT_P (op))
2465 /* During reload, accept a pseudo */
2466 || (reload_in_progress && GET_CODE (op) == REG
2467 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2472 if (GET_CODE (op) == MEM
2473 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
2474 || GET_CODE (XEXP (op, 0)) == POST_DEC))
2479 if (GET_CODE (op) == MEM
2480 && (GET_CODE (XEXP (op, 0)) == PRE_INC
2481 || GET_CODE (XEXP (op, 0)) == POST_INC))
2486 #ifndef REAL_ARITHMETIC
2487 /* Match any CONST_DOUBLE, but only if
2488 we can examine the bits of it reliably. */
2489 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2490 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
2491 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
2494 if (GET_CODE (op) == CONST_DOUBLE)
2499 if (GET_CODE (op) == CONST_DOUBLE)
2505 if (GET_CODE (op) == CONST_DOUBLE
2506 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
2511 if (GET_CODE (op) == CONST_INT
2512 || (GET_CODE (op) == CONST_DOUBLE
2513 && GET_MODE (op) == VOIDmode))
2516 if (CONSTANT_P (op))
2521 if (GET_CODE (op) == CONST_INT
2522 || (GET_CODE (op) == CONST_DOUBLE
2523 && GET_MODE (op) == VOIDmode))
2535 if (GET_CODE (op) == CONST_INT
2536 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
2541 if (GET_CODE (op) == MEM
2542 && ((strict > 0 && ! offsettable_memref_p (op))
2544 && !(CONSTANT_P (op) || GET_CODE (op) == MEM))
2545 || (reload_in_progress
2546 && !(GET_CODE (op) == REG
2547 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
2552 if ((strict > 0 && offsettable_memref_p (op))
2553 || (strict == 0 && offsettable_nonstrict_memref_p (op))
2554 /* Before reload, accept what reload can handle. */
2556 && (CONSTANT_P (op) || GET_CODE (op) == MEM))
2557 /* During reload, accept a pseudo */
2558 || (reload_in_progress && GET_CODE (op) == REG
2559 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2565 enum reg_class class;
2567 class = (c == 'r' ? GENERAL_REGS : REG_CLASS_FROM_LETTER (c));
2568 if (class != NO_REGS)
2572 && GET_CODE (op) == REG
2573 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2574 || (strict == 0 && GET_CODE (op) == SCRATCH)
2575 || (GET_CODE (op) == REG
2576 && reg_fits_class_p (op, class, offset, mode)))
2579 #ifdef EXTRA_CONSTRAINT
2580 else if (EXTRA_CONSTRAINT (op, c))
2587 constraints[opno] = p;
2588 /* If this operand did not win somehow,
2589 this alternative loses. */
2593 /* This alternative won; the operands are ok.
2594 Change whichever operands this alternative says to change. */
2599 /* See if any earlyclobber operand conflicts with some other
2603 for (eopno = 0; eopno < recog_data.n_operands; eopno++)
2604 /* Ignore earlyclobber operands now in memory,
2605 because we would often report failure when we have
2606 two memory operands, one of which was formerly a REG. */
2607 if (earlyclobber[eopno]
2608 && GET_CODE (recog_data.operand[eopno]) == REG)
2609 for (opno = 0; opno < recog_data.n_operands; opno++)
2610 if ((GET_CODE (recog_data.operand[opno]) == MEM
2611 || recog_data.operand_type[opno] != OP_OUT)
2613 /* Ignore things like match_operator operands. */
2614 && *recog_data.constraints[opno] != 0
2615 && ! (matching_operands[opno] == eopno
2616 && operands_match_p (recog_data.operand[opno],
2617 recog_data.operand[eopno]))
2618 && ! safe_from_earlyclobber (recog_data.operand[opno],
2619 recog_data.operand[eopno]))
2624 while (--funny_match_index >= 0)
2626 recog_data.operand[funny_match[funny_match_index].other]
2627 = recog_data.operand[funny_match[funny_match_index].this];
2634 which_alternative++;
2636 while (which_alternative < recog_data.n_alternatives);
2638 which_alternative = -1;
2639 /* If we are about to reject this, but we are not to test strictly,
2640 try a very loose test. Only return failure if it fails also. */
2642 return constrain_operands (-1);
2647 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2648 is a hard reg in class CLASS when its regno is offset by OFFSET
2649 and changed to mode MODE.
2650 If REG occupies multiple hard regs, all of them must be in CLASS. */
2653 reg_fits_class_p (operand, class, offset, mode)
2655 enum reg_class class;
2657 enum machine_mode mode;
2659 int regno = REGNO (operand);
2660 if (regno < FIRST_PSEUDO_REGISTER
2661 && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2666 for (sr = HARD_REGNO_NREGS (regno, mode) - 1;
2668 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2677 /* Split single instruction. Helper function for split_all_insns.
2678 Return last insn in the sequence if successful, or NULL if unsuccessful. */
2686 /* Don't split no-op move insns. These should silently
2687 disappear later in final. Splitting such insns would
2688 break the code that handles REG_NO_CONFLICT blocks. */
2690 else if ((set = single_set (insn)) != NULL && set_noop_p (set))
2692 /* Nops get in the way while scheduling, so delete them
2693 now if register allocation has already been done. It
2694 is too risky to try to do this before register
2695 allocation, and there are unlikely to be very many
2696 nops then anyways. */
2697 if (reload_completed)
2699 PUT_CODE (insn, NOTE);
2700 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2701 NOTE_SOURCE_FILE (insn) = 0;
2706 /* Split insns here to get max fine-grain parallelism. */
2707 rtx first = PREV_INSN (insn);
2708 rtx last = try_split (PATTERN (insn), insn, 1);
2712 /* try_split returns the NOTE that INSN became. */
2713 PUT_CODE (insn, NOTE);
2714 NOTE_SOURCE_FILE (insn) = 0;
2715 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2717 /* ??? Coddle to md files that generate subregs in post-
2718 reload splitters instead of computing the proper
2720 if (reload_completed && first != last)
2722 first = NEXT_INSN (first);
2726 cleanup_subreg_operands (first);
2729 first = NEXT_INSN (first);
2737 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2740 split_all_insns (upd_life)
2747 blocks = sbitmap_alloc (n_basic_blocks);
2748 sbitmap_zero (blocks);
2751 for (i = n_basic_blocks - 1; i >= 0; --i)
2753 basic_block bb = BASIC_BLOCK (i);
2756 for (insn = bb->head; insn ; insn = next)
2760 /* Can't use `next_real_insn' because that might go across
2761 CODE_LABELS and short-out basic blocks. */
2762 next = NEXT_INSN (insn);
2763 last = split_insn (insn);
2766 /* The split sequence may include barrier, but the
2767 BB boundary we are interested in will be set to previous
2770 while (GET_CODE (last) == BARRIER)
2771 last = PREV_INSN (last);
2772 SET_BIT (blocks, i);
2777 if (insn == bb->end)
2787 find_many_sub_basic_blocks (blocks);
2790 if (changed && upd_life)
2792 count_or_remove_death_notes (blocks, 1);
2793 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
2795 #ifdef ENABLE_CHECKING
2796 verify_flow_info ();
2799 sbitmap_free (blocks);
2802 /* Same as split_all_insns, but do not expect CFG to be available.
2803 Used by machine depedent reorg passes. */
2806 split_all_insns_noflow ()
2810 for (insn = get_insns (); insn; insn = next)
2812 next = NEXT_INSN (insn);
2818 #ifdef HAVE_peephole2
2819 struct peep2_insn_data
2825 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
2826 static int peep2_current;
2828 /* A non-insn marker indicating the last insn of the block.
2829 The live_before regset for this element is correct, indicating
2830 global_live_at_end for the block. */
2831 #define PEEP2_EOB pc_rtx
2833 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2834 does not exist. Used by the recognizer to find the next insn to match
2835 in a multi-insn pattern. */
2841 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2845 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2846 n -= MAX_INSNS_PER_PEEP2 + 1;
2848 if (peep2_insn_data[n].insn == PEEP2_EOB)
2850 return peep2_insn_data[n].insn;
2853 /* Return true if REGNO is dead before the Nth non-note insn
2857 peep2_regno_dead_p (ofs, regno)
2861 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2864 ofs += peep2_current;
2865 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2866 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2868 if (peep2_insn_data[ofs].insn == NULL_RTX)
2871 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
2874 /* Similarly for a REG. */
2877 peep2_reg_dead_p (ofs, reg)
2883 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2886 ofs += peep2_current;
2887 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2888 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2890 if (peep2_insn_data[ofs].insn == NULL_RTX)
2893 regno = REGNO (reg);
2894 n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2896 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n))
2901 /* Try to find a hard register of mode MODE, matching the register class in
2902 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2903 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2904 in which case the only condition is that the register must be available
2905 before CURRENT_INSN.
2906 Registers that already have bits set in REG_SET will not be considered.
2908 If an appropriate register is available, it will be returned and the
2909 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2913 peep2_find_free_register (from, to, class_str, mode, reg_set)
2915 const char *class_str;
2916 enum machine_mode mode;
2917 HARD_REG_SET *reg_set;
2919 static int search_ofs;
2920 enum reg_class class;
2924 if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1)
2927 from += peep2_current;
2928 if (from >= MAX_INSNS_PER_PEEP2 + 1)
2929 from -= MAX_INSNS_PER_PEEP2 + 1;
2930 to += peep2_current;
2931 if (to >= MAX_INSNS_PER_PEEP2 + 1)
2932 to -= MAX_INSNS_PER_PEEP2 + 1;
2934 if (peep2_insn_data[from].insn == NULL_RTX)
2936 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
2940 HARD_REG_SET this_live;
2942 if (++from >= MAX_INSNS_PER_PEEP2 + 1)
2944 if (peep2_insn_data[from].insn == NULL_RTX)
2946 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
2947 IOR_HARD_REG_SET (live, this_live);
2950 class = (class_str[0] == 'r' ? GENERAL_REGS
2951 : REG_CLASS_FROM_LETTER (class_str[0]));
2953 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2955 int raw_regno, regno, success, j;
2957 /* Distribute the free registers as much as possible. */
2958 raw_regno = search_ofs + i;
2959 if (raw_regno >= FIRST_PSEUDO_REGISTER)
2960 raw_regno -= FIRST_PSEUDO_REGISTER;
2961 #ifdef REG_ALLOC_ORDER
2962 regno = reg_alloc_order[raw_regno];
2967 /* Don't allocate fixed registers. */
2968 if (fixed_regs[regno])
2970 /* Make sure the register is of the right class. */
2971 if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno))
2973 /* And can support the mode we need. */
2974 if (! HARD_REGNO_MODE_OK (regno, mode))
2976 /* And that we don't create an extra save/restore. */
2977 if (! call_used_regs[regno] && ! regs_ever_live[regno])
2979 /* And we don't clobber traceback for noreturn functions. */
2980 if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM)
2981 && (! reload_completed || frame_pointer_needed))
2985 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
2987 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
2988 || TEST_HARD_REG_BIT (live, regno + j))
2996 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
2997 SET_HARD_REG_BIT (*reg_set, regno + j);
2999 /* Start the next search with the next register. */
3000 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
3002 search_ofs = raw_regno;
3004 return gen_rtx_REG (mode, regno);
3012 /* Perform the peephole2 optimization pass. */
3015 peephole2_optimize (dump_file)
3016 FILE *dump_file ATTRIBUTE_UNUSED;
3018 regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2];
3022 #ifdef HAVE_conditional_execution
3026 bool do_cleanup_cfg = false;
3027 bool do_rebuild_jump_labels = false;
3029 /* Initialize the regsets we're going to use. */
3030 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3031 peep2_insn_data[i].live_before = INITIALIZE_REG_SET (rs_heads[i]);
3032 live = INITIALIZE_REG_SET (rs_heads[i]);
3034 #ifdef HAVE_conditional_execution
3035 blocks = sbitmap_alloc (n_basic_blocks);
3036 sbitmap_zero (blocks);
3039 count_or_remove_death_notes (NULL, 1);
3042 for (b = n_basic_blocks - 1; b >= 0; --b)
3044 basic_block bb = BASIC_BLOCK (b);
3045 struct propagate_block_info *pbi;
3047 /* Indicate that all slots except the last holds invalid data. */
3048 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3049 peep2_insn_data[i].insn = NULL_RTX;
3051 /* Indicate that the last slot contains live_after data. */
3052 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3053 peep2_current = MAX_INSNS_PER_PEEP2;
3055 /* Start up propagation. */
3056 COPY_REG_SET (live, bb->global_live_at_end);
3057 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3059 #ifdef HAVE_conditional_execution
3060 pbi = init_propagate_block_info (bb, live, NULL, NULL, 0);
3062 pbi = init_propagate_block_info (bb, live, NULL, NULL, PROP_DEATH_NOTES);
3065 for (insn = bb->end; ; insn = prev)
3067 prev = PREV_INSN (insn);
3070 rtx try, before_try, x;
3074 /* Record this insn. */
3075 if (--peep2_current < 0)
3076 peep2_current = MAX_INSNS_PER_PEEP2;
3077 peep2_insn_data[peep2_current].insn = insn;
3078 propagate_one_insn (pbi, insn);
3079 COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
3081 /* Match the peephole. */
3082 try = peephole2_insns (PATTERN (insn), insn, &match_len);
3085 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3086 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3087 cfg-related call notes. */
3088 for (i = 0; i <= match_len; ++i)
3091 rtx old_insn, new_insn, note;
3093 j = i + peep2_current;
3094 if (j >= MAX_INSNS_PER_PEEP2 + 1)
3095 j -= MAX_INSNS_PER_PEEP2 + 1;
3096 old_insn = peep2_insn_data[j].insn;
3097 if (GET_CODE (old_insn) != CALL_INSN)
3100 new_insn = NULL_RTX;
3101 if (GET_CODE (try) == SEQUENCE)
3102 for (k = XVECLEN (try, 0) - 1; k >= 0; k--)
3104 rtx x = XVECEXP (try, 0, k);
3105 if (GET_CODE (x) == CALL_INSN)
3111 else if (GET_CODE (try) == CALL_INSN)
3116 CALL_INSN_FUNCTION_USAGE (new_insn)
3117 = CALL_INSN_FUNCTION_USAGE (old_insn);
3119 for (note = REG_NOTES (old_insn);
3121 note = XEXP (note, 1))
3122 switch (REG_NOTE_KIND (note))
3126 case REG_ALWAYS_RETURN:
3127 REG_NOTES (new_insn)
3128 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note),
3130 REG_NOTES (new_insn));
3132 /* Discard all other reg notes. */
3136 /* Croak if there is another call in the sequence. */
3137 while (++i <= match_len)
3139 j = i + peep2_current;
3140 if (j >= MAX_INSNS_PER_PEEP2 + 1)
3141 j -= MAX_INSNS_PER_PEEP2 + 1;
3142 old_insn = peep2_insn_data[j].insn;
3143 if (GET_CODE (old_insn) == CALL_INSN)
3149 i = match_len + peep2_current;
3150 if (i >= MAX_INSNS_PER_PEEP2 + 1)
3151 i -= MAX_INSNS_PER_PEEP2 + 1;
3153 note = find_reg_note (peep2_insn_data[i].insn,
3154 REG_EH_REGION, NULL_RTX);
3156 /* Replace the old sequence with the new. */
3157 try = emit_insn_after (try, peep2_insn_data[i].insn);
3158 before_try = PREV_INSN (insn);
3159 delete_insn_chain (insn, peep2_insn_data[i].insn);
3161 /* Re-insert the EH_REGION notes. */
3166 for (eh_edge = bb->succ; eh_edge
3167 ; eh_edge = eh_edge->succ_next)
3168 if (eh_edge->flags & EDGE_EH)
3171 for (x = try ; x != before_try ; x = PREV_INSN (x))
3172 if (GET_CODE (x) == CALL_INSN
3173 || (flag_non_call_exceptions
3174 && may_trap_p (PATTERN (x))
3175 && !find_reg_note (x, REG_EH_REGION, NULL)))
3178 = gen_rtx_EXPR_LIST (REG_EH_REGION,
3182 if (x != bb->end && eh_edge)
3187 nfte = split_block (bb, x);
3188 flags = EDGE_EH | EDGE_ABNORMAL;
3189 if (GET_CODE (x) == CALL_INSN)
3190 flags |= EDGE_ABNORMAL_CALL;
3191 nehe = make_edge (nfte->src, eh_edge->dest,
3194 nehe->probability = eh_edge->probability;
3196 = REG_BR_PROB_BASE - nehe->probability;
3198 do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3199 #ifdef HAVE_conditional_execution
3200 SET_BIT (blocks, nfte->dest->index);
3208 /* Converting possibly trapping insn to non-trapping is
3209 possible. Zap dummy outgoing edges. */
3210 do_cleanup_cfg |= purge_dead_edges (bb);
3213 #ifdef HAVE_conditional_execution
3214 /* With conditional execution, we cannot back up the
3215 live information so easily, since the conditional
3216 death data structures are not so self-contained.
3217 So record that we've made a modification to this
3218 block and update life information at the end. */
3219 SET_BIT (blocks, b);
3222 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3223 peep2_insn_data[i].insn = NULL_RTX;
3224 peep2_insn_data[peep2_current].insn = PEEP2_EOB;
3226 /* Back up lifetime information past the end of the
3227 newly created sequence. */
3228 if (++i >= MAX_INSNS_PER_PEEP2 + 1)
3230 COPY_REG_SET (live, peep2_insn_data[i].live_before);
3232 /* Update life information for the new sequence. */
3239 i = MAX_INSNS_PER_PEEP2;
3240 peep2_insn_data[i].insn = x;
3241 propagate_one_insn (pbi, x);
3242 COPY_REG_SET (peep2_insn_data[i].live_before, live);
3248 /* ??? Should verify that LIVE now matches what we
3249 had before the new sequence. */
3254 /* If we generated a jump instruction, it won't have
3255 JUMP_LABEL set. Recompute after we're done. */
3256 for (x = try; x != before_try; x = PREV_INSN (x))
3257 if (GET_CODE (x) == JUMP_INSN)
3259 do_rebuild_jump_labels = true;
3265 if (insn == bb->head)
3269 free_propagate_block_info (pbi);
3272 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3273 FREE_REG_SET (peep2_insn_data[i].live_before);
3274 FREE_REG_SET (live);
3276 if (do_rebuild_jump_labels)
3277 rebuild_jump_labels (get_insns ());
3279 /* If we eliminated EH edges, we may be able to merge blocks. Further,
3280 we've changed global life since exception handlers are no longer
3285 update_life_info (0, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
3287 #ifdef HAVE_conditional_execution
3290 count_or_remove_death_notes (blocks, 1);
3291 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
3293 sbitmap_free (blocks);
3296 #endif /* HAVE_peephole2 */