1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
41 #include "gdb/sim-arm.h"
44 #include "coff/internal.h"
47 #include "gdb_assert.h"
51 /* Each OS has a different mechanism for accessing the various
52 registers stored in the sigcontext structure.
54 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
55 function pointer) which may be used to determine the addresses
56 of the various saved registers in the sigcontext structure.
58 For the ARM target, there are three parameters to this function.
59 The first is the pc value of the frame under consideration, the
60 second the stack pointer of this frame, and the last is the
61 register number to fetch.
63 If the tm.h file does not define this macro, then it's assumed that
64 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
67 When it comes time to multi-arching this code, see the identically
68 named machinery in ia64-tdep.c for an example of how it could be
69 done. It should not be necessary to modify the code below where
70 this macro is used. */
72 #ifdef SIGCONTEXT_REGISTER_ADDRESS
73 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
74 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
77 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
78 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
81 /* Macros for setting and testing a bit in a minimal symbol that marks
82 it as Thumb function. The MSB of the minimal symbol's "info" field
83 is used for this purpose.
85 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
86 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
88 #define MSYMBOL_SET_SPECIAL(msym) \
89 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
92 #define MSYMBOL_IS_SPECIAL(msym) \
93 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
95 /* The list of available "set arm ..." and "show arm ..." commands. */
96 static struct cmd_list_element *setarmcmdlist = NULL;
97 static struct cmd_list_element *showarmcmdlist = NULL;
99 /* The type of floating-point to use. Keep this in sync with enum
100 arm_float_model, and the help string in _initialize_arm_tdep. */
101 static const char *fp_model_strings[] =
110 /* A variable that can be configured by the user. */
111 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
112 static const char *current_fp_model = "auto";
114 /* Number of different reg name sets (options). */
115 static int num_disassembly_options;
117 /* We have more registers than the disassembler as gdb can print the value
118 of special registers as well.
119 The general register names are overwritten by whatever is being used by
120 the disassembler at the moment. We also adjust the case of cpsr and fps. */
122 /* Initial value: Register names used in ARM's ISA documentation. */
123 static char * arm_register_name_strings[] =
124 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
125 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
126 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
127 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
128 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
129 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
130 "fps", "cpsr" }; /* 24 25 */
131 static char **arm_register_names = arm_register_name_strings;
133 /* Valid register name styles. */
134 static const char **valid_disassembly_styles;
136 /* Disassembly style to use. Default to "std" register names. */
137 static const char *disassembly_style;
138 /* Index to that option in the opcodes table. */
139 static int current_option;
141 /* This is used to keep the bfd arch_info in sync with the disassembly
143 static void set_disassembly_style_sfunc(char *, int,
144 struct cmd_list_element *);
145 static void set_disassembly_style (void);
147 static void convert_from_extended (const struct floatformat *, const void *,
149 static void convert_to_extended (const struct floatformat *, void *,
152 struct arm_prologue_cache
154 /* The stack pointer at the time this frame was created; i.e. the
155 caller's stack pointer when this function was called. It is used
156 to identify this frame. */
159 /* The frame base for this frame is just prev_sp + frame offset -
160 frame size. FRAMESIZE is the size of this stack frame, and
161 FRAMEOFFSET if the initial offset from the stack pointer (this
162 frame's stack pointer, not PREV_SP) to the frame base. */
167 /* The register used to hold the frame pointer for this frame. */
170 /* Saved register offsets. */
171 struct trad_frame_saved_reg *saved_regs;
174 /* Addresses for calling Thumb functions have the bit 0 set.
175 Here are some macros to test, set, or clear bit 0 of addresses. */
176 #define IS_THUMB_ADDR(addr) ((addr) & 1)
177 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
178 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
180 /* Set to true if the 32-bit mode is in use. */
184 /* Determine if the program counter specified in MEMADDR is in a Thumb
188 arm_pc_is_thumb (CORE_ADDR memaddr)
190 struct minimal_symbol *sym;
192 /* If bit 0 of the address is set, assume this is a Thumb address. */
193 if (IS_THUMB_ADDR (memaddr))
196 /* Thumb functions have a "special" bit set in minimal symbols. */
197 sym = lookup_minimal_symbol_by_pc (memaddr);
200 return (MSYMBOL_IS_SPECIAL (sym));
208 /* Remove useless bits from addresses in a running program. */
210 arm_addr_bits_remove (CORE_ADDR val)
213 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
215 return (val & 0x03fffffc);
218 /* When reading symbols, we need to zap the low bit of the address,
219 which may be set to 1 for Thumb functions. */
221 arm_smash_text_address (CORE_ADDR val)
226 /* Immediately after a function call, return the saved pc. Can't
227 always go through the frames for this because on some machines the
228 new frame is not set up until the new function executes some
232 arm_saved_pc_after_call (struct frame_info *frame)
234 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
237 /* Determine whether the function invocation represented by FI has a
238 frame on the stack associated with it. If it does return zero,
239 otherwise return 1. */
242 arm_frameless_function_invocation (struct frame_info *fi)
244 CORE_ADDR func_start, after_prologue;
247 /* Sometimes we have functions that do a little setup (like saving the
248 vN registers with the stmdb instruction, but DO NOT set up a frame.
249 The symbol table will report this as a prologue. However, it is
250 important not to try to parse these partial frames as frames, or we
251 will get really confused.
253 So I will demand 3 instructions between the start & end of the
254 prologue before I call it a real prologue, i.e. at least
259 func_start = (get_frame_func (fi) + FUNCTION_START_OFFSET);
260 after_prologue = SKIP_PROLOGUE (func_start);
262 /* There are some frameless functions whose first two instructions
263 follow the standard APCS form, in which case after_prologue will
264 be func_start + 8. */
266 frameless = (after_prologue < func_start + 12);
270 /* A typical Thumb prologue looks like this:
274 Sometimes the latter instruction may be replaced by:
282 or, on tpcs, like this:
289 There is always one instruction of three classes:
294 When we have found at least one of each class we are done with the prolog.
295 Note that the "sub sp, #NN" before the push does not count.
299 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
301 CORE_ADDR current_pc;
303 bit 0 - push { rlist }
304 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
305 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
309 for (current_pc = pc;
310 current_pc + 2 < func_end && current_pc < pc + 40;
313 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
315 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
317 findmask |= 1; /* push found */
319 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
322 if ((findmask & 1) == 0) /* before push ? */
325 findmask |= 4; /* add/sub sp found */
327 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
329 findmask |= 2; /* setting of r7 found */
331 else if (insn == 0x466f) /* mov r7, sp */
333 findmask |= 2; /* setting of r7 found */
335 else if (findmask == (4+2+1))
337 /* We have found one of each type of prologue instruction */
341 /* Something in the prolog that we don't care about or some
342 instruction from outside the prolog scheduled here for
350 /* Advance the PC across any function entry prologue instructions to
351 reach some "real" code.
353 The APCS (ARM Procedure Call Standard) defines the following
357 [stmfd sp!, {a1,a2,a3,a4}]
358 stmfd sp!, {...,fp,ip,lr,pc}
359 [stfe f7, [sp, #-12]!]
360 [stfe f6, [sp, #-12]!]
361 [stfe f5, [sp, #-12]!]
362 [stfe f4, [sp, #-12]!]
363 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
366 arm_skip_prologue (CORE_ADDR pc)
370 CORE_ADDR func_addr, func_end = 0;
372 struct symtab_and_line sal;
374 /* If we're in a dummy frame, don't even try to skip the prologue. */
375 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
378 /* See what the symbol table says. */
380 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
384 /* Found a function. */
385 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
386 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
388 /* Don't use this trick for assembly source files. */
389 sal = find_pc_line (func_addr, 0);
390 if ((sal.line != 0) && (sal.end < func_end))
395 /* Check if this is Thumb code. */
396 if (arm_pc_is_thumb (pc))
397 return thumb_skip_prologue (pc, func_end);
399 /* Can't find the prologue end in the symbol table, try it the hard way
400 by disassembling the instructions. */
402 /* Like arm_scan_prologue, stop no later than pc + 64. */
403 if (func_end == 0 || func_end > pc + 64)
406 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
408 inst = read_memory_integer (skip_pc, 4);
410 /* "mov ip, sp" is no longer a required part of the prologue. */
411 if (inst == 0xe1a0c00d) /* mov ip, sp */
414 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
417 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
420 /* Some prologues begin with "str lr, [sp, #-4]!". */
421 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
424 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
427 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
430 /* Any insns after this point may float into the code, if it makes
431 for better instruction scheduling, so we skip them only if we
432 find them, but still consider the function to be frame-ful. */
434 /* We may have either one sfmfd instruction here, or several stfe
435 insns, depending on the version of floating point code we
437 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
440 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
443 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
446 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
449 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
450 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
451 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
454 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
455 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
456 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
459 /* Un-recognized instruction; stop scanning. */
463 return skip_pc; /* End of prologue */
467 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
468 This function decodes a Thumb function prologue to determine:
469 1) the size of the stack frame
470 2) which registers are saved on it
471 3) the offsets of saved regs
472 4) the offset from the stack pointer to the frame pointer
474 A typical Thumb function prologue would create this stack frame
475 (offsets relative to FP)
476 old SP -> 24 stack parameters
479 R7 -> 0 local variables (16 bytes)
480 SP -> -12 additional stack space (12 bytes)
481 The frame size would thus be 36 bytes, and the frame offset would be
482 12 bytes. The frame register is R7.
484 The comments for thumb_skip_prolog() describe the algorithm we use
485 to detect the end of the prolog. */
489 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
491 CORE_ADDR prologue_start;
492 CORE_ADDR prologue_end;
493 CORE_ADDR current_pc;
494 /* Which register has been copied to register n? */
497 bit 0 - push { rlist }
498 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
499 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
504 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
506 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
508 if (sal.line == 0) /* no line info, use current PC */
509 prologue_end = prev_pc;
510 else if (sal.end < prologue_end) /* next line begins after fn end */
511 prologue_end = sal.end; /* (probably means no prologue) */
514 /* We're in the boondocks: allow for
515 16 pushes, an add, and "mv fp,sp". */
516 prologue_end = prologue_start + 40;
518 prologue_end = min (prologue_end, prev_pc);
520 /* Initialize the saved register map. When register H is copied to
521 register L, we will put H in saved_reg[L]. */
522 for (i = 0; i < 16; i++)
525 /* Search the prologue looking for instructions that set up the
526 frame pointer, adjust the stack pointer, and save registers.
527 Do this until all basic prolog instructions are found. */
529 cache->framesize = 0;
530 for (current_pc = prologue_start;
531 (current_pc < prologue_end) && ((findmask & 7) != 7);
538 insn = read_memory_unsigned_integer (current_pc, 2);
540 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
543 findmask |= 1; /* push found */
544 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
545 whether to save LR (R14). */
546 mask = (insn & 0xff) | ((insn & 0x100) << 6);
548 /* Calculate offsets of saved R0-R7 and LR. */
549 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
550 if (mask & (1 << regno))
552 cache->framesize += 4;
553 cache->saved_regs[saved_reg[regno]].addr = -cache->framesize;
554 /* Reset saved register map. */
555 saved_reg[regno] = regno;
558 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
561 if ((findmask & 1) == 0) /* before push? */
564 findmask |= 4; /* add/sub sp found */
566 offset = (insn & 0x7f) << 2; /* get scaled offset */
567 if (insn & 0x80) /* is it signed? (==subtracting) */
569 cache->frameoffset += offset;
572 cache->framesize -= offset;
574 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
576 findmask |= 2; /* setting of r7 found */
577 cache->framereg = THUMB_FP_REGNUM;
578 /* get scaled offset */
579 cache->frameoffset = (insn & 0xff) << 2;
581 else if (insn == 0x466f) /* mov r7, sp */
583 findmask |= 2; /* setting of r7 found */
584 cache->framereg = THUMB_FP_REGNUM;
585 cache->frameoffset = 0;
586 saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
588 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
590 int lo_reg = insn & 7; /* dest. register (r0-r7) */
591 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
592 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
595 /* Something in the prolog that we don't care about or some
596 instruction from outside the prolog scheduled here for
602 /* This function decodes an ARM function prologue to determine:
603 1) the size of the stack frame
604 2) which registers are saved on it
605 3) the offsets of saved regs
606 4) the offset from the stack pointer to the frame pointer
607 This information is stored in the "extra" fields of the frame_info.
609 There are two basic forms for the ARM prologue. The fixed argument
610 function call will look like:
613 stmfd sp!, {fp, ip, lr, pc}
617 Which would create this stack frame (offsets relative to FP):
618 IP -> 4 (caller's stack)
619 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
620 -4 LR (return address in caller)
621 -8 IP (copy of caller's SP)
623 SP -> -28 Local variables
625 The frame size would thus be 32 bytes, and the frame offset would be
626 28 bytes. The stmfd call can also save any of the vN registers it
627 plans to use, which increases the frame size accordingly.
629 Note: The stored PC is 8 off of the STMFD instruction that stored it
630 because the ARM Store instructions always store PC + 8 when you read
633 A variable argument function call will look like:
636 stmfd sp!, {a1, a2, a3, a4}
637 stmfd sp!, {fp, ip, lr, pc}
640 Which would create this stack frame (offsets relative to FP):
641 IP -> 20 (caller's stack)
646 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
647 -4 LR (return address in caller)
648 -8 IP (copy of caller's SP)
650 SP -> -28 Local variables
652 The frame size would thus be 48 bytes, and the frame offset would be
655 There is another potential complication, which is that the optimizer
656 will try to separate the store of fp in the "stmfd" instruction from
657 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
658 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
660 Also, note, the original version of the ARM toolchain claimed that there
663 instruction at the end of the prologue. I have never seen GCC produce
664 this, and the ARM docs don't mention it. We still test for it below in
670 arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache)
672 int regno, sp_offset, fp_offset, ip_offset;
673 CORE_ADDR prologue_start, prologue_end, current_pc;
674 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
676 /* Assume there is no frame until proven otherwise. */
677 cache->framereg = ARM_SP_REGNUM;
678 cache->framesize = 0;
679 cache->frameoffset = 0;
681 /* Check for Thumb prologue. */
682 if (arm_pc_is_thumb (prev_pc))
684 thumb_scan_prologue (prev_pc, cache);
688 /* Find the function prologue. If we can't find the function in
689 the symbol table, peek in the stack frame to find the PC. */
690 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
692 /* One way to find the end of the prologue (which works well
693 for unoptimized code) is to do the following:
695 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
698 prologue_end = prev_pc;
699 else if (sal.end < prologue_end)
700 prologue_end = sal.end;
702 This mechanism is very accurate so long as the optimizer
703 doesn't move any instructions from the function body into the
704 prologue. If this happens, sal.end will be the last
705 instruction in the first hunk of prologue code just before
706 the first instruction that the scheduler has moved from
707 the body to the prologue.
709 In order to make sure that we scan all of the prologue
710 instructions, we use a slightly less accurate mechanism which
711 may scan more than necessary. To help compensate for this
712 lack of accuracy, the prologue scanning loop below contains
713 several clauses which'll cause the loop to terminate early if
714 an implausible prologue instruction is encountered.
720 is a suitable endpoint since it accounts for the largest
721 possible prologue plus up to five instructions inserted by
724 if (prologue_end > prologue_start + 64)
726 prologue_end = prologue_start + 64; /* See above. */
731 /* We have no symbol information. Our only option is to assume this
732 function has a standard stack frame and the normal frame register.
733 Then, we can find the value of our frame pointer on entrance to
734 the callee (or at the present moment if this is the innermost frame).
735 The value stored there should be the address of the stmfd + 8. */
737 LONGEST return_value;
739 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
740 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
744 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
745 prologue_end = prologue_start + 64; /* See above. */
749 if (prev_pc < prologue_end)
750 prologue_end = prev_pc;
752 /* Now search the prologue looking for instructions that set up the
753 frame pointer, adjust the stack pointer, and save registers.
755 Be careful, however, and if it doesn't look like a prologue,
756 don't try to scan it. If, for instance, a frameless function
757 begins with stmfd sp!, then we will tell ourselves there is
758 a frame, which will confuse stack traceback, as well as "finish"
759 and other operations that rely on a knowledge of the stack
762 In the APCS, the prologue should start with "mov ip, sp" so
763 if we don't see this as the first insn, we will stop.
765 [Note: This doesn't seem to be true any longer, so it's now an
766 optional part of the prologue. - Kevin Buettner, 2001-11-20]
768 [Note further: The "mov ip,sp" only seems to be missing in
769 frameless functions at optimization level "-O2" or above,
770 in which case it is often (but not always) replaced by
771 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
773 sp_offset = fp_offset = ip_offset = 0;
775 for (current_pc = prologue_start;
776 current_pc < prologue_end;
779 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
781 if (insn == 0xe1a0c00d) /* mov ip, sp */
786 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
788 unsigned imm = insn & 0xff; /* immediate value */
789 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
790 imm = (imm >> rot) | (imm << (32 - rot));
794 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
796 unsigned imm = insn & 0xff; /* immediate value */
797 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
798 imm = (imm >> rot) | (imm << (32 - rot));
802 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
805 cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
808 else if ((insn & 0xffff0000) == 0xe92d0000)
809 /* stmfd sp!, {..., fp, ip, lr, pc}
811 stmfd sp!, {a1, a2, a3, a4} */
813 int mask = insn & 0xffff;
815 /* Calculate offsets of saved registers. */
816 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
817 if (mask & (1 << regno))
820 cache->saved_regs[regno].addr = sp_offset;
823 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
824 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
825 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
827 /* No need to add this to saved_regs -- it's just an arg reg. */
830 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
831 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
832 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
834 /* No need to add this to saved_regs -- it's just an arg reg. */
837 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
839 unsigned imm = insn & 0xff; /* immediate value */
840 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
841 imm = (imm >> rot) | (imm << (32 - rot));
842 fp_offset = -imm + ip_offset;
843 cache->framereg = ARM_FP_REGNUM;
845 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
847 unsigned imm = insn & 0xff; /* immediate value */
848 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
849 imm = (imm >> rot) | (imm << (32 - rot));
852 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
855 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
856 cache->saved_regs[regno].addr = sp_offset;
858 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
861 unsigned int fp_start_reg, fp_bound_reg;
863 if ((insn & 0x800) == 0x800) /* N0 is set */
865 if ((insn & 0x40000) == 0x40000) /* N1 is set */
872 if ((insn & 0x40000) == 0x40000) /* N1 is set */
878 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
879 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
880 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
883 cache->saved_regs[fp_start_reg++].addr = sp_offset;
886 else if ((insn & 0xf0000000) != 0xe0000000)
887 break; /* Condition not true, exit early */
888 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
889 break; /* Don't scan past a block load */
891 /* The optimizer might shove anything into the prologue,
892 so we just skip what we don't recognize. */
896 /* The frame size is just the negative of the offset (from the
897 original SP) of the last thing thing we pushed on the stack.
898 The frame offset is [new FP] - [new SP]. */
899 cache->framesize = -sp_offset;
900 if (cache->framereg == ARM_FP_REGNUM)
901 cache->frameoffset = fp_offset - sp_offset;
903 cache->frameoffset = 0;
906 static struct arm_prologue_cache *
907 arm_make_prologue_cache (struct frame_info *next_frame)
910 struct arm_prologue_cache *cache;
911 CORE_ADDR unwound_fp;
913 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
914 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
916 arm_scan_prologue (next_frame, cache);
918 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
922 cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
924 /* Calculate actual addresses of saved registers using offsets
925 determined by arm_scan_prologue. */
926 for (reg = 0; reg < NUM_REGS; reg++)
927 if (trad_frame_addr_p (cache->saved_regs, reg))
928 cache->saved_regs[reg].addr += cache->prev_sp;
933 /* Our frame ID for a normal frame is the current function's starting PC
934 and the caller's SP when we were called. */
937 arm_prologue_this_id (struct frame_info *next_frame,
939 struct frame_id *this_id)
941 struct arm_prologue_cache *cache;
945 if (*this_cache == NULL)
946 *this_cache = arm_make_prologue_cache (next_frame);
949 func = frame_func_unwind (next_frame);
951 /* This is meant to halt the backtrace at "_start". Make sure we
952 don't halt it at a generic dummy frame. */
953 if (func <= LOWEST_PC)
956 /* If we've hit a wall, stop. */
957 if (cache->prev_sp == 0)
960 id = frame_id_build (cache->prev_sp, func);
962 /* Check that we're not going round in circles with the same frame
963 ID (but avoid applying the test to sentinel frames which do go
964 round in circles). */
965 if (frame_relative_level (next_frame) >= 0
966 && get_frame_type (next_frame) == NORMAL_FRAME
967 && frame_id_eq (get_frame_id (next_frame), id))
974 arm_prologue_prev_register (struct frame_info *next_frame,
978 enum lval_type *lvalp,
983 struct arm_prologue_cache *cache;
985 if (*this_cache == NULL)
986 *this_cache = arm_make_prologue_cache (next_frame);
989 /* If we are asked to unwind the PC, then we need to return the LR
990 instead. The saved value of PC points into this frame's
991 prologue, not the next frame's resume location. */
992 if (prev_regnum == ARM_PC_REGNUM)
993 prev_regnum = ARM_LR_REGNUM;
995 /* SP is generally not saved to the stack, but this frame is
996 identified by NEXT_FRAME's stack pointer at the time of the call.
997 The value was already reconstructed into PREV_SP. */
998 if (prev_regnum == ARM_SP_REGNUM)
1002 store_unsigned_integer (valuep, 4, cache->prev_sp);
1006 trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum,
1007 optimized, lvalp, addrp, realnump, valuep);
1010 struct frame_unwind arm_prologue_unwind = {
1012 arm_prologue_this_id,
1013 arm_prologue_prev_register
1016 static const struct frame_unwind *
1017 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
1019 return &arm_prologue_unwind;
1023 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1025 struct arm_prologue_cache *cache;
1027 if (*this_cache == NULL)
1028 *this_cache = arm_make_prologue_cache (next_frame);
1029 cache = *this_cache;
1031 return cache->prev_sp + cache->frameoffset - cache->framesize;
1034 struct frame_base arm_normal_base = {
1035 &arm_prologue_unwind,
1036 arm_normal_frame_base,
1037 arm_normal_frame_base,
1038 arm_normal_frame_base
1041 static struct arm_prologue_cache *
1042 arm_make_sigtramp_cache (struct frame_info *next_frame)
1044 struct arm_prologue_cache *cache;
1047 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
1049 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
1051 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1053 for (reg = 0; reg < NUM_REGS; reg++)
1054 cache->saved_regs[reg].addr
1055 = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp,
1056 frame_pc_unwind (next_frame), reg);
1058 /* FIXME: What about thumb mode? */
1059 cache->framereg = ARM_SP_REGNUM;
1061 = read_memory_integer (cache->saved_regs[cache->framereg].addr,
1062 register_size (current_gdbarch, cache->framereg));
1068 arm_sigtramp_this_id (struct frame_info *next_frame,
1070 struct frame_id *this_id)
1072 struct arm_prologue_cache *cache;
1074 if (*this_cache == NULL)
1075 *this_cache = arm_make_sigtramp_cache (next_frame);
1076 cache = *this_cache;
1078 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1079 the sigtramp frame; the PC should be the beginning of the trampoline. */
1080 *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame));
1084 arm_sigtramp_prev_register (struct frame_info *next_frame,
1088 enum lval_type *lvalp,
1093 struct arm_prologue_cache *cache;
1095 if (*this_cache == NULL)
1096 *this_cache = arm_make_sigtramp_cache (next_frame);
1097 cache = *this_cache;
1099 trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum,
1100 optimized, lvalp, addrp, realnump, valuep);
1103 struct frame_unwind arm_sigtramp_unwind = {
1105 arm_sigtramp_this_id,
1106 arm_sigtramp_prev_register
1109 static const struct frame_unwind *
1110 arm_sigtramp_unwind_sniffer (struct frame_info *next_frame)
1112 /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1113 against the name of the function, the code below will have to be
1114 changed to first fetch the name of the function and then pass
1115 this name to PC_IN_SIGTRAMP. */
1117 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1118 && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame), (char *) 0))
1119 return &arm_sigtramp_unwind;
1124 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1125 dummy frame. The frame ID's base needs to match the TOS value
1126 saved by save_dummy_frame_tos() and returned from
1127 arm_push_dummy_call, and the PC needs to match the dummy frame's
1130 static struct frame_id
1131 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1133 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1134 frame_pc_unwind (next_frame));
1137 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1138 be used to construct the previous frame's ID, after looking up the
1139 containing function). */
1142 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1145 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1146 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1150 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1152 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1155 /* DEPRECATED_CALL_DUMMY_WORDS:
1156 This sequence of words is the instructions
1162 Note this is 12 bytes. */
1164 static LONGEST arm_call_dummy_words[] =
1166 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1169 /* When arguments must be pushed onto the stack, they go on in reverse
1170 order. The code below implements a FILO (stack) to do this. */
1175 struct stack_item *prev;
1179 static struct stack_item *
1180 push_stack_item (struct stack_item *prev, void *contents, int len)
1182 struct stack_item *si;
1183 si = xmalloc (sizeof (struct stack_item));
1184 si->data = xmalloc (len);
1187 memcpy (si->data, contents, len);
1191 static struct stack_item *
1192 pop_stack_item (struct stack_item *si)
1194 struct stack_item *dead = si;
1201 /* We currently only support passing parameters in integer registers. This
1202 conforms with GCC's default model. Several other variants exist and
1203 we should probably support some of them based on the selected ABI. */
1206 arm_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1207 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1208 struct value **args, CORE_ADDR sp, int struct_return,
1209 CORE_ADDR struct_addr)
1214 struct stack_item *si = NULL;
1216 /* Set the return address. For the ARM, the return breakpoint is
1217 always at BP_ADDR. */
1218 /* XXX Fix for Thumb. */
1219 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1221 /* Walk through the list of args and determine how large a temporary
1222 stack is required. Need to take care here as structs may be
1223 passed on the stack, and we have to to push them. */
1226 argreg = ARM_A1_REGNUM;
1229 /* Some platforms require a double-word aligned stack. Make sure sp
1230 is correctly aligned before we start. We always do this even if
1231 it isn't really needed -- it can never hurt things. */
1232 sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1);
1234 /* The struct_return pointer occupies the first parameter
1235 passing register. */
1239 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1240 REGISTER_NAME (argreg), paddr (struct_addr));
1241 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1245 for (argnum = 0; argnum < nargs; argnum++)
1248 struct type *arg_type;
1249 struct type *target_type;
1250 enum type_code typecode;
1253 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1254 len = TYPE_LENGTH (arg_type);
1255 target_type = TYPE_TARGET_TYPE (arg_type);
1256 typecode = TYPE_CODE (arg_type);
1257 val = VALUE_CONTENTS (args[argnum]);
1259 /* If the argument is a pointer to a function, and it is a
1260 Thumb function, create a LOCAL copy of the value and set
1261 the THUMB bit in it. */
1262 if (TYPE_CODE_PTR == typecode
1263 && target_type != NULL
1264 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1266 CORE_ADDR regval = extract_unsigned_integer (val, len);
1267 if (arm_pc_is_thumb (regval))
1270 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1274 /* Copy the argument to general registers or the stack in
1275 register-sized pieces. Large arguments are split between
1276 registers and stack. */
1279 int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE;
1281 if (argreg <= ARM_LAST_ARG_REGNUM)
1283 /* The argument is being passed in a general purpose
1285 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1287 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1288 argnum, REGISTER_NAME (argreg),
1289 phex (regval, DEPRECATED_REGISTER_SIZE));
1290 regcache_cooked_write_unsigned (regcache, argreg, regval);
1295 /* Push the arguments onto the stack. */
1297 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1299 si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE);
1300 nstack += DEPRECATED_REGISTER_SIZE;
1307 /* If we have an odd number of words to push, then decrement the stack
1308 by one word now, so first stack argument will be dword aligned. */
1315 write_memory (sp, si->data, si->len);
1316 si = pop_stack_item (si);
1319 /* Finally, update teh SP register. */
1320 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1326 print_fpu_flags (int flags)
1328 if (flags & (1 << 0))
1329 fputs ("IVO ", stdout);
1330 if (flags & (1 << 1))
1331 fputs ("DVZ ", stdout);
1332 if (flags & (1 << 2))
1333 fputs ("OFL ", stdout);
1334 if (flags & (1 << 3))
1335 fputs ("UFL ", stdout);
1336 if (flags & (1 << 4))
1337 fputs ("INX ", stdout);
1341 /* Print interesting information about the floating point processor
1342 (if present) or emulator. */
1344 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1345 struct frame_info *frame, const char *args)
1347 unsigned long status = read_register (ARM_FPS_REGNUM);
1350 type = (status >> 24) & 127;
1351 printf ("%s FPU type %d\n",
1352 (status & (1 << 31)) ? "Hardware" : "Software",
1354 fputs ("mask: ", stdout);
1355 print_fpu_flags (status >> 16);
1356 fputs ("flags: ", stdout);
1357 print_fpu_flags (status);
1360 /* Return the GDB type object for the "standard" data type of data in
1363 static struct type *
1364 arm_register_type (struct gdbarch *gdbarch, int regnum)
1366 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1368 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1369 return builtin_type_arm_ext_big;
1371 return builtin_type_arm_ext_littlebyte_bigword;
1374 return builtin_type_int32;
1377 /* Index within `registers' of the first byte of the space for
1381 arm_register_byte (int regnum)
1383 if (regnum < ARM_F0_REGNUM)
1384 return regnum * INT_REGISTER_SIZE;
1385 else if (regnum < ARM_PS_REGNUM)
1386 return (NUM_GREGS * INT_REGISTER_SIZE
1387 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE);
1389 return (NUM_GREGS * INT_REGISTER_SIZE
1390 + NUM_FREGS * FP_REGISTER_SIZE
1391 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1394 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1396 arm_register_sim_regno (int regnum)
1399 gdb_assert (reg >= 0 && reg < NUM_REGS);
1401 if (reg < NUM_GREGS)
1402 return SIM_ARM_R0_REGNUM + reg;
1405 if (reg < NUM_FREGS)
1406 return SIM_ARM_FP0_REGNUM + reg;
1409 if (reg < NUM_SREGS)
1410 return SIM_ARM_FPS_REGNUM + reg;
1413 internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum);
1416 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1417 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1418 It is thought that this is is the floating-point register format on
1419 little-endian systems. */
1422 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1426 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1427 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1429 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1431 floatformat_from_doublest (fmt, &d, dbl);
1435 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1438 floatformat_to_doublest (fmt, ptr, &d);
1439 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1440 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1442 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1447 condition_true (unsigned long cond, unsigned long status_reg)
1449 if (cond == INST_AL || cond == INST_NV)
1455 return ((status_reg & FLAG_Z) != 0);
1457 return ((status_reg & FLAG_Z) == 0);
1459 return ((status_reg & FLAG_C) != 0);
1461 return ((status_reg & FLAG_C) == 0);
1463 return ((status_reg & FLAG_N) != 0);
1465 return ((status_reg & FLAG_N) == 0);
1467 return ((status_reg & FLAG_V) != 0);
1469 return ((status_reg & FLAG_V) == 0);
1471 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1473 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1475 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1477 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1479 return (((status_reg & FLAG_Z) == 0) &&
1480 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1482 return (((status_reg & FLAG_Z) != 0) ||
1483 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1488 /* Support routines for single stepping. Calculate the next PC value. */
1489 #define submask(x) ((1L << ((x) + 1)) - 1)
1490 #define bit(obj,st) (((obj) >> (st)) & 1)
1491 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1492 #define sbits(obj,st,fn) \
1493 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1494 #define BranchDest(addr,instr) \
1495 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1498 static unsigned long
1499 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1500 unsigned long status_reg)
1502 unsigned long res, shift;
1503 int rm = bits (inst, 0, 3);
1504 unsigned long shifttype = bits (inst, 5, 6);
1508 int rs = bits (inst, 8, 11);
1509 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1512 shift = bits (inst, 7, 11);
1515 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1516 + (bit (inst, 4) ? 12 : 8))
1517 : read_register (rm));
1522 res = shift >= 32 ? 0 : res << shift;
1526 res = shift >= 32 ? 0 : res >> shift;
1532 res = ((res & 0x80000000L)
1533 ? ~((~res) >> shift) : res >> shift);
1536 case 3: /* ROR/RRX */
1539 res = (res >> 1) | (carry ? 0x80000000L : 0);
1541 res = (res >> shift) | (res << (32 - shift));
1545 return res & 0xffffffff;
1548 /* Return number of 1-bits in VAL. */
1551 bitcount (unsigned long val)
1554 for (nbits = 0; val != 0; nbits++)
1555 val &= val - 1; /* delete rightmost 1-bit in val */
1560 thumb_get_next_pc (CORE_ADDR pc)
1562 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1563 unsigned short inst1 = read_memory_integer (pc, 2);
1564 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1565 unsigned long offset;
1567 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1571 /* Fetch the saved PC from the stack. It's stored above
1572 all of the other registers. */
1573 offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE;
1574 sp = read_register (ARM_SP_REGNUM);
1575 nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
1576 nextpc = ADDR_BITS_REMOVE (nextpc);
1578 error ("Infinite loop detected");
1580 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1582 unsigned long status = read_register (ARM_PS_REGNUM);
1583 unsigned long cond = bits (inst1, 8, 11);
1584 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1585 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1587 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1589 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1591 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1593 unsigned short inst2 = read_memory_integer (pc + 2, 2);
1594 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1595 nextpc = pc_val + offset;
1596 /* For BLX make sure to clear the low bits. */
1597 if (bits (inst2, 11, 12) == 1)
1598 nextpc = nextpc & 0xfffffffc;
1600 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1602 if (bits (inst1, 3, 6) == 0x0f)
1605 nextpc = read_register (bits (inst1, 3, 6));
1607 nextpc = ADDR_BITS_REMOVE (nextpc);
1609 error ("Infinite loop detected");
1616 arm_get_next_pc (CORE_ADDR pc)
1618 unsigned long pc_val;
1619 unsigned long this_instr;
1620 unsigned long status;
1623 if (arm_pc_is_thumb (pc))
1624 return thumb_get_next_pc (pc);
1626 pc_val = (unsigned long) pc;
1627 this_instr = read_memory_integer (pc, 4);
1628 status = read_register (ARM_PS_REGNUM);
1629 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1631 if (condition_true (bits (this_instr, 28, 31), status))
1633 switch (bits (this_instr, 24, 27))
1636 case 0x1: /* data processing */
1640 unsigned long operand1, operand2, result = 0;
1644 if (bits (this_instr, 12, 15) != 15)
1647 if (bits (this_instr, 22, 25) == 0
1648 && bits (this_instr, 4, 7) == 9) /* multiply */
1649 error ("Illegal update to pc in instruction");
1651 /* BX <reg>, BLX <reg> */
1652 if (bits (this_instr, 4, 28) == 0x12fff1
1653 || bits (this_instr, 4, 28) == 0x12fff3)
1655 rn = bits (this_instr, 0, 3);
1656 result = (rn == 15) ? pc_val + 8 : read_register (rn);
1657 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1660 error ("Infinite loop detected");
1665 /* Multiply into PC */
1666 c = (status & FLAG_C) ? 1 : 0;
1667 rn = bits (this_instr, 16, 19);
1668 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1670 if (bit (this_instr, 25))
1672 unsigned long immval = bits (this_instr, 0, 7);
1673 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1674 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1677 else /* operand 2 is a shifted register */
1678 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1680 switch (bits (this_instr, 21, 24))
1683 result = operand1 & operand2;
1687 result = operand1 ^ operand2;
1691 result = operand1 - operand2;
1695 result = operand2 - operand1;
1699 result = operand1 + operand2;
1703 result = operand1 + operand2 + c;
1707 result = operand1 - operand2 + c;
1711 result = operand2 - operand1 + c;
1717 case 0xb: /* tst, teq, cmp, cmn */
1718 result = (unsigned long) nextpc;
1722 result = operand1 | operand2;
1726 /* Always step into a function. */
1731 result = operand1 & ~operand2;
1738 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1741 error ("Infinite loop detected");
1746 case 0x5: /* data transfer */
1749 if (bit (this_instr, 20))
1752 if (bits (this_instr, 12, 15) == 15)
1758 if (bit (this_instr, 22))
1759 error ("Illegal update to pc in instruction");
1761 /* byte write to PC */
1762 rn = bits (this_instr, 16, 19);
1763 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1764 if (bit (this_instr, 24))
1767 int c = (status & FLAG_C) ? 1 : 0;
1768 unsigned long offset =
1769 (bit (this_instr, 25)
1770 ? shifted_reg_val (this_instr, c, pc_val, status)
1771 : bits (this_instr, 0, 11));
1773 if (bit (this_instr, 23))
1778 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1781 nextpc = ADDR_BITS_REMOVE (nextpc);
1784 error ("Infinite loop detected");
1790 case 0x9: /* block transfer */
1791 if (bit (this_instr, 20))
1794 if (bit (this_instr, 15))
1799 if (bit (this_instr, 23))
1802 unsigned long reglist = bits (this_instr, 0, 14);
1803 offset = bitcount (reglist) * 4;
1804 if (bit (this_instr, 24)) /* pre */
1807 else if (bit (this_instr, 24))
1811 unsigned long rn_val =
1812 read_register (bits (this_instr, 16, 19));
1814 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1818 nextpc = ADDR_BITS_REMOVE (nextpc);
1820 error ("Infinite loop detected");
1825 case 0xb: /* branch & link */
1826 case 0xa: /* branch */
1828 nextpc = BranchDest (pc, this_instr);
1831 if (bits (this_instr, 28, 31) == INST_NV)
1832 nextpc |= bit (this_instr, 24) << 1;
1834 nextpc = ADDR_BITS_REMOVE (nextpc);
1836 error ("Infinite loop detected");
1842 case 0xe: /* coproc ops */
1847 fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n");
1855 /* single_step() is called just before we want to resume the inferior,
1856 if we want to single-step it but there is no hardware or kernel
1857 single-step support. We find the target of the coming instruction
1860 single_step() is also called just after the inferior stops. If we
1861 had set up a simulated single-step, we undo our damage. */
1864 arm_software_single_step (enum target_signal sig, int insert_bpt)
1866 static int next_pc; /* State between setting and unsetting. */
1867 static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
1871 next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
1872 target_insert_breakpoint (next_pc, break_mem);
1875 target_remove_breakpoint (next_pc, break_mem);
1878 #include "bfd-in2.h"
1879 #include "libcoff.h"
1882 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1884 if (arm_pc_is_thumb (memaddr))
1886 static asymbol *asym;
1887 static combined_entry_type ce;
1888 static struct coff_symbol_struct csym;
1889 static struct bfd fake_bfd;
1890 static bfd_target fake_target;
1892 if (csym.native == NULL)
1894 /* Create a fake symbol vector containing a Thumb symbol.
1895 This is solely so that the code in print_insn_little_arm()
1896 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1897 the presence of a Thumb symbol and switch to decoding
1898 Thumb instructions. */
1900 fake_target.flavour = bfd_target_coff_flavour;
1901 fake_bfd.xvec = &fake_target;
1902 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1904 csym.symbol.the_bfd = &fake_bfd;
1905 csym.symbol.name = "fake";
1906 asym = (asymbol *) & csym;
1909 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1910 info->symbols = &asym;
1913 info->symbols = NULL;
1915 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1916 return print_insn_big_arm (memaddr, info);
1918 return print_insn_little_arm (memaddr, info);
1921 /* The following define instruction sequences that will cause ARM
1922 cpu's to take an undefined instruction trap. These are used to
1923 signal a breakpoint to GDB.
1925 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1926 modes. A different instruction is required for each mode. The ARM
1927 cpu's can also be big or little endian. Thus four different
1928 instructions are needed to support all cases.
1930 Note: ARMv4 defines several new instructions that will take the
1931 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1932 not in fact add the new instructions. The new undefined
1933 instructions in ARMv4 are all instructions that had no defined
1934 behaviour in earlier chips. There is no guarantee that they will
1935 raise an exception, but may be treated as NOP's. In practice, it
1936 may only safe to rely on instructions matching:
1938 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1939 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1940 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1942 Even this may only true if the condition predicate is true. The
1943 following use a condition predicate of ALWAYS so it is always TRUE.
1945 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1946 and NetBSD all use a software interrupt rather than an undefined
1947 instruction to force a trap. This can be handled by by the
1948 abi-specific code during establishment of the gdbarch vector. */
1951 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1952 override these definitions. */
1953 #ifndef ARM_LE_BREAKPOINT
1954 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1956 #ifndef ARM_BE_BREAKPOINT
1957 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1959 #ifndef THUMB_LE_BREAKPOINT
1960 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1962 #ifndef THUMB_BE_BREAKPOINT
1963 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1966 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
1967 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
1968 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
1969 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
1971 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1972 the program counter value to determine whether a 16-bit or 32-bit
1973 breakpoint should be used. It returns a pointer to a string of
1974 bytes that encode a breakpoint instruction, stores the length of
1975 the string to *lenptr, and adjusts the program counter (if
1976 necessary) to point to the actual memory location where the
1977 breakpoint should be inserted. */
1979 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
1980 breakpoints and storing their handles instread of what was in
1981 memory. It is nice that this is the same size as a handle -
1982 otherwise remote-rdp will have to change. */
1984 static const unsigned char *
1985 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1987 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1989 if (arm_pc_is_thumb (*pcptr))
1991 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1992 *lenptr = tdep->thumb_breakpoint_size;
1993 return tdep->thumb_breakpoint;
1997 *lenptr = tdep->arm_breakpoint_size;
1998 return tdep->arm_breakpoint;
2002 /* Extract from an array REGBUF containing the (raw) register state a
2003 function return value of type TYPE, and copy that, in virtual
2004 format, into VALBUF. */
2007 arm_extract_return_value (struct type *type,
2008 struct regcache *regs,
2011 bfd_byte *valbuf = dst;
2013 if (TYPE_CODE_FLT == TYPE_CODE (type))
2015 switch (arm_get_fp_model (current_gdbarch))
2019 /* The value is in register F0 in internal format. We need to
2020 extract the raw value and then convert it to the desired
2022 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2024 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2025 convert_from_extended (floatformat_from_type (type), tmpbuf,
2030 case ARM_FLOAT_SOFT_FPA:
2031 case ARM_FLOAT_SOFT_VFP:
2032 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2033 if (TYPE_LENGTH (type) > 4)
2034 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2035 valbuf + INT_REGISTER_SIZE);
2040 (__FILE__, __LINE__,
2041 "arm_extract_return_value: Floating point model not supported");
2045 else if (TYPE_CODE (type) == TYPE_CODE_INT
2046 || TYPE_CODE (type) == TYPE_CODE_CHAR
2047 || TYPE_CODE (type) == TYPE_CODE_BOOL
2048 || TYPE_CODE (type) == TYPE_CODE_PTR
2049 || TYPE_CODE (type) == TYPE_CODE_REF
2050 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2052 /* If the the type is a plain integer, then the access is
2053 straight-forward. Otherwise we have to play around a bit more. */
2054 int len = TYPE_LENGTH (type);
2055 int regno = ARM_A1_REGNUM;
2060 /* By using store_unsigned_integer we avoid having to do
2061 anything special for small big-endian values. */
2062 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2063 store_unsigned_integer (valbuf,
2064 (len > INT_REGISTER_SIZE
2065 ? INT_REGISTER_SIZE : len),
2067 len -= INT_REGISTER_SIZE;
2068 valbuf += INT_REGISTER_SIZE;
2073 /* For a structure or union the behaviour is as if the value had
2074 been stored to word-aligned memory and then loaded into
2075 registers with 32-bit load instruction(s). */
2076 int len = TYPE_LENGTH (type);
2077 int regno = ARM_A1_REGNUM;
2078 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2082 regcache_cooked_read (regs, regno++, tmpbuf);
2083 memcpy (valbuf, tmpbuf,
2084 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2085 len -= INT_REGISTER_SIZE;
2086 valbuf += INT_REGISTER_SIZE;
2091 /* Extract from an array REGBUF containing the (raw) register state
2092 the address in which a function should return its structure value. */
2095 arm_extract_struct_value_address (struct regcache *regcache)
2099 regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret);
2103 /* Will a function return an aggregate type in memory or in a
2104 register? Return 0 if an aggregate type can be returned in a
2105 register, 1 if it must be returned in memory. */
2108 arm_use_struct_convention (int gcc_p, struct type *type)
2111 enum type_code code;
2113 CHECK_TYPEDEF (type);
2115 /* In the ARM ABI, "integer" like aggregate types are returned in
2116 registers. For an aggregate type to be integer like, its size
2117 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2118 offset of each addressable subfield must be zero. Note that bit
2119 fields are not addressable, and all addressable subfields of
2120 unions always start at offset zero.
2122 This function is based on the behaviour of GCC 2.95.1.
2123 See: gcc/arm.c: arm_return_in_memory() for details.
2125 Note: All versions of GCC before GCC 2.95.2 do not set up the
2126 parameters correctly for a function returning the following
2127 structure: struct { float f;}; This should be returned in memory,
2128 not a register. Richard Earnshaw sent me a patch, but I do not
2129 know of any way to detect if a function like the above has been
2130 compiled with the correct calling convention. */
2132 /* All aggregate types that won't fit in a register must be returned
2134 if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE)
2139 /* The only aggregate types that can be returned in a register are
2140 structs and unions. Arrays must be returned in memory. */
2141 code = TYPE_CODE (type);
2142 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2147 /* Assume all other aggregate types can be returned in a register.
2148 Run a check for structures, unions and arrays. */
2151 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2154 /* Need to check if this struct/union is "integer" like. For
2155 this to be true, its size must be less than or equal to
2156 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2157 subfield must be zero. Note that bit fields are not
2158 addressable, and unions always start at offset zero. If any
2159 of the subfields is a floating point type, the struct/union
2160 cannot be an integer type. */
2162 /* For each field in the object, check:
2163 1) Is it FP? --> yes, nRc = 1;
2164 2) Is it addressable (bitpos != 0) and
2165 not packed (bitsize == 0)?
2169 for (i = 0; i < TYPE_NFIELDS (type); i++)
2171 enum type_code field_type_code;
2172 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2174 /* Is it a floating point type field? */
2175 if (field_type_code == TYPE_CODE_FLT)
2181 /* If bitpos != 0, then we have to care about it. */
2182 if (TYPE_FIELD_BITPOS (type, i) != 0)
2184 /* Bitfields are not addressable. If the field bitsize is
2185 zero, then the field is not packed. Hence it cannot be
2186 a bitfield or any other packed type. */
2187 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2199 /* Write into appropriate registers a function return value of type
2200 TYPE, given in virtual format. */
2203 arm_store_return_value (struct type *type, struct regcache *regs,
2206 const bfd_byte *valbuf = src;
2208 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2210 char buf[MAX_REGISTER_SIZE];
2212 switch (arm_get_fp_model (current_gdbarch))
2216 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2217 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2220 case ARM_FLOAT_SOFT_FPA:
2221 case ARM_FLOAT_SOFT_VFP:
2222 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2223 if (TYPE_LENGTH (type) > 4)
2224 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2225 valbuf + INT_REGISTER_SIZE);
2230 (__FILE__, __LINE__,
2231 "arm_store_return_value: Floating point model not supported");
2235 else if (TYPE_CODE (type) == TYPE_CODE_INT
2236 || TYPE_CODE (type) == TYPE_CODE_CHAR
2237 || TYPE_CODE (type) == TYPE_CODE_BOOL
2238 || TYPE_CODE (type) == TYPE_CODE_PTR
2239 || TYPE_CODE (type) == TYPE_CODE_REF
2240 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2242 if (TYPE_LENGTH (type) <= 4)
2244 /* Values of one word or less are zero/sign-extended and
2246 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2247 LONGEST val = unpack_long (type, valbuf);
2249 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2250 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2254 /* Integral values greater than one word are stored in consecutive
2255 registers starting with r0. This will always be a multiple of
2256 the regiser size. */
2257 int len = TYPE_LENGTH (type);
2258 int regno = ARM_A1_REGNUM;
2262 regcache_cooked_write (regs, regno++, valbuf);
2263 len -= INT_REGISTER_SIZE;
2264 valbuf += INT_REGISTER_SIZE;
2270 /* For a structure or union the behaviour is as if the value had
2271 been stored to word-aligned memory and then loaded into
2272 registers with 32-bit load instruction(s). */
2273 int len = TYPE_LENGTH (type);
2274 int regno = ARM_A1_REGNUM;
2275 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2279 memcpy (tmpbuf, valbuf,
2280 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2281 regcache_cooked_write (regs, regno++, tmpbuf);
2282 len -= INT_REGISTER_SIZE;
2283 valbuf += INT_REGISTER_SIZE;
2289 arm_get_longjmp_target (CORE_ADDR *pc)
2292 char buf[INT_REGISTER_SIZE];
2293 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2295 jb_addr = read_register (ARM_A1_REGNUM);
2297 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2301 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2305 /* Return non-zero if the PC is inside a thumb call thunk. */
2308 arm_in_call_stub (CORE_ADDR pc, char *name)
2310 CORE_ADDR start_addr;
2312 /* Find the starting address of the function containing the PC. If
2313 the caller didn't give us a name, look it up at the same time. */
2314 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2318 return strncmp (name, "_call_via_r", 11) == 0;
2321 /* If PC is in a Thumb call or return stub, return the address of the
2322 target PC, which is in a register. The thunk functions are called
2323 _called_via_xx, where x is the register name. The possible names
2324 are r0-r9, sl, fp, ip, sp, and lr. */
2327 arm_skip_stub (CORE_ADDR pc)
2330 CORE_ADDR start_addr;
2332 /* Find the starting address and name of the function containing the PC. */
2333 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2336 /* Call thunks always start with "_call_via_". */
2337 if (strncmp (name, "_call_via_", 10) == 0)
2339 /* Use the name suffix to determine which register contains the
2341 static char *table[15] =
2342 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2343 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2347 for (regno = 0; regno <= 14; regno++)
2348 if (strcmp (&name[10], table[regno]) == 0)
2349 return read_register (regno);
2352 return 0; /* not a stub */
2356 set_arm_command (char *args, int from_tty)
2358 printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
2359 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2363 show_arm_command (char *args, int from_tty)
2365 cmd_show_list (showarmcmdlist, from_tty, "");
2368 enum arm_float_model
2369 arm_get_fp_model (struct gdbarch *gdbarch)
2371 if (arm_fp_model == ARM_FLOAT_AUTO)
2372 return gdbarch_tdep (gdbarch)->fp_model;
2374 return arm_fp_model;
2378 arm_set_fp (struct gdbarch *gdbarch)
2380 enum arm_float_model fp_model = arm_get_fp_model (gdbarch);
2382 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2383 && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA))
2385 set_gdbarch_double_format (gdbarch,
2386 &floatformat_ieee_double_littlebyte_bigword);
2387 set_gdbarch_long_double_format
2388 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2392 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
2393 set_gdbarch_long_double_format (gdbarch,
2394 &floatformat_ieee_double_little);
2399 set_fp_model_sfunc (char *args, int from_tty,
2400 struct cmd_list_element *c)
2402 enum arm_float_model fp_model;
2404 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2405 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2407 arm_fp_model = fp_model;
2411 if (fp_model == ARM_FLOAT_LAST)
2412 internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.",
2415 if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2416 arm_set_fp (current_gdbarch);
2420 show_fp_model (char *args, int from_tty,
2421 struct cmd_list_element *c)
2423 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2425 if (arm_fp_model == ARM_FLOAT_AUTO
2426 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2427 printf_filtered (" - the default for the current ABI is \"%s\".\n",
2428 fp_model_strings[tdep->fp_model]);
2431 /* If the user changes the register disassembly style used for info
2432 register and other commands, we have to also switch the style used
2433 in opcodes for disassembly output. This function is run in the "set
2434 arm disassembly" command, and does that. */
2437 set_disassembly_style_sfunc (char *args, int from_tty,
2438 struct cmd_list_element *c)
2440 set_disassembly_style ();
2443 /* Return the ARM register name corresponding to register I. */
2445 arm_register_name (int i)
2447 return arm_register_names[i];
2451 set_disassembly_style (void)
2453 const char *setname, *setdesc, **regnames;
2456 /* Find the style that the user wants in the opcodes table. */
2458 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2459 while ((disassembly_style != setname)
2460 && (current < num_disassembly_options))
2461 get_arm_regnames (++current, &setname, &setdesc, ®names);
2462 current_option = current;
2464 /* Fill our copy. */
2465 for (j = 0; j < numregs; j++)
2466 arm_register_names[j] = (char *) regnames[j];
2469 if (isupper (*regnames[ARM_PC_REGNUM]))
2471 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2472 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2476 arm_register_names[ARM_FPS_REGNUM] = "fps";
2477 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2480 /* Synchronize the disassembler. */
2481 set_arm_regname_option (current);
2484 /* arm_othernames implements the "othernames" command. This is deprecated
2485 by the "set arm disassembly" command. */
2488 arm_othernames (char *names, int n)
2490 /* Circle through the various flavors. */
2491 current_option = (current_option + 1) % num_disassembly_options;
2493 disassembly_style = valid_disassembly_styles[current_option];
2494 set_disassembly_style ();
2497 /* Test whether the coff symbol specific value corresponds to a Thumb
2501 coff_sym_is_thumb (int val)
2503 return (val == C_THUMBEXT ||
2504 val == C_THUMBSTAT ||
2505 val == C_THUMBEXTFUNC ||
2506 val == C_THUMBSTATFUNC ||
2507 val == C_THUMBLABEL);
2510 /* arm_coff_make_msymbol_special()
2511 arm_elf_make_msymbol_special()
2513 These functions test whether the COFF or ELF symbol corresponds to
2514 an address in thumb code, and set a "special" bit in a minimal
2515 symbol to indicate that it does. */
2518 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2520 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2522 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2524 MSYMBOL_SET_SPECIAL (msym);
2528 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2530 if (coff_sym_is_thumb (val))
2531 MSYMBOL_SET_SPECIAL (msym);
2535 arm_write_pc (CORE_ADDR pc, ptid_t ptid)
2537 write_register_pid (ARM_PC_REGNUM, pc, ptid);
2539 /* If necessary, set the T bit. */
2542 CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid);
2543 if (arm_pc_is_thumb (pc))
2544 write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid);
2546 write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid);
2550 static enum gdb_osabi
2551 arm_elf_osabi_sniffer (bfd *abfd)
2553 unsigned int elfosabi, eflags;
2554 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2556 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2561 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2562 file are conforming to the base specification for that machine
2563 (there are no OS-specific extensions). In order to determine the
2564 real OS in use we must look for OS notes that have been added. */
2565 bfd_map_over_sections (abfd,
2566 generic_elf_osabi_sniff_abi_tag_sections,
2568 if (osabi == GDB_OSABI_UNKNOWN)
2570 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2571 field for more information. */
2572 eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
2575 case EF_ARM_EABI_VER1:
2576 osabi = GDB_OSABI_ARM_EABI_V1;
2579 case EF_ARM_EABI_VER2:
2580 osabi = GDB_OSABI_ARM_EABI_V2;
2583 case EF_ARM_EABI_UNKNOWN:
2584 /* Assume GNU tools. */
2585 osabi = GDB_OSABI_ARM_APCS;
2589 internal_error (__FILE__, __LINE__,
2590 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2591 "version 0x%x", eflags);
2597 /* GNU tools use this value. Check note sections in this case,
2599 bfd_map_over_sections (abfd,
2600 generic_elf_osabi_sniff_abi_tag_sections,
2602 if (osabi == GDB_OSABI_UNKNOWN)
2604 /* Assume APCS ABI. */
2605 osabi = GDB_OSABI_ARM_APCS;
2609 case ELFOSABI_FREEBSD:
2610 osabi = GDB_OSABI_FREEBSD_ELF;
2613 case ELFOSABI_NETBSD:
2614 osabi = GDB_OSABI_NETBSD_ELF;
2617 case ELFOSABI_LINUX:
2618 osabi = GDB_OSABI_LINUX;
2626 /* Initialize the current architecture based on INFO. If possible,
2627 re-use an architecture from ARCHES, which is a list of
2628 architectures already created during this debugging session.
2630 Called e.g. at program startup, when reading a core file, and when
2631 reading a binary file. */
2633 static struct gdbarch *
2634 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2636 struct gdbarch_tdep *tdep;
2637 struct gdbarch *gdbarch;
2639 /* Try to deterimine the ABI of the object we are loading. */
2641 if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN)
2643 switch (bfd_get_flavour (info.abfd))
2645 case bfd_target_aout_flavour:
2646 /* Assume it's an old APCS-style ABI. */
2647 info.osabi = GDB_OSABI_ARM_APCS;
2650 case bfd_target_coff_flavour:
2651 /* Assume it's an old APCS-style ABI. */
2653 info.osabi = GDB_OSABI_ARM_APCS;
2657 /* Leave it as "unknown". */
2662 /* If there is already a candidate, use it. */
2663 arches = gdbarch_list_lookup_by_info (arches, &info);
2665 return arches->gdbarch;
2667 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2668 gdbarch = gdbarch_alloc (&info, tdep);
2670 /* We used to default to FPA for generic ARM, but almost nobody uses that
2671 now, and we now provide a way for the user to force the model. So
2672 default to the most useful variant. */
2673 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
2676 switch (info.byte_order)
2678 case BFD_ENDIAN_BIG:
2679 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2680 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2681 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2682 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2686 case BFD_ENDIAN_LITTLE:
2687 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2688 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2689 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2690 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2695 internal_error (__FILE__, __LINE__,
2696 "arm_gdbarch_init: bad byte order for float format");
2699 /* On ARM targets char defaults to unsigned. */
2700 set_gdbarch_char_signed (gdbarch, 0);
2702 /* This should be low enough for everything. */
2703 tdep->lowest_pc = 0x20;
2704 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2706 set_gdbarch_deprecated_call_dummy_words (gdbarch, arm_call_dummy_words);
2707 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0);
2709 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2711 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2713 /* Frame handling. */
2714 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2715 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2716 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2718 set_gdbarch_deprecated_frameless_function_invocation (gdbarch, arm_frameless_function_invocation);
2720 frame_base_set_default (gdbarch, &arm_normal_base);
2722 /* Address manipulation. */
2723 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2724 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2726 /* Advance PC across function entry code. */
2727 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2729 /* Get the PC when a frame might not be available. */
2730 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
2732 /* The stack grows downward. */
2733 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2735 /* Breakpoint manipulation. */
2736 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2738 /* Information about registers, etc. */
2739 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2740 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2741 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2742 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2743 set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte);
2744 set_gdbarch_deprecated_register_bytes (gdbarch,
2745 (NUM_GREGS * INT_REGISTER_SIZE
2746 + NUM_FREGS * FP_REGISTER_SIZE
2747 + NUM_SREGS * STATUS_REGISTER_SIZE));
2748 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2749 set_gdbarch_register_type (gdbarch, arm_register_type);
2751 /* Internal <-> external register number maps. */
2752 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2754 /* Integer registers are 4 bytes. */
2755 set_gdbarch_deprecated_register_size (gdbarch, 4);
2756 set_gdbarch_register_name (gdbarch, arm_register_name);
2758 /* Returning results. */
2759 set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value);
2760 set_gdbarch_store_return_value (gdbarch, arm_store_return_value);
2761 set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention);
2762 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address);
2764 /* Single stepping. */
2765 /* XXX For an RDI target we should ask the target if it can single-step. */
2766 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2769 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
2771 /* Minsymbol frobbing. */
2772 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2773 set_gdbarch_coff_make_msymbol_special (gdbarch,
2774 arm_coff_make_msymbol_special);
2776 /* Hook in the ABI-specific overrides, if they have been registered. */
2777 gdbarch_init_osabi (info, gdbarch);
2779 /* Add some default predicates. */
2780 frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer);
2781 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
2783 /* Now we have tuned the configuration, set a few final things,
2784 based on what the OS ABI has told us. */
2786 if (tdep->jb_pc >= 0)
2787 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
2789 /* Floating point sizes and format. */
2790 switch (info.byte_order)
2792 case BFD_ENDIAN_BIG:
2793 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
2794 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
2795 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
2799 case BFD_ENDIAN_LITTLE:
2800 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
2801 arm_set_fp (gdbarch);
2805 internal_error (__FILE__, __LINE__,
2806 "arm_gdbarch_init: bad byte order for float format");
2813 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2815 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2820 fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx",
2821 (unsigned long) tdep->lowest_pc);
2825 arm_init_abi_eabi_v1 (struct gdbarch_info info,
2826 struct gdbarch *gdbarch)
2832 arm_init_abi_eabi_v2 (struct gdbarch_info info,
2833 struct gdbarch *gdbarch)
2839 arm_init_abi_apcs (struct gdbarch_info info,
2840 struct gdbarch *gdbarch)
2845 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
2848 _initialize_arm_tdep (void)
2850 struct ui_file *stb;
2852 struct cmd_list_element *new_set, *new_show;
2853 const char *setname;
2854 const char *setdesc;
2855 const char **regnames;
2857 static char *helptext;
2859 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
2861 /* Register an ELF OS ABI sniffer for ARM binaries. */
2862 gdbarch_register_osabi_sniffer (bfd_arch_arm,
2863 bfd_target_elf_flavour,
2864 arm_elf_osabi_sniffer);
2866 /* Register some ABI variants for embedded systems. */
2867 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1,
2868 arm_init_abi_eabi_v1);
2869 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2,
2870 arm_init_abi_eabi_v2);
2871 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS,
2874 /* Get the number of possible sets of register names defined in opcodes. */
2875 num_disassembly_options = get_arm_regname_num_options ();
2877 /* Add root prefix command for all "set arm"/"show arm" commands. */
2878 add_prefix_cmd ("arm", no_class, set_arm_command,
2879 "Various ARM-specific commands.",
2880 &setarmcmdlist, "set arm ", 0, &setlist);
2882 add_prefix_cmd ("arm", no_class, show_arm_command,
2883 "Various ARM-specific commands.",
2884 &showarmcmdlist, "show arm ", 0, &showlist);
2886 /* Sync the opcode insn printer with our register viewer. */
2887 parse_arm_disassembler_option ("reg-names-std");
2889 /* Begin creating the help text. */
2890 stb = mem_fileopen ();
2891 fprintf_unfiltered (stb, "Set the disassembly style.\n"
2892 "The valid values are:\n");
2894 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2895 valid_disassembly_styles
2896 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
2897 for (i = 0; i < num_disassembly_options; i++)
2899 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2900 valid_disassembly_styles[i] = setname;
2901 fprintf_unfiltered (stb, "%s - %s\n", setname,
2903 /* Copy the default names (if found) and synchronize disassembler. */
2904 if (!strcmp (setname, "std"))
2906 disassembly_style = setname;
2908 for (j = 0; j < numregs; j++)
2909 arm_register_names[j] = (char *) regnames[j];
2910 set_arm_regname_option (i);
2913 /* Mark the end of valid options. */
2914 valid_disassembly_styles[num_disassembly_options] = NULL;
2916 /* Finish the creation of the help text. */
2917 fprintf_unfiltered (stb, "The default is \"std\".");
2918 helptext = ui_file_xstrdup (stb, &length);
2919 ui_file_delete (stb);
2921 /* Add the deprecated disassembly-flavor command. */
2922 new_set = add_set_enum_cmd ("disassembly-flavor", no_class,
2923 valid_disassembly_styles,
2927 set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
2928 deprecate_cmd (new_set, "set arm disassembly");
2929 deprecate_cmd (add_show_from_set (new_set, &showlist),
2930 "show arm disassembly");
2932 /* And now add the new interface. */
2933 new_set = add_set_enum_cmd ("disassembler", no_class,
2934 valid_disassembly_styles, &disassembly_style,
2935 helptext, &setarmcmdlist);
2937 set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
2938 add_show_from_set (new_set, &showarmcmdlist);
2940 add_setshow_cmd_full ("apcs32", no_class,
2941 var_boolean, (char *) &arm_apcs_32,
2942 "Set usage of ARM 32-bit mode.",
2943 "Show usage of ARM 32-bit mode.",
2945 &setlist, &showlist, &new_set, &new_show);
2946 deprecate_cmd (new_set, "set arm apcs32");
2947 deprecate_cmd (new_show, "show arm apcs32");
2949 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
2950 "Set usage of ARM 32-bit mode. "
2951 "When off, a 26-bit PC will be used.",
2952 "Show usage of ARM 32-bit mode. "
2953 "When off, a 26-bit PC will be used.",
2955 &setarmcmdlist, &showarmcmdlist);
2957 /* Add a command to allow the user to force the FPU model. */
2958 new_set = add_set_enum_cmd
2959 ("fpu", no_class, fp_model_strings, ¤t_fp_model,
2960 "Set the floating point type.\n"
2961 "auto - Determine the FP typefrom the OS-ABI.\n"
2962 "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
2963 "fpa - FPA co-processor (GCC compiled).\n"
2964 "softvfp - Software FP with pure-endian doubles.\n"
2965 "vfp - VFP co-processor.",
2967 set_cmd_sfunc (new_set, set_fp_model_sfunc);
2968 set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model);
2970 /* Add the deprecated "othernames" command. */
2971 deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames,
2972 "Switch to the next set of register names."),
2973 "set arm disassembly");
2975 /* Debugging flag. */
2976 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
2977 "Set ARM debugging. "
2978 "When on, arm-specific debugging is enabled.",
2979 "Show ARM debugging. "
2980 "When on, arm-specific debugging is enabled.",
2982 &setdebuglist, &showdebuglist);