1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 #include <ctype.h> /* XXX for isupper () */
29 #include "gdb_string.h"
30 #include "dis-asm.h" /* For register styles. */
34 #include "arch-utils.h"
36 #include "frame-unwind.h"
37 #include "frame-base.h"
38 #include "trad-frame.h"
41 #include "gdb/sim-arm.h"
44 #include "coff/internal.h"
47 #include "gdb_assert.h"
51 /* Each OS has a different mechanism for accessing the various
52 registers stored in the sigcontext structure.
54 SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
55 function pointer) which may be used to determine the addresses
56 of the various saved registers in the sigcontext structure.
58 For the ARM target, there are three parameters to this function.
59 The first is the pc value of the frame under consideration, the
60 second the stack pointer of this frame, and the last is the
61 register number to fetch.
63 If the tm.h file does not define this macro, then it's assumed that
64 no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
67 When it comes time to multi-arching this code, see the identically
68 named machinery in ia64-tdep.c for an example of how it could be
69 done. It should not be necessary to modify the code below where
70 this macro is used. */
72 #ifdef SIGCONTEXT_REGISTER_ADDRESS
73 #ifndef SIGCONTEXT_REGISTER_ADDRESS_P
74 #define SIGCONTEXT_REGISTER_ADDRESS_P() 1
77 #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
78 #define SIGCONTEXT_REGISTER_ADDRESS_P() 0
81 /* Macros for setting and testing a bit in a minimal symbol that marks
82 it as Thumb function. The MSB of the minimal symbol's "info" field
83 is used for this purpose.
85 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
86 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
88 #define MSYMBOL_SET_SPECIAL(msym) \
89 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
92 #define MSYMBOL_IS_SPECIAL(msym) \
93 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
95 /* The list of available "set arm ..." and "show arm ..." commands. */
96 static struct cmd_list_element *setarmcmdlist = NULL;
97 static struct cmd_list_element *showarmcmdlist = NULL;
99 /* The type of floating-point to use. Keep this in sync with enum
100 arm_float_model, and the help string in _initialize_arm_tdep. */
101 static const char *fp_model_strings[] =
110 /* A variable that can be configured by the user. */
111 static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
112 static const char *current_fp_model = "auto";
114 /* Number of different reg name sets (options). */
115 static int num_disassembly_options;
117 /* We have more registers than the disassembler as gdb can print the value
118 of special registers as well.
119 The general register names are overwritten by whatever is being used by
120 the disassembler at the moment. We also adjust the case of cpsr and fps. */
122 /* Initial value: Register names used in ARM's ISA documentation. */
123 static char * arm_register_name_strings[] =
124 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
125 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
126 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
127 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
128 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
129 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
130 "fps", "cpsr" }; /* 24 25 */
131 static char **arm_register_names = arm_register_name_strings;
133 /* Valid register name styles. */
134 static const char **valid_disassembly_styles;
136 /* Disassembly style to use. Default to "std" register names. */
137 static const char *disassembly_style;
138 /* Index to that option in the opcodes table. */
139 static int current_option;
141 /* This is used to keep the bfd arch_info in sync with the disassembly
143 static void set_disassembly_style_sfunc(char *, int,
144 struct cmd_list_element *);
145 static void set_disassembly_style (void);
147 static void convert_from_extended (const struct floatformat *, const void *,
149 static void convert_to_extended (const struct floatformat *, void *,
152 struct arm_prologue_cache
154 /* The stack pointer at the time this frame was created; i.e. the
155 caller's stack pointer when this function was called. It is used
156 to identify this frame. */
159 /* The frame base for this frame is just prev_sp + frame offset -
160 frame size. FRAMESIZE is the size of this stack frame, and
161 FRAMEOFFSET if the initial offset from the stack pointer (this
162 frame's stack pointer, not PREV_SP) to the frame base. */
167 /* The register used to hold the frame pointer for this frame. */
170 /* Saved register offsets. */
171 struct trad_frame_saved_reg *saved_regs;
174 /* Addresses for calling Thumb functions have the bit 0 set.
175 Here are some macros to test, set, or clear bit 0 of addresses. */
176 #define IS_THUMB_ADDR(addr) ((addr) & 1)
177 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
178 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
180 /* Set to true if the 32-bit mode is in use. */
184 /* Determine if the program counter specified in MEMADDR is in a Thumb
188 arm_pc_is_thumb (CORE_ADDR memaddr)
190 struct minimal_symbol *sym;
192 /* If bit 0 of the address is set, assume this is a Thumb address. */
193 if (IS_THUMB_ADDR (memaddr))
196 /* Thumb functions have a "special" bit set in minimal symbols. */
197 sym = lookup_minimal_symbol_by_pc (memaddr);
200 return (MSYMBOL_IS_SPECIAL (sym));
208 /* Remove useless bits from addresses in a running program. */
210 arm_addr_bits_remove (CORE_ADDR val)
213 return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
215 return (val & 0x03fffffc);
218 /* When reading symbols, we need to zap the low bit of the address,
219 which may be set to 1 for Thumb functions. */
221 arm_smash_text_address (CORE_ADDR val)
226 /* Immediately after a function call, return the saved pc. Can't
227 always go through the frames for this because on some machines the
228 new frame is not set up until the new function executes some
232 arm_saved_pc_after_call (struct frame_info *frame)
234 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
237 /* Determine whether the function invocation represented by FI has a
238 frame on the stack associated with it. If it does return zero,
239 otherwise return 1. */
242 arm_frameless_function_invocation (struct frame_info *fi)
244 CORE_ADDR func_start, after_prologue;
247 /* Sometimes we have functions that do a little setup (like saving the
248 vN registers with the stmdb instruction, but DO NOT set up a frame.
249 The symbol table will report this as a prologue. However, it is
250 important not to try to parse these partial frames as frames, or we
251 will get really confused.
253 So I will demand 3 instructions between the start & end of the
254 prologue before I call it a real prologue, i.e. at least
259 func_start = (get_frame_func (fi) + FUNCTION_START_OFFSET);
260 after_prologue = SKIP_PROLOGUE (func_start);
262 /* There are some frameless functions whose first two instructions
263 follow the standard APCS form, in which case after_prologue will
264 be func_start + 8. */
266 frameless = (after_prologue < func_start + 12);
270 /* A typical Thumb prologue looks like this:
274 Sometimes the latter instruction may be replaced by:
282 or, on tpcs, like this:
289 There is always one instruction of three classes:
294 When we have found at least one of each class we are done with the prolog.
295 Note that the "sub sp, #NN" before the push does not count.
299 thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
301 CORE_ADDR current_pc;
303 bit 0 - push { rlist }
304 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
305 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
309 for (current_pc = pc;
310 current_pc + 2 < func_end && current_pc < pc + 40;
313 unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
315 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
317 findmask |= 1; /* push found */
319 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
322 if ((findmask & 1) == 0) /* before push ? */
325 findmask |= 4; /* add/sub sp found */
327 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
329 findmask |= 2; /* setting of r7 found */
331 else if (insn == 0x466f) /* mov r7, sp */
333 findmask |= 2; /* setting of r7 found */
335 else if (findmask == (4+2+1))
337 /* We have found one of each type of prologue instruction */
341 /* Something in the prolog that we don't care about or some
342 instruction from outside the prolog scheduled here for
350 /* Advance the PC across any function entry prologue instructions to
351 reach some "real" code.
353 The APCS (ARM Procedure Call Standard) defines the following
357 [stmfd sp!, {a1,a2,a3,a4}]
358 stmfd sp!, {...,fp,ip,lr,pc}
359 [stfe f7, [sp, #-12]!]
360 [stfe f6, [sp, #-12]!]
361 [stfe f5, [sp, #-12]!]
362 [stfe f4, [sp, #-12]!]
363 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
366 arm_skip_prologue (CORE_ADDR pc)
370 CORE_ADDR func_addr, func_end = 0;
372 struct symtab_and_line sal;
374 /* If we're in a dummy frame, don't even try to skip the prologue. */
375 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
378 /* See what the symbol table says. */
380 if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
384 /* Found a function. */
385 sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
386 if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
388 /* Don't use this trick for assembly source files. */
389 sal = find_pc_line (func_addr, 0);
390 if ((sal.line != 0) && (sal.end < func_end))
395 /* Check if this is Thumb code. */
396 if (arm_pc_is_thumb (pc))
397 return thumb_skip_prologue (pc, func_end);
399 /* Can't find the prologue end in the symbol table, try it the hard way
400 by disassembling the instructions. */
402 /* Like arm_scan_prologue, stop no later than pc + 64. */
403 if (func_end == 0 || func_end > pc + 64)
406 for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
408 inst = read_memory_integer (skip_pc, 4);
410 /* "mov ip, sp" is no longer a required part of the prologue. */
411 if (inst == 0xe1a0c00d) /* mov ip, sp */
414 if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
417 if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
420 /* Some prologues begin with "str lr, [sp, #-4]!". */
421 if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
424 if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
427 if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
430 /* Any insns after this point may float into the code, if it makes
431 for better instruction scheduling, so we skip them only if we
432 find them, but still consider the function to be frame-ful. */
434 /* We may have either one sfmfd instruction here, or several stfe
435 insns, depending on the version of floating point code we
437 if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
440 if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
443 if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
446 if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
449 if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
450 (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
451 (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
454 if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
455 (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
456 (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
459 /* Un-recognized instruction; stop scanning. */
463 return skip_pc; /* End of prologue */
467 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
468 This function decodes a Thumb function prologue to determine:
469 1) the size of the stack frame
470 2) which registers are saved on it
471 3) the offsets of saved regs
472 4) the offset from the stack pointer to the frame pointer
474 A typical Thumb function prologue would create this stack frame
475 (offsets relative to FP)
476 old SP -> 24 stack parameters
479 R7 -> 0 local variables (16 bytes)
480 SP -> -12 additional stack space (12 bytes)
481 The frame size would thus be 36 bytes, and the frame offset would be
482 12 bytes. The frame register is R7.
484 The comments for thumb_skip_prolog() describe the algorithm we use
485 to detect the end of the prolog. */
489 thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache)
491 CORE_ADDR prologue_start;
492 CORE_ADDR prologue_end;
493 CORE_ADDR current_pc;
494 /* Which register has been copied to register n? */
497 bit 0 - push { rlist }
498 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
499 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
504 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
506 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
508 if (sal.line == 0) /* no line info, use current PC */
509 prologue_end = prev_pc;
510 else if (sal.end < prologue_end) /* next line begins after fn end */
511 prologue_end = sal.end; /* (probably means no prologue) */
514 /* We're in the boondocks: allow for
515 16 pushes, an add, and "mv fp,sp". */
516 prologue_end = prologue_start + 40;
518 prologue_end = min (prologue_end, prev_pc);
520 /* Initialize the saved register map. When register H is copied to
521 register L, we will put H in saved_reg[L]. */
522 for (i = 0; i < 16; i++)
525 /* Search the prologue looking for instructions that set up the
526 frame pointer, adjust the stack pointer, and save registers.
527 Do this until all basic prolog instructions are found. */
529 cache->framesize = 0;
530 for (current_pc = prologue_start;
531 (current_pc < prologue_end) && ((findmask & 7) != 7);
538 insn = read_memory_unsigned_integer (current_pc, 2);
540 if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
543 findmask |= 1; /* push found */
544 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
545 whether to save LR (R14). */
546 mask = (insn & 0xff) | ((insn & 0x100) << 6);
548 /* Calculate offsets of saved R0-R7 and LR. */
549 for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
550 if (mask & (1 << regno))
552 cache->framesize += 4;
553 cache->saved_regs[saved_reg[regno]].addr = -cache->framesize;
554 /* Reset saved register map. */
555 saved_reg[regno] = regno;
558 else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
561 if ((findmask & 1) == 0) /* before push? */
564 findmask |= 4; /* add/sub sp found */
566 offset = (insn & 0x7f) << 2; /* get scaled offset */
567 if (insn & 0x80) /* is it signed? (==subtracting) */
569 cache->frameoffset += offset;
572 cache->framesize -= offset;
574 else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
576 findmask |= 2; /* setting of r7 found */
577 cache->framereg = THUMB_FP_REGNUM;
578 /* get scaled offset */
579 cache->frameoffset = (insn & 0xff) << 2;
581 else if (insn == 0x466f) /* mov r7, sp */
583 findmask |= 2; /* setting of r7 found */
584 cache->framereg = THUMB_FP_REGNUM;
585 cache->frameoffset = 0;
586 saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
588 else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
590 int lo_reg = insn & 7; /* dest. register (r0-r7) */
591 int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
592 saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
595 /* Something in the prolog that we don't care about or some
596 instruction from outside the prolog scheduled here for
602 /* This function decodes an ARM function prologue to determine:
603 1) the size of the stack frame
604 2) which registers are saved on it
605 3) the offsets of saved regs
606 4) the offset from the stack pointer to the frame pointer
607 This information is stored in the "extra" fields of the frame_info.
609 There are two basic forms for the ARM prologue. The fixed argument
610 function call will look like:
613 stmfd sp!, {fp, ip, lr, pc}
617 Which would create this stack frame (offsets relative to FP):
618 IP -> 4 (caller's stack)
619 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
620 -4 LR (return address in caller)
621 -8 IP (copy of caller's SP)
623 SP -> -28 Local variables
625 The frame size would thus be 32 bytes, and the frame offset would be
626 28 bytes. The stmfd call can also save any of the vN registers it
627 plans to use, which increases the frame size accordingly.
629 Note: The stored PC is 8 off of the STMFD instruction that stored it
630 because the ARM Store instructions always store PC + 8 when you read
633 A variable argument function call will look like:
636 stmfd sp!, {a1, a2, a3, a4}
637 stmfd sp!, {fp, ip, lr, pc}
640 Which would create this stack frame (offsets relative to FP):
641 IP -> 20 (caller's stack)
646 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
647 -4 LR (return address in caller)
648 -8 IP (copy of caller's SP)
650 SP -> -28 Local variables
652 The frame size would thus be 48 bytes, and the frame offset would be
655 There is another potential complication, which is that the optimizer
656 will try to separate the store of fp in the "stmfd" instruction from
657 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
658 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
660 Also, note, the original version of the ARM toolchain claimed that there
663 instruction at the end of the prologue. I have never seen GCC produce
664 this, and the ARM docs don't mention it. We still test for it below in
670 arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache)
672 int regno, sp_offset, fp_offset, ip_offset;
673 CORE_ADDR prologue_start, prologue_end, current_pc;
674 CORE_ADDR prev_pc = frame_pc_unwind (next_frame);
676 /* Assume there is no frame until proven otherwise. */
677 cache->framereg = ARM_SP_REGNUM;
678 cache->framesize = 0;
679 cache->frameoffset = 0;
681 if (frame_tdep_pc_fixup)
682 frame_tdep_pc_fixup(&prev_pc);
684 /* Check for Thumb prologue. */
685 if (arm_pc_is_thumb (prev_pc))
687 thumb_scan_prologue (prev_pc, cache);
691 /* Find the function prologue. If we can't find the function in
692 the symbol table, peek in the stack frame to find the PC. */
693 if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end))
695 /* One way to find the end of the prologue (which works well
696 for unoptimized code) is to do the following:
698 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
701 prologue_end = prev_pc;
702 else if (sal.end < prologue_end)
703 prologue_end = sal.end;
705 This mechanism is very accurate so long as the optimizer
706 doesn't move any instructions from the function body into the
707 prologue. If this happens, sal.end will be the last
708 instruction in the first hunk of prologue code just before
709 the first instruction that the scheduler has moved from
710 the body to the prologue.
712 In order to make sure that we scan all of the prologue
713 instructions, we use a slightly less accurate mechanism which
714 may scan more than necessary. To help compensate for this
715 lack of accuracy, the prologue scanning loop below contains
716 several clauses which'll cause the loop to terminate early if
717 an implausible prologue instruction is encountered.
723 is a suitable endpoint since it accounts for the largest
724 possible prologue plus up to five instructions inserted by
727 if (prologue_end > prologue_start + 64)
729 prologue_end = prologue_start + 64; /* See above. */
734 /* We have no symbol information. Our only option is to assume this
735 function has a standard stack frame and the normal frame register.
736 Then, we can find the value of our frame pointer on entrance to
737 the callee (or at the present moment if this is the innermost frame).
738 The value stored there should be the address of the stmfd + 8. */
740 LONGEST return_value;
742 frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM);
743 if (!safe_read_memory_integer (frame_loc, 4, &return_value))
747 prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
748 prologue_end = prologue_start + 64; /* See above. */
752 if (prev_pc < prologue_end)
753 prologue_end = prev_pc;
755 /* Now search the prologue looking for instructions that set up the
756 frame pointer, adjust the stack pointer, and save registers.
758 Be careful, however, and if it doesn't look like a prologue,
759 don't try to scan it. If, for instance, a frameless function
760 begins with stmfd sp!, then we will tell ourselves there is
761 a frame, which will confuse stack traceback, as well as "finish"
762 and other operations that rely on a knowledge of the stack
765 In the APCS, the prologue should start with "mov ip, sp" so
766 if we don't see this as the first insn, we will stop.
768 [Note: This doesn't seem to be true any longer, so it's now an
769 optional part of the prologue. - Kevin Buettner, 2001-11-20]
771 [Note further: The "mov ip,sp" only seems to be missing in
772 frameless functions at optimization level "-O2" or above,
773 in which case it is often (but not always) replaced by
774 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
776 sp_offset = fp_offset = ip_offset = 0;
778 for (current_pc = prologue_start;
779 current_pc < prologue_end;
782 unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
784 if (insn == 0xe1a0c00d) /* mov ip, sp */
789 else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
791 unsigned imm = insn & 0xff; /* immediate value */
792 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
793 imm = (imm >> rot) | (imm << (32 - rot));
797 else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
799 unsigned imm = insn & 0xff; /* immediate value */
800 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
801 imm = (imm >> rot) | (imm << (32 - rot));
805 else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
808 cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset;
811 else if ((insn & 0xffff0000) == 0xe92d0000)
812 /* stmfd sp!, {..., fp, ip, lr, pc}
814 stmfd sp!, {a1, a2, a3, a4} */
816 int mask = insn & 0xffff;
818 /* Calculate offsets of saved registers. */
819 for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
820 if (mask & (1 << regno))
823 cache->saved_regs[regno].addr = sp_offset;
826 else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
827 (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
828 (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
830 /* No need to add this to saved_regs -- it's just an arg reg. */
833 else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
834 (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
835 (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
837 /* No need to add this to saved_regs -- it's just an arg reg. */
840 else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
842 unsigned imm = insn & 0xff; /* immediate value */
843 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
844 imm = (imm >> rot) | (imm << (32 - rot));
845 fp_offset = -imm + ip_offset;
846 cache->framereg = ARM_FP_REGNUM;
848 else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
850 unsigned imm = insn & 0xff; /* immediate value */
851 unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
852 imm = (imm >> rot) | (imm << (32 - rot));
855 else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
858 regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
859 cache->saved_regs[regno].addr = sp_offset;
861 else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
864 unsigned int fp_start_reg, fp_bound_reg;
866 if ((insn & 0x800) == 0x800) /* N0 is set */
868 if ((insn & 0x40000) == 0x40000) /* N1 is set */
875 if ((insn & 0x40000) == 0x40000) /* N1 is set */
881 fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7);
882 fp_bound_reg = fp_start_reg + n_saved_fp_regs;
883 for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
886 cache->saved_regs[fp_start_reg++].addr = sp_offset;
889 else if ((insn & 0xf0000000) != 0xe0000000)
890 break; /* Condition not true, exit early */
891 else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */
892 break; /* Don't scan past a block load */
894 /* The optimizer might shove anything into the prologue,
895 so we just skip what we don't recognize. */
899 /* The frame size is just the negative of the offset (from the
900 original SP) of the last thing thing we pushed on the stack.
901 The frame offset is [new FP] - [new SP]. */
902 cache->framesize = -sp_offset;
903 if (cache->framereg == ARM_FP_REGNUM)
904 cache->frameoffset = fp_offset - sp_offset;
906 cache->frameoffset = 0;
909 static struct arm_prologue_cache *
910 arm_make_prologue_cache (struct frame_info *next_frame)
913 struct arm_prologue_cache *cache;
914 CORE_ADDR unwound_fp;
916 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
917 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
919 arm_scan_prologue (next_frame, cache);
920 unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg);
924 cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset;
926 /* Calculate actual addresses of saved registers using offsets
927 determined by arm_scan_prologue. */
928 for (reg = 0; reg < NUM_REGS; reg++)
929 if (trad_frame_addr_p (cache->saved_regs, reg))
930 cache->saved_regs[reg].addr += cache->prev_sp;
935 /* Our frame ID for a normal frame is the current function's starting PC
936 and the caller's SP when we were called. */
939 arm_prologue_this_id (struct frame_info *next_frame,
941 struct frame_id *this_id)
943 struct arm_prologue_cache *cache;
947 if (*this_cache == NULL)
948 *this_cache = arm_make_prologue_cache (next_frame);
951 func = frame_func_unwind (next_frame);
953 /* This is meant to halt the backtrace at "_start". Make sure we
954 don't halt it at a generic dummy frame. */
955 if (func <= LOWEST_PC)
958 /* If we've hit a wall, stop. */
959 if (cache->prev_sp == 0)
962 id = frame_id_build (cache->prev_sp, func);
964 /* Check that we're not going round in circles with the same frame
965 ID (but avoid applying the test to sentinel frames which do go
966 round in circles). */
967 if (frame_relative_level (next_frame) >= 0
968 && get_frame_type (next_frame) == NORMAL_FRAME
969 && frame_id_eq (get_frame_id (next_frame), id))
976 arm_prologue_prev_register (struct frame_info *next_frame,
980 enum lval_type *lvalp,
985 struct arm_prologue_cache *cache;
987 if (*this_cache == NULL)
988 *this_cache = arm_make_prologue_cache (next_frame);
991 /* If we are asked to unwind the PC, then we need to return the LR
992 instead. The saved value of PC points into this frame's
993 prologue, not the next frame's resume location. */
994 if (prev_regnum == ARM_PC_REGNUM)
995 prev_regnum = ARM_LR_REGNUM;
997 /* SP is generally not saved to the stack, but this frame is
998 identified by NEXT_FRAME's stack pointer at the time of the call.
999 The value was already reconstructed into PREV_SP. */
1000 if (prev_regnum == ARM_SP_REGNUM)
1004 store_unsigned_integer (valuep, 4, cache->prev_sp);
1008 trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum,
1009 optimized, lvalp, addrp, realnump, valuep);
1012 struct frame_unwind arm_prologue_unwind = {
1014 arm_prologue_this_id,
1015 arm_prologue_prev_register
1018 static const struct frame_unwind *
1019 arm_prologue_unwind_sniffer (struct frame_info *next_frame)
1021 return &arm_prologue_unwind;
1025 arm_normal_frame_base (struct frame_info *next_frame, void **this_cache)
1027 struct arm_prologue_cache *cache;
1029 if (*this_cache == NULL)
1030 *this_cache = arm_make_prologue_cache (next_frame);
1031 cache = *this_cache;
1033 return cache->prev_sp + cache->frameoffset - cache->framesize;
1036 struct frame_base arm_normal_base = {
1037 &arm_prologue_unwind,
1038 arm_normal_frame_base,
1039 arm_normal_frame_base,
1040 arm_normal_frame_base
1043 static struct arm_prologue_cache *
1044 arm_make_sigtramp_cache (struct frame_info *next_frame)
1046 struct arm_prologue_cache *cache;
1049 cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache));
1051 cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM);
1053 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1055 for (reg = 0; reg < NUM_REGS; reg++)
1056 cache->saved_regs[reg].addr
1057 = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp,
1058 frame_pc_unwind (next_frame), reg);
1060 /* FIXME: What about thumb mode? */
1061 cache->framereg = ARM_SP_REGNUM;
1063 = read_memory_integer (cache->saved_regs[cache->framereg].addr,
1064 register_size (current_gdbarch, cache->framereg));
1070 arm_sigtramp_this_id (struct frame_info *next_frame,
1072 struct frame_id *this_id)
1074 struct arm_prologue_cache *cache;
1076 if (*this_cache == NULL)
1077 *this_cache = arm_make_sigtramp_cache (next_frame);
1078 cache = *this_cache;
1080 /* FIXME drow/2003-07-07: This isn't right if we single-step within
1081 the sigtramp frame; the PC should be the beginning of the trampoline. */
1082 *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame));
1086 arm_sigtramp_prev_register (struct frame_info *next_frame,
1090 enum lval_type *lvalp,
1095 struct arm_prologue_cache *cache;
1097 if (*this_cache == NULL)
1098 *this_cache = arm_make_sigtramp_cache (next_frame);
1099 cache = *this_cache;
1101 trad_frame_prev_register (next_frame, cache->saved_regs, prev_regnum,
1102 optimized, lvalp, addrp, realnump, valuep);
1105 struct frame_unwind arm_sigtramp_unwind = {
1107 arm_sigtramp_this_id,
1108 arm_sigtramp_prev_register
1111 static const struct frame_unwind *
1112 arm_sigtramp_unwind_sniffer (struct frame_info *next_frame)
1114 /* Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
1115 against the name of the function, the code below will have to be
1116 changed to first fetch the name of the function and then pass
1117 this name to PC_IN_SIGTRAMP. */
1119 if (SIGCONTEXT_REGISTER_ADDRESS_P ()
1120 && PC_IN_SIGTRAMP (frame_pc_unwind (next_frame), (char *) 0))
1121 return &arm_sigtramp_unwind;
1126 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1127 dummy frame. The frame ID's base needs to match the TOS value
1128 saved by save_dummy_frame_tos() and returned from
1129 arm_push_dummy_call, and the PC needs to match the dummy frame's
1132 static struct frame_id
1133 arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1135 return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM),
1136 frame_pc_unwind (next_frame));
1139 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1140 be used to construct the previous frame's ID, after looking up the
1141 containing function). */
1144 arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
1147 pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
1148 return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
1152 arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
1154 return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
1157 /* DEPRECATED_CALL_DUMMY_WORDS:
1158 This sequence of words is the instructions
1164 Note this is 12 bytes. */
1166 static LONGEST arm_call_dummy_words[] =
1168 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
1171 /* When arguments must be pushed onto the stack, they go on in reverse
1172 order. The code below implements a FILO (stack) to do this. */
1177 struct stack_item *prev;
1181 static struct stack_item *
1182 push_stack_item (struct stack_item *prev, void *contents, int len)
1184 struct stack_item *si;
1185 si = xmalloc (sizeof (struct stack_item));
1186 si->data = xmalloc (len);
1189 memcpy (si->data, contents, len);
1193 static struct stack_item *
1194 pop_stack_item (struct stack_item *si)
1196 struct stack_item *dead = si;
1203 /* We currently only support passing parameters in integer registers. This
1204 conforms with GCC's default model. Several other variants exist and
1205 we should probably support some of them based on the selected ABI. */
1208 arm_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1209 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1210 struct value **args, CORE_ADDR sp, int struct_return,
1211 CORE_ADDR struct_addr)
1216 struct stack_item *si = NULL;
1218 /* Set the return address. For the ARM, the return breakpoint is
1219 always at BP_ADDR. */
1220 /* XXX Fix for Thumb. */
1221 regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
1223 /* Walk through the list of args and determine how large a temporary
1224 stack is required. Need to take care here as structs may be
1225 passed on the stack, and we have to to push them. */
1228 argreg = ARM_A1_REGNUM;
1231 /* Some platforms require a double-word aligned stack. Make sure sp
1232 is correctly aligned before we start. We always do this even if
1233 it isn't really needed -- it can never hurt things. */
1234 sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1);
1236 /* The struct_return pointer occupies the first parameter
1237 passing register. */
1241 fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
1242 REGISTER_NAME (argreg), paddr (struct_addr));
1243 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
1247 for (argnum = 0; argnum < nargs; argnum++)
1250 struct type *arg_type;
1251 struct type *target_type;
1252 enum type_code typecode;
1255 arg_type = check_typedef (VALUE_TYPE (args[argnum]));
1256 len = TYPE_LENGTH (arg_type);
1257 target_type = TYPE_TARGET_TYPE (arg_type);
1258 typecode = TYPE_CODE (arg_type);
1259 val = VALUE_CONTENTS (args[argnum]);
1261 /* If the argument is a pointer to a function, and it is a
1262 Thumb function, create a LOCAL copy of the value and set
1263 the THUMB bit in it. */
1264 if (TYPE_CODE_PTR == typecode
1265 && target_type != NULL
1266 && TYPE_CODE_FUNC == TYPE_CODE (target_type))
1268 CORE_ADDR regval = extract_unsigned_integer (val, len);
1269 if (arm_pc_is_thumb (regval))
1272 store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
1276 /* Copy the argument to general registers or the stack in
1277 register-sized pieces. Large arguments are split between
1278 registers and stack. */
1281 int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE;
1283 if (argreg <= ARM_LAST_ARG_REGNUM)
1285 /* The argument is being passed in a general purpose
1287 CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
1289 fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
1290 argnum, REGISTER_NAME (argreg),
1291 phex (regval, DEPRECATED_REGISTER_SIZE));
1292 regcache_cooked_write_unsigned (regcache, argreg, regval);
1297 /* Push the arguments onto the stack. */
1299 fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
1301 si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE);
1302 nstack += DEPRECATED_REGISTER_SIZE;
1309 /* If we have an odd number of words to push, then decrement the stack
1310 by one word now, so first stack argument will be dword aligned. */
1317 write_memory (sp, si->data, si->len);
1318 si = pop_stack_item (si);
1321 /* Finally, update teh SP register. */
1322 regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
1328 print_fpu_flags (int flags)
1330 if (flags & (1 << 0))
1331 fputs ("IVO ", stdout);
1332 if (flags & (1 << 1))
1333 fputs ("DVZ ", stdout);
1334 if (flags & (1 << 2))
1335 fputs ("OFL ", stdout);
1336 if (flags & (1 << 3))
1337 fputs ("UFL ", stdout);
1338 if (flags & (1 << 4))
1339 fputs ("INX ", stdout);
1343 /* Print interesting information about the floating point processor
1344 (if present) or emulator. */
1346 arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
1347 struct frame_info *frame, const char *args)
1349 unsigned long status = read_register (ARM_FPS_REGNUM);
1352 type = (status >> 24) & 127;
1353 printf ("%s FPU type %d\n",
1354 (status & (1 << 31)) ? "Hardware" : "Software",
1356 fputs ("mask: ", stdout);
1357 print_fpu_flags (status >> 16);
1358 fputs ("flags: ", stdout);
1359 print_fpu_flags (status);
1362 /* Return the GDB type object for the "standard" data type of data in
1365 static struct type *
1366 arm_register_type (struct gdbarch *gdbarch, int regnum)
1368 if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
1370 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1371 return builtin_type_arm_ext_big;
1373 return builtin_type_arm_ext_littlebyte_bigword;
1376 return builtin_type_int32;
1379 /* Index within `registers' of the first byte of the space for
1383 arm_register_byte (int regnum)
1385 if (regnum < ARM_F0_REGNUM)
1386 return regnum * INT_REGISTER_SIZE;
1387 else if (regnum < ARM_PS_REGNUM)
1388 return (NUM_GREGS * INT_REGISTER_SIZE
1389 + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE);
1391 return (NUM_GREGS * INT_REGISTER_SIZE
1392 + NUM_FREGS * FP_REGISTER_SIZE
1393 + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
1396 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1398 arm_register_sim_regno (int regnum)
1401 gdb_assert (reg >= 0 && reg < NUM_REGS);
1403 if (reg < NUM_GREGS)
1404 return SIM_ARM_R0_REGNUM + reg;
1407 if (reg < NUM_FREGS)
1408 return SIM_ARM_FP0_REGNUM + reg;
1411 if (reg < NUM_SREGS)
1412 return SIM_ARM_FPS_REGNUM + reg;
1415 internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum);
1418 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1419 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1420 It is thought that this is is the floating-point register format on
1421 little-endian systems. */
1424 convert_from_extended (const struct floatformat *fmt, const void *ptr,
1428 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1429 floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
1431 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
1433 floatformat_from_doublest (fmt, &d, dbl);
1437 convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
1440 floatformat_to_doublest (fmt, ptr, &d);
1441 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1442 floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
1444 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
1449 condition_true (unsigned long cond, unsigned long status_reg)
1451 if (cond == INST_AL || cond == INST_NV)
1457 return ((status_reg & FLAG_Z) != 0);
1459 return ((status_reg & FLAG_Z) == 0);
1461 return ((status_reg & FLAG_C) != 0);
1463 return ((status_reg & FLAG_C) == 0);
1465 return ((status_reg & FLAG_N) != 0);
1467 return ((status_reg & FLAG_N) == 0);
1469 return ((status_reg & FLAG_V) != 0);
1471 return ((status_reg & FLAG_V) == 0);
1473 return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
1475 return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
1477 return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
1479 return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
1481 return (((status_reg & FLAG_Z) == 0) &&
1482 (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
1484 return (((status_reg & FLAG_Z) != 0) ||
1485 (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
1490 /* Support routines for single stepping. Calculate the next PC value. */
1491 #define submask(x) ((1L << ((x) + 1)) - 1)
1492 #define bit(obj,st) (((obj) >> (st)) & 1)
1493 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1494 #define sbits(obj,st,fn) \
1495 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1496 #define BranchDest(addr,instr) \
1497 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1500 static unsigned long
1501 shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
1502 unsigned long status_reg)
1504 unsigned long res, shift;
1505 int rm = bits (inst, 0, 3);
1506 unsigned long shifttype = bits (inst, 5, 6);
1510 int rs = bits (inst, 8, 11);
1511 shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
1514 shift = bits (inst, 7, 11);
1517 ? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
1518 + (bit (inst, 4) ? 12 : 8))
1519 : read_register (rm));
1524 res = shift >= 32 ? 0 : res << shift;
1528 res = shift >= 32 ? 0 : res >> shift;
1534 res = ((res & 0x80000000L)
1535 ? ~((~res) >> shift) : res >> shift);
1538 case 3: /* ROR/RRX */
1541 res = (res >> 1) | (carry ? 0x80000000L : 0);
1543 res = (res >> shift) | (res << (32 - shift));
1547 return res & 0xffffffff;
1550 /* Return number of 1-bits in VAL. */
1553 bitcount (unsigned long val)
1556 for (nbits = 0; val != 0; nbits++)
1557 val &= val - 1; /* delete rightmost 1-bit in val */
1562 thumb_get_next_pc (CORE_ADDR pc)
1564 unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
1565 unsigned short inst1 = read_memory_integer (pc, 2);
1566 CORE_ADDR nextpc = pc + 2; /* default is next instruction */
1567 unsigned long offset;
1569 if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
1573 /* Fetch the saved PC from the stack. It's stored above
1574 all of the other registers. */
1575 offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE;
1576 sp = read_register (ARM_SP_REGNUM);
1577 nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
1578 nextpc = ADDR_BITS_REMOVE (nextpc);
1580 error ("Infinite loop detected");
1582 else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
1584 unsigned long status = read_register (ARM_PS_REGNUM);
1585 unsigned long cond = bits (inst1, 8, 11);
1586 if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
1587 nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
1589 else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */
1591 nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
1593 else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
1595 unsigned short inst2 = read_memory_integer (pc + 2, 2);
1596 offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
1597 nextpc = pc_val + offset;
1598 /* For BLX make sure to clear the low bits. */
1599 if (bits (inst2, 11, 12) == 1)
1600 nextpc = nextpc & 0xfffffffc;
1602 else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
1604 if (bits (inst1, 3, 6) == 0x0f)
1607 nextpc = read_register (bits (inst1, 3, 6));
1609 nextpc = ADDR_BITS_REMOVE (nextpc);
1611 error ("Infinite loop detected");
1618 arm_get_next_pc (CORE_ADDR pc)
1620 unsigned long pc_val;
1621 unsigned long this_instr;
1622 unsigned long status;
1625 if (arm_pc_is_thumb (pc))
1626 return thumb_get_next_pc (pc);
1628 pc_val = (unsigned long) pc;
1629 this_instr = read_memory_integer (pc, 4);
1630 status = read_register (ARM_PS_REGNUM);
1631 nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
1633 if (condition_true (bits (this_instr, 28, 31), status))
1635 switch (bits (this_instr, 24, 27))
1638 case 0x1: /* data processing */
1642 unsigned long operand1, operand2, result = 0;
1646 if (bits (this_instr, 12, 15) != 15)
1649 if (bits (this_instr, 22, 25) == 0
1650 && bits (this_instr, 4, 7) == 9) /* multiply */
1651 error ("Illegal update to pc in instruction");
1653 /* BX <reg>, BLX <reg> */
1654 if (bits (this_instr, 4, 28) == 0x12fff1
1655 || bits (this_instr, 4, 28) == 0x12fff3)
1657 rn = bits (this_instr, 0, 3);
1658 result = (rn == 15) ? pc_val + 8 : read_register (rn);
1659 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1662 error ("Infinite loop detected");
1667 /* Multiply into PC */
1668 c = (status & FLAG_C) ? 1 : 0;
1669 rn = bits (this_instr, 16, 19);
1670 operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
1672 if (bit (this_instr, 25))
1674 unsigned long immval = bits (this_instr, 0, 7);
1675 unsigned long rotate = 2 * bits (this_instr, 8, 11);
1676 operand2 = ((immval >> rotate) | (immval << (32 - rotate)))
1679 else /* operand 2 is a shifted register */
1680 operand2 = shifted_reg_val (this_instr, c, pc_val, status);
1682 switch (bits (this_instr, 21, 24))
1685 result = operand1 & operand2;
1689 result = operand1 ^ operand2;
1693 result = operand1 - operand2;
1697 result = operand2 - operand1;
1701 result = operand1 + operand2;
1705 result = operand1 + operand2 + c;
1709 result = operand1 - operand2 + c;
1713 result = operand2 - operand1 + c;
1719 case 0xb: /* tst, teq, cmp, cmn */
1720 result = (unsigned long) nextpc;
1724 result = operand1 | operand2;
1728 /* Always step into a function. */
1733 result = operand1 & ~operand2;
1740 nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
1743 error ("Infinite loop detected");
1748 case 0x5: /* data transfer */
1751 if (bit (this_instr, 20))
1754 if (bits (this_instr, 12, 15) == 15)
1760 if (bit (this_instr, 22))
1761 error ("Illegal update to pc in instruction");
1763 /* byte write to PC */
1764 rn = bits (this_instr, 16, 19);
1765 base = (rn == 15) ? pc_val + 8 : read_register (rn);
1766 if (bit (this_instr, 24))
1769 int c = (status & FLAG_C) ? 1 : 0;
1770 unsigned long offset =
1771 (bit (this_instr, 25)
1772 ? shifted_reg_val (this_instr, c, pc_val, status)
1773 : bits (this_instr, 0, 11));
1775 if (bit (this_instr, 23))
1780 nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
1783 nextpc = ADDR_BITS_REMOVE (nextpc);
1786 error ("Infinite loop detected");
1792 case 0x9: /* block transfer */
1793 if (bit (this_instr, 20))
1796 if (bit (this_instr, 15))
1801 if (bit (this_instr, 23))
1804 unsigned long reglist = bits (this_instr, 0, 14);
1805 offset = bitcount (reglist) * 4;
1806 if (bit (this_instr, 24)) /* pre */
1809 else if (bit (this_instr, 24))
1813 unsigned long rn_val =
1814 read_register (bits (this_instr, 16, 19));
1816 (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
1820 nextpc = ADDR_BITS_REMOVE (nextpc);
1822 error ("Infinite loop detected");
1827 case 0xb: /* branch & link */
1828 case 0xa: /* branch */
1830 nextpc = BranchDest (pc, this_instr);
1833 if (bits (this_instr, 28, 31) == INST_NV)
1834 nextpc |= bit (this_instr, 24) << 1;
1836 nextpc = ADDR_BITS_REMOVE (nextpc);
1838 error ("Infinite loop detected");
1844 case 0xe: /* coproc ops */
1849 fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n");
1857 /* single_step() is called just before we want to resume the inferior,
1858 if we want to single-step it but there is no hardware or kernel
1859 single-step support. We find the target of the coming instruction
1862 single_step() is also called just after the inferior stops. If we
1863 had set up a simulated single-step, we undo our damage. */
1866 arm_software_single_step (enum target_signal sig, int insert_bpt)
1868 static int next_pc; /* State between setting and unsetting. */
1869 static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
1873 next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
1874 target_insert_breakpoint (next_pc, break_mem);
1877 target_remove_breakpoint (next_pc, break_mem);
1880 #include "bfd-in2.h"
1881 #include "libcoff.h"
1884 gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
1886 if (arm_pc_is_thumb (memaddr))
1888 static asymbol *asym;
1889 static combined_entry_type ce;
1890 static struct coff_symbol_struct csym;
1891 static struct bfd fake_bfd;
1892 static bfd_target fake_target;
1894 if (csym.native == NULL)
1896 /* Create a fake symbol vector containing a Thumb symbol.
1897 This is solely so that the code in print_insn_little_arm()
1898 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1899 the presence of a Thumb symbol and switch to decoding
1900 Thumb instructions. */
1902 fake_target.flavour = bfd_target_coff_flavour;
1903 fake_bfd.xvec = &fake_target;
1904 ce.u.syment.n_sclass = C_THUMBEXTFUNC;
1906 csym.symbol.the_bfd = &fake_bfd;
1907 csym.symbol.name = "fake";
1908 asym = (asymbol *) & csym;
1911 memaddr = UNMAKE_THUMB_ADDR (memaddr);
1912 info->symbols = &asym;
1915 info->symbols = NULL;
1917 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1918 return print_insn_big_arm (memaddr, info);
1920 return print_insn_little_arm (memaddr, info);
1923 /* The following define instruction sequences that will cause ARM
1924 cpu's to take an undefined instruction trap. These are used to
1925 signal a breakpoint to GDB.
1927 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1928 modes. A different instruction is required for each mode. The ARM
1929 cpu's can also be big or little endian. Thus four different
1930 instructions are needed to support all cases.
1932 Note: ARMv4 defines several new instructions that will take the
1933 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1934 not in fact add the new instructions. The new undefined
1935 instructions in ARMv4 are all instructions that had no defined
1936 behaviour in earlier chips. There is no guarantee that they will
1937 raise an exception, but may be treated as NOP's. In practice, it
1938 may only safe to rely on instructions matching:
1940 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1941 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1942 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1944 Even this may only true if the condition predicate is true. The
1945 following use a condition predicate of ALWAYS so it is always TRUE.
1947 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1948 and NetBSD all use a software interrupt rather than an undefined
1949 instruction to force a trap. This can be handled by by the
1950 abi-specific code during establishment of the gdbarch vector. */
1953 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1954 override these definitions. */
1955 #ifndef ARM_LE_BREAKPOINT
1956 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1958 #ifndef ARM_BE_BREAKPOINT
1959 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1961 #ifndef THUMB_LE_BREAKPOINT
1962 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1964 #ifndef THUMB_BE_BREAKPOINT
1965 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1968 static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
1969 static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
1970 static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
1971 static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
1973 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1974 the program counter value to determine whether a 16-bit or 32-bit
1975 breakpoint should be used. It returns a pointer to a string of
1976 bytes that encode a breakpoint instruction, stores the length of
1977 the string to *lenptr, and adjusts the program counter (if
1978 necessary) to point to the actual memory location where the
1979 breakpoint should be inserted. */
1981 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
1982 breakpoints and storing their handles instread of what was in
1983 memory. It is nice that this is the same size as a handle -
1984 otherwise remote-rdp will have to change. */
1986 static const unsigned char *
1987 arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
1989 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1991 if (arm_pc_is_thumb (*pcptr))
1993 *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
1994 *lenptr = tdep->thumb_breakpoint_size;
1995 return tdep->thumb_breakpoint;
1999 *lenptr = tdep->arm_breakpoint_size;
2000 return tdep->arm_breakpoint;
2004 /* Extract from an array REGBUF containing the (raw) register state a
2005 function return value of type TYPE, and copy that, in virtual
2006 format, into VALBUF. */
2009 arm_extract_return_value (struct type *type,
2010 struct regcache *regs,
2013 bfd_byte *valbuf = dst;
2015 if (TYPE_CODE_FLT == TYPE_CODE (type))
2017 switch (arm_get_fp_model (current_gdbarch))
2021 /* The value is in register F0 in internal format. We need to
2022 extract the raw value and then convert it to the desired
2024 bfd_byte tmpbuf[FP_REGISTER_SIZE];
2026 regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
2027 convert_from_extended (floatformat_from_type (type), tmpbuf,
2032 case ARM_FLOAT_SOFT_FPA:
2033 case ARM_FLOAT_SOFT_VFP:
2034 regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
2035 if (TYPE_LENGTH (type) > 4)
2036 regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
2037 valbuf + INT_REGISTER_SIZE);
2042 (__FILE__, __LINE__,
2043 "arm_extract_return_value: Floating point model not supported");
2047 else if (TYPE_CODE (type) == TYPE_CODE_INT
2048 || TYPE_CODE (type) == TYPE_CODE_CHAR
2049 || TYPE_CODE (type) == TYPE_CODE_BOOL
2050 || TYPE_CODE (type) == TYPE_CODE_PTR
2051 || TYPE_CODE (type) == TYPE_CODE_REF
2052 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2054 /* If the the type is a plain integer, then the access is
2055 straight-forward. Otherwise we have to play around a bit more. */
2056 int len = TYPE_LENGTH (type);
2057 int regno = ARM_A1_REGNUM;
2062 /* By using store_unsigned_integer we avoid having to do
2063 anything special for small big-endian values. */
2064 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2065 store_unsigned_integer (valbuf,
2066 (len > INT_REGISTER_SIZE
2067 ? INT_REGISTER_SIZE : len),
2069 len -= INT_REGISTER_SIZE;
2070 valbuf += INT_REGISTER_SIZE;
2075 /* For a structure or union the behaviour is as if the value had
2076 been stored to word-aligned memory and then loaded into
2077 registers with 32-bit load instruction(s). */
2078 int len = TYPE_LENGTH (type);
2079 int regno = ARM_A1_REGNUM;
2080 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2084 regcache_cooked_read (regs, regno++, tmpbuf);
2085 memcpy (valbuf, tmpbuf,
2086 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2087 len -= INT_REGISTER_SIZE;
2088 valbuf += INT_REGISTER_SIZE;
2093 /* Extract from an array REGBUF containing the (raw) register state
2094 the address in which a function should return its structure value. */
2097 arm_extract_struct_value_address (struct regcache *regcache)
2101 regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret);
2105 /* Will a function return an aggregate type in memory or in a
2106 register? Return 0 if an aggregate type can be returned in a
2107 register, 1 if it must be returned in memory. */
2110 arm_use_struct_convention (int gcc_p, struct type *type)
2113 enum type_code code;
2115 CHECK_TYPEDEF (type);
2117 /* In the ARM ABI, "integer" like aggregate types are returned in
2118 registers. For an aggregate type to be integer like, its size
2119 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2120 offset of each addressable subfield must be zero. Note that bit
2121 fields are not addressable, and all addressable subfields of
2122 unions always start at offset zero.
2124 This function is based on the behaviour of GCC 2.95.1.
2125 See: gcc/arm.c: arm_return_in_memory() for details.
2127 Note: All versions of GCC before GCC 2.95.2 do not set up the
2128 parameters correctly for a function returning the following
2129 structure: struct { float f;}; This should be returned in memory,
2130 not a register. Richard Earnshaw sent me a patch, but I do not
2131 know of any way to detect if a function like the above has been
2132 compiled with the correct calling convention. */
2134 /* All aggregate types that won't fit in a register must be returned
2136 if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE)
2141 /* The only aggregate types that can be returned in a register are
2142 structs and unions. Arrays must be returned in memory. */
2143 code = TYPE_CODE (type);
2144 if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code))
2149 /* Assume all other aggregate types can be returned in a register.
2150 Run a check for structures, unions and arrays. */
2153 if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code))
2156 /* Need to check if this struct/union is "integer" like. For
2157 this to be true, its size must be less than or equal to
2158 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2159 subfield must be zero. Note that bit fields are not
2160 addressable, and unions always start at offset zero. If any
2161 of the subfields is a floating point type, the struct/union
2162 cannot be an integer type. */
2164 /* For each field in the object, check:
2165 1) Is it FP? --> yes, nRc = 1;
2166 2) Is it addressable (bitpos != 0) and
2167 not packed (bitsize == 0)?
2171 for (i = 0; i < TYPE_NFIELDS (type); i++)
2173 enum type_code field_type_code;
2174 field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
2176 /* Is it a floating point type field? */
2177 if (field_type_code == TYPE_CODE_FLT)
2183 /* If bitpos != 0, then we have to care about it. */
2184 if (TYPE_FIELD_BITPOS (type, i) != 0)
2186 /* Bitfields are not addressable. If the field bitsize is
2187 zero, then the field is not packed. Hence it cannot be
2188 a bitfield or any other packed type. */
2189 if (TYPE_FIELD_BITSIZE (type, i) == 0)
2201 /* Write into appropriate registers a function return value of type
2202 TYPE, given in virtual format. */
2205 arm_store_return_value (struct type *type, struct regcache *regs,
2208 const bfd_byte *valbuf = src;
2210 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2212 char buf[MAX_REGISTER_SIZE];
2214 switch (arm_get_fp_model (current_gdbarch))
2218 convert_to_extended (floatformat_from_type (type), buf, valbuf);
2219 regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
2222 case ARM_FLOAT_SOFT_FPA:
2223 case ARM_FLOAT_SOFT_VFP:
2224 regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
2225 if (TYPE_LENGTH (type) > 4)
2226 regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
2227 valbuf + INT_REGISTER_SIZE);
2232 (__FILE__, __LINE__,
2233 "arm_store_return_value: Floating point model not supported");
2237 else if (TYPE_CODE (type) == TYPE_CODE_INT
2238 || TYPE_CODE (type) == TYPE_CODE_CHAR
2239 || TYPE_CODE (type) == TYPE_CODE_BOOL
2240 || TYPE_CODE (type) == TYPE_CODE_PTR
2241 || TYPE_CODE (type) == TYPE_CODE_REF
2242 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2244 if (TYPE_LENGTH (type) <= 4)
2246 /* Values of one word or less are zero/sign-extended and
2248 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2249 LONGEST val = unpack_long (type, valbuf);
2251 store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
2252 regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
2256 /* Integral values greater than one word are stored in consecutive
2257 registers starting with r0. This will always be a multiple of
2258 the regiser size. */
2259 int len = TYPE_LENGTH (type);
2260 int regno = ARM_A1_REGNUM;
2264 regcache_cooked_write (regs, regno++, valbuf);
2265 len -= INT_REGISTER_SIZE;
2266 valbuf += INT_REGISTER_SIZE;
2272 /* For a structure or union the behaviour is as if the value had
2273 been stored to word-aligned memory and then loaded into
2274 registers with 32-bit load instruction(s). */
2275 int len = TYPE_LENGTH (type);
2276 int regno = ARM_A1_REGNUM;
2277 bfd_byte tmpbuf[INT_REGISTER_SIZE];
2281 memcpy (tmpbuf, valbuf,
2282 len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
2283 regcache_cooked_write (regs, regno++, tmpbuf);
2284 len -= INT_REGISTER_SIZE;
2285 valbuf += INT_REGISTER_SIZE;
2291 arm_get_longjmp_target (CORE_ADDR *pc)
2294 char buf[INT_REGISTER_SIZE];
2295 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2297 jb_addr = read_register (ARM_A1_REGNUM);
2299 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2303 *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
2307 /* Return non-zero if the PC is inside a thumb call thunk. */
2310 arm_in_call_stub (CORE_ADDR pc, char *name)
2312 CORE_ADDR start_addr;
2314 /* Find the starting address of the function containing the PC. If
2315 the caller didn't give us a name, look it up at the same time. */
2316 if (0 == find_pc_partial_function (pc, name ? NULL : &name,
2320 return strncmp (name, "_call_via_r", 11) == 0;
2323 /* If PC is in a Thumb call or return stub, return the address of the
2324 target PC, which is in a register. The thunk functions are called
2325 _called_via_xx, where x is the register name. The possible names
2326 are r0-r9, sl, fp, ip, sp, and lr. */
2329 arm_skip_stub (CORE_ADDR pc)
2332 CORE_ADDR start_addr;
2334 /* Find the starting address and name of the function containing the PC. */
2335 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2338 /* Call thunks always start with "_call_via_". */
2339 if (strncmp (name, "_call_via_", 10) == 0)
2341 /* Use the name suffix to determine which register contains the
2343 static char *table[15] =
2344 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2345 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2349 for (regno = 0; regno <= 14; regno++)
2350 if (strcmp (&name[10], table[regno]) == 0)
2351 return read_register (regno);
2354 return 0; /* not a stub */
2358 set_arm_command (char *args, int from_tty)
2360 printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
2361 help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
2365 show_arm_command (char *args, int from_tty)
2367 cmd_show_list (showarmcmdlist, from_tty, "");
2370 enum arm_float_model
2371 arm_get_fp_model (struct gdbarch *gdbarch)
2373 if (arm_fp_model == ARM_FLOAT_AUTO)
2374 return gdbarch_tdep (gdbarch)->fp_model;
2376 return arm_fp_model;
2380 arm_set_fp (struct gdbarch *gdbarch)
2382 enum arm_float_model fp_model = arm_get_fp_model (gdbarch);
2384 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2385 && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA))
2387 set_gdbarch_double_format (gdbarch,
2388 &floatformat_ieee_double_littlebyte_bigword);
2389 set_gdbarch_long_double_format
2390 (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
2394 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
2395 set_gdbarch_long_double_format (gdbarch,
2396 &floatformat_ieee_double_little);
2401 set_fp_model_sfunc (char *args, int from_tty,
2402 struct cmd_list_element *c)
2404 enum arm_float_model fp_model;
2406 for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++)
2407 if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0)
2409 arm_fp_model = fp_model;
2413 if (fp_model == ARM_FLOAT_LAST)
2414 internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.",
2417 if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2418 arm_set_fp (current_gdbarch);
2422 show_fp_model (char *args, int from_tty,
2423 struct cmd_list_element *c)
2425 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2427 if (arm_fp_model == ARM_FLOAT_AUTO
2428 && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
2429 printf_filtered (" - the default for the current ABI is \"%s\".\n",
2430 fp_model_strings[tdep->fp_model]);
2433 /* If the user changes the register disassembly style used for info
2434 register and other commands, we have to also switch the style used
2435 in opcodes for disassembly output. This function is run in the "set
2436 arm disassembly" command, and does that. */
2439 set_disassembly_style_sfunc (char *args, int from_tty,
2440 struct cmd_list_element *c)
2442 set_disassembly_style ();
2445 /* Return the ARM register name corresponding to register I. */
2447 arm_register_name (int i)
2449 return arm_register_names[i];
2453 set_disassembly_style (void)
2455 const char *setname, *setdesc, **regnames;
2458 /* Find the style that the user wants in the opcodes table. */
2460 numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
2461 while ((disassembly_style != setname)
2462 && (current < num_disassembly_options))
2463 get_arm_regnames (++current, &setname, &setdesc, ®names);
2464 current_option = current;
2466 /* Fill our copy. */
2467 for (j = 0; j < numregs; j++)
2468 arm_register_names[j] = (char *) regnames[j];
2471 if (isupper (*regnames[ARM_PC_REGNUM]))
2473 arm_register_names[ARM_FPS_REGNUM] = "FPS";
2474 arm_register_names[ARM_PS_REGNUM] = "CPSR";
2478 arm_register_names[ARM_FPS_REGNUM] = "fps";
2479 arm_register_names[ARM_PS_REGNUM] = "cpsr";
2482 /* Synchronize the disassembler. */
2483 set_arm_regname_option (current);
2486 /* arm_othernames implements the "othernames" command. This is deprecated
2487 by the "set arm disassembly" command. */
2490 arm_othernames (char *names, int n)
2492 /* Circle through the various flavors. */
2493 current_option = (current_option + 1) % num_disassembly_options;
2495 disassembly_style = valid_disassembly_styles[current_option];
2496 set_disassembly_style ();
2499 /* Test whether the coff symbol specific value corresponds to a Thumb
2503 coff_sym_is_thumb (int val)
2505 return (val == C_THUMBEXT ||
2506 val == C_THUMBSTAT ||
2507 val == C_THUMBEXTFUNC ||
2508 val == C_THUMBSTATFUNC ||
2509 val == C_THUMBLABEL);
2512 /* arm_coff_make_msymbol_special()
2513 arm_elf_make_msymbol_special()
2515 These functions test whether the COFF or ELF symbol corresponds to
2516 an address in thumb code, and set a "special" bit in a minimal
2517 symbol to indicate that it does. */
2520 arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym)
2522 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2524 if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info)
2526 MSYMBOL_SET_SPECIAL (msym);
2530 arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym)
2532 if (coff_sym_is_thumb (val))
2533 MSYMBOL_SET_SPECIAL (msym);
2537 arm_write_pc (CORE_ADDR pc, ptid_t ptid)
2539 write_register_pid (ARM_PC_REGNUM, pc, ptid);
2541 /* If necessary, set the T bit. */
2544 CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid);
2545 if (arm_pc_is_thumb (pc))
2546 write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid);
2548 write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid);
2552 static enum gdb_osabi
2553 arm_elf_osabi_sniffer (bfd *abfd)
2555 unsigned int elfosabi, eflags;
2556 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
2558 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2563 /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
2564 file are conforming to the base specification for that machine
2565 (there are no OS-specific extensions). In order to determine the
2566 real OS in use we must look for OS notes that have been added. */
2567 bfd_map_over_sections (abfd,
2568 generic_elf_osabi_sniff_abi_tag_sections,
2570 if (osabi == GDB_OSABI_UNKNOWN)
2572 /* Existing ARM tools don't set this field, so look at the EI_FLAGS
2573 field for more information. */
2574 eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
2577 case EF_ARM_EABI_VER1:
2578 osabi = GDB_OSABI_ARM_EABI_V1;
2581 case EF_ARM_EABI_VER2:
2582 osabi = GDB_OSABI_ARM_EABI_V2;
2585 case EF_ARM_EABI_VER3:
2586 case EF_ARM_EABI_VER4:
2587 case EF_ARM_EABI_VER5:
2589 * GDB does not support these EABI versions. Fallback
2590 * to the highest known to make the KGDB working with
2593 osabi = GDB_OSABI_ARM_EABI_V2;
2595 "arm_elf_osabi_sniffer: Unsupported ARM EABI "
2596 "version 0x%x, falling back to 0x%x\n",
2597 __FILE__, __LINE__, eflags, EF_ARM_EABI_VER2);
2600 case EF_ARM_EABI_UNKNOWN:
2601 /* Assume GNU tools. */
2602 osabi = GDB_OSABI_ARM_APCS;
2606 internal_error (__FILE__, __LINE__,
2607 "arm_elf_osabi_sniffer: Unknown ARM EABI "
2608 "version 0x%x", eflags);
2614 /* GNU tools use this value. Check note sections in this case,
2616 bfd_map_over_sections (abfd,
2617 generic_elf_osabi_sniff_abi_tag_sections,
2619 if (osabi == GDB_OSABI_UNKNOWN)
2621 /* Assume APCS ABI. */
2622 osabi = GDB_OSABI_ARM_APCS;
2626 case ELFOSABI_FREEBSD:
2627 osabi = GDB_OSABI_FREEBSD_ELF;
2630 case ELFOSABI_NETBSD:
2631 osabi = GDB_OSABI_NETBSD_ELF;
2634 case ELFOSABI_LINUX:
2635 osabi = GDB_OSABI_LINUX;
2643 /* Initialize the current architecture based on INFO. If possible,
2644 re-use an architecture from ARCHES, which is a list of
2645 architectures already created during this debugging session.
2647 Called e.g. at program startup, when reading a core file, and when
2648 reading a binary file. */
2650 static struct gdbarch *
2651 arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2653 struct gdbarch_tdep *tdep;
2654 struct gdbarch *gdbarch;
2656 /* Try to deterimine the ABI of the object we are loading. */
2658 if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN)
2660 switch (bfd_get_flavour (info.abfd))
2662 case bfd_target_aout_flavour:
2663 /* Assume it's an old APCS-style ABI. */
2664 info.osabi = GDB_OSABI_ARM_APCS;
2667 case bfd_target_coff_flavour:
2668 /* Assume it's an old APCS-style ABI. */
2670 info.osabi = GDB_OSABI_ARM_APCS;
2674 /* Leave it as "unknown". */
2679 /* If there is already a candidate, use it. */
2680 arches = gdbarch_list_lookup_by_info (arches, &info);
2682 return arches->gdbarch;
2684 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2685 gdbarch = gdbarch_alloc (&info, tdep);
2687 /* We used to default to FPA for generic ARM, but almost nobody uses that
2688 now, and we now provide a way for the user to force the model. So
2689 default to the most useful variant. */
2690 tdep->fp_model = ARM_FLOAT_SOFT_FPA;
2693 switch (info.byte_order)
2695 case BFD_ENDIAN_BIG:
2696 tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
2697 tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint);
2698 tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint;
2699 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint);
2703 case BFD_ENDIAN_LITTLE:
2704 tdep->arm_breakpoint = arm_default_arm_le_breakpoint;
2705 tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint);
2706 tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint;
2707 tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint);
2712 internal_error (__FILE__, __LINE__,
2713 "arm_gdbarch_init: bad byte order for float format");
2716 /* On ARM targets char defaults to unsigned. */
2717 set_gdbarch_char_signed (gdbarch, 0);
2719 /* This should be low enough for everything. */
2720 tdep->lowest_pc = 0x20;
2721 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
2723 set_gdbarch_deprecated_call_dummy_words (gdbarch, arm_call_dummy_words);
2724 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, 0);
2726 set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
2728 set_gdbarch_write_pc (gdbarch, arm_write_pc);
2730 /* Frame handling. */
2731 set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id);
2732 set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
2733 set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
2735 set_gdbarch_deprecated_frameless_function_invocation (gdbarch, arm_frameless_function_invocation);
2737 frame_base_set_default (gdbarch, &arm_normal_base);
2739 /* Address manipulation. */
2740 set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
2741 set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
2743 /* Advance PC across function entry code. */
2744 set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
2746 /* Get the PC when a frame might not be available. */
2747 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
2749 /* The stack grows downward. */
2750 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2752 /* Breakpoint manipulation. */
2753 set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
2755 /* Information about registers, etc. */
2756 set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
2757 set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
2758 set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
2759 set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
2760 set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte);
2761 set_gdbarch_deprecated_register_bytes (gdbarch,
2762 (NUM_GREGS * INT_REGISTER_SIZE
2763 + NUM_FREGS * FP_REGISTER_SIZE
2764 + NUM_SREGS * STATUS_REGISTER_SIZE));
2765 set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
2766 set_gdbarch_register_type (gdbarch, arm_register_type);
2768 /* Internal <-> external register number maps. */
2769 set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
2771 /* Integer registers are 4 bytes. */
2772 set_gdbarch_deprecated_register_size (gdbarch, 4);
2773 set_gdbarch_register_name (gdbarch, arm_register_name);
2775 /* Returning results. */
2776 set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value);
2777 set_gdbarch_store_return_value (gdbarch, arm_store_return_value);
2778 set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention);
2779 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address);
2781 /* Single stepping. */
2782 /* XXX For an RDI target we should ask the target if it can single-step. */
2783 set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
2786 set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
2788 /* Minsymbol frobbing. */
2789 set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
2790 set_gdbarch_coff_make_msymbol_special (gdbarch,
2791 arm_coff_make_msymbol_special);
2793 /* Hook in the ABI-specific overrides, if they have been registered. */
2794 gdbarch_init_osabi (info, gdbarch);
2796 /* Add some default predicates. */
2797 frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer);
2798 frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer);
2800 /* Now we have tuned the configuration, set a few final things,
2801 based on what the OS ABI has told us. */
2803 if (tdep->jb_pc >= 0)
2804 set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
2806 /* Floating point sizes and format. */
2807 switch (info.byte_order)
2809 case BFD_ENDIAN_BIG:
2810 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
2811 set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
2812 set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
2816 case BFD_ENDIAN_LITTLE:
2817 set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
2818 arm_set_fp (gdbarch);
2822 internal_error (__FILE__, __LINE__,
2823 "arm_gdbarch_init: bad byte order for float format");
2830 arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2832 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2837 fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx",
2838 (unsigned long) tdep->lowest_pc);
2842 arm_init_abi_eabi_v1 (struct gdbarch_info info,
2843 struct gdbarch *gdbarch)
2849 arm_init_abi_eabi_v2 (struct gdbarch_info info,
2850 struct gdbarch *gdbarch)
2856 arm_init_abi_apcs (struct gdbarch_info info,
2857 struct gdbarch *gdbarch)
2862 extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
2865 _initialize_arm_tdep (void)
2867 struct ui_file *stb;
2869 struct cmd_list_element *new_set, *new_show;
2870 const char *setname;
2871 const char *setdesc;
2872 const char **regnames;
2874 static char *helptext;
2876 gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
2878 /* Register an ELF OS ABI sniffer for ARM binaries. */
2879 gdbarch_register_osabi_sniffer (bfd_arch_arm,
2880 bfd_target_elf_flavour,
2881 arm_elf_osabi_sniffer);
2883 /* Register some ABI variants for embedded systems. */
2884 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1,
2885 arm_init_abi_eabi_v1);
2886 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2,
2887 arm_init_abi_eabi_v2);
2888 gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS,
2891 /* Get the number of possible sets of register names defined in opcodes. */
2892 num_disassembly_options = get_arm_regname_num_options ();
2894 /* Add root prefix command for all "set arm"/"show arm" commands. */
2895 add_prefix_cmd ("arm", no_class, set_arm_command,
2896 "Various ARM-specific commands.",
2897 &setarmcmdlist, "set arm ", 0, &setlist);
2899 add_prefix_cmd ("arm", no_class, show_arm_command,
2900 "Various ARM-specific commands.",
2901 &showarmcmdlist, "show arm ", 0, &showlist);
2903 /* Sync the opcode insn printer with our register viewer. */
2904 parse_arm_disassembler_option ("reg-names-std");
2906 /* Begin creating the help text. */
2907 stb = mem_fileopen ();
2908 fprintf_unfiltered (stb, "Set the disassembly style.\n"
2909 "The valid values are:\n");
2911 /* Initialize the array that will be passed to add_set_enum_cmd(). */
2912 valid_disassembly_styles
2913 = xmalloc ((num_disassembly_options + 1) * sizeof (char *));
2914 for (i = 0; i < num_disassembly_options; i++)
2916 numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
2917 valid_disassembly_styles[i] = setname;
2918 fprintf_unfiltered (stb, "%s - %s\n", setname,
2920 /* Copy the default names (if found) and synchronize disassembler. */
2921 if (!strcmp (setname, "std"))
2923 disassembly_style = setname;
2925 for (j = 0; j < numregs; j++)
2926 arm_register_names[j] = (char *) regnames[j];
2927 set_arm_regname_option (i);
2930 /* Mark the end of valid options. */
2931 valid_disassembly_styles[num_disassembly_options] = NULL;
2933 /* Finish the creation of the help text. */
2934 fprintf_unfiltered (stb, "The default is \"std\".");
2935 helptext = ui_file_xstrdup (stb, &length);
2936 ui_file_delete (stb);
2938 /* Add the deprecated disassembly-flavor command. */
2939 new_set = add_set_enum_cmd ("disassembly-flavor", no_class,
2940 valid_disassembly_styles,
2944 set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
2945 deprecate_cmd (new_set, "set arm disassembly");
2946 deprecate_cmd (add_show_from_set (new_set, &showlist),
2947 "show arm disassembly");
2949 /* And now add the new interface. */
2950 new_set = add_set_enum_cmd ("disassembler", no_class,
2951 valid_disassembly_styles, &disassembly_style,
2952 helptext, &setarmcmdlist);
2954 set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
2955 add_show_from_set (new_set, &showarmcmdlist);
2957 add_setshow_cmd_full ("apcs32", no_class,
2958 var_boolean, (char *) &arm_apcs_32,
2959 "Set usage of ARM 32-bit mode.",
2960 "Show usage of ARM 32-bit mode.",
2962 &setlist, &showlist, &new_set, &new_show);
2963 deprecate_cmd (new_set, "set arm apcs32");
2964 deprecate_cmd (new_show, "show arm apcs32");
2966 add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
2967 "Set usage of ARM 32-bit mode. "
2968 "When off, a 26-bit PC will be used.",
2969 "Show usage of ARM 32-bit mode. "
2970 "When off, a 26-bit PC will be used.",
2972 &setarmcmdlist, &showarmcmdlist);
2974 /* Add a command to allow the user to force the FPU model. */
2975 new_set = add_set_enum_cmd
2976 ("fpu", no_class, fp_model_strings, ¤t_fp_model,
2977 "Set the floating point type.\n"
2978 "auto - Determine the FP typefrom the OS-ABI.\n"
2979 "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
2980 "fpa - FPA co-processor (GCC compiled).\n"
2981 "softvfp - Software FP with pure-endian doubles.\n"
2982 "vfp - VFP co-processor.",
2984 set_cmd_sfunc (new_set, set_fp_model_sfunc);
2985 set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model);
2987 /* Add the deprecated "othernames" command. */
2988 deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames,
2989 "Switch to the next set of register names."),
2990 "set arm disassembly");
2992 /* Debugging flag. */
2993 add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
2994 "Set ARM debugging. "
2995 "When on, arm-specific debugging is enabled.",
2996 "Show ARM debugging. "
2997 "When on, arm-specific debugging is enabled.",
2999 &setdebuglist, &showdebuglist);