1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 static const struct objfile_data *mips_pdr_data;
59 static void set_reg_offset (CORE_ADDR *saved_regs, int regnum, CORE_ADDR off);
60 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
62 /* A useful bit in the CP0 status register (PS_REGNUM). */
63 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
64 #define ST0_FR (1 << 26)
66 /* The sizes of floating point registers. */
70 MIPS_FPU_SINGLE_REGSIZE = 4,
71 MIPS_FPU_DOUBLE_REGSIZE = 8
75 static const char *mips_abi_string;
77 static const char *mips_abi_strings[] = {
88 struct frame_extra_info
90 mips_extra_func_info_t proc_desc;
94 /* Various MIPS ISA options (related to stack analysis) can be
95 overridden dynamically. Establish an enum/array for managing
98 static const char size_auto[] = "auto";
99 static const char size_32[] = "32";
100 static const char size_64[] = "64";
102 static const char *size_enums[] = {
109 /* Some MIPS boards don't support floating point while others only
110 support single-precision floating-point operations. See also
111 FP_REGISTER_DOUBLE. */
115 MIPS_FPU_DOUBLE, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE /* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto = 1;
124 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
126 static int mips_debug = 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi;
136 enum mips_abi found_abi;
137 enum mips_fpu_type mips_fpu_type;
138 int mips_last_arg_regnum;
139 int mips_last_fp_arg_regnum;
140 int mips_default_saved_regsize;
141 int mips_fp_register_double;
142 int mips_default_stack_argsize;
143 int default_mask_address_p;
144 /* Is the target using 64-bit raw integer registers but only
145 storing a left-aligned 32-bit value in each? */
146 int mips64_transfers_32bit_regs_p;
147 /* Indexes for various registers. IRIX and embedded have
148 different values. This contains the "public" fields. Don't
149 add any that do not need to be public. */
150 const struct mips_regnum *regnum;
151 /* Register names table for the current register set. */
152 const char **mips_processor_reg_names;
155 const struct mips_regnum *
156 mips_regnum (struct gdbarch *gdbarch)
158 return gdbarch_tdep (gdbarch)->regnum;
162 mips_fpa0_regnum (struct gdbarch *gdbarch)
164 return mips_regnum (gdbarch)->fp0 + 12;
167 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
168 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
170 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
172 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
174 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
176 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
177 functions to test, set, or clear bit 0 of addresses. */
180 is_mips16_addr (CORE_ADDR addr)
186 make_mips16_addr (CORE_ADDR addr)
192 unmake_mips16_addr (CORE_ADDR addr)
194 return ((addr) & ~1);
197 /* Return the contents of register REGNUM as a signed integer. */
200 read_signed_register (int regnum)
202 void *buf = alloca (register_size (current_gdbarch, regnum));
203 deprecated_read_register_gen (regnum, buf);
204 return (extract_signed_integer
205 (buf, register_size (current_gdbarch, regnum)));
209 read_signed_register_pid (int regnum, ptid_t ptid)
214 if (ptid_equal (ptid, inferior_ptid))
215 return read_signed_register (regnum);
217 save_ptid = inferior_ptid;
219 inferior_ptid = ptid;
221 retval = read_signed_register (regnum);
223 inferior_ptid = save_ptid;
228 /* Return the MIPS ABI associated with GDBARCH. */
230 mips_abi (struct gdbarch *gdbarch)
232 return gdbarch_tdep (gdbarch)->mips_abi;
236 mips_regsize (struct gdbarch *gdbarch)
238 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word
239 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte);
242 /* Return the currently configured (or set) saved register size. */
244 static const char *mips_saved_regsize_string = size_auto;
247 mips_saved_regsize (struct gdbarch_tdep *tdep)
249 if (mips_saved_regsize_string == size_auto)
250 return tdep->mips_default_saved_regsize;
251 else if (mips_saved_regsize_string == size_64)
253 else /* if (mips_saved_regsize_string == size_32) */
257 /* Functions for setting and testing a bit in a minimal symbol that
258 marks it as 16-bit function. The MSB of the minimal symbol's
259 "info" field is used for this purpose.
261 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
262 i.e. refers to a 16-bit function, and sets a "special" bit in a
263 minimal symbol to mark it as a 16-bit function
265 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
268 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym)
270 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16)
272 MSYMBOL_INFO (msym) = (char *)
273 (((long) MSYMBOL_INFO (msym)) | 0x80000000);
274 SYMBOL_VALUE_ADDRESS (msym) |= 1;
279 msymbol_is_special (struct minimal_symbol *msym)
281 return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0);
284 /* XFER a value from the big/little/left end of the register.
285 Depending on the size of the value it might occupy the entire
286 register or just part of it. Make an allowance for this, aligning
287 things accordingly. */
290 mips_xfer_register (struct regcache *regcache, int reg_num, int length,
291 enum bfd_endian endian, bfd_byte * in,
292 const bfd_byte * out, int buf_offset)
295 gdb_assert (reg_num >= NUM_REGS);
296 /* Need to transfer the left or right part of the register, based on
297 the targets byte order. */
301 reg_offset = register_size (current_gdbarch, reg_num) - length;
303 case BFD_ENDIAN_LITTLE:
306 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */
310 internal_error (__FILE__, __LINE__, "bad switch");
313 fprintf_unfiltered (gdb_stderr,
314 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
315 reg_num, reg_offset, buf_offset, length);
316 if (mips_debug && out != NULL)
319 fprintf_unfiltered (gdb_stdlog, "out ");
320 for (i = 0; i < length; i++)
321 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
324 regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
327 regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
329 if (mips_debug && in != NULL)
332 fprintf_unfiltered (gdb_stdlog, "in ");
333 for (i = 0; i < length; i++)
334 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
337 fprintf_unfiltered (gdb_stdlog, "\n");
340 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
341 compatiblity mode. A return value of 1 means that we have
342 physical 64-bit registers, but should treat them as 32-bit registers. */
345 mips2_fp_compat (void)
347 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
349 if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) ==
354 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
355 in all the places we deal with FP registers. PR gdb/413. */
356 /* Otherwise check the FR bit in the status register - it controls
357 the FP compatiblity mode. If it is clear we are in compatibility
359 if ((read_register (PS_REGNUM) & ST0_FR) == 0)
366 /* Indicate that the ABI makes use of double-precision registers
367 provided by the FPU (rather than combining pairs of registers to
368 form double-precision values). See also MIPS_FPU_TYPE. */
369 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
371 /* The amount of space reserved on the stack for registers. This is
372 different to MIPS_SAVED_REGSIZE as it determines the alignment of
373 data allocated after the registers have run out. */
375 static const char *mips_stack_argsize_string = size_auto;
378 mips_stack_argsize (struct gdbarch_tdep *tdep)
380 if (mips_stack_argsize_string == size_auto)
381 return tdep->mips_default_stack_argsize;
382 else if (mips_stack_argsize_string == size_64)
384 else /* if (mips_stack_argsize_string == size_32) */
388 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
390 static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR,
391 struct frame_info *, int);
393 static CORE_ADDR heuristic_proc_start (CORE_ADDR);
395 static CORE_ADDR read_next_frame_reg (struct frame_info *, int);
397 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
399 static mips_extra_func_info_t find_proc_desc (CORE_ADDR pc,
400 struct frame_info *next_frame,
403 static CORE_ADDR after_prologue (CORE_ADDR pc,
404 mips_extra_func_info_t proc_desc);
406 static struct type *mips_float_register_type (void);
407 static struct type *mips_double_register_type (void);
409 /* The list of available "set mips " and "show mips " commands */
411 static struct cmd_list_element *setmipscmdlist = NULL;
412 static struct cmd_list_element *showmipscmdlist = NULL;
414 /* Integer registers 0 thru 31 are handled explicitly by
415 mips_register_name(). Processor specific registers 32 and above
416 are listed in the followign tables. */
419 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) };
423 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
424 "sr", "lo", "hi", "bad", "cause", "pc",
425 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
426 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
427 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
428 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
429 "fsr", "fir", "" /*"fp" */ , "",
430 "", "", "", "", "", "", "", "",
431 "", "", "", "", "", "", "", "",
434 /* Names of IDT R3041 registers. */
436 static const char *mips_r3041_reg_names[] = {
437 "sr", "lo", "hi", "bad", "cause", "pc",
438 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
439 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
440 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
441 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
442 "fsr", "fir", "", /*"fp" */ "",
443 "", "", "bus", "ccfg", "", "", "", "",
444 "", "", "port", "cmp", "", "", "epc", "prid",
447 /* Names of tx39 registers. */
449 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
450 "sr", "lo", "hi", "bad", "cause", "pc",
451 "", "", "", "", "", "", "", "",
452 "", "", "", "", "", "", "", "",
453 "", "", "", "", "", "", "", "",
454 "", "", "", "", "", "", "", "",
456 "", "", "", "", "", "", "", "",
457 "", "", "config", "cache", "debug", "depc", "epc", ""
460 /* Names of IRIX registers. */
461 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
462 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
463 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
464 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
465 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
466 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
470 /* Return the name of the register corresponding to REGNO. */
472 mips_register_name (int regno)
474 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
475 /* GPR names for all ABIs other than n32/n64. */
476 static char *mips_gpr_names[] = {
477 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
478 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
479 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
480 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
483 /* GPR names for n32 and n64 ABIs. */
484 static char *mips_n32_n64_gpr_names[] = {
485 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
486 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
487 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
488 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
491 enum mips_abi abi = mips_abi (current_gdbarch);
493 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
494 don't make the raw register names visible. */
495 int rawnum = regno % NUM_REGS;
496 if (regno < NUM_REGS)
499 /* The MIPS integer registers are always mapped from 0 to 31. The
500 names of the registers (which reflects the conventions regarding
501 register use) vary depending on the ABI. */
502 if (0 <= rawnum && rawnum < 32)
504 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64)
505 return mips_n32_n64_gpr_names[rawnum];
507 return mips_gpr_names[rawnum];
509 else if (32 <= rawnum && rawnum < NUM_REGS)
511 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS);
512 return tdep->mips_processor_reg_names[rawnum - 32];
515 internal_error (__FILE__, __LINE__,
516 "mips_register_name: bad register number %d", rawnum);
519 /* Return the groups that a MIPS register can be categorised into. */
522 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
523 struct reggroup *reggroup)
528 int rawnum = regnum % NUM_REGS;
529 int pseudo = regnum / NUM_REGS;
530 if (reggroup == all_reggroup)
532 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
533 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
534 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
535 (gdbarch), as not all architectures are multi-arch. */
536 raw_p = rawnum < NUM_REGS;
537 if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0')
539 if (reggroup == float_reggroup)
540 return float_p && pseudo;
541 if (reggroup == vector_reggroup)
542 return vector_p && pseudo;
543 if (reggroup == general_reggroup)
544 return (!vector_p && !float_p) && pseudo;
545 /* Save the pseudo registers. Need to make certain that any code
546 extracting register values from a saved register cache also uses
548 if (reggroup == save_reggroup)
549 return raw_p && pseudo;
550 /* Restore the same pseudo register. */
551 if (reggroup == restore_reggroup)
552 return raw_p && pseudo;
556 /* Map the symbol table registers which live in the range [1 *
557 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
558 registers. Take care of alignment and size problems. */
561 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
562 int cookednum, void *buf)
564 int rawnum = cookednum % NUM_REGS;
565 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
566 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
567 regcache_raw_read (regcache, rawnum, buf);
568 else if (register_size (gdbarch, rawnum) >
569 register_size (gdbarch, cookednum))
571 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
572 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
573 regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
575 regcache_raw_read_part (regcache, rawnum, 4, 4, buf);
578 internal_error (__FILE__, __LINE__, "bad register size");
582 mips_pseudo_register_write (struct gdbarch *gdbarch,
583 struct regcache *regcache, int cookednum,
586 int rawnum = cookednum % NUM_REGS;
587 gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS);
588 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
589 regcache_raw_write (regcache, rawnum, buf);
590 else if (register_size (gdbarch, rawnum) >
591 register_size (gdbarch, cookednum))
593 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
594 || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
595 regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
597 regcache_raw_write_part (regcache, rawnum, 4, 4, buf);
600 internal_error (__FILE__, __LINE__, "bad register size");
603 /* Table to translate MIPS16 register field to actual register number. */
604 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
606 /* Heuristic_proc_start may hunt through the text section for a long
607 time across a 2400 baud serial line. Allows the user to limit this
610 static unsigned int heuristic_fence_post = 0;
612 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
613 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
614 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
615 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
616 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
617 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
618 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
619 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
620 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
621 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
622 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
623 this will corrupt pdr.iline. Fortunately we don't use it. */
624 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
625 #define _PROC_MAGIC_ 0x0F0F0F0F
626 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
627 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
629 struct linked_proc_info
631 struct mips_extra_func_info info;
632 struct linked_proc_info *next;
634 *linked_proc_desc_table = NULL;
636 /* Number of bytes of storage in the actual machine representation for
637 register N. NOTE: This defines the pseudo register type so need to
638 rebuild the architecture vector. */
640 static int mips64_transfers_32bit_regs_p = 0;
643 set_mips64_transfers_32bit_regs (char *args, int from_tty,
644 struct cmd_list_element *c)
646 struct gdbarch_info info;
647 gdbarch_info_init (&info);
648 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
649 instead of relying on globals. Doing that would let generic code
650 handle the search for this specific architecture. */
651 if (!gdbarch_update_p (info))
653 mips64_transfers_32bit_regs_p = 0;
654 error ("32-bit compatibility mode not supported");
658 /* Convert to/from a register and the corresponding memory value. */
661 mips_convert_register_p (int regnum, struct type *type)
663 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
664 && register_size (current_gdbarch, regnum) == 4
665 && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
666 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32
667 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
671 mips_register_to_value (struct frame_info *frame, int regnum,
672 struct type *type, void *to)
674 get_frame_register (frame, regnum + 0, (char *) to + 4);
675 get_frame_register (frame, regnum + 1, (char *) to + 0);
679 mips_value_to_register (struct frame_info *frame, int regnum,
680 struct type *type, const void *from)
682 put_frame_register (frame, regnum + 0, (const char *) from + 4);
683 put_frame_register (frame, regnum + 1, (const char *) from + 0);
686 /* Return the GDB type object for the "standard" data type of data in
690 mips_register_type (struct gdbarch *gdbarch, int regnum)
692 gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS);
693 if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0
694 && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32)
696 /* The floating-point registers raw, or cooked, always match
697 mips_regsize(), and also map 1:1, byte for byte. */
698 switch (gdbarch_byte_order (gdbarch))
701 if (mips_regsize (gdbarch) == 4)
702 return builtin_type_ieee_single_big;
704 return builtin_type_ieee_double_big;
705 case BFD_ENDIAN_LITTLE:
706 if (mips_regsize (gdbarch) == 4)
707 return builtin_type_ieee_single_little;
709 return builtin_type_ieee_double_little;
710 case BFD_ENDIAN_UNKNOWN:
712 internal_error (__FILE__, __LINE__, "bad switch");
716 (NUM_REGS + mips_regnum (current_gdbarch)->fp_control_status)
717 && regnum <= NUM_REGS + LAST_EMBED_REGNUM)
718 /* The pseudo/cooked view of the embedded registers is always
719 32-bit. The raw view is handled below. */
720 return builtin_type_int32;
721 else if (regnum >= NUM_REGS && mips_regsize (gdbarch)
722 && gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
723 /* The target, while using a 64-bit register buffer, is only
724 transfering 32-bits of each integer register. Reflect this in
725 the cooked/pseudo register value. */
726 return builtin_type_int32;
727 else if (mips_regsize (gdbarch) == 8)
729 return builtin_type_int64;
732 return builtin_type_int32;
735 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
740 return read_signed_register (SP_REGNUM);
743 /* Should the upper word of 64-bit addresses be zeroed? */
744 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
747 mips_mask_address_p (struct gdbarch_tdep *tdep)
749 switch (mask_address_var)
751 case AUTO_BOOLEAN_TRUE:
753 case AUTO_BOOLEAN_FALSE:
756 case AUTO_BOOLEAN_AUTO:
757 return tdep->default_mask_address_p;
759 internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch");
765 show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c)
767 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
768 switch (mask_address_var)
770 case AUTO_BOOLEAN_TRUE:
771 printf_filtered ("The 32 bit mips address mask is enabled\n");
773 case AUTO_BOOLEAN_FALSE:
774 printf_filtered ("The 32 bit mips address mask is disabled\n");
776 case AUTO_BOOLEAN_AUTO:
778 ("The 32 bit address mask is set automatically. Currently %s\n",
779 mips_mask_address_p (tdep) ? "enabled" : "disabled");
782 internal_error (__FILE__, __LINE__, "show_mask_address: bad switch");
787 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
790 pc_is_mips16 (bfd_vma memaddr)
792 struct minimal_symbol *sym;
794 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
795 if (is_mips16_addr (memaddr))
798 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
799 the high bit of the info field. Use this to decide if the function is
800 MIPS16 or normal MIPS. */
801 sym = lookup_minimal_symbol_by_pc (memaddr);
803 return msymbol_is_special (sym);
808 /* MIPS believes that the PC has a sign extended value. Perhaphs the
809 all registers should be sign extended for simplicity? */
812 mips_read_pc (ptid_t ptid)
814 return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid);
818 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
820 return frame_unwind_register_signed (next_frame,
821 NUM_REGS + mips_regnum (gdbarch)->pc);
824 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
825 dummy frame. The frame ID's base needs to match the TOS value
826 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
829 static struct frame_id
830 mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
832 return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + SP_REGNUM),
833 frame_pc_unwind (next_frame));
837 mips_write_pc (CORE_ADDR pc, ptid_t ptid)
839 write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid);
842 /* This returns the PC of the first inst after the prologue. If we can't
843 find the prologue, then return 0. */
846 after_prologue (CORE_ADDR pc, mips_extra_func_info_t proc_desc)
848 struct symtab_and_line sal;
849 CORE_ADDR func_addr, func_end;
851 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
852 to read the stack pointer from the current machine state, because
853 the current machine state has nothing to do with the information
854 we need from the proc_desc; and the process may or may not exist
857 proc_desc = find_proc_desc (pc, NULL, 0);
861 /* If function is frameless, then we need to do it the hard way. I
862 strongly suspect that frameless always means prologueless... */
863 if (PROC_FRAME_REG (proc_desc) == SP_REGNUM
864 && PROC_FRAME_OFFSET (proc_desc) == 0)
868 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
869 return 0; /* Unknown */
871 sal = find_pc_line (func_addr, 0);
873 if (sal.end < func_end)
876 /* The line after the prologue is after the end of the function. In this
877 case, tell the caller to find the prologue the hard way. */
882 /* Decode a MIPS32 instruction that saves a register in the stack, and
883 set the appropriate bit in the general register mask or float register mask
884 to indicate which register is saved. This is a helper function
885 for mips_find_saved_regs. */
888 mips32_decode_reg_save (t_inst inst, unsigned long *gen_mask,
889 unsigned long *float_mask)
893 if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
894 || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
895 || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
897 /* It might be possible to use the instruction to
898 find the offset, rather than the code below which
899 is based on things being in a certain order in the
900 frame, but figuring out what the instruction's offset
901 is relative to might be a little tricky. */
902 reg = (inst & 0x001f0000) >> 16;
903 *gen_mask |= (1 << reg);
905 else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
906 || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
907 || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
910 reg = ((inst & 0x001f0000) >> 16);
911 *float_mask |= (1 << reg);
915 /* Decode a MIPS16 instruction that saves a register in the stack, and
916 set the appropriate bit in the general register or float register mask
917 to indicate which register is saved. This is a helper function
918 for mips_find_saved_regs. */
921 mips16_decode_reg_save (t_inst inst, unsigned long *gen_mask)
923 if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
925 int reg = mips16_to_32_reg[(inst & 0x700) >> 8];
926 *gen_mask |= (1 << reg);
928 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
930 int reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
931 *gen_mask |= (1 << reg);
933 else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */
934 || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
935 *gen_mask |= (1 << RA_REGNUM);
939 /* Fetch and return instruction from the specified location. If the PC
940 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
943 mips_fetch_instruction (CORE_ADDR addr)
945 char buf[MIPS_INSTLEN];
949 if (pc_is_mips16 (addr))
951 instlen = MIPS16_INSTLEN;
952 addr = unmake_mips16_addr (addr);
955 instlen = MIPS_INSTLEN;
956 status = read_memory_nobpt (addr, buf, instlen);
958 memory_error (status, addr);
959 return extract_unsigned_integer (buf, instlen);
963 mips16_fetch_instruction (CORE_ADDR addr)
965 char buf[MIPS_INSTLEN];
969 instlen = MIPS16_INSTLEN;
970 addr = unmake_mips16_addr (addr);
971 status = read_memory_nobpt (addr, buf, instlen);
973 memory_error (status, addr);
974 return extract_unsigned_integer (buf, instlen);
978 mips32_fetch_instruction (CORE_ADDR addr)
980 char buf[MIPS_INSTLEN];
983 instlen = MIPS_INSTLEN;
984 status = read_memory_nobpt (addr, buf, instlen);
986 memory_error (status, addr);
987 return extract_unsigned_integer (buf, instlen);
991 /* These the fields of 32 bit mips instructions */
992 #define mips32_op(x) (x >> 26)
993 #define itype_op(x) (x >> 26)
994 #define itype_rs(x) ((x >> 21) & 0x1f)
995 #define itype_rt(x) ((x >> 16) & 0x1f)
996 #define itype_immediate(x) (x & 0xffff)
998 #define jtype_op(x) (x >> 26)
999 #define jtype_target(x) (x & 0x03ffffff)
1001 #define rtype_op(x) (x >> 26)
1002 #define rtype_rs(x) ((x >> 21) & 0x1f)
1003 #define rtype_rt(x) ((x >> 16) & 0x1f)
1004 #define rtype_rd(x) ((x >> 11) & 0x1f)
1005 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1006 #define rtype_funct(x) (x & 0x3f)
1009 mips32_relative_offset (unsigned long inst)
1012 x = itype_immediate (inst);
1013 if (x & 0x8000) /* sign bit set */
1015 x |= 0xffff0000; /* sign extension */
1021 /* Determine whate to set a single step breakpoint while considering
1022 branch prediction */
1024 mips32_next_pc (CORE_ADDR pc)
1028 inst = mips_fetch_instruction (pc);
1029 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1031 if (itype_op (inst) >> 2 == 5)
1032 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1034 op = (itype_op (inst) & 0x03);
1044 goto greater_branch;
1049 else if (itype_op (inst) == 17 && itype_rs (inst) == 8)
1050 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1052 int tf = itype_rt (inst) & 0x01;
1053 int cnum = itype_rt (inst) >> 2;
1055 read_signed_register (mips_regnum (current_gdbarch)->
1057 int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01);
1059 if (((cond >> cnum) & 0x01) == tf)
1060 pc += mips32_relative_offset (inst) + 4;
1065 pc += 4; /* Not a branch, next instruction is easy */
1068 { /* This gets way messy */
1070 /* Further subdivide into SPECIAL, REGIMM and other */
1071 switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */
1073 case 0: /* SPECIAL */
1074 op = rtype_funct (inst);
1079 /* Set PC to that address */
1080 pc = read_signed_register (rtype_rs (inst));
1086 break; /* end SPECIAL */
1087 case 1: /* REGIMM */
1089 op = itype_rt (inst); /* branch condition */
1094 case 16: /* BLTZAL */
1095 case 18: /* BLTZALL */
1097 if (read_signed_register (itype_rs (inst)) < 0)
1098 pc += mips32_relative_offset (inst) + 4;
1100 pc += 8; /* after the delay slot */
1104 case 17: /* BGEZAL */
1105 case 19: /* BGEZALL */
1106 if (read_signed_register (itype_rs (inst)) >= 0)
1107 pc += mips32_relative_offset (inst) + 4;
1109 pc += 8; /* after the delay slot */
1111 /* All of the other instructions in the REGIMM category */
1116 break; /* end REGIMM */
1121 reg = jtype_target (inst) << 2;
1122 /* Upper four bits get never changed... */
1123 pc = reg + ((pc + 4) & 0xf0000000);
1126 /* FIXME case JALX : */
1129 reg = jtype_target (inst) << 2;
1130 pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */
1131 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1133 break; /* The new PC will be alternate mode */
1134 case 4: /* BEQ, BEQL */
1136 if (read_signed_register (itype_rs (inst)) ==
1137 read_signed_register (itype_rt (inst)))
1138 pc += mips32_relative_offset (inst) + 4;
1142 case 5: /* BNE, BNEL */
1144 if (read_signed_register (itype_rs (inst)) !=
1145 read_signed_register (itype_rt (inst)))
1146 pc += mips32_relative_offset (inst) + 4;
1150 case 6: /* BLEZ, BLEZL */
1151 if (read_signed_register (itype_rs (inst) <= 0))
1152 pc += mips32_relative_offset (inst) + 4;
1158 greater_branch: /* BGTZ, BGTZL */
1159 if (read_signed_register (itype_rs (inst) > 0))
1160 pc += mips32_relative_offset (inst) + 4;
1167 } /* mips32_next_pc */
1169 /* Decoding the next place to set a breakpoint is irregular for the
1170 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1171 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1172 We dont want to set a single step instruction on the extend instruction
1176 /* Lots of mips16 instruction formats */
1177 /* Predicting jumps requires itype,ritype,i8type
1178 and their extensions extItype,extritype,extI8type
1180 enum mips16_inst_fmts
1182 itype, /* 0 immediate 5,10 */
1183 ritype, /* 1 5,3,8 */
1184 rrtype, /* 2 5,3,3,5 */
1185 rritype, /* 3 5,3,3,5 */
1186 rrrtype, /* 4 5,3,3,3,2 */
1187 rriatype, /* 5 5,3,3,1,4 */
1188 shifttype, /* 6 5,3,3,3,2 */
1189 i8type, /* 7 5,3,8 */
1190 i8movtype, /* 8 5,3,3,5 */
1191 i8mov32rtype, /* 9 5,3,5,3 */
1192 i64type, /* 10 5,3,8 */
1193 ri64type, /* 11 5,3,3,5 */
1194 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */
1195 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1196 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */
1197 extRRItype, /* 15 5,5,5,5,3,3,5 */
1198 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */
1199 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1200 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */
1201 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */
1202 extRi64type, /* 20 5,6,5,5,3,3,5 */
1203 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1205 /* I am heaping all the fields of the formats into one structure and
1206 then, only the fields which are involved in instruction extension */
1210 unsigned int regx; /* Function in i8 type */
1215 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1216 for the bits which make up the immediatate extension. */
1219 extended_offset (unsigned int extension)
1222 value = (extension >> 21) & 0x3f; /* * extract 15:11 */
1224 value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
1226 value |= extension & 0x01f; /* extract 4:0 */
1230 /* Only call this function if you know that this is an extendable
1231 instruction, It wont malfunction, but why make excess remote memory references?
1232 If the immediate operands get sign extended or somthing, do it after
1233 the extension is performed.
1235 /* FIXME: Every one of these cases needs to worry about sign extension
1236 when the offset is to be used in relative addressing */
1240 fetch_mips_16 (CORE_ADDR pc)
1243 pc &= 0xfffffffe; /* clear the low order bit */
1244 target_read_memory (pc, buf, 2);
1245 return extract_unsigned_integer (buf, 2);
1249 unpack_mips16 (CORE_ADDR pc,
1250 unsigned int extension,
1252 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk)
1257 switch (insn_format)
1264 value = extended_offset (extension);
1265 value = value << 11; /* rom for the original value */
1266 value |= inst & 0x7ff; /* eleven bits from instruction */
1270 value = inst & 0x7ff;
1271 /* FIXME : Consider sign extension */
1280 { /* A register identifier and an offset */
1281 /* Most of the fields are the same as I type but the
1282 immediate value is of a different length */
1286 value = extended_offset (extension);
1287 value = value << 8; /* from the original instruction */
1288 value |= inst & 0xff; /* eleven bits from instruction */
1289 regx = (extension >> 8) & 0x07; /* or i8 funct */
1290 if (value & 0x4000) /* test the sign bit , bit 26 */
1292 value &= ~0x3fff; /* remove the sign bit */
1298 value = inst & 0xff; /* 8 bits */
1299 regx = (inst >> 8) & 0x07; /* or i8 funct */
1300 /* FIXME: Do sign extension , this format needs it */
1301 if (value & 0x80) /* THIS CONFUSES ME */
1303 value &= 0xef; /* remove the sign bit */
1313 unsigned long value;
1314 unsigned int nexthalf;
1315 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
1316 value = value << 16;
1317 nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
1325 internal_error (__FILE__, __LINE__, "bad switch");
1327 upk->offset = offset;
1334 add_offset_16 (CORE_ADDR pc, int offset)
1336 return ((offset << 2) | ((pc + 2) & (0xf0000000)));
1340 extended_mips16_next_pc (CORE_ADDR pc,
1341 unsigned int extension, unsigned int insn)
1343 int op = (insn >> 11);
1346 case 2: /* Branch */
1349 struct upk_mips16 upk;
1350 unpack_mips16 (pc, extension, insn, itype, &upk);
1351 offset = upk.offset;
1357 pc += (offset << 1) + 2;
1360 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1362 struct upk_mips16 upk;
1363 unpack_mips16 (pc, extension, insn, jalxtype, &upk);
1364 pc = add_offset_16 (pc, upk.offset);
1365 if ((insn >> 10) & 0x01) /* Exchange mode */
1366 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
1373 struct upk_mips16 upk;
1375 unpack_mips16 (pc, extension, insn, ritype, &upk);
1376 reg = read_signed_register (upk.regx);
1378 pc += (upk.offset << 1) + 2;
1385 struct upk_mips16 upk;
1387 unpack_mips16 (pc, extension, insn, ritype, &upk);
1388 reg = read_signed_register (upk.regx);
1390 pc += (upk.offset << 1) + 2;
1395 case 12: /* I8 Formats btez btnez */
1397 struct upk_mips16 upk;
1399 unpack_mips16 (pc, extension, insn, i8type, &upk);
1400 /* upk.regx contains the opcode */
1401 reg = read_signed_register (24); /* Test register is 24 */
1402 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
1403 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
1404 /* pc = add_offset_16(pc,upk.offset) ; */
1405 pc += (upk.offset << 1) + 2;
1410 case 29: /* RR Formats JR, JALR, JALR-RA */
1412 struct upk_mips16 upk;
1413 /* upk.fmt = rrtype; */
1418 upk.regx = (insn >> 8) & 0x07;
1419 upk.regy = (insn >> 5) & 0x07;
1427 break; /* Function return instruction */
1433 break; /* BOGUS Guess */
1435 pc = read_signed_register (reg);
1442 /* This is an instruction extension. Fetch the real instruction
1443 (which follows the extension) and decode things based on
1447 pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
1460 mips16_next_pc (CORE_ADDR pc)
1462 unsigned int insn = fetch_mips_16 (pc);
1463 return extended_mips16_next_pc (pc, 0, insn);
1466 /* The mips_next_pc function supports single_step when the remote
1467 target monitor or stub is not developed enough to do a single_step.
1468 It works by decoding the current instruction and predicting where a
1469 branch will go. This isnt hard because all the data is available.
1470 The MIPS32 and MIPS16 variants are quite different */
1472 mips_next_pc (CORE_ADDR pc)
1475 return mips16_next_pc (pc);
1477 return mips32_next_pc (pc);
1480 struct mips_frame_cache
1483 struct trad_frame_saved_reg *saved_regs;
1487 static struct mips_frame_cache *
1488 mips_mdebug_frame_cache (struct frame_info *next_frame, void **this_cache)
1490 mips_extra_func_info_t proc_desc;
1491 struct mips_frame_cache *cache;
1492 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1493 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1494 /* r0 bit means kernel trap */
1496 /* What registers have been saved? Bitmasks. */
1497 unsigned long gen_mask, float_mask;
1500 if ((*this_cache) != NULL)
1501 return (*this_cache);
1502 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
1503 (*this_cache) = cache;
1504 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
1506 /* Get the mdebug proc descriptor. */
1507 proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame, 1);
1508 if (proc_desc == NULL)
1509 /* I'm not sure how/whether this can happen. Normally when we
1510 can't find a proc_desc, we "synthesize" one using
1511 heuristic_proc_desc and set the saved_regs right away. */
1514 /* Extract the frame's base. */
1515 cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
1516 + PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
1517 /* Save registers offset from scratching by following find_proc_desc call */
1518 reg_offset = PROC_REG_OFFSET (proc_desc);
1520 kernel_trap = PROC_REG_MASK (proc_desc) & 1;
1521 gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
1522 float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
1524 /* In any frame other than the innermost or a frame interrupted by a
1525 signal, we assume that all registers have been saved. This
1526 assumes that all register saves in a function happen before the
1527 first function call. */
1528 if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc))
1529 /* Not sure exactly what kernel_trap means, but if it means the
1530 kernel saves the registers without a prologue doing it, we
1531 better not examine the prologue to see whether registers
1532 have been saved yet. */
1535 /* We need to figure out whether the registers that the
1536 proc_desc claims are saved have been saved yet. */
1540 /* Bitmasks; set if we have found a save for the register. */
1541 unsigned long gen_save_found = 0;
1542 unsigned long float_save_found = 0;
1545 /* If the address is odd, assume this is MIPS16 code. */
1546 addr = PROC_LOW_ADDR (proc_desc);
1547 mips16 = pc_is_mips16 (addr);
1549 /* Scan through this function's instructions preceding the
1550 current PC, and look for those that save registers. */
1551 while (addr < frame_pc_unwind (next_frame))
1555 mips16_decode_reg_save (mips16_fetch_instruction (addr),
1557 addr += MIPS16_INSTLEN;
1561 mips32_decode_reg_save (mips32_fetch_instruction (addr),
1562 &gen_save_found, &float_save_found);
1563 addr += MIPS_INSTLEN;
1566 gen_mask = gen_save_found;
1567 float_mask = float_save_found;
1570 /* Fill in the offsets for the registers which gen_mask says were
1573 CORE_ADDR reg_position = (cache->base + reg_offset);
1575 for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
1576 if (gen_mask & 0x80000000)
1578 cache->saved_regs[NUM_REGS + ireg].addr = reg_position;
1579 reg_position -= mips_saved_regsize (tdep);
1583 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1584 order of that normally used by gcc. Therefore, we have to fetch
1585 the first instruction of the function, and if it's an entry
1586 instruction that saves $s0 or $s1, correct their saved addresses. */
1587 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
1589 ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc));
1590 if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
1594 int sreg_count = (inst >> 6) & 3;
1596 /* Check if the ra register was pushed on the stack. */
1597 CORE_ADDR reg_position = (cache->base
1598 + PROC_REG_OFFSET (proc_desc));
1600 reg_position -= mips_saved_regsize (tdep);
1602 /* Check if the s0 and s1 registers were pushed on the
1604 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1606 for (reg = 16; reg < sreg_count + 16; reg++)
1608 cache->saved_regs[NUM_REGS + reg].addr = reg_position;
1609 reg_position -= mips_saved_regsize (tdep);
1614 /* Fill in the offsets for the registers which float_mask says were
1617 CORE_ADDR reg_position = (cache->base
1618 + PROC_FREG_OFFSET (proc_desc));
1620 /* Fill in the offsets for the float registers which float_mask
1622 for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
1623 if (float_mask & 0x80000000)
1625 if (mips_saved_regsize (tdep) == 4
1626 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1628 /* On a big endian 32 bit ABI, floating point registers
1629 are paired to form doubles such that the most
1630 significant part is in $f[N+1] and the least
1631 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1632 registers are also spilled as a pair and stored as a
1635 When little-endian the least significant part is
1636 stored first leading to the memory order $f[N] and
1639 Unfortunately, when big-endian the most significant
1640 part of the double is stored first, and the least
1641 significant is stored second. This leads to the
1642 registers being ordered in memory as firt $f[N+1] and
1645 For the big-endian case make certain that the
1646 addresses point at the correct (swapped) locations
1647 $f[N] and $f[N+1] pair (keep in mind that
1648 reg_position is decremented each time through the
1651 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
1652 .addr = reg_position - mips_saved_regsize (tdep);
1654 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
1655 .addr = reg_position + mips_saved_regsize (tdep);
1658 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
1659 .addr = reg_position;
1660 reg_position -= mips_saved_regsize (tdep);
1663 cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
1664 = cache->saved_regs[NUM_REGS + RA_REGNUM];
1667 /* SP_REGNUM, contains the value and not the address. */
1668 trad_frame_set_value (cache->saved_regs, NUM_REGS + SP_REGNUM, cache->base);
1670 return (*this_cache);
1674 mips_mdebug_frame_this_id (struct frame_info *next_frame, void **this_cache,
1675 struct frame_id *this_id)
1677 struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
1679 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
1683 mips_mdebug_frame_prev_register (struct frame_info *next_frame,
1685 int regnum, int *optimizedp,
1686 enum lval_type *lvalp, CORE_ADDR *addrp,
1687 int *realnump, void *valuep)
1689 struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
1691 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
1692 optimizedp, lvalp, addrp, realnump, valuep);
1695 static const struct frame_unwind mips_mdebug_frame_unwind =
1698 mips_mdebug_frame_this_id,
1699 mips_mdebug_frame_prev_register
1702 static const struct frame_unwind *
1703 mips_mdebug_frame_sniffer (struct frame_info *next_frame)
1705 return &mips_mdebug_frame_unwind;
1709 mips_mdebug_frame_base_address (struct frame_info *next_frame,
1712 struct mips_frame_cache *info = mips_mdebug_frame_cache (next_frame,
1717 static const struct frame_base mips_mdebug_frame_base = {
1718 &mips_mdebug_frame_unwind,
1719 mips_mdebug_frame_base_address,
1720 mips_mdebug_frame_base_address,
1721 mips_mdebug_frame_base_address
1724 static const struct frame_base *
1725 mips_mdebug_frame_base_sniffer (struct frame_info *next_frame)
1727 return &mips_mdebug_frame_base;
1731 read_next_frame_reg (struct frame_info *fi, int regno)
1733 /* Always a pseudo. */
1734 gdb_assert (regno >= NUM_REGS);
1738 regcache_cooked_read_signed (current_regcache, regno, &val);
1741 else if ((regno % NUM_REGS) == SP_REGNUM)
1742 /* The SP_REGNUM is special, its value is stored in saved_regs.
1743 In fact, it is so special that it can even only be fetched
1744 using a raw register number! Once this code as been converted
1745 to frame-unwind the problem goes away. */
1746 return frame_unwind_register_signed (fi, regno % NUM_REGS);
1748 return frame_unwind_register_signed (fi, regno);
1752 /* mips_addr_bits_remove - remove useless address bits */
1755 mips_addr_bits_remove (CORE_ADDR addr)
1757 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1758 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
1759 /* This hack is a work-around for existing boards using PMON, the
1760 simulator, and any other 64-bit targets that doesn't have true
1761 64-bit addressing. On these targets, the upper 32 bits of
1762 addresses are ignored by the hardware. Thus, the PC or SP are
1763 likely to have been sign extended to all 1s by instruction
1764 sequences that load 32-bit addresses. For example, a typical
1765 piece of code that loads an address is this:
1767 lui $r2, <upper 16 bits>
1768 ori $r2, <lower 16 bits>
1770 But the lui sign-extends the value such that the upper 32 bits
1771 may be all 1s. The workaround is simply to mask off these
1772 bits. In the future, gcc may be changed to support true 64-bit
1773 addressing, and this masking will have to be disabled. */
1774 return addr &= 0xffffffffUL;
1779 /* mips_software_single_step() is called just before we want to resume
1780 the inferior, if we want to single-step it but there is no hardware
1781 or kernel single-step support (MIPS on GNU/Linux for example). We find
1782 the target of the coming instruction and breakpoint it.
1784 single_step is also called just after the inferior stops. If we had
1785 set up a simulated single-step, we undo our damage. */
1788 mips_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1790 static CORE_ADDR next_pc;
1791 typedef char binsn_quantum[BREAKPOINT_MAX];
1792 static binsn_quantum break_mem;
1795 if (insert_breakpoints_p)
1797 pc = read_register (mips_regnum (current_gdbarch)->pc);
1798 next_pc = mips_next_pc (pc);
1800 target_insert_breakpoint (next_pc, break_mem);
1803 target_remove_breakpoint (next_pc, break_mem);
1806 static struct mips_extra_func_info temp_proc_desc;
1808 /* This hack will go away once the get_prev_frame() code has been
1809 modified to set the frame's type first. That is BEFORE init extra
1810 frame info et.al. is called. This is because it will become
1811 possible to skip the init extra info call for sigtramp and dummy
1813 static CORE_ADDR *temp_saved_regs;
1815 /* Set a register's saved stack address in temp_saved_regs. If an
1816 address has already been set for this register, do nothing; this
1817 way we will only recognize the first save of a given register in a
1820 For simplicity, save the address in both [0 .. NUM_REGS) and
1821 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1822 is used as it is only second range (the ABI instead of ISA
1823 registers) that comes into play when finding saved registers in a
1827 set_reg_offset (CORE_ADDR *saved_regs, int regno, CORE_ADDR offset)
1829 if (saved_regs[regno] == 0)
1831 saved_regs[regno + 0 * NUM_REGS] = offset;
1832 saved_regs[regno + 1 * NUM_REGS] = offset;
1837 /* Test whether the PC points to the return instruction at the
1838 end of a function. */
1841 mips_about_to_return (CORE_ADDR pc)
1843 if (pc_is_mips16 (pc))
1844 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1845 generates a "jr $ra"; other times it generates code to load
1846 the return address from the stack to an accessible register (such
1847 as $a3), then a "jr" using that register. This second case
1848 is almost impossible to distinguish from an indirect jump
1849 used for switch statements, so we don't even try. */
1850 return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */
1852 return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */
1856 /* This fencepost looks highly suspicious to me. Removing it also
1857 seems suspicious as it could affect remote debugging across serial
1861 heuristic_proc_start (CORE_ADDR pc)
1868 pc = ADDR_BITS_REMOVE (pc);
1870 fence = start_pc - heuristic_fence_post;
1874 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS)
1875 fence = VM_MIN_ADDRESS;
1877 instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN;
1879 /* search back for previous return */
1880 for (start_pc -= instlen;; start_pc -= instlen)
1881 if (start_pc < fence)
1883 /* It's not clear to me why we reach this point when
1884 stop_soon, but with this test, at least we
1885 don't print out warnings for every child forked (eg, on
1886 decstation). 22apr93 rich@cygnus.com. */
1887 if (stop_soon == NO_STOP_QUIETLY)
1889 static int blurb_printed = 0;
1892 ("Warning: GDB can't find the start of the function at 0x%s.",
1897 /* This actually happens frequently in embedded
1898 development, when you first connect to a board
1899 and your stack pointer and pc are nowhere in
1900 particular. This message needs to give people
1901 in that situation enough information to
1902 determine that it's no big deal. */
1903 printf_filtered ("\n\
1904 GDB is unable to find the start of the function at 0x%s\n\
1905 and thus can't determine the size of that function's stack frame.\n\
1906 This means that GDB may be unable to access that stack frame, or\n\
1907 the frames below it.\n\
1908 This problem is most likely caused by an invalid program counter or\n\
1910 However, if you think GDB should simply search farther back\n\
1911 from 0x%s for code which looks like the beginning of a\n\
1912 function, you can increase the range of the search using the `set\n\
1913 heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc));
1920 else if (pc_is_mips16 (start_pc))
1922 unsigned short inst;
1924 /* On MIPS16, any one of the following is likely to be the
1925 start of a function:
1929 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1930 inst = mips_fetch_instruction (start_pc);
1931 if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
1932 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */
1933 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */
1934 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */
1936 else if ((inst & 0xff00) == 0x6300 /* addiu sp */
1937 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
1942 else if (mips_about_to_return (start_pc))
1944 start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */
1951 /* Fetch the immediate value from a MIPS16 instruction.
1952 If the previous instruction was an EXTEND, use it to extend
1953 the upper bits of the immediate value. This is a helper function
1954 for mips16_heuristic_proc_desc. */
1957 mips16_get_imm (unsigned short prev_inst, /* previous instruction */
1958 unsigned short inst, /* current instruction */
1959 int nbits, /* number of bits in imm field */
1960 int scale, /* scale factor to be applied to imm */
1961 int is_signed) /* is the imm field signed? */
1965 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1967 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0);
1968 if (offset & 0x8000) /* check for negative extend */
1969 offset = 0 - (0x10000 - (offset & 0xffff));
1970 return offset | (inst & 0x1f);
1974 int max_imm = 1 << nbits;
1975 int mask = max_imm - 1;
1976 int sign_bit = max_imm >> 1;
1978 offset = inst & mask;
1979 if (is_signed && (offset & sign_bit))
1980 offset = 0 - (max_imm - offset);
1981 return offset * scale;
1986 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1987 stream from start_pc to limit_pc. */
1990 mips16_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
1991 struct frame_info *next_frame, CORE_ADDR sp)
1994 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */
1995 unsigned short prev_inst = 0; /* saved copy of previous instruction */
1996 unsigned inst = 0; /* current instruction */
1997 unsigned entry_inst = 0; /* the entry instruction */
1999 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2001 PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */
2002 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2004 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN)
2006 /* Save the previous instruction. If it's an EXTEND, we'll extract
2007 the immediate offset extension from it in mips16_get_imm. */
2010 /* Fetch and decode the instruction. */
2011 inst = (unsigned short) mips_fetch_instruction (cur_pc);
2012 if ((inst & 0xff00) == 0x6300 /* addiu sp */
2013 || (inst & 0xff00) == 0xfb00) /* daddiu sp */
2015 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1);
2016 if (offset < 0) /* negative stack adjustment? */
2017 PROC_FRAME_OFFSET (&temp_proc_desc) -= offset;
2019 /* Exit loop if a positive stack adjustment is found, which
2020 usually means that the stack cleanup code in the function
2021 epilogue is reached. */
2024 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */
2026 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2027 reg = mips16_to_32_reg[(inst & 0x700) >> 8];
2028 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2029 set_reg_offset (temp_saved_regs, reg, sp + offset);
2031 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */
2033 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2034 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2035 PROC_REG_MASK (&temp_proc_desc) |= (1 << reg);
2036 set_reg_offset (temp_saved_regs, reg, sp + offset);
2038 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */
2040 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2041 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2042 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2044 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2046 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0);
2047 PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM);
2048 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2050 else if (inst == 0x673d) /* move $s1, $sp */
2053 PROC_FRAME_REG (&temp_proc_desc) = 17;
2055 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */
2057 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0);
2058 frame_addr = sp + offset;
2059 PROC_FRAME_REG (&temp_proc_desc) = 17;
2060 PROC_FRAME_ADJUST (&temp_proc_desc) = offset;
2062 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2064 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0);
2065 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2066 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2067 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2069 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2071 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0);
2072 reg = mips16_to_32_reg[(inst & 0xe0) >> 5];
2073 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2074 set_reg_offset (temp_saved_regs, reg, frame_addr + offset);
2076 else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */
2077 entry_inst = inst; /* save for later processing */
2078 else if ((inst & 0xf800) == 0x1800) /* jal(x) */
2079 cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */
2082 /* The entry instruction is typically the first instruction in a function,
2083 and it stores registers at offsets relative to the value of the old SP
2084 (before the prologue). But the value of the sp parameter to this
2085 function is the new SP (after the prologue has been executed). So we
2086 can't calculate those offsets until we've seen the entire prologue,
2087 and can calculate what the old SP must have been. */
2088 if (entry_inst != 0)
2090 int areg_count = (entry_inst >> 8) & 7;
2091 int sreg_count = (entry_inst >> 6) & 3;
2093 /* The entry instruction always subtracts 32 from the SP. */
2094 PROC_FRAME_OFFSET (&temp_proc_desc) += 32;
2096 /* Now we can calculate what the SP must have been at the
2097 start of the function prologue. */
2098 sp += PROC_FRAME_OFFSET (&temp_proc_desc);
2100 /* Check if a0-a3 were saved in the caller's argument save area. */
2101 for (reg = 4, offset = 0; reg < areg_count + 4; reg++)
2103 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2104 set_reg_offset (temp_saved_regs, reg, sp + offset);
2105 offset += mips_saved_regsize (tdep);
2108 /* Check if the ra register was pushed on the stack. */
2110 if (entry_inst & 0x20)
2112 PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM;
2113 set_reg_offset (temp_saved_regs, RA_REGNUM, sp + offset);
2114 offset -= mips_saved_regsize (tdep);
2117 /* Check if the s0 and s1 registers were pushed on the stack. */
2118 for (reg = 16; reg < sreg_count + 16; reg++)
2120 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2121 set_reg_offset (temp_saved_regs, reg, sp + offset);
2122 offset -= mips_saved_regsize (tdep);
2128 mips32_heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2129 struct frame_info *next_frame, CORE_ADDR sp)
2132 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */
2134 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2135 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2136 PROC_FRAME_OFFSET (&temp_proc_desc) = 0;
2137 PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */
2138 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN)
2140 unsigned long inst, high_word, low_word;
2143 /* Fetch the instruction. */
2144 inst = (unsigned long) mips_fetch_instruction (cur_pc);
2146 /* Save some code by pre-extracting some useful fields. */
2147 high_word = (inst >> 16) & 0xffff;
2148 low_word = inst & 0xffff;
2149 reg = high_word & 0x1f;
2151 if (high_word == 0x27bd /* addiu $sp,$sp,-i */
2152 || high_word == 0x23bd /* addi $sp,$sp,-i */
2153 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */
2155 if (low_word & 0x8000) /* negative stack adjustment? */
2156 PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word;
2158 /* Exit loop if a positive stack adjustment is found, which
2159 usually means that the stack cleanup code in the function
2160 epilogue is reached. */
2163 else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2165 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2166 set_reg_offset (temp_saved_regs, reg, sp + low_word);
2167 /* Do we have registers offset yet? */
2168 if (!PROC_REG_OFFSET (&temp_proc_desc))
2169 PROC_REG_OFFSET (&temp_proc_desc) = low_word - PROC_FRAME_OFFSET (&temp_proc_desc);
2171 else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2173 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2174 set_reg_offset (temp_saved_regs, reg,
2176 /* Do we have registers offset yet? */
2177 if (!PROC_REG_OFFSET (&temp_proc_desc))
2178 PROC_REG_OFFSET (&temp_proc_desc) = low_word - PROC_FRAME_OFFSET (&temp_proc_desc);
2180 else if (high_word == 0x27be) /* addiu $30,$sp,size */
2182 /* Old gcc frame, r30 is virtual frame pointer. */
2183 if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc))
2184 frame_addr = sp + low_word;
2185 else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2187 unsigned alloca_adjust;
2188 PROC_FRAME_REG (&temp_proc_desc) = 30;
2189 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
2190 alloca_adjust = (unsigned) (frame_addr - (sp + low_word));
2191 if (alloca_adjust > 0)
2193 /* FP > SP + frame_size. This may be because
2194 * of an alloca or somethings similar.
2195 * Fix sp to "pre-alloca" value, and try again.
2197 sp += alloca_adjust;
2202 /* move $30,$sp. With different versions of gas this will be either
2203 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2204 Accept any one of these. */
2205 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
2207 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2208 if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM)
2210 unsigned alloca_adjust;
2211 PROC_FRAME_REG (&temp_proc_desc) = 30;
2212 frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30);
2213 alloca_adjust = (unsigned) (frame_addr - sp);
2214 if (alloca_adjust > 0)
2216 /* FP > SP + frame_size. This may be because
2217 * of an alloca or somethings similar.
2218 * Fix sp to "pre-alloca" value, and try again.
2220 sp += alloca_adjust;
2225 else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2227 PROC_REG_MASK (&temp_proc_desc) |= 1 << reg;
2228 set_reg_offset (temp_saved_regs, reg, frame_addr + low_word);
2233 static mips_extra_func_info_t
2234 heuristic_proc_desc (CORE_ADDR start_pc, CORE_ADDR limit_pc,
2235 struct frame_info *next_frame, int cur_frame)
2240 sp = read_next_frame_reg (next_frame, NUM_REGS + SP_REGNUM);
2246 memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc));
2247 temp_saved_regs = xrealloc (temp_saved_regs, SIZEOF_FRAME_SAVED_REGS);
2248 memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS);
2249 PROC_LOW_ADDR (&temp_proc_desc) = start_pc;
2250 PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM;
2251 PROC_PC_REG (&temp_proc_desc) = RA_REGNUM;
2253 if (start_pc + 200 < limit_pc)
2254 limit_pc = start_pc + 200;
2255 if (pc_is_mips16 (start_pc))
2256 mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2258 mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp);
2259 return &temp_proc_desc;
2262 struct mips_objfile_private
2268 /* Global used to communicate between non_heuristic_proc_desc and
2269 compare_pdr_entries within qsort (). */
2270 static bfd *the_bfd;
2273 compare_pdr_entries (const void *a, const void *b)
2275 CORE_ADDR lhs = bfd_get_32 (the_bfd, (bfd_byte *) a);
2276 CORE_ADDR rhs = bfd_get_32 (the_bfd, (bfd_byte *) b);
2280 else if (lhs == rhs)
2286 static mips_extra_func_info_t
2287 non_heuristic_proc_desc (CORE_ADDR pc, CORE_ADDR *addrptr)
2289 CORE_ADDR startaddr;
2290 mips_extra_func_info_t proc_desc;
2291 struct block *b = block_for_pc (pc);
2293 struct obj_section *sec;
2294 struct mips_objfile_private *priv;
2296 if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
2299 find_pc_partial_function (pc, NULL, &startaddr, NULL);
2301 *addrptr = startaddr;
2305 sec = find_pc_section (pc);
2308 priv = (struct mips_objfile_private *) objfile_data (sec->objfile, mips_pdr_data);
2310 /* Search the ".pdr" section generated by GAS. This includes most of
2311 the information normally found in ECOFF PDRs. */
2313 the_bfd = sec->objfile->obfd;
2315 && (the_bfd->format == bfd_object
2316 && bfd_get_flavour (the_bfd) == bfd_target_elf_flavour
2317 && elf_elfheader (the_bfd)->e_ident[EI_CLASS] == ELFCLASS64))
2319 /* Right now GAS only outputs the address as a four-byte sequence.
2320 This means that we should not bother with this method on 64-bit
2321 targets (until that is fixed). */
2323 priv = obstack_alloc (&sec->objfile->objfile_obstack,
2324 sizeof (struct mips_objfile_private));
2326 set_objfile_data (sec->objfile, mips_pdr_data, priv);
2328 else if (priv == NULL)
2332 priv = obstack_alloc (&sec->objfile->objfile_obstack,
2333 sizeof (struct mips_objfile_private));
2335 bfdsec = bfd_get_section_by_name (sec->objfile->obfd, ".pdr");
2338 priv->size = bfd_section_size (sec->objfile->obfd, bfdsec);
2339 priv->contents = obstack_alloc (&sec->objfile->objfile_obstack,
2341 bfd_get_section_contents (sec->objfile->obfd, bfdsec,
2342 priv->contents, 0, priv->size);
2344 /* In general, the .pdr section is sorted. However, in the
2345 presence of multiple code sections (and other corner cases)
2346 it can become unsorted. Sort it so that we can use a faster
2348 qsort (priv->contents, priv->size / 32, 32,
2349 compare_pdr_entries);
2354 set_objfile_data (sec->objfile, mips_pdr_data, priv);
2358 if (priv->size != 0)
2364 high = priv->size / 32;
2370 mid = (low + high) / 2;
2372 ptr = priv->contents + mid * 32;
2373 pdr_pc = bfd_get_signed_32 (sec->objfile->obfd, ptr);
2374 pdr_pc += ANOFFSET (sec->objfile->section_offsets,
2375 SECT_OFF_TEXT (sec->objfile));
2376 if (pdr_pc == startaddr)
2378 if (pdr_pc > startaddr)
2383 while (low != high);
2387 struct symbol *sym = find_pc_function (pc);
2389 /* Fill in what we need of the proc_desc. */
2390 proc_desc = (mips_extra_func_info_t)
2391 obstack_alloc (&sec->objfile->objfile_obstack,
2392 sizeof (struct mips_extra_func_info));
2393 PROC_LOW_ADDR (proc_desc) = startaddr;
2395 /* Only used for dummy frames. */
2396 PROC_HIGH_ADDR (proc_desc) = 0;
2398 PROC_FRAME_OFFSET (proc_desc)
2399 = bfd_get_32 (sec->objfile->obfd, ptr + 20);
2400 PROC_FRAME_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2402 PROC_FRAME_ADJUST (proc_desc) = 0;
2403 PROC_REG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2405 PROC_FREG_MASK (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2407 PROC_REG_OFFSET (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2409 PROC_FREG_OFFSET (proc_desc)
2410 = bfd_get_32 (sec->objfile->obfd, ptr + 16);
2411 PROC_PC_REG (proc_desc) = bfd_get_32 (sec->objfile->obfd,
2413 proc_desc->pdr.isym = (long) sym;
2423 if (startaddr > BLOCK_START (b))
2425 /* This is the "pathological" case referred to in a comment in
2426 print_frame_info. It might be better to move this check into
2431 sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_DOMAIN, 0, NULL);
2433 /* If we never found a PDR for this function in symbol reading, then
2434 examine prologues to find the information. */
2437 proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym);
2438 if (PROC_FRAME_REG (proc_desc) == -1)
2448 static mips_extra_func_info_t
2449 find_proc_desc (CORE_ADDR pc, struct frame_info *next_frame, int cur_frame)
2451 mips_extra_func_info_t proc_desc;
2452 CORE_ADDR startaddr = 0;
2454 proc_desc = non_heuristic_proc_desc (pc, &startaddr);
2458 /* IF this is the topmost frame AND
2459 * (this proc does not have debugging information OR
2460 * the PC is in the procedure prologue)
2461 * THEN create a "heuristic" proc_desc (by analyzing
2462 * the actual code) to replace the "official" proc_desc.
2464 if (next_frame == NULL)
2466 struct symtab_and_line val;
2467 struct symbol *proc_symbol =
2468 PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc);
2472 val = find_pc_line (BLOCK_START
2473 (SYMBOL_BLOCK_VALUE (proc_symbol)), 0);
2474 val.pc = val.end ? val.end : pc;
2476 if (!proc_symbol || pc < val.pc)
2478 mips_extra_func_info_t found_heuristic =
2479 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc),
2480 pc, next_frame, cur_frame);
2481 if (found_heuristic)
2482 proc_desc = found_heuristic;
2488 /* Is linked_proc_desc_table really necessary? It only seems to be used
2489 by procedure call dummys. However, the procedures being called ought
2490 to have their own proc_descs, and even if they don't,
2491 heuristic_proc_desc knows how to create them! */
2493 struct linked_proc_info *link;
2495 for (link = linked_proc_desc_table; link; link = link->next)
2496 if (PROC_LOW_ADDR (&link->info) <= pc
2497 && PROC_HIGH_ADDR (&link->info) > pc)
2501 startaddr = heuristic_proc_start (pc);
2503 proc_desc = heuristic_proc_desc (startaddr, pc, next_frame, cur_frame);
2508 /* MIPS stack frames are almost impenetrable. When execution stops,
2509 we basically have to look at symbol information for the function
2510 that we stopped in, which tells us *which* register (if any) is
2511 the base of the frame pointer, and what offset from that register
2512 the frame itself is at.
2514 This presents a problem when trying to examine a stack in memory
2515 (that isn't executing at the moment), using the "frame" command. We
2516 don't have a PC, nor do we have any registers except SP.
2518 This routine takes two arguments, SP and PC, and tries to make the
2519 cached frames look as if these two arguments defined a frame on the
2520 cache. This allows the rest of info frame to extract the important
2521 arguments without difficulty. */
2524 setup_arbitrary_frame (int argc, CORE_ADDR *argv)
2527 error ("MIPS frame specifications require two arguments: sp and pc");
2529 return create_new_frame (argv[0], argv[1]);
2532 /* According to the current ABI, should the type be passed in a
2533 floating-point register (assuming that there is space)? When there
2534 is no FPU, FP are not even considered as possibile candidates for
2535 FP registers and, consequently this returns false - forces FP
2536 arguments into integer registers. */
2539 fp_register_arg_p (enum type_code typecode, struct type *arg_type)
2541 return ((typecode == TYPE_CODE_FLT
2543 && (typecode == TYPE_CODE_STRUCT
2544 || typecode == TYPE_CODE_UNION)
2545 && TYPE_NFIELDS (arg_type) == 1
2546 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT))
2547 && MIPS_FPU_TYPE != MIPS_FPU_NONE);
2550 /* On o32, argument passing in GPRs depends on the alignment of the type being
2551 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2554 mips_type_needs_double_align (struct type *type)
2556 enum type_code typecode = TYPE_CODE (type);
2558 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
2560 else if (typecode == TYPE_CODE_STRUCT)
2562 if (TYPE_NFIELDS (type) < 1)
2564 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
2566 else if (typecode == TYPE_CODE_UNION)
2570 n = TYPE_NFIELDS (type);
2571 for (i = 0; i < n; i++)
2572 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
2579 /* Adjust the address downward (direction of stack growth) so that it
2580 is correctly aligned for a new stack frame. */
2582 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2584 return align_down (addr, 16);
2587 /* Determine how a return value is stored within the MIPS register
2588 file, given the return type `valtype'. */
2590 struct return_value_word
2599 return_value_location (struct type *valtype,
2600 struct return_value_word *hi,
2601 struct return_value_word *lo)
2603 int len = TYPE_LENGTH (valtype);
2604 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2606 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
2607 && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8))
2608 || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4)))
2610 if (!FP_REGISTER_DOUBLE && len == 8)
2612 /* We need to break a 64bit float in two 32 bit halves and
2613 spread them across a floating-point register pair. */
2614 lo->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2615 hi->buf_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 0 : 4;
2616 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2617 && register_size (current_gdbarch,
2618 mips_regnum (current_gdbarch)->
2619 fp0) == 8) ? 4 : 0);
2620 hi->reg_offset = lo->reg_offset;
2621 lo->reg = mips_regnum (current_gdbarch)->fp0 + 0;
2622 hi->reg = mips_regnum (current_gdbarch)->fp0 + 1;
2628 /* The floating point value fits in a single floating-point
2630 lo->reg_offset = ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2631 && register_size (current_gdbarch,
2632 mips_regnum (current_gdbarch)->
2634 && len == 4) ? 4 : 0);
2635 lo->reg = mips_regnum (current_gdbarch)->fp0;
2646 /* Locate a result possibly spread across two registers. */
2648 lo->reg = regnum + 0;
2649 hi->reg = regnum + 1;
2650 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2651 && len < mips_saved_regsize (tdep))
2653 /* "un-left-justify" the value in the low register */
2654 lo->reg_offset = mips_saved_regsize (tdep) - len;
2659 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG && len > mips_saved_regsize (tdep) /* odd-size structs */
2660 && len < mips_saved_regsize (tdep) * 2
2661 && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
2662 TYPE_CODE (valtype) == TYPE_CODE_UNION))
2664 /* "un-left-justify" the value spread across two registers. */
2665 lo->reg_offset = 2 * mips_saved_regsize (tdep) - len;
2666 lo->len = mips_saved_regsize (tdep) - lo->reg_offset;
2668 hi->len = len - lo->len;
2672 /* Only perform a partial copy of the second register. */
2675 if (len > mips_saved_regsize (tdep))
2677 lo->len = mips_saved_regsize (tdep);
2678 hi->len = len - mips_saved_regsize (tdep);
2686 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
2687 && register_size (current_gdbarch, regnum) == 8
2688 && mips_saved_regsize (tdep) == 4)
2690 /* Account for the fact that only the least-signficant part
2691 of the register is being used */
2692 lo->reg_offset += 4;
2693 hi->reg_offset += 4;
2696 hi->buf_offset = lo->len;
2700 /* Should call_function allocate stack space for a struct return? */
2703 mips_eabi_use_struct_convention (int gcc_p, struct type *type)
2705 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2706 return (TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep));
2709 /* Should call_function pass struct by reference?
2710 For each architecture, structs are passed either by
2711 value or by reference, depending on their size. */
2714 mips_eabi_reg_struct_has_addr (int gcc_p, struct type *type)
2716 enum type_code typecode = TYPE_CODE (check_typedef (type));
2717 int len = TYPE_LENGTH (check_typedef (type));
2718 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2720 if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)
2721 return (len > mips_saved_regsize (tdep));
2727 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
2728 struct regcache *regcache, CORE_ADDR bp_addr,
2729 int nargs, struct value **args, CORE_ADDR sp,
2730 int struct_return, CORE_ADDR struct_addr)
2736 int stack_offset = 0;
2737 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2739 /* For shared libraries, "t9" needs to point at the function
2741 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
2743 /* Set the return address register to point to the entry point of
2744 the program, where a breakpoint lies in wait. */
2745 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
2747 /* First ensure that the stack and structure return address (if any)
2748 are properly aligned. The stack has to be at least 64-bit
2749 aligned even on 32-bit machines, because doubles must be 64-bit
2750 aligned. For n32 and n64, stack frames need to be 128-bit
2751 aligned, so we round to this widest known alignment. */
2753 sp = align_down (sp, 16);
2754 struct_addr = align_down (struct_addr, 16);
2756 /* Now make space on the stack for the args. We allocate more
2757 than necessary for EABI, because the first few arguments are
2758 passed in registers, but that's OK. */
2759 for (argnum = 0; argnum < nargs; argnum++)
2760 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
2761 mips_stack_argsize (tdep));
2762 sp -= align_up (len, 16);
2765 fprintf_unfiltered (gdb_stdlog,
2766 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2767 paddr_nz (sp), (long) align_up (len, 16));
2769 /* Initialize the integer and float register pointers. */
2771 float_argreg = mips_fpa0_regnum (current_gdbarch);
2773 /* The struct_return pointer occupies the first parameter-passing reg. */
2777 fprintf_unfiltered (gdb_stdlog,
2778 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2779 argreg, paddr_nz (struct_addr));
2780 write_register (argreg++, struct_addr);
2783 /* Now load as many as possible of the first arguments into
2784 registers, and push the rest onto the stack. Loop thru args
2785 from first to last. */
2786 for (argnum = 0; argnum < nargs; argnum++)
2789 char valbuf[MAX_REGISTER_SIZE];
2790 struct value *arg = args[argnum];
2791 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
2792 int len = TYPE_LENGTH (arg_type);
2793 enum type_code typecode = TYPE_CODE (arg_type);
2796 fprintf_unfiltered (gdb_stdlog,
2797 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2798 argnum + 1, len, (int) typecode);
2800 /* The EABI passes structures that do not fit in a register by
2802 if (len > mips_saved_regsize (tdep)
2803 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
2805 store_unsigned_integer (valbuf, mips_saved_regsize (tdep),
2806 VALUE_ADDRESS (arg));
2807 typecode = TYPE_CODE_PTR;
2808 len = mips_saved_regsize (tdep);
2811 fprintf_unfiltered (gdb_stdlog, " push");
2814 val = (char *) VALUE_CONTENTS (arg);
2816 /* 32-bit ABIs always start floating point arguments in an
2817 even-numbered floating point register. Round the FP register
2818 up before the check to see if there are any FP registers
2819 left. Non MIPS_EABI targets also pass the FP in the integer
2820 registers so also round up normal registers. */
2821 if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type))
2823 if ((float_argreg & 1))
2827 /* Floating point arguments passed in registers have to be
2828 treated specially. On 32-bit architectures, doubles
2829 are passed in register pairs; the even register gets
2830 the low word, and the odd register gets the high word.
2831 On non-EABI processors, the first two floating point arguments are
2832 also copied to general registers, because MIPS16 functions
2833 don't use float registers for arguments. This duplication of
2834 arguments in general registers can't hurt non-MIPS16 functions
2835 because those registers are normally skipped. */
2836 /* MIPS_EABI squeezes a struct that contains a single floating
2837 point value into an FP register instead of pushing it onto the
2839 if (fp_register_arg_p (typecode, arg_type)
2840 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
2842 if (!FP_REGISTER_DOUBLE && len == 8)
2844 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
2845 unsigned long regval;
2847 /* Write the low word of the double to the even register(s). */
2848 regval = extract_unsigned_integer (val + low_offset, 4);
2850 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2851 float_argreg, phex (regval, 4));
2852 write_register (float_argreg++, regval);
2854 /* Write the high word of the double to the odd register(s). */
2855 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
2857 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2858 float_argreg, phex (regval, 4));
2859 write_register (float_argreg++, regval);
2863 /* This is a floating point value that fits entirely
2864 in a single register. */
2865 /* On 32 bit ABI's the float_argreg is further adjusted
2866 above to ensure that it is even register aligned. */
2867 LONGEST regval = extract_unsigned_integer (val, len);
2869 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
2870 float_argreg, phex (regval, len));
2871 write_register (float_argreg++, regval);
2876 /* Copy the argument to general registers or the stack in
2877 register-sized pieces. Large arguments are split between
2878 registers and stack. */
2879 /* Note: structs whose size is not a multiple of
2880 mips_regsize() are treated specially: Irix cc passes them
2881 in registers where gcc sometimes puts them on the stack.
2882 For maximum compatibility, we will put them in both
2884 int odd_sized_struct = ((len > mips_saved_regsize (tdep))
2885 && (len % mips_saved_regsize (tdep) != 0));
2887 /* Note: Floating-point values that didn't fit into an FP
2888 register are only written to memory. */
2891 /* Remember if the argument was written to the stack. */
2892 int stack_used_p = 0;
2893 int partial_len = (len < mips_saved_regsize (tdep)
2894 ? len : mips_saved_regsize (tdep));
2897 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
2900 /* Write this portion of the argument to the stack. */
2901 if (argreg > MIPS_LAST_ARG_REGNUM
2903 || fp_register_arg_p (typecode, arg_type))
2905 /* Should shorter than int integer values be
2906 promoted to int before being stored? */
2907 int longword_offset = 0;
2910 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2912 if (mips_stack_argsize (tdep) == 8
2913 && (typecode == TYPE_CODE_INT
2914 || typecode == TYPE_CODE_PTR
2915 || typecode == TYPE_CODE_FLT) && len <= 4)
2916 longword_offset = mips_stack_argsize (tdep) - len;
2917 else if ((typecode == TYPE_CODE_STRUCT
2918 || typecode == TYPE_CODE_UNION)
2919 && (TYPE_LENGTH (arg_type)
2920 < mips_stack_argsize (tdep)))
2921 longword_offset = mips_stack_argsize (tdep) - len;
2926 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
2927 paddr_nz (stack_offset));
2928 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
2929 paddr_nz (longword_offset));
2932 addr = sp + stack_offset + longword_offset;
2937 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
2939 for (i = 0; i < partial_len; i++)
2941 fprintf_unfiltered (gdb_stdlog, "%02x",
2945 write_memory (addr, val, partial_len);
2948 /* Note!!! This is NOT an else clause. Odd sized
2949 structs may go thru BOTH paths. Floating point
2950 arguments will not. */
2951 /* Write this portion of the argument to a general
2952 purpose register. */
2953 if (argreg <= MIPS_LAST_ARG_REGNUM
2954 && !fp_register_arg_p (typecode, arg_type))
2957 extract_unsigned_integer (val, partial_len);
2960 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
2963 mips_saved_regsize (tdep)));
2964 write_register (argreg, regval);
2971 /* Compute the the offset into the stack at which we
2972 will copy the next parameter.
2974 In the new EABI (and the NABI32), the stack_offset
2975 only needs to be adjusted when it has been used. */
2978 stack_offset += align_up (partial_len,
2979 mips_stack_argsize (tdep));
2983 fprintf_unfiltered (gdb_stdlog, "\n");
2986 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
2988 /* Return adjusted stack pointer. */
2992 /* Given a return value in `regbuf' with a type `valtype', extract and
2993 copy its value into `valbuf'. */
2996 mips_eabi_extract_return_value (struct type *valtype,
2997 char regbuf[], char *valbuf)
2999 struct return_value_word lo;
3000 struct return_value_word hi;
3001 return_value_location (valtype, &hi, &lo);
3003 memcpy (valbuf + lo.buf_offset,
3004 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) +
3005 lo.reg_offset, lo.len);
3008 memcpy (valbuf + hi.buf_offset,
3009 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) +
3010 hi.reg_offset, hi.len);
3013 /* Given a return value in `valbuf' with a type `valtype', write it's
3014 value into the appropriate register. */
3017 mips_eabi_store_return_value (struct type *valtype, char *valbuf)
3019 char raw_buffer[MAX_REGISTER_SIZE];
3020 struct return_value_word lo;
3021 struct return_value_word hi;
3022 return_value_location (valtype, &hi, &lo);
3024 memset (raw_buffer, 0, sizeof (raw_buffer));
3025 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
3026 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg),
3027 raw_buffer, register_size (current_gdbarch,
3032 memset (raw_buffer, 0, sizeof (raw_buffer));
3033 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
3034 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg),
3036 register_size (current_gdbarch,
3041 /* N32/N64 ABI stuff. */
3044 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3045 struct regcache *regcache, CORE_ADDR bp_addr,
3046 int nargs, struct value **args, CORE_ADDR sp,
3047 int struct_return, CORE_ADDR struct_addr)
3053 int stack_offset = 0;
3054 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3056 /* For shared libraries, "t9" needs to point at the function
3058 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3060 /* Set the return address register to point to the entry point of
3061 the program, where a breakpoint lies in wait. */
3062 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3064 /* First ensure that the stack and structure return address (if any)
3065 are properly aligned. The stack has to be at least 64-bit
3066 aligned even on 32-bit machines, because doubles must be 64-bit
3067 aligned. For n32 and n64, stack frames need to be 128-bit
3068 aligned, so we round to this widest known alignment. */
3070 sp = align_down (sp, 16);
3071 struct_addr = align_down (struct_addr, 16);
3073 /* Now make space on the stack for the args. */
3074 for (argnum = 0; argnum < nargs; argnum++)
3075 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3076 mips_stack_argsize (tdep));
3077 sp -= align_up (len, 16);
3080 fprintf_unfiltered (gdb_stdlog,
3081 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3082 paddr_nz (sp), (long) align_up (len, 16));
3084 /* Initialize the integer and float register pointers. */
3086 float_argreg = mips_fpa0_regnum (current_gdbarch);
3088 /* The struct_return pointer occupies the first parameter-passing reg. */
3092 fprintf_unfiltered (gdb_stdlog,
3093 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3094 argreg, paddr_nz (struct_addr));
3095 write_register (argreg++, struct_addr);
3098 /* Now load as many as possible of the first arguments into
3099 registers, and push the rest onto the stack. Loop thru args
3100 from first to last. */
3101 for (argnum = 0; argnum < nargs; argnum++)
3104 struct value *arg = args[argnum];
3105 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3106 int len = TYPE_LENGTH (arg_type);
3107 enum type_code typecode = TYPE_CODE (arg_type);
3110 fprintf_unfiltered (gdb_stdlog,
3111 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3112 argnum + 1, len, (int) typecode);
3114 val = (char *) VALUE_CONTENTS (arg);
3116 if (fp_register_arg_p (typecode, arg_type)
3117 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3119 /* This is a floating point value that fits entirely
3120 in a single register. */
3121 /* On 32 bit ABI's the float_argreg is further adjusted
3122 above to ensure that it is even register aligned. */
3123 LONGEST regval = extract_unsigned_integer (val, len);
3125 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3126 float_argreg, phex (regval, len));
3127 write_register (float_argreg++, regval);
3130 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3131 argreg, phex (regval, len));
3132 write_register (argreg, regval);
3137 /* Copy the argument to general registers or the stack in
3138 register-sized pieces. Large arguments are split between
3139 registers and stack. */
3140 /* Note: structs whose size is not a multiple of
3141 mips_regsize() are treated specially: Irix cc passes them
3142 in registers where gcc sometimes puts them on the stack.
3143 For maximum compatibility, we will put them in both
3145 int odd_sized_struct = ((len > mips_saved_regsize (tdep))
3146 && (len % mips_saved_regsize (tdep) != 0));
3147 /* Note: Floating-point values that didn't fit into an FP
3148 register are only written to memory. */
3151 /* Rememer if the argument was written to the stack. */
3152 int stack_used_p = 0;
3153 int partial_len = (len < mips_saved_regsize (tdep)
3154 ? len : mips_saved_regsize (tdep));
3157 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3160 /* Write this portion of the argument to the stack. */
3161 if (argreg > MIPS_LAST_ARG_REGNUM
3163 || fp_register_arg_p (typecode, arg_type))
3165 /* Should shorter than int integer values be
3166 promoted to int before being stored? */
3167 int longword_offset = 0;
3170 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3172 if (mips_stack_argsize (tdep) == 8
3173 && (typecode == TYPE_CODE_INT
3174 || typecode == TYPE_CODE_PTR
3175 || typecode == TYPE_CODE_FLT) && len <= 4)
3176 longword_offset = mips_stack_argsize (tdep) - len;
3181 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3182 paddr_nz (stack_offset));
3183 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3184 paddr_nz (longword_offset));
3187 addr = sp + stack_offset + longword_offset;
3192 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3194 for (i = 0; i < partial_len; i++)
3196 fprintf_unfiltered (gdb_stdlog, "%02x",
3200 write_memory (addr, val, partial_len);
3203 /* Note!!! This is NOT an else clause. Odd sized
3204 structs may go thru BOTH paths. Floating point
3205 arguments will not. */
3206 /* Write this portion of the argument to a general
3207 purpose register. */
3208 if (argreg <= MIPS_LAST_ARG_REGNUM
3209 && !fp_register_arg_p (typecode, arg_type))
3212 extract_unsigned_integer (val, partial_len);
3214 /* A non-floating-point argument being passed in a
3215 general register. If a struct or union, and if
3216 the remaining length is smaller than the register
3217 size, we have to adjust the register value on
3220 It does not seem to be necessary to do the
3221 same for integral types.
3223 cagney/2001-07-23: gdb/179: Also, GCC, when
3224 outputting LE O32 with sizeof (struct) <
3225 mips_saved_regsize(), generates a left shift as
3226 part of storing the argument in a register a
3227 register (the left shift isn't generated when
3228 sizeof (struct) >= mips_saved_regsize()). Since
3229 it is quite possible that this is GCC
3230 contradicting the LE/O32 ABI, GDB has not been
3231 adjusted to accommodate this. Either someone
3232 needs to demonstrate that the LE/O32 ABI
3233 specifies such a left shift OR this new ABI gets
3234 identified as such and GDB gets tweaked
3237 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3238 && partial_len < mips_saved_regsize (tdep)
3239 && (typecode == TYPE_CODE_STRUCT ||
3240 typecode == TYPE_CODE_UNION))
3241 regval <<= ((mips_saved_regsize (tdep) - partial_len) *
3245 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3248 mips_saved_regsize (tdep)));
3249 write_register (argreg, regval);
3256 /* Compute the the offset into the stack at which we
3257 will copy the next parameter.
3259 In N32 (N64?), the stack_offset only needs to be
3260 adjusted when it has been used. */
3263 stack_offset += align_up (partial_len,
3264 mips_stack_argsize (tdep));
3268 fprintf_unfiltered (gdb_stdlog, "\n");
3271 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3273 /* Return adjusted stack pointer. */
3277 static enum return_value_convention
3278 mips_n32n64_return_value (struct gdbarch *gdbarch,
3279 struct type *type, struct regcache *regcache,
3280 void *readbuf, const void *writebuf)
3282 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3283 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3284 || TYPE_CODE (type) == TYPE_CODE_UNION
3285 || TYPE_CODE (type) == TYPE_CODE_ARRAY
3286 || TYPE_LENGTH (type) > 2 * mips_saved_regsize (tdep))
3287 return RETURN_VALUE_STRUCT_CONVENTION;
3288 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3289 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3291 /* A floating-point value belongs in the least significant part
3294 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3295 mips_xfer_register (regcache,
3296 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
3298 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3299 return RETURN_VALUE_REGISTER_CONVENTION;
3301 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3302 && TYPE_NFIELDS (type) <= 2
3303 && TYPE_NFIELDS (type) >= 1
3304 && ((TYPE_NFIELDS (type) == 1
3305 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3307 || (TYPE_NFIELDS (type) == 2
3308 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3310 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3312 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3314 /* A struct that contains one or two floats. Each value is part
3315 in the least significant part of their floating point
3319 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
3320 field < TYPE_NFIELDS (type); field++, regnum += 2)
3322 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3325 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3327 mips_xfer_register (regcache, NUM_REGS + regnum,
3328 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3329 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3331 return RETURN_VALUE_REGISTER_CONVENTION;
3333 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3334 || TYPE_CODE (type) == TYPE_CODE_UNION)
3336 /* A structure or union. Extract the left justified value,
3337 regardless of the byte order. I.e. DO NOT USE
3341 for (offset = 0, regnum = V0_REGNUM;
3342 offset < TYPE_LENGTH (type);
3343 offset += register_size (current_gdbarch, regnum), regnum++)
3345 int xfer = register_size (current_gdbarch, regnum);
3346 if (offset + xfer > TYPE_LENGTH (type))
3347 xfer = TYPE_LENGTH (type) - offset;
3349 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3350 offset, xfer, regnum);
3351 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3352 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3354 return RETURN_VALUE_REGISTER_CONVENTION;
3358 /* A scalar extract each part but least-significant-byte
3362 for (offset = 0, regnum = V0_REGNUM;
3363 offset < TYPE_LENGTH (type);
3364 offset += register_size (current_gdbarch, regnum), regnum++)
3366 int xfer = register_size (current_gdbarch, regnum);
3367 if (offset + xfer > TYPE_LENGTH (type))
3368 xfer = TYPE_LENGTH (type) - offset;
3370 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3371 offset, xfer, regnum);
3372 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3373 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3375 return RETURN_VALUE_REGISTER_CONVENTION;
3379 /* O32 ABI stuff. */
3382 mips_o32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3383 struct regcache *regcache, CORE_ADDR bp_addr,
3384 int nargs, struct value **args, CORE_ADDR sp,
3385 int struct_return, CORE_ADDR struct_addr)
3391 int stack_offset = 0;
3392 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3394 /* For shared libraries, "t9" needs to point at the function
3396 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3398 /* Set the return address register to point to the entry point of
3399 the program, where a breakpoint lies in wait. */
3400 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3402 /* First ensure that the stack and structure return address (if any)
3403 are properly aligned. The stack has to be at least 64-bit
3404 aligned even on 32-bit machines, because doubles must be 64-bit
3405 aligned. For n32 and n64, stack frames need to be 128-bit
3406 aligned, so we round to this widest known alignment. */
3408 sp = align_down (sp, 16);
3409 struct_addr = align_down (struct_addr, 16);
3411 /* Now make space on the stack for the args. */
3412 for (argnum = 0; argnum < nargs; argnum++)
3413 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3414 mips_stack_argsize (tdep));
3415 sp -= align_up (len, 16);
3418 fprintf_unfiltered (gdb_stdlog,
3419 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3420 paddr_nz (sp), (long) align_up (len, 16));
3422 /* Initialize the integer and float register pointers. */
3424 float_argreg = mips_fpa0_regnum (current_gdbarch);
3426 /* The struct_return pointer occupies the first parameter-passing reg. */
3430 fprintf_unfiltered (gdb_stdlog,
3431 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3432 argreg, paddr_nz (struct_addr));
3433 write_register (argreg++, struct_addr);
3434 stack_offset += mips_stack_argsize (tdep);
3437 /* Now load as many as possible of the first arguments into
3438 registers, and push the rest onto the stack. Loop thru args
3439 from first to last. */
3440 for (argnum = 0; argnum < nargs; argnum++)
3443 struct value *arg = args[argnum];
3444 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3445 int len = TYPE_LENGTH (arg_type);
3446 enum type_code typecode = TYPE_CODE (arg_type);
3449 fprintf_unfiltered (gdb_stdlog,
3450 "mips_o32_push_dummy_call: %d len=%d type=%d",
3451 argnum + 1, len, (int) typecode);
3453 val = (char *) VALUE_CONTENTS (arg);
3455 /* 32-bit ABIs always start floating point arguments in an
3456 even-numbered floating point register. Round the FP register
3457 up before the check to see if there are any FP registers
3458 left. O32/O64 targets also pass the FP in the integer
3459 registers so also round up normal registers. */
3460 if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type))
3462 if ((float_argreg & 1))
3466 /* Floating point arguments passed in registers have to be
3467 treated specially. On 32-bit architectures, doubles
3468 are passed in register pairs; the even register gets
3469 the low word, and the odd register gets the high word.
3470 On O32/O64, the first two floating point arguments are
3471 also copied to general registers, because MIPS16 functions
3472 don't use float registers for arguments. This duplication of
3473 arguments in general registers can't hurt non-MIPS16 functions
3474 because those registers are normally skipped. */
3476 if (fp_register_arg_p (typecode, arg_type)
3477 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3479 if (!FP_REGISTER_DOUBLE && len == 8)
3481 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3482 unsigned long regval;
3484 /* Write the low word of the double to the even register(s). */
3485 regval = extract_unsigned_integer (val + low_offset, 4);
3487 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3488 float_argreg, phex (regval, 4));
3489 write_register (float_argreg++, regval);
3491 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3492 argreg, phex (regval, 4));
3493 write_register (argreg++, regval);
3495 /* Write the high word of the double to the odd register(s). */
3496 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3498 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3499 float_argreg, phex (regval, 4));
3500 write_register (float_argreg++, regval);
3503 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3504 argreg, phex (regval, 4));
3505 write_register (argreg++, regval);
3509 /* This is a floating point value that fits entirely
3510 in a single register. */
3511 /* On 32 bit ABI's the float_argreg is further adjusted
3512 above to ensure that it is even register aligned. */
3513 LONGEST regval = extract_unsigned_integer (val, len);
3515 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3516 float_argreg, phex (regval, len));
3517 write_register (float_argreg++, regval);
3518 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3519 registers for each argument. The below is (my
3520 guess) to ensure that the corresponding integer
3521 register has reserved the same space. */
3523 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3524 argreg, phex (regval, len));
3525 write_register (argreg, regval);
3526 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3528 /* Reserve space for the FP register. */
3529 stack_offset += align_up (len, mips_stack_argsize (tdep));
3533 /* Copy the argument to general registers or the stack in
3534 register-sized pieces. Large arguments are split between
3535 registers and stack. */
3536 /* Note: structs whose size is not a multiple of
3537 mips_regsize() are treated specially: Irix cc passes them
3538 in registers where gcc sometimes puts them on the stack.
3539 For maximum compatibility, we will put them in both
3541 int odd_sized_struct = ((len > mips_saved_regsize (tdep))
3542 && (len % mips_saved_regsize (tdep) != 0));
3543 /* Structures should be aligned to eight bytes (even arg registers)
3544 on MIPS_ABI_O32, if their first member has double precision. */
3545 if (mips_saved_regsize (tdep) < 8
3546 && mips_type_needs_double_align (arg_type))
3551 /* Note: Floating-point values that didn't fit into an FP
3552 register are only written to memory. */
3555 /* Remember if the argument was written to the stack. */
3556 int stack_used_p = 0;
3557 int partial_len = (len < mips_saved_regsize (tdep)
3558 ? len : mips_saved_regsize (tdep));
3561 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
3564 /* Write this portion of the argument to the stack. */
3565 if (argreg > MIPS_LAST_ARG_REGNUM
3567 || fp_register_arg_p (typecode, arg_type))
3569 /* Should shorter than int integer values be
3570 promoted to int before being stored? */
3571 int longword_offset = 0;
3574 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3576 if (mips_stack_argsize (tdep) == 8
3577 && (typecode == TYPE_CODE_INT
3578 || typecode == TYPE_CODE_PTR
3579 || typecode == TYPE_CODE_FLT) && len <= 4)
3580 longword_offset = mips_stack_argsize (tdep) - len;
3585 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
3586 paddr_nz (stack_offset));
3587 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
3588 paddr_nz (longword_offset));
3591 addr = sp + stack_offset + longword_offset;
3596 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
3598 for (i = 0; i < partial_len; i++)
3600 fprintf_unfiltered (gdb_stdlog, "%02x",
3604 write_memory (addr, val, partial_len);
3607 /* Note!!! This is NOT an else clause. Odd sized
3608 structs may go thru BOTH paths. Floating point
3609 arguments will not. */
3610 /* Write this portion of the argument to a general
3611 purpose register. */
3612 if (argreg <= MIPS_LAST_ARG_REGNUM
3613 && !fp_register_arg_p (typecode, arg_type))
3615 LONGEST regval = extract_signed_integer (val, partial_len);
3616 /* Value may need to be sign extended, because
3617 mips_regsize() != mips_saved_regsize(). */
3619 /* A non-floating-point argument being passed in a
3620 general register. If a struct or union, and if
3621 the remaining length is smaller than the register
3622 size, we have to adjust the register value on
3625 It does not seem to be necessary to do the
3626 same for integral types.
3628 Also don't do this adjustment on O64 binaries.
3630 cagney/2001-07-23: gdb/179: Also, GCC, when
3631 outputting LE O32 with sizeof (struct) <
3632 mips_saved_regsize(), generates a left shift as
3633 part of storing the argument in a register a
3634 register (the left shift isn't generated when
3635 sizeof (struct) >= mips_saved_regsize()). Since
3636 it is quite possible that this is GCC
3637 contradicting the LE/O32 ABI, GDB has not been
3638 adjusted to accommodate this. Either someone
3639 needs to demonstrate that the LE/O32 ABI
3640 specifies such a left shift OR this new ABI gets
3641 identified as such and GDB gets tweaked
3644 if (mips_saved_regsize (tdep) < 8
3645 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3646 && partial_len < mips_saved_regsize (tdep)
3647 && (typecode == TYPE_CODE_STRUCT ||
3648 typecode == TYPE_CODE_UNION))
3649 regval <<= ((mips_saved_regsize (tdep) - partial_len) *
3653 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
3656 mips_saved_regsize (tdep)));
3657 write_register (argreg, regval);
3660 /* Prevent subsequent floating point arguments from
3661 being passed in floating point registers. */
3662 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
3668 /* Compute the the offset into the stack at which we
3669 will copy the next parameter.
3671 In older ABIs, the caller reserved space for
3672 registers that contained arguments. This was loosely
3673 refered to as their "home". Consequently, space is
3674 always allocated. */
3676 stack_offset += align_up (partial_len,
3677 mips_stack_argsize (tdep));
3681 fprintf_unfiltered (gdb_stdlog, "\n");
3684 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
3686 /* Return adjusted stack pointer. */
3690 static enum return_value_convention
3691 mips_o32_return_value (struct gdbarch *gdbarch, struct type *type,
3692 struct regcache *regcache,
3693 void *readbuf, const void *writebuf)
3695 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3697 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3698 || TYPE_CODE (type) == TYPE_CODE_UNION
3699 || TYPE_CODE (type) == TYPE_CODE_ARRAY)
3700 return RETURN_VALUE_STRUCT_CONVENTION;
3701 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3702 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3704 /* A single-precision floating-point value. It fits in the
3705 least significant part of FP0. */
3707 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
3708 mips_xfer_register (regcache,
3709 NUM_REGS + mips_regnum (current_gdbarch)->fp0,
3711 TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3712 return RETURN_VALUE_REGISTER_CONVENTION;
3714 else if (TYPE_CODE (type) == TYPE_CODE_FLT
3715 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3717 /* A double-precision floating-point value. The most
3718 significant part goes in FP1, and the least significant in
3721 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
3722 switch (TARGET_BYTE_ORDER)
3724 case BFD_ENDIAN_LITTLE:
3725 mips_xfer_register (regcache,
3726 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3727 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3728 mips_xfer_register (regcache,
3729 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3730 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3732 case BFD_ENDIAN_BIG:
3733 mips_xfer_register (regcache,
3734 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3735 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0);
3736 mips_xfer_register (regcache,
3737 NUM_REGS + mips_regnum (current_gdbarch)->fp0 +
3738 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4);
3741 internal_error (__FILE__, __LINE__, "bad switch");
3743 return RETURN_VALUE_REGISTER_CONVENTION;
3746 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3747 && TYPE_NFIELDS (type) <= 2
3748 && TYPE_NFIELDS (type) >= 1
3749 && ((TYPE_NFIELDS (type) == 1
3750 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3752 || (TYPE_NFIELDS (type) == 2
3753 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
3755 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
3757 && tdep->mips_fpu_type != MIPS_FPU_NONE)
3759 /* A struct that contains one or two floats. Each value is part
3760 in the least significant part of their floating point
3762 bfd_byte reg[MAX_REGISTER_SIZE];
3765 for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0;
3766 field < TYPE_NFIELDS (type); field++, regnum += 2)
3768 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
3771 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
3773 mips_xfer_register (regcache, NUM_REGS + regnum,
3774 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
3775 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3777 return RETURN_VALUE_REGISTER_CONVENTION;
3781 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
3782 || TYPE_CODE (type) == TYPE_CODE_UNION)
3784 /* A structure or union. Extract the left justified value,
3785 regardless of the byte order. I.e. DO NOT USE
3789 for (offset = 0, regnum = V0_REGNUM;
3790 offset < TYPE_LENGTH (type);
3791 offset += register_size (current_gdbarch, regnum), regnum++)
3793 int xfer = register_size (current_gdbarch, regnum);
3794 if (offset + xfer > TYPE_LENGTH (type))
3795 xfer = TYPE_LENGTH (type) - offset;
3797 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
3798 offset, xfer, regnum);
3799 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3800 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
3802 return RETURN_VALUE_REGISTER_CONVENTION;
3807 /* A scalar extract each part but least-significant-byte
3808 justified. o32 thinks registers are 4 byte, regardless of
3809 the ISA. mips_stack_argsize controls this. */
3812 for (offset = 0, regnum = V0_REGNUM;
3813 offset < TYPE_LENGTH (type);
3814 offset += mips_stack_argsize (tdep), regnum++)
3816 int xfer = mips_stack_argsize (tdep);
3817 if (offset + xfer > TYPE_LENGTH (type))
3818 xfer = TYPE_LENGTH (type) - offset;
3820 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
3821 offset, xfer, regnum);
3822 mips_xfer_register (regcache, NUM_REGS + regnum, xfer,
3823 TARGET_BYTE_ORDER, readbuf, writebuf, offset);
3825 return RETURN_VALUE_REGISTER_CONVENTION;
3829 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3833 mips_o64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
3834 struct regcache *regcache, CORE_ADDR bp_addr,
3836 struct value **args, CORE_ADDR sp,
3837 int struct_return, CORE_ADDR struct_addr)
3843 int stack_offset = 0;
3844 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3846 /* For shared libraries, "t9" needs to point at the function
3848 regcache_cooked_write_signed (regcache, T9_REGNUM, func_addr);
3850 /* Set the return address register to point to the entry point of
3851 the program, where a breakpoint lies in wait. */
3852 regcache_cooked_write_signed (regcache, RA_REGNUM, bp_addr);
3854 /* First ensure that the stack and structure return address (if any)
3855 are properly aligned. The stack has to be at least 64-bit
3856 aligned even on 32-bit machines, because doubles must be 64-bit
3857 aligned. For n32 and n64, stack frames need to be 128-bit
3858 aligned, so we round to this widest known alignment. */
3860 sp = align_down (sp, 16);
3861 struct_addr = align_down (struct_addr, 16);
3863 /* Now make space on the stack for the args. */
3864 for (argnum = 0; argnum < nargs; argnum++)
3865 len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])),
3866 mips_stack_argsize (tdep));
3867 sp -= align_up (len, 16);
3870 fprintf_unfiltered (gdb_stdlog,
3871 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3872 paddr_nz (sp), (long) align_up (len, 16));
3874 /* Initialize the integer and float register pointers. */
3876 float_argreg = mips_fpa0_regnum (current_gdbarch);
3878 /* The struct_return pointer occupies the first parameter-passing reg. */
3882 fprintf_unfiltered (gdb_stdlog,
3883 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3884 argreg, paddr_nz (struct_addr));
3885 write_register (argreg++, struct_addr);
3886 stack_offset += mips_stack_argsize (tdep);
3889 /* Now load as many as possible of the first arguments into
3890 registers, and push the rest onto the stack. Loop thru args
3891 from first to last. */
3892 for (argnum = 0; argnum < nargs; argnum++)
3895 struct value *arg = args[argnum];
3896 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
3897 int len = TYPE_LENGTH (arg_type);
3898 enum type_code typecode = TYPE_CODE (arg_type);
3901 fprintf_unfiltered (gdb_stdlog,
3902 "mips_o64_push_dummy_call: %d len=%d type=%d",
3903 argnum + 1, len, (int) typecode);
3905 val = (char *) VALUE_CONTENTS (arg);
3907 /* 32-bit ABIs always start floating point arguments in an
3908 even-numbered floating point register. Round the FP register
3909 up before the check to see if there are any FP registers
3910 left. O32/O64 targets also pass the FP in the integer
3911 registers so also round up normal registers. */
3912 if (!FP_REGISTER_DOUBLE && fp_register_arg_p (typecode, arg_type))
3914 if ((float_argreg & 1))
3918 /* Floating point arguments passed in registers have to be
3919 treated specially. On 32-bit architectures, doubles
3920 are passed in register pairs; the even register gets
3921 the low word, and the odd register gets the high word.
3922 On O32/O64, the first two floating point arguments are
3923 also copied to general registers, because MIPS16 functions
3924 don't use float registers for arguments. This duplication of
3925 arguments in general registers can't hurt non-MIPS16 functions
3926 because those registers are normally skipped. */
3928 if (fp_register_arg_p (typecode, arg_type)
3929 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM)
3931 if (!FP_REGISTER_DOUBLE && len == 8)
3933 int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0;
3934 unsigned long regval;
3936 /* Write the low word of the double to the even register(s). */
3937 regval = extract_unsigned_integer (val + low_offset, 4);
3939 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3940 float_argreg, phex (regval, 4));
3941 write_register (float_argreg++, regval);
3943 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3944 argreg, phex (regval, 4));
3945 write_register (argreg++, regval);
3947 /* Write the high word of the double to the odd register(s). */
3948 regval = extract_unsigned_integer (val + 4 - low_offset, 4);
3950 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3951 float_argreg, phex (regval, 4));
3952 write_register (float_argreg++, regval);
3955 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3956 argreg, phex (regval, 4));
3957 write_register (argreg++, regval);
3961 /* This is a floating point value that fits entirely
3962 in a single register. */
3963 /* On 32 bit ABI's the float_argreg is further adjusted
3964 above to ensure that it is even register aligned. */
3965 LONGEST regval = extract_unsigned_integer (val, len);
3967 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
3968 float_argreg, phex (regval, len));
3969 write_register (float_argreg++, regval);
3970 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3971 registers for each argument. The below is (my
3972 guess) to ensure that the corresponding integer
3973 register has reserved the same space. */
3975 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
3976 argreg, phex (regval, len));
3977 write_register (argreg, regval);
3978 argreg += FP_REGISTER_DOUBLE ? 1 : 2;
3980 /* Reserve space for the FP register. */
3981 stack_offset += align_up (len, mips_stack_argsize (tdep));
3985 /* Copy the argument to general registers or the stack in
3986 register-sized pieces. Large arguments are split between
3987 registers and stack. */
3988 /* Note: structs whose size is not a multiple of
3989 mips_regsize() are treated specially: Irix cc passes them
3990 in registers where gcc sometimes puts them on the stack.
3991 For maximum compatibility, we will put them in both
3993 int odd_sized_struct = ((len > mips_saved_regsize (tdep))
3994 && (len % mips_saved_regsize (tdep) != 0));
3995 /* Structures should be aligned to eight bytes (even arg registers)
3996 on MIPS_ABI_O32, if their first member has double precision. */
3997 if (mips_saved_regsize (tdep) < 8
3998 && mips_type_needs_double_align (arg_type))
4003 /* Note: Floating-point values that didn't fit into an FP
4004 register are only written to memory. */
4007 /* Remember if the argument was written to the stack. */
4008 int stack_used_p = 0;
4009 int partial_len = (len < mips_saved_regsize (tdep)
4010 ? len : mips_saved_regsize (tdep));
4013 fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
4016 /* Write this portion of the argument to the stack. */
4017 if (argreg > MIPS_LAST_ARG_REGNUM
4019 || fp_register_arg_p (typecode, arg_type))
4021 /* Should shorter than int integer values be
4022 promoted to int before being stored? */
4023 int longword_offset = 0;
4026 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4028 if (mips_stack_argsize (tdep) == 8
4029 && (typecode == TYPE_CODE_INT
4030 || typecode == TYPE_CODE_PTR
4031 || typecode == TYPE_CODE_FLT) && len <= 4)
4032 longword_offset = mips_stack_argsize (tdep) - len;
4037 fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s",
4038 paddr_nz (stack_offset));
4039 fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s",
4040 paddr_nz (longword_offset));
4043 addr = sp + stack_offset + longword_offset;
4048 fprintf_unfiltered (gdb_stdlog, " @0x%s ",
4050 for (i = 0; i < partial_len; i++)
4052 fprintf_unfiltered (gdb_stdlog, "%02x",
4056 write_memory (addr, val, partial_len);
4059 /* Note!!! This is NOT an else clause. Odd sized
4060 structs may go thru BOTH paths. Floating point
4061 arguments will not. */
4062 /* Write this portion of the argument to a general
4063 purpose register. */
4064 if (argreg <= MIPS_LAST_ARG_REGNUM
4065 && !fp_register_arg_p (typecode, arg_type))
4067 LONGEST regval = extract_signed_integer (val, partial_len);
4068 /* Value may need to be sign extended, because
4069 mips_regsize() != mips_saved_regsize(). */
4071 /* A non-floating-point argument being passed in a
4072 general register. If a struct or union, and if
4073 the remaining length is smaller than the register
4074 size, we have to adjust the register value on
4077 It does not seem to be necessary to do the
4078 same for integral types.
4080 Also don't do this adjustment on O64 binaries.
4082 cagney/2001-07-23: gdb/179: Also, GCC, when
4083 outputting LE O32 with sizeof (struct) <
4084 mips_saved_regsize(), generates a left shift as
4085 part of storing the argument in a register a
4086 register (the left shift isn't generated when
4087 sizeof (struct) >= mips_saved_regsize()). Since
4088 it is quite possible that this is GCC
4089 contradicting the LE/O32 ABI, GDB has not been
4090 adjusted to accommodate this. Either someone
4091 needs to demonstrate that the LE/O32 ABI
4092 specifies such a left shift OR this new ABI gets
4093 identified as such and GDB gets tweaked
4096 if (mips_saved_regsize (tdep) < 8
4097 && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
4098 && partial_len < mips_saved_regsize (tdep)
4099 && (typecode == TYPE_CODE_STRUCT ||
4100 typecode == TYPE_CODE_UNION))
4101 regval <<= ((mips_saved_regsize (tdep) - partial_len) *
4105 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
4108 mips_saved_regsize (tdep)));
4109 write_register (argreg, regval);
4112 /* Prevent subsequent floating point arguments from
4113 being passed in floating point registers. */
4114 float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1;
4120 /* Compute the the offset into the stack at which we
4121 will copy the next parameter.
4123 In older ABIs, the caller reserved space for
4124 registers that contained arguments. This was loosely
4125 refered to as their "home". Consequently, space is
4126 always allocated. */
4128 stack_offset += align_up (partial_len,
4129 mips_stack_argsize (tdep));
4133 fprintf_unfiltered (gdb_stdlog, "\n");
4136 regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
4138 /* Return adjusted stack pointer. */
4143 mips_o64_extract_return_value (struct type *valtype,
4144 char regbuf[], char *valbuf)
4146 struct return_value_word lo;
4147 struct return_value_word hi;
4148 return_value_location (valtype, &hi, &lo);
4150 memcpy (valbuf + lo.buf_offset,
4151 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + lo.reg) +
4152 lo.reg_offset, lo.len);
4155 memcpy (valbuf + hi.buf_offset,
4156 regbuf + DEPRECATED_REGISTER_BYTE (NUM_REGS + hi.reg) +
4157 hi.reg_offset, hi.len);
4161 mips_o64_store_return_value (struct type *valtype, char *valbuf)
4163 char raw_buffer[MAX_REGISTER_SIZE];
4164 struct return_value_word lo;
4165 struct return_value_word hi;
4166 return_value_location (valtype, &hi, &lo);
4168 memset (raw_buffer, 0, sizeof (raw_buffer));
4169 memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len);
4170 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo.reg),
4171 raw_buffer, register_size (current_gdbarch,
4176 memset (raw_buffer, 0, sizeof (raw_buffer));
4177 memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len);
4178 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi.reg),
4180 register_size (current_gdbarch,
4185 /* Floating point register management.
4187 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4188 64bit operations, these early MIPS cpus treat fp register pairs
4189 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4190 registers and offer a compatibility mode that emulates the MIPS2 fp
4191 model. When operating in MIPS2 fp compat mode, later cpu's split
4192 double precision floats into two 32-bit chunks and store them in
4193 consecutive fp regs. To display 64-bit floats stored in this
4194 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4195 Throw in user-configurable endianness and you have a real mess.
4197 The way this works is:
4198 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4199 double-precision value will be split across two logical registers.
4200 The lower-numbered logical register will hold the low-order bits,
4201 regardless of the processor's endianness.
4202 - If we are on a 64-bit processor, and we are looking for a
4203 single-precision value, it will be in the low ordered bits
4204 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4205 save slot in memory.
4206 - If we are in 64-bit mode, everything is straightforward.
4208 Note that this code only deals with "live" registers at the top of the
4209 stack. We will attempt to deal with saved registers later, when
4210 the raw/cooked register interface is in place. (We need a general
4211 interface that can deal with dynamic saved register sizes -- fp
4212 regs could be 32 bits wide in one frame and 64 on the frame above
4215 static struct type *
4216 mips_float_register_type (void)
4218 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4219 return builtin_type_ieee_single_big;
4221 return builtin_type_ieee_single_little;
4224 static struct type *
4225 mips_double_register_type (void)
4227 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4228 return builtin_type_ieee_double_big;
4230 return builtin_type_ieee_double_little;
4233 /* Copy a 32-bit single-precision value from the current frame
4234 into rare_buffer. */
4237 mips_read_fp_register_single (struct frame_info *frame, int regno,
4240 int raw_size = register_size (current_gdbarch, regno);
4241 char *raw_buffer = alloca (raw_size);
4243 if (!frame_register_read (frame, regno, raw_buffer))
4244 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4247 /* We have a 64-bit value for this register. Find the low-order
4251 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4256 memcpy (rare_buffer, raw_buffer + offset, 4);
4260 memcpy (rare_buffer, raw_buffer, 4);
4264 /* Copy a 64-bit double-precision value from the current frame into
4265 rare_buffer. This may include getting half of it from the next
4269 mips_read_fp_register_double (struct frame_info *frame, int regno,
4272 int raw_size = register_size (current_gdbarch, regno);
4274 if (raw_size == 8 && !mips2_fp_compat ())
4276 /* We have a 64-bit value for this register, and we should use
4278 if (!frame_register_read (frame, regno, rare_buffer))
4279 error ("can't read register %d (%s)", regno, REGISTER_NAME (regno));
4283 if ((regno - mips_regnum (current_gdbarch)->fp0) & 1)
4284 internal_error (__FILE__, __LINE__,
4285 "mips_read_fp_register_double: bad access to "
4286 "odd-numbered FP register");
4288 /* mips_read_fp_register_single will find the correct 32 bits from
4290 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4292 mips_read_fp_register_single (frame, regno, rare_buffer + 4);
4293 mips_read_fp_register_single (frame, regno + 1, rare_buffer);
4297 mips_read_fp_register_single (frame, regno, rare_buffer);
4298 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4);
4304 mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
4306 { /* do values for FP (float) regs */
4308 double doub, flt1; /* doubles extracted from raw hex data */
4312 (char *) alloca (2 *
4313 register_size (current_gdbarch,
4314 mips_regnum (current_gdbarch)->fp0));
4316 fprintf_filtered (file, "%s:", REGISTER_NAME (regnum));
4317 fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)),
4320 if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ())
4322 /* 4-byte registers: Print hex and floating. Also print even
4323 numbered registers as doubles. */
4324 mips_read_fp_register_single (frame, regnum, raw_buffer);
4325 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4327 print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w',
4330 fprintf_filtered (file, " flt: ");
4332 fprintf_filtered (file, " <invalid float> ");
4334 fprintf_filtered (file, "%-17.9g", flt1);
4336 if (regnum % 2 == 0)
4338 mips_read_fp_register_double (frame, regnum, raw_buffer);
4339 doub = unpack_double (mips_double_register_type (), raw_buffer,
4342 fprintf_filtered (file, " dbl: ");
4344 fprintf_filtered (file, "<invalid double>");
4346 fprintf_filtered (file, "%-24.17g", doub);
4351 /* Eight byte registers: print each one as hex, float and double. */
4352 mips_read_fp_register_single (frame, regnum, raw_buffer);
4353 flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1);
4355 mips_read_fp_register_double (frame, regnum, raw_buffer);
4356 doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2);
4359 print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g',
4362 fprintf_filtered (file, " flt: ");
4364 fprintf_filtered (file, "<invalid float>");
4366 fprintf_filtered (file, "%-17.9g", flt1);
4368 fprintf_filtered (file, " dbl: ");
4370 fprintf_filtered (file, "<invalid double>");
4372 fprintf_filtered (file, "%-24.17g", doub);
4377 mips_print_register (struct ui_file *file, struct frame_info *frame,
4378 int regnum, int all)
4380 struct gdbarch *gdbarch = get_frame_arch (frame);
4381 char raw_buffer[MAX_REGISTER_SIZE];
4384 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
4386 mips_print_fp_register (file, frame, regnum);
4390 /* Get the data in raw format. */
4391 if (!frame_register_read (frame, regnum, raw_buffer))
4393 fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum));
4397 fputs_filtered (REGISTER_NAME (regnum), file);
4399 /* The problem with printing numeric register names (r26, etc.) is that
4400 the user can't use them on input. Probably the best solution is to
4401 fix it so that either the numeric or the funky (a2, etc.) names
4402 are accepted on input. */
4403 if (regnum < MIPS_NUMREGS)
4404 fprintf_filtered (file, "(r%d): ", regnum);
4406 fprintf_filtered (file, ": ");
4408 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4410 register_size (current_gdbarch,
4411 regnum) - register_size (current_gdbarch, regnum);
4415 print_scalar_formatted (raw_buffer + offset,
4416 gdbarch_register_type (gdbarch, regnum), 'x', 0,
4420 /* Replacement for generic do_registers_info.
4421 Print regs in pretty columns. */
4424 print_fp_register_row (struct ui_file *file, struct frame_info *frame,
4427 fprintf_filtered (file, " ");
4428 mips_print_fp_register (file, frame, regnum);
4429 fprintf_filtered (file, "\n");
4434 /* Print a row's worth of GP (int) registers, with name labels above */
4437 print_gp_register_row (struct ui_file *file, struct frame_info *frame,
4440 struct gdbarch *gdbarch = get_frame_arch (frame);
4441 /* do values for GP (int) regs */
4442 char raw_buffer[MAX_REGISTER_SIZE];
4443 int ncols = (mips_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */
4447 /* For GP registers, we print a separate row of names above the vals */
4448 fprintf_filtered (file, " ");
4449 for (col = 0, regnum = start_regnum;
4450 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4452 if (*REGISTER_NAME (regnum) == '\0')
4453 continue; /* unused register */
4454 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4456 break; /* end the row: reached FP register */
4457 fprintf_filtered (file,
4458 mips_regsize (current_gdbarch) == 8 ? "%17s" : "%9s",
4459 REGISTER_NAME (regnum));
4462 /* print the R0 to R31 names */
4463 if ((start_regnum % NUM_REGS) < MIPS_NUMREGS)
4464 fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS);
4466 fprintf_filtered (file, "\n ");
4468 /* now print the values in hex, 4 or 8 to the row */
4469 for (col = 0, regnum = start_regnum;
4470 col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
4472 if (*REGISTER_NAME (regnum) == '\0')
4473 continue; /* unused register */
4474 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4476 break; /* end row: reached FP register */
4477 /* OK: get the data in raw format. */
4478 if (!frame_register_read (frame, regnum, raw_buffer))
4479 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4480 /* pad small registers */
4482 byte < (mips_regsize (current_gdbarch)
4483 - register_size (current_gdbarch, regnum)); byte++)
4484 printf_filtered (" ");
4485 /* Now print the register value in hex, endian order. */
4486 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4488 register_size (current_gdbarch,
4489 regnum) - register_size (current_gdbarch, regnum);
4490 byte < register_size (current_gdbarch, regnum); byte++)
4491 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4493 for (byte = register_size (current_gdbarch, regnum) - 1;
4495 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]);
4496 fprintf_filtered (file, " ");
4499 if (col > 0) /* ie. if we actually printed anything... */
4500 fprintf_filtered (file, "\n");
4505 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4508 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
4509 struct frame_info *frame, int regnum, int all)
4511 if (regnum != -1) /* do one specified register */
4513 gdb_assert (regnum >= NUM_REGS);
4514 if (*(REGISTER_NAME (regnum)) == '\0')
4515 error ("Not a valid register for the current processor type");
4517 mips_print_register (file, frame, regnum, 0);
4518 fprintf_filtered (file, "\n");
4521 /* do all (or most) registers */
4524 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4526 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
4529 if (all) /* true for "INFO ALL-REGISTERS" command */
4530 regnum = print_fp_register_row (file, frame, regnum);
4532 regnum += MIPS_NUMREGS; /* skip floating point regs */
4535 regnum = print_gp_register_row (file, frame, regnum);
4540 /* Is this a branch with a delay slot? */
4542 static int is_delayed (unsigned long);
4545 is_delayed (unsigned long insn)
4548 for (i = 0; i < NUMOPCODES; ++i)
4549 if (mips_opcodes[i].pinfo != INSN_MACRO
4550 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match)
4552 return (i < NUMOPCODES
4553 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY
4554 | INSN_COND_BRANCH_DELAY
4555 | INSN_COND_BRANCH_LIKELY)));
4559 mips_step_skips_delay (CORE_ADDR pc)
4561 char buf[MIPS_INSTLEN];
4563 /* There is no branch delay slot on MIPS16. */
4564 if (pc_is_mips16 (pc))
4567 if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0)
4568 /* If error reading memory, guess that it is not a delayed branch. */
4570 return is_delayed ((unsigned long)
4571 extract_unsigned_integer (buf, MIPS_INSTLEN));
4574 /* Skip the PC past function prologue instructions (32-bit version).
4575 This is a helper function for mips_skip_prologue. */
4578 mips32_skip_prologue (CORE_ADDR pc)
4582 int seen_sp_adjust = 0;
4583 int load_immediate_bytes = 0;
4585 /* Find an upper bound on the prologue. */
4586 end_pc = skip_prologue_using_sal (pc);
4588 end_pc = pc + 100; /* Magic. */
4590 /* Skip the typical prologue instructions. These are the stack adjustment
4591 instruction and the instructions that save registers on the stack
4592 or in the gcc frame. */
4593 for (; pc < end_pc; pc += MIPS_INSTLEN)
4595 unsigned long high_word;
4597 inst = mips_fetch_instruction (pc);
4598 high_word = (inst >> 16) & 0xffff;
4600 if (high_word == 0x27bd /* addiu $sp,$sp,offset */
4601 || high_word == 0x67bd) /* daddiu $sp,$sp,offset */
4603 else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */
4604 inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
4606 else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4607 || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4608 && (inst & 0x001F0000)) /* reg != $zero */
4611 else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4613 else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000))
4615 continue; /* reg != $zero */
4617 /* move $s8,$sp. With different versions of gas this will be either
4618 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4619 Accept any one of these. */
4620 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
4623 else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4625 else if (high_word == 0x3c1c) /* lui $gp,n */
4627 else if (high_word == 0x279c) /* addiu $gp,$gp,n */
4629 else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */
4630 || inst == 0x033ce021) /* addu $gp,$t9,$gp */
4632 /* The following instructions load $at or $t0 with an immediate
4633 value in preparation for a stack adjustment via
4634 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4635 a local variable, so we accept them only before a stack adjustment
4636 instruction was seen. */
4637 else if (!seen_sp_adjust)
4639 if (high_word == 0x3c01 || /* lui $at,n */
4640 high_word == 0x3c08) /* lui $t0,n */
4642 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4645 else if (high_word == 0x3421 || /* ori $at,$at,n */
4646 high_word == 0x3508 || /* ori $t0,$t0,n */
4647 high_word == 0x3401 || /* ori $at,$zero,n */
4648 high_word == 0x3408) /* ori $t0,$zero,n */
4650 load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */
4660 /* In a frameless function, we might have incorrectly
4661 skipped some load immediate instructions. Undo the skipping
4662 if the load immediate was not followed by a stack adjustment. */
4663 if (load_immediate_bytes && !seen_sp_adjust)
4664 pc -= load_immediate_bytes;
4668 /* Skip the PC past function prologue instructions (16-bit version).
4669 This is a helper function for mips_skip_prologue. */
4672 mips16_skip_prologue (CORE_ADDR pc)
4675 int extend_bytes = 0;
4676 int prev_extend_bytes;
4678 /* Table of instructions likely to be found in a function prologue. */
4681 unsigned short inst;
4682 unsigned short mask;
4688 , /* addiu $sp,offset */
4691 , /* daddiu $sp,offset */
4694 , /* sw reg,n($sp) */
4697 , /* sd reg,n($sp) */
4700 , /* sw $ra,n($sp) */
4703 , /* sd $ra,n($sp) */
4709 , /* sw $a0-$a3,n($s1) */
4712 , /* move reg,$a0-$a3 */
4715 , /* entry pseudo-op */
4718 , /* addiu $s1,$sp,n */
4720 0, 0} /* end of table marker */
4723 /* Find an upper bound on the prologue. */
4724 end_pc = skip_prologue_using_sal (pc);
4726 end_pc = pc + 100; /* Magic. */
4728 /* Skip the typical prologue instructions. These are the stack adjustment
4729 instruction and the instructions that save registers on the stack
4730 or in the gcc frame. */
4731 for (; pc < end_pc; pc += MIPS16_INSTLEN)
4733 unsigned short inst;
4736 inst = mips_fetch_instruction (pc);
4738 /* Normally we ignore an extend instruction. However, if it is
4739 not followed by a valid prologue instruction, we must adjust
4740 the pc back over the extend so that it won't be considered
4741 part of the prologue. */
4742 if ((inst & 0xf800) == 0xf000) /* extend */
4744 extend_bytes = MIPS16_INSTLEN;
4747 prev_extend_bytes = extend_bytes;
4750 /* Check for other valid prologue instructions besides extend. */
4751 for (i = 0; table[i].mask != 0; i++)
4752 if ((inst & table[i].mask) == table[i].inst) /* found, get out */
4754 if (table[i].mask != 0) /* it was in table? */
4755 continue; /* ignore it */
4759 /* Return the current pc, adjusted backwards by 2 if
4760 the previous instruction was an extend. */
4761 return pc - prev_extend_bytes;
4767 /* To skip prologues, I use this predicate. Returns either PC itself
4768 if the code at PC does not look like a function prologue; otherwise
4769 returns an address that (if we're lucky) follows the prologue. If
4770 LENIENT, then we must skip everything which is involved in setting
4771 up the frame (it's OK to skip more, just so long as we don't skip
4772 anything which might clobber the registers which are being saved.
4773 We must skip more in the case where part of the prologue is in the
4774 delay slot of a non-prologue instruction). */
4777 mips_skip_prologue (CORE_ADDR pc)
4779 /* See if we can determine the end of the prologue via the symbol table.
4780 If so, then return either PC, or the PC after the prologue, whichever
4783 CORE_ADDR post_prologue_pc = after_prologue (pc, NULL);
4785 if (post_prologue_pc != 0)
4786 return max (pc, post_prologue_pc);
4788 /* Can't determine prologue from the symbol table, need to examine
4791 if (pc_is_mips16 (pc))
4792 return mips16_skip_prologue (pc);
4794 return mips32_skip_prologue (pc);
4797 /* Exported procedure: Is PC in the signal trampoline code */
4800 mips_pc_in_sigtramp (CORE_ADDR pc, char *ignore)
4802 if (sigtramp_address == 0)
4804 return (pc >= sigtramp_address && pc < sigtramp_end);
4807 /* Root of all "set mips "/"show mips " commands. This will eventually be
4808 used for all MIPS-specific commands. */
4811 show_mips_command (char *args, int from_tty)
4813 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
4817 set_mips_command (char *args, int from_tty)
4820 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4821 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
4824 /* Commands to show/set the MIPS FPU type. */
4827 show_mipsfpu_command (char *args, int from_tty)
4830 switch (MIPS_FPU_TYPE)
4832 case MIPS_FPU_SINGLE:
4833 fpu = "single-precision";
4835 case MIPS_FPU_DOUBLE:
4836 fpu = "double-precision";
4839 fpu = "absent (none)";
4842 internal_error (__FILE__, __LINE__, "bad switch");
4844 if (mips_fpu_type_auto)
4846 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4850 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
4855 set_mipsfpu_command (char *args, int from_tty)
4858 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4859 show_mipsfpu_command (args, from_tty);
4863 set_mipsfpu_single_command (char *args, int from_tty)
4865 struct gdbarch_info info;
4866 gdbarch_info_init (&info);
4867 mips_fpu_type = MIPS_FPU_SINGLE;
4868 mips_fpu_type_auto = 0;
4869 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4870 instead of relying on globals. Doing that would let generic code
4871 handle the search for this specific architecture. */
4872 if (!gdbarch_update_p (info))
4873 internal_error (__FILE__, __LINE__, "set mipsfpu failed");
4877 set_mipsfpu_double_command (char *args, int from_tty)
4879 struct gdbarch_info info;
4880 gdbarch_info_init (&info);
4881 mips_fpu_type = MIPS_FPU_DOUBLE;
4882 mips_fpu_type_auto = 0;
4883 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4884 instead of relying on globals. Doing that would let generic code
4885 handle the search for this specific architecture. */
4886 if (!gdbarch_update_p (info))
4887 internal_error (__FILE__, __LINE__, "set mipsfpu failed");
4891 set_mipsfpu_none_command (char *args, int from_tty)
4893 struct gdbarch_info info;
4894 gdbarch_info_init (&info);
4895 mips_fpu_type = MIPS_FPU_NONE;
4896 mips_fpu_type_auto = 0;
4897 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4898 instead of relying on globals. Doing that would let generic code
4899 handle the search for this specific architecture. */
4900 if (!gdbarch_update_p (info))
4901 internal_error (__FILE__, __LINE__, "set mipsfpu failed");
4905 set_mipsfpu_auto_command (char *args, int from_tty)
4907 mips_fpu_type_auto = 1;
4910 /* Attempt to identify the particular processor model by reading the
4911 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4912 the relevant processor still exists (it dates back to '94) and
4913 secondly this is not the way to do this. The processor type should
4914 be set by forcing an architecture change. */
4917 deprecated_mips_set_processor_regs_hack (void)
4919 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4922 prid = read_register (PRID_REGNUM);
4924 if ((prid & ~0xf) == 0x700)
4925 tdep->mips_processor_reg_names = mips_r3041_reg_names;
4928 /* Just like reinit_frame_cache, but with the right arguments to be
4929 callable as an sfunc. */
4932 reinit_frame_cache_sfunc (char *args, int from_tty,
4933 struct cmd_list_element *c)
4935 reinit_frame_cache ();
4939 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
4941 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4942 mips_extra_func_info_t proc_desc;
4944 /* Search for the function containing this address. Set the low bit
4945 of the address when searching, in case we were given an even address
4946 that is the start of a 16-bit function. If we didn't do this,
4947 the search would fail because the symbol table says the function
4948 starts at an odd address, i.e. 1 byte past the given address. */
4949 memaddr = ADDR_BITS_REMOVE (memaddr);
4950 proc_desc = non_heuristic_proc_desc (make_mips16_addr (memaddr), NULL);
4952 /* Make an attempt to determine if this is a 16-bit function. If
4953 the procedure descriptor exists and the address therein is odd,
4954 it's definitely a 16-bit function. Otherwise, we have to just
4955 guess that if the address passed in is odd, it's 16-bits. */
4956 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4957 disassembler needs to be able to locally determine the ISA, and
4958 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4962 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
4963 info->mach = bfd_mach_mips16;
4967 if (pc_is_mips16 (memaddr))
4968 info->mach = bfd_mach_mips16;
4971 /* Round down the instruction address to the appropriate boundary. */
4972 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3);
4974 /* Set the disassembler options. */
4975 if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64)
4977 /* Set up the disassembler info, so that we get the right
4978 register names from libopcodes. */
4979 if (tdep->mips_abi == MIPS_ABI_N32)
4980 info->disassembler_options = "gpr-names=n32";
4982 info->disassembler_options = "gpr-names=64";
4983 info->flavour = bfd_target_elf_flavour;
4986 /* This string is not recognized explicitly by the disassembler,
4987 but it tells the disassembler to not try to guess the ABI from
4988 the bfd elf headers, such that, if the user overrides the ABI
4989 of a program linked as NewABI, the disassembly will follow the
4990 register naming conventions specified by the user. */
4991 info->disassembler_options = "gpr-names=32";
4993 /* Call the appropriate disassembler based on the target endian-ness. */
4994 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
4995 return print_insn_big_mips (memaddr, info);
4997 return print_insn_little_mips (memaddr, info);
5000 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5001 counter value to determine whether a 16- or 32-bit breakpoint should be
5002 used. It returns a pointer to a string of bytes that encode a breakpoint
5003 instruction, stores the length of the string to *lenptr, and adjusts pc
5004 (if necessary) to point to the actual memory location where the
5005 breakpoint should be inserted. */
5007 static const unsigned char *
5008 mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
5010 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
5012 if (pc_is_mips16 (*pcptr))
5014 static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 };
5015 *pcptr = unmake_mips16_addr (*pcptr);
5016 *lenptr = sizeof (mips16_big_breakpoint);
5017 return mips16_big_breakpoint;
5021 /* The IDT board uses an unusual breakpoint value, and
5022 sometimes gets confused when it sees the usual MIPS
5023 breakpoint instruction. */
5024 static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd };
5025 static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd };
5026 static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd };
5028 *lenptr = sizeof (big_breakpoint);
5030 if (strcmp (target_shortname, "mips") == 0)
5031 return idt_big_breakpoint;
5032 else if (strcmp (target_shortname, "ddb") == 0
5033 || strcmp (target_shortname, "pmon") == 0
5034 || strcmp (target_shortname, "lsi") == 0)
5035 return pmon_big_breakpoint;
5037 return big_breakpoint;
5042 if (pc_is_mips16 (*pcptr))
5044 static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 };
5045 *pcptr = unmake_mips16_addr (*pcptr);
5046 *lenptr = sizeof (mips16_little_breakpoint);
5047 return mips16_little_breakpoint;
5051 static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 };
5052 static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 };
5053 static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 };
5055 *lenptr = sizeof (little_breakpoint);
5057 if (strcmp (target_shortname, "mips") == 0)
5058 return idt_little_breakpoint;
5059 else if (strcmp (target_shortname, "ddb") == 0
5060 || strcmp (target_shortname, "pmon") == 0
5061 || strcmp (target_shortname, "lsi") == 0)
5062 return pmon_little_breakpoint;
5064 return little_breakpoint;
5069 /* If PC is in a mips16 call or return stub, return the address of the target
5070 PC, which is either the callee or the caller. There are several
5071 cases which must be handled:
5073 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5074 target PC is in $31 ($ra).
5075 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5076 and the target PC is in $2.
5077 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5078 before the jal instruction, this is effectively a call stub
5079 and the the target PC is in $2. Otherwise this is effectively
5080 a return stub and the target PC is in $18.
5082 See the source code for the stubs in gcc/config/mips/mips16.S for
5085 This function implements the SKIP_TRAMPOLINE_CODE macro.
5089 mips_skip_stub (CORE_ADDR pc)
5092 CORE_ADDR start_addr;
5094 /* Find the starting address and name of the function containing the PC. */
5095 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
5098 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5099 target PC is in $31 ($ra). */
5100 if (strcmp (name, "__mips16_ret_sf") == 0
5101 || strcmp (name, "__mips16_ret_df") == 0)
5102 return read_signed_register (RA_REGNUM);
5104 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5106 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5107 and the target PC is in $2. */
5108 if (name[19] >= '0' && name[19] <= '9')
5109 return read_signed_register (2);
5111 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5112 before the jal instruction, this is effectively a call stub
5113 and the the target PC is in $2. Otherwise this is effectively
5114 a return stub and the target PC is in $18. */
5115 else if (name[19] == 's' || name[19] == 'd')
5117 if (pc == start_addr)
5119 /* Check if the target of the stub is a compiler-generated
5120 stub. Such a stub for a function bar might have a name
5121 like __fn_stub_bar, and might look like this:
5126 la $1,bar (becomes a lui/addiu pair)
5128 So scan down to the lui/addi and extract the target
5129 address from those two instructions. */
5131 CORE_ADDR target_pc = read_signed_register (2);
5135 /* See if the name of the target function is __fn_stub_*. */
5136 if (find_pc_partial_function (target_pc, &name, NULL, NULL) ==
5139 if (strncmp (name, "__fn_stub_", 10) != 0
5140 && strcmp (name, "etext") != 0
5141 && strcmp (name, "_etext") != 0)
5144 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5145 The limit on the search is arbitrarily set to 20
5146 instructions. FIXME. */
5147 for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN)
5149 inst = mips_fetch_instruction (target_pc);
5150 if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */
5151 pc = (inst << 16) & 0xffff0000; /* high word */
5152 else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */
5153 return pc | (inst & 0xffff); /* low word */
5156 /* Couldn't find the lui/addui pair, so return stub address. */
5160 /* This is the 'return' part of a call stub. The return
5161 address is in $r18. */
5162 return read_signed_register (18);
5165 return 0; /* not a stub */
5169 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5170 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5173 mips_in_call_stub (CORE_ADDR pc, char *name)
5175 CORE_ADDR start_addr;
5177 /* Find the starting address of the function containing the PC. If the
5178 caller didn't give us a name, look it up at the same time. */
5179 if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) ==
5183 if (strncmp (name, "__mips16_call_stub_", 19) == 0)
5185 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5186 if (name[19] >= '0' && name[19] <= '9')
5188 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5189 before the jal instruction, this is effectively a call stub. */
5190 else if (name[19] == 's' || name[19] == 'd')
5191 return pc == start_addr;
5194 return 0; /* not a stub */
5198 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5199 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5202 mips_in_return_stub (CORE_ADDR pc, char *name)
5204 CORE_ADDR start_addr;
5206 /* Find the starting address of the function containing the PC. */
5207 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0)
5210 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5211 if (strcmp (name, "__mips16_ret_sf") == 0
5212 || strcmp (name, "__mips16_ret_df") == 0)
5215 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5216 i.e. after the jal instruction, this is effectively a return stub. */
5217 if (strncmp (name, "__mips16_call_stub_", 19) == 0
5218 && (name[19] == 's' || name[19] == 'd') && pc != start_addr)
5221 return 0; /* not a stub */
5225 /* Return non-zero if the PC is in a library helper function that should
5226 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5229 mips_ignore_helper (CORE_ADDR pc)
5233 /* Find the starting address and name of the function containing the PC. */
5234 if (find_pc_partial_function (pc, &name, NULL, NULL) == 0)
5237 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5238 that we want to ignore. */
5239 return (strcmp (name, "__mips16_ret_sf") == 0
5240 || strcmp (name, "__mips16_ret_df") == 0);
5244 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5245 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5248 mips_stab_reg_to_regnum (int num)
5251 if (num >= 0 && num < 32)
5253 else if (num >= 38 && num < 70)
5254 regnum = num + mips_regnum (current_gdbarch)->fp0 - 38;
5256 regnum = mips_regnum (current_gdbarch)->hi;
5258 regnum = mips_regnum (current_gdbarch)->lo;
5260 /* This will hopefully (eventually) provoke a warning. Should
5261 we be calling complaint() here? */
5262 return NUM_REGS + NUM_PSEUDO_REGS;
5263 return NUM_REGS + regnum;
5267 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5268 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5271 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num)
5274 if (num >= 0 && num < 32)
5276 else if (num >= 32 && num < 64)
5277 regnum = num + mips_regnum (current_gdbarch)->fp0 - 32;
5279 regnum = mips_regnum (current_gdbarch)->hi;
5281 regnum = mips_regnum (current_gdbarch)->lo;
5283 /* This will hopefully (eventually) provoke a warning. Should we
5284 be calling complaint() here? */
5285 return NUM_REGS + NUM_PSEUDO_REGS;
5286 return NUM_REGS + regnum;
5290 mips_register_sim_regno (int regnum)
5292 /* Only makes sense to supply raw registers. */
5293 gdb_assert (regnum >= 0 && regnum < NUM_REGS);
5294 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5295 decide if it is valid. Should instead define a standard sim/gdb
5296 register numbering scheme. */
5297 if (REGISTER_NAME (NUM_REGS + regnum) != NULL
5298 && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0')
5301 return LEGACY_SIM_REGNO_IGNORE;
5305 /* Convert an integer into an address. By first converting the value
5306 into a pointer and then extracting it signed, the address is
5307 guarenteed to be correctly sign extended. */
5310 mips_integer_to_address (struct type *type, void *buf)
5312 char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr));
5313 LONGEST val = unpack_long (type, buf);
5314 store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val);
5315 return extract_signed_integer (tmp,
5316 TYPE_LENGTH (builtin_type_void_data_ptr));
5320 mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
5322 enum mips_abi *abip = (enum mips_abi *) obj;
5323 const char *name = bfd_get_section_name (abfd, sect);
5325 if (*abip != MIPS_ABI_UNKNOWN)
5328 if (strncmp (name, ".mdebug.", 8) != 0)
5331 if (strcmp (name, ".mdebug.abi32") == 0)
5332 *abip = MIPS_ABI_O32;
5333 else if (strcmp (name, ".mdebug.abiN32") == 0)
5334 *abip = MIPS_ABI_N32;
5335 else if (strcmp (name, ".mdebug.abi64") == 0)
5336 *abip = MIPS_ABI_N64;
5337 else if (strcmp (name, ".mdebug.abiO64") == 0)
5338 *abip = MIPS_ABI_O64;
5339 else if (strcmp (name, ".mdebug.eabi32") == 0)
5340 *abip = MIPS_ABI_EABI32;
5341 else if (strcmp (name, ".mdebug.eabi64") == 0)
5342 *abip = MIPS_ABI_EABI64;
5344 warning ("unsupported ABI %s.", name + 8);
5347 static enum mips_abi
5348 global_mips_abi (void)
5352 for (i = 0; mips_abi_strings[i] != NULL; i++)
5353 if (mips_abi_strings[i] == mips_abi_string)
5354 return (enum mips_abi) i;
5356 internal_error (__FILE__, __LINE__, "unknown ABI string");
5359 static struct gdbarch *
5360 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5362 struct gdbarch *gdbarch;
5363 struct gdbarch_tdep *tdep;
5365 enum mips_abi mips_abi, found_abi, wanted_abi;
5367 enum mips_fpu_type fpu_type;
5369 /* First of all, extract the elf_flags, if available. */
5370 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
5371 elf_flags = elf_elfheader (info.abfd)->e_flags;
5372 else if (arches != NULL)
5373 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
5377 fprintf_unfiltered (gdb_stdlog,
5378 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
5380 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5381 switch ((elf_flags & EF_MIPS_ABI))
5383 case E_MIPS_ABI_O32:
5384 found_abi = MIPS_ABI_O32;
5386 case E_MIPS_ABI_O64:
5387 found_abi = MIPS_ABI_O64;
5389 case E_MIPS_ABI_EABI32:
5390 found_abi = MIPS_ABI_EABI32;
5392 case E_MIPS_ABI_EABI64:
5393 found_abi = MIPS_ABI_EABI64;
5396 if ((elf_flags & EF_MIPS_ABI2))
5397 found_abi = MIPS_ABI_N32;
5399 found_abi = MIPS_ABI_UNKNOWN;
5403 /* GCC creates a pseudo-section whose name describes the ABI. */
5404 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL)
5405 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi);
5407 /* If we have no usefu BFD information, use the ABI from the last
5408 MIPS architecture (if there is one). */
5409 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
5410 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
5412 /* Try the architecture for any hint of the correct ABI. */
5413 if (found_abi == MIPS_ABI_UNKNOWN
5414 && info.bfd_arch_info != NULL
5415 && info.bfd_arch_info->arch == bfd_arch_mips)
5417 switch (info.bfd_arch_info->mach)
5419 case bfd_mach_mips3900:
5420 found_abi = MIPS_ABI_EABI32;
5422 case bfd_mach_mips4100:
5423 case bfd_mach_mips5000:
5424 found_abi = MIPS_ABI_EABI64;
5426 case bfd_mach_mips8000:
5427 case bfd_mach_mips10000:
5428 /* On Irix, ELF64 executables use the N64 ABI. The
5429 pseudo-sections which describe the ABI aren't present
5430 on IRIX. (Even for executables created by gcc.) */
5431 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5432 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5433 found_abi = MIPS_ABI_N64;
5435 found_abi = MIPS_ABI_N32;
5440 /* Default 64-bit objects to N64 instead of O32. */
5441 if (found_abi == MIPS_ABI_UNKNOWN
5442 && info.abfd != NULL
5443 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour
5444 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5445 found_abi = MIPS_ABI_N64;
5448 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
5451 /* What has the user specified from the command line? */
5452 wanted_abi = global_mips_abi ();
5454 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
5457 /* Now that we have found what the ABI for this binary would be,
5458 check whether the user is overriding it. */
5459 if (wanted_abi != MIPS_ABI_UNKNOWN)
5460 mips_abi = wanted_abi;
5461 else if (found_abi != MIPS_ABI_UNKNOWN)
5462 mips_abi = found_abi;
5464 mips_abi = MIPS_ABI_O32;
5466 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
5469 /* Also used when doing an architecture lookup. */
5471 fprintf_unfiltered (gdb_stdlog,
5472 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5473 mips64_transfers_32bit_regs_p);
5475 /* Determine the MIPS FPU type. */
5476 if (!mips_fpu_type_auto)
5477 fpu_type = mips_fpu_type;
5478 else if (info.bfd_arch_info != NULL
5479 && info.bfd_arch_info->arch == bfd_arch_mips)
5480 switch (info.bfd_arch_info->mach)
5482 case bfd_mach_mips3900:
5483 case bfd_mach_mips4100:
5484 case bfd_mach_mips4111:
5485 fpu_type = MIPS_FPU_NONE;
5487 case bfd_mach_mips4650:
5488 fpu_type = MIPS_FPU_SINGLE;
5491 fpu_type = MIPS_FPU_DOUBLE;
5494 else if (arches != NULL)
5495 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type;
5497 fpu_type = MIPS_FPU_DOUBLE;
5499 fprintf_unfiltered (gdb_stdlog,
5500 "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
5502 /* try to find a pre-existing architecture */
5503 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5505 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5507 /* MIPS needs to be pedantic about which ABI the object is
5509 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
5511 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
5513 /* Need to be pedantic about which register virtual size is
5515 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
5516 != mips64_transfers_32bit_regs_p)
5518 /* Be pedantic about which FPU is selected. */
5519 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type)
5521 return arches->gdbarch;
5524 /* Need a new architecture. Fill in a target specific vector. */
5525 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
5526 gdbarch = gdbarch_alloc (&info, tdep);
5527 tdep->elf_flags = elf_flags;
5528 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
5529 tdep->found_abi = found_abi;
5530 tdep->mips_abi = mips_abi;
5531 tdep->mips_fpu_type = fpu_type;
5533 /* Initially set everything according to the default ABI/ISA. */
5534 set_gdbarch_short_bit (gdbarch, 16);
5535 set_gdbarch_int_bit (gdbarch, 32);
5536 set_gdbarch_float_bit (gdbarch, 32);
5537 set_gdbarch_double_bit (gdbarch, 64);
5538 set_gdbarch_long_double_bit (gdbarch, 64);
5539 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p);
5540 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read);
5541 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write);
5543 set_gdbarch_elf_make_msymbol_special (gdbarch,
5544 mips_elf_make_msymbol_special);
5546 /* Fill in the OS dependant register numbers and names. */
5548 const char **reg_names;
5549 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch,
5550 struct mips_regnum);
5551 if (info.osabi == GDB_OSABI_IRIX)
5556 regnum->badvaddr = 66;
5559 regnum->fp_control_status = 69;
5560 regnum->fp_implementation_revision = 70;
5562 reg_names = mips_irix_reg_names;
5566 regnum->lo = MIPS_EMBED_LO_REGNUM;
5567 regnum->hi = MIPS_EMBED_HI_REGNUM;
5568 regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
5569 regnum->cause = MIPS_EMBED_CAUSE_REGNUM;
5570 regnum->pc = MIPS_EMBED_PC_REGNUM;
5571 regnum->fp0 = MIPS_EMBED_FP0_REGNUM;
5572 regnum->fp_control_status = 70;
5573 regnum->fp_implementation_revision = 71;
5575 if (info.bfd_arch_info != NULL
5576 && info.bfd_arch_info->mach == bfd_mach_mips3900)
5577 reg_names = mips_tx39_reg_names;
5579 reg_names = mips_generic_reg_names;
5581 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5582 replaced by read_pc? */
5583 set_gdbarch_pc_regnum (gdbarch, regnum->pc);
5584 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0);
5585 set_gdbarch_num_regs (gdbarch, num_regs);
5586 set_gdbarch_num_pseudo_regs (gdbarch, num_regs);
5587 set_gdbarch_register_name (gdbarch, mips_register_name);
5588 tdep->mips_processor_reg_names = reg_names;
5589 tdep->regnum = regnum;
5595 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call);
5596 set_gdbarch_return_value (gdbarch, mips_o32_return_value);
5597 tdep->mips_default_saved_regsize = 4;
5598 tdep->mips_default_stack_argsize = 4;
5599 tdep->mips_fp_register_double = 0;
5600 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5601 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5602 tdep->default_mask_address_p = 0;
5603 set_gdbarch_long_bit (gdbarch, 32);
5604 set_gdbarch_ptr_bit (gdbarch, 32);
5605 set_gdbarch_long_long_bit (gdbarch, 64);
5608 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call);
5609 set_gdbarch_deprecated_store_return_value (gdbarch,
5610 mips_o64_store_return_value);
5611 set_gdbarch_deprecated_extract_return_value (gdbarch,
5612 mips_o64_extract_return_value);
5613 tdep->mips_default_saved_regsize = 8;
5614 tdep->mips_default_stack_argsize = 8;
5615 tdep->mips_fp_register_double = 1;
5616 tdep->mips_last_arg_regnum = A0_REGNUM + 4 - 1;
5617 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1;
5618 tdep->default_mask_address_p = 0;
5619 set_gdbarch_long_bit (gdbarch, 32);
5620 set_gdbarch_ptr_bit (gdbarch, 32);
5621 set_gdbarch_long_long_bit (gdbarch, 64);
5622 set_gdbarch_use_struct_convention (gdbarch,
5623 always_use_struct_convention);
5625 case MIPS_ABI_EABI32:
5626 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5627 set_gdbarch_deprecated_store_return_value (gdbarch,
5628 mips_eabi_store_return_value);
5629 set_gdbarch_deprecated_extract_return_value (gdbarch,
5630 mips_eabi_extract_return_value);
5631 tdep->mips_default_saved_regsize = 4;
5632 tdep->mips_default_stack_argsize = 4;
5633 tdep->mips_fp_register_double = 0;
5634 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5635 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5636 tdep->default_mask_address_p = 0;
5637 set_gdbarch_long_bit (gdbarch, 32);
5638 set_gdbarch_ptr_bit (gdbarch, 32);
5639 set_gdbarch_long_long_bit (gdbarch, 64);
5640 set_gdbarch_deprecated_reg_struct_has_addr
5641 (gdbarch, mips_eabi_reg_struct_has_addr);
5642 set_gdbarch_use_struct_convention (gdbarch,
5643 mips_eabi_use_struct_convention);
5645 case MIPS_ABI_EABI64:
5646 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call);
5647 set_gdbarch_deprecated_store_return_value (gdbarch,
5648 mips_eabi_store_return_value);
5649 set_gdbarch_deprecated_extract_return_value (gdbarch,
5650 mips_eabi_extract_return_value);
5651 tdep->mips_default_saved_regsize = 8;
5652 tdep->mips_default_stack_argsize = 8;
5653 tdep->mips_fp_register_double = 1;
5654 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5655 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5656 tdep->default_mask_address_p = 0;
5657 set_gdbarch_long_bit (gdbarch, 64);
5658 set_gdbarch_ptr_bit (gdbarch, 64);
5659 set_gdbarch_long_long_bit (gdbarch, 64);
5660 set_gdbarch_deprecated_reg_struct_has_addr
5661 (gdbarch, mips_eabi_reg_struct_has_addr);
5662 set_gdbarch_use_struct_convention (gdbarch,
5663 mips_eabi_use_struct_convention);
5666 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5667 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5668 tdep->mips_default_saved_regsize = 8;
5669 tdep->mips_default_stack_argsize = 8;
5670 tdep->mips_fp_register_double = 1;
5671 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5672 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5673 tdep->default_mask_address_p = 0;
5674 set_gdbarch_long_bit (gdbarch, 32);
5675 set_gdbarch_ptr_bit (gdbarch, 32);
5676 set_gdbarch_long_long_bit (gdbarch, 64);
5679 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call);
5680 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value);
5681 tdep->mips_default_saved_regsize = 8;
5682 tdep->mips_default_stack_argsize = 8;
5683 tdep->mips_fp_register_double = 1;
5684 tdep->mips_last_arg_regnum = A0_REGNUM + 8 - 1;
5685 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1;
5686 tdep->default_mask_address_p = 0;
5687 set_gdbarch_long_bit (gdbarch, 64);
5688 set_gdbarch_ptr_bit (gdbarch, 64);
5689 set_gdbarch_long_long_bit (gdbarch, 64);
5692 internal_error (__FILE__, __LINE__, "unknown ABI in switch");
5695 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5696 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5699 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5700 flag in object files because to do so would make it impossible to
5701 link with libraries compiled without "-gp32". This is
5702 unnecessarily restrictive.
5704 We could solve this problem by adding "-gp32" multilibs to gcc,
5705 but to set this flag before gcc is built with such multilibs will
5706 break too many systems.''
5708 But even more unhelpfully, the default linker output target for
5709 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5710 for 64-bit programs - you need to change the ABI to change this,
5711 and not all gcc targets support that currently. Therefore using
5712 this flag to detect 32-bit mode would do the wrong thing given
5713 the current gcc - it would make GDB treat these 64-bit programs
5714 as 32-bit programs by default. */
5716 set_gdbarch_read_pc (gdbarch, mips_read_pc);
5717 set_gdbarch_write_pc (gdbarch, mips_write_pc);
5718 set_gdbarch_read_sp (gdbarch, mips_read_sp);
5720 /* Add/remove bits from an address. The MIPS needs be careful to
5721 ensure that all 32 bit addresses are sign extended to 64 bits. */
5722 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove);
5724 /* Unwind the frame. */
5725 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc);
5726 frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer);
5727 set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id);
5728 frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer);
5730 /* Map debug register numbers onto internal register numbers. */
5731 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum);
5732 set_gdbarch_ecoff_reg_to_regnum (gdbarch,
5733 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5734 set_gdbarch_dwarf_reg_to_regnum (gdbarch,
5735 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5736 set_gdbarch_dwarf2_reg_to_regnum (gdbarch,
5737 mips_dwarf_dwarf2_ecoff_reg_to_regnum);
5738 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno);
5740 /* MIPS version of CALL_DUMMY */
5742 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5743 replaced by a command, and all targets will default to on stack
5744 (regardless of the stack's execute status). */
5745 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL);
5746 set_gdbarch_frame_align (gdbarch, mips_frame_align);
5748 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p);
5749 set_gdbarch_register_to_value (gdbarch, mips_register_to_value);
5750 set_gdbarch_value_to_register (gdbarch, mips_value_to_register);
5752 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
5753 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
5755 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
5757 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address);
5758 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer);
5759 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address);
5761 set_gdbarch_register_type (gdbarch, mips_register_type);
5763 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
5764 set_gdbarch_pc_in_sigtramp (gdbarch, mips_pc_in_sigtramp);
5766 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
5768 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5769 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5770 need to all be folded into the target vector. Since they are
5771 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5772 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5774 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
5776 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub);
5778 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5779 to support MIPS16. This is a bad thing. Make sure not to do it
5780 if we have an OS ABI that actually supports shared libraries, since
5781 shared library support is more important. If we have an OS someday
5782 that supports both shared libraries and MIPS16, we'll have to find
5783 a better place for these. */
5784 if (info.osabi == GDB_OSABI_UNKNOWN)
5786 set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub);
5787 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub);
5790 /* Hook in OS ABI-specific overrides, if they have been registered. */
5791 gdbarch_init_osabi (info, gdbarch);
5797 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
5799 struct gdbarch_info info;
5801 /* Force the architecture to update, and (if it's a MIPS architecture)
5802 mips_gdbarch_init will take care of the rest. */
5803 gdbarch_info_init (&info);
5804 gdbarch_update_p (info);
5807 /* Print out which MIPS ABI is in use. */
5810 show_mips_abi (char *ignore_args, int from_tty)
5812 if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips)
5814 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5817 enum mips_abi global_abi = global_mips_abi ();
5818 enum mips_abi actual_abi = mips_abi (current_gdbarch);
5819 const char *actual_abi_str = mips_abi_strings[actual_abi];
5821 if (global_abi == MIPS_ABI_UNKNOWN)
5823 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5825 else if (global_abi == actual_abi)
5827 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5831 /* Probably shouldn't happen... */
5833 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5834 actual_abi_str, mips_abi_strings[global_abi]);
5840 mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
5842 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
5846 int ef_mips_32bitmode;
5847 /* determine the ISA */
5848 switch (tdep->elf_flags & EF_MIPS_ARCH)
5866 /* determine the size of a pointer */
5867 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
5868 fprintf_unfiltered (file,
5869 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5871 fprintf_unfiltered (file,
5872 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5874 fprintf_unfiltered (file,
5875 "mips_dump_tdep: ef_mips_arch = %d\n",
5877 fprintf_unfiltered (file,
5878 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5879 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
5880 fprintf_unfiltered (file,
5881 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5882 mips_mask_address_p (tdep),
5883 tdep->default_mask_address_p);
5885 fprintf_unfiltered (file,
5886 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5887 FP_REGISTER_DOUBLE);
5888 fprintf_unfiltered (file,
5889 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5890 MIPS_DEFAULT_FPU_TYPE,
5891 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none"
5892 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5893 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5895 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI);
5896 fprintf_unfiltered (file,
5897 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5899 (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none"
5900 : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single"
5901 : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double"
5903 fprintf_unfiltered (file,
5904 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5905 FP_REGISTER_DOUBLE);
5906 fprintf_unfiltered (file,
5907 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5908 mips_stack_argsize (tdep));
5909 fprintf_unfiltered (file, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM);
5910 fprintf_unfiltered (file,
5911 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5912 XSTRING (ADDR_BITS_REMOVE (ADDR)));
5913 fprintf_unfiltered (file,
5914 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5915 XSTRING (ATTACH_DETACH));
5916 fprintf_unfiltered (file,
5917 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5918 XSTRING (DWARF_REG_TO_REGNUM (REGNUM)));
5919 fprintf_unfiltered (file,
5920 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5921 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM)));
5922 fprintf_unfiltered (file,
5923 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5924 FIRST_EMBED_REGNUM);
5925 fprintf_unfiltered (file,
5926 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
5927 XSTRING (IGNORE_HELPER_CALL (PC)));
5928 fprintf_unfiltered (file,
5929 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5930 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME)));
5931 fprintf_unfiltered (file,
5932 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
5933 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC, NAME)));
5934 fprintf_unfiltered (file,
5935 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5937 #ifdef MACHINE_CPROC_FP_OFFSET
5938 fprintf_unfiltered (file,
5939 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5940 MACHINE_CPROC_FP_OFFSET);
5942 #ifdef MACHINE_CPROC_PC_OFFSET
5943 fprintf_unfiltered (file,
5944 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5945 MACHINE_CPROC_PC_OFFSET);
5947 #ifdef MACHINE_CPROC_SP_OFFSET
5948 fprintf_unfiltered (file,
5949 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5950 MACHINE_CPROC_SP_OFFSET);
5952 fprintf_unfiltered (file,
5953 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
5955 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5956 fprintf_unfiltered (file,
5957 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5958 fprintf_unfiltered (file,
5959 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN);
5960 fprintf_unfiltered (file,
5961 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5962 MIPS_LAST_ARG_REGNUM,
5963 MIPS_LAST_ARG_REGNUM - A0_REGNUM + 1);
5964 fprintf_unfiltered (file,
5965 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS);
5966 fprintf_unfiltered (file,
5967 "mips_dump_tdep: mips_saved_regsize() = %d\n",
5968 mips_saved_regsize (tdep));
5969 fprintf_unfiltered (file,
5970 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM);
5971 fprintf_unfiltered (file,
5972 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
5973 fprintf_unfiltered (file,
5974 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5975 fprintf_unfiltered (file,
5976 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5977 fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5978 fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5979 fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5980 fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5981 fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5982 fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n");
5983 fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n");
5984 fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5985 fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n");
5986 fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM);
5987 fprintf_unfiltered (file, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM);
5989 fprintf_unfiltered (file,
5990 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES);
5993 fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP);
5996 fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC);
5998 fprintf_unfiltered (file,
5999 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6000 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS)));
6001 fprintf_unfiltered (file,
6002 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6003 fprintf_unfiltered (file,
6004 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6005 XSTRING (SKIP_TRAMPOLINE_CODE (PC)));
6006 fprintf_unfiltered (file,
6007 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6008 XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P)));
6009 fprintf_unfiltered (file,
6010 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6011 SOFTWARE_SINGLE_STEP_P ());
6012 fprintf_unfiltered (file,
6013 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6014 XSTRING (STAB_REG_TO_REGNUM (REGNUM)));
6015 #ifdef STACK_END_ADDR
6016 fprintf_unfiltered (file,
6017 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6020 fprintf_unfiltered (file,
6021 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6022 XSTRING (STEP_SKIPS_DELAY (PC)));
6023 fprintf_unfiltered (file,
6024 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6025 STEP_SKIPS_DELAY_P);
6026 fprintf_unfiltered (file,
6027 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6028 XSTRING (STOPPED_BY_WATCHPOINT (WS)));
6029 fprintf_unfiltered (file, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM);
6030 fprintf_unfiltered (file,
6031 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6032 fprintf_unfiltered (file,
6033 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6034 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6035 (TYPE, CNT, OTHERTYPE)));
6036 fprintf_unfiltered (file,
6037 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6038 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS));
6040 fprintf_unfiltered (file,
6041 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6042 XSTRING (TRACE_CLEAR (THREAD, STATE)));
6045 fprintf_unfiltered (file,
6046 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR);
6048 #ifdef TRACE_FLAVOR_SIZE
6049 fprintf_unfiltered (file,
6050 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6054 fprintf_unfiltered (file,
6055 "mips_dump_tdep: TRACE_SET # %s\n",
6056 XSTRING (TRACE_SET (X, STATE)));
6058 #ifdef UNUSED_REGNUM
6059 fprintf_unfiltered (file,
6060 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM);
6062 fprintf_unfiltered (file, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM);
6063 fprintf_unfiltered (file,
6064 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6065 (long) VM_MIN_ADDRESS);
6066 fprintf_unfiltered (file,
6067 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM);
6068 fprintf_unfiltered (file,
6069 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_);
6072 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */
6075 _initialize_mips_tdep (void)
6077 static struct cmd_list_element *mipsfpulist = NULL;
6078 struct cmd_list_element *c;
6080 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
6081 if (MIPS_ABI_LAST + 1
6082 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
6083 internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync");
6085 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
6087 mips_pdr_data = register_objfile_data ();
6089 /* Add root prefix command for all "set mips"/"show mips" commands */
6090 add_prefix_cmd ("mips", no_class, set_mips_command,
6091 "Various MIPS specific commands.",
6092 &setmipscmdlist, "set mips ", 0, &setlist);
6094 add_prefix_cmd ("mips", no_class, show_mips_command,
6095 "Various MIPS specific commands.",
6096 &showmipscmdlist, "show mips ", 0, &showlist);
6098 /* Allow the user to override the saved register size. */
6099 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6102 &mips_saved_regsize_string, "\
6103 Set size of general purpose registers saved on the stack.\n\
6104 This option can be set to one of:\n\
6105 32 - Force GDB to treat saved GP registers as 32-bit\n\
6106 64 - Force GDB to treat saved GP registers as 64-bit\n\
6107 auto - Allow GDB to use the target's default setting or autodetect the\n\
6108 saved GP register size from information contained in the executable.\n\
6109 (default: auto)", &setmipscmdlist), &showmipscmdlist);
6111 /* Allow the user to override the argument stack size. */
6112 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6115 &mips_stack_argsize_string, "\
6116 Set the amount of stack space reserved for each argument.\n\
6117 This option can be set to one of:\n\
6118 32 - Force GDB to allocate 32-bit chunks per argument\n\
6119 64 - Force GDB to allocate 64-bit chunks per argument\n\
6120 auto - Allow GDB to determine the correct setting from the current\n\
6121 target and executable (default)", &setmipscmdlist), &showmipscmdlist);
6123 /* Allow the user to override the ABI. */
6124 c = add_set_enum_cmd
6125 ("abi", class_obscure, mips_abi_strings, &mips_abi_string,
6126 "Set the ABI used by this program.\n"
6127 "This option can be set to one of:\n"
6128 " auto - the default ABI associated with the current binary\n"
6130 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist);
6131 set_cmd_sfunc (c, mips_abi_update);
6132 add_cmd ("abi", class_obscure, show_mips_abi,
6133 "Show ABI in use by MIPS target", &showmipscmdlist);
6135 /* Let the user turn off floating point and set the fence post for
6136 heuristic_proc_start. */
6138 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
6139 "Set use of MIPS floating-point coprocessor.",
6140 &mipsfpulist, "set mipsfpu ", 0, &setlist);
6141 add_cmd ("single", class_support, set_mipsfpu_single_command,
6142 "Select single-precision MIPS floating-point coprocessor.",
6144 add_cmd ("double", class_support, set_mipsfpu_double_command,
6145 "Select double-precision MIPS floating-point coprocessor.",
6147 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
6148 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
6149 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
6150 add_cmd ("none", class_support, set_mipsfpu_none_command,
6151 "Select no MIPS floating-point coprocessor.", &mipsfpulist);
6152 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
6153 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
6154 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
6155 add_cmd ("auto", class_support, set_mipsfpu_auto_command,
6156 "Select MIPS floating-point coprocessor automatically.",
6158 add_cmd ("mipsfpu", class_support, show_mipsfpu_command,
6159 "Show current use of MIPS floating-point coprocessor target.",
6162 /* We really would like to have both "0" and "unlimited" work, but
6163 command.c doesn't deal with that. So make it a var_zinteger
6164 because the user can always use "999999" or some such for unlimited. */
6165 c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger,
6166 (char *) &heuristic_fence_post, "\
6167 Set the distance searched for the start of a function.\n\
6168 If you are debugging a stripped executable, GDB needs to search through the\n\
6169 program for the start of a function. This command sets the distance of the\n\
6170 search. The only need to set it is when debugging a stripped executable.", &setlist);
6171 /* We need to throw away the frame cache when we set this, since it
6172 might change our ability to get backtraces. */
6173 set_cmd_sfunc (c, reinit_frame_cache_sfunc);
6174 add_show_from_set (c, &showlist);
6176 /* Allow the user to control whether the upper bits of 64-bit
6177 addresses should be zeroed. */
6178 add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\
6179 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6180 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6181 allow GDB to determine the correct value.\n", "\
6182 Show zeroing of upper 32 bits of 64-bit addresses.",
6183 NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist);
6185 /* Allow the user to control the size of 32 bit registers within the
6186 raw remote packet. */
6187 add_setshow_cmd ("remote-mips64-transfers-32bit-regs", class_obscure,
6188 var_boolean, &mips64_transfers_32bit_regs_p, "\
6189 Set compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6190 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6191 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6192 64 bits for others. Use \"off\" to disable compatibility mode", "\
6193 Show compatibility with 64-bit MIPS targets that transfer 32-bit quantities.\n\
6194 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6195 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6196 64 bits for others. Use \"off\" to disable compatibility mode", set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist);
6198 /* Debug this files internals. */
6199 add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
6200 &mips_debug, "Set mips debugging.\n\
6201 When non-zero, mips specific debugging is enabled.", &setdebuglist), &showdebuglist);